UPD78053YGC-XXX-8BT [RENESAS]
8-BIT, MROM, 5MHz, MICROCONTROLLER, PQFP80, 14 X 14 MM, PLASTIC, LQFP-80;
| 型号： | UPD78053YGC-XXX-8BT |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | 8-BIT, MROM, 5MHz, MICROCONTROLLER, PQFP80, 14 X 14 MM, PLASTIC, LQFP-80 时钟 外围集成电路 |
| 文件： | 总76页 (文件大小：572K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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April 1st, 2010
Renesas Electronics Corporation
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DATA SHEET
MOS INTEGRATED CIRCUIT
µPD78052Y, 78053Y, 78054Y, 78055Y, 78056Y, 78058Y
8-BIT SINGLE-CHIP MICROCONTROLLER
DESCRIPTION
The µPD78052Y, 78053Y, 78054Y, 78055Y, 78056Y, and 78058Y versions add the I2C bus control function to
the µPD78052, 78053, 78054, 78055, 78056, and 78058, and are suitable for application in AV products.
Various peripheral hardware such as 8-bit resolution D/A converter, timer, serial interface, real-time output port
and interrupt functions are incorporated.
The 78P058Y, a one-time PROM or EPROM version which can be operated in the same supply voltage as for
the mask ROM version, and various development tools are also available.
Detailed function descriptions, etc., are provided in the following User's Manual. Be sure to read it when
designing.
µPD78054, 78054Y Subseries User’s Manual : U11747E
78K/0 Series User’s Manual Instructions
: U12326E
FEATURES
•
•
Internal high-capacity ROM and RAM
External memory expansion space : 64 Kbytes
Item Program memory
Data memory
Internal High-Speed RAM Internal Buffer RAM
Part number
µPD78052Y
(ROM)
Internal Expanded RAM
No
16 Kbytes
24 Kbytes
32 Kbytes
40 Kbytes
48 Kbytes
60 Kbytes
512 bytes
32 bytes
µPD78053Y
µPD78054Y
µPD78055Y
µPD78056Y
µPD78058Y
1024 bytes
1024 bytes
•
•
•
•
•
•
•
Minimum instruction execution time can be varied from high-speed (0.4 µs) to ultra-low-speed (122 µs)
I/O ports : 69 (N-ch open-drain : 4)
8-bit resolution A/D converter: 8 channels
8-bit resolution D/A converter: 2 channels
Serial interface : 3 channels (I2C bus mode : 1 channel)
Timer : 5 channels
Supply voltage : VDD = 2.0 to 6.0 V
APPLICATIONS
Cellular phones, pagers, printers, AV equipment, airconditioners, cameras, PPC, fuzzy home applicances,
vending machines, etc.
The information in this document is subject to change without notice.
Document No. U10906EJ2V0DS00 (2nd edition)
Date Published September 1997 N
Printed in Japan
The mark
shows major revised points.
1993
©
µPD78052Y, 78053Y, 78054Y, 78055Y, 78056Y, 78058Y
ORDERING INFORMATION
Part Number
Package
µPD78052YGC-xxx-8BT
µPD78053YGC-xxx-8BT
µPD78054YGC-xxx-8BT
µPD78055YGC-xxx-8BT
µPD78056YGC-xxx-8BT
µPD78058YGC-xxx-8BT
80-pin plastic QFP (14 x 14 mm)
80-pin plastic QFP (14 x 14 mm)
80-pin plastic QFP (14 x 14 mm)
80-pin plastic QFP (14 x 14 mm)
80-pin plastic QFP (14 x 14 mm)
80-pin plastic QFP (14 x 14 mm)
Remark xxx indicates the ROM code suffix.
2
µPD78052Y, 78053Y, 78054Y, 78055Y, 78056Y, 78058Y
78K/0 SERIES DEVELOPMENT
The following shows the 78K/0 Series products development. Subseries names are shown inside frames.
Under mass production
Under development
Y subseries provide I2C bus interface function
Controller
EMI noise reduced version of the
Added a timer and enhanced external interface to the
ROM-less versions of the PD78078
µ
PD78078
100-pin
100-pin
100-pin
100-pin
80-pin
µ
PD78075B
µ
µ
µ
µ
PD78075BY
PD78078Y
PD78070AY
µ
PD78078
µPD78054 Subseries
µ
PD78070A
µ
PD780018AY
Enhanced serial I/O of the
Enhanced serial I/O of the
µ
µ
PD78078Y with limited number of functions
PD78054, EMI noise reduced version
Note
µ
PD780058
PD78058F
PD78054
µ
µ
PD780058Y
PD78058FY
µ
EMI noise reduced version of the
Added UART, and D/A to the PD78014 and enhanced I/O ports
Enhanced A/D of the PD780024
Enhanced serial I/O of the PD78018F, EMI noise reduced version
EMI noise reduced version of the PD78018F
µ
PD78054
80-pin
80-pin
µ
µ
µ
PD78054Y
PD780034Y
PD780024Y
64-pin
64-pin
64-pin
64-pin
64-pin
64-pin
64-pin
42/44-pin
µ
µ
µ
µ
µ
PD780034
PD780024
PD78014H
PD78018F
µ
µ
µ
µ
Low voltage (1.8 V) operation version of the
enhanced ROM and RAM variation
µ
PD78014,
µ
PD78018FY
µ
PD78014
PD780001
PD78002
PD78083
µ
PD78014Y
Added an A/D and 16-bit timer/event to the PD78002
µ
µ
Added A/D to the
Basic subseries for controller
On-chip UART, operatable at a low-voltage (1.8 V)
µPD78002
µ
µ
µ
PD78002Y
Inverter controller
Enhanced the inverter control, timer, and SIO of the PD78064. Expanded ROM and RAM.
µ
64-pin
64-pin
64-pin
µ
PD780988
µ
PD780964
µPD780924
Enhanced A/D of the
µ
PD780924
On-chip inverter control circuit and UART, EMI noise reduced version
FIP driver
µ
Enhanced I/O ports, FIP controller/driver of the PD78044F,
100-pin
100-pin
80-pin
80-pin
µ
PD780208
PD780228
Total display outputs: 53
78K/0
Series
Enhanced I/O ports, FIP controller/driver of the
Total display outputs: 48
µ
PD78044H,
µ
Added an N-ch open-drain input/output to the
Total display outputs: 34
µPD78044F,
µ
µ
PD78044H
PD78044F
Basic subseries for FIP drive,
Total display outputs: 34
LCD driver
PD780308
100-pin
100-pin
100-pin
µ
µ
PD780308Y
Enhanced SIO to the
EMI noise reduced version of the
Basic subseries for LCD driving, on-chip UART
µ
PD78064 and expanded ROM and RAM
µ
PD78064B
PD78064
µ
PD78064
µ
µPD78064Y
IEBus supported
PD78098B
80-pin
80-pin
µ
µ
EMI noise reduced version of the PD78098
µ
PD78098
Added an IEBus controller to the PD78054
µ
Meter controller
PD780973
80-pin
64-pin
µ
Automobile meter drive controller/driver incorporated
LV
PD78P0914
µ
Incorporated PWM output, LV digital code decorder, and Hsync counter
Note Under planning
3
µPD78052Y, 78053Y, 78054Y, 78055Y, 78056Y, 78058Y
The major functional differences among the subseries are shown below.
Function
ROM
VDD MIN.
Value
Serial Interface
I/O
88
Subseries Name
Capacity
Control
µPD78075BY 32 K to 40 K 3-wire/2-wire/I2C
: 1 ch
: 1 ch
: 1 ch
1.8 V
With automatic transmit/receive function, 3-wire
3-wire/UART
µPD78078Y
48 K to 60 K
–
µPD78070AY
61
88
2.7 V
µPD780018AY 48 K to 60 K With automatic transmit/receive function, 3-wire
Time division 3-wire
: 1 ch
: 1 ch
: 1 ch
I2C bus (multi master supported)
µPD780058Y 24 K to 60 K 3-wire/2-wire/I2C
With automatic transmit/receive function, 3-wire
3-wire/Time division UART
: 1 ch
: 1 ch
: 1 ch
68
69
51
53
1.8 V
µPD78058FY 48 K to 60 K 3-wire/2-wire/I2C
: 1 ch
: 1 ch
: 1 ch
2.7 V
2.0 V
1.8 V
With automatic transmit/receive function, 3-wire
µPD78054Y
16 K to 60 K
3-wire/UART
µPD780034Y 8 K to 32 K
µPD780024Y
UART
: 1 ch
: 1 ch
: 1 ch
3-wire
I2C bus (multi master supported)
µPD78018FY 8 K to 60 K
3-wire/2-wire/I2C
: 1 ch
: 1 ch
With automatic transmit/receive function, 3-wire
µPD78014Y
µPD78002Y
8 K to 32 K
8 K to 16 K
3-wire/2-wire/SBI/I2C
: 1 ch
: 1 ch
2.7 V
2.0 V
With automatic transmit/receive function, 3-wire
3-wire/2-wire/SBI/I2C
: 1 ch
LCD
µPD780308Y 48 K to 60 K 3-wire/2-wire/I2C
3-wire/Time division UART
: 1 ch
: 1 ch
: 1 ch
57
driver
3-wire
µPD78064Y
16 K to 32 K 3-wire/2-wire/I2C
3-wire/UART
: 1 ch
: 1 ch
Remark The functions other than the serial interface are the same as those of Subseries products without the suffix Y.
4
µPD78052Y, 78053Y, 78054Y, 78055Y, 78056Y, 78058Y
OVERVIEW OF FUNCTION
Product Name
Item
µPD78052Y µPD78053Y µPD78054Y µPD78055Y µPD78056Y µPD78058Y
Internal
Memory
ROM
16 Kbytes
512 bytes
24 Kbytes
32 Kbytes
40 Kbytes
1024 bytes
48 Kbytes
60 Kbytes
High-speed RAM
Buffer RAM
Expanded RAM
32 bytes
None
1024 bytes
Memory space
64 Kbytes
General registers
8 bits × 32 registers (8 bits × 8 registers × 4 banks)
On-chip minimum instruction execution time cycle modification function
Minimum instruction execution time
When main system clock selected 0.4 µs/0.8 µs/1.6 µs/3.2 µs/6.4 µs/12.8 µs (@ 5.0-MHz operation)
When subsystem clock selected
Instruction set
122 µs (@ 32.768-kHz operation)
• 16-bit operation
• Multiplication/division (8 bits × 8 bits,16 bits ÷ 8 bits)
• Bit manipulation (set, reset, test, boolean operation)
• BCD adjustment, etc.
I/O ports
Total
:
:
:
:
69
02
63
4
• CMOS input
• CMOS I/O
• N-ch open-drain I/O
A/D converter
D/A converter
Serial interface
• 8-bit resolution × 8 channels
• 8-bit resolution × 2 channels
• 3-wire serial I/O/2-wire serial I/O mode/I2C bus mode selectable: 1 channel
•
3-wire serial I/O mode (on-chip max. 32-byte automatic data transmit/receive
function): 1 channel
• 3-wire serial I/O/UART mode selectable : 1 channel
Timer
• 16-bit timer/event counter : 1 channel
• 8-bit timer/event counter : 2 channels
• Watch timer
: 1 channel
: 1 channel
• Watchdog timer
Timer output
Clock output
3 (14-bit PWM output × 1)
19.5 kHz, 39.1 kHz, 78.1 kHz, 156 kHz, 313 kHz, 625 kHz, 1.25 MHz, 2.5 MHz, 5.0 MHz
(@ 5.0-MHz operation with main system clock)
32.768 kHz (@ 32.768-kHz operation with subsystem clock)
Buzzer output
1.2 kHz, 2.4 kHz, 4.9 kHz, 9.8 kHz (@ 5.0-MHz operation with main system clock)
Vectored
interrupt
sources
Maskable
Internal interrupt : 13, external interrupt : 7
Internal interrupt : 1
Non-maskable
Software
1
Test input
Internal : 1, external : 1
VDD = 2.0 to 6.0 V
Supply voltage
Operating ambient temperature
Package
TA = –40 to +85°C
• 80-pin plastic QFP (14 × 14 mm)
5
µPD78052Y, 78053Y, 78054Y, 78055Y, 78056Y, 78058Y
CONTENTS
1. PIN CONFIGURATION (TOP VIEW) ..............................................................................................................
2. BLOCK DIAGRAM .........................................................................................................................................
7
9
3
PIN FUNCTIONS .......................................................................................................................................... 10
3.1 Port Pins.............................................................................................................................................. 10
3.2 Non-port Pins ....................................................................................................................................... 12
3.3 Pin I/O Circuits and Recommended Connection of Unused Pins ................................................ 14
4. MEMORY SPACE ............................................................................................................................................ 18
5. PERIPHERAL HARDWARE FUNCTION FEATURES .................................................................................. 19
5.1 Ports....................................................................................................................................................... 19
5.2 Clock Generator ................................................................................................................................... 20
5.3 Timer/Event Counter............................................................................................................................ 20
5.4 Clock Output Control Circuit.............................................................................................................. 23
5.5 Buzzer Output Control Circuit ........................................................................................................... 23
5.6 A/D Converter ....................................................................................................................................... 24
5.7 D/A Converter ....................................................................................................................................... 25
5.8 Serial Interfaces ................................................................................................................................... 25
5.9 Real-Time Output Port Functions ...................................................................................................... 27
6. INTERRUPT FUNCTIONS AND TEST FUNCTIONS .................................................................................... 28
6.1 Interrupt Functions ............................................................................................................................ 28
6.2 Test Functions...................................................................................................................................... 32
7. EXTERNAL DEVICE EXPANSION FUNCTIONS .......................................................................................... 33
8. STANDBY FUNCTION .................................................................................................................................... 33
9. RESET FUNCTION .......................................................................................................................................... 33
10. INSTRUCTION SET ......................................................................................................................................... 34
11. ELECTRICAL SPECIFICATIONS ................................................................................................................... 37
12. CHARACTERISTIC CURVES (REFERENCE VALUE) ................................................................................. 64
13. PACKAGE DRAWING ..................................................................................................................................... 66
14. RECOMMENDED SOLDERING CONDITIONS ............................................................................................. 67
APPENDIX A. DEVELOPMENT TOOLS ............................................................................................................ 68
APPENDIX B. RELATED DOCUMENTS........................................................................................................... 70
6
µPD78052Y, 78053Y, 78054Y, 78055Y, 78056Y, 78058Y
1. PIN CONFIGURATION (TOP VIEW)
• 80-pin plastic QFP (14 × 14 mm)
µPD78052YGC-xxx-8BT
µPD78053YGC-xxx-8BT
µPD78054YGC-xxx-8BT
µPD78055YGC-xxx-8BT
µPD78056YGC-xxx-8BT
µPD78058YGC-xxx-8BT
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
P15/ANI5
P16/ANI6
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
RESET
1
2
P127/RTP7
P126/RTP6
P125/RTP5
P124/RTP4
P123/RTP3
P122/RTP2
P121/RTP1
P120/RTP0
P37
P17/ANI7
3
AVSS
4
P130/ANO0
P131/ANO1
AVREF1
5
6
7
P70/SI2/RxD
P71/SO2/TxD
P72/SCK2/ASCK
P20/SI1
8
9
10
11
12
13
14
15
16
17
18
19
20
P36/BUZ
P35/PCL
P34/TI2
P21/SO1
P22/SCK1
P23/STB
P33/TI1
P24/BUSY
P32/TO2
P31/TO1
P30/TO0
P67/ASTB
P66/WAIT
P65/WR
P25/SI0/SB0/SDA0
P26/SO0/SB1/SDA1
P27/SCK0/SCL
P40/AD0
P41/AD1
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
Cautions 1. IC (Internally Connected) pin should be connected directly to VSS.
2. AVDD pin should be connected to VDD pin.
3. AVSS pin should be connected to VSS pin.
7
µPD78052Y, 78053Y, 78054Y, 78055Y, 78056Y, 78058Y
A8 to A15
AD0 to AD7
ANI0 to ANI7
ANO0, ANO1
ASCK
: Address Bus
PCL
: Programmable Clock
: Read Strobe
: Reset
: Address/Data Bus
: Analog Input
RD
RESET
: Analog Output
RTP0 to RTP7 : Real-Time Output Port
: Asynchronous Serial Clock
: Address Strobe
: Analog Power Supply
: Analog Reference Voltage
: Analog Ground
RXD
: Receive Data
: Serial Bus
ASTB
SB0, SB1
AVDD
SCK0 to SCK2 : Serial Clock
AVREF0, AVREF1
AVSS
SCL
: Serial Clock
: Serial Data
SDA0, SDA1
SI0 to SI2
SO0 to SO2
STB
BUSY
: Busy
: Serial Input
BUZ
: Buzzer Clock
: Serial Output
: Strobe
IC
: Internally Connected
INTP0 to INTP6 : Interrupt from Peripherals
TI00, TI01
TI1, TI2
TO0 to TO2
TXD
: Timer Input
P00 to P07
P10 to P17
P20 to P27
P30 to P37
P40 to P47
P50 to P57
P60 to P67
P70 to P72
P120 to P127
P130, P131
: Port0
: Port1
: Port2
: Port3
: Port4
: Port5
: Port6
: Port7
: Port12
: Port13
: Timer Input
: Timer Output
: Transmit Data
: Power Supply
: Ground
VDD
VSS
WAIT
: Wait
WR
: Write Strobe
: Crystal (Main System Clock)
: Crystal (Subsystem Clock)
X1, X2
XT1, XT2
8
µPD78052Y, 78053Y, 78054Y, 78055Y, 78056Y, 78058Y
2. BLOCK DIAGRAM
P00
TO0/P30
P01 to P06
P07
PORT0
PORT1
PORT2
PORT3
PORT4
PORT5
PORT6
PORT7
PORT12
PORT13
16-bit TIMER/
EVENT COUNTER
TI00/INTP0/P00
TI01/INTP1/P01
P10 to P17
P20 to P27
P30 to P37
P40 to P47
P50 to P57
P60 to P67
P70 to P72
P120 to P127
P130, P131
TO1/P31
TI1/P33
8-bit TIMER/
EVENT COUNTER 1
TO2/P32
TI2/P34
8-bit TIMER/
EVENT COUNTER 2
WATCHDOG TIMER
WATCH TIMER
SI0/SB0/SDA0/P25
SO0/SB1/SDA1/P26
SCK0/SCL/P27
SERIAL
INTERFACE 0
78K/0
CPU CORE
ROM
SI1/P20
SO1/P21
SCK1/P22
STB/P23
SERIAL
INTERFACE 1
BUSY/P24
SI2/RxD/P70
SO2/TxD/P71
SERIAL
INTERFACE 2
SCK2/ASCK/P72
RAM
ANI0/P10 to
ANI7/P17
RTP0/P120 to
RTP7/P127
REAL-TIME
OUTPUT PORT
A/D CONVERTER
D/A CONVERTER
AVDD
AVSS
AVREF0
AD0/P40-
AD7/P47
ANO0/P130,
ANO1/P131
A8/P50 to
A15/P57
EXTERNAL
ACCESS
AVSS
RD/P64
AVREF1
WR/P65
WAIT/P66
ASTB/P67
INTP0/P00 to
INTP6/P06
INTERRUPT
CONTROL
RESET
X1
BUZ/P36
PCL/P35
BUZZER OUTPUT
SYSTEM
CONTROL
X2
XT1/P07
XT2
CLOCK OUTPUT
CONTROL
VDD
VSS
IC
Remark The internal ROM and RAM capacity depends on the product.
9
µPD78052Y, 78053Y, 78054Y, 78055Y, 78056Y, 78058Y
3. PIN FUNCTIONS
3.1 Port Pins (1/2)
After
Alternate
Function
Pin Name
I/O
Input
Function
Reset
P00
P01
Port 0
Input only
Input
Input
INTP0/TI00
INTP1/TI01
INTP2
8-bit I/O port
Input/
Input/output can be specified bit-wise.
When used as an input port, on-chip pull-up resistor
can be used by software.
output
P02
P03
INTP3
P04
INTP4
P05
INTP5
P06
INTP6
P07Note 1
P10 to P17
Input
Input only
Input
Input
XT1
Input/
Port 1
ANI0 to ANI7
output
8-bit input/output port.
Input/output can be specified bit-wise.
When used as an input port, on-chip pull-up resistor can be used by
software.Note 2
P20
P21
Input/
Port 2
Input
Input
Input
SI1
SO1
output
8-bit input/output port.
Input/output can be specified bit-wise.
When used as an input port, on-chip pull-up resistor can be used by
software.
P22
SCK1
P23
STB
P24
BUSY
SI0/SB0/SDA0
SO0/SB1/SDA1
SCK0/SCL
TO0
P25
P26
P27
P30
Input/
Port 3
output
8-bit input/output port.
P31
TO1
Input/output can be specified bit-wise.
When used as an input port, on-chip pull-up resistor can be used by
software.
P32
TO2
P33
TI1
P34
TI2
P35
PCL
P36
BUZ
P37
—
P40 to P47
Input/
Port 4
AD0 to AD7
output
8-bit input/output port.
Input/output can be specified in 8-bit unit.
When used as an input port, on-chip pull-up resistor can be used by
software. Test input flag (KRIF) is set to 1 by falling edge detection.
Notes 1. When using the P07/XT1 pins as an input port, set 1 in bit 6 (FRC) of the processor clock control register
(PCC). On-chip feedback resistor of the subsystem clock oscillator should not be used.
2. When using the P10/ANI0 to P17/ANI7 pins as the A/D converter analog input pins, set port 1 to the input
mode. The pull-up resistor is disabled automatically.
10
µPD78052Y, 78053Y, 78054Y, 78055Y, 78056Y, 78058Y
3.1 Port Pins (2/2)
After
Alternate
Function
Pin Name
I/O
Function
Reset
P50 to P57
Input/
Port 5
Input
A8 to A15
output
8-bit input/output port.
LED can be driven directly.
Input/output can be specified bit-wise.
When used as an input port, on-chip pull-up resistor can be used by
software.
P60
P61
P62
P63
P64
P65
P66
P67
P70
Input/
Port 6
N-ch open-drain input/output port.
On-chip pull-up resistor can be
specified by mask option.
Input
Input
Input
—
output
8-bit input/outport port.
Input/output can be specified
bit-wise.
LED can be driven directly.
When used as an input port,
on-chip pull-up resistor can be used
by software.
RD
WR
WAIT
ASTB
SI2/RxD
Port 7
Input/
3-bit input/output port.
output
P71
P72
SO2/TxD
SCK2/ASCK
RTP0 to RTP7
Input/output can be specified bit-wise.
When used as an input port, on-chip pull-up resistor can be used by software.
P120 to P127 Input/
output
Port 12
Input
Input
8-bit input/output port.
Input/output can be specified bit-wise.
When used as an input port, on-chip pull-up resistor can be used by software.
P130, P131 Input/
output
Port 13
ANO0, ANO1
2-bit input/output port.
Input/output can be specified bit-wise.
When used as an input port, on-chip pull-up resistor can be used by software.
11
µPD78052Y, 78053Y, 78054Y, 78055Y, 78056Y, 78058Y
3.2 Non-port Pins (1/2)
After
Alternate
Function
Pin Name
I/O
Input
Function
Reset
INTP0
INTP1
INTP2
INTP3
INTP4
INTP5
INTP6
SI0
External interrupt request input for which the effective edge (rising
edge, falling edge, or both rising edge and falling edge) can be
specified.
Input
P00/TI00
P01/TI01
P02
P03
P04
P05
P06
Input
Serial interface serial data input.
Serial interface serial data output.
Serial interface serial data input/output.
Input
Input
Input
P25/SB0/SDA0
P20
SI1
SI2
P70/RxD
P26/SB1/SDA1
P21
SO0
Output
SO1
SO2
P71/TxD
P25/SI0/SDA0
P26/SO0/SDA1
P25/SI0/SB0
P26/SO0/SB1
P27/SCL
P22
SB0
Input/
output
SB1
SDA0
SDA1
SCK0
SCK1
SCK2
SCL
Input/
Serial interface serial clock input/ output
Input
output
P72/ASCK
P27/SCK0
P23
STB
Output
Input
Serial interface automatic transmit/receive strobe output.
Serial interface automatic transmit/receive busy input.
Asynchronous serial interface serial data input.
Asynchronous serial interface serial data output.
Asynchronous serial interface serial clock input.
External count clock input to the 16-bit timer (TM0)
Capture trigger signal input to the capture register (CR00)
External count clock input to the 8-bit timer (TM1)
External count clock input to the 8-bit timer (TM2)
16-bit timer (TM0) output (dual-function as 14-bit PWM output)
8-bit timer (TM1) output
Input
Input
Input
Input
Input
Input
BUSY
RxD
P24
Input
P70/SI2
P71/SO2
P72/SCK2
P00/INTP0
P01/INTP1
P33
TxD
Output
Input
ASCK
TI00
TI01
TI1
Input
TI2
P34
TO0
Output
Input
P30
TO1
P31
TO2
8-bit timer (TM2) output
P32
PCL
Output
Output
Clock output (for main system clock, subsystem clock trimming).
Buzzer output.
Input
Input
P35
BUZ
P36
RTP0 to RTP7 Output
Real-time output port by which data is output in synchronization with a trigger. Input
P120 to P127
P40 to P47
AD0 to AD7 Input/
output
Low-order address/data bus at external memory expansion.
Input
A8 to A15
RD
Output
Output
High-order address bus at external memory expansion.
External memory read operation strobe signal output.
External memory write operation strobe signal output.
Input
Input
P50 to P57
P64
WR
P65
12
µPD78052Y, 78053Y, 78054Y, 78055Y, 78056Y, 78058Y
3.2 Non-port Pins (2/2)
After
Dual-
Pin Name
I/O
Function
Reset
Function Pin
WAIT
ASTB
Input
Wait insertion at external memory access.
Input
Input
P66
P67
Output
Strobe output which latches the address information output at port 4
and port 5 to access external memory.
ANI0 to ANI7
ANO0, ANO1
AVREF0
AVREF1
AVDD
AVSS
Input
Output
Input
Input
—
A/D converter analog input.
Input
Input
—
P10 to P17
D/A converter analog output.
P130, P131
A/D converter reference voltage input.
D/A converter reference voltage input.
A/D converter analog power supply. Connect to VDD
Ground potential of A/D converter and D/A converter. Connect to VSS
System reset input.
—
—
—
—
—
—
—
—
RESET
X1
Input
Input
—
—
—
Main system clock oscillation crystal connection.
—
—
X2
—
—
XT1
Input
—
Subsystem clock oscillation crystal connection.
Input
—
P07
—
XT2
VDD
—
Positive power supply.
—
—
VSS
—
Ground potential.
—
—
IC
—
Internally connected. Connect directly to VSS.
—
—
13
µPD78052Y, 78053Y, 78054Y, 78055Y, 78056Y, 78058Y
3.3 Pin I/O Circuits and Recommended Connection of Unused Pins
The input/output circuit type of each pin and recommended connection of unused pins are shown in Table 3-1.
For the input/output circuit configuration of each type, see Figure 3-1.
Table 3-1. Input/Output Circuit Type of Each Pin (1/2)
Input/output
Pin Name
I/O
Recommended Connection when Used
Connect to VSS .
Circuit Type
P00/INTP0/TI00
P01/INTP1/TI01
P02/INTP2
P03/INTP3
P04/INTP4
P05/INTP5
P06/INTP6
P07/XT1
2
Input
8-A
Input/output
Independently connect to VSS through resistor.
16
11
Input
Connect to VDD.
P10/ANI0 to P17/ANI7
P20/SI1
Input/output
Independently connect to VDD or VSS through resistor.
8-A
5-A
8-A
5-A
8-A
10-A
P21/SO1
P22/SCK1
P23/STB
P24/BUSY
P25/SI0/SB0/SDA0
P26/SO0/SB1/SDA1
P27/SCK0/SCL
P30/TO0
5-A
P31/TO1
P32/TO2
P33/TI1
8-A
5-A
P34/TI2
P35/PCL
P36/BUZ
P37
P40/AD0 to P47/AD7
P50/A8 to P57/A15
P60 to P63
P64/RD
5-E
5-A
Independently connect to VDD through resistor.
Independently connect to VDD or VSS through resistor.
Independently connect to VDD through resistor.
Independently connect to VDD or VSS through resistor.
13-B
5-A
P65/WR
P66/WAIT
P67/ASTB
14
µPD78052Y, 78053Y, 78054Y, 78055Y, 78056Y, 78058Y
Table 3-1. Input/Output Circuit Type of Each Pin (2/2)
Input/output
Pin Name
P70/SI2/RxD
I/O
Recommended Connection when Used
Circuit Type
8-A
5-A
8-A
5-A
12-A
2
Input/output
Independently connect to VDD or VSS through resistor.
P71/SO2/TxD
P72/SCK2/ASCK
P120/RTP0 to P127/RTP7
P130/ANO0 , P131/ANO1
Independently connect to VSS through resistor.
RESET
XT2
Input
—
—
16
Leave open.
AVREF0
AVREF1
AVDD
AVSS
IC
—
Connect to VSS .
Connect to VDD .
Connect to VSS .
Connect directly to VSS.
15
µPD78052Y, 78053Y, 78054Y, 78055Y, 78056Y, 78058Y
Figure 3-1. Pin Input/Output Circuits (1/2)
Type 2
Type 8-A
VDD
pull-up
enable
P-ch
IN
VDD
data
P-ch
IN/OUT
output
N-ch
Schmitt-Triggered Input with Hysteresis Characteristic
disable
VDD
Type 5-A
VDD
Type 10-A
pull-up
enable
pul-lup
enable
P-ch
P-ch
VDD
VDD
data
data
P-ch
P-ch
IN/OUT
IN/OUT
output
disable
open drain
output disable
N-ch
N-ch
input
enable
VDD
Type 5-E
Type 11
VDD
pull-up
enable
P-ch
pull-up
enable
P-ch
VDD
data
VDD
P-ch
P-ch
IN/OUT
data
N-ch
output
disable
Comparator
IN/OUT
P-ch
N-ch
output
disable
N-ch
+
-
VREF (Threshold Voltage)
input
enable
16
µPD78052Y, 78053Y, 78054Y, 78055Y, 78056Y, 78058Y
Figure 3-1. Pin Input/Output Circuits (2/2)
VDD
Type 12-A
Type 16
pull-up
enable
feed back
P-ch
cut-off
VDD
P-ch
data
P-ch
IN/OUT
N-ch
output
disable
input
enable
P-ch
N-ch
XT1
XT2
Analog Output
Voltage
Type 13-B
VDD
Mask
Option
IN/OUT
data
output disable
N-ch
VDD
P-ch
RD
Middle-High Voltage Input Buffer
17
µPD78052Y, 78053Y, 78054Y, 78055Y, 78056Y, 78058Y
4. MEMORY SPACE
Figure 4-1 shows the µPD78052Y/78053Y/78054Y/78055Y/78056Y/78058Y memory map.
Figure 4-1. Memory Map
FFFFH
Special Function Registers
(SFR) 256 x 8 bits
FF00H
FEFFH
7A7FH
General Registers
32 x 8 bits
Use Prohibited
FEE0H
FEDFH
F800H
F7FFH
Internal Expanded RAM
1024 x 8 bits
Note1
Internal High-Speed
RAM Note3
F400H
F3FFH
mmmmH
mmmmH − 1
Use Prohibited Note2
F000H
nnnnH
Use Prohibited
FAE0H
FADFH
Data Memory
Space
Buffer RAM 32 x 8 bits
Program Area
FAC0H
FABFH
1000H
0FFFH
Use Prohibited
CALLF Entry Area
FA80H
FA7FH
0800H
07FFH
Program Area
CALLT Table Area
Vector Table Area
External Memory
0080H
007FH
Program Memory
Space
nnnnH + 1
nnnnH
0040H
003FH
Internal ROM Note3
0000H
0000H
Notes 1. Provided in the µPD78058Y only
2. When the external device expansion function is used with the µPD78058Y, set the internal ROM capacity
to 56 Kbytes or less using the internal memory size switching register (IMS).
3. The internal ROM capacity and internal high-speed RAM capacity depend on the products (see the next
table).
Internal ROM Last Address
Internal High-Speed RAM First Address
mmmmH
Relevant Product Name
nnnnH
3FFFH
5FFFH
7FFFH
9FFFH
BFFFH
EFFFH
µPD78052Y
µPD78053Y
µPD78054Y
µPD78055Y
µPD78056Y
µPD78058Y
FD00H
FB00H
18
µPD78052Y, 78053Y, 78054Y, 78055Y, 78056Y, 78058Y
5. PERIPHERAL HARDWARE FUNCTION FEATURES
5.1 Ports
The following 3 types of I/O ports are available.
•
•
•
CMOS input (P00, P07)
:
:
:
:
2
63
4
CMOS input/output (P01 to P06, port 1 to port 5, P64 to P67, port 7, port 12, port 13)
N-channel open-drain input/output (P60 to P63)
Total
69
Table 5-1. Port Functions
Name
Port 0
Pin Name
P00, P07
Function
Dedicated input port pins
Input/output port pins. Input/output specifiable bit-wise.
P01 to P06
When used as input port pins, on-chip pull-up resistor can be used by software.
Port 1
Port 2
Port 3
Port 4
P10 to P17
P20 to P27
P30 to P37
P40 to P47
Input/output port pins. Input/output specifiable bit-wise.
When used as input port pins, on-chip pull-up resistor can be used by software.
Input/output port pins. Input/output specifiable bit-wise.
When used as input port pins, on-chip pull-up resistor can be used by software.
Input/output port pins. Input/output specifiable bit-wise.
When used as input port pins, on-chip pull-up resistor can be used by software.
Input/output port pins. Input/output specifiable in 8-bit units.
When used as input port pins, on-chip pull-up resistor can be used by software.
Test input flag (KRIF) is set to 1 by falling edge detection.
Port 5
Port 6
P50 to P57
P60 to P63
Input/output port pins. Input/output specifiable bit-wise.
When used as input port pins, on-chip pull-up resistor can be used by software.
LED direct drive capability.
N-channel open-drain input/output port pins. Input/output specifiable bit-wise.
On-chip pull-up resistor can be used by mask option.
LED direct drive capability.
P64 to P67
P70 to P72
Input/output port pins. Input/output specifiable bit-wise.
When used as input port pins, on-chip pull-up resistor can be used by software.
Port 7
Input/output port pins. Input/output specifiable bit-wise.
When used as input port pins, on-chip pull-up resistor can be used by software.
Port 12
Port 13
P120 to P127 Input/output port pins. Input/output specifiable bit-wise.
When used as input port pins, on-chip pull-up resistor can be used by software.
P130, P131
Input/output port pins. Input/output specifiable bit-wise.
When used as input port pins, on-chip pull-up resistor can be used by software.
19
µPD78052Y, 78053Y, 78054Y, 78055Y, 78056Y, 78058Y
5.2 Clock Generator
Two types of generators, a main system clock generator and a subsystem clock generator, are avaibable.
The minimum instruction execution time can also be changed.
•
•
0.4 µs/0.8 µs/1.6 µs/3.2 µs/6.4 µs/12.8 µs (@5.0-MHz operation with main system clock)
122 µs (@32.768-kHz operation with subsystem clock)
Figure 5-1. Clock Generator Block Diagram
XT1/P07
XT2
Subsystem
Clock
Oscillator
f
XT
Watch Timer, Clock
Output Function
Prescaler
1
2
f
X
X1
X2
Main System
Clock
Oscillator
Clock to Peripheral
Hardware
Selector
Prescaler
f
XX
Scaler
f
2
XX
f
XX
f
XX
f
XX
f
XT
22 23 24
2
f
2
X
Standby
Control
Circuit
Wait Control
Circuit
STOP
Selector
CPU Clock
(fCPU
)
To INTP0
Sampling Clock
5.3 Timer/Event Counter
5 timer/event counter channels are incorporated.
•
•
•
•
16-bit timer/event counter : 1 channel
8-bit timer/event counter : 2 channels
Watch timer
: 1 channel
: 1 channel
Watchdog timer
Table 5-2. Operation of Timer/Event Counter
16-Bit Timer/Event Counter 8-Bit Timer/Event Counter Watch Timer Watchdog Timer
Operation mode
Interval timer
1 channel
1 channel
2 channels
2 channels
1 channel
—
1 channel
—
External event counter
Function
Timer output
1 output
1 output
2 inputs
1 output
1 output
2
2 outputs
—
—
—
—
—
PWM output
Pulse amplitude measurement
Square wave output
One-shot pulse output
Interrupt source
Test input
2 outputs
—
—
—
—
1
—
2
1
—
—
1 input
—
20
µPD78052Y, 78053Y, 78054Y, 78055Y, 78056Y, 78058Y
Figure 5-2. 16-Bit Timer/Event Counter Block Diagram
Internal Bus
INTP1
TI01/P01/INTP1
16-Bit Capture/
Compare Register
(CR00)
Selector
INTTM00
TO0/P30
PWM pulse
Output
Control
Circuit
Match
Output Control
Circuit
Watch Timer
Output
2fXX
f
XX
16-Bit Timer Register
(TM0)
Selector
f
XX/2
f
XX/22
Clear
Selector
Edge
Detector
TI00/P00/INTP0
Match
INTTM01
INTP0
16-Bit Capture/
Compare Register
(CR01)
Internal Bus
Figure 5-3. 8-Bit Timer/Event Counter Block Diagram
Internal Bus
INTTM1
8-Bit Compare
Register (CR10)
8-Bit Compare
Register (CR20)
Output
Control
Circuit
Selector
Match
TO2/P32
INTTM2
Match
f
xx/2 to fxx/29
8-Bit Timer
Register 1 (TM1)
11
Selector
Selector
f
xx/2
8-Bit Timer
Register 2 (TM2)
Selector
TI1/P33
Clear
Clear
f
xx/2 to fxx/29
xx/211
Selector
f
TI2/P34
Output
Control
Circuit
TO1/P31
Internal Bus
21
µPD78052Y, 78053Y, 78054Y, 78055Y, 78056Y, 78058Y
Figure 5-4. Watch Timer Block Diagram
f
W
214
Selector
5-Bit Counter
f
XX/27
fW
Selector
INTWT
Prescaler
Selector
fXT
f
W
213
f
W
24
f
W
25
f
W
26
f
W
27
f
W
28
f
W
29
INTTM3
Selector
To 16-Bit Timer/
Event Counter
Figure 5-5. Watchdog Timer Block Diagram
f
XX
23
Prescaler
f
XX
24
f
XX
25
f
XX
26
f
XX
27
f
XX
28
f
XX
29
f
XX
211
INTWDT
Maskable
Interrupt Request
Control
Circuit
Selector
8-Bit Counter
RESET
INTWDT
Non-Maskable
Interrupt Request
22
µPD78052Y, 78053Y, 78054Y, 78055Y, 78056Y, 78058Y
5.4 Clock Output Control Circuit
A clock with the following frequencies can be output as the clock output.
•
19.5 kHz/39.1 kHz/78.1 kHz/156 kHz/313 kHz/625 kHz/1.25 MHz/2.5 MHz/5.0 MHz (@5.0-MHz opera-
tion with main system clock)
•
32.768 kHz (@32.768-kHz operation with subsystem clock)
Figure 5-6. Clock Output Control Circuit Block Diagram
fXX
f
XX/2
f
f
f
XX/22
XX/23
XX/24
Synchronization
Circuit
Output Control
Circuit
Selector
PCL/P35
f
XX/25
f
f
XX/26
XX/27
f
XT
5.5 Buzzer Output Control Circuit
A clock with the following frequencies can be output as the buzzer output.
•
1.2 kHz/2.4 kHz/4.9 kHz/9.8 kHz (@5.0-MHz operation with main system clock)
Figure 5-7. Buzzer Output Control Circuit Block Diagram
f
XX/29
10
Output Control
Circuit
BUZ/P36
Selector
f
f
XX/2
11
XX/2
23
µPD78052Y, 78053Y, 78054Y, 78055Y, 78056Y, 78058Y
5.6 A/D Converter
An A/D converter of 8-bit resolution x 8 channels is incorporated.
The following two A/D conversion operation start-up methods are available.
• Hardware start
• Software start
Figure 5-8. A/D Converter Block Diagram
Series Resistor String
AVDD
Sample & Hold Circuit
ANI0/P10
ANI1/P11
ANI2/P12
ANI3/P13
ANI4/P14
ANI5/P15
ANI6/P16
ANI7/P17
AVREF0
Voltage Comparator
Tap
Selector
Selector
Successive Approximation
Register (SAR)
AVSS
Edge
Detection
Circuit
Control
Circuit
INTAD
INTP3
INTP3/P03
A/D Conversion
Result Register (ADCR)
Internal Bus
24
µPD78052Y, 78053Y, 78054Y, 78055Y, 78056Y, 78058Y
5.7 D/A Converter
A D/A converter of 8-bit resolution × 2 channels is available.
Conversion method is R-2R resistor ladder method.
Figure 5-9. D/A Converter Block Diagram
AVREF1
ANOn
Selector
DACSn
Write
AVSS
INTTM
X
D/A Conversion Value Set Register n
(DACSn)
DAMm
D/A Converter
Mode Register
Internal Bus
n = 0, 1
m = 4, 5
x = 1, 2
5.8 Serial Interfaces
3 channels of the clocked serial interface are incorporated.
•
•
•
Serial interface channel 0
Serial interface channel 1
Serial interface channel 2
Table 5-3. Types and Functions of Serial Interface
Function
Serial Interface Channel 0
(MSB/LSB first switchable)
—
Serial Interface Channel 1
(MSB/LSB first switchable)
(MSB/LSB first switchable)
Serial Interface Channel 2
(MSB/LSB first switchable)
—
3-wire serial I/O made
3-wire serial I/O mode with auto-
matic transmit/receive function
2-wire serial I/O mode
I2C bus mode
(MSB first)
(MSB first)
—
—
—
—
—
—
Asynchronous serial interface
(UART) mode
(Dedicated baud rate
generator incorporated)
25
µPD78052Y, 78053Y, 78054Y, 78055Y, 78056Y, 78058Y
Figure 5-10. Serial Interface Channel 0 Block Diagram
Internal Bus
SI0/SB0/SDA0/P25
SO0/SB1/SDA1/P26
Output
Latch
Serial I/O Shift
Register 0 (SIO0)
Selector
Selector
Acknowledge
Output Circuit
Stop Condition/Start
Condition/Acknowledge
Detection Circuit
Interrupt
Request
Signal
INTCSI0
Serial Clock Counter
SCK0/SCL/P27
Generator
f
XX/2 to fXX/28
Serial Clock
Control Circuit
Selector
TO2
Figure 5-11. Serial Interface Channel 1 Block Diagram
Internal Bus
Automatic Data
Automatic Data Transmit/
Receive Address Pointer
(ADTP)
Buffer RAM
Transmit/Receive
Interval Specification
Register (ADTI)
Match
SI1/P20
Serial I/O Shift Register 1 (SIO1)
SO1/P21
STB/P23
5-Bit Counter
Handshake
Control
Circuit
BUSY/P24
Interrupt Request
Signal Generator
Serial Clock Counter
INTCSI1
SCK1/P22
f
XX/2 to fXX/28
Selector
Serial Clock Control Circuit
TO2
26
µPD78052Y, 78053Y, 78054Y, 78055Y, 78056Y, 78058Y
Figure 5-12. Serial Interface Channel 2 Block Diagram
Internal Bus
Receive Buffer Register
Direction Control Circuit
(RXB/SIO2)
Transmit Shift Register
Direction Control Circuit
(TXS/SIO2)
Receive Shift Register
Transmit Control Circuit
INTST
RxD/SI2/P70
(RXS)
TXD/SO2/P71
INTSER
Receive Control Circuit
INTSR/INTCSI2
SCK Output
Control Circuit
ASCK/SCK2/P72
Baud Rate
Generator
f
XX to fXX/210
5.9 Real-time Output Port Functions
Data set previously in the real-time output buffer register is transferred to the output latch by hardware concurrently
with timer interrupt or external interrupt generation in order to output to off-chip. This is a real-time output function.
Pins used to output data to off-chip are called real-time output ports.
By using a real-time output port, a signal which has no jitter can be output. This is most applicable to control
stepping motors, etc.
Figure 5-13. Real-Time Output Port Block Diagram
Internal Bus
Real-Time Output Real-Time Output
INTP2
INTTM1
Output Trigger
Control Circuit
Buffer Register
Higher 4 Bits
(RTBH)
Buffer Register
Lower 4 Bits
(RTBL)
INTTM2
Real-Time Output Port Mode
Register (RTPM)
Output Latch
P127
P120
27
µPD78052Y, 78053Y, 78054Y, 78055Y, 78056Y, 78058Y
6. INTERRUPT FUNCTIONS AND TEST FUNCTIONS
6.1 Interrupt Functions
There are interrupt functions, 22 sources of three different types, as shown below.
•
•
•
Non-maskable interrupt: 1
Maskable interrupts: 20
Software interrupt: 1
The following table shows the interrupt source list.
Table 6-1. Interrupt Source List (1/2)
Vector
Table
Basic
Interrupt Source
Trigger
DefaultNote 1
Priority
Internal/
External
Interrupt Type
Non-maskable
Maskable
Configuration
TypeNote 2
Name
Address
—
0
INTWDT Watchdog timer overflow
(watchdog timer mode 1 selected)
Internal
0004H
(A)
INTWDT Watchdog timer overflow
(interval timer mode selected)
(B)
1
2
INTP0
INTP1
INTP2
INTP3
INTP4
INTP5
INTP6
Pin input edge detection
External
0006H
0008H
000AH
000CH
000EH
0010H
0012H
0014H
0016H
0018H
(C)
(D)
3
4
5
6
7
8
INTCSI0 End of serial interface channel 0 transfer Internal
INTCSI1 End of serial interface channel 1 transfer
(B)
9
10
INTSER Generation of serial interface channel 2
UART receive error
11
12
INTSR
End of serial interface channel 2 UART
reception
001AH
INTCSI2 End of serial interface channel 2 3-wire
transfer
INTST
End of serial interface channel 2 UART
transmission
001CH
Notes 1. The default priority is a priority order when two or more maskable interrupt requests are generated
simultaneously. 0 is the highest order and 18, the lowest.
2. Basic configuration types (A) to (E) correspond to (A) to (E) in Figure 6-1, respectively.
28
µPD78052Y, 78053Y, 78054Y, 78055Y, 78056Y, 78058Y
Table 6-1. Interrupt Source List (2/2)
Vector
Table
Basic
Interrupt Source
Trigger
DefaultNote 1
Priority
Internal/
External
Interrupt Type
Maskable
Configuration
TypeNote 2
Name
Address
13
14
INTTM3 Reference time interval signal from
watch timer
Internal
001EH
(B)
INTTM00 Generation of match signal of 16-bit
timer register and capture/compare
register (CR00)
0020H
15
INTTM01 Generation of match signal of 16-bit
timer register and capture/compare
register (CR01)
0022H
16
17
INTTM1 Generation of match signal of 8-bit
timer/event counter 1
0024H
0026H
INTTM2 Generation of match signal of 8-bit
timer/event counter 2
18
—
INTAD
BRK
End of conversion by A/D converter
BRK instruction execution
0028H
003EH
Software
—
(E)
Notes 1. The default priority is a priority order when two or more maskable interrupts are generated
simultaneously. 0 is the highest order and 18, the lowest.
2. Basic configuration types (A) to (E) correspond to (A) to (E) in Figure 6-1, respectively.
29
µPD78052Y, 78053Y, 78054Y, 78055Y, 78056Y, 78058Y
Figure 6-1. Interrupt Function Basic Configuration(1/2)
(A) Internal non-maskable interrupt
Internal Bus
Vector Table
Address
Generator
Interrupt
Request
Priority
Control Circuit
Standby Release
Signal
(B) Internal maskable interrupt
Internal Bus
IE
PR
ISP
MK
Vector Table
Priority
Control Circuit
Interrupt
Request
Address
IF
Generator
Standby Release
Signal
(C) External maskable interrupt (INTP0)
Internal Bus
Sampling Clock
Select Register
(SCS)
External Interrupt
Mode Register
(INTM0)
PR
ISP
MK
IE
Vector Table
Address
Generator
Priority
Control Circuit
Edge
Detection
Circuit
Interrupt
Request
Sampling
Clock
IF
Standby Release
Signal
30
µPD78052Y, 78053Y, 78054Y, 78055Y, 78056Y, 78058Y
Figure 6-1. Interrupt Function Basic Configuration(2/2)
(D) External maskable interrupt (except INTP0)
Internal Bus
MK
External Interrupt
Mode Register
PR
ISP
IE
(INTM0 and INTM1)
Vector Table
Address
Generator
Priority
Control Circuit
Interrupt
Request
Edge Detection
Circuit
IF
Standby Release
Signal
(E) Software interrupt
Internal Bus
Vector Table
Address
Generator
Priority
Control Circuit
Interrupt
Request
IF : Interrupt request flag
IE : Interrupt enable flag
ISP : In-service priority flag
MK : Interrupt mask flag
PR : Priority specification flag
31
µPD78052Y, 78053Y, 78054Y, 78055Y, 78056Y, 78058Y
6.2 Test Functions
There are two test functions as shown in Table 6-2.
Table 6-2. Test Input Source List
Test Input Source
Trigger
Internal/External
Name
INTWT
INTPT4
Watch timer overflow
Port 4 falling edge detection
Internal
External
Figure 6-2. Test Function Basic Configuration
Internal Bus
MK
Standby Release
Test
IF
Signal
Input
IF : Test input flag
MK : Test mask flag
32
µPD78052Y, 78053Y, 78054Y, 78055Y, 78056Y, 78058Y
7. EXTERNAL DEVICE EXPANSION FUNCTIONS
The external device expansion functions connect external devices to areas other than the internal ROM, RAM,
and SFR. Ports 4 to 6 are used for external device connection.
8. STANDBY FUNCTION
There are the following two standby functions to reduce the system current consumption.
•
•
HALT mode : The CPU operating clock is stopped.
The average current consumption can be reduced by intermittent operation in combination with
the normal operating mode.
STOP mode : The main system clock oscillation is stopped. The whole operation by the main system clock
is stopped, so that the system operates with ultra-low current consumption using only the
subsystem clock.
Figure 8-1. Standby Function
CSS=1
Main System
Clock Operation
Subsystem Clock
Operation Note
CSS=0
HALT
Instruction
STOP
Instruction
HALT
Instruction
Interrupt
Request
Interrupt
Request
Interrupt
Request
STOP Mode
(Main system clock
oscillation stopped)
HALT Mode
(Clock supply to CPU is
stopped, oscillation)
HALT Mode Note
(Clock supply to CPU is
stopped, oscillation)
Note The current consumption can be reduced by stopping the main system clock.
When the CPU is operating on the subsystem clock, set bit 7 (MCC) of processor clock control register (PCC)
to stop the main system clock. The STOP instruction cannot be used.
Caution
When the main system clock is stopped and the system is operated by the subsystem clock, the
subsystem clock should be switched again to the main system clock after the oscillation
stabilization time is secured by the program.
9. RESET FUNCTION
There are the following two reset methods.
•
•
External reset input by RESET pin
Internal reset by watchdog time runaway time detection
33
µPD78052Y, 78053Y, 78054Y, 78055Y, 78056Y, 78058Y
10. INSTRUCTION SET
(1) 8-bit instructions
MOV, XCH, ADD ADDC, SUB, SUBC, AND, OR, XOR, CMP, MULU, DIVUW, INC, DEC, ROR, ROL, RORC,
ROLC, ROR4, ROL4, PUSH, POP, DBNZ
Second
Operand
[HL + Byte]
[HL + B]
[HL + C]
#byte
A
r Note
sfr
saddr !addr16 PSW
[DE]
[HL]
$addr16
1
None
First
Operand
A
ADD
MOV
MOV
XCH
MOV
XCH
ADD
MOV
XCH
ADD
MOV
MOV
XCH
MOV
XCH
ADD
MOV
XCH
ADD
ROR
ROL
ADDC
SUB
XCH
ADD
RORC
ROLC
ADDC
SUB
ADDC ADDC
ADDC ADDC
SUB SUB
SUBC SUBC
SUBC
AND
OR
SUB
SUB
SUBC
AND
OR
SUBC
AND
OR
SUBC
AND
OR
XOR
AND
OR
AND
OR
CMP
XOR
CMP
XOR
CMP
XOR
CMP
XOR
CMP
XOR
CMP
r
MOV
MOV
ADD
INC
DEC
ADDC
SUB
SUBC
AND
OR
XOR
CMP
DBNZ
DBNZ
B, C
sfr
MOV
MOV
MOV
saddr
MOV
ADD
INC
DEC
ADDC
SUB
SUBC
AND
OR
XOR
CMP
!addr16
PSW
MOV
MOV
MOV
PUSH
POP
[DE]
[HL]
MOV
MOV
ROR4
ROL4
[HL + Byte]
MOV
[HL + B]
[HL + C]
X
C
MULU
DIVUW
Note Except r = A
34
µPD78052Y, 78053Y, 78054Y, 78055Y, 78056Y, 78058Y
(2) 16-bit instructions
MOV, XCHW, ADDW, SUBW, CMPW, PUSH, POP, INCW, DECW
Second Operand
#word
ADDW
AX
rp Note
sfrp
saddrp
MOVW
!addr16
MOVW
SP
None
First Operand
MOVW
XCHW
MOVW
MOVW
AX
SUBW
CMPW
MOVW
MOVW Note
INCW
rp
DECW
PUSH
POP
sfrp
MOVW
MOVW
MOVW
MOVW
MOVW
MOVW
saddrp
!addr16
SP
MOVW
Note Only when rp = BC, DE, or HL
(3) Bit manipulate instructions
MOV1, AND1, OR1, XOR1, SET1, CLR1, NOT1, BT, BF, BTCLR
Second Operand
A.bit
sfr.bit
saddr.bit
PSW.bit
[HL].bit
CY
$addr16
None
First Operand
A.bit
MOV1
BT
SET1
CLR1
BF
BTCLR
SET1
CLR1
BT
MOV1
MOV1
MOV1
MOV1
sfr.bit
BF
BTCLR
BT
SET1
CLR1
saddr.bit
PSW.bit
BF
BTCLR
BT
SET1
CLR1
BF
BTCLR
BT
SET1
CLR1
[HL].bit
CY
BF
BTCLR
MOV1
MOV1
MOV1
AND1
MOV1
AND1
MOV1
AND1
SET1
CLR1
NOT1
AND1
AND1
OR1
OR1
OR1
OR1
OR1
XOR1
XOR1
XOR1
XOR1
XOR1
35
µPD78052Y, 78053Y, 78054Y, 78055Y, 78056Y, 78058Y
(4) Call instruction/branch instructions
CALL, CALLF, CALLT, BR, BC, BNC, BZ, BNZ, BT, BF, BTCLR, DBNZ
Second Operand
AX
!addr16
!addr11
CALLF
[addr5]
CALLT
$addr16
BR
First Operand
Basic instruction
BR
CALL
BR
BC
BNC
BZ
BNZ
Compound
instruction
BT
BF
BTCLR
DBNZ
(5) Other instructions
ADJBA, ADJBS, BRK, RET, RETI, RETB, SEL, NOP, EI, DI, HALT, STOP
36
µPD78052Y, 78053Y, 78054Y, 78055Y, 78056Y, 78058Y
11. ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings (TA = 25°C)
Parameter
Symbol
VDD
Test Conditions
Rating
Unit
V
Supply voltage
–0.3 to +7.0
AVDD
AVREF0
AVREF1
AVSS
VI1
–0.3 to VDD + 0.3
–0.3 to VDD + 0.3
–0.3 to VDD + 0.3
–0.3 to +0.3
V
V
V
V
Input voltage
P00 to P07, P10 to P17, P20 to P27, P30 to P37,
P40 to P47, P50 to P57, P64 to P67, P70 to P72,
P120 to P127, P130, P131, X1, X2, XT2, RESET
–0.3 to VDD + 0.3
V
VI2
VO
P60 to P63
N-ch Open-drain
–0.3 to +16
–0.3 to VDD + 0.3
AVSS – 0.3 to AVREF0 + 0.3
–10
V
V
Output voltage
Analog input voltage
VAN
IOH
P10 to P17
1 pin
Analog input pin
V
Output
mA
mA
current high
P01 to P06, P30 to P37, P56, P57, P60 to P67,
P120 to P127 total
–15
P10 to P17, P20 to P27, P40 to P47, P50 to P55,
P70 to P72, P130, P131 total
–15
mA
Note 2
Output
IOL
1 pin
Peak value
r.m.s. value
Peak value
r.m.s. value
Peak value
r.m.s. value
30
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
°C
current low
15
P50 to P55 total
P56, P57, P60 to P63 total
100
70
100
70
P10 to P17, P20 to P27, P40 to P47, Peak value
50
P70 to P72, P130, P131 total
r.m.s. value
20
50
P01 to P06, P30 to P37, P64 to P67, Peak value
P120 to P127 total
r.m.s. value
20
Operating ambient
temperature
TA
–40 to +85
Storage
Tstg
–65 to +150
°C
temperature
Note The r.m.s. should be calculated as follows: [r.m.s.] = [Peak value] × √duty
Caution
If any of the parameters exceed the absolute maximum ratings, even momentarily, device
reliability may be impaired. The absolute maximum ratings are values that may physically damage
the product. Be sure to use the product within the ratings.
Remark The characteristics of dual-function pins and port pins are the same unless otherwise specified.
37
µPD78052Y, 78053Y, 78054Y, 78055Y, 78056Y, 78058Y
Main System Clock Oscillation Circuit Characteristics (TA = –40 to +85°C, VDD = 2.0 to 6.0 V)
Recommended
Circuit
Resonator
Test Conditions
VDD = Oscillator
Parameter
Oscillator
MIN.
1.0
TYP.
MAX.
5.0
Unit
X2
X1 IC
MHz
Ceramic
Note 1
resonator
voltage range
frequency (fx)
C1
C2
4
ms
After VDD reaches oscil-
lation voltage range MIN.
Oscillation
Note 2
stabilization time
Oscillator
X2
R1
X1 IC
C1
1.0
Crystal
5.0
MHz
ms
Note 1
resonator
frequency (fx)
C2
10
30
VDD = 4.5 to 6.0 V
Oscillation
stabilization time Note 2
X1 input
5.0
MHz
ns
1.0
85
External
clock
Note 1
X2
X1
frequency (fx)
500
X1 input
µPD74HCU04
high/low level width
(tXH , tXL)
Notes 1. Indicates only oscillation circuit characteristics. Refer to “AC Characteristics” for instruction execution
time.
2. Time required to stabilize oscillation after reset or STOP mode release.
Cautions 1. When using the main system clock oscillator, wiring in the area enclosed with the broken line
should be carried out as follows to avoid adverse effects from wiring capacitance.
•
•
•
•
•
•
Wiring should be as short as possible.
Wiring should not cross other signal lines.
Wiring should not be placed close to a varying high current.
The potential of the oscillator capacitor ground should be the same as VSS.
Do not ground wiring to a ground pattern in which a high current flows.
Do not fetch a signal from the oscillator.
2. When the main system clock is stopped and the system is operated by the subsystem clock,
the subsystem clock should be switched again to the main system clock after the oscillation
stabilization time is secured by the program.
38
µPD78052Y, 78053Y, 78054Y, 78055Y, 78056Y, 78058Y
Subsystem Clock Oscillation Circuit Characteristics (TA = –40 to +85°C, VDD = 2.0 to 6.0 V)
Resonator
Parameter
Oscillator
Test Conditions
Recommended Circuit
MIN.
32
TYP.
MAX.
35
Unit
kHz
IC XT2 XT1
R2
32.768
Crystal
Note 1
resonator
frequency (fXT)
C4
C3
VDD = 4.5 to 6.0 V
1.2
2
s
Oscillation
Note 2
stabilization time
10
100
32
5
kHz
External
clock
XT1 input
XT2
XT1
Note 1
frequency (fXT)
µs
15
XT1 input
high/low level width
(tXTH , tXTL)
Notes 1. Indicates only oscillation circuit characteristics. Refer to AC Characteristics for instruction execution
time.
2. Time required to stabilize oscillation after VDD reaches MIN. in the oscillation voltage range.
Cautions 1. When using the subsystem clock oscillator, wiring in the area enclosed with the broken line
should be carried out as follows to avoid an adverse effect from wiring capacitance.
•
•
•
•
•
•
Wiring should be as short as possible.
Wiring should not cross other signal lines.
Wiring should not be placed close to a varying high current.
The potential of the oscillator capacitor ground should be the same as VSS.
Do not ground wiring to a ground pattern in which a high current flows.
Do not fetch a signal from the oscillator.
2. The subsystem clock oscillation circuit is a circuit with a low amplification level, more prone
to misoperation due to noise than the main system clock. When using the subsystem clock,
pay special attention to wiring as described above.
39
µPD78052Y, 78053Y, 78054Y, 78055Y, 78056Y, 78058Y
Recommended Oscillator Constant
(1) µPD78052Y, 78053Y, 78054Y, 78055Y, 78056Y
Main System Clock: Ceramic Resonator (TA = –40 to +85°C)
Recommended
Frequency
Oscillator
Manufacturer
Product Name
Circuit consonant
Voltage range
Remarks
(MHz)
C1 (pF)
30
C2 (pF) MIN. (V) MAX. (V)
Murata Mfg.
Co., Ltd.
CSA5.00MG
CST5.00MGW
KBR-5.0MSA
KBR-5.0MKS
5.00
5.00
5.00
5.00
30
2.0
2.0
2.0
2.0
6.0
6.0
6.0
6.0
On-chip On-chip
33 33
Capacitor on chip
Lead type
Kyocera
Corp.
On-chip On-chip
Capacitor on chip,
lead type
KBR-5.0MWS
5.00
On-chip On-chip
2.0
6.0
Capacitor on chip,
lead type
PBRC 5.00A
CCR4.0MC3
CCR5.0MC3
5.00
4.00
5.00
33
33
2.0
2.0
2.0
6.0
6.0
6.0
Chip type
TDK Corp.
On-chip On-chip
On-chip On-chip
Capacitor on chip
Capacitor on chip
Main System Clock: Crystal Resonator (TA = –10 to +70°C)
Oscillator
Recommended
Circuit Constant
Frequency
(MHz)
Voltage Range
Manufacturer
Product Name
C1 (pF)
27
C2 (pF) R1 (kΩ)
27 1.5
MIN. (V) MAX. (V)
Daishinku Corp. SMD-49
3.579545
2.0
6.0
Subsystem Clock: Crystal Resonator (TA = –10 to +70°C)
Oscillator
Recommended
Circuit Constant
Frequency
(MHz)
Voltage Range
Manufacturer
Product Name
C3 (pF)
27
C4 (pF) R2 (kΩ)
20 330
MIN. (V) MAX. (V)
Daishinku Corp. DT-38
(1TA252E00)
32.768
2.0
6.0
Caution
The oscillation circuit constants and oscillation voltage range indicate conditions for stable
oscillation. However, they do not guarantee accuracy of the oscillation frequency. If the
application circuit requires accuracy of the oscillation frequency, it is necessary to set the
oscillation frequency in the application circuit. For this, it is necessary to directly contact the
manufacturer of the resonator being used.
40
µPD78052Y, 78053Y, 78054Y, 78055Y, 78056Y, 78058Y
(2) µPD78058Y
Main System Clock: Ceramic Resonator (TA = –40 to +85°C)
Recommended
Frequency
Oscillator
Manufacturer
Product Name
Circuit consonant
Voltage range
Remarks
(MHz)
C1 (pF)
33
C2 (pF) MIN. (V) MAX. (V)
Kyocera
Corp.
PBRC4.19A
4.19
4.19
4.19
4.19
4.91
4.91
4.91
4.91
33
2.0
2.0
2.0
2.0
2.0
2.0
2.0
2.0
6.0
6.0
6.0
6.0
6.0
6.0
6.0
6.0
PBRC4.19B
On-chip On-chip
33 33
On-chip On-chip
33 33
On-chip On-chip
33 33
On-chip On-chip
Capacitor on chip
Capacitor on chip
Capacitor on chip
Capacitor on chip
KBR-4.19MSA
KBR-4.19MKS
PBRC4.91A
PBRC4.91B
KBR-4.91MSA
KBR-4.91MKS
Caution
The oscillation circuit constants and oscillation voltage range indicate conditions for stable
oscillation. However, they do not guarantee accuracy of the oscillation frequency. If the
application circuit requires accuracy of the oscillation frequency, it is necessary to set the
oscillation frequency in the application circuit. For this, it is necessary to directly contact the
manufacturer of the resonator being used.
Capacitance (TA = 25°C, VDD = VSS = 0 V)
Parameter
Input
Symbol
Test Conditions
MIN.
TYP.
MAX.
15
Unit
pF
CIN
f = 1 MHz
Measured pins retured to 0 V.
capacitance
Input/output
capacitance
CIO
f = 1 MHz
P01 to P06, P10 to P17,
15
pF
Measured pins retured P20 to P27, P30 to P37,
to 0 V.
P40 to P47, P50 to P57,
P64 to P67, P70 to P72,
P120 to P127, P130, P131
P60 to P63
20
pF
Remark The characteristics of the dual-function pins and port pins are the same unless otherwise specified.
41
µPD78052Y, 78053Y, 78054Y, 78055Y, 78056Y, 78058Y
DC Characteristics (TA = –40 to +85°C, VDD = 2.0 to 6.0 V)
Parameter
Symbol
VIH1
Test Conditions
MIN.
TYP.
MAX
Unit
V
Input voltage,
high
P10 to P17, P21, P23, P30 to P32, VDD = 2.7 to 6.0 V
P35 to P37, P40 to P47, P50 to P57,
P64 to P67, P71, P120 to P127,
P130, P131
0.7 VDD
VDD
0.8 VDD
VDD
V
VIH2
VIH3
VIH4
VIH5
VDD = 2.7 to 6.0 V
VDD = 2.7 to 6.0 V
VDD = 2.7 to 6.0 V
0.8 VDD
0.85 VDD
0.7 VDD
VDD
VDD
V
V
V
V
V
V
V
V
V
V
P00 to P06, P20, P22, P24 to P27,
P33, P34, P70, P72, RESET
P60 to P63
15
(N-ch open-drain)
0.8 VDD
15
X1, X2
VDD – 0.5
VDD – 0.2
0.8 VDD
VDD
VDD
XT1/P07, XT2
4.5 V≤ VDD ≤ 6.0 V
2.7 V≤ VDD < 4.5 V
VDD
0.9 VDD
VDD
2.0 V≤ VDD < 2.7 VNote 0.9 VDD
VDD
Input voltage,
low
VIL1
P10 to P17, P21, P23, P30 to P32, VDD = 2.7 to 6.0 V
P35 to P37, P40 to P47, P50 to P57,
P64 to P67, P71, P120 to P127,
P130, P131
0
0.3 VDD
0
0.2 VDD
V
VIL2
VIL3
P00 to P06, P20, P22, P24 to P27, VDD = 2.7 to 6.0 V
P33, P34, P70, P72, RESET
0
0.2 VDD
0.15 VDD
0.3 VDD
0.2 VDD
0.1 VDD
0.4
V
V
V
V
V
V
V
V
V
V
V
V
V
0
P60 to P63
4.5 V≤ VDD ≤ 6.0 V
2.7 V≤ VDD < 4.5 V
0
0
0
VIL4
VIL5
X1, X2
VDD = 2.7 to 6.0 V
0
0
0.2
XT1/P07, XT2
4.5 V≤ VDD ≤ 6.0 V
2.7 V≤ VDD < 4.5 V
2.0 V≤ VDD < 2.7 VNote
0
0.2 VDD
0.1 VDD
0.1 VDD
0
0
Output voltage,
high
VOH
VDD = 4.5 to 6.0 V, IOH = –1 mA
IOH = –100 µA
VDD – 1.0
VDD – 0.5
Output voltage,
low
VOL1
P50 to P57, P60 to P63
VDD = 4.5 to 6.0 V,
IOL = 15 mA
0.4
2.0
0.4
P01 to P06, P10 to P17, P20 to P27, VDD = 4.5 to 6.0 V,
P30 to P37, P40 to P47, P64 to P67, IOL = 1.6 mA
P70 to P72, P120 to P127, P130,
P131
V
VOL2
VOL3
SB0, SB1, SCK0
VDD = 4.5 to 6.0 V,
open-drain,
0.2 VDD
0.5
V
V
pulled-up (R = 1 KΩ)
IOL = 400 µA
Note For use the P07/XT1 pin as P07, input the reverse phase of P07 to the XT2 pin.
Remark The characteristics of dual-function pins and port pins are the same unless otherwise specified.
42
µPD78052Y, 78053Y, 78054Y, 78055Y, 78056Y, 78058Y
DC Characteristics (TA = –40 to +85°C, VDD = 2.7 to 6.0 V)
Parameter
Symbol
ILIH1
Test Conditions
MIN.
TYP.
MAX
3
Unit
Input leakage
current, high
VIN = VDD
P00 to P06, P10 to P17, P20 to P27,
P30 to P37, P40 to P47, P50 to P57,
P60 to P67, P70 to P72,
µA
P120 to P127, P130, P131, RESET
ILIH2
ILIH3
ILIL1
X1, X2, XT1/P07, XT2
P60 to P63
20
80
–3
µA
µA
µA
VIN = 15 V
VIN = 0 V
Input leakage
current, low
P00 to P06, P10 to P17, P20 to P27,
P30 to P37, P40 to P47, P50 to P57,
P64 to P67, P70 to P72,
P120 to P127, P130, P131, RESET
ILIL2
ILIL3
ILOH
X1, X2, XT1/P07, XT2
P60 to P63
–20
–3Note 1
3
µA
µA
µA
Output leakage
current, high
VOUT = VDD
Output leakage
current, low
ILOL
VOUT = 0 V
–3
90
90
µA
kΩ
kΩ
Mask option
R1
VIN = 0 V, P60 to P63
20
15
40
40
pull-up resistor
Software pull-up R2
VIN = 0 V, P01 to P06,
P10 to P17, P20 to P27,
P30 to P37, P40 to P47,
4.5 V≤ VDD ≤ 6.0 V
Note 2
resistor
P50 to P57, P64 to P67, 2.7 V≤ VDD < 4.5 V
P70 to P72, P120 to
20
500
kΩ
P127, P130, P131
Notes 1. If no pull-up resistor is connected in P60 to P63 (specified with mask option), a –200 µA (MAX.) low-level
input leak current flows only during the 1.5-clock interval (no wait interval) during which a read instruction
is executed for port 6 (P6) and port mode register (PM6).
The leak current is –3 µA (MAX.) at all times other than the 1.5-clock interval during which the read
instruction is executed.
2. A software pull-up resistor can be used only in the range of VDD = 2.7 to 6.0 V.
Remark The characteristics of dual-function pins and port pins are the same unless otherwise specified.
43
µPD78052Y, 78053Y, 78054Y, 78055Y, 78056Y, 78058Y
DC Characteristics (TA = –40 to +85°C, VDD = 2.0 to 6.0 V)
Parameter
Symbol
Test Conditions
5.0 MHz Crystal oscillation
MIN.
TYP.
MAX
Unit
Note 1
Note 2
Note 2
Power supply
current Note 5
IDD1
VDD = 5.0 V ±10 %
VDD = 3.0 V ±10 %
VDD = 2.2 V ±10 %
4
12
1.8
mA
mA
mA
operating mode
(fXX = 2.5 MHz)
0.6
Note 3
0.35
1.05
Note 1
Note 2
5.0 MHz Crystal oscillation
operating mode
VDD = 5.0 V ±10 %
VDD = 3.0 V ±10 %
6.5
0.8
19.5
2.4
mA
mA
Note 4
(fXX = 5.0 MHz)
IDD2
5.0 MHz Crystal oscillation
HALT mode
VDD = 5.0 V ±10 %
VDD = 3.0 V ±10 %
VDD = 2.2 V ±10 %
1.4
0.5
280
4.2
1.5
840
mA
mA
µA
Note 3
(fXX = 2.5 MHz)
5.0 MHz Crystal oscillation
HALT mode
VDD = 5.0 V ±10 %
VDD = 3.0 V ±10 %
1.6
4.8
mA
mA
Note 4
0.65
1.95
(fXX = 5.0 MHz)
IDD3
IDD4
IDD5
IDD6
32.768 kHz Crystal oscillation
VDD = 5.0 V ±10 %
VDD = 3.0 V ±10 %
VDD = 2.2 V ±10 %
VDD = 5.0 V ±10 %
VDD = 3.0 V ±10 %
VDD = 2.2 V ±10 %
VDD = 5.0 V ±10 %
VDD = 3.0 V ±10 %
VDD = 2.2 V ±10 %
VDD = 5.0 V ±10 %
VDD = 3.0 V ±10 %
VDD = 2.2 V ±10 %
60
32
120
64
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
Note 6
operating mode
24
48
32.768 kHz Crystal oscillation
HALT mode Note 6
25
55
5
15
2.5
1
12.5
30
XT1 = VDD
STOP mode
0.5
0.3
0.1
0.05
0.05
10
When feedback resistor is used
10
XT1 = VDD
30
STOP mode
10
When feedback resistor is unused
10
Notes 1. The on-chip pull-up resistor, AVREF0, AVREF1, AVDD current, and port current are not included.
2. Operation with main system clock fXX = fX/2 (when oscillation mode selection register (OSMS) is set to
00H)
3. Operation with main system clock fXX = fX (when OSMS is set to 01H)
4. When the main system clock operation is halted.
5. Operating in high-speed mode (when the processor clock control register (PCC) is set to 00H.)
6. Operating in low-speed mode (when PCC is set to 04H)
44
µPD78052Y, 78053Y, 78054Y, 78055Y, 78056Y, 78058Y
AC Characteristics
(1) Basic Operation (TA = –40 to +85°C, VDD = 2.0 to 6.0 V)
Parameter
Cycle time
Symbol
Test Conditions
MIN.
TYP.
MAX.
64
Unit
µs
TCY
Operating on main system clock
(fXX = 2.5 MHz)Note 1
VDD = 2.7 to 6.0 V
0.8
(Min. instruction
execution time)
2.2
0.4
64
µs
Operating on main system clock
(fXX = 5.0 MHz)Note 2
4.5 V≤ VDD ≤ 6.0 V
2.7 V≤ VDD < 4.5 V
32
µs
0.8
32
µs
Operating on sub system clock
3.5 V ≤ VDD ≤ 6.0 V
40Note 3
2/fsam + 0.1Note4
2/fsam + 0.2Note4
2/fsam + 0.5Note4
10
122
125
µs
TI00 input
tTIH00,
µs
high-/low-level width tTIL00
2.7 V ≤ VDD < 3.5 V
µs
µs
TI01 input
tTIH01,
VDD = 2.7 to 6.0 V
VDD = 4.5 to 6.0 V
VDD = 4.5 to 6.0 V
INTP0
µs
high-/low-level width tTIL01
20
µs
TI1, TI2
fTI1
0
4
MHz
kHz
ns
input frequency
0
275
TI1, TI2 input
tTIH1,
100
high-/low-level width tTIL1
1.8
µs
Interrupt request
input high-/
tINTH,
tINTL
3.5 V ≤ VDD ≤ 6.0 V 2/fsam + 0.1 Note4
2.7 V ≤ VDD < 3.5 V 2/fsam + 0.2 Note4
2/fsam + 0.5 Note4
µs
µs
low-level width
µs
INTP1 to INTP6, KR0 to KR7
VDD = 2.7 to 6.0 V
VDD = 2.7 to 6.0 V
10
20
10
20
µs
µs
RESET low
level width
tRSL
µs
µs
Notes 1. Main system clock fXX = fX/2 operation (when an oscillation mode selection register (OSMS) is set to 00H)
2. Main system clock fXX = fX operation (when OSMS is set to 01H)
3. On an external clock. When a crystal resonator is used, the minimum value is 114 µs.
4. In combination with bits 0 (SCS0) and 1 (SCS1) of sampling clock selection register, fsam is selectable
between fXX/2N, fXX/32, fXX/64, and fXX/128 (when N= 0 to 4).
45
µPD78052Y, 78053Y, 78054Y, 78055Y, 78056Y, 78058Y
T
CY vs VDD (At fXX = f
X
/2 main system clock operation)
T
CY vs VDD (At fXX = f
X
main system clock operation)
60
60
10
10
Operation Guaranteed
Range
Operation Guaranteed
Range
2.0
1.0
2.0
1.0
0.5
0.4
0.5
0.4
0
0
1
2
3
4
5
6
1
2
3
4
5
6
Supply Voltage VDD [V]
Supply Voltage VDD [V]
46
µPD78052Y, 78053Y, 78054Y, 78055Y, 78056Y, 78058Y
(2) Read/write Operation
(a) When MCS = 1, PCC2 to PCC0 = 000B (TA = –40 to +85°C, VDD = 4.5 to 6.0 V)
Parameter
ASTB high-level width
Address setup time
Symbol
tASTH
tADS
Test Conditions
MIN.
0.85tCY – 50
0.85tCY – 50
50
MAX.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address hold time
tADH
Data input time from address
tADD1
tADD2
tRDD1
tRDD2
tRDH
(2.85 + 2n)tCY – 80
(4 + 2n)tCY – 100
(2 + 2n)tCY – 100
(2.85 + 2n)tCY – 100
Data input time from RD↓
Read data hold time
RD low-level width
0
tRDL1
tRDL2
tRDWT1
tRDWT2
tWRWT
tWTL
(2 + 2n)tCY – 60
(2.85 + 2n)tCY – 60
WAIT↓ input time from RD↓
0.85tCY – 50
2tCY – 60
WAIT↓ input time from WR↓
WAIT low-level width
2tCY – 60
(1.15 + 2n)tCY
(2.85 + 2n)tCY – 100
20
(2 + 2n)tCY
Write data setup time
tWDS
Write data hold time
tWDH
WR low-level width
tWRL
(2.85 + 2n)tCY – 60
25
RD↓ delay time from ASTB↓
WR↓ delay time from ASTB↓
tASTRD
tASTWR
tRDAST
0.85tCY + 20
0.85tCY – 10
ASTB↑ delay time from
RD↑ in external fetch
1.15tCY + 20
1.15tCY + 50
Address hold time from
tRDADH
0.85tCY – 50
ns
RD↑ in external fetch
Write data output time from RD↑
Write data output time from WR↓
Address hold time from WR↑
RD↑ delay time from WAIT↑
WR↑ delay time from WAIT↑
tRDWD
tRDWD
tWRADH
tWTRD
tWTWR
40
0
ns
ns
ns
ns
ns
50
0.85tCY
1.15tCY + 40
3.15tCY + 40
3.15tCY + 30
1.15tCY + 40
1.15tCY + 30
Remarks 1. MCS: Oscillation mode selection register (OSMS) bit 0
2. PCC2 to PCC0: Processor clock control register (PCC) bit 2 to 0
3. tCY = TCY/4
4. n indicates number of waits.
47
µPD78052Y, 78053Y, 78054Y, 78055Y, 78056Y, 78058Y
(b) Except when MCS = 1, PCC2 to PCC0 = 000B (TA = –40 to +85°C, VDD = 2.0 to 6.0 V)
(1/2)
Parameter
Symbol
Test Conditions
MIN.
MAX.
Unit
ASTB high-level width
tASTH
VDD = 2.7 to 6.0 V
tCY – 80
tCY – 150
tCY – 80
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address setup time
tADS
VDD = 2.7 to 6.0 V
VDD = 2.7 to 6.0 V
VDD = 2.7 to 6.0 V
VDD = 2.7 to 6.0 V
VDD = 2.7 to 6.0 V
VDD = 2.7 to 6.0 V
tCY – 150
0.4tCY – 10
0.37tCY – 40
Address hold time
tADH
Data input time from address
tADD1
tADD2
tRDD1
tRDD2
(3 + 2n)tCY – 160
(3 + 2n)tCY – 320
(4 + 2n)tCY – 200
(4 + 2n)tCY – 300
(1.4 + 2n)tCY – 70
(1.37 + 2n)tCY – 120
(2.4 + 2n)tCY – 70
(2.37 + 2n)tCY – 120
Data input time from RD↓
Read data hold time
RD low-level width
tRDH
0
tRDL1
VDD = 2.7 to 6.0 V
VDD = 2.7 to 6.0 V
VDD = 2.7 to 6.0 V
VDD = 2.7 to 6.0 V
VDD = 2.7 to 6.0 V
(1.4 + 2n)tCY – 20
(1.37 + 2n)tCY – 20
(2.4 + 2n)tCY – 20
(2.37 + 2n)tCY – 20
tRDL2
WAIT↓ input time from RD↓
WAIT↓ input time from WR↓
tRDWT1
tRDWT2
tWRWT
tCY – 100
tCY – 200
2tCY – 100
2tCY – 200
2tCY – 100
2tCY – 200
(2 + 2n)tCY
WAIT low-level width
Write data setup time
tWTL
tWDS
(1 + 2n)tCY
(2.4 + 2n)tCY – 60
(2.37 + 2n)tCY – 100
20
VDD = 2.7 to 6.0 V
Write data hold time
WR low-level width
tWDH
tWRL
VDD = 2.7 to 6.0 V
VDD = 2.7 to 6.0 V
VDD = 2.7 to 6.0 V
(2.4 + 2n)tCY – 20
(2.37 + 2n)tCY – 20
0.4tCY – 30
RD↓ delay time from ASTB↓
WR↓ delay time from ASTB↓
tASTRD
0.37tCY – 50
tASTWR
1.4tCY – 30
1.37tCY – 50
Remarks 1. MCS: Oscillation mode selection register (OSMS) bit 0
2. PCC2 to PCC0: Processor clock control register (PCC) bit 2 to 0
3. tCY = TCY/4
4. n indicates the number of waits.
48
µPD78052Y, 78053Y, 78054Y, 78055Y, 78056Y, 78058Y
(b) Except when MCS = 1, PCC2 to PCC0 = 000B (TA = –40 to +85°C, VDD = 2.0 to 6.0 V)
(1/2)
Parameter
Symbol
tRDAST
Test Conditions
MIN.
MAX.
Unit
ns
ASTB↑ delay time from
RD↑ in external fetch
tCY – 10
tCY + 20
Address hold time from
tRDADH
tRDWD
tCY – 50
tCY + 50
ns
RD↑ in external fetch
Write data output time from RD↑
Write data output time from WR↓
Address hold time from WR↑
RD↑ delay time from WAIT↑
WR↑ delay time from WAIT↑
VDD = 2.7 to 6.0 V
VDD = 2.7 to 6.0 V
VDD = 2.7 to 6.0 V
VDD = 2.7 to 6.0 V
VDD = 2.7 to 6.0 V
0.4tCY – 20
0.37tCY – 40
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tWRWD
tWRADH
tWTRD
tWTWR
60
0
120
tCY
tCY + 60
tCY
tCY + 120
0.6tCY + 180
0.63tCY + 350
0.6tCY + 120
0.63tCY + 240
2.6tCY + 180
2.63tCY + 350
2.6tCY + 120
2.63tCY + 240
Remarks 1. MCS: Oscillation mode selection register (OSMS) bit 0
2. PCC2 to PCC0: Processor clock control register (PCC) bit 2 to 0
3. tCY = TCY/4
4. n indicates number of waits.
49
µPD78052Y, 78053Y, 78054Y, 78055Y, 78056Y, 78058Y
(3) Serial Interface (TA = –40 to +85°C, VDD = 2.0 to 6.0 V)
(a) Serial interface channel 0
(i) 3-wire serial I/O mode (SCK0... Internal clock output)
Parameter
Symbol
Test Conditions
4.5 V ≤ VDD ≤ 6.0 V
2.7 V ≤ VDD < 4.5 V
MIN.
800
TYP.
MAX.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
SCK0 cycle time
tKCY1
1600
3200
SCK0 high-/low-level
width
tKH1, tKL1
tSIK1
VDD = 4.5 to 6.0 V
tKCY1/2 – 50
tKCY1/2 – 100
100
SI0 setup time
4.5 V ≤ VDD ≤ 6.0 V
2.7 V ≤ VDD < 4.5 V
(to SCK0↑)
150
300
SI0 hold time (from
tKSI1
400
SCK0↑)
SO0 output delay time tKSO1
C = 100 pF Note
300
ns
from SCK0↓
Note C is the load capacitance of SCK0, SO0 output line.
(ii) 3-wire serial I/O mode (SCK0... External clock input)
Parameter
Symbol
Test Conditions
4.5 V ≤ VDD ≤ 6.0 V
2.7 V ≤ VDD < 4.5 V
MIN.
800
TYP.
MAX.
Unit
ns
ns
ns
ns
ns
ns
ns
SCK0 cycle time
tKCY2
1600
3200
400
SCK0 high-/low-level
width
tKH2, tKL2
4.5 V ≤ VDD ≤ 6.0 V
2.7 V ≤ VDD < 4.5 V
800
1600
100
SI0 setup time (to
tSIK2
SCK0↑)
SI0 hold time (from
tKSI2
400
ns
ns
ns
ns
SCK0↑)
SO0 output delay time tKSO2
C = 100 pF Note
300
160
from SCK0↓
SCK0 rise, fall time
tR2, tF2
When using external device
expansion function
When not using external device
expansion function
1000
Note C is the load capacitance of SO0 output line.
50
µPD78052Y, 78053Y, 78054Y, 78055Y, 78056Y, 78058Y
(iii) 2-wire serial I/O mode (SCK0... Internal clock output)
Parameter
Symbol
Test Conditions
MIN.
1600
TYP.
MAX.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SCK0 cycle time
tKCY3
R = 1 kΩ,
C = 100 pF Note
VDD = 2.7 to 6.0 V
VDD = 2.7 to 6.0 V
VDD = 4.5 to 6.0 V
3200
SCK0 high-level width
SCK0 low-level width
tKH3
tKL3
tSIK3
tKCY3/2 – 160
tKCY3/2 – 190
tKCY3/2 – 50
tKCY3/2 – 100
300
SB0, SB1 setup time
4.5 V ≤ VDD ≤ 6.0 V
2.7 V ≤ VDD < 4.5 V
(to SCK0↑)
350
400
SB0, SB1 hold time
tKSI3
600
(from SCK0↑)
SB0, SB1 output delay
tKSO3
0
300
ns
time from SCK0↓
Note R and C are the load resistance and load capacitance of the SCK0, SB0, and SB1 output line.
(iv) 2-wire serial I/O mode (SCK0... External clock input)
Parameter
Symbol
Test Conditions
VDD = 2.7 to 6.0 V
MIN.
1600
3200
650
TYP.
MAX.
Unit
ns
ns
ns
ns
ns
ns
ns
SCK0 cycle time
tKCY4
SCK0 high-level width
SCK0 low-level width
tKH4
VDD = 2.7 to 6.0 V
VDD = 2.7 to 6.0 V
1300
800
tKL4
1600
100
SB0, SB1 setup time
tSIK4
tKSI4
tKSO4
(to SCK0↑)
SB0, SB1 hold time
tKCY4/2
ns
(from SCK0↑)
SB0, SB1 output delay
R = 1 kΩ,
VDD = 4.5 to 6.0 V
0
0
300
500
160
ns
ns
ns
time from SCK0↓
C = 100 pF Note
SCK0 rise, fall time
tR4, tF4
When using external device
expansion function
When not using external device
expansion function
1000
ns
Note R and C are the load resistance and load capacitance of the SCK0, SB0, and SB1 output line.
51
µPD78052Y, 78053Y, 78054Y, 78055Y, 78056Y, 78058Y
(v) I2C Bus mode (SCL...Internal clock output)
Parameter
Symbol
Test Conditions
VDD = 2.7 to 6.0 V
MIN.
10
TYP.
MAX.
Unit
µs
µs
ns
ns
ns
ns
ns
ns
ns
SCL cycle time
tKCY5
R = 1 kΩ
Note
C = 100pF
20
SCL high-level width
SCL low-level width
tKH5
tKL5
VDD = 2.7 to 6.0 V
VDD = 4.5 to 6.0 V
VDD = 2.7 to 6.0 V
tKCY5 – 160
tKCY5 – 190
tKCY5 – 50
tKCY5 – 100
200
SDA0, SDA1 setup time tSIK5
(to SCL↑)
300
SDA0, SDA1 hold time
tKSI5
0
(to SCL↓)
SDA0, SDA1 output
tKSO5
VDD = 4.5 to 6.0 V
0
0
300
500
ns
ns
ns
delay time from SCL↓
SCL↑→SDA0, SDA1↓
tKSB
200
or SCL↑→SDA0, SDA1↑
SDA0, SDA1↓
→
SCL↓
tSBK
tSBH
400
500
ns
ns
SDA0, SDA1 high-level
width
Note R and C are the load resistance and load capacitance of the SCK0, SB0, and SB1 output line.
(vi) I2C Bus mode (SCL...External clock input)
Parameter
Symbol
Test Conditions
MIN.
1000
400
TYP.
MAX.
Unit
ns
SCL cycle time
tKCY6
SCL high-/low-level width tKH6, tKL6
ns
SDA0, SDA1 setup time tSIK6
200
ns
(to SCL↑)
SDA0, SDA1 hold time
tKSI6
0
ns
(to SCL↓)
SCL↓→ SDA0, SDA1
tKSO6
R = 1 kΩ,
VDD = 4.5 to 6.0 V
0
0
300
500
ns
ns
ns
output delay time
Note
C = 100 pF
SCL↑→SDA0, SDA1↓
tKSB
200
or SCL↑→SDA0, SDA1↑
SDA0, SDA1↓
→
SCL↓
tSBK
tSBH
400
500
ns
ns
SDA0, SDA1 high-level
width
SCL rise, fall time
tR6, tF6
When using external device
expansion function
160
ns
ns
When not using external device
expansion function
1000
Note R and C are the load resistance and load capacitance of the SDA0, SDA1 output line.
52
µPD78052Y, 78053Y, 78054Y, 78055Y, 78056Y, 78058Y
(b) Serial interface channel 1
(i) 3-wire serial I/O mode (SCK1... Internal clock output)
Parameter
Symbol
Test Conditions
4.5 V ≤ VDD ≤ 6.0 V
2.7 V ≤ VDD < 4.5 V
MIN.
TYP.
800
MAX.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
SCK1 cycle time
tKCY7
1600
3200
SCK1 high-/low-level
width
tKH7, tKL7
tSIK7
V
DD = 4.5 to 6.0 V
tKCY7/2 – 50
tKCY7/2 – 100
100
SI1 setup time
4.5 V ≤ VDD ≤ 6.0 V
2.7 V ≤ VDD < 4.5 V
(to SCK1↑)
150
300
SI1 hold time
tKSI7
400
(from SCK1↑)
Note
SO1 output delay time
tKSO7
C = 100 pF
300
ns
from SCK1↓
Note C is the load capacitance of the SCK1 and SO1 output lines.
(ii) 3-wire serial I/O mode (SCK1... External clock input)
Parameter
Symbol
Test Conditions
4.5 V ≤ VDD ≤ 6.0 V
2.7 V ≤ VDD < 4.5 V
MIN.
800
TYP.
MAX.
Unit
ns
ns
ns
ns
ns
ns
ns
SCK1 cycle time
tKCY8
1600
3200
400
SCK1 high-/low-level
width
tKH8, tKL8 4.5 V ≤ VDD ≤ 6.0 V
2.7 V ≤ VDD < 4.5 V
800
1600
100
SI1 setup time
tSIK8
(to SCK1↑)
SI1 hold time
tKSI8
400
ns
ns
ns
ns
(from SCK1↑)
Note
SO1 output delay
tKSO8
C = 100 pF
300
160
time from SCK1↓
SCK1 rise, fall time
tR8, tF8
When using external device
expansion function
When not using external device
expansion function
1000
Note C is the load capacitance of the SO1 output line.
53
µPD78052Y, 78053Y, 78054Y, 78055Y, 78056Y, 78058Y
(iii) 3-wire serial I/O mode with automatic transmit/receive function (SCK1...Internal clock output)
Parameter
SCK1 cycle time
Symbol
Test Conditions
4.5 V ≤ VDD ≤ 6.0 V
2.7 V ≤ VDD < 4.5 V
MIN.
800
TYP.
MAX.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tKCY9
1600
3200
SCK1 high-/low-level width
tKH9,
tKL9
VDD = 4.5 to 6.0 V
tKCY9/2 – 50
tKCY9/2 – 100
100
SI1 setup time (to SCK1↑)
tSIK9
4.5 V ≤ VDD ≤ 6.0 V
2.7 V ≤ VDD < 4.5 V
150
300
SI1 hold time (from SCK1↑)
SO1 output delay time from SCK1↓
STB↑ from SCK1↑
tKSI9
tKSO9
tSBD
tSBW
400
C = 100 pF Note
VDD = 2.7 to 6.0V
300
tKCY9/2 – 100
tKCY9 – 30
tKCY9 – 60
100
tKCY9/2 + 100
tKCY9 + 30
tKCY9 + 60
Strobe signal high-level width
Busy signal setup time
tBYS
tBYH
(to busy signal detection timing)
Busy signal hold time
4.5 V ≤ VDD ≤ 6.0 V
2.7 V ≤ VDD < 4.5 V
100
150
200
ns
ns
ns
ns
(from busy signal detection timing)
SCK1↓ from busy inactive
tSPS
2tKCY9
Note C is the load capacitance of the SCK1, SO1 output line.
(iv) 3-wire serial I/O mode with automatic transmit/receive function (SCK1...External clock input)
Parameter
SCK1 cycle time
Symbol
Test Conditions
4.5 V ≤ VDD ≤ 6.0 V
2.7 V ≤ VDD < 4.5 V
MIN.
800
TYP.
MAX.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tKCY10
1600
3200
400
SCK1 high-/low-level width
tKH10,
tKL10
4.5 V ≤ VDD ≤ 6.0 V
2.7 V ≤ VDD < 4.5 V
800
1600
100
SI1 setup time (to SCK1↑)
SI1 hold time (from SCK1↑)
SO1 output delay time from SCK1↓
SCK1 rise, fall time
tSIK10
tKIS10
tKSO10
400
C = 100 pF Note
300
160
tR10,
tF10
When using external
device expansion function
When not using external
device expansion function
1000
ns
Note C is the load capacitance of the SO1 output line.
54
µPD78052Y, 78053Y, 78054Y, 78055Y, 78056Y, 78058Y
(c) Serial interface channel 2
(i) 3-wire serial I/O mode (SCK2... Internal clock output)
Parameter
Symbol
Test Conditions
4.5 V ≤ VDD ≤ 6.0 V
2.7 V ≤ VDD < 4.5 V
MIN.
800
TYP.
MAX.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
SCK2 cycle time
tKCY11
1600
3200
SCK2 high-/low-level
width
tKH11,
tKL11
tSIK11
V
DD = 4.5 to 6.0 V
tKCY11/2 – 50
tKCY11/2 – 100
100
SI2 setup time
4.5 V ≤ VDD ≤ 6.0 V
2.7 V ≤ VDD < 4.5 V
(to SCK2↑)
150
300
SI2 hold time
tKSI11
400
(to SCK2↑)
Note
SO2 output delay time
tKSO11
C = 100 pF
300
ns
from SCK2↓
Note C is the load capacitance of the SCK2, SO2 output line.
(ii) UART mode (Dedicated baud rate generator output)
Parameter
Transfer rate
Symbol
Test Conditions
4.5 V ≤ VDD ≤ 6.0 V
2.7 V ≤ VDD < 4.5 V
MIN.
TYP.
MAX.
78125
39063
19531
Unit
bps
bps
bps
(iii) UART mode (External clock input)
Parameter
Symbol
Test Conditions
4.5 V ≤ VDD ≤ 6.0 V
MIN.
800
TYP.
MAX.
Unit
ns
ASCK cycle time
tKCY12
2.7 V ≤ VDD < 4.5 V
1600
3200
400
ns
ns
ASCK high-/low-level
width
tKH12,
tKL12
4.5 V ≤ VDD ≤ 6.0 V
2.7 V ≤ VDD < 4.5 V
ns
800
ns
1600
ns
Transfer rate
4.5 V ≤ VDD ≤ 6.0 V
2.7 V ≤ VDD < 4.5 V
39063
19531
9766
bps
bps
bps
ns
ASCK rise, fall time
tR12, tF12
VDD = 4.5 to 6.0 V,
1000
when not using external
device expansion function.
160
ns
55
µPD78052Y, 78053Y, 78054Y, 78055Y, 78056Y, 78058Y
AC Timing Test Point (Excluding X1, XT1 Input)
0.8 VDD
0.2 VDD
0.8 VDD
0.2 VDD
Test Points
Clock Timing
1/fX
t
XL
t
XH
V
V
IH4 (MIN.)
IL4 (MAX.)
X1 Input
1/fXT
t
XTL
t
XTH
V
V
IH5 (MIN.)
IL5 (MAX.)
XT1 Input
TI Timing
tTIL00, tTIL01
tTIH00, tTIH01
TI00, TI01
1/fTI1
tTIL1
tTIH1
TI1, TI2
56
µPD78052Y, 78053Y, 78054Y, 78055Y, 78056Y, 78058Y
Read/Write Operation
External Fetch (No Wait) :
A8 to A15
Higher 8-Bit Address
Lower 8-Bit
Address
t
ADD1
Hi-z
Operation
Code
AD0 to AD7
t
RDADH
t
ADS
t
RDD1
t
ADH
t
ASTH
t
RDAST
ASTB
RD
t
ASTRD
t
RDL1
t
RDH
External Fetch (Wait Insertion) :
A8 to A15
Higher 8-Bit Address
Lower 8-Bit
Address
tADD1
Hi-z
Operation
Code
AD0 to AD7
tRDD1
t
RDADH
tADS
tADH
tASTH
t
RDAST
ASTB
RD
tASTRD
tRDL1
tRDH
WAIT
t
WTRD
tWTL
t
RDWT1
57
µPD78052Y, 78053Y, 78054Y, 78055Y, 78056Y, 78058Y
External Data Access (No Wait) :
A8 to A15
Higher 8-Bit Address
Lower
8-Bit
Address
tADD2
Hi-z
Hi-z
Hi-z
AD0 to AD7
Read Data
Write Data
t
RDD2
t
ADS
t
ADH
t
RDH
t
ASTH
ASTB
RD
tASTRD
t
WDH
t
RDWD
tRDL2
t
WDS
t
WDWR
WR
t
ASTWR
tWRL
t
WRADH
External Data Access (Wait Insertion) :
A8 to A15
Higher 8-Bit Address
Lower
8-Bit
Address
tADD2
Hi-z
Hi-z
Hi-z
AD0 to AD7
Read Data
Write Data
t
RDD2
t
ADS
t
ADH
t
RDH
t
ASTH
ASTB
RD
tASTRD
t
WDH
t
RDWD
tRDL2
t
WDS
t
WDWR
WR
t
ASTWR
t
WRL
t
WRADH
WAIT
t
RDWT2
t
WTRD
t
WTL
t
WRWT
t
WTL
t
WTWR
58
µPD78052Y, 78053Y, 78054Y, 78055Y, 78056Y, 78058Y
Serial Transfer Timing
3-wire Serial I/O Mode :
t
KCYm
t
KLm
tKHm
t
Rn
t
Fn
SCK0 to SCK2
t
SIKm
t
KSIm
SI0 to SI2
Input Data
t
KSOm
Output Data
SO0 to SO2
m = 1, 2, 7, 8, 11
n = 2, 8
2-wire Serial I/O Mode :
t
KCY3, 4
t
KL3, 4
t
KH3, 4
t
R4
t
F4
SCK0
t
SIK3, 4
t
KSO3, 4
t
KSI3, 4
SB0, SB1
I2C Bus Mode:
tF6
tR6
t
KCY5, 6
SCL
tKSB
tKSB
tSIK5, 6
t
KH5, 6
tKL5, 6
tKSI5, 6
tSBK
tKSO5, 6
SDA0, SDA1
tSBH
tSBK
59
µPD78052Y, 78053Y, 78054Y, 78055Y, 78056Y, 78058Y
3-wire Serial I/O Mode with Automatic Transmit/Receive Function :
SO1
SI1
D2
D1
D0
D7
D2
D1
D0
D7
tKSI9, 10
tSIK9, 10
tKH9, 10
tKSO9, 10
tF10
SCK1
STB
tR10
t
KL9, 10
KCY9, 10
t
tSBD
tSBW
3-wire Serial I/O Mode with Automatic Transmit/Receive Function (Busy processing) :
SCK1
7
8
9 Note
10 Note
10+n Note
1
t
BYS
tBYH
t
SPS
BUSY
(Active high)
Note The signal is not actually driven low here; it is shown as such to indicate the timing.
UART Mode (External Clock Input) :
KCY12
t
t
KL12
tKH12
t
F12
t
R12
ASCK
60
µPD78052Y, 78053Y, 78054Y, 78055Y, 78056Y, 78058Y
A/D Converter Characteristics (TA = –40 to +85°C, AVDD = VDD = 2.0 to 6.0 V, AVSS = VSS = 0 V)
Parameter
Symbol
Test Conditions
MIN.
8
TYP.
8
MAX.
8
Unit
bit
%
Resolution
Overall error Note
2.7 V ≤ AVREF0 ≤ AVDD
2.0 V ≤ AVREF0 < 2.7 V
±0.6
±1.4
200
%
Conversion time
tCONV
19.1
12/fxx
AVSS
2.0
µs
µs
V
Sampling time
tSAMP
Analog input voltage
Reference voltage
VIAN
AVREF0
AVDD
AVREF0
RAIREF0
V
Resistance between AVREF0 and AVSS
4
14
kΩ
Note Overall error excluding quantization error (±1/2 LSB). It is indicated as a ratio to the full-scale value.
fXX
fX
: Main system clock frequency (fX or fX/2)
: Main system clock oscillation frequency
D/A Converter Characteristics (TA = –40 to +85°C, VDD = 2.0 to 6.0 V, AVSS = VSS = 0 V)
Parameter
Symbol
Test Conditions
MIN.
TYP.
MAX.
8
Unit
bit
%
Resolution
Overall error
R = 2 MΩ Note1
1.2
0.8
0.6
10
R = 4 MΩ Note1
%
R = 10 MΩ Note1
%
Settling time
C=30pF 4.5 V ≤ AVREF1 ≤ 6.0 V
µs
µs
µs
kΩ
V
Note1
2.7 V ≤ AVREF1 < 4.5 V
15
2.0 V ≤ AVREF1 < 2.7 V
20
RO
DACS0, DACS1 = 55H Note 2
10
Output resistance
Analog reference voltage
AVREF1 current
AVREF1
IREF1
2.0
VDD
Note2
1.5
mA
Notes 1. R and C denote D/A converter output pin load resistance and load capacitance, respectively.
2. Value for one D/A converter channel
DACS0, DACS1: D/A conversion value setting register.
61
µPD78052Y, 78053Y, 78054Y, 78055Y, 78056Y, 78058Y
Data Memory Stop Mode Low Supply Voltage Data Retention Characteristics (TA = –40 to +85°C)
Parameter
Symbol
Test Conditions
MIN.
1.8
TYP.
MAX.
6.0
Unit
V
Data retention power
supply voltage
VDDDR
Data retention
power supply
current
IDDDR
VDDDR = 1.8 V
0.1
10
µA
Subsystem clock stop and feedback resistor
disconnected
Release signal set time
tSREL
tWAIT
0
µs
Oscillation stabiliation
wait time
Release by RESET
217/fx
ms
Release by interrupt request
Note
ms
Note In combination with bits 0 to 2 (OSTS0 to OSTS2) of oscillation stabilization time selection register (OSTS), selection
of 212/fXX and 214/fXX to 217/fXX is possible.
fXX
: Main system clock frequency (fX or fX/2)
: Main system clock oscillation frequency
fX
Data Retention Timing (STOP Mode Release by RESET)
Internal Reset Operation
HALT Mode
Operating Mode
STOP Mode
Data Retention Mode
VDD
VDDDR
t
SREL
STOP Instruction Execution
RESET
tWAIT
Data Retention Timing (Standby Release Signal: STOP Mode Release by Interrupt Request Signal)
HALT Mode
Operating Mode
STOP Mode
Data Retention Mode
V
DD
V
DDDR
tSREL
STOP Instruction Execution
Standby Release Signal
(Interrupt Request)
tWAIT
62
µPD78052Y, 78053Y, 78054Y, 78055Y, 78056Y, 78058Y
Interrupt Request Input Timing
tINTL
tINTH
INTP0 to INTP6
RESET Input Timing
tRSL
RESET
63
µPD78052Y, 78053Y, 78054Y, 78055Y, 78056Y, 78058Y
12. CHARACTERISTIC CURVES (REFERENCE VALUE)
I
DD vs VDD (fx = fxx = 5.0 MHz)
(TA = 25°C)
10.0
5.0
PCC = 00H
PCC = 01H
PCC = 02H
PCC = 03H
PCC = 04H
PCC = 30H
HALT (X1 oscillation, XT1 oscillation)
1.0
0.5
0.1
PCC = B0H
0.05
HALT (X1 stop, XT1 oscillation)
0.01
0.005
0.001
0
2
3
4
5
6
7
8
9
Supply Voltage VDD (V)
64
µPD78052Y, 78053Y, 78054Y, 78055Y, 78056Y, 78058Y
I
DD vs VDD (fx = 5.0 MHz, fxx = 2.5 MHz)
(TA = 25°C)
10.0
5.0
PCC = 00H
PCC = 01H
PCC = 02H
PCC = 03H
PCC = 04H
PCC = 30H
HALT (X1 oscillation, XT1 oscillation)
1.0
0.5
0.1
PCC = B0H
0.05
HALT (X1 Stop, XT1 oscillation)
0.01
0.005
0.001
0
2
3
4
5
6
7
8
9
Supply Voltage VDD (V)
65
µPD78052Y, 78053Y, 78054Y, 78055Y, 78056Y, 78058Y
13. PACKAGE DRAWING
80 PIN PLASTIC QFP (14×14)
A
B
60
61
41
40
detail of lead end
S
C
D
R
Q
80
1
21
20
F
J
M
G
P
H
I
K
L
M
N
NOTE
ITEM MILLIMETERS
INCHES
Each lead centerline is located within 0.13 mm (0.005 inch) of
its true position (T.P.) at maximum material condition.
A
B
17.20±0.20
14.00±0.20
0.677±0.008
+0.009
0.551
–0.008
+0.009
0.551
C
D
14.00±0.20
17.20±0.20
–0.008
0.677±0.008
F
0.825
0.825
0.032
0.032
G
+0.002
0.013
H
0.32±0.06
–0.003
I
0.13
0.005
J
K
0.65 (T.P.)
1.60±0.20
0.026 (T.P.)
0.063±0.008
+0.009
0.031
L
0.80±0.20
–0.008
+0.03
0.17
+0.001
0.007
M
–0.07
–0.003
N
P
Q
0.10
0.004
1.40±0.10
0.125±0.075
0.055±0.004
0.005±0.003
+7°
3°
+7°
3°
R
S
–3°
–3°
1.70 MAX.
0.067 MAX.
P80GC-65-8BT
Remark Dimensions and materials of ES product are the same as those of mass-production products.
66
µPD78052Y, 78053Y, 78054Y, 78055Y, 78056Y, 78058Y
14. RECOMMENDED SOLDERING CONDITIONS
This product should be soldered and mounted under the conditions recommended in the table below.
For a detailed description of recommended soldering conditions, refer to the information document Semiconduc-
tor Device Mounting Technology Manual (C10535E).
For soldering methods and conditions other than those recommended below, contact an NEC sales representative.
Table 14-1. Surface Mounting Type Soldering Conditions
µPD78052YGC-xxx-8BT : 80-pin plastic QFP (14 × 14 mm)
µPD78053YGC-xxx-8BT : 80-pin plastic QFP (14 × 14 mm)
µPD78054YGC-xxx-8BT : 80-pin plastic QFP (14 × 14 mm)
µPD78055YGC-xxx-8BT : 80-pin plastic QFP (14 × 14 mm)
µPD78056YGC-xxx-8BT : 80-pin plastic QFP (14 × 14 mm)
µPD78058YGC-xxx-8BT : 80-pin plastic QFP (14 × 14 mm)
Recommended
Soldering Method
Infrared reflow
Soldering Conditions
Condition Symbol
Package peak temperature: 235 °C, Duration: 30 sec. max. (at 210°C or above),
IR35-00-2
Number of times: Twice max.
VPS
Package peak temperature: 215 °C, Duration: 40 sec. max. (at 200°C or above),
VP15-00-2
WS60-00-1
—
Number of times: Twice max.
Wave soldering
Partial heating
Solder bath temperature : 260°C max., Duration : 10 sec. max., Number of times:
once, Preheating temperature : 120°C max. (package surface temperature)
Pin temperature: 300°C max. Duration: 3 sec. max. (per pin row)
Caution
Avoid as much as possible combining two or more soldering methods (except for the partial
heating method).
67
µPD78052Y, 78053Y, 78054Y, 78055Y, 78056Y, 78058Y
APPENDIX A. DEVELOPMENT TOOLS
The following development tools are available for system development using µPD78054Y subseries.
Language Processing Software
RA78K/0 Notes 1, 2, 3, 4
CC78K/0 Notes 1, 2, 3, 4
DF78054 Notes 1, 2, 3, 4
CC78K/0-L Notes 1, 2, 3, 4
78K/0 series common assembler package
78K/0 series common C compiler package
Device file common to µPD78054 subseries
78K/0 series common C compiler library source file
PROM Writing Tools
PG-1500
PROM programmer
PA-78P054GC
Programmer adapters connected to PG-1500
PA-78P054KK-T
PG-1500 controller Notes 1, 2
PG-1500 control program
Debugging Tools
IE-78000-R
In-circuit emulator common to 78K/0 series
IE-78000-R-A
In-circuit emulator common to 78K/0 series (for integrated debugger)
Break board common to 78K/0 series
IE-78000-R-BK
IE-780308-R-EM
IE-78000-R-SV3
IE-78000-98-IF-B
Emulation board common to µPD780308 subseries
Interface adapter and cable when using EWS for the host machine (for IE-78000-R-A)
Interface adapter when using the PC-9800 series (except for notebook computers) for the
host machine (for IE-78000-R-A)
IE-78000-98N-IF
IE-78000-PC-IF-B
Interface adapter and cable when using the PC-9800 series notebook computers for the host
machine (for IE-78000-R-A)
Interface adapter when using IBM/PC AT™ and its compatibles for the host machine
(for IE-78000-R-A)
EP-78230GC-R
EV-9200GC-80
Emulation probe common to µPD78234 subseries
Socket to be mounted in the target system board manufactured for 80-pin plastic QFP
(GC-8BT type)
Notes 5, 6, 7
SM78K0
System simulator common to 78K/0 series
Integrated debugger for IE-78000-R-A
Screen debugger for IE-78000-R
ID78K0 Notes 4, 5, 6, 7
SD78K/0 Notes 1, 2
Notes 1, 2, 4, 5, 6, 7
DF78054
Device file common to µPD78054 subseries
Notes 1. PC-9800 series (MS-DOSTM) based
2. IBM PC/AT and compatible computer (PC DOSTM/IBM DOSTM/MS-DOS) based
3. HP9000 series 300TM (HP-UXTM) based
4. HP9000 series 700TM (HP-UX) based, SPARCstationTM (Sun OSTM) based, EWS4800 series (EWS-UX/
V) based
5. PC-9800 series (MS-DOS + WindowsTM) based
6. IBM PC/AT and compatible computer (PC DOS/IBM DOS/MS-DOS + Windows) based
7. NEWSTM (NEWS-OSTM) based
68
µPD78052Y, 78053Y, 78054Y, 78055Y, 78056Y, 78058Y
Real-Time OS
RX78K/0 Notes 1, 2, 3, 4
MX78K0 Notes 1, 2, 3, 4
Real-time OS for 78K/0 series
OS for 78K/0 series
Fuzzy Inference Development Support System
Note 5
FE9000 Note 1/ FE9200
FT9080 Note 1/ FT9085
Fuzzy knowledge data creation tool
Note 2
Translator
Notes 1, 2
FI78K0
Fuzzy inference module
Fussy inference debugger
Notes 1, 2
FD78K0
Notes 1. PC-9800 series (MS-DOS) based
2. IBM PC/AT and its compatible computers (PC DOS/IBM DOS/MS-DOS) based
3. HP9000 series 300 (HP-UX) based
4. HP9000 series 700 (HP-UX) based, SPARCstation (Sun OS) based, EWS4800 series (EWS-UX/V) based
5. IBM PC/AT and its compatible computers (PC DOS/IBM DOS/MS-DOS + Windows) based
Remarks 1. For third party development tools, see the 78K/0 Series Selection Guide (U11126E).
2. RA78K/0, CC78K/0, SM78K0, ID78K0, SD78K/0, and RX78K/0 are used in combination with DF78054.
69
µPD78052Y, 78053Y, 78054Y, 78055Y, 78056Y, 78058Y
APPENDIX B. RELATED DOCUMENTS
Device Related Documents
Document No.
(English)
Document No.
(Japanese)
Document Name
µPD78052Y,78053Y, 78054Y, 78055Y, 78056Y, 78058Y Data Sheet
µPD78P058Y Data Sheet
This document
U10906J
U10907J
U11747J
U12326J
U10904J
U10903J
U10087J
U10182J
U10907E
µPD78054 and µPD78054Y Subseries User’s Manual
78K/0 Series User’s Manual Instructions
78K/0 Series Instruction Set
IEU-1356
U12326E
–
78K/0 Series Instruction Table
–
–
µPD78054Y Special Function Register Table
78K/0 Series Application Note
Basics (III)
U10182E
Development Tool Related Documents (User’s Manual)
Document Name
Document No.
(English)
Document No.
(Japanese)
RA78K Series Assembler Package
Operation
EEU-1399
EEU-1404
EEU-1402
U11802E
U11801E
U11789E
EEU-1280
EEU-1284
U11517E
U11518E
EEA-1208
U12322E
U11940E
EEU-1291
U10540E
U11376E
U10057E
EEU-1427
U11362E
EEU-1515
U10181E
U10092E
EEU-809
EEU-815
U12323J
U11802J
U11801J
U11789J
EEU-656
EEU-655
U11517J
U11518J
EEA-618
U12322J
U11940J
EEU-704
EEU-5008
U11376J
U10057J
EEU-867
U11362J
EEU-985
U10181J
U10092J
Language
RA78K Series Structured Assembler Preprocessor
CC78K0 C Assembler Package
Operation
Assembly Language
Structured Assembly Language
Operation
CC78K Series C Compiler
CC78K0 C Compiler
Language
Operation
Language
CC78K/0 C Compiler Application Note
CC78K Series Library Source File
PG-1500 PROM Programmer
PG-1500 Controller PC-9800 Series (MS-DOS) Based
PG-1500 Controller IBM PC Series (PC DOS) Based
IE-78000-R
Programming Know-How
IE-78000-R-A
IE-78000-R-BK
IE-780308-R-EM
EP-78230
SM78K0 System Simulator WIndows based
SM78K Series System Simulator
Reference
External Part User Open
Interface Specifications
SD78K/0 Screen Debugger
Introduction
Reference
Introduction
Reference
Reference
Reference
Guide
–
EEU-852
U10952J
EEU-5024
U11279J
U11151J
U11539J
U11649J
PC-9800 Series (MS-DOS) Based
–
SD78K/0 Screen Debugger
IBM PC/AT (PC DOS) Based
U10539E
U11279E
—
ID78K0 Integrated Debugger EWS based
ID78K0 Integrated Debugger PC based
ID78K0 Integrated Debugger Windows based
U11539E
U11649E
Caution
The above documents are subject to change without notice. For design purpose, etc., be sure
to use the latest document.
70
µPD78052Y, 78053Y, 78054Y, 78055Y, 78056Y, 78058Y
Embedded Software Documents (User’s Manual)
Document Name
Document No.
(English)
Document No.
(Japanese)
78K/0 Series Real Time OS
Basics
U11537E
U11536E
U12257E
EEU-1438
EEU-1444
EEU-1441
EEU-1458
U11537J
U11536J
U12257J
EEU-829
EEU-862
EEU-858
EEU-921
Installation
Basic
MX78K0: OS for 78K/0 Series
Fuzzy Knowledge Data Creation Tools
78K/0, 78K/II, 87AD Series Fuzzy Inference Development Support System Translator
78K/0 Series Fuzzy Inference Development Support System Fuzzy Inference Module
78K/0 Series Fuzzy Inference Development Support System Fuzzy Inference Debugger
Other Documents
Document No.
(English)
Document No.
(Japanese)
Document Name
IC Package Manual
C10943X
Semiconductor Device Mounting Technology Manual
Quality Grades on NEC Semiconductor Device
C10535E
C11531E
C10983E
C11892E
MEI-1202
–
C10535J
C11531J
C10983J
C11892J
C11893J
U11416J
NEC Semiconductor Device Reliability/Quality Control System
Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD)
Guide to Quality Assurance for Semiconductor Devices
Microcomputer-related Product Guide, Third Party Products
Caution
The above related documents are subject to change without notice. For design purpose, etc.,
be sure to use the latest documents.
71
µPD78052Y, 78053Y, 78054Y, 78055Y, 78056Y, 78058Y
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note: Strong electric field, when exposed to a MOS device, can cause destruction
of the gate oxide and ultimately degrade the device operation. Steps must
be taken to stop generation of static electricity as much as possible, and
quickly dissipate it once, when it has occurred. Environmental control must
be adequate. When it is dry, humidifier should be used. It is recommended
to avoid using insulators that easily build static electricity. Semiconductor
devices must be stored and transported in an anti-static container, static
shielding bag or conductive material. All test and measurement tools
including work bench and floor should be grounded. The operator should
be grounded using wrist strap. Semiconductor devices must not be touched
with bare hands. Similar precautions need to be taken for PW boards with
semiconductor devices on it.
2 HANDLING OF UNUSED INPUT PINS FOR CMOS
Note: No connection for CMOS device inputs can be cause of malfunction. If no
connection is provided to the input pins, it is possible that an internal input
level may be generated due to noise, etc., hence causing malfunction. CMOS
devices behave differently than Bipolar or NMOS devices. Input levels of
CMOS devices must be fixed high or low by using a pull-up or pull-down
circuitry. Each unused pin should be connected to VDD or GND with a
resistor, if it is considered to have a possibility of being an output pin. All
handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3 STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note: Power-on does not necessarily define initial status of MOS device. Production
process of MOS does not define the initial operation status of the device.
Immediately after the power source is turned ON, the devices with reset
function have not yet been initialized. Hence, power-on does not guarantee
out-pin levels, I/O settings or contents of registers. Device is not initialized
until the reset signal is received. Reset operation must be executed imme-
diately after power-on for devices having reset function.
72
µPD78052Y, 78053Y, 78054Y, 78055Y, 78056Y, 78058Y
Regional Information
Some information contained in this document may vary from country to country. Before using any NEC
product in your application, please contact the NEC office in your country to obtain a list of authorized
representatives and distributors. They will verify:
• Device availability
• Ordering information
• Product release schedule
• Availability of related technical literature
• Development environment specifications (for example, specifications for third-party tools and
components, host computers, power plugs, AC supply voltages, and so forth)
• Network requirements
In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary
from country to country.
NEC Electronics Inc. (U.S.)
Santa Clara, California
Tel: 800-366-9782
NEC Electronics Hong Kong Ltd.
Hong Kong
Tel: 2886-9318
NEC Electronics (Germany) GmbH
Benelux Office
Eindhoven, The Netherlands
Tel: 040-2445845
Fax: 800-729-9288
Fax: 2886-9022/9044
Fax: 040-2444580
NEC Electronics (Germany) GmbH
Duesseldorf, Germany
Tel: 0211-65 03 02
NEC Electronics Hong Kong Ltd.
Seoul Branch
Seoul, Korea
NEC Electronics (France) S.A.
Velizy-Villacoublay, France
Tel: 01-30-67 58 00
Fax: 0211-65 03 490
Tel: 02-528-0303
Fax: 02-528-4411
Fax: 01-30-67 58 99
NEC Electronics (UK) Ltd.
Milton Keynes, UK
Tel: 01908-691-133
NEC Electronics Singapore Pte. Ltd.
United Square, Singapore 1130
Tel: 253-8311
NEC Electronics (France) S.A.
Spain Office
Madrid, Spain
Fax: 01908-670-290
Fax: 250-3583
Tel: 01-504-2787
NEC Electronics Italiana s.r.1.
Milano, Italy
Tel: 02-66 75 41
Fax: 01-504-2860
NEC Electronics Taiwan Ltd.
Taipei, Taiwan
Tel: 02-719-2377
NEC Electronics (Germany) GmbH
Scandinavia Office
Fax: 02-66 75 42 99
Fax: 02-719-5951
Taeby, Sweden
Tel: 08-63 80 820
NEC do Brasil S.A.
Sao Paulo-SP, Brasil
Tel: 011-889-1680
Fax: 011-889-1689
Fax: 08-63 80 388
J96. 8
73
µPD78052Y, 78053Y, 78054Y, 78055Y, 78056Y, 78058Y
CAUTION
Purchase of NEC I2C components conveys a license under the Philips I2C Patent Rights to use these
components in an I2C system, provided that the system conforms to the I2C Standard Specification
as defined by Philips.
FIP and IEBus are trademarks of NEC Corporation.
MS-DOS and Windows are either registered trademarks or trademarks of Microsoft Corporation in the
United States and/or other countries.
IBM DOS, PC/AT, and PC DOS are trademarks of International Business Machines Corporation.
HP9000 series 300, HP9000 series 700, and HP-UX are trademarks of Hewlett-Packard Company.
SPARCstation is a trademark of SPARC International, Inc.
SunOS is a trademark of Sun Microsystems, Inc.
NEWS and NEWS-OS are trademarks of SONY Corporation.
The export of this product from Japan is regulated by the Japanese government. To export this product may be prohibited
without governmental licence, the need for which must be judged by the customer. The export or re-
export of this product from a country other than Japan may also be prohibited without a licence from the country.
Please call an NEC sales representative.
No part of this document may be copied or reproduced in any form or by any means without the prior written
consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in
this document.
NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property
rights of third parties by or arising from use of a device described herein or any other liability arising from use
of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other
intellectual property rights of NEC Corporation or others.
While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,
the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or
property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety
measures in its design, such as redundancy, fire-containment, and anti-failure features.
NEC devices are classified into the following three quality grades:
"Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a
customer designated "quality assurance program" for a specific application. The recommended applications of
a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device
before using it in a particular application.
Standard: Computers, office equipment, communications equipment, test and measurement equipment,
audio and visual equipment, home electronic appliances, machine tools, personal electronic
equipment and industrial robots
Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems or medical equipment for life support, etc.
The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books.
If customers intend to use NEC devices for applications other than those specified for Standard quality grade,
they should contact an NEC sales representative in advance.
Anti-radioactive design is not implemented in this product.
M4 96.5
相关型号：
UPD78054GC-XXX-3B9
Microcontroller, 8-Bit, MROM, 5MHz, CMOS, PQFP80, 14 X 14 MM, 2.70 MM HEIGHT, PLASTIC, QFP-80
NEC
UPD78054GK-XXX-BE9
Microcontroller, 8-Bit, MROM, MOS, PQFP80, 12 X 12 MM, FINE PITCH, PLASTIC, TQFP-80
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