UPD78070A [RENESAS]
8-BIT SINGLE-CHIP MICROCONTROLLER; 8位单芯片微控制器
| 型号： | UPD78070A |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | 8-BIT SINGLE-CHIP MICROCONTROLLER |
| 文件： | 总58页 (文件大小：410K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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Old Company Name in Catalogs and Other Documents
On April 1st, 2010, NEC Electronics Corporation merged with Renesas Technology
Corporation, and Renesas Electronics Corporation took over all the business of both
companies. Therefore, although the old company name remains in this document, it is a valid
Renesas Electronics document. We appreciate your understanding.
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April 1st, 2010
Renesas Electronics Corporation
Issued by: Renesas Electronics Corporation (http://www.renesas.com)
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DATA SHEET
MOS INTEGRATED CIRCUIT
µPD78P083
8-BIT SINGLE-CHIP MICROCONTROLLER
DESCRIPTION
The µPD78P083 is a member of the µPD78083 subseries of the 78K/0 series products. It includes an on-chip, 24-Kbyte,
one-time PROM or EPROM.
Because this device can be programmed by users, it is ideally suited for applications involving the evaluation of systems
in development stages, small-scale production of many different products, and rapid development and time-to-market of
a new product.
Caution
The µPD78P083DU does not maintain planned reliability when used in your systems’ mass-produced
products. Please use only experimentally or for evaluation purposes during trial manufacture.
The details of functions are described in the user’s manuals. Be sure to read the following manuals before
designing.
µPD78083 Subseries User's Manual
: IEU-1407
78K/0 Series User's Manual — Instructions : IEU-1372
FEATURES
• Pin-compatible with mask ROM version (except VPP pin)
Note
• Internal PROM: 24 Kbytes
• µPD78P083DU: Reprogrammable (ideally suited for system evaluation)
• µPD78P083CU, µPD78P083GB: One-time programmable (ideally suited for small-scale production)
Note
• Internal high-speed RAM: 512 bytes
• Can be operated in the same supply voltage as the mask ROM version (VDD = 1.8 to 5.5 V)
• Corresponding to QTOPTM Microcontrollers
Note The internal PROM and internal high-speed RAM capacities can be changed by setting the internal memory size
switching register (IMS).
Remark
QTOP microcontroller is a general term for microcontrollers which incorporate one-time PROM and are totally
supported by NEC's programming service (from programming to marking, screening and verification).
*
Differs from the mask ROM version in the following points
The same memory mapping as the mask ROM version is enabled by setting the internal memory size switching
register (IMS).
In this document, the term PROM is used in parts common to one-time PROM versions and EPROM versions.
The information in this document is subject to change without notice.
Document No. U11006EJ1V0DS00 (1st edition)
(Previous No. IP-3556)
Date Published June 1996 P
The mark
shows major revised points.
*
Printed in Japan
1995
©
µPD78P083
ORDERING INFORMATION
Part Number
Package
Internal ROM
µPD78P083CU
42-pin plastic shrink DIP (600 mil)
44-pin plastic QFP (10 x 10 mm)
44-pin plastic QFP (10 x 10 mm)
42-pin ceramic shrink DIP
One-Time PROM
One-Time PROM
One-Time PROM
EPROM
µPD78P083GB-3B4
µPD78P083GB-3BS-MTX
µPD78P083DU
*
(with window) (600 mil)
Caution
µPD78P083GB has two kinds of package. (Refer to 9. PACKAGE DRAWINGS). Please refer an
NEC’s sales representative for the available package.
QUALITY GRADE
Part Number
Package
Quality Grades
µPD78P083CU
42-pin plastic shrink DIP (600 mil)
44-pin plastic QFP (10 x 10 mm)
44-pin plastic QFP (10 x 10 mm)
42-pin ceramic shrink DIP
Standard
µPD78P083GB-3B4
µPD78P083GB-3BS-MTX
µPD78P083DU
Standard
Standard
Not applicable
(with window) (600 mil)
Please refer to “Quality grades on NEC Semiconductor Devices” (Document number IEI-1209) published by NEC
Corporation to know the specification of quality grade on the devices and its recommended applications.
2
µPD78P083
78K/0 SERIES DEVELOPMENT
The following shows the 78K/0 series products development. Subseries names are shown inside frames.
Products in mass production
Products under development
Y subseries products are compatible with I2C bus.
Control
A timer was added to the µPD78054 and external interface function was enhanced
µPD78078
µPD78078Y
100-pin
100-pin
80-pin
80-pin
64-pin
64-pin
64-pin
64-pin
42/44-pin
µPD78070A
µPD78058F
µPD78054
µPD78018F
µPD78014
µPD780001
µPD78002
µPD78083
µPD78070AY
µPD78058FY
µPD78054Y
µPD78018FY
µPD78014Y
ROM-less versions of the µPD78078
EMI noise reduced product of the µPD78054
UART and D/A converter were added to the µPD78014 and I/O was enhanced
Low-voltage (1.8 V) operation versions of the µPD78014 with several ROM and RAM
capacities are available.
An A/D converter and 16-bit timer were added to the µPD78002
An A/D converter was added to the µPD78002
µPD78002Y
Basic subseries for control
On-chip UART, capable of operating at a low voltage (1.8 V)
FIPTM drive
µPD780208
µPD78044A
µPD78024
The I/O and FIP C/D of the µPD78044A were enhanced. Display output total: 53
A 6-bit U/D counter was added to the µPD78024. Display output total: 34
Basic subseries for driving FIP. Display output total: 26
100-pin
80-pin
64-pin
78K/0
Series
LCD drive
The enhanced SIO to the µPD78064 and increased ROM and RAM capacities
µPD780308Y
µPD78064Y
100-pin
100-pin
100-pin
µPD780308
µPD78064B
µPD78064
EMI noise reduced product of the µPD78064
Subseries for driving LCDs, On-chip UART
IEBusTM supported
µPD78098
80-pin
64-pin
The IEBus controller was added to the µPD78054
LV control
On-chip PWM, LV digital code decoder, and Hsync counter
µPD78P0914
3
µPD78P083
The following table shows the differences among subseries functions.
Function ROM
Capacity
32 K to 60 K 4ch 1ch 1ch 1ch 8ch 2ch 3ch (UART: 1ch) 88
Timer
8-bit 8-bit Serial Interface
I/O VDD MIN. External
Part Number
Control
8-bit 16-bit Watch WDT A/D D/A
Value
1.8 V
2.7 V
Expansion
Available
µPD78078
µPD78070A
–
61
69
µPD78058F 48 K to 60 K 2ch
µPD78054 16 K to 60 K
µPD78018F 8 K to 60 K
µPD78014 8 K to 32 K
µPD780001 8 K
2.0 V
1.8 V
2.7 V
–
2ch
1ch
53
–
–
1ch
–
39
53
–
µPD78002
µPD78083
8 K to 16 K
–
Available
8ch
1ch (UART: 1ch) 33
1.8 V
2.7 V
–
–
FIP drive
µPD780208 32 K to 60 K 2ch 1ch 1ch 1ch 8ch
µPD78044A 16 K to 40 K
–
–
2ch
74
68
54
µPD78024
24 K to 32 K
LCD drive
µPD780308 48 K to 60 K 2ch 1ch 1ch 1ch 8ch
µPD78064B 32 K
3ch (UART: 1ch) 57
2ch (UART: 1ch)
1.8 V
2.0 V
–
µPD78064
µPD78098
16 K to 32 K
32 K to 60 K 2ch 1ch 1ch 1ch 8ch 2ch 3ch (UART: 1ch) 69
IEBus
2.7 V
4.5 V
Available
Available
supported
LV control
µPD78P0914 32 K
6ch
–
–
1ch 8ch
–
2ch
54
4
µPD78P083
FUNCTION DESCRIPTION
Item
Function
Note
Internal memory
• PROM: 24 Kbytes
• RAM
Internal high-speed RAM: 512 bytes Note
Memory space
General register
Instruction cycles
64 Kbytes
8 bits x 32 registers (8 bits x 8 registers x 4 banks)
Instruction execution time variable function is integrated.
0.4 µs/0.8 µs/1.6 µs/3.2 µs/6.4 µs/12.8 µs (@5.0-MHz operation with main system clock)
• 16-bit operation
Instruction set
• Multiply/divide (8 bits x 8 bits, 16 bits ÷ 8 bits)
• Bit manipulation (set, reset, test, Boolean operation)
• BCD adjust, etc.
I/O ports
Total
• CMOS input
• CMOS input/output
:
:
:
33
1
32
A/D converter
Serial interface
Timer
• 8-bit resolution x 8 channels
• 3-wire serial I/O/UART mode selectable: 1 channel
• 8-bit timer/event counter: 2 channels
• Watchdog timer: 1 channel
Timer output
Clock output
2 pins (8-bit PWM output enable)
19.5 kHz, 39.1 kHz, 78.1 kHz, 156 kHz, 313 kHz, 625 kHz, 1.25 MHz, 2.5 MHz, and
5.0 MHz (@ 5.0-MHz operation with main system clock)
1.2 kHz, 2.4 kHz, 4.9 kHz, and 9.8 kHz
Buzzer output
(@ 5.0-MHz operation with main system clock)
Vectored
interrupts
Maskable interrupts Internal
Non-maskable interrupt Internal
Software interrupt Internal
:
:
:
8
1
1
external
:
3
Power supply voltage
Operating ambient temperature
Packages
VDD = 1.8 to 5.5 V
TA = –40 to +85°C
• 42-pin plastic shrink DIP (600 mil)
• 44-pin plastic QFP (10 x 10 mm)
• 42-pin ceramic shrink DIP (with window) (600 mil)
Note
Internal PROM and high-speed RAM capacities can be changed by setting the internal memory size switching
register (IMS).
5
µPD78P083
PIN CONFIGURATIONS (Top View)
(1) Normal operating mode
• 42-pin plastic shrink DIP (600 mil) µPD78P083CU
• 42-pin ceramic shrink DIP (with window) (600 mil) µPD78P083DU
P55
P56
1
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
V
SS
2
P54
P57
3
P53
P30
4
P52
P31
5
P51
P32
6
P50
P33
7
P100/TI5/TO5
P101/TI6/TO6
P34
8
P35/PCL
P36/BUZ
P37
9
P70/R
X
D/SI2
10
11
12
13
14
15
16
17
18
19
P71/T
XD/SO2
P72/ASCK/SCK2
P17/ANI7
P16/ANI6
P15/ANI5
P14/ANI4
P13/ANI3
P12/ANI2
P11/ANI1
P10/ANI0
P00
P01/INTP1
P02/INTP2
P03/INTP3
RESET
VPP
X2
X1
V
DD
20
21
23
22
AVSS
AVDD
AVREF
Cautions 1. Connect VPP pin directly to VSS.
2. Connect AVDD pin to VDD.
3. Connect AVSS pin to VSS.
6
µPD78P083
• 44-pin plastic QFP (10 x 10 mm)
µPD78P083GB-3B4, µPD78P083GB-3BS-MTX
44 43 42 41 40 39 38 37 36 35 34
33
P12/ANI2
P13/ANI3
1
P03/INTP3
P02/INTP2
P01/INTP1
P00
2
32
31
30
29
28
27
26
25
24
23
P14/ANI4
3
P15/ANI5
4
P16/ANI6
5
P37
P17/ANI7
6
P36/BUZ
P35/PCL
P34
P72/ASCK/SCK2
7
P71/T
X
D/SO2
D/SI2
8
P70/R
X
9
P33
P101/TI6/TO6
P100/TI5/TO5
10
P32
11
NC
12 13 14 15 16 17 18 19 20 21 22
Cautions 1. Connect VPP pin directly to VSS.
2. Connect AVDD pin to VDD.
3. Connect AVSS pin to VSS.
4. Connect NC pin to VSS for noise protection (It can be left open).
7
µPD78P083
P00 to P03
P10 to P17
P30 to P37
P50 to P57
P70 to P72
P100, P101
INTP1 to INTP3
TI5, TI6
: Port 0
PCL
: Programmable Clock
: Port 1
BUZ
: Buzzer Clock
: Port 3
X1, X2
RESET
ANI0-ANI7
AVDD
AVSS
AVREF
VDD
: Crystal (Main System Clock)
: Reset
: Port 5
: Port 7
: Analog Input
: Port 10
: Analog Power Supply
: Analog Ground
: Interrupt from Peripherals
: Timer Input
: Timer Output
: Serial Input
: Serial Output
: Serial Clock
: Receive Data
: Transmit Data
: Asynchronous Serial Clock
: Analog Reference Voltage
: Power Supply
TO5, TO6
SI2
VPP
: Programming Power Supply
: Ground
SO2
VSS
SCK2
NC
: Non-connection
RxD
TxD
ASCK
8
µPD78P083
(2) PROM programming mode
• 42-pin plastic shrink DIP (600 mil) µPD78P083CU
• 42-pin ceramic shrink DIP (with window) (600 mil) µPD78P083DU
A5
A6
1
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
V
SS
2
A4
A7
3
A3
OE
CE
4
A2
5
A1
PGM
A8
6
A0
7
A10
A11
A12
A13
A14
D7
D6
D5
D4
D3
D2
D1
D0
8
9
(L)
10
11
12
13
14
15
16
17
18
19
A9
(L)
RESET
VPP
Open
(L)
V
DD
DD
20
21
23
22
V
SS
SS
V
V
Cautions 1. (L):
2. VSS:
Individually connect to VSS via a pull-down resistor.
Connect to GND.
3. RESET: Set to low level.
4. Open:
Leave open.
9
µPD78P083
• 44-pin plastic QFP (10 x 10 mm)
µPD78P083GB-3B4, µPD78P083GB-3BS-MTX
44 43 42 41 40 39 38 37 36 35 34
33
D2
D3
1
2
32
31
30
29
28
27
26
25
24
23
(L)
(L)
D4
3
D5
4
A9
A8
D6
5
D7
6
A14
A13
A12
A11
A10
7
8
9
10
PGM
(L)
11
12 13 14 15 16 17 18 19 20 21 22
Cautions 1. (L):
2. VSS:
Individually connect to VSS via a pull-down resistor.
Connect to GND.
3. RESET: Set to low level.
4. Open: Leave open.
A0 to A14
: Address Bus
: Data Bus
RESET
VDD
: Reset
: Power Supply
D0 to D7
CE
: Chip Enable
: Output Enable
: Program
VPP
: Programming Power Supply
: Ground
OE
VSS
PGM
10
µPD78P083
BLOCK DIAGRAM
P100/TI5/TO5
P00
8-bit TIMER/
EVENT COUNTER 5
PORT 0
PORT 1
PORT 3
PORT 5
P01-P03
8-bit TIMER/
EVENT COUNTER 6
P101/TI6/TO6
P10-P17
P30-P37
78K/0
CPU
CORE
WATCHDOG
TIMER
PROM
(24 KBytes)
SI2/R
X
D/P70
D/P71
SERIAL
INTERFACE 2
SO2/T
X
P50-P57
P70-P72
SCK2/ASCK/P72
ANI0/P10-
ANI7/P17
A/D
CONVERTER
AVDD
AVSS
PORT 7
AVREF
DATA
MEMORY
(512 Bytes)
INTP1/P01-
INTP3/P03
PORT 10
P100, P101
INTERRUPT
CONTROL
BUZZER OUTPUT
BUZ/P36
PCL/P35
RESET
X1
SYSTEM
CONTROL
CLOCK OUTPUT
CONTROL
X2
VDD
VSS
VPP
11
µPD78P083
CONTENTS
1.
2.
DIFFERENCES BETWEEN THE µPD78P083 AND MASK ROM VERSIONS ··· 13
PIN FUNCTIONS ··· 14
2.1 Pins in Normal Operating Mode ··· 14
2.2 Pins in PROM Programming Mode ··· 16
2.3 Pin Input/Output Circuits and Recommended Connection of Unused Pins ··· 16
3.
4.
INTERNAL MEMORY SIZE SWITCHING REGISTER (IMS) ··· 18
PROM PROGRAMMING ··· 19
4.1 Operating Modes ··· 19
4.2 PROM Write Procedure ··· 21
4.3 PROM Read Procedure ··· 25
5.
6.
7.
8.
9.
PROGRAM ERASURE (µPD78P083DU ONLY) ··· 26
OPAQUE FILM ON ERASURE WINDOW (µPD78P083DU ONLY) ··· 26
ONE-TIME PROM VERSION SCREENING ··· 26
ELECTRICAL SPECIFICATIONS ··· 27
*
*
PACKAGE DRAWINGS ··· 45
10. RECOMMENDED SOLDERING CONDITIONS ··· 49
APPENDIX A. DEVELOPMENT TOOLS ··· 50
APPENDIX B. RELATED DOCUMENTS ··· 52
12
µPD78P083
1. DIFFERENCES BETWEEN THE µPD78P083 AND MASK ROM VERSIONS
The µPD78P083 is a single-chip microcontroller with an on-chip one-time PROM or with an on-chip EPROM which has
program write, erasure and rewrite capability.
Setting the internal memory size switching register (IMS) makes the functions except the PROM specification identical
to the mask ROM versions, that is, the µPD78081 and µPD78082.
Differences between the µPD78P083 and mask ROM versions are shown in Table 1-1.
Table 1-1. Differences between the µPD78P083 and Mask ROM Versions
Parameter
µPD78P083
One-time PROM/EPROM
24 Kbytes
Mask ROM Versions
Mask ROM
ROM type
ROM capacity
µPD78081
µPD78082
µPD78081
µPD78082
:
:
:
:
8 Kbytes
16 Kbytes
256 bytes
384 bytes
Internal high-speed RAM capacity
512 bytes
Note
Internal ROM and internal high-speed
RAM capacity change by internal
memory size switching register
IC pin
Can be changed
Can not be changed
No
Yes
No
VPP pin
Yes
Electrical specifications
Refer to a data sheet of each product
Note
The internal PROM becomes 24 Kbytes and the internal expansion RAM becomes 512 bytes by the RESET input.
13
µPD78P083
2. PIN FUNCTIONS
2.1 Pins in Normal Operating Mode
(1) Port pins
Pin Name
P00
Input/Output
Input
Function
Input only
After Reset
Input
Alternate Function
Port 0
—
INTP1
P01
P02
P03
Input/output
Input/output
Input/output
Input/output
4-bit input/output port
Input/output is specifiable
bit-wise. When used as the
input port, it is possible to
connect a pull-up resistor by
software.
Input
INTP2
INTP3
P10-P17
Port 1
Input
Input
Input
ANI0-ANI7
8-bit input/output port
Input/output is specifiable bit-wise.
When used as the input port, it is possible to connect
Note
a pull-up resistor by software.
P30-P34
P35
Port 3
—
PCL
8-bit input/output port
P36
Input/output is specifiable bit-wise.
When used as the input port, it is possible to connect
a pull-up resistor by software.
Port 5
BUZ
P37
—
P50-P57
—
8-bit input/output port
Can drive up to seven LEDs directly.
Input/output is specifiable bit-wise.
When used as the input port, it is possible to connect
a pull-up resistor by software.
Port 7
P70
P71
P72
Input/output
Input/output
Input
Input
SI2/RxD
3-bit input/output port
SO2/TxD
SCK2/ASCK
Input/output is specifiable bit-wise.
When used as the input port, it is possible to connect
a pull-up resistor by software.
Port 10
P100
P101
TI5/TO5
TI6/TO6
2-bit input/output port
Input/output is specifiable bit-wise.
When used as the input port, it is possible to connect
a pull-up resistor by software.
Note
When P10/ANI0-P17/ANI7 pins are used as the analog inputs for the A/D converter, set the port 1 to the input mode.
The on-chip pull-up resistor is automatically disabled.
14
µPD78P083
(2) Non-port pins
Pin Name
INTP1
Input/Output
Function
After Reset
Alternate Function
Input
External interrupt input by which the active edge (rising edge, Input
falling edge, or both rising and falling edges) can be specified.
P01
INTP2
INTP3
SI2
P02
P03
Input
Serial interface serial data input.
Serial interface serial data output.
Input
Input
Input
Input
Input
Input
Input
P70/RxD
SO2
SCK2
RxD
Output
P71/TxD
Input/Output Serial interface serial clock input/output.
P72/ASCK
Input
Output
Input
Input
Asynchronous serial interface serial data input.
Asynchronous serial interface serial data output.
Asynchronous serial interface serial clock input.
External count clock input to 8-bit timer (TM5).
External count clock input to 8-bit timer (TM6).
8-bit timer output.
P70/SI2
TxD
P71/SO2
ASCK
TI5
P72/SCK2
P100/TO5
TI6
P101/TO6
TO5
Output
Input
P100/TI5
TO6
P101/TI6
PCL
Output
Output
Input
Clock output. (for main system clock trimming)
Buzzer output.
Input
Input
Input
P35
BUZ
ANI0-ANI7
AVREF
AVDD
AVSS
RESET
X1
P36
A/D converter analog input.
P10-P17
Input
A/D converter reference voltage input.
A/D converter analog power supply. Connected to VDD.
A/D converter ground potential. Connected to VSS.
System reset input.
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Input
Input
Main system clock oscillation crystal connection.
X2
–
–
–
VDD
Positive power supply.
VPP
High-voltage applied during program write/verification.
Connected directly to VSS in normal operating mode.
Ground potential.
VSS
–
–
–
–
–
–
NC
Does not internally connected. Connect to VSS.
(It can be left open)
15
µPD78P083
2.2 Pins in PROM Programming Mode
Pin Name
RESET
Input/Output Function
Input
PROM programming mode setting
When +5 V or +12.5 V is applied to the VPP pin and a low-level signal is applied to the RESET pin,
this chip is set in the PROM programming mode.
VPP
Input
Input
Input/output
Input
Input
Input
—
PROM programming mode setting and high-voltage applied during program write/verification.
A0-A14
D0-D7
CE
Address bus
Data bus
PROM enable input/program pulse input
Read strobe input to PROM
Program/program inhibit input in PROM programming mode.
Positive power supply
OE
PGM
VDD
VSS
—
Ground potential
2.3 Pin Input/Output Circuits and Recommended Connection of Unused Pins
Types of input/output circuits of the pins and recommeded connection of unused pins are shown in Table 2-1.
For the configuration of each type of input/output circuit, see Figure 2-1.
Table 2-1. Type of Input/Output Circuit of Each Pin
Pin Name
Input/Output
Circuit Type
Input/Output
Recommended Connection for Unused Pins
P00
2
Input
Connect to VSS.
P01/INTP1
P02/INTP2
P03/INTP3
P10/ANI0-P17/ANI7
P30-P32
8-A
Input/Output
Input/Output
Independently connect to VSS via a resistor.
11
Independently connect to VDD or VSS via
a resistor.
5-A
8-A
5-A
P33, P34
P35/PCL
P36/BUZ
P37
P50-P57
5-A
8-A
5-A
8-A
8-A
P70/SI2/RxD
P71/SO2/TxD
P72/SCK2/ASCK
P100/TI5/TO5
P101/TI6/TO6
RESET
2
Input
–
–
Connect to VSS.
AVREF
–
AVDD
Connect to VDD.
AVSS
Connect to VSS.
VPP
Connect directly to VSS.
Connect to VSS (can leave open)
NC
16
µPD78P083
Figure 2-1. Types of Pin Input/Output Circuits
Type 2
Type 8-A
VDD
pull-up
enable
P-ch
IN
V
DD
data
P-ch
IN/OUT
output
disable
N-ch
Schmitt-triggered input with hysteresis characteristics
VDD
Type 5-A
V
DD
Type 11
pull-up
enable
pull-up
enable
P-ch
P-ch
V
DD
V
DD
data
P-ch
IN/OUT
data
P-ch
output
disable
N-ch
IN/OUT
P-ch
output
disable
N-ch
Comparator
+
–
N-ch
REF (threshold voltage)
V
input
enable
input
enable
17
µPD78P083
3. INTERNAL MEMORY SIZE SWITCHING REGISTER (IMS)
This is a register to disable use of part of internal memories by software. By setting this internal memory size switching
register (IMS), it is possible to get the same memory mapping as that of the mask ROM versions with a different internal
memory (ROM, RAM).
IMS is set with an 8-bit memory manipulation instruction.
RESET input sets IMS to 46H.
Figure 3-1. Internal Memory Size Switching Register Format
Symbol
IMS
R/W
R/W
7
6
5
4
0
3
2
1
0
Address
FFF0H
After Reset
46H
RAM2 RAM1 RAM0
ROM3 ROM2 ROM1
ROM0
Selection of Internal
ROM Capacity
ROM3 ROM2 ROM1 ROM0
0
0
0
0
1
1
1
0
1
0
0
0
8 Kbytes
16 Kbytes
24 Kbytes
Other than above
Setting prohibited
RAM2 RAM1 RAM0 Selection of Internal
High-Speed RAM Capacity
0
0
1
1
1
0
0
1
0
512 bytes
384 bytes
256 bytes
Other than above
Setting prohibited
Table 3-1 shows the setting values of IMS which make the memory mapping the same as that of the mask ROM version.
Table 3-1. Internal Memory Size Switching Register Setting Values
Target Mask ROM Versions
µPD78081
IMS Setting Value
82H
64H
µPD78082
18
µPD78P083
4. PROM PROGRAMMING
The µPD78P083 has an internal 24-Kbyte PROM as a program memory. For programming, set the PROM programming
mode with the VPP and RESET pins. For the connection of unused pins, refer to “PIN CONFIGURATIONS (TOP VIEW)
(2) PROM programming mode.”
Caution
Programs must be written in addresses 0000H to 5FFFH (The last address 5FFFH must be specified).
They cannot be written by a PROM programmer which cannot specify the write address.
4.1 Operating Modes
When +5 V or +12.5 V is applied to the VPP pin and a low-level signal is applied to the RESET pin, the PROM programming
mode is set. This mode will become the operating mode as shown in Table 4-1 when the CE, OE, and PGM pins are set
as shown.
Further, when the read mode is set, it is possible to read the contents of the PROM.
Table 4-1. Operating Modes of PROM Programming
Pin
RESET
L
VPP
VDD
CE
OE
PGM
D0 to D7
Operating Mode
Page data latch
Page write
+12.5 V
+6.5 V
H
H
L
L
x
L
H
L
Data input
H
H
L
High-impedance
Data input
Byte write
L
Program verify
Program inhibit
H
H
L
Data output
H
L
High-impedance
x
Read
+5 V
+5 V
L
L
H
L
H
x
Data output
Output disable
Standby
H
x
High-impedance
High-impedance
x
x : L or H
19
µPD78P083
(1) Read mode
Read mode is set if CE = L, OE = L is set.
(2) Output disable mode
Data output becomes high-impedance, and is in the output disable mode, if OE = H is set.
Therefore, it allows data to be read from any device by controlling the OE pin, if multiple µPD78P083s are connected
to the data bus.
(3) Standby mode
Standby mode is set if CE = H is set.
In this mode, data outputs become high-impedance irrespective of the OE status.
(4) Page data latch mode
Page data latch mode is set if CE = H, PGM = H, OE = L are set at the beginning of page write mode.
In this mode, 1 page 4-byte data is latched in an internal address/data latch circuit.
(5) Page write mode
After 1 page 4 bytes of addresses and data are latched in the page data latch mode, a page write is executed by applying
a 0.1-ms program pulse (active low) to the PGM pin with CE = H, OE = H. Then, program verification can be performed,
if CE = L, OE = L are set.
If programming is not performed by a one-time program pulse, X times (X ≤ 10) write and verification operations should
be executed repeatedly.
(6) Byte write mode
Byte write is executed when a 0.1-ms program pulse (active low) is applied to the PGM pin with CE = L, OE = H. Then,
program verification can be performed if OE = L is set.
If programming is not performed by a one-time program pulse, X times (X ≤ 10) write and verification operations should
be executed repeatedly.
(7) Program verify mode
Program verify mode is set if CE = L, PGM = H, OE = L are set.
In this mode, check if a write operation is performed correctly after the write.
(8) Program inhibit mode
Program inhibit mode is used when the OE pin, VPP pin, and D0-D7 pins of multiple µPD78P083s are connected in
parallel and a write is performed to one of those devices.
When a write operation is performed, the page write mode or byte write mode described above is used. At this time,
a write is not performed to a device which has the PGM pin driven high.
20
µPD78P083
4.2 PROM Write Procedure
Figure 4-1. Page Program Mode Flow Chart
Start
Address = G
V
DD = +6.5 V, VPP = +12.5 V
X = 0
Latch
Address = Address + 1
Latch
Address = Address + 1
Latch
Address = Address + 1
Latch
Address = Address + 1
No
X = X + 1
Yes
X = 10 ?
0.1-ms program pulse
Fail
Verify 4 bytes
Pass
No
Address = N ?
Yes
V
DD = 4.5 to 5.5 V, VPP = VDD
Pass
Fail
Verify all bytes
All Pass
Write end
Defective product
G = Start address
N = Program last address
21
µPD78P083
Figure 4-2. Page Program Mode Timing
Page Data Latch
Page Program
Program Verify
A2-A14
A0, A1
D0-D7
Data Input
Data Output
V
V
V
PP
V
V
PP
DD
DD + 1.5
DD
V
DD
IH
V
CE
V
IL
VIH
VIL
VIH
VIL
PGM
OE
22
µPD78P083
Figure 4-3. Byte Program Mode Flow Chart
Start
Address = G
V
DD = +6.5 V, VPP = +12.5 V
X = 0
X = X + 1
No
Yes
X = 10 ?
0.1-ms program pulse
Address = Address + 1
Fail
Verify
Pass
No
Address = N ?
Yes
V
DD = 4.5 to 5.5 V, VPP = VDD
Pass
Fail
Verify all bytes
All Pass
Write end
Defective product
G = Start address
N = Program last address
23
µPD78P083
Figure 4-4. Byte Program Mode Timing
Program
Program Verify
A0-A14
D0-D7
Data Input
Data Output
VPP
VPP
VDD
VDD + 1.5
VDD
VDD
VIH
CE
PGM
OE
VIL
VIH
VIL
VIH
VIL
Cautions 1. VDD should be applied before VPP and removed after VPP.
2. VPP must not exceed +13.5 V including overshoot.
3. Reliability may be adversely affected if removal/reinsertion is performed while +12.5 V is being
applied to VPP.
24
µPD78P083
4.3 PROM Read Procedure
The contents of PROM are readable to the external data bus (D0-D7) according to the read procedure shown below.
(1) Fix the RESET pin at low level, supply +5 V to the VPP pin, and connect all other unused pins as shown in “PIN
CONFIGURATIONS (TOP VIEW) (2) PROM programming mode”.
(2) Supply +5 V to the VDD and VPP pins.
(3) Input address of read data into the A0-A16 pins.
(4) Read mode
(5) Output data to D0-D7 pins.
The timings of the above steps (2) to (5) are shown in Figure 4-5.
Figure 4-5. PROM Read Timings
A0-A14
Address Input
CE (Input)
OE (Input)
D0-D7
Hi-Z
Hi-Z
Data Output
25
µPD78P083
5. PROGRAM ERASURE (µPD78P083DU ONLY)
*
The µPD78P083DU is capable of erasing (FFH) the data written in a program memory and rewriting.
To erase the programmed data, expose the erasure window to light having a wavelength shorter than about 400 nm.
Normally, irradiate ultraviolet rays of 254-nm wavelength. The amount of exposure required to completely erase the
programmed data is as follows:
•
•
UV intensity x erasing time
: 30 W•s/cm2 or more
Erasure time: 40 min. or more (When a UV lamp of 12,000 µW/cm2 is used. However, a longer time may be needed
because of deterioration in performance of the UV lamp, soiled erasure window, etc.)
When erasing the contents of data, set up the UV lamp within 2.5 cm from the erasure window. Further, if a filter is provided
for a UV lamp, irradiate the ultraviolet rays after removing the filter.
6. OPAQUE FILM ON ERASURE WINDOW (µPD78P083DU ONLY)
To protect from unintentional erasure by rays other than that of the lamp for erasing EPROM contents, or to protect internal
circuit other than EPROM from misoperating by rays, cover the erasure window with an opaque film when EPROM contents
erasure is not performed.
7. ONE-TIME PROM VERSION SCREENING
The one-time PROM version (µPD78P083CU, 78P083GB-3B4, 78P083GB-3BS-MTX) cannot be tested completely by
NEC before it is shipped, because of its structure. It is recommended to perform screening to verify PROM after writing
necessary data and performing high-temperature storage under the condition below.
Storage Temperature
Storage Time
24 hours
125°C
NEC offers for an additional fee one-time PROM writing to marking, screening, and verify for products designated as
"QTOP Microcontroller". Please contact an NEC sales representative for details.
*
26
µPD78P083
8. ELECTRICAL SPECIFICATIONS
*
Absolute Maximum Ratings (TA = 25°C)
Parameter
Symbol Test Conditions
Ratings
–0.3 to +7.0
Unit
V
Supply voltage
VDD
VPP
AVDD
AVREF
AVSS
VI1
–0.3 to +13.5
V
–0.3 to VDD + 0.3
–0.3 to VDD + 0.3
–0.3 to +0.3
V
V
V
Input voltage
–0.3 to VDD + 0.3
PROM programming mode –0.3 to +13.5
–0.3 to VDD + 0.3
Analog input pins
–10
V
VI2
A9
V
Output voltage
VO
V
Analog input voltage
Output current, high
VAN
IOH
P10-P17
Per pin
AVSS – 0.3 to AVREF + 0.3
V
mA
mA
Total for P10-P17, P50-P54, P70-P72,
P100, P101
–15
Total for P01-P03, P30-P37, P55-P57
–15
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
°C
Note
Output current, low
IOL
Per pin
Peak value 30
r.m.s. value 15
Total for P50-P54
Total for P55-P57
Peak value 100
r.m.s. value 70
Peak value 100
r.m.s. value 70
Peak value 50
r.m.s. value 20
Peak value 50
r.m.s. value 20
Total for P10-P17, P70-P72, P100,
P101
Total for P01-P03, P30-P37
Operating ambient temperature
Storage temperature
TA
–40 to +85
–65 to +150
Tstg
°C
Note The r.m.s. value should be calculated as follows: [r.m.s. value] = [Peak value] x Duty
Caution
Remark
If the absolute maximum rating of even one of the above parameters is exceeded, the quality of the
product may be degraded. The absolute maximum ratings are therefore the rated values that may, if
exceeded, physically damage the product. Be sure to use the product with all the absolute maximum
ratings observed.
Unless otherwise specified, dual-function pin characteristics are the same as port pin characteristics.
27
µPD78P083
Capacitance (TA = 25°C, VDD = VSS = 0 V)
Parameter
Symbol Test Conditions
MIN.
TYP.
MAX.
15
Unit
pF
Input capacitance
I/O capacitance
CIN
CIO
f = 1 MHz, Unmeasured pins returned to 0 V.
f = 1 MHz,
P01-P03, P10-P17, P30-P37,
P50-P57, P70-P72, P100,
P101
15
pF
Unmeasured pins
returned to 0 V.
Remark
Unless otherwise specified, dual-function pin characteristics are the same as port pin characteristics.
Main System Clock Oscillator Characteristics (TA = –40 to +85°C, VDD = 1.8 to 5.5 V)
Resonator
Recommended
Circuit
Parameter
Test Conditions
MIN.
1.0
TYP.
MAX.
5.0
Unit
Ceramic
V
PP X2
X1
Oscillation frequency
(fX) Note 1
VDD = Oscillation voltage
range
MHz
resonator
C2
C1
Oscillation stabilization
timeNote 2
After VDD came to MIN.
of oscillation voltage range
4
ms
V
PP X2
C2
X1
Crystal
Oscillation frequency
(fX) Note 1
1.0
5.0
MHz
ms
resonator
C1
Oscillation stabilization
timeNote 2
VDD = 4.5 to 5.5 V
10
30
5.0
External clock
X1 input frequency
(fX) Note 1
1.0
85
MHz
ns
X2
X1
X1 input high- and
low-level widths (tXH, tXL)
500
µ
PD74HCU04
Notes 1. Only the oscillator characteristics are shown. For the instruction execution time, refer to AC Characteristics.
2. Time required for oscillation to stabilize after a reset or the STOP mode has been released.
Caution When using the oscillation circuit of the main system clock, wire the portion enclosed in broken lines
in the figures as follows to avoid adverse influences on the wiring capacitance:
•
•
•
•
•
•
Keep the wiring length as short as possible.
Do not cross the wiring over other signal lines.
Do not route the wiring in the vicinity of lines through which a high fluctuating current flows.
Always keep the ground point of the capacitor of the oscillation circuit at the same potential as VSS.
Do not connect the power source pattern through which a high current flows.
Do not extract signals from the oscillation circuit.
28
µPD78P083
DC Characteristics (TA = –40 to +85°C, VDD = 1.8 to 5.5 V)
Parameter
Symbol
Test Conditions
MIN.
TYP.
MAX.
Unit
V
Input voltage, high
VIH1
P10-P17, P30-P32,
VDD = 2.7 to 5.5 V
0.7VDD
VDD
P35-P37, P50-P57,
P71
0.8VDD
0.8VDD
VDD
VDD
V
V
VIH2
P00-P03, P33, P34,
P70, P72, P100, P101,
RESET
VDD = 2.7 to 5.5 V
0.85VDD
VDD
V
VIH3
VIL1
X1, X2
VDD = 2.7 to 5.5 V
VDD = 2.7 to 5.5 V
VDD–0.5
VDD–0.2
0
VDD
VDD
V
V
V
Input voltage, low
P10-P17, P30-P32,
P35-P37, P50-P57,
P71
0.3VDD
0
0
0.2VDD
0.2VDD
V
V
VIL2
P00-P03, P33, P34,
P70, P72, P100,
P101, RESET
X1, X2
VDD = 2.7 to 5.5 V
VDD = 2.7 to 5.5 V
0.15VDD
0
V
VIL3
VOH
VOL
0
0.4
0.2
V
V
V
V
V
0
Output voltage, high
Output voltage, low
VDD = 4.5 to 5.5 V, IOH = –1 mA
VDD–1.0
VDD–0.5
IOH = –100 µA
P50-P57
VDD = 2.0 to 4.5 V,
0.8
2.0
0.4
IOL = 10 mA
VDD = 4.5 to 5.5 V,
IOL = 15 mA
0.4
V
V
P01-P03, P10-P17,
P30-P37, P70-P72,
P100, P101
VDD = 4.5 to 5.5 V,
IOL = 1.6 mA
IOL = 400 µA
0.5
3
V
Input-leak current, high
Input-leak current, low
ILIH1
VIN = VDD
P00-P03, P10-P17,
P30-P37, P50-P57,
P70-P72, P100,
P101, RESET
X1, X2
µA
ILIH2
ILIL1
20
–3
µA
µA
VIN = 0 V
P00-P03, P10-P17,
P30-P37, P50-P57,
P70-P72, P100,
P101, RESET
X1, X2
ILIL2
ILOH
ILOL
R
–20
3
µA
µA
µA
kΩ
Output leak current, high
Output leak current, low
Software pull-up resistor
VOUT = VDD
VOUT = 0 V
VIN = 0 V
–3
90
P01-P03, P10-P17,
P30-P37, P50-P57,
P70-P72, P100,
P101
15
40
Remark Unless otherwise specified, dual-function pin characteristics are the same as port pin characteristics.
29
µPD78P083
DC Characteristics (TA = –40 to +85°C, VDD = 1.8 to 5.5 V)
Parameter
Symbol
Test Conditions
MIN.
TYP.
5.4
MAX.
16.2
2.4
Unit
mA
mA
mA
mA
mA
Note 1
Note 4
Note 5
Note 5
Note 4
Note 5
Supply current
IDD1
5.0-MHz crystal
oscillation operating
VDD = 5.0 V ± 10%
VDD = 3.0 V ± 10%
0.8
mode (fXX = 2.5 MHz) Note 2 VDD = 2.0 V ± 10%
5.0-MHz crystal oscil- VDD = 5.0 V ± 10%
lation operating mode VDD = 3.0 V ± 10%
0.45
9.5
1.35
28.5
3.0
1.0
Note 3
(fXX = 5.0 MHz)
IDD2
5.0-MHz crystal oscil- VDD = 5.0 V ± 10%
1.4
0.5
4.2
1.5
mA
mA
µA
lation HALT mode
VDD = 3.0 V ± 10%
VDD = 2.0 V ± 10%
Note 2
(fXX = 2.5 MHz)
280
1.6
840
4.8
5.0-MHz crystal oscil- VDD = 5.0 V ± 10%
mA
mA
lation HALT mode
VDD = 3.0 V ± 10%
0.65
1.95
Note 3
(fXX = 5.0 MHz)
STOP mode
IDD3
VDD = 5.0 V ± 10%
VDD = 3.0 V ± 10%
VDD = 2.0 V ± 10%
0.1
30
10
10
µA
µA
µA
0.05
0.05
Notes 1. Not including AVREF, AVDD currents or port currents (including current flowing into internal pull-up resistors).
2. fXX = fX/2 operation (when oscillation mode selection register (OSMS) is set to 00H).
3. fXX = fX operation (when oscillation mode selection register (OSMS) is set to 01H).
4. High-speed mode operation (when processor clock control register (PCC) is set to 00H).
5. Low-speed mode operation (when processor clock control register (PCC) is set to 04H).
Remark
fxx: Main system clock frequency (fx or fx/2)
fx: Main system clock oscillation frequency
30
µPD78P083
AC Characteristics
(1) Basic Operation (TA = –40 to +85°C, VDD = 1.8 to 5.5 V)
Parameter
Cycle time
Symbol
Test Conditions
VDD = 2.7 to 5.5 V
MIN.
0.8
2.0
0.4
0.8
0
TYP.
MAX.
64
Unit
µs
Note1
TCY
fXX = fX/2
(minimum instruction execution
time)
64
µs
Note2
fXX = fX
3.5 V ≤ VDD ≤ 5.5 V
2.7 V ≤ VDD < 3.5 V
32
µs
32
µs
TI5, TI6
fTI
VDD = 4.5 to 5.5 V
VDD = 4.5 to 5.5 V
VDD = 2.7 to 5.5 V
VDD = 2.7 to 5.5 V
4
MHz
kHz
ns
input frequency
TI5, TI6 input high-/
low-level widths
Interrupt input high-/
low-level widths
RESET low-level width
0
275
tTIH,
tTIL
100
1.8
10
µs
tINTH,
tINTL
tRSL
µs
20
µs
10
µs
20
µs
Notes 1. When oscillation mode selection register (OSMS) is set to 00H.
2. When OSMS is set to 01H.
Remark
fxx: Main system clock frequency (fx or fx/2)
fx: Main system clock oscillation frequency
TCY vs VDD
TCY vs VDD
(Main System Clock fxx = fx/2 Operation)
(Main System Clock fxx = fx Operation)
60
10
60
10
µ
µ
Operation
Operation
Guaranteed Range
Guaranteed
Range
2.0
1.0
2.0
1.0
0.5
0.4
0.5
0.4
0
0
1
2
3
4
5
6
1
2
3
4
5
6
Power Supply Voltage VDD [V]
Power Supply Voltage VDD [V]
31
µPD78P083
(2) Serial Interface (TA = –40 to +85°C, VDD = 1.8 to 5.5 V)
(a) 3-wire serial I/O mode (SCK2 ··· internal clock output)
Parameter
SCK2 cycle time
Symbol
Test Conditions
4.5 V ≤ VDD ≤ 5.5 V
MIN.
800
TYP.
MAX.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tKCY1
2.7 V ≤ VDD < 4.5 V
2.0 V ≤ VDD < 2.7 V
1600
3200
4800
tKCY1/2–50
tKCY1/2–100
100
SCK2 high-/low-level width
tKH1,
tKL1
VDD = 4.5 to 5.5 V
SI2 setup time
tSIK1
4.5 V ≤ VDD ≤ 5.5 V
2.7 V ≤ VDD < 4.5 V
2.0 V ≤ VDD < 2.7 V
(to SCK2 ↑)
150
300
400
SI2 hold time
tKSI1
400
(from SCK2 ↑)
SCK2 ↓ → SO2
output delay time
tKSO1
C = 100 pFNote
300
ns
Note C is the SCK2, SO2 output line load capacitance.
(b) 3-wire serial I/O mode (SCK2 ··· external clock input)
Parameter
SCK2 cycle time
Symbol
Test Conditions
4.5 V ≤ VDD ≤ 5.5 V
MIN.
800
TYP.
MAX.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tKCY2
2.7 V ≤ VDD < 4.5 V
2.0 V ≤ VDD < 2.7 V
1600
3200
4800
400
SCK2 high-/low-level width
tKH2,
tKL2
4.5 V ≤ VDD ≤ 5.5 V
2.7 V ≤ VDD < 4.5 V
2.0 V ≤ VDD < 2.7 V
800
1600
2400
100
SI2 setup time
(to SCK2 ↑)
tSIK2
tKSI2
tKSO2
VDD = 2.0 to 5.5 V
150
SI2 hold time
400
(from SCK2 ↑)
SCK2 ↓ → SO2
output delay time
SCK2 rise, fall time
C = 100 pFNote
VDD = 2.0 to 5.5 V
300
500
ns
ns
ns
tR2,
tF2
1000
Note C is the SO2 output line load capacitance.
32
µPD78P083
(c) UART mode (Dedicated baud rate generator output)
Parameter
Transfer rate
Symbol
Test Conditions
4.5 V ≤ VDD ≤ 5.5 V
MIN.
TYP.
MAX.
78125
39063
19531
9766
Unit
bps
bps
bps
bps
2.7 V ≤ VDD < 4.5 V
2.0 V ≤ VDD < 2.7 V
(d) UART mode (External clock input)
Parameter
ASCK cycle time
Symbol
Test Conditions
4.5 V ≤ VDD ≤ 5.5 V
MIN.
800
TYP.
MAX.
Unit
ns
tKCY3
2.7 V ≤ VDD < 4.5 V
2.0 V ≤ VDD < 2.7 V
1600
3200
4800
400
ns
ns
ns
ASCK high-/low-level width
tKH3,
tKL3
4.5 V ≤ VDD ≤ 5.5 V
2.7 V ≤ VDD < 4.5 V
2.0 V ≤ VDD < 2.7 V
ns
800
ns
1600
2400
ns
ns
Transfer rate
4.5 V ≤ VDD ≤ 5.5 V
2.7 V ≤ VDD < 4.5 V
2.0 V ≤ VDD < 2.7 V
39063
19531
9766
bps
bps
bps
bps
ns
6510
ASCK rise, fall time
tR3,
1000
tF3
33
µPD78P083
AC Timing Test Point (Excluding X1 Input)
0.8 VDD
0.2 VDD
0.8 VDD
0.2 VDD
Test Points
Clock Timing
1/fx
tXL
tXH
VDD – 0.5 V
0.4 V
X1 Input
TI Timing
1/fTI
tTIL
tTIH
TI5, TI6
34
µPD78P083
Serial Transfer Timing
3-wire serial I/O mode:
tKCY1, 2
tKH1, 2
tKL1, 2
tR2
tF2
SCK2
SI2
tSIK1, 2
tKSI1, 2
Input Data
tKSO1, 2
Output Data
SO2
UART mode (external clock input):
tKCY3
tKL3
tKH3
tR3
tF3
ASCK
35
µPD78P083
A/D Converter Characteristics (TA = –40 to +85°C, AVDD = VDD = 2.7 to 5.5 V, AVSS = VSS = 0 V)
Parameter
Resolution
Symbol
Test Conditions
MIN.
8
TYP.
8
MAX.
8
Unit
bit
%
Note
Total error
2.7 V ≤ AVREF ≤ AVDD
1.4
200
Conversion time
tCONV
tSAMP
VIAN
19.1
12/fxx
AVSS
2.7
µs
µs
V
Sampling time
Analog input voltage
Reference voltage
AVREF-AVSS resistance
AVREF
AVDD
AVREF
RAIREF
V
4
14
kΩ
Note Excluding quantization error (±1/2 LSB). Shown as a percentage of the full scale value.
Remark
fxx: Main system clock frequency (fx or fx/2)
fx: Main system clock oscillation frequency
36
µPD78P083
Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics (TA = –40 to +85°C)
Parameter
Symbol
Test Conditions
MIN.
1.8
TYP.
0.1
MAX.
5.5
Unit
V
Data retention supply voltage VDDDR
Data retention supply current
Release signal set time
Oscillation stabilization wait
time
IDDDR
tSREL
tWAIT
VDDDR = 1.8 V
10
µA
µs
0
Release by RESET
Release by interrupt
217/fx
ms
ms
Note
Note 212/fxx or 214/fxx-217/fxx can be selected by bit 0-bit 2 (OSTS0-OSTS2) of oscillation stabilization time selection register
(OSTS).
Remark
fxx: Main system clock frequency (fx or fx/2)
fx: Main system clock oscillation frequency
Data Retention Timing (STOP mode released by RESET)
Internal reset operation
HALT mode
Operating
mode
STOP mode
Data retention mode
VDD
VDDDR
tSREL
STOP instruction execution
RESET
tWAIT
Data Retention Timing (Standby release signal: STOP mode released by interrupt signal)
HALT mode
Operating
mode
STOP mode
Data retention mode
VDD
VDDDR
tSREL
STOP instruction execution
Standby release signal
(interrupt request)
tWAIT
37
µPD78P083
Interrupt Input Timing
tINTL
tINTH
INTP1-INTP3
RESET Input Timing
tRSL
RESET
38
µPD78P083
PROM Programming Characteristics
DC Characteristics
(1) PROM Write Mode (TA = 25 ±5˚C, VDD = 6.5 ±0.25 V, VPP = 12.5 ±0.3 V)
Parameter
Input voltage, high
Input voltage, low
Output voltage, high
Output voltage, low
Input leakage current
VPP supply voltage
VDD supply voltage
VPP supply current
VDD supply current
Symbol SymbolNote
Test Conditions
MIN.
0.7VDD
0
TYP.
MAX.
VDD
Unit
V
VIH
VIL
VOH
VOL
ILI
VIH
VIL
0.3VDD
V
VOH
VOL
ILI
IOH = –1 mA
VDD – 1.0
V
IOL = 1.6 mA
0.4
+10
12.8
6.75
50
V
0 ≤ VIN ≤ VDD
–10
12.2
6.25
µA
V
VPP
VDD
IPP
VPP
VCC
IPP
12.5
6.5
V
PGM = VIL
mA
mA
IDD
ICC
50
(2) PROM Read Mode (TA = 25 ±5˚C, VDD = 5.0 ±0.5 V, VPP = VDD ±0.6 V)
Parameter
Input voltage, high
Input voltage, low
Output voltage, high
Symbol SymbolNote
Test Conditions
MIN.
0.7VDD
0
TYP.
MAX.
VDD
Unit
V
VIH
VIL
VIH
VIL
0.3VDD
V
VOH1
VOH2
VOL
ILI
VOH1
VOH2
VOL
ILI
IOH = –1 mA
VDD – 1.0
VDD – 0.5
V
IOH = –100 µA
V
Output voltage, low
Input leakage current
Output leakage current
VPP supply voltage
VDD supply voltage
VPP supply current
VDD supply current
IOL = 1.6 mA
0.4
+10
V
0 ≤ VIN ≤ VDD
–10
–10
µA
µA
V
ILO
ILO
0 ≤ VOUT ≤ VDD, OE = VIH
+10
VPP
VDD
IPP
VPP
VCC
IPP
VDD – 0.6
4.5
VDD
VDD + 0.6
5.5
5.0
V
VPP = VDD
100
µA
mA
IDD
ICCA1
CE = VIL, VIN = VIH
50
Note Corresponding µPD27C1001A symbol.
39
µPD78P083
AC Characteristics
(1) PROM Write Mode
(a) Page program mode (TA = 25 ±5˚C, VDD = 6.5 ±0.25 V, VPP = 12.5 ±0.3 V)
Parameter
Address setup time (to OE ↓) tAS
Symbol Symbol Note
Test Conditions
MIN.
TYP.
MAX.
Unit
µs
µs
µs
µs
µs
µs
µs
µs
ns
tAS
2
2
2
2
2
2
0
2
0
OE setup time
tOES
tCES
tOES
tCES
tDS
CE setup time (to OE ↓)
Input data setup time (to OE ↓) tDS
Address hold time (from OE ↑) tAH
tAH
tAHL
tAHV
tAHL
tAHV
tDH
Input data hold time (from OE ↑) tDH
OE ↑ → Data output float
delay time
tDF
tDF
250
VPP setup time (to OE ↓)
VDD setup time (to OE ↓)
Program pulse width
tVPS
tVDS
tPW
tVPS
tVCS
tPW
tOE
1.0
1.0
ms
ms
ms
µs
0.095
0.1
0.105
1
OE ↓ → Valid data delay time tOE
OE pulse width during data
latching
tLW
tLW
1
µs
PGM setup time
CE hold time
tPGMS
tCEH
tPGMS
tCEH
2
2
2
µs
µs
µs
OE hold time
tOEH
tOEH
(b) Byte program mode (TA = 25 ±5˚C, VDD = 6.5 ±0.25 V, VPP = 12.5 ±0.3 V)
Parameter
Address setup time (to PGM ↓) tAS
Symbol Symbol Note
Test Conditions
MIN.
TYP.
MAX.
Unit
µs
µs
µs
µs
µs
µs
tAS
2
2
2
2
2
2
OE set time
tOES
tCES
tOES
tCES
tDS
CE setup time (to PGM ↓)
Input data setup time (to PGM ↓) tDS
Address hold time (from OE ↑) tAH
tAH
Input data hold time
(from PGM ↑)
tDH
tDH
OE ↑ → Data output float
delay time
tDF
tDF
0
250
ns
VPP setup time (to PGM ↓)
VDD setup time (to PGM ↓)
Program pulse width
tVPS
tVDS
tPW
tVPS
tVCS
tPW
tOE
1.0
1.0
ms
ms
ms
µs
0.095
0.1
0.105
1
OE ↓ → Valid data delay time tOE
OE hold time
tOEH
—
2
µs
Note Corresponding µPD27C1001A symbol.
40
µPD78P083
(2) PROM Read Mode (TA = 25 ±5˚C, VDD = 5.0 ±0.5 V, VPP = VDD ±0.6 V)
Parameter
Address → Data output
delay time
Symbol Symbol Note
Test Conditions
CE = OE = VIL
MIN.
TYP.
MAX.
800
Unit
ns
tACC
tACC
CE ↓ → Data output delay time
OE ↓ → Data output delay time
OE ↑ → Data output float
delay time
tCE
tOE
tDF
tCE
tOE
tDF
OE = VIL
CE = VIL
CE = VIL
800
200
60
ns
ns
ns
0
0
Address → Data hold time
tOH
tOH
CE = OE = VIL
ns
Note Corresponding µPD27C1001A symbol.
(3) PROM Programming Mode (TA = 25˚C, VSS = 0 V)
Parameter
PROM programming mode
setup time
Symbol
tSMA
Test Conditions
MIN.
10
TYP.
MAX.
Unit
µs
41
µPD78P083
PROM Write Mode Timing (page program mode)
Page Data Latch
Page Program
Program Verify
A2-A14
t
AS
t
t
AHL
DH
t
AHV
A0, A1
D0-D7
t
DS
t
DF
Hi-Z
Hi-Z
Hi-Z
Data
Output
tPGMS
t
AH
t
OE
t
VPS
Data Input
VPP
V
PP
VDD
t
VDS
V
DD+1.5
V
DD
V
DD
t
OEH
t
CES
V
IH
CE
VIL
t
CEH
t
PW
V
IH
PGM
OE
V
IL
t
OES
t
LW
V
IH
VIL
42
µPD78P083
PROM Write Mode Timing (byte program mode)
Program
Program Verify
Data Output
A0-A14
t
AS
t
DF
Hi-Z
Hi-Z
Hi-Z
Data Input
D0-D7
t
DS
t
DH
t
AH
VPP
VPP
V
DD
t
VPS
V
DD+1.5
V
DD
V
DD
t
t
VDS
CES
t
OEH
V
IH
CE
PGM
OE
V
IL
t
PW
V
IH
V
IL
t
OES
t
OE
V
IH
VIL
Cautions 1. VDD should be applied before VPP, and removed after VPP.
2. VPP must not exceed +13.5 V including overshoot.
3. Reliability may be adversely affected if removal/reinsertion is performed while + 12.5 V is being
applied to VPP.
PROM Read Mode Timing
Effective Address
A0-A14
VIH
CE
OE
V
IL
t
CE
V
IH
Note 2
DF
VIL
t
Note 1
ACC
Note 1
OE
t
t
t
OH
Hi-Z
Hi-Z
D0-D7
Data Output
Notes 1. If you want to read within the range of tACC, make the OE input delay time from the fall of CE a maximum of tACC–
tOE.
2. tDF is the time from when either OE or CE first reaches VIH.
43
µPD78P083
PROM Programming Mode Setting Timing
V
DD
VDD
0
RESET
V
DD
V
PP
0
t
SMA
Effective Address
A0-A14
44
µPD78P083
9. PACKAGE DRAWINGS
42PIN PLASTIC SHRINK DIP (600 mil)
42
22
1
21
A
K
L
F
B
R
M
C
D
M
N
NOTES
ITEM MILLIMETERS
INCHES
1) Each lead centerline is located within 0.17 mm (0.007 inch) of
its true position (T.P.) at maximum material condition.
A
B
C
39.13 MAX.
1.78 MAX.
1.778 (T.P.)
1.541 MAX.
0.070 MAX.
0.070 (T.P.)
2) Item "K" to center of leads when formed parallel.
+0.004
0.020
D
0.50±0.10
–0.005
F
G
H
I
0.9 MIN.
3.2±0.3
0.035 MIN.
0.126±0.012
0.020 MIN.
0.170 MAX.
0.200 MAX.
0.600 (T.P.)
0.520
0.51 MIN.
4.31 MAX.
5.08 MAX.
15.24 (T.P.)
13.2
J
K
L
+0.004
0.010
+0.10
0.25
M
–0.003
–0.05
N
R
0.17
0.007
0~15°
0~15°
P42C-70-600A-1
Remark The shape and material of ES versions are the same as those of mass-produced versions.
45
µPD78P083
µPD78P083GB-3B4
44 PIN PLASTIC QFP ( 10)
A
B
23
22
33
34
detail of lead end
S
C
D
R
Q
12
11
44
1
F
G
J
M
I
H
K
M
P
N
L
NOTE
ITEM MILLIMETERS
INCHES
Each lead centerline is located within 0.15 mm (0.006 inch) of
its true position (T.P.) at maximum material condition.
+0.017
0.535
A
B
C
D
13.6±0.4
10.0±0.2
10.0±0.2
13.6±0.4
–0.016
+0.008
–0.009
0.394
0.394
0.535
+0.008
–0.009
+0.017
–0.016
F
1.0
1.0
0.039
0.039
G
+0.004
–0.005
H
0.35±0.10
0.014
I
0.15
0.006
J
0.8 (T.P.)
0.031 (T.P)
+0.008
0.071
K
L
1.8±0.2
0.8±0.2
–0.009
+0.009
0.031
–0.008
+0.10
0.15
+0.004
0.006
M
–0.05
–0.003
N
P
Q
R
S
0.10
0.004
2.7
0.106
0.1±0.1
5°±5°
3.0 MAX.
0.004±0.004
5°±5°
0.119 MAX.
P44GB-80-3B4-3
Remark The shape and material of ES versions are the same as those of mass-produced versions.
46
µPD78P083
µPD78P083GB-3BS-MTX
44 PIN PLASTIC QFP ( 10)
A
B
23
22
33
34
detail of lead end
S
C
D
R
Q
12
11
44
1
F
J
M
H
G
I
K
M
P
N
L
NOTE
ITEM MILLIMETERS
INCHES
Each lead centerline is located within 0.16 mm (0.007 inch) of
its true position (T.P.) at maximum material condition.
+0.008
0.520
A
B
C
D
13.2±0.2
10.0±0.2
10.0±0.2
13.2±0.2
–0.009
+0.008
0.394
–0.009
+0.008
0.394
–0.009
+0.008
0.520
–0.009
F
1.0
1.0
0.039
0.039
G
+0.08
+0.003
0.015
H
0.37
–0.07
–0.004
I
0.16
0.007
J
0.8 (T.P.)
1.6±0.2
0.031 (T.P.)
K
L
0.063±0.008
+0.009
0.031
0.8±0.2
–0.008
+0.002
0.007
+0.06
0.17
M
–0.003
–0.05
N
P
Q
0.10
0.004
2.7
0.106
0.125±0.075
0.005±0.003
+7°
3°
+7°
3°
R
S
–3°
–3°
3.0 MAX.
0.119 MAX.
S44GB-80-3BS
Remark The shape and material of ES versions are the same as those of mass-produced versions.
47
µPD78P083
42PIN CERAMIC SHRINK DIP (WINDOW) (600 mil)
X
42
22
1
21
A
K
L
Z
F
D
B
M
N
M
C
0°~15°
P42DW-70-600A
NOTES
ITEM
MILLIMETERS
38.25 MAX.
1.345 MAX.
1.778 (T.P.)
0.46 0.05
0.85 MIN.
3.5 0.3
INCHES
1) Each lead centerline is located within 0.25
mm (0.01 inch) of its true position (T.P.) at
maximum material condition.
A
B
C
D
F
1.506 MAX.
0.053 MAX.
0.07 (T.P.)
0.018 0.002
0.033 MIN.
0.138 0.012
0.040 MIN.
0.119
2) Item "K" to center of leads when formed
parallel.
G
H
I
1.02 MIN.
3.026
J
5.282 MAX.
15.24 (T.P.)
0.208 MAX.
0.600 (T.P.)
0.590
K
L
14.99
0.010+–0.0023
M
N
X
Y
Z
0.25 0.05
0.25
0.01
12.0
6.0
0.472
0.236
4-R3.0
4-R0.118
48
µPD78P083
10. RECOMMENDED SOLDERING CONDITIONS
*
It is recommended that the µPD78P083 be soldered under the following conditions.
For details on the recommended soldering conditions, refer to information document "Semiconductor Device Mounting
Technology Manual" (C10535E).
For soldering methods and conditions other than those recommended, please contact your NEC sales representative.
Table 10-1. Soldering Conditions for Surface Mount Types
µPD78P083GB-3B4
: 44-pin plastic QFP (10 x 10 mm)
µPD78P083GB-3BS-MTX : 44-pin plastic QFP (10 x 10 mm)
Soldering Method
Infrared ray reflow
Soldering Conditions
Symbol
Package peak temperature: 235˚C, Reflow time: 30 seconds or
less (at 210˚C or higher), Number of reflow processes: 2 or less
< Cautions >
IR35-00-2
VP15-00-2
(1) Wait for the device temperature to return to normal after the
first reflow before starting the second reflow.
(2) Do not perform flux cleaning with water after the first reflow.
Package peak temperature: 215˚C, Reflow time: 40 seconds or
less (at 200˚C or higher), Number of reflow processes: 2 or less
< Cautions >
VPS
(1) Wait for the device temperature to return to normal after the
first reflow before starting the second reflow.
(2) Do not perform flux cleaning with water after the first reflow.
Solder temperature: 260˚C or below, Flow time: 10 seconds or
less, Number of flow processes: 1,
Wave soldering
Partial heating
WS60-00-1
Preheating temperature: 120˚C max. (package surface
temperature)
Pin temperature: 300˚C or below,
—
Flow time: 3 seconds or less (per pin row)
Caution Do not use different soldering methods together (except for partial heating method).
Table 10-2. Soldering Condition for Hole-Through Types
µPD78P083CU : 42-pin plastic shrink DIP (600 mil)
µPD78P083DU : 42-pin ceramic shrink DIP (with window) (600 mil)
Soldering Method
Soldering Conditions
Wave Soldering
(only pins)
Solder temperature: 260°C or below, Flow time: 10 seconds or less
Partial heating
Pin temperature: 300°C or below, Flow time: 3 seconds or less (per pin)
Caution Apply wave soldering only to the pins and be careful so as not to bring solder into direct contact with
the package.
49
µPD78P083
APPENDIX A. DEVELOPMENT TOOLS
*
The following development tools are available to support development of systems using the µPD78P083.
Language Processing Software
Notes 1, 2, 3, 4
RA78K/0
CC78K/0
DF78083
Assembler package common to the 78K/0 series
C compiler package common to the 78K/0 series
Device file used for the µPD78083 subseries
Notes 1, 2, 3, 4
Notes 1, 2, 3, 4
Notes 1, 2, 3, 4
CC78K/0–L
C compiler library source file common to the 78K/0 series
PROM Writing Tools
PG-1500
PROM programmer
PA-78P083CU
PA-78P083GB
Programmer adapter connected to the PG-1500
Notes 1, 2
PG-1500 Controller
Control program for the PG-1500
Debugging Tools
IE-78000-R
In-circuit emulator common to the 78K/0 series
Note 8
IE-78000-R-A
In-circuit emulator common to the 78K/0 series (for integrated debugger)
Break board common to the 78K/0 series
IE-78000-R-BK
IE-78078-R-EM
EP-78083CU-R
EP-78083GB-R
EV-9200G-44
Emulation board common to the µPD78078 subseries
Emulation probe for the µPD78083 subseries
Socket mounted on the target system board prepared for 44-pin plastic QFP
System simulator common to the 78K/0 series
Integrated debugger for IE-78000-R-A
Notes 5, 6, 7
SM78K0
Notes 4, 5, 6, 7, 8
ID78K0
Notes 1, 2
SD78K/0
Screen debugger for the IE-78000-R
Notes 1, 2, 5, 6, 7
DF78083
Device file used for the µPD78083 subseries
Notes 1. Based on PC-9800 series (MS-DOSTM)
2. Based on IBM PC/ATTM and its compatibles (PC DOSTM/IBM DOSTM/MS-DOS)
3. Based on HP9000 series 300TM (HP-UXTM)
4. Based on HP9000 series 700TM (HP-UX), SPARCstationTM (SunOSTM), and EWS4800 series (EWS-UX/V)
5. Based on PC-9800 series (MS-DOS + WindowsTM)
6. IBM PC/AT and its compatibles (PC DOS/IBM DOS/MS-DOS + Windows)
7. Based on NEWSTM (NEWS-OSTM)
8. Under development
Remarks 1. Please refer to the 78K/0 Series Selection Guide (U11126E) for information on the third party development
tools.
2. Use the RA78K/0, CC78K/0, SM78K0, ID78K0, and SD78K/0 in combination with the DF78083.
50
µPD78P083
Fuzzy Inference Development Support System
Note 2
FE9000 Note 1/FE9200
FT9080 Note 1/FT9085
Fuzzy knowledge data creation tool
Note 3
Translator
Notes 1, 3
FI78K0
Fuzzy inference module
Fuzzy inference debugger
Notes 1, 3
FD78K0
Notes 1. Based on PC-9800 series (MS-DOS)
2. Based on IBM PC/AT and its compatibles (PC DOS/IBM DOS/MS-DOS+Windows)
3. Based on IBM PC/AT and its compatibles (PC DOS/IBM DOS/MS-DOS)
Remark
Please refer to the 78K/0 Series Selection Guide (U11126E) for information on the third party development
tools.
51
µPD78P083
APPENDIX B. RELATED DOCUMENTS
Documents Related to Devices
*
Document Name
Document No.
Japanese
IEU-886
English
IEU-1407
IEU-1372
—
µPD78083 Subseries User’s Manual
78K/0 Series User’s Manual—Instructions
78K/0 Series Instruction Table
IEU-849
U10903J
U10904J
IEM-5599
IEA-767
78K/0 Series Instruction Set
—
µPD78083 Subseries Special Function Register Table
78K/0 Series Application Note
—
Basic (III)
U10182E
Documents Related to Development Tools (User's Manual)
Document Name
Document No.
Japanese
English
EEU-1399
EEU-1404
EEU-1402
EEU-1280
EEU-1284
EEA-1208
RA78K Series Assembler Package
Operation
Language
EEU-809
EEU-815
EEU-817
EEU-656
EEU-655
EEA-618
RA78K Series Structured Assembler Preprocessor
CC78K Series C Compiler
Operation
Language
Programming
know-how
CC78K/0 C Compiler Application Note
CC78K Series Library Source File
PG-1500 PROM Programmer
PG-1500 Controller PC-9800 Series (MS-DOS) Based
PG-1500 Controller IBM PC Series (PC DOS) Based
IE-78000-R
EEU-777
EEU-651
EEU-704
EEU-5008
EEU-810
U10057J
EEU-867
U10775J
EEU-5003
EEU-5002
U10092J
—
EEU-1335
EEU-1291
U10540E
EEU-1398
U10057E
EEU-1427
EEU-1504
EEU-1529
U10181E
U10092E
IE-78000-R-A
IE-78000-R-BK
IE-78078-R-EM
EP-78083
SM78K0 System Simulator
SM78K Series System Simulator
Reference
Third party’s user
open interface
specifications
Introduction
Reference
SD78K/0 Screen Debugger
PC-9800 Series (MS-DOS) Based
SD78K/0 Screen Debugger
IBM PC/AT (PC DOS) Based
EEU-852
U10952J
EEU-5024
EEU-993
—
—
Introduction
Reference
EEU-1414
EEU-1413
Caution
The contents of the documents listed above are subject to change without prior notice. Make sure to
use the latest edition when starting design.
52
µPD78P083
Documents Related to Embedded Software (User’s Manual)
Document Name
Document No.
Japanese English
EEU-5010
78K/0 Series OS MX78K0
Basic
—
Fuzzy Knowledge Data Creation Tool
EEU-829
EEU-862
EEU-858
EEU-921
EEU-1438
EEU-1444
EEU-1441
EEU-1458
78K/0, 78K/II, and 87AD Series Fuzzy Inference Development Support System Translator
78K/0 Series Fuzzy Inference Development Support System Fuzzy Inference Module
78K/0 Series Fuzzy Inference Development Support System Fuzzy Inference Debugger
Other Documents
Document Name
Document No.
Japanese
English
IEI-1213
C10535E
IEI-1209
C10983E
IEI-1201
MEI-1202
—
Semiconductor Device Package Manual
IEI-635
Semiconductor Device Mounting Technology Manual
Quality Grades on NEC Semiconductor Devices
NEC Semiconductor Device Reliability/Quality Control System
Electrostatic Discharge (ESD) Test
C10535J
IEI-620
C10983J
MEM-539
MEI-603
MEI-604
Guide to Quality Assurance for Semicoductor Devices
Microcontroller-Related Product Guide – Third Party Products –
Caution
The contents of the documents listed above are subject to change without prior notice. Be sure to use
the latest edition when starting design.
53
µPD78P083
[MEMO]
54
µPD78P083
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note: Strong electric field, when exposed to a MOS device, can cause destruction of the
gate oxide and ultimately degrade the device operation. Steps must be taken to
stop generation of static electricity as much as possible, and quickly dissipate it
once, when it has occurred. Environmental control must be adequate. When it
is dry, humidifier should be used. It is recommended to avoid using insulators that
easily build static electricity. Semiconductor devices must be stored and trans-
ported in an anti-static container, static shielding bag or conductive material. All
test and measurement tools including work bench and floor should be grounded.
The operator should be grounded using wrist strap. Semiconductor devices must
not be touched with bare hands. Similar precautions need to be taken for PW
boards with semiconductor devices on it.
2 HANDLING OF UNUSED INPUT PINS FOR CMOS
Note: No connection for CMOS device inputs can be cause of malfunction. If no
connection is provided to the input pins, it is possible that an internal input level
may be generated due to noise, etc., hence causing malfunction. CMOS devices
behave differently than Bipolar or NMOS devices. Input levels of CMOS devices
must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to VDD or GND with a resistor, if it is considered to have
a possibility of being an output pin. All handling related to the unused pins must
be judged device by device and related specifications governing the devices.
3 STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note: Power-on does not necessarily define initial status of MOS device. Production
process of MOS does not define the initial operation status of the device.
Immediately after the power source is turned ON, the devices with reset function
have not yet been initialized. Hence, power-on does not guarantee out-pin levels,
I/O settings or contents of registers. Device is not initialized until the reset signal
is received. Reset operation must be executed immediately after power-on for
devices having reset function.
FIP, IEBus, and QTOP are trademarks of NEC Corporation.
MS-DOS and Windows are trademarks of Microsoft Corporation.
IBM DOS, PC/AT and PC DOS are trademarks of International Business Machines Corporation.
HP9000 series 300, HP9000 series 700, and HP-UX are trademarks of Hewlett-Packard Company.
SPARCstation is a trademark of SPARC International, Inc.
SunOS is a trademark of Sun Microsystems, Inc.
NEWS and NEWS-OS are trademarks of Sony Corporation.
55
µPD78P083
The related documents indicated in this publication may include preliminary versions. However, preliminary versions
are not marked as such.
The export of these products from Japan is regulated by the Japanese government. The export of some or all of
these products may be prohibited without governmental license. To export or re-export some or all of these products
from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales
representive.
License not needed
The customer must judge the need for license
: µPD78P083CU, 78P083GB-3B4, 78P083GB-3BS-MTX
: µPD78P083DU
No part of this document may be copied or reproduced in any form or by any means without the prior written
consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this
document.
NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual
property rights of third parties by or arising from use of a device described herein or any other liability arising
from use of such device. No license, either express, implied or otherwise, is granted under any patents,
copyrights or other intellectual property rights of NEC Corporation or others.
While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,
the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or
property arising from a defect in an NEC semiconductor device, customer must incorporate sufficient safety
measures in its design, such as redundancy, fire-containment, and anti-failure features.
NEC devices are classified into the following three quality grades:
“Standard“, “Special“, and “Specific“. The Specific quality grade applies only to devices developed based on
a customer designated “quality assurance program“ for a specific application. The recommended applications
of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each
device before using it in a particular application.
Standard: Computers, office equipment, communications equipment, test and measurement equipment,
audio and visual equipment, home electronic appliances, machine tools, personal electronic
equipment and industrial robots
Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems or medical equipment for life support, etc.
The quality grade of NEC devices in “Standard“ unless otherwise specified in NEC's Data Sheets or Data Books.
If customers intend to use NEC devices for applications other than those specified for Standard quality grade,
they should contact NEC Sales Representative in advance.
Anti-radioactive design is not implemented in this product.
M4 94.11
相关型号：
UPD78070AGC-8EU
8-BIT, MROM, 5MHz, MICROCONTROLLER, PQFP100, 14 X 14 MM, 1.40 MM HEIGHT, FINE PITCH, PLASTIC, LQFP-100
RENESAS
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