UPD784927GF-A-A-A-3BA [RENESAS]
16-BIT, MROM, 8MHz, MICROCONTROLLER, PQFP100, 14 X 20 MM, PLASTIC, QFP-100;
| 型号： | UPD784927GF-A-A-A-3BA |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | 16-BIT, MROM, 8MHz, MICROCONTROLLER, PQFP100, 14 X 20 MM, PLASTIC, QFP-100 时钟 外围集成电路 |
| 文件： | 总99页 (文件大小：774K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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DATA SHEET
MOS INTEGRATED CIRCUIT
µPD784927, 784928, 784927Y, 784928Y
16-BIT SINGLE-CHIP MICROCONTROLLER
DESCRIPTION
The µPD784927 and 784928 are members of the NEC 78K/IV Series of microcontrollers equipped with a high-
speed, high-performance 16-bit CPU for VCR software servo control.
The µPD784927Y and 784928Y are based on the µPD784928 with the addition of an I2C bus interface compatible
with multi-master.
They contain many peripheral hardware units ideal for VCR control, such as a multi-function timer unit (super timer
unit) for software servo control and VCR analog circuits.
Flash memory models, the µPD78F4928 and µPD78F4928Y, are under development.
The functions of the µPD784927 is described in detail in the following User’s Manual. Be sure to read this
manual before designing your system.
µPD784928, 784928Y Subseries User’s Manual - Hardware
: U12648E
: U10905E
78K/IV Series User’s Manual - Instruction
FEATURES
High instruction execution speed realized by 16-bit CPU core
•
•
Minimum instruction execution time: 250 ns (with 8 MHz internal clock)
High internal memory capacity
•
Part Number
Item
µPD784927, 784927Y
96K bytes
µPD784928, 784928Y
128K bytes
Internal ROM capacity
Internal RAM capacity
2048 bytes
3584 bytes
VCR analog circuits conforming to VHS Standard
•
•
•
•
CTL amplifier
•
•
•
DFG amplifier
DPG amplifier
•
•
Reel FG comparator (2 channels)
CSYNC comparator
RECCTL driver (rewritable)
CFG amplifier
DPFG separation circuit (ternary separation circuit)
Timer unit (super timer unit) for servo control
•
•
•
•
•
•
•
•
•
Serial interface : 3 channels
3-wire serial I/O : 2 channels
I2C bus interface: 1 channel
A/D converter: 12 channels (conversion time: 10 µs)
Low-frequency oscillation mode: main system clock frequency = internal clock frequency
Low-power consumption mode: CPU can operate with a subsystem clock.
Supply voltage range: VDD = +2.7 to 5.5 V
Hardware watch function: watch operation at low voltage (VDD = 2.7 V (MIN.)) and low current consumption
Unless otherwise specified, the µPD784927 is treated as the representative model throughout this document.
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for availability
and additional information.
The mark shows major revised points.
Document No. U12255EJ2V1DS00 (2nd edition)
Date Published October 2005 N CP(K)
Printed in Japan
1997, 1999
µPD784927, 784928, 784927Y, 784928Y
APPLICATION FIELDS
Stationary VCR, video camera, In-TV VCR
ORDERING INFORMATION
(1) µPD784928 subseries
Part Number
Package
µPD784927GC-×××-8EUNote
µPD784927GF-×××-3BA
µPD784928GC-×××-8EUNote
µPD784928GF-×××-3BA
µPD784927GF-×××-3BA-A
µPD784928GF-×××-3BA-A
100-pin plastic LQFP (fine pitch) (14 × 14 mm)
100-pin plastic QFP (14 × 20 mm)
100-pin plastic LQFP (fine pitch) (14 × 14 mm)
100-pin plastic QFP (14 × 20 mm)
100-pin plastic QFP (14 × 20 mm)
100-pin plastic QFP (14 × 20 mm)
(2) µPD784928Y subseries
Part Number
Package
µPD784927YGC-×××-8EUNote
µPD784927YGF-×××-3BA
µPD784928YGC-×××-8EUNote
µPD784928YGF-×××-3BA
µPD784927YGF-×××-3BA-A
µPD784928YGF-×××-3BA-A
100-pin plastic LQFP (fine pitch) (14 × 14 mm)
100-pin plastic QFP (14 × 20 mm)
100-pin plastic LQFP (fine pitch) (14 × 14 mm)
100-pin plastic QFP (14 × 20 mm)
100-pin plastic QFP (14 × 20 mm)
100-pin plastic QFP (14 × 20 mm)
Note Under development
Remarks 1. ××× indicates ROM code suffix.
2. Products that have the part numbers suffixed by “-A” are lead-free products.
2
Data Sheet U12255EJ2V1DS
µPD784927, 784928, 784927Y, 784928Y
PRODUCT DEVELOPMENT OF VCR-SERVO MICROCONTROLLERS
The product development of VCR-servo microcontrollers is shown below. Enclosed in a frame are subseries
names.
The Y subseries is a collection of products supporting the I2C bus.
Products under mass production
Products under development
100-pin QFP. With flash memory.
Expanded internal memory capacity.
78K/IV series
More powerful analog amplifier. Improved VCR functions.
Increased I/O. High-current port added.
I2C function added (Y model only).
µ
µ
µ
PD784928Y
PD784928
PD784915
100-pin QFP.
Expanded internal memory capacity.
Internal analog amplifier. Reinforced super timer.
Low-power consumption mode added.
78K/I series
100-pin QFP
µPD78148
Expanded internal RAM capacity. Operational amplifier,
watch function, multiplier added.
µ
PD78138
80-pin QFP
Data Sheet U12255EJ2V1DS
3
µPD784927, 784928, 784927Y, 784928Y
FUNCTION LIST (1/2)
Part Number
µPD784927, 784927Y
µPD784928, 784928Y
Item
Internal ROM capacity
Internal RAM capacity
Operating clock
96K bytes
128K bytes
3584 bytes
2048 bytes
16 MHz (internal clock: 8 MHz)
Low frequency oscillation mode : 8 MHz (internal clock: 8 MHz)
Low power consumption mode : 32.768 kHz (subsystem clock)
Minimum instruction execu-
tion time
250 ns (with 8 MHz internal clock)
I/O port
input : 20
74
I/O
: 54 (including 8 ports for LED direct drive)
Real-time output port
Timer/counter
11 (including one each for pseudo VSYNC, head amplifier switch, and chrominance rotation)
Timer/counter
TM0 (16 bits)
TM1 (16 bits)
FRC (22 bits)
TM3 (16 bits)
UDC (5 bits)
EC (8 bits)
Compare register
Capture register
Remark
3
3
—
1
—
2
6
1
1
—
—
—
4
For HSW signal generation
For CFG signal division
EDV (8 bits)
1
Capture register
Input signal
CFG
Number of bits
Measurable cycle
125 ns to 524 ms
125 ns to 524 ms
1 µs to 65.5 ms
125 ns to 524 ms
1 µs to 65.5 ms
125 ns to 524 ms
125 ns to 524 ms
Operating edge
22
22
16
22
16
22
22
↑
↑
↑
↑
↑
↑
↑
↓
DFG
HSW
↓
VSYNC
CTL
Super
↓
↓
↓
timer unit
TREEL
SREEL
VCR special
circuit
•
•
•
•
VSYNC separation circuit, HSYNC separation circuit
VISS detection, wide aspect detection circuits
Field identification circuit
Head amplifier switch/chrominance rotation output circuit
General-purpose
timer
Timer
Compare register
Capture register
TM2 (16 bits)
TM4 (16 bits)
TM5 (16 bits)
1
—
1
1 (capture/compare)
1
—
PWM output
Serial interface
•
•
16-bit resolution : 3 channels (carrier frequency: 62.5 kHz)
8-bit resolution : 3 channels (carrier frequency: 62.5 kHz)
3-wire serial I/O: 2 channels (BUSY/STRB control: 1 channel)
I2C bus interface: 1 channel (µPD784928Y subseries only)
•
A/D converter
8-bit resolution × 12 channels, conversion time: 10 µs
4
Data Sheet U12255EJ2V1DS
µPD784927, 784928, 784927Y, 784928Y
FUNCTION LIST (2/2)
Part Number
µPD784927, 784927Y
µPD784928, 784928Y
Item
Analog circuit
• CTL amplifier
• RECCTL driver (rewritable)
• DFG amplifier, DPG amplifier, CFG amplifier
• DPFG separation circuit (ternary separation circuit)
• Reel FG comparator (2 channels)
• CSYNC comparator
Interrupt sources
4 levels (programmable), vectored interrupt, macro service, context switching
9 (including NMI)
External
Internal
22 (including software interrupt)
23 (including software interrupt)
Standby function
Watch function
HALT mode/STOP mode/low power consumption mode/low power consumption HALT mode
STOP mode can be released by input of valid edge of NMI pin, watch interrupt (INTW), or INTP1/
INTP2/KEY0-KEY4 pins
0.5-second measurement, low-voltage operation (VDD = 2.7 V)
Buzzer output function
1.95 kHz, 3.91 kHz, 7.81 kHz, 15.6 kHz (Internal clock: 8 MHz)
2.048 kHz, 4.096 kHz, 32.768 kHz (Subsystem clock: 32.768 kHz)
Supply voltage
Package
VDD = +2.7 to 5.5 V
• 100-pin plastic LQFP (fine pitch)(14 × 14 mm)Note
• 100-pin plastic QFP (14 × 20 mm)
Note Under development
Data Sheet U12255EJ2V1DS
5
µPD784927, 784928, 784927Y, 784928Y
PIN CONFIGURATION (Top View)
• 100-pin plastic LQFP (fine pitch)(14 × 14 mm)
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
P84/PWM2/SDANote 2
1
2
3
4
5
6
7
8
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
P65/HWIN/DPGMON
P64/BUZ/DFGMON
P103/CSYNCIN
P102/REEL0IN/INTP3
P101/REEL1IN
DFGIN
P100/DPGIN
CFGCPIN
CFGAMP0
CFGIN
AVDD1
AVSS1
VREFC
CTLOUT2
CTLOUT1
CTLIN
RECCTL−
RECCTL+
CTLDLY
P83/ROTC
P82/HASW
P80
P57
P56
P55
P54
P53
P52
P51
P50
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
VSS
VDD
P47
P46
P45
P44
P43
P42
P41
P40
P07
P06
P05
AVSS2
P113/ANI11
P112/ANI10
P111/ANI9
P110/ANI8
P77/ANI7
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Notes 1. Under development
2. Pins SCL and SDA are provided for the µPD784928Y subseries only.
Caution Directly connect the IC (Internally Connected) pins to VSS in the normal operation mode.
6
Data Sheet U12255EJ2V1DS
µPD784927, 784928, 784927Y, 784928Y
• 100-pin plastic QFP (14 × 20 mm)
99 9897 9695 9493 9291 9089 8887 86858483 8281
DFGMON/P64/BUZ
DPGMON/P65/HWIN
CFGMON/P66/PWM4
CTLMON/P67/PWM5
P60/STRB/CLO
P61/SCK1/BUZ
P62/SO1
1100
2
3
4
5
6
7
8
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
ANI9/P111
ANI8/P110
P77/ANI7
P76/ANI6
P75/ANI5
P74/ANI4
P73/ANI3
P72/ANI2
P71/ANI1
P70/ANI0
AVREF
P63/SI1
P37/PWM0
P36/PWM1
P35/SCK2
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
P34/SO2
P33/SI2/BUSY
AVDD2
P96
VDD
P95/KEY4
P94/KEY3
P93/KEY2
P92/KEY1
P91/KEY0
P90/ENV
NMI/P20
INTP0/P21
INTP1/P22
INTP2/23
P00
P01
P02
P03
P04
P05
P06
XT1
XT2
VSS
X2
X1
RESET
IC
P32/PTO02
P31/PTO01
P30/PTO00
P87/PTO11
P86/PTO10
SCLNote/P85/PWM3
SDANote/P84/PWM2
P83/ROTC
P82/HASW
3132 3334 3536 3738 3940 4142 4344 45464748 4950
Note Pins SCL and SDA are provided for the µPD784928Y subseries only.
Caution Directly connect the IC (Internally Connected) pins to VSS.
Data Sheet U12255EJ2V1DS
7
µPD784927, 784928, 784927Y, 784928Y
ANI0-ANI11
AVDD1, AVDD2
AVSS1, AVSS2
AVREF
: Analog Input
P20-P23
: Port2
: Port3
: Port4
: Port5
: Port6
: Port7
: Port8
: Port9
: Port10
: Port11
: Analog Power Supply
: Analog Ground
P30-P37
P40-P47
: Analog Reference Voltage
: Serial Busy
P50-P57
BUSY
P60-P67
BUZ
: Buzzer Output
P70-P77
CFGAMPO
CFGCPIN
CFGIN
: Capstan FG Amplifier Output
: Capstan FG Capacitor Input
: Analog Unit Input
P80, P82-P87
P90-P96
P100-P103
P110-P113
PTO00-PTO02,
PTO10, PTO11
PWM0-PWM5
CFGMON
CLO
: Capstan FG Monitor
: Clock Output
CSYNCIN
CTLDLY
CTLIN
: Analog Unit Input
: Programmable Timer Output
: Pulse Width Modulation Output
: Control Delay Input
: CTL Amplifier Input Capacitor
: CTL Amplifier Monitor
RECCTL+, RECCTL– : RECCTL Output/PBCLT Input
REEL0IN, REEL1IN : Analog Unit Input
CTLMON
CTLOUT1, CTLOUT2 : CTL Amplifier Output
RESET
ROTC
: Reset
DFGIN
: Analog Unit Input
: DFG Monitor
: Chrominance Rotate Output
: Serial Clock
DFGMON
DPGIN
DPGMON
ENV
SCK1, SCK2
SCLNote
SDANote
SI1, SI2
SO1, SO2
STRB
: Analog Unit Input
: DPG Monitor
: Serial Clock
: Serial Data
: Envelope Input
: Serial Input
HASW
: Head Amplifier Switch Output
: Hardware Timer External Input
: Internally Connected
: Interrupt From Peripherals
: Key Return
: Serial Output
HWIN
: Serial Strobe
IC
VDD
: Power Supply
INTP0-INTP3
KEY0-KEY4
NMI
VREFC
VSS
: Reference Amplifier Capacitor
: Ground
: Nonmaskable Interrupt
: Port0
X1, X2
: Crystal (Main System Clock)
: Crystal (Subsystem Clock)
P00-P07
XT1, XT2
Note Pins SCL and SDA are provided for the µPD784928Y subseries only.
8
Data Sheet U12255EJ2V1DS
µPD784927, 784928, 784927Y, 784928Y
INTERNAL BLOCK DIAGRAM
NMI
V
V
X1
DD
SS
INTERRUPT
CONTROL
INTP0-INTP3
SYSTEM
CONTROL
X2
XT1
XT2
RESET
PWM0-PWM5
PTO00-PTO02
PTO10, PTO11
SUPER TIMER
UNIT
CLOCK OUTPUT
BUZZER OUTPUT
CLO
BUZ
VREFC
REEL0IN
REEL1IN
CSYNCIN
DFGIN
KEY INPUT
KEY0-KEY4
DPGIN
CFGIN
P00-P07
CFGAMPO
CFGCPIN
CTLOUT1
CTLOUT2
CTLIN
78K/IV
16-BIT CPU CORE
(RAM: 512 bytes)
REAL-TIME
OUTPUT PORT
P80, P82, P83
RECCTL+
PORT0
PORT2
PORT3
PORT4
PORT5
PORT6
PORT7
PORT8
PORT9
PORT10
PORT11
P00-P07
RECCTL
-
CTLDLY
DFGMON
DPGMON
CFGMON
CTLMON
AVDD1, AVDD2
AVSS1, AVSS2
AVREF
P20-P23
ANALOG UNIT
&
A/D CONVERTER
P30-P37
RAM
ROM
P40-P47
AN10-AN11
P50-P57
SI1
SO1
SCK1
SERIAL
INTERFACE 1
P60-P67
P70-P77
SI2/BUSY
SO2
SERIAL
INTERFACE 2
P80, P82-P87
P90-P96
SCK2
STRB
SERIAL
SDA
SCL
P100-P103
P110-P113
INTERFACE 3Note
Note Only the µPD784928 subseries supports I2C bus interface.
Remark Internal ROM and RAM capacities differ depending on the product.
Data Sheet U12255EJ2V1DS
9
µPD784927, 784928, 784927Y, 784928Y
SYSTEM CONFIGURATION EXAMPLE
•
Video camera
µPD784927
DFG
DPG
PORT
PORT
Key matrix
DFGIN
DPGIN
Drum motor
M
M
Driver
Driver
PWM0
CFGIN
PORT
SCK1
SI1
INTP0
Camera-
SCK
SO
controlling
microcontroller
µPD784038
CFG
SO1
SI
INTP0
PORT
Capstan motor
PWM1
Camera block
RECCTL+
PORT
SCK2
SO2
CS
CTL head
CLK
LCD C/D
µPD7225
RECCTL
-
DATA
BUSY
BUSY
Loading motor
M
Driver
PWM2
LCD display panel
CS
PORT
Audio/video
signal
processing
circuit
PORT
Composite sync signal
Video head switch
CSYNCIN
PTO00
PTO01
P80
CLK
OSD
DATA
µPD6461
BUSY
Audio head switch
Pseudo vertical sync signal
STRB
PORT
STB
Remote
controller
signal
Remote controller
reception signal
Mechanical block
INTP2
µPC2800A
+VDD +VDD
EEPROMTM
SDA
SDANote
SCLNote
SCL
Other ICs
SDA
SCL
X1
X2
XT1 XT2
32.768 kHz
16 MHz
Note Pins SCL and SDA are provided for the µPD784928Y subseries only.
10
Data Sheet U12255EJ2V1DS
µPD784927, 784928, 784927Y, 784928Y
•
Stationary VCR
µPD784927
DFG
DPG
DFGIN
DPGIN
PORT
SCK1
SI1
STB
CLK
DOUT
DIN
FIPTM C/D
µ
PD16311
SO1
Drum motor
M
M
Driver
Driver
PWM0
CFGIN
PWM1
CFG
FIP
Key matrix
Capstan motor
PORT
SCK2
SO2
CS
OSD
PD6464A
CLK
DATA
µ
RECCTL+
CTL head
RECCTL
PWM2
-
PORT
Composite sync signal
Video head switch
Audio head switch
Audio/video signal
processing circuit
CSYNCIN
PTO00
PTO01
P80
Loading motor
M
Driver
Pseudo vertical sync signal
Reel FG0
REEL0IN
PWM3
PWM5
PORT
Tuner
M
M
Driver
Reel motor
PORT
INTP2
Mechanical block
Driver
PWM4
Remote controller
reception signal
Remote controller
signal
Reel FG1
REEL1IN
µPC2800A
EEPROM
+VDD +VDD
SDANote
SCLNote
SDA
SCL
Other ICs
SDA
SCL
Low frequency
oscillation mode
X1
X2 XT1 XT2
8 MHz
32.768 kHz
Note Pins SCL and SDA are provided for the µPD784928Y subseries only.
Data Sheet U12255EJ2V1DS
11
µPD784927, 784928, 784927Y, 784928Y
CONTENTS
1. DIFFERENCE BETWEEN µPD784928 SUBSERIES AND 784928Y SUBSERIES .................... 13
2. PIN FUNCTION ............................................................................................................................... 14
2.1 Port Pins ................................................................................................................................................ 14
2.2 Pins Other Than Port Pins .................................................................................................................. 15
2.3 I/O Circuits of Pins and Processing of Unused Pins...................................................................... 17
3. INTERNAL BLOCK FUNCTION ..................................................................................................... 20
3.1 CPU Registers ...................................................................................................................................... 20
3.1.1 General-purpose registers ......................................................................................................... 20
3.1.2 Other CPU registers................................................................................................................... 21
3.2 Memory Space ...................................................................................................................................... 22
3.3 Special Function Registers (SFRs) ................................................................................................... 25
3.4 Ports ....................................................................................................................................................... 31
3.5 Real-Time Output Port ......................................................................................................................... 32
3.6 Super Timer Unit .................................................................................................................................. 36
3.7 Serial Interface ..................................................................................................................................... 42
3.8 A/D Converter ....................................................................................................................................... 45
3.9 VCR Analog Circuits ............................................................................................................................ 46
3.10 Watch Function .................................................................................................................................... 51
3.11 Clock Output Function ........................................................................................................................ 52
3.12 Buzzer Output Function ...................................................................................................................... 53
4. INTERNAL/EXTERNAL CONTROL FUNCTION ........................................................................... 54
4.1 Interrupt Function ................................................................................................................................ 54
4.1.1 Vectored interrupt....................................................................................................................... 57
4.1.2 Context switching ....................................................................................................................... 57
4.1.3 Macro service ............................................................................................................................. 58
4.1.4 Application example of macro service ...................................................................................... 60
4.2 Standby Function ................................................................................................................................. 63
4.3 Clock Generation Circuit..................................................................................................................... 65
4.4 Reset Function ..................................................................................................................................... 66
5. INSTRUCTION SET ........................................................................................................................ 67
6. ELECTRICAL SPECIFICATIONS .................................................................................................. 71
7. PACKAGE DRAWING .................................................................................................................... 86
8. RECOMMENDED SOLDERING CONDITIONS ............................................................................. 88
APPENDIX A. DEVELOPMENT TOOLS............................................................................................. 89
APPENDIX B. RELATED DOCUMENTS ............................................................................................ 92
12
Data Sheet U12255EJ2V1DS
µPD784927, 784928, 784927Y, 784928Y
1. DIFFERENCE BETWEEN µPD784928 SUBSERIES AND 784928Y SUBSERIES
The µPD78F4928 and 78F4928Y are based on the µPD784927 and 784927Y and are provided with a 128K-byte
flash memory instead of a mask ROM.
Table 1-1 shows the differences between the products in the µPD784928 subseries and 784928Y subseries.
Table 1-1. Differences between µPD784928 Subseries and 784928Y Subseries
Part Number
µPD784927,
µPD784927Y
µPD784928,
µPD784928Y
µPD78F4928,
µPD78F4928Y
Item
Internal ROM
Mask ROM
Flash memory
96K bytes
128K bytes
3584 bytes
Internal RAM
2048 bytes
Not provided
Internal memory capacity
select register (IMS)
Provided
IC pin
Provided
Not provided
Provided
VPP pin
Not provided
Electrical characteristics
Refer to the Data Sheet of each product.
Data Sheet U12255EJ2V1DS
13
µPD784927, 784928, 784927Y, 784928Y
2. PIN FUNCTION
2.1 Port Pins
Pin Name
P00-P07
I/O
I/O
Shared with:
Function
Real-time
8-bit I/O port (port 0).
output port
• Can be set in input or output mode in 1-bit units.
• Can be connected with software pull-up resistors.
P20
Input
I/O
NMI
4-bit I/O port (port 2).
P21-P23
P30-P32
P33
INTP0-INTP2
PTO00-PTO02
SI2/BUSY
SO2
• Can be connected with software pull-up resistors (P22 and P23 only).
8-bit I/O port (port 3).
• Can be set in input or output mode in 1-bit units.
• Can be connected with software pull-up resistors.
P34
P35
SCK2
P36, P37
P40-P47
PWM1, PWM0
—
I/O
8-bit I/O port (port 4).
• Can be set in input or output mode in 1-bit units.
• Can be connected with software pull-up resistors.
• Can directly drive LED.
P50-P57
I/O
I/O
—
8-bit I/O port (port 5).
• Can be set in input or output mode in 1-bit units.
• Can be connected with software pull-up resistors.
P60
STRB/CLO
SCK1/BUZ
SO1
8-bit I/O port (port 6).
P61
• Can be set in input or output mode in 1-bit units.
• Can be connected with software pull-up resistors.
P62
P63
SI1
P64
DFGMON/BUZ
DPGMON/HWIN
CFGMON/PWM4
CTLMON/PWM5
ANI0-ANI7
Real-time
P65
P66
P67
P70-P77
P80
Input
I/O
8-bit input port (port 7)
Pseudo VSYNC output
HASW output
7-bit I/O port (port 8).
P82
output port
• Can be set in input or output mode
in 1-bit units.
P83
ROTC output
P84
PWM2/SDANote
PWM3/SCLNote
PTO10
• Can be connected with software
pull-up resistors.
P85
P86
P87
PTO11
P90
I/O
ENV
7-bit I/O port (port 9).
P91-P95
P96
KEY0-KEY4
—
• Can be set in input or output mode in 1-bit units.
• Can be connected with software pull-up resistors.
4-bit input port (port 10).
P100
P101
P102
P103
P110-P113
Input
DPGIN
REEL1IN
REEL0IN/INTP3
CSYNCIN
ANI8-ANI11
Input
4-bit input port (port 11).
Note Pins SCL and SDA are provided for the µPD784928Y subseries only.
14
Data Sheet U12255EJ2V1DS
µPD784927, 784928, 784927Y, 784928Y
2.2 Pins Other Than Port Pins (1/2)
Pin Name
REEL0IN
I/O
Shared with:
P102/INTP3
P101
Function
Input
Reel FG input
REEL1IN
DFGIN
DPGIN
CFGIN
CSYNCIN
CFGCPIN
CFGAMPO
PTO00
PTO01
PTO02
PTO10
PTO11
PWM0
—
Drum FG, PFG input (ternary)
Drum PG input
P100
—
Capstan FG input
P103
Composite SYNC input
CFG comparator input
—
Output
Output
—
CFG amplifier output
P30
Programmable timer output of super timer unit
P31
P32
P86
P87
Output
P37
PWM output of super timer unit
PWM1
P36
PWM2
P84/SDANote
P85/SCLNote
P66/CFGMON
P67/CTLMON
P82
PWM3
PWM4
PWM5
HASW
Output
Output
Input
Head amplifier switch signal output
Chrominance rotation signal output
Envelope signal input
ROTC
P83
ENV
P90
SI1
Input
P63
Serial data input (serial interface channel 1)
Serial data output (serial interface channel 1)
Serial clock I/O (serial interface channel 1)
Serial data input (serial interface channel 2)
Serial data output (serial interface channel 2)
Serial clock I/O (serial interface channel 2)
Serial busy signal input (serial interface channel 2)
Serial strobe signal output (serial interface channel 2)
I2C bus data I/O
SO1
Output
I/O
P62
SCK1
P61/BUZ
P33/BUSY
P34
SI2
Input
SO2
Output
I/O
SCK2
P35
BUSY
Input
P33/SI2
P60/CLO
P84/PWM2
P85/PWM3
P70-P77
P110-P113
—
STRB
Output
I/O
SDA
SCL
I/O
I2C bus clock I/O
ANI0-ANI7
ANI8-ANI11
CTLIN
Analog input
Analog signal input of A/D converter
—
Output
I/O
CTL amplifier input capacitor connection
CTL amplifier output
CTLOUT1
CTLOUT2
RECCTL+, RECCTL–
CTLDLY
—
—
Logic signal input/CTL amplifier output
RECCTL signal output/PBCTL signal input
External time constant connection (for RECCTL rewriting)
I/O
—
—
—
Note Pins SCL and SDA are provided for the µPD784928Y subseries only.
Data Sheet U12255EJ2V1DS
15
µPD784927, 784928, 784927Y, 784928Y
2.2 Pins Other Than Port Pins (2/2)
Pin Name
VREFC
I/O
—
Shared with:
—
Function
VREF amplifier AC connection
Drum FG signal output
DFGMON
DPGMON
CFGMON
CTLMON
NMI
Output
P64/BUZ
P65/HWIN
P66/PWM4
P67/PWM5
P20
Drum PG signal output
CFG signal output
CTL signal output
Input
Input
Non-maskable interrupt request input
External interrupt request input
INTP0-INTP2
INTP3
P21-P23
P102/REEL0IN
P91-P95
P60/STRB
P61/SCK1
P64/DFGMON
P65/DPGMON
—
Input
KEY0-KEY4
CLO
Input
Key input signal input
Clock output
Output
Output
BUZ
Buzzer output
HWIN
RESET
X1
Input
Input
Input
—
External input of hardware watch counter
Reset input
—
Crystal connection for main system clock oscillation
X2
XT1
Input
—
—
Crystal connection for subsystem clock oscillation.
Crystal connection for watch clock oscillation
Positive power supply to analog amplifier circuit
PositivepowersupplytoA/Dconverterandanalogcircuitsinputbuffer
GND of analog amplifier circuit
XT2
AVDD1
AVDD2
AVSS1
AVSS2
AVREF
VDD
—
—
—
—
—
—
—
—
—
—
—
—
GND of A/D converter and analog circuits input buffer
Reference voltage input to A/D converter
Positive power supply to digital circuits
—
—
VSS
—
GND of digital circuits
IC
—
Internally connected. Directly connect this pin to VSS.
16
Data Sheet U12255EJ2V1DS
µPD784927, 784928, 784927Y, 784928Y
2.3 I/O Circuits of Pins and Processing of Unused Pins
Table 2-1 shows the types of the I/O circuits of the respective pins and processing of the unused pins. Figure
2-1 shows the circuits of the respective types.
Table 2-1. I/O Circuits of Respective Pins and Processing of Unused Pins (1/2)
Pin
I/O Circuit Type
5-A
I/O
I/O
Recommended Connection of Unused Pins
Input: Connect to VDD.
P00-P07
Output: Leave unconnected.
Connect to VDD.
P20/NMI
2
Input
I/O
P21/INTP0
Connect to VDD or VSS.
Connect to VDD.
P22/INTP1, P23/INTP2
P30/PTO00-P32/PTO02
P33/SI2/BUSY
P34/SO2
2-A
5-A
8-A
5-A
8-A
5-A
Input: Connect to VDD.
Output: Leave unconnected.
P35/SCK2
P36/PWM1, P37/PWM0
P40-P47
P50-P57
P60/STRB/CLO
P61/SCK1/BUZ
P62/SO1
8-A
5-A
8-A
5-A
8-A
5-A
P63/SI1
P64/DFGMON/BUZ
P65/HWIN/DPGMON
P66/PWM4/CFGMON
P67/PWM5/CTLMON
P70/ANI0-P77/ANI7
P80
9
Input
I/O
Connect to VSS.
5-A
Input: Connect to VDD.
Output: Leave unconnected.
P82/HASW
P83/ROTC
P84/PWM2/SDANote
P85/PWM3/SCLNote
P86/PTO10
10-A
5-A
P87/PTO11
P90/ENV
P91/KEY0-P95/KEY4
P96
8-A
5-A
Note Pins SCL and SDA are provided for the µPD784928Y subseries only.
Data Sheet U12255EJ2V1DS
17
µPD784927, 784928, 784927Y, 784928Y
Table 2-1. I/O Circuits of Respective Pins and Processing of Unused Pins (2/2)
Pin
I/O Circuit Type
—
I/O
Recommended Connection of Unused Pins
When ENDRUM = 0 or ENDRUM = 1 and
SELPGSEPA = 0: Connect to VSS.
P100/DPGIN
Input
P101/REEL1IN
P102/REEL0IN/INTP3
P103/CSYNCIN
P110/ANI8-P113/ANI11
RECCTL+, RECCTL–
DFGIN
When ENREEL = 0: Connect to VSS.
When ENCSYN = 0: Connect to VSS.
Connect to VSS.
9
Input
I/O
—
—
When ENCTL = 0 and ENREC = 0: Connect to VSS.
When ENDRUM = 0: Connect to VSS.
When ENCAP = 0: Connect to VSS.
Leave unconnected.
Input
CFGIN, CFGCPIN
CTLOUT1
—
—
Output
I/O
CTLOUT2
When ENCTL = 0 and ENCOMP = 0: Connect to VSS.
When ENCTL = 1: Leave unconnected.
Leave unconnected.
CFGAMPO
CTLIN
—
—
Output
—
When ENCTL = 0: Leave unconnected.
When ENCTL = 0 and ENCAP = 0 and ENCOMP = 0: Leave unconnected.
Leave unconnected.
VREFC
CTLDLY
AVDD1, AVDD2
AVREF, AVSS1, AVSS2
RESET
—
—
Connect to VDD.
Connect to VSS.
2
—
—
—
XT1
—
Connect to VSS.
XT2
Leave unconnected.
IC
Directly connect to VSS.
Remark ENCTL
ENREC
: bit 1 of amplifier control register (AMPC)
: bit 7 of amplifier mode register 0 (AMPM0)
: bit 2 of amplifier control register (AMPC)
ENDRUM
SELPGSEPA : bit 2 of amplifier mode register 0 (AMPM0)
ENCAP
: bit 3 of amplifier control register (AMPC)
: bit 5 of amplifier control register (AMPC)
: bit 6 of amplifier control register (AMPC)
: bit 4 of amplifier control register (AMPC)
ENCSYN
ENREEL
ENCOMP
18
Data Sheet U12255EJ2V1DS
µPD784927, 784928, 784927Y, 784928Y
Figure 2-1. I/O Circuits of Respective Pins
Type 2
Type 8-A
VDD
IN
Pull-up
enable
P-ch
V
DD
Schmitt trigger input with hysteresis characteristics
Type 2-A
Data
P-ch
IN/
OUT
Output
disable
N-ch
V
DD
Pull-up
enable
P-ch
Type 9
IN
IN
Comparator
P-ch
N-ch
+
Schmitt trigger input with hysteresis characteristics
Type 5-A
-
VREF (Threshold voltage)
VDD
Input enable
Pull-up
enable
P-ch
V
DD
Data
Type 10-A
P-ch
VDD
IN/
OUT
Output
disable
N-ch
Pull-up
Enable
P-ch
V
DD
Input
enable
Data
P-ch
IN/OUT
Open drain
Output disable
N-ch
Data Sheet U12255EJ2V1DS
19
µPD784927, 784928, 784927Y, 784928Y
3. INTERNAL BLOCK FUNCTION
3.1 CPU Registers
3.1.1 General-purpose registers
The µPD784927 has eight banks of general-purpose registers. One bank consists of sixteen 8-bit general-purpose
registers. Two of these 8-bit registers can be used in pairs as a 16-bit register. Four of the 16-bit general-purpose
registers can be used to specify a 24-bit address in combination with an 8-bit address expansion register.
These eight banks of general-purpose registers can be selected by software or context switching function.
The general-purpose registers, except for the address expansion registers V, U, T, and W, are mapped to the
internal RAM.
Figure 3-1. Configuration of General-Purpose Register
A (R1)
B (R3)
R5
X (R0)
C (R2)
R4
AX (RP0)
BC (RP1)
RP2
R7
R6
RP3
V
U
T
R9
R8
VP (RP4)
VVP (RG4)
R11
R10
UP (RP5)
UUP (RG5)
D (R13)
DE (RP6)
TDE (RG6)
H (R15)
HL (RP7)
E (R12)
L (R14)
W
8 banks
WHL (RG7)
(
): absolute name
Caution Although R4, R5, R6, R7, RP2, and RP3 can be used as X, A, C, B, AX, and BC registers,
respectively, by setting the RSS bit of PSW to 1, do not use this function. The function of the
RSS bit is planned to be deleted from the future models in the 78K/IV Series.
20
Data Sheet U12255EJ2V1DS
µPD784927, 784928, 784927Y, 784928Y
3.1.2 Other CPU registers
(1) Program counter
The program counter of the µPD784927 is 20 bits wide. The value of the program counter is automatically
updated as the program is executed.
19
0
PC
(2) Program status word
This is a register that holds the various statuses of the CPU. Its contents are automatically updated as the
program is executed.
15
14
13
12
11
10
9
8
PSWH UF RBS2 RBS1 RBS0
PSW
7
6
Z
5
4
3
2
1
0
0
Note
PSWL
S
AC
IE
P/V
CY
RSS
Note The RSS flag is provided to maintain compatibility with the microcomputers in the 78K/III Series.
Always clear this flag to 0 except when the software of the 78K/III Series is used.
(3) Stack pointer
This is a 24-bit pointer that holds the first address of the stack.
Be sure to write 0 to the high-order 4 bits.
23
0
20
0
0
SP
0
0
Data Sheet U12255EJ2V1DS
21
µPD784927, 784928, 784927Y, 784928Y
3.2 Memory Space
A memory space of 1M bytes can be accessed. The mapping of the internal data area (special function registers
and internal RAM) can be selected by using the LOCATION instruction. The LOCATION instruction must be always
executed after reset has been cleared, and cannot be used more than once.
(1) When LOCATION 0H instruction is executed
Part Number
Internal Data Area
0F700H-0FFFFH
Internal ROM Area
µPD784927, 784927Y
00000H-0F6FFH
10000H-17FFFH
µPD784928, 784928Y
0F100H-0FFFFH
00000H-0F0FFH
10000H-1FFFFH
Remark The area of the internal ROM overlapping the internal data area cannot be used when the
LOCATION 0 instruction is executed.
Part Number
µPD784927, 784927Y
µPD784928, 784928Y
Unusable Area
0F700H-0FFFFH (2304 bytes)
0F100H-0FFFFH (3840 bytes)
(2) When LOCATION 0FH instruction is executed
Part Number
µPD784927, 784927Y
µPD784928, 784928Y
Internal Data Area
FF700H-FFFFFH
FF100H-FFFFFH
Internal ROM Area
00000H-17FFFH
00000H-1FFFFH
22
Data Sheet U12255EJ2V1DS
Figure 3-2. Memory Map of µPD784927, 784927Y
When LOCATION 0H instruction is executed
When LOCATION 0FH instruction is executed
FFFFFH
FFFDFH
FFFD0H
FFF00H
Special function registers (SFRs)
Note 1
FFFFFH
(256 bytes)
0FEFFH
FFEFFH
FFEFFH
Cannot be used
Internal RAM
(2048 bytes)
General-purpose registers
(128 bytes)
0FE80H
0FE7FH
FFE80H
FFE7FH
FF700H
FF6FFH
18000H
17FFFH
Internal ROM
FFE3BH
FFE06H
(32768 bytes)
0FE3BH
0FE06H
10000H
Macro service control
word area (54 bytes)
0FFFFH
0FFDFH
0FFD0H
0FF00H
0FEFFH
Special function registers (SFRs)
Note 1
(256 bytes)
Data area (512 bytes)
0FD00H
0FCFFH
FFD00H
FFCFFH
Internal RAM
(2048 bytes)
Program/data area
(1536 bytes)
µ
0F700H
FF700H
17FFFH
Cannot be used
0F700H
0F6FFH
17FFFH
10000H
Note 2
0F6FFH
Program/data areaNote 3
Note 4
01000H
00FFFH
Internal ROM
(63232 bytes)
CALLF entry area
(2K bytes)
18000H
17FFFH
00800H
007FFH
00080H
0007FH
Note 4
CALLT table area
(64 bytes)
Internal ROM
(96K bytes)
00040H
0003FH
Vector table area
(64 bytes)
00000H
00000H
00000H
Notes 1. Accessed in external memory expansion mode
2. The 2304 bytes in this area can be used as an internal ROM only when the LOCATION 0FH instruction is executed.
3. When LOCATION 0H instruction is executed: 96000 bytes, when LOCATION 0FH instruction is executed: 98304 bytes
4. Base area or entry area for reset or interrupt. Excluding the internal RAM for reset.
Figure 3-3. Memory Map of µPD784928, 784928Y
When LOCATION 0H instruction is executed
When LOCATION 0FH instruction is executed
FFFFFH
FFFDFH
FFFD0H
FFF00H
Special function registers (SFRs)
Note 1
FFFFFH
(256 bytes)
0FEFFH
FFEFFH
FFEFFH
Cannot be used
Internal RAM
(3584 bytes)
General-purpose registers
(128 bytes)
0FE80H
0FE7FH
FFE80H
FFE7FH
FF100H
FF0FFH
20000H
1FFFFH
Internal ROM
FFE3BH
FFE06H
(65536 bytes)
0FE3BH
0FE06H
10000H
Macro service control
word area (54 bytes)
0FFFFH
0FFDFH
0FFD0H
0FF00H
0FEFFH
Special function registers (SFRs)
Note 1
(256 bytes)
Data area (512 bytes)
0FD00H
0FCFFH
FFD00H
FFCFFH
Internal RAM
(3584 bytes)
Program/data area
(3072 bytes)
0F100H
FF100H
1FFFFH
Cannot be used
0F100H
0F0FFH
µ
1FFFFH
10000H
Note 2
0F0FFH
Program/data areaNote 3
Note 4
01000H
00FFFH
Internal ROM
(61696 bytes)
CALLF entry area
(2K bytes)
20000H
1FFFFH
00800H
007FFH
00080H
0007FH
Note 4
CALLT table area
(64 bytes)
Internal ROM
(128K bytes)
00040H
0003FH
Vector table area
(64 bytes)
00000H
00000H
00000H
Notes 1. Accessed in external memory expansion mode
2. The 3840 bytes in this area can be used as an internal ROM only when the LOCATION 0FH instruction is executed.
3. When LOCATION 0H instruction is executed: 127232 bytes, when LOCATION 0FH instruction is executed: 131072 bytes
4. Base area or entry area for reset or interrupt. Excluding the internal RAM for reset.
µPD784927, 784928, 784927Y, 784928Y
3.3 Special Function Registers (SFRs)
Special function registers are assigned special functions and mapped to a 256-byte space of addresses FF00H
through FFFFH. These registers include mode registers and control registers that control the internal peripheral
hardware units.
Caution Do not access an address to which no SFR is assigned. If such an address is accessed by
mistake, the µPD784927 may be deadlocked. This deadlock can be cleared only by reset input.
Table 3-1 lists the special function registers (SFRs). The meanings of the symbols in this table are as follows:
• Symbol .................................... Abbreviation of an SFR. This abbreviation is reserved for NEC’s assembler
(RA78K4). With a C compiler (CC78K4), the abbreviation can be used as sfr
variable by the #pragma sfr instruction.
• R/W ......................................... Indicates whether the SFR in question can be read or written.
R/W : Read/write
R
: Read only
: Write only
W
• Bit length................................. Indicates the bit length (word length) of the SFR.
• Bit units for manipulation ....... Indicates bit units in which the SFR in question can be manipulated. An SFR that
can be manipulated in 16-bit units can be used as the operand sfrp of an
instruction. Specify an even address to manipulate this SFR.
An SFR that can be manipulated in 1-bit units can be used for a bit manipulation
instruction.
• After clearing reset ................. Indicates the status of each register immediately after clearing reset.
Caution The addresses shown in Table 3-1 are used when the LOCATION 0H instruction is executed. Add
“F0000H” to the address values shown in the table when the LOCATION 0FH instruction is
executed.
Data Sheet U12255EJ2V1DS
25
µPD784927, 784928, 784927Y, 784928Y
Table 3-1. Special Function Registers (1/5)
Address
Special Function Register (SFR) Name
Symbol
R/W
Bit
Length
8
Bit Units for Manipulation After Clearing
1 bit
8 bits 16 bits
Reset
FF00H Port 0
P0
P2
R/W
R
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Undefined
FF02H Port 2
8
FF03H Port 3
P3
R/W
8
FF04H Port 4
P4
8
FF05H Port 5
P5
8
FF06H Port 6
P6
8
FF07H Port 7
P7
R
8
FF08H Port 8
P8
R/W
8
FF09H Port 9
P9
8
FF0AH Port 10
P10
R
8
FF0BH Port 11
P11
8
FF0EH Port 0 buffer register L
FF0FH Port 0 buffer register H
FF10H Timer 0 compare register 0
FF11H Event counter compare register 0
FF12H Timer 0 compare register 1
FF13H Event counter compare register 1
FF14H Timer 0 compare register 2
FF15H Event counter compare register 2
FF16H Timer 1 compare register 0
FF17H Event counter compare register 3
FF18H Timer 1 compare register 1
FF1AH Timer 1 compare register 2
FF1CH Timer 1 compare register 3
FF1EH Timer 2 compare register 0
FF20H Port 0 mode register
FF23H Port 3 mode register
FF24H Port 4 mode register
FF25H Port 5 mode register
FF26H Port 6 mode register
FF28H Port 8 mode register
FF29H Port 9 mode register
FF2EH Real-time output port 0 control register
FF30H Timer counter 0
P0L
R/W
8
P0H
CR00
ECC0
CR01
ECC1
CR02
ECC2
CR10
ECC3
CR11
CR12
CR13
CR20
PM0
PM3
PM4
PM5
PM6
PM8
PM9
RTPC
TM0
EC
8
16
8
—
—
—
—
—
—
—
—
—
—
—
—
Cleared to 0
W
R/W
W
16
8
R/W
W
16
8
R/W
W
16
8
R/W
R
16
16
16
16
8
R/W
FFH
8
8
8
8
8
FDH
7FH
8
8
00H
R
R/W
R
16
8
—
—
—
—
—
—
Cleared to 0
FF31H Event counter
FF32H Timer counter 1
TM1
FRCL
FRCH
TM2
16
16
8
FF34H Free running counter (bits 0-15)
FF35H Free running counter (bits 16-21)
FF36H Timer counter 2
0000H
00H
16
Cleared to 0
Remark Cleared to 0: Counter is initialized to 0 within 16 clocks after the reset signal has been cleared (the
contents before initialization are undefined).
26
Data Sheet U12255EJ2V1DS
µPD784927, 784928, 784927Y, 784928Y
Table 3-1. Special Function Registers (2/5)
Address
Special Function Register (SFR) Name
Symbol
R/W
Bit
Bit Units for Manipulation After Clearing
Length
8
1 bit
8 bits 16 bits
Reset
00H
FF38H Timer control register 0
FF39H Timer control register 1
FF3AH Timer control register 2
FF3BH Timer control register 3
FF3CH Timer counter 3
TMC0
TMC1
TMC2
TMC3
TM3
R/W
—
—
8
8
—
8
—
00×00000
Cleared to 0
××000000
Cleared to 0
00H
R
16
8
—
—
—
FF3DH Timer control register 4
FF3EH Timer counter 4
TMC4
TM4
R/W
R
—
16
8
—
FF43H Port 3 mode control register
FF48H Port 8 mode control register
FF4BH Control mode select register
FF4DH Trigger source select register 0
FF4EH Pull-up resistor option register L
FF4FH Pull-up resistor option register H
FF50H Input control register
PMC3
PMC8
CMS
R/W
—
8
—
8
—
TRGS0
PUOL
PUOH
ICR
8
—
8
—
8
—
8
—
10H
FF51H Up/down counter count register
FF52H Event divider counter
UDC
8
—
—
—
Undefined
Cleared to 0
00H
EDV
R
R/W
R
8
—
FF53H Capture mode register
CPTM
TM5
8
—
FF54H Timer counter 5
16
16
8
—
—
—
—
—
—
—
—
—
Cleared to 0
FF56H Timer 3 capture register 0
FF58H Timer 0 output mode register
FF59H Timer 0 output control register
FF5AH Timer 1 output mode register
FF5BH Timer 1 output control register
FF5CH Timer 3 compare register 0
FF5EH Timer 3 compare register 1
FF60H Port 8 buffer register L
CPT30
TOM0
TOC0
—
W
—
××000000
00H
8
—
Note 1
TOM1
R/W
W
8
—
80H
TOC1
CR30
CR31
P8L
8
—
00H
R/W
16
16
8
—
Cleared to 0
—
—
000×0×0×
Undefined
00H
FF63H Up/down counter compare register
FF65H Trigger source select register 1
FF66H Port 6 mode control register
FF68H A/D converter mode register
UDCC
TRGS1
PMC6
ADM
W
8
—
—
—
R/W
8
—
8
—
16
8
—
0000H
Note 2
ADML
—
FF6AH A/D conversion result register
FF6CH Hardware watch counter 0
FF6EH Hardware watch counter 1
FF6FH Watch mode register
ADCR
HW0
R
8
—
—
—
—
Undefined
Not affected
by reset
R/W
R
16
16
8
—
HW1
—
WM
R/W
—
00××0×00
05H
FF70H PWM control register 0
PWMC0
8
—
Notes 1. When the TOM1 is read, the write sequence of the REC driver is read (bits 0 and 1).
2. ADML is the low-order 8 bits of ADM and can be manipulated in 1- or 8-bit units.
Remark Cleared to 0: Counter is initialized to 0 within 16 clocks after the reset signal has been cleared (the
contents before initialization are undefined).
Data Sheet U12255EJ2V1DS
27
µPD784927, 784928, 784927Y, 784928Y
Table 3-1. Special Function Registers (3/5)
Address
Special Function Register (SFR) Name
Symbol
R/W
R/W
Bit
Bit Units for Manipulation After Clearing
Length
8
1 bit
8 bits 16 bits
Reset
15H
FF71H PWM control register 1
FF72H PWM0 modulo register
FF73H PWM2 modulo register
FF74H PWM1 modulo register
FF75H PWM3 modulo register
FF76H PWM5 modulo register
FF77H PWM4 modulo register
FF78H Event divider control register
FF79H Clock output mode register
FF7AH Timer 4 capture/compare register 0
FF7BH Clock control register
PWMC1
PWM0
PWM2
PWM1
PWM3
PWM5
PWM4
EDVC
CLOM
CR40
CC
—
16
8
—
—
—
—
—
—
—
—
0000H
00H
—
16
8
—
0000H
00H
—
16
8
—
0000H
00H
—
W
8
—
Cleared to 0
00H
R/W
8
—
16
8
—
—
Cleared to 0
00H
—
FF7CH Timer 4 capture register 1
FF7DH Capture/compare control register
FF7EH Timer 5 compare register
FF80H I2C control register
CR41
CRC
R
W
16
8
—
—
—
—
Cleared to 0
00H
—
CR50
IICC
R/W
16
8
—
Cleared to 0
00H
—
FF82H I2C clock select register
FF84H Serial mode register 1
FF85H Serial shift register 1
IICCL
CSIM1
SIO1
8
—
8
—
8
—
—
Undefined
00H
FF86H Slave address register
FF88H Serial mode register 2
FF89H Serial shift register 2
SVA
8
—
CSIM2
SIO2
8
—
8
—
—
—
Undefined
00H
FF8AH Serial control register 2
FF8CH I2C bus status registerNote
FF8EH I2C bus shift registerNote
FF90H Amplifier mode register 2
FF91H Head amplifier switch output control register
FF94H Amplifier control register
FF95H Amplifier mode register 0
FF96H Amplifier mode register 1
FF97H Gain control register
CSIC2
IICS
8
—
R
8
—
IIC
R/W
8
—
AMPM2
HAPC
AMPC
AMPM0
AMPM1
CTLM
VSFT0
8
—
8
—
8
—
8
—
8
—
8
—
FF98H VISS detection circuit shift register 0
FF99H
16
—
—
—
0000H
FF9AH VISS detection circuit shift register 1
FF9BH
VSFT1
16
—
FFA0H External interrupt mode register
FFA1H External capture mode register 1
FFA2H External capture mode register 2
FFA3H VISS detection circuit control register
INTM0
INTM1
INTM2
VDC
8
8
8
8
—
—
—
—
000000×0
00H
Note These registers are provided for the µPD784928Y subseries only.
Remark Cleared to 0: Counter is initialized to 0 within 16 clocks after the reset signal has been cleared (the
contents before initialization are undefined).
28
Data Sheet U12255EJ2V1DS
µPD784927, 784928, 784927Y, 784928Y
Table 3-1. Special Function Registers (4/5)
Address
Special Function Register (SFR) Name
Symbol
R/W
Bit
Bit Units for Manipulation After Clearing
Length
8
1 bit
—
8 bits 16 bits
Reset
00H
FFA4H VISS detection circuit up/down counter register
FFA5H VUDC value setting register
FFA6H Key interrupt control register
FFA7H VISS pulse pattern setting register
FFA8H In-service priority register
FFAAH Interrupt mode control register
FFACH Interrupt mask flag register
FFADH
VUDC
VUDST
KEYC
VPS
R/W
—
—
—
—
—
—
8
—
8
70H
00H
8
—
ISPR
IMC
R
8
R/W
8
80H
FFH
MK0L
8
MK0
MK1
MK0H
MK1L
MK1H
8
FFAEH
8
FFAFH
8
FFB0H FRC capture register 0L
FFB1H FRC capture register 0H
FFB2H FRC capture register 1L
FFB3H FRC capture register 1H
FFB4H FRC capture register 2L
FFB5H FRC capture register 2H
FFB6H FRC capture register 3L
FFB7H FRC capture register 3H
FFB8H FRC capture register 4L
FFB9H FRC capture register 4H
FFBAH FRC capture register 5L
FFBBH FRC capture register 5H
FFBDH VSYNC separation circuit control register
CPT0L
R
16
8
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Cleared to 0
CPT0H
CPT1L
CPT1H
CPT2L
CPT2H
CPT3L
CPT3H
CPT4L
CPT4H
CPT5L
CPT5H
VSC
16
8
16
8
16
8
16
8
16
8
R/W
8
00H
FFBEH
VSYNC separation circuit up/down counter register
VSUDC
VSCMP
STBC
8
—
—
—
—
FFBFH VSYNC separation circuit compare register
FFC0H Standby control register
8
FFH
0011×000
20H
8
FFC4H Execution speed select register
FFCEH CPU clock status register
MM
W
R
8
PCS
8
00H
FFCFH Oscillation stabilization time specification register
FFE0H Interrupt control register (INTP0)
FFE1H Interrupt control register (INTCPT3)
FFE2H Interrupt control register (INTCPT2)
FFE3H Interrupt control register (INTCR12)
FFE4H Interrupt control register (INTCR00)
FFE5H Interrupt control register (INTCLR1)
FFE6H Interrupt control register (INTCR10)
OSTS
W
8
—
PIC0
R/W
8
43H
CPTIC3
CPTIC2
CRIC12
CRIC00
CLRIC1
CRIC10
8
8
8
8
8
8
Remark Cleared to 0: Counter is initialized to 0 within 16 clocks after the reset signal has been cleared (the
contents before initialization are undefined).
Data Sheet U12255EJ2V1DS
29
µPD784927, 784928, 784927Y, 784928Y
Table 3-1. Special Function Registers (5/5)
Address
Special Function Register (SFR) Name
Symbol
R/W
R/W
Bit
Bit Units for Manipulation After Clearing
Length
1 bit
8 bits 16 bits
Reset
43H
FFE7H Interrupt control register (INTCR01)
FFE8H Interrupt control register (INTCR02)
FFE9H Interrupt control register (INTCR11)
FFEAH Interrupt control register (INTCPT1)
FFEBH Interrupt control register (INTCR20)
CRIC01
CRIC02
CRIC11
CPTIC1
CRIC20
IICIC
8
8
8
8
8
8
8
8
8
—
—
—
—
—
—
—
—
—
Note 1
FFECH Interrupt control register (INTIIC)
FFEDH Interrupt control register (INTTB)
FFEEH Interrupt control register (INTAD)
TBIC
ADIC
Note 2
FFEFH Interrupt control register (INTP2)
Interrupt control register (INTCR40)
PIC2
Note 2
CRIC40
UDCIC
CRIC30
CRIC50
CRIC13
CSIIC1
WIC
FFF0H Interrupt control register (INTUDC)
FFF1H Interrupt control register (INTCR30)
FFF2H Interrupt control register (INTCR50)
FFF3H Interrupt control register (INTCR13)
FFF4H Interrupt control register (INTCSI1)
FFF5H Interrupt control register (INTW)
FFF6H Interrupt control register (INTVISS)
FFF7H Interrupt control register (INTP1)
FFF8H Interrupt control register (INTP3)
FFFAH Interrupt control register (INTCSI2)
8
8
8
8
8
8
8
8
8
8
—
—
—
—
—
—
—
—
—
—
×1000011
VISIC
43H
PIC1
PIC3
CSIIC2
Notes 1. µPD784928Y subseries only.
2. PIC2 and CRIC40 are at the same address (register).
Remark Cleared to 0: Counter is initialized to 0 within 16 clocks after the reset signal has been cleared (the
contents before initialization are undefined).
30
Data Sheet U12255EJ2V1DS
µPD784927, 784928, 784927Y, 784928Y
3.4 Ports
The µPD784927 is provided with the ports shown in Figure 3-3. Table 3-2 shows the function of each port.
Figure 3-4. Port Configuration
P00
P60
Port 0
Port 2
Port 3
Port 6
P07
P20
P67
P70-P77
8
Port 7
Port 8
P23
P30
P80
P82
P87
P90
P37
P40
Port 9
Port 4
Port 5
P96
P47
P50
P100
P103
Port 10
Port 11
P110
P113
P57
Table 3-2. Port Function
Name
Port 0
Pin Name
P00-P07
Function
Specification of Pull-up Resistor
Can be set in input or output mode in
1-bit units.
Pull-up resistors are connected to all
pins in input mode.
Port 2
Port 3
Port 4
P20-P23
P30-P37
P40-P47
Input port
Pull-up resistors are connected to pins
P22 and P23.
Can be set in input or output mode in
1-bit units.
Pull-up resistors are connected to all pins
in input mode.
Can be set in input or output mode in
1-bit units.
Can directly drive LED.
Port 5
Port 6
Port 7
Port 8
Port 9
Port 10
Port 11
P50-P57
P60-P67
P70-P77
Can be set in input or output mode in
1-bit units.
Input port
Pull-up resistor is not provided.
Pull-up resistors are connected to all pins
in input mode.
P80, P82-P87
P90-P96
Can be set in input or output mode in
1-bit units.
Input port
P100-P103
P110-P113
Pull-up resistor is not provided.
Data Sheet U12255EJ2V1DS
31
µPD784927, 784928, 784927Y, 784928Y
3.5 Real-Time Output Port
A real-time output port consists of a port output latch and a buffer register (refer to Figure 3-5).
The function to transfer the data prepared in advance in the buffer register to the output latch when a trigger such
as a timer interrupt occurs, and output the data to an external device is called a real-time output function. A port used
in this way is called a real-time output port (RTP).
Table 3-3 shows the real-time output ports of the µPD784927.
Table 3-4 shows the trigger sources of RTPs.
Figure 3-5. Configuration of RTP
Buffer register
Output trigger
Port output latch
Port
Table 3-3. Bit Configuration of RTP
RTP
RTP0
RTP8
Shared with:
Port 0
Number of Bits of
Number of Bits That Can
Be Specified as RTP
Remark
—
Real-Time Output Data
4 bits × 2 channels or
8 bits × 1 channel
4-bit units
Port 8
1 bit × 1 channel and
2 bits × 1 channel
1-bit units
Pseudo VSYNC output: 1 channel (RTP80)
Head amplifier switch: 1 channel (RTP82)
Chrominance rotation signal output: 1
channel (RTP83)
Table 3-4. Trigger Sources of RTP
Trigger Source
INTCR00
INTCR01
INTCR02
INTCR13
INTCR50
INTP0
Remark
RTP
RTP0
High-order 4 bits
Low-order 4 bits
All 8 bits
RTP8
Bit 0
Note 1
Note 2
Bits 2 and 3
Notes 1. Select one of the four trigger sources.
2. When the real-time output port mode is set by the port mode control register 8 (PMC8), the HASW and
ROT-C signals that are set by the head amplifier switch output control register (HAPC) are directly
output. The HASW and ROT-C signals are synchronized with HSW output (TM0-CR00 coincidence
signal). However, the set signal is output immediately when the HAPC register is rewritten.
32
Data Sheet U12255EJ2V1DS
µPD784927, 784928, 784927Y, 784928Y
Figures 3-6 and 3-7 show the block diagrams of RTP0 and RTP8. Figure 3-8 shows the types of RTP output trigger
sources.
Figure 3-6. Block Diagram of RTP0
Internal bus
8
4
4
Buffer register
Real-time output port 0
control register (RTPC)
8
P0H
P0L
4
4
INTP0
INTCR01
INTCR02
Output trigger
Control circuit
Output latch (P0)
P07
P00
Remark INTCR01: TM0-CR01 coincidence signal
INTCR02: TM0-CR02 coincidence signal
Figure 3-7. Block Diagram of RTP8
Internal bus
8
8
8
Head amplifier output control register (HAPC)
Port 8 buffer register L (P8L)
SEL SEL SEL PB
ROTCHASW ENV MOD2 MOD1 MOD0
PB
PB
SEL
0
0
0
0
0
P8L4 MD80 P8L2
0 P8L0
TRGP80
HASW, ROT-C
control circuit
Pseudo VSYNC output
control circuit
TM0-CR00
coincidence signal
PMC80
0
PMC82
PMC83
PMC8
Output latch (P8)
H
SYNC
superimposition
circuit
P83P82
P80
Data Sheet U12255EJ2V1DS
33
µPD784927, 784928, 784927Y, 784928Y
Figure 3-8. Types of RTP Output Trigger Sources
Real-time output port 0
control register (RTPC)
INTP0
TM0
Selector
Trigger of P0H
Trigger of P0L
CR00
CR01
CR02
Interrupt and
timer output
Trigger of P82 and P83
Trigger of P80
Selector
TM1
Trigger source select
register 0 (TRGS0)
CR10
CR11
CR12
CR13
Interrupt and
timer output
Capture
Interrupt
TM5
Interrupt
CR50
34
Data Sheet U12255EJ2V1DS
µPD784927, 784928, 784927Y, 784928Y
RTP80 can output low-level, high-level, and high-impedance values real-time.
Because RTP80 can superimpose a horizontal sync signal, it can be used to create pseudo vertical sync signal.
When RTP80 is set in the pseudo VSYNC output mode, it repeatedly outputs a specific pattern when an output trigger
occurs.
Figure 3-9 shows the operation timing of RTP80.
Figure 3-9. Example of Operation Timing of RTP80
(a) When HSYNC signal is superimposed
High level
P80 High impedance
Low level
Trigger signal
(b) Pseudo VSYNC output mode
High level
P80 High impedance
Low level
Trigger signal
Data Sheet U12255EJ2V1DS
35
µPD784927, 784928, 784927Y, 784928Y
3.6 Super Timer Unit
The µPD784927 is provided with a super timer unit that consists of the timers, and VCR special circuits such as
a VISS detection circuit and a VSYNC separation circuit, etc., shown in Table 3-5.
Table 3-5. Configuration of Super Timer Unit
Maximum
Unit Name Timer/Counter Resolution
Register
CR00
Remark
Count Time
65.5 ms
Timer 0
TM0
1 µs
Controls delay of video head switching signal
Controls delay of audio head switching signal
Controls pseudo VSYNC output timing
(16-bit timer)
CR01
CR02
EC
—
—
ECC0, ECC1,
ECC2, ECC3
CPT0
Creates internal head switching signal
(8-bit counter)
FRC
Free
125 ns
524 ms
Detects reference phase (to control drum phase)
Detects phase of drum motor (to control drum
phase)
running
counter
(22-bit counter)
CPT1
CPT2
CPT3
Detects speed of drum motor (to control drum
speed)
Detects speed of capstan motor (to control speed
of capstan motor)
CPT4, CPT5
CR10
Detects remaining tape for reel FG
Playback: Creates internal reference signal
Recording: Buffer oscillator in case VSYNC is
missing
Timer 1
TM1
1 µs
65.5 ms
(16-bit timer)
CR11
CR12
Controls RECCTL output timing
Detects phase of capstan motor (to control capstan
phase)
CR13
Controls VSYNC mask as noise preventive measures
Controls duty detection timing of PBCTL signal
Measures cycle of PBCTL signal
Divides CFG signal frequency
TM3
1 µs or
1.1 µs
—
65.5 ms or CR30, CR31
(16-bit timer)
EDV
71.5 ms
—
CPT30
EDVC
(8-bit counter)
TM2
Timer 2
Timer 4
1 µs
2 µs
65.5 ms
131 ms
CR20
CR40
CR41
CR50
UDCC
Can be used as interval timer (to control system)
(16-bit timer)
TM4
Detects duty of remote controller signal (to decode
remote controller signal)
(16-bit timer)
Measures cycle of remote controller signal (to de
code remote controller signal)
Timer 5
TM5
2 µs
—
131 ms
—
Can be used as interval timer (to control system)
(16-bit timer)
UDC
Up/down
counter
PWM
Creates linear tape counter
(5-bit counter)
—
—
—
PWM0, PWM1, 16-bit resolution (carrier frequency: 62.5 kHz)
output unit
PWM5
PWM2, PWM3, 8-bit resolution (carrier frequency: 62.5 kHz)
PWM4
36
Data Sheet U12255EJ2V1DS
µPD784927, 784928, 784927Y, 784928Y
(1) Timer 0 unit
Timer 0 unit creates head switching signal and pseudo VSYNC output timing from the PG and FG signals of the
drum motor.
This unit consists of an event counter (EC: 8 bits), compare registers (ECC0 through ECC3), a timer (TM0:
16 bits), and compare registers (CR00 through CR02).
A signal indicating coincidence between the value of timer 0 and the value of a compare register can be used
as the output trigger of the real-time output port.
(2) Free running counter unit
The free running counter unit detects the speed and phase of the drum motor, and the speed and reel speed
of the capstan motor.
This unit consists of a free running counter (FRC), capture registers (CPT0 through CPT5), a VSYNC separation
circuit, and a HSYNC separation circuit.
(3) Timer 1 unit
Timer 1 unit is a reference timer unit synchronized with the frame cycle and creates the RECCTL signal, detects
the phase of the capstan motor, and detects the duty factor of the PBCTL signal. This unit consists of the
following three groups:
•
•
•
Timer 1 (TM1), compare registers (CR10, CR11, and CR13), and capture register (CR12)
Timer 3 (TM3), compare registers (CR30 and CR31), and capture register (CPT30)
Event divider counter (EDV) and compare register (EDVC)
The TM1-CR13 coincidence signal can be used for automatic unmasking of VSYNC or as the output trigger of
the real-time output port.
Data Sheet U12255EJ2V1DS
37
Figure 3-10. Block Diagram of Super Timer Unit (TM0, FRC, TM1)
DPGIN
DFGIN
Divider
Mask
Selector
Clear
TM0
Writes
Output control circuit
Output control circuit
Output control circuit
PTO00
PTO01
PTO02
00H to EC
INTCR00
INTCR01
INTCR02
RTP
Clear
EC
CR00
CR01
CR02
RTP, A/D
RTP, A/D
ECC3
ECC2
ECC1
ECC0
F/F
F/F
(Superimposition)
(Superimposition)
H
circuit
SYNC separation
To P80
V
SYNC separation
circuit
CSYNCIN
INTCLR1
µ
FRC
CPT0
CPT1
CPT2
CPT3
CPT4
CPT5
Capture
Capture
Capture
Capture
Capture
Mask
REEL0IN
REEL1IN
INTCPT1
INTCPT2
INTCPT3
Capture
INTP3
Clear
CFGIN
EDV
Output control circuit
PTO10
PTO11
Clear
TM1
INTCR10
EDVC
CR10
CR11
CR12
CR13
Output control circuit
PBCTL
PTO10
PTO11
INTCR11
INTCR12
INTCR13
Clear
TM3
Capture
FFLVL
CR30
CR31
CPT30
INTCR30 To PBCTL signal
input block
CTL
F/F
Capture
µPD784927, 784928, 784927Y, 784928Y
(4) Timer 2 unit
Timer 2 unit is a general-purpose 16-bit timer unit.
This unit consists of a timer (TM2) and a compare register (CR20).
The timer is cleared when the TM2-CR20 coincidence signal occurs, and at the same time, an interrupt request
is generated.
Figure 3-11. Block Diagram of Timer 2 Unit
Clear
TM2
INTCR20
CR20
(5) Timer 4 unit
Timer 4 unit is a general-purpose 16-bit timer unit.
This unit consists of a timer (TM4), a capture/compare register (CR40), and a capture register (CR41).
The value of the timer is captured to CR40/CR41 when the INTP2 signal is input. This timer can be used to
decode a remote controller signal.
Figure 3-12. Block Diagram of Timer 4 Unit
Mask
Clear
TM4
INTCR40
CR40
CR41
INTP2
(6) Timer 5 unit
Timer 5 unit is a general-purpose 16-bit timer unit.
This unit consists of a timer (TM5) and a compare register (CR50).
The timer is cleared by the TM5-CR50 coincidence signal, and at the same time, an interrupt request is
generated.
Figure 3-13. Block Diagram of Timer 5 Unit
Clear
TM5
INTCR50
RTP, A/D
CR50
Data Sheet U12255EJ2V1DS
39
µPD784927, 784928, 784927Y, 784928Y
(7) Up/down counter unit
The up/down counter unit is a counter that realizes a linear time counter.
This unit consists of an up/down counter (UDC) and a compare register (UDCC).
The up/down counter counts up the rising edges of PBCTL and counts down the falling edges of PBCTL. When
the value of the up/down counter coincides with the value of the compare register, or when the counter
underflows, an interrupt request is generated.
Figure 3-14. Block Diagram of Up/Down Counter Unit
SELUD
PTO10
PTO11
P77
UP/DOWN
UDC
EDVC output
PBCTL
UDCC
INTUDC
(8) PWM output unit
The PWM output unit has three 16-bit accuracy output lines (PWM0, PWM1, and PWM5) and 8-bit accuracy
output lines (PWM2 through PWM4). The carrier frequency of all the output lines is 62.5 kHz (fCLK = 8 MHz).
PWM0 and PWM1 can be used to control the drum motor and capstan motor.
Figure 3-15. Block Diagram of 16-Bit PWM Output Unit
(n = 0, 1, 5)
Internal bus
16
8
PWMn
15
8
7
0
PWMC0
8
8
To selector
Reload
Reload
Reload control
PWM pulse
generation circuit
16 MHz
8-bit down counter
PWMn
Output control
circuit
1/256
8-bit counter
RESET
40
Data Sheet U12255EJ2V1DS
µPD784927, 784928, 784927Y, 784928Y
Figure 3-16. Block Diagram of 8-Bit PWM Output Unit
Internal bus
PWM2
PWM3
PWM4
PWMC1
8-bit comparator
8-bit comparator
PWM counter
8-bit comparator
Output control
circuit
PWM4
PWM3
PWM2
16 MHz
Output control
circuit
Output control
circuit
(9) VISS detection circuit
Figure 3-17. Block Diagram of VISS Detection Circuit
PBCTL
UP/DOWN
CFG signal
VUDST
(VUDC value
setting register)
f
CLK/16
CLK/64
VUDC
(8-bit up/down counter)
f
fCLK/256
VISS malfunction
prevention circuit
VSFT0
(shift register 0)
VSFT1
(shift register 1)
Coincidence
INTVISS
VPS
VCMP
(compare register)
(VISS pulse pattern
setting register)
Data Sheet U12255EJ2V1DS
41
µPD784927, 784928, 784927Y, 784928Y
(10) VSYNC separation circuit
Figure 3-18. Block Diagram of VSYNC Separation Circuit
CSYNC signal
Digital noise rejection circuit
f
CLK/4
CLK/8
VSUDC
(8-bit up/down
counter)
f
V
SYNC F/F
VSCMP
(8-bit compare
register)
V
SYNC
S
Q
R
"00"
3.7 Serial Interface
The µPD784927 is provided with the serial interfaces shown in Table 3-6.
Data can be automatically transmitted or received through these serial interfaces, when the macro service is used.
Table 3-6. Types of Serial Interfaces
Name
Function
Serial interface channel 1
•
•
•
Clocked serial interface (3-wire)
Bit length: 8 bits
Clock rate: External clock/31.25 kHz/62.5 kHz/125 kHz/250 kHz/500 kHz/1 MHz
(fCLK = 8 MHz)
•
MSB first/LSB first selectable
Serial interface channel 2
•
•
•
Clocked serial interface (3-wire)
Bit length: 8 bits
Clock rate: External clock/31.25 kHz/62.5 kHz/125 kHz/250 kHz/500 kHz/1 MHz
(fCLK = 8 MHz)
•
•
MSB first/LSB first selectable
BUSY/STRB control function
Serial interface channel 3
•
I2C bus interface
For multimaster
42
Data Sheet U12255EJ2V1DS
µPD784927, 784928, 784927Y, 784928Y
(1) Serial interface channels 1, 2
Figure 3-19. Block Diagram of Serial Interface Channel n (n = 1 or 2)
Internal bus
SIn /BUSY
SOn
SIOn register
CSIMn register
Serial clock counter
INTCSIn
SCKn
f
f
f
f
f
f
CLK/8
CLK/16
CLK/32
CLK/64
CLK/128
CLK/256
Busy detection circuit
Strobe generation circuit
STRB
CSIC2 register
Internal bus
Remark The circuits enclosed in the broken line are provided to serial interface channel 2 only.
Data Sheet U12255EJ2V1DS
43
µPD784927, 784928, 784927Y, 784928Y
(2) Serial interface channel 3 (µPD784928Y subseries only)
This channel transfers 8-bit data with multiple devices using two lines: serial clock (SCL) and serial data bus
(SDA).
It conforms to the I2C bus format, and can output a “start condition”, “data”, and “stop condition” onto the serial
data bus during transmission. This data is automatically detected by hardware during reception.
SCL and SDA are open-drain output pins and therefore, must be connected with a pull-up resistor.
Figure 3-20. Serial Interface Channel 3
+VDD+VDD
Master CPU2
Slave CPU2
Serial data bus
SDA
SCL
SDA
SCL
Master CPU1
Slave CPU1
Serial clock
Address 1
SDA
SCL
Slave CPU3
Address 2
SDA
SCL
Slave IC
Address 3
SDA
SCL
Slave IC
Address N
44
Data Sheet U12255EJ2V1DS
µPD784927, 784928, 784927Y, 784928Y
3.8 A/D Converter
The µPD784927Y has an analog-to-digital (A/D) converter with 12 multiplexed analog inputs (ANI0 through ANI11).
This A/D converter is of successive approximation type, and the conversion result is held by an 8-bit A/D conversion
result register (ADCR) (conversion time: 10 µs at fCLK = 8 MHz).
A/D conversion can be started in the following two modes:
• Hardware start: Conversion is started by a hardware triggerNote
.
• Software start : Conversion is started by setting a bit of the A/D converter mode register (ADM).
After conversion has been started, the A/D converter operates in the following modes:
• Scan mode : Sequentially selects more than one analog input to obtain data to be converted from all the pins.
• Select mode: Use only one pin for analog input to obtain successive data to be converted.
When the conversion result is transferred to ADCR, interrupt request INTAD is generated. By processing this
interrupt with the macro service, the conversion result can be successively transferred to memory.
A mode in which starting A/D conversion of the next pin is kept pending until the value of ADCR is read is also
available. When this ode is used, reading the conversion result by mistake when timing is shifted because an interrupt
is disabled can be prevented.
Note A hardware trigger is the following coincidence signals, one of which is selected by the trigger source select
register 1 (TRGS1):
• TM0-CR01 coincidence signal
• TM0-CR02 coincidence signal
• TM1-CR13 coincidence signal
• TM5-CR50 coincidence signal
Data Sheet U12255EJ2V1DS
45
µPD784927, 784928, 784927Y, 784928Y
Figure 3-21. Block Diagram of A/D Converter
ADM.7 (CS)
ANI0
ANI1
ANI2
Series resistor string
1 : ON
Sample & hold circuit
AVREF
ANI3
R/2
R
Voltage
comparator
.
.
.
.
.
.
ANI11
Successive approximation
register (SAR)
R/2
Conversion
trigger
TM0-CR01 coincidence
TM0-CR02 coincidence
TM1-CR13 coincidence
TM5-CR50 coincidence
AVSS2
Control circuit
INTAD
A/D conversion
end interrupt
8
Trigger
enable
Delay detection
circuit
Trigger source select register 1
(TRGS1)
A/D conversion result
register (ADCR)
A/D converter mode
register (ADM)
8
16
Internal bus
3.9 VCR Analog Circuits
The µPD784927 is provided with the following VCR analog circuits:
• CTL amplifier
• RECCTL driver (rewritable)
• DPG amplifier
• DFG amplifier
• DPFG separation circuit (ternary separation circuit)
• CFG amplifier
• Reel FG comparator (2 channels)
• CSYNC comparator
46
Data Sheet U12255EJ2V1DS
µPD784927, 784928, 784927Y, 784928Y
(1) CTL amplifier/RECCTL driver
The CTL amplifier is used to amplify the playback control (PBCTL) signal that is reproduced from the CTL signal
recorded on a VCR tape.
The gain of the CTL amplifier is set by the gain control register (CTLM). Thirty-two types of gains can be set
in increments of about 1.78 dB.
The µPD784927 is also provided with a gain control signal generation circuit that monitors the status of the
amplifier output to perform optimum gain control by software. The gain control signal generation circuit
generates a CTL detection flag that identifies the amplitude status of the CTL amplifier output. By using this
CTL detection flag, the gain of the CTL amplifier can be optimized.
The RECCTL driver writes a control signal onto a VCR tape.
This driver operates in two modes: REC mode that is used for recording, and rewrite mode used to rewrite
the VISS signal. The output status of the RECCTL pin is changed by hardware, by using the timer output
from the super timer unit as a trigger.
Figure 3-22. Block Diagram of CTL Amplifier and RECCTL Driver
ANI11
CTLDLY
TOM1.4-TOM1.6
RECCTL+
TM1-CR11 coincidence signal
TM1-CR13 coincidence signal
TM3-CR30 coincidence signal
RECCTL driver
AMPC. 1
RECCTL
-
CTL head
V
REF
+
-
AMPC. 1
CTL detection flag L (AMPM0. 1)
CTL detection flag S (AMPM0. 3)
CTL detection flag clear
(1 write to AMPM0. 6)
+
Gain control signal
generation circuit
CTLIN
-
CTLOUT1
CTLM. 0-CTLM. 4
Waveform
shaping circuit
PBCTL signal (to timer unit)
CTLMON (to P67)
CTLOUT2
Data Sheet U12255EJ2V1DS
47
µPD784927, 784928, 784927Y, 784928Y
(2) DPG amplifier, DFG amplifier, and DFPG separation circuit
The DPG amplifier converts the drum PG (DPG) signal that indicates the phase information of the drum motor
into a logic signal.
The DFG amplifier amplifies the drum FG (DFG) signal that indicates the speed information of the drum motor.
The DPFG separation circuit (ternary separation circuit) separates a drum PFG (DPFG) signal having speed
and phase information into a DFG and DPG signals.
Figure 3-23. Block Diagram of DPG Amplifier, DFG Amplifier, and DPFG Separation Circuit
AMPC.7
V
REF
AMPM0.2
AMPC.2
AMPC.2
AMPM0.0
DPGIN
0 : ON
1
0
Drum PG signal
1
V
REF
DPG signal
(to timer unit)
DPG
comparator
+
0
DPGMON
(to P65)
–
DPG amplifier
V
REF
AMPC.2
+
AMPM0.0
DFGIN
DFG amplifier
Drum FG signal or
drum PFG signal
–
AMPM0.2
AMPM0.2
AMPC.2
0
1
AMPC.2
DPFG separation
circuit (ternary
separation circuit)
1
0
1
DFG signal
(to timer unit)
AMPM0.2
0
DFGMON
(to P64)
48
Data Sheet U12255EJ2V1DS
µPD784927, 784928, 784927Y, 784928Y
(3) CFG amplifier
The CFG amplifier amplifies the capstan FG (CFG) signal that indicates the speed information of the capstan
motor. This amplifier consists of an operational amplifier and a comparator. The gain of the operational
amplifier is set by using an external resistor.
When the gain of the operational amplifier is set to 50 dB, the output duty accuracy of the CFG signal can be
improved to 50.0 0.3%.
Figure 3-24. Block Diagram of CFG Amplifier
VREF
AMPC.3
+
CFG amplifier
-
Capstan FG signal
CFGIN
CFGAMPO
VREF
AMPM0.0
AMPC.3
AMPC.3
CFG
comparator
-
1
CFGCPIN
CFG signal
(to timer unit)
+
0
CFGMON
(to P66)
(4) Reel FG comparators
The reel FG comparator converts a reel FG signal that indicates the speed information of the reel motor into
a logic signal. Two comparators, one for take-up and the other for supply, are provided.
Figure 3-25. Block Diagram of Reel FG Comparators
VREF
AMPC.6
AMPM0.0
REEL0IN
1
0
Supply reel signal
Reel FG0 signal
(to timer unit)
Reel FG comparator
VREF
AMPC.6
AMPC.6
AMPM0.0
REEL1IN
1
0
Take-up reel signal
Reel FG1 signal
(to timer unit)
Reel FG comparator
Data Sheet U12255EJ2V1DS
49
µPD784927, 784928, 784927Y, 784928Y
(5) CSYNC comparator
The CSYNC comparator converts the COMPSYNC signal into a logic signal.
Figure 3-26. Block Diagram of COMPSYNC Comparator
VREF
AMPM1.7
AMPC.5
AMPC.5
AMPM0.0
CSYNCIN
1
COMPSYNC signal
C
SYNC signal
CSYNC comparator
(to timer unit)
0
(6) Reference amplifier
The reference amplifier generates a reference voltage (VREF) to be supplied to the internal amplifiers and
comparators of the µPD784927.
Figure 3-27. Block Diagram of Reference Amplifier
ENCAP (AMPC.3)
AVDD1
-
VREFC
V
REF (CFG amplifier)
+
-
AVSS1
V
REF (CFG amplifier)
+
ENCTL (AMPC.1)
-
V
REF (CTL amplifier)
ENDRUM (AMPC.2)
+
ENREEL (AMPC.6)
ENCSYN (AMPC.5)
-
V
REF DFG amplifier, DPG comparator,
reel FG comparator, and CSYNC
comparator)
+
Remark Multiple reference amplifiers are provided to assure the accuracy of the amplifiers and comparators.
50
Data Sheet U12255EJ2V1DS
µPD784927, 784928, 784927Y, 784928Y
(7) Analog circuit monitor function
This function is to output the following signals to port pins, and is mainly used for debugging.
•
•
•
•
Comparator output of CTL amplifier → CTLMON (multiplexed port: P67)
Comparator output of CFG amplifier → CFGMON (multiplexed port: P66)
Comparator output of DPG amplifier → DPGMON (multiplexed port: P65)
Comparator output of DFG amplifier → DFGMON (multiplexed port: P64)
3.10 Watch Function
The µPD784927 has a watch function that counts the overflow signals of the watch timer by hardware. As the clock,
the subsystem clock (32.768 kHz) is used.
Because this watch function is independent of the CPU, it can be used even while the CPU is in the standby mode
(STOP mode) or is reset. In addition, this function can be used at a low voltage of VDD = 2.7 V (MIN.).
Therefore, by using only the watch function with the CPU set in the standby mode or reset, a watch operation can
be performed at a low voltage and low current consumption.
In addition, the watch function can also be used while the CPU is in the normal operation mode, because a dedicated
counter is provided.
The watch function can be used to count up to about 17 years of data.
The hardware watch counters (HW0 and HW1) are shared with external input counters. These counters execute
counting at the falling edge of input to the P65 pin, and can be used to count the HSYNC signals.
Figure 3-28. Block Diagram of Watch Counter
PM65
PMC65
CMS5
Edge detection
P65
P65
Pin level read
WM.2
WM.2
(enables/disables operation)
(enables/disables operation)
1
0
0
13
0
15
0
13
0
Normal
1
fXT
(32.768 kHz)
Watch timer
HW0
HW1
WM.2
Fast
forward
To NMI generation block
WM.1
Subclock
BUZ signal
WM.6
INTW
WM.7
WM.5
WM.4
WM.2
Data Sheet U12255EJ2V1DS
51
µPD784927, 784928, 784927Y, 784928Y
3.11 Clock Output Function
The µPD784927 can output a square wave (with a duty factor of 50%) to the P60/STRB/CLO pin as the operating
clock for the peripheral devices or other microcomputers. To enable or disable the clock output, and to set the
frequency of the clock, the clock output mode register (CLOM) is used.
When setting the frequency, the division ratio can be set to fCLK/n (where n = 1, 2, 4, 8, 16, 32, 64, or 128) (fCLK
= fOSC/2: fOSC is the oscillation frequency of the resonator).
Figure 3-29 shows the block diagram of the clock output circuit.
The clock output (CLO) pin is shared with P60 and STRB.
Figure 3-29. Block Diagram of Clock Output Circuit
CLOM CLOM7 CLOM6 CLOM5 ENCLO
0
SELFRQ2 SELFRQ1 SELFRQ0
fCLK
f
f
f
CLK/2
CLK/4
CLK/8
1
f
f
f
CLK/16
CLK/32
CLK/64
P60/STRB/CLO
0
P60
(Output latch)
RESET
f
CLK/128
Remark fCLK: internal system clock
Caution Do not use the clock output function in the STOP mode. Clear ENCLO (CLOM.4) to 0 in the STOP
mode.
Figure 3-30. Application Example of Clock Output Function
µ
PD784927
µPD7503A
LCD
24
System clock
CLO
SCK1
SI1
CL1
SCK
SO
SI
SO1
52
Data Sheet U12255EJ2V1DS
µPD784927, 784928, 784927Y, 784928Y
3.12 Buzzer Output Function
The BUZ signal can be superimposed on P61 or P64.
The buzzer output frequency can be generated from the subsystem clock frequency or main system clock
frequency.
Figure 3-31 shows the block diagram of the BUZ output circuit.
The BUZ signal can be also used for trimming the subsystem clock.
Figure 3-31. Block Diagram of BUZ Output Circuit
WM4
CMS4
WM5
WM7
2.048 kHz
0
1
4.096 kHz
P61
(Output latch)
CLOM7
P61/BUZ
32.768 kHz
0
1
BUZ output
CLOM5
CLOM6
f
CLK/512
0
P64
(Output latch)
f
f
f
CLK/1024
CLK/2048
CLK/4096
P64/BUZ
1
BUZ output
Data Sheet U12255EJ2V1DS
53
µPD784927, 784928, 784927Y, 784928Y
4. INTERNAL/EXTERNAL CONTROL FUNCTION
4.1 Interrupt Function
The µPD784927 has as many as 32 interrupt sources, including internal and external sources. For 28 sources,
a high-speed interrupt processing mode such as context switching or macro service can be specified by software.
Table 4-1 lists the interrupt sources.
54
Data Sheet U12255EJ2V1DS
µPD784927, 784928, 784927Y, 784928Y
Table 4-1. Interrupt Sources
Interrupt
Control
Register
Name
Interrupt
Macro Context Macro Service Vector
Service Switching Control Word Table
Address Address
Interrupt Request Source
Trigger
Request Priority
Type
Name
Reset
—
—
RESET RESET pin input
—
—
No
No
—
—
0000H
0002H
Non-
NMI
NMI pin input edge
maskable
Maskable
0
1
2
3
INTP0
INTP0 pin input edge
PIC0
Yes
Yes
FE06H
FE08H
FE0AH
FE0CH
0006H
0008H
000AH
000CH
INTCPT3 EDVC output signal (CPT3 capture)
INTCPT2 DFGIN pin input edge (CPT2 capture)
INTCR12 PBCTL input edge/EDVC output signal
(CR12 capture)
CPTIC3
CPTIC2
CRIC12
4
5
INTCR00 TM0-CR00 coincidence signal
INTCLR1 CSYNCIN pin input edge
INTCR10 TM1-CR10 coincidence signal
INTCR01 TM0-CR01 coincidence signal
INTCR02 TM0-CR02 coincidence signal
INTCR11 TM1-CR11 coincidence signal
INTCPT1 Pin input edge/EC output signal
(CPT1 capture)
CRIC00
CLRIC1
CRIC10
CRIC01
CRIC02
CRIC11
CPTIC1
FE0EH
FE10H
FE12H
FE14H
FE16H
FE18H
FE1AH
000EH
0010H
0012H
0014H
0016H
0018H
001AH
6
7
8
9
10
11
12
13
14
15
INTCR20 TM2-CR20 coincidence signal
CRIC20
IICICNote
TBIC
FE1CH
FE1EH
FE20H
FE22H
FE24H
001CH
001EH
0020H
0022H
0024H
INTIIC
INTTB
End of I2C bus transfer
Time base from FRC
INTAD A/D converter conversion end
INTP2 INTP2 pin input edge
ADIC
PIC2
INTCR40 TM4-CR40 coincidence signal
INTUDC UDC-UDCC coincidence/UDC underflow
INTCR30 TM3-CR30 coincidence signal
INTCR50 TM5-CR50 coincidence signal
INTCR13 TM1-CR13 coincidence signal
INTCSI1 End of serial transfer (channel 1)
CRIC40
UDCIC
CRIC30
CRIC50
CRIC13
CSIIC1
WIC
16
17
18
19
20
21
22
23
24
25
—
FE26H
FE28H
FE2AH
FE2CH
FE2EH
FE30H
FE32H
FE34H
FE36H
FE3AH
—
0026H
0028H
002AH
002CH
002EH
0030H
0032H
0034H
0036H
003AH
003CH
INTW
Overflow of watch timer
INTVISS VISS detection signal
VISIC
PIC1
INTP1
INTP3
INTP1 pin input edge
INTP3 pin input edge
PIC3
INTCSI2 End of serial transfer (channel 2)
CSIIC2
—
Operand
error
—
Illegal operand of MOV STBC, #byte or
LOCATION instruction
No
No
Software
—
—
—
—
Execution of BRK instruction
Execution of BRKCS instruction
—
—
—
—
003EH
—
Yes
Note µPD784928Y subseries only.
Remark EVDC : Event divider compare register
EC
: Event counter
FRC : Free running counter
MSCW: Macro service control register
Data Sheet U12255EJ2V1DS
55
µPD784927, 784928, 784927Y, 784928Y
Figure 4-1. Differences in Operation Depending on Interrupt Processing Mode
Main
routine
Macro service
processing
Main routine
Macro service
Context
Interrupt
processing
Main
routine
Note 2
Note 4
Note 4
Note 3 Main routine
switchingNote 1
Vectored
interruptNote 1
Restoring
PC and
PSW
SEL
Interrupt
Main
routine
Main routine
RBn
processing
Initializing
general-purpose
register
Saving
general-purpose
register
Restoring
general-purpose
register
Restoring
PC and
PSW
Interrupt
processing
Main
routine
Main
routine
Vectored interrupt
Interrupt request generated
Notes 1. When the register bank switching function is used and when initial values are set in advance to the
registers
2. Selecting a register bank and saving PC and PSW by context switching
3. Restoring register bank, PC, and PSW by context switching
4. Saves PC and PSW to stack and loads vector address to PC
56
Data Sheet U12255EJ2V1DS
µPD784927, 784928, 784927Y, 784928Y
4.1.1 Vectored interrupt
When an interrupt request is acknowledged, an interrupt processing program is executed according to the data
stored in the vector table area (the first address of the interrupt processing program created by the user).
In addition, four levels of priorities can be specified by software.
4.1.2 Context switching
When an interrupt request is generated or when the BRKCS instruction is executed, a specific register bank is
selected by hardware, and execution branches to a vector address set in advance in the register bank. At the same
time, the current contents of the program counter (PC) and program status word (PSW) are saved to the registers
in the register bank. Because the contents of PC and PSW are not saved to the stack area, execution can be branched
to an interrupt processing routine more quickly than the vectored interrupt.
Figure 4-2. Context Switching Operation When Interrupt Request Is Generated
Register bank
(0-7)
<7> 0H
Register bank n (n = 0-7)
PC19-16
PC15-0
A
B
X
C
<6> Exchange
R5
R7
R4
R6
<2> Save
Bits 8-11 of temporary
register
<3> Switching register bank
(RBS0-RBS2 ← n)
<4> RSS ← 0
<5> Save
V
U
T
VP
UP
Temporary register
<1> Save
PSW
IE ← 0
D
H
E
L
W
Data Sheet U12255EJ2V1DS
57
µPD784927, 784928, 784927Y, 784928Y
4.1.3 Macro service
The macro service is a function to transfer data between the memory and a special function register (SFR) without
intervention by the CPU. A macro service controller accesses the memory and SFR and directly transfers the data.
Because the status of the CPU is not saved or restored, data can be transferred more quickly than context switching.
The processing that can be executed with the macro service is described below.
Figure 4-3. Macro Service
Read
Write
Write
Read
Macro service
controller
CPU
Memory
SFR
Internal bus
(1) Counter mode
In this mode, the value of the macro service counter (MSC) is decremented when an interrupt request occurs.
This mode can be used to execute the division operation of an interrupt request or count the number of times
an interrupt request has occurred.
When the value of the macro service counter has been decremented to 0, a vectored interrupt occurs.
MSC
-1
(2) Compound data transfer mode
When an interrupt request occurs, data are simultaneously transferred from an 8-bit SFR to memory, a 16-
bit SFR to memory (word), memory (byte) to an 8-bit SFR, and memory (word) to a 16-bit SFR (3 points MAX.
for each transfer).
This mode can also be used to exchange data, instead of transferring data.
This mode can be used for automatic transfer/reception by the serial interface or automatic updating of data/
timing by the serial output port.
When the value of the macro service counter reaches to 0, a vectored interrupt request occurs.
Memory
.
.
SFR<4>-1 SFR<4>-2 SFR<4>-3
SFR<2>-1 SFR<2>-2 SFR<2>-3
SFR<3>-1
SFR<3>-2
SFR<1>-2
SFR<3>-3
SFR<1>-3
.
Internal bus
SFR<1>-1
Internal bus
58
Data Sheet U12255EJ2V1DS
µPD784927, 784928, 784927Y, 784928Y
(3) Macro service type A
When an interrupt request occurs, data is transferred from an 8-/16-bit SFR to memory (byte/word) or from
memory (byte/word) to an 8-/16-bit SFR.
Data is transferred the number of times set in advance by the macro service counter.
This mode can be used to store the result of A/D conversion or for automatic transfer (or reception) by the
serial interface.
Because transfer data is stored at an address FE00H to FEFFH, if only a small quantity of data is to be
transferred, the data can be transferred at high speeds.
When the value of the macro service counter is decremented to 0, a vectored interrupt request occurs.
Data storage buffer (memory)
Data n
Data storage buffer (memory)
Data n
Data n
-
1
Data n -1
Data 2
Data 1
Data 2
Data 1
Internal bus
SFR
Internal bus
SFR
(4) Data pattern identification mode (VISS detection mode)
This mode of macro service is for detection of the VISS signal and is used in combination with a pulse width
detection circuit.
When an interrupt request occurs, the content of bit 7 of an SFR (usually, TMC3) specified by SFR pointer
1 is shifted into the buffer area. At the same time, the data in the buffer area is compared with the data in
the compare area. If the two data coincide, a vectored interrupt request is generated. When the value of the
macro service counter is decremented to 0, a vectored interrupt request occurs.
It can be specified by option that the value of an SFR (usually, CPT30) specified by SFR pointer 2 be multiplied
by a coefficient and the result of this multiplication be stored to an SFR (usually, CR30) specified by SFR pointer
3 (this operation is to automatically update an identification threshold value when the tape speed fluctuates).
Buffer area (memory)
Compare area (memory)
Coefficient (memory)
CPT30
TM3
Multiplier
Coincidence
CR30
Vectored interrupt
CTL F/F
(bit 7 of TMC3)
Data Sheet U12255EJ2V1DS
59
µPD784927, 784928, 784927Y, 784928Y
4.1.4 Application example of macro service
(1) Automatic transfer/reception of serial interface
Automatic transfer/reception of 3-byte data by serial interface channel 1
Setting of macro service register: compound data transfer mode (exchange mode)
7
0
FE50H
High-order address
Macro service counter (MSC = 2)
Memory pointer H (= FD)
Memory pointer L (= 50)
ddccbbaa (= 01000100B)
SFR pointer <2> (SFRP2 = 85H)
SFR pointer <4> (SFRP4 = 85H)
Macro service channel
Channel pointer (= 50H)
Macro service control word
Mode register (= 10110011B) FE2EH
Low-order address
(Before transfer)
(Exchange 2)
SI1
Transmit data 3 FD52H
SIO1 (FF85H)
<3>
SO1
Transmit data 2 FD51H
<2>
(Transmit data 1) FD50H
(Exchange 1)
<1> Transfer is started by writing
transmit data 1 to SIO1 by
software.
(After transfer)
Receive data 2 FD51H
Receive data 1 FD50H
(Receive data 3 is the data of SIO1.)
60
Data Sheet U12255EJ2V1DS
µPD784927, 784928, 784927Y, 784928Y
(2) Reception operation of serial interface
Transfer of receive data by serial interface channel 1 (16 bytes)
Setting of macro service mode register: macro service type A (1-byte data transfer from SFR to memory)
Internal RAM
MSC 0FH
Setting of number of transfers
FE7FH
SFR pointer 85H
Low-order 8 bits of address of SIO1 register
Channel pointer (= 7FH)
FE2EH Mode register (= 00010001B) Starts macro service when INTCSI1 occurs
SIO1
(FF85H)
SI1
Data Sheet U12255EJ2V1DS
61
µPD784927, 784928, 784927Y, 784928Y
(3) VISS detection operation
Setting of macro service mode register: data pattern identification mode (with multiplication, 8-byte compari-
son)
CPT30
High-order address
TM3
Macro service counter (MSC = FFH)
SFR pointer 2 (SFRP2 = 56H)
Coefficient (6EH: 43%)
FE50H
Multiplier
CR30
TMC3
SFR pointer 3 (SFRP3 = 5CH)
SFR pointer 1 (SFRP1 = 3BH)
Bit 7
0
Buffer size specification
register (64 bits: 8H)
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1050H
8 bytes
8 bytes
1
1
1
1
1
1
1
0
Compare area pointer (high): 10H
Compare area pointer (low): 50H
Coincidence (vectored interrupt)
Channel pointer (= 50H)
FE0CH Mode register (= 00010100B) (CTL signal input edge detection interrupt)
Low-order address
62
Data Sheet U12255EJ2V1DS
µPD784927, 784928, 784927Y, 784928Y
4.2 Standby Function
The standby function is to reduce the power consumption of the chip and is used in the following modes:
Mode
Function
HALT mode
STOP mode
Stops operating clock of CPU. Reduces average power consumption when used
in combination with normal mode for intermittent operation
Stops oscillator. Stops all internal operations of chip to minimize power consump-
tion to leakage current only
Low power consumption mode
Stops main system clock with subsystem clock used as system clock. CPU can
operate with subsystem clock to reduce current consumption
Low power consumption HALT mode
Standby function in low power consumption mode. Stops operating clock of CPU.
Reduces power consumption of overall system
These modes are programmable.
The macro service can be started in the HALT mode.
Figure 4-4. Status Transition of Standby Function
Sets low power consumption mode
Restores normal operation
Low power
consumption mode
(subsystem
Normal
operation
clock operation)
Macro
service
Waits for
stabilization
of oscillation
Low power
consumption
HALT mode
(standby)
STOP mode
(standby)
HALT mode
(standby)
Unmasked
interrupt request
Notes 1. NMI input means starting NMI by NMI pin input, watch interrupt, or key interrupt input.
2. Unmasked interrupt request
Data Sheet U12255EJ2V1DS
63
µPD784927, 784928, 784927Y, 784928Y
Figure 4-5. Relations among NMI, Watch Interrupt, and Key Interrupt When STOP Mode Is Released
INTM0.0
Standby control
block
NMI
Latch
Interrupt control
Clear
block
INTP1
INTP2
KEY0
KEY1
KEY2
KEY3
KEY4
S
R
Q
KEYC.7
Cleared when "0" is
written to KEYC.7
Mask KEYC.6
Mask KEYC.5
Mask KEYC.4
S
R
Q
KEYC.0
WM.6
Cleared when "0" is
written to KEYC.0
Watch timer
INTW (OVF)
Divides INTW
by 128 (HW0L.7)
Mask WM.3
64
Data Sheet U12255EJ2V1DS
Figure 4-6. Block Diagram of Clock Generation Circuit
CC.7
µ
PD784927
STBC.4, 5
Oscillation stabilization timer
Low-frequency
X1
Main
oscillation mode
XX/16 (fXX/8)Note 1
STBC.6
system
clock
f
f
XX
1/2
1/2
1/2
Normal mode
oscillation
circuit
f
f
XX/8 (fXX/4)Note 1
1/2
X2
XX/4 (fXX/2)Note 1
16 MHz or 8 MHz
Oscillation stop
CPU
f
CLK
From standby control block
Note 1
f
XX/2 (fXX)
Peripheral hardware
operation clockNote 2
XT1
Subsystem
f
XT
clock
Watch timer
Hardware watch function
Watch interrupt
oscillation
circuit
µ
XT2
32.768 kHz
Oscillation stop
STBC.7
Notes 1. fXX: oscillation frequency, ( ): in low-frequency oscillation mode.
2. The peripheral hardware units that can operate with the subsystem clock have some restrictions. For details, refer to µPD784928,
784928Y Subseries User’s Manual-Hardware (U12648E).
µPD784927, 784928, 784927Y, 784928Y
4.4 Reset Function
When a low-level signal is input to the RESET pin, the system is reset, and each hardware unit is initialized (reset
status). During the reset period, oscillation of the system clock is unconditionally stopped, so that the current
consumption of the overall system can be reduced.
When the RESET pin goes high, the reset status is cleared. After the count time of the oscillation stabilization timer
(32.8 ms at 16 MHz or 65.6 ms at 8 MHz) has elapsed, the contents of the reset vector table are set to the program
counter (PC), and execution branches to the address set to the PC, and the program is executed starting from the
branch destination address. Therefore, execution can be reset and started from any address.
Figure 4-7. Oscillation of Main System Clock during Reset Period
Main system clock
oscillation circuit
During reset, oscillation
is unconditionally stopped.
f
CLT
RESET input
Oscillation stabilization
timer count time
The RESET pin is provided with an analog delay noise rejection circuit to prevent malfunctioning due to noise.
Figure 4-8. Accepting Reset Signal
Oscillation
stabilization
time
Analog
delay
Analog delay
Analog delay
RESET input
Internal reset signal
Internal clock
66
Data Sheet U12255EJ2V1DS
µPD784927, 784928, 784927Y, 784928Y
5. INSTRUCTION SET
(1) 8-bit instructions (( ): combination realized by using A as r)
MOV, XCH, ADD, ADDC, SUB, SUBC, AND, OR, XOR, CMP, MULU, DIVUW, INC, DEC, ROR, ROL, RORC,
ROLC, SHR, SHL, ROR4, ROL4, DBNZ, PUSH, POP, MOVM, XCHM, CMPME, CMPMNE, CMPMNC,
CMPMC, MOVBK, XCHBK, CMPBKE, CMPBKNE, CMPBKNC, CMPBKC, CHKL, CHKLA
2nd Operand
# byte
A
r
saddr
saddr'
sfr
!addr16
mem
r3
[WHL+]
[WHL–]
n
NoneNote 2
r'
!!addr24 [saddrp]
PSWL
1st Operand
A
[%saddrg] PSWH
Note 6
(MOV)
(MOV)
(XCH)
MOV
XCH
(MOV)
MOV
(MOV)
(XCH)
MOV
MOV
(MOV)
(XCH)
(MOV)
(XCH)
Note 1
Note 6
1,6
ADD
(XCH)
(XCH)
XCH
Note 1
Note 1
Note 1
Note 1
Note 1
Note 1
Note 1
(ADD)
(ADD)
MOV
XCH
(ADD)Notes
(ADD)
MOV
XCH
ADD
ADD
(ADD)
(ADD)
Note 3
r
MOV
(MOV)
(XCH)
MOV
MOV
XCH
ROR
MULU
DIVUW
INC
Note 1
ADD
XCH
Note 1
(ADD)
ADDNote 1 ADDNote 1 ADDNote 1
DEC
Note 6
saddr
sfr
MOV
ADDNote 1 (ADD)
(MOV)
MOV
ADDNote 1 XCH
MOV
INC
Note 1
Note 1
DEC
ADDNote 1
DBNZ
PUSH
POP
MOV
ADDNote 1 (ADD)
MOV
MOV
ADDNote 1
CHKL
CHKLA
!addr16
!!addr24
mem
MOV
(MOV)
ADDNote 1
MOV
MOV
[saddrp]
[%saddrg]
mem3
ADDNote 1
ROR4
ROL4
r3
MOV
MOV
MOV
PSWL
PSWH
B, C
DBNZ
STBC, WDM
[TDE+]
5
(MOV)
MOVBKNote
Note 1
(ADD)
4
MOVMNote
5
[TDE–]
(MOV)
MOVBKNote
(ADD)Note 1
4
MOVMNote
Notes 1. ADDC, SUB, SUBC, AND, OR, XOR, and CMP are the same as ADD.
2. Either the second operand is not used, or the second operation is not an operand address.
3. ROL, RORC, ROLC, SHR, and SHL are the same as ROR.
4. XCHM, CMPME, CMPMNE, CMPMNC, and CMPMC are the same as MOVM.
5. XCHBK, CMPBKE, CMPBKNE, CMPBKNC, and CMPBKC are the same as MOVBK.
6. If saddr2 instead of saddr is used in this combination, the code length of some instructions is short.
Data Sheet U12255EJ2V1DS
67
µPD784927, 784928, 784927Y, 784928Y
(2) 16-bit instructions (( ): combination realized by using AX as rp)
MOVW, XCHW, ADDW, SUBW, CMPW, MULUW, MULW, DIVUX, INCW, DECW, SHRW, SHLW, PUSH,
POP, ADDWG, SUBWG, PUSHU, POPU, MOVTBLW, MACW, MACSW, SACW
2nd Operand
# word
AX
rp
saddrp
saddrp
sfrp
!addr16
!!addr24
mem
[WHL+]
byte
n
None Note 2
rp'
[saddrp]
[%saddrg]
1st Operand
AX
(MOVM)
ADDWNote 1 (XCHW)
(MOVW)
(MOVW)
(XCHW)
(MOVW)Note 3 MOVW
(MOVW) MOVW
(MOVW)
(XCHW)
Note 3
(
XCHW
)
(XCHW)
(ADDW)Note 1
MOVW
XCHW
XCHW
(ADDW)Note 1 (ADDW)Note 1 (ADDW)Notes
1,3
rp
MOVW
ADDWNote 1 (XCHW)
(MOVW)
MOVW
XCHW
MOVW
XCHW
MOVW
SHRW
SHLW
MULWNote 4
INCW
XCHW
(ADDW)Note 1 ADDWNote 1 ADDWNote 1 ADDWNote 1
(MOVW)Note 3 MOVW
MOVW
ADDWNote 1 (ADDW)Note 1 ADDWNote 1 XCHW
ADDWNote 1
DECW
INCW
saddrp
sfrp
MOVW
DECW
MOVW
MOVW
MOVW
PUSH
POP
ADDWNote 1 (ADDW)Note 1 ADDWNote 1
!addr16
!!addr24
mem
MOVW
(MOVW)
MOVW
MOVW
MOVTBLW
[saddrp]
[%saddrg]
PSW
PUSH
POP
SP
ADDWG
SUBWG
post
PUSH
POP
PUSHU
POPU
[TDE+]
byte
(MOVW)
SACW
MACW
MACSW
Notes 1. SUBW and CMPW are the same as ADDW.
2. Either the second operand is not used, or the second operation is not an operand address.
3. If saddr2 instead of saddr is used in this combination, the code length of some instructions is short.
4. MULUW and DIVUX are the same as MULW.
68
Data Sheet U12255EJ2V1DS
µPD784927, 784928, 784927Y, 784928Y
(3) 24-bit instructions (( ): combination realized by using WHL as rg)
MOVG, ADDG, SUBG, INCG, DECG, PUSH, POP
2nd Operand
# imm24
WHL
rg
saddrg
!!addr24
(MOVG)
MOVG
mem1
MOVG
[%saddrg]
SP
NoneNote
rg'
1st Operand
WHL
(MOVG)
(ADDG)
(SUBG)
MOVG
ADDG
(MOVG)
(ADDG)
(SUBG)
(MOVG)
(ADDG)
(SUBG)
(MOVG)
(ADDG)
(SUBG)
MOVG
ADDG
(MOVG)
ADDG
SUBG
MOVG
MOVG
rg
MOVG
INCG
DECG
PUSH
POP
SUBG
SUBG
saddrg
!!addr24
mem1
(MOVG)
(MOVG)
MOVG
MOVG
MOVG
MOVG
MOVG
[%saddrg]
SP
MOVG
INCG
DECG
Note Either the second operand is not used, or the second operation is not an operand address.
(4) Bit manipulation instructions
MOV1, AND1, OR1, XOR1, SET1, CLR1, NOT1, BT, BF, BTCLR, BFSET
2nd Operand
CY
saddr.bit
sfr.bit
/saddr.bit
/sfr.bit
NoneNote
A.bit
/A.bit
X.bit
/X.bit
PSWL.bit
PSWH.bit
mem2.bit
iaddr16.bit
!addr24.bit
/PSWL.bit
/PSWH.bit
/mem2.bit
/!addr16.bit
/!!addr24.bit
1st Operand
CY
MOV1
AND1
OR1
AND1
OR1
NOT1
SET1
CLR1
XOR1
saddr.bit
sfr.bit
MOV1
NOT1
SET1
CLR1
BF
A.bit
X.bit
PSWL.bit
PSWH.bit
mem2.bit
!addr16.bit
!!addr24.bit
BT
BTCLR
BFSET
Note Either the second operand is not used, or the second operation is not an operand address.
Data Sheet U12255EJ2V1DS
69
µPD784927, 784928, 784927Y, 784928Y
(5) Call/return and branch instructions
CALL, CALLF, CALLT, BRK, RET, RETI, RETB, RETCS, RETCSB, BRKCS, BR, BNZ, BNE, BZ, BE, BNC,
BNL, BC, BL, BNV, BPO, BV, BPE, BP, BN, BLT, BGE, BLE, BGT, BNH, BH, BF, BT, BTCLR, BFSET, DBNZ
Operand of $addr20 $!addr20 !addr16
instruction
!!addr20
rp
rg
[rp]
[rg]
!addr11 [addr5]
RBn
None
address
Note
Basic
BC
CALL
BR
CALL
BR
CALL
BR
CALL
BR
CALL
BR
CALL
BR
CALL
BR
CALLF CALLT BRKCS BRK
instruction BR
RET
RETCS
RETCSB
RETI
RETB
Compound BF
instruction BT
BTCLR
BFSET
DBNZ
Note BNZ, BNE, BZ, BE, BNC, BNL, BL, BNV, BPO, BV, BPE, BP, BN, BLT, BGE, BLE, BGT, BNH, and BH are
the same as BC.
(6) Other instructions
ADJBA, ADJBS, CVTBW, LOCATION, SEL, NOT, EI, DI, SWRS
70
Data Sheet U12255EJ2V1DS
µPD784927, 784928, 784927Y, 784928Y
6. ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings (TA = 25°C)
Parameter
Supply voltage
Symbol
VDD
Conditions
| VDD – AVDD1 | ≤ 0.5 V
Ratings
–0.5 to +7.0
–0.5 to +7.0
–0.5 to +7.0
–0.5 to +0.5
–0.5 to +0.5
–0.5 to VDD + 0.5
–0.5 to AVDD2 + 0.5
–0.5 to VDD + 0.5
–0.5 to VDD + 0.5
15
Unit
V
AVDD1
AVDD2
AVSS1
AVSS2
VI
| VDD – AVDD2 | ≤ 0.5 V
V
| AVDD1 – AVDD2 | ≤ 0.5 V
V
V
V
Input voltage
V
Analog input voltage
(ANI0-ANI11)
VIAN
VDD ≥ AVDD2
V
VDD < AVDD2
V
Output voltage
VO
IOL
V
Low-level output current
Pin 1
mA
mA
mA
mA
°C
°C
Total of all pins
Pin 1
100
High-level output current
IOH
–10
Total of all pins
–50
Operating ambient temperature
Storage temperature
TA
–10 to +70
–65 to +150
Tstg
Caution If the rated value of even one of the above parameters is exceeded even momentarily, the quality
of the product may be degraded. Absolute maximum ratings therefore specify the values
exceeding which the product may be physically damaged. Never exceed these values when
using the product.
Operating Conditions
Clock Frequency
Operating Ambient Temperature (T
A
)
Operating Conditions
All functions
Supply Voltage (VDD)
+4.5 to +5.5 V
4 MHz ≤ fXX ≤ 16 MHz
–10 to +70°C
CPU function only
+4.0 to +5.5 V
32 kHz ≤ fXT ≤ 35 kHz
Subclock operation
(CPU, watch, and port
functions only)
+2.7 to +5.5 V
Data Sheet U12255EJ2V1DS
71
µPD784927, 784928, 784927Y, 784928Y
Oscillator Characteristics (main clock) (TA = –10 to +70°C, VDD = AVDD = 4.0 to 5.5 V, VSS = AVSS = 0 V)
Resonator
Recommended Circuit
Parameter
MIN.
4
MAX. Unit
16 MHz
Crystal resonator
Oscillation frequency (fXX)
X1
X2
VSS
C1
C2
Oscillator Characteristics (subclock) (TA = –10 to +70°C, VDD = AVDD = 2.7 to 5.5 V, VSS = AVSS = 0 V)
Resonator
Recommended Circuit
Parameter
MIN.
32
MAX. Unit
35 kHz
Crystal resonator
Oscillation frequency (fXT)
XT1
XT2
VSS
C1
C2
Caution When using the main system clock and subsystem clock oscillator, wire the portion enclosed
by the broken line in the above figures as follows to avoid the adverse influence of wiring
capacitance:
• Keep the wiring length as short as possible.
• Do not cross the wiring with the other signal lines. Do not route the wiring in the
neighborhood of a signal line through which a high alternating current flows.
• Always keep the ground point of the capacitor of the oscillator to the same potential as VSS.
Do not ground the capacitor to a ground pattern to which a high current flows.
• Do not extract signals from the oscillation circuit.
Exercise particular care in using the subsystem clock oscillator because the amplification factor
of this circuit is kept low to reduce the current consumption.
Remark For the resonator selection and oscillator constant, customers are requested to either evaluate the
oscillation themselves or apply to the resonator manufacturer for evaluation.
72
Data Sheet U12255EJ2V1DS
µPD784927, 784928, 784927Y, 784928Y
DC Characteristics (TA = –10 to +70°C, VDD = AVDD = 4.5 to 5.5 V, VSS = AVSS = 0 V)
Parameter
Symbol
VIL1
Conditions
Pins other than those listed in Note 1 below
Pins listed in Note 1 below
X1, X2
MIN.
TYP.
MAX.
0.3 VDD
0.2 VDD
0.4
Unit
V
Low-level input voltage
0
0
VIL2
V
VIL3
0
V
High-level input voltage
Low-level output voltage
VIH1
VIH2
VIH3
VOL1
VOL2
VOL3
VOL4
VOH1
VOH2
ILI
Pins other than those listed in Note 1 below
Pins listed in Note 1 below
X1, X2
0.7 VDD
0.8 VDD
VDD – 0.5
VDD
V
VDD
V
VDD
V
IOL = 8.0 mA (pins in Note 2)
IOL = 5.0 mA (pins in Note 4)
IOL = 2.0 mA
1.0
V
0.6
V
0.45
0.25
V
IOL = 100 µA
V
High-level output voltage
IOH = –1.0 mA
VDD – 1.0
VDD – 0.4
V
IOH = –100 µA
V
Input leakage current
Output leakage current
VDD supply current
0 ≤ VI ≤ VDD
10
10
50
µA
µA
mA
ILO
0 ≤ VO ≤ VDD
IDD1
Operation
mode
fXX = 16 MHz
30
fXX = 8 MHz (low-frequency os-
cillation mode)
Internally, 8 MHz main
clock operation
fXT = 32.768 kHz
Subclock operation (CPU,
watch, port)
50
10
80
25
µA
VDD = 2.7 V
IDD2
HALT mode fXX = 16 MHz
fXX = 8 MHz (low-frequency
mA
oscillation mode)
Internally, 8 MHz main clock
operation
fXT = 32.768 MHz
Subclock operation (CPU,
watch, port)
25
50
µA
VDD = 2.7 V
Data hold voltage
VDDDR STOP mode
2.5
V
Note 3
Data hold current
IDDDR
STOP mode Subclock oscillates
18
2.5
0.2
55
50
10
µA
VDDDR = 5.0 V
STOP mode Subclock oscillates
VDDDR = 2.7 V
µA
µA
kΩ
STOP mode Subclock stops
VDDDR = 2.5 V
7.0
110
Pull-up resistor
RL
VI = 0 V
25
Notes 1. RESET, IC, NMI, INTP0-INTP2, P61/SCK1/BUZ, P63/SI1, SCK2, SI2/BUSY, P65/HWIN, P91/KEY0 to
P95/KEY4
2. P40 to P47
3. In the STOP mode in which the subclock oscillation is stopped, disconnect the feedback resistor, and
connect the XT1 pin to VDD.
4. P46, P47
Data Sheet U12255EJ2V1DS
73
µPD784927, 784928, 784927Y, 784928Y
AC Characteristics
CPU and peripheral circuit operation clock (TA = –10 to +70°C, VDD = AVDD = 4.5 to 5.5 V, VSS = AVSS = 0 V)
Parameter
Symbol
tCLK
Conditions
TYP.
125
Unit
ns
CPU operation clock cycle time
fXX = 16 MHz
VDD = AVDD = 4.0 to 5.5 V
CPU function only
fXX = 16 MHz
fXX = 8 MHz
low-frequency oscillation mode
(Bit 7 of CC = 1)
Peripheral operation clock cycle time
tCLK1
fXX = 16 MHz
fXX = 8MHz
125
ns
low-frequency oscillation mode
(Bit 7 of CC = 1)
Serial interface
(1) SIOn: n = 1 or 2 (TA = –10 to +70°C, VDD = AVDD = 4.5 to 5.5 V, VSS = AVSS = 0 V)
Parameter
Serial clock cycle time
Symbol
tCYSK
Conditions
External clock
MIN.
1.0
MAX.
Unit
µs
µs
µs
µs
µs
µs
µs
ns
ns
ns
ns
ns
Input
Output fCLK1/8
fCLK1/16
1.0
2.0
fCLK1/32
4.0
fCLK1/64
8.0
fCLK1/128
16
fCLK1/256
32
Serial clock high- and low-level widths
tWSKH
tWSKL
tSSSK
tHSSK
tDSSK
Input
External clock
420
tCYSK/2 – 50
100
400
0
Output Internal clock
SIn setup time (vs. SCKn ↑)
SIn hold time (vs. SCKn ↑ )
SOn output delay time (vs. SCKn ↓ )
300
Remarks 1. fCLK1: operating clock of peripheral circuit (8 MHz)
2. n = 1 or 2
(2) SIO2 only (TA = –10 to +70°C, VDD = AVDD = 4.5 to 5.5 V, VSS = AVSS = 0 V)
Parameter
SCK2(8) ↑→STRB ↑
Symbol
tDSTRB
Conditions
MIN.
tWSKH
MAX.
tCYSK
Unit
Strobe high-level width
BUSY setup time
tWSTRB
tSBUSY
tCYSK – 30
100
tCYSK + 30
ns
ns
(vs. BUSY detection timing)
BUSY hold time
tHBUSY
100
ns
(vs. BUSY detection timing)
BUSY inactive →SCK2(1) ↓
tLBUSY
tCYSK + tWSKH
Remarks 1. The value in ( ) following SCK2 indicates the number of SCK2.
2. BUSY is detected after the time of (n + 2) x tCYSK (n = 0, 1, and so on) in respect to SCK2 (8) ↑ .
3. BUSY inactive →SCK2 (1) ↓ is the value when data has been completely written to SIO2.
74
Data Sheet U12255EJ2V1DS
µPD784927, 784928, 784927Y, 784928Y
I2C bus mode (µPD784928Y subseries only)
Parameter
Symbol
Standard Mode
High-speed Mode
MIN MAX.
Unit
MIN.
MAX
100
–
SCL clock frequency
fCLK
0
0
400
–
kHz
Bus free time (between stop and start
conditions)
tBUF
4.7
1.3
µs
Note 1
Hold time
tHD : STA
tLOW
4.0
4.7
4.0
4.7
–
–
0.6
1.3
0.6
0.6
–
–
–
–
µs
µs
µs
µs
µs
µs
ns
ns
ns
µs
ns
SCL clock low-level width
SCL clock high-level width
Start/restart condition setup time
tHIGH
–
tSU : STA
tHD : DAT
–
Data hold
time
CBUS compatible master
5.0
–
–
–
2
Note 2
Note 2
Note 2
I C bus
0
–
0
0.9
Note 4
Data setup time
tSU : DAT
tR
250
–
–
100
20+0.1Cb
20+0.1Cb
0.6
–
Note 5
Note 5
SDA and SCL signal rise time
SDA and SCL signal fall time
Stop condition setup time
Pulse width of spike restrained by input
filter
1000
300
–
300
300
–
tF
–
tSU : STO
tSP
4.0
–
–
0
50
Each bus line capacitative load
Cb
–
400
–
400
pF
Notes 1. The first clock pulse is generated at the start condition after this period.
2. The device needs to internally supply a hold time of at least 300 ns for the SDA signal to fill the undefined
area at the falling edge of the SCL (VIHmin. of the SCL signal).
3. Unless the device extends the low hold time (tLOW) of the SCL signal, it is necessary to fill only the
maximum data hold time (tHD : DAT).
4. The high-speed mode I2C bus can be used in the standard mode I2C bus system. In this case, satisfy
the following conditions:
• When the device does not extend the low hold time of the SCL signal
tSU : DAT ≥ 250 ns
• When the device extends the low hold time of the SCL signal
Send the next data bit to the SDA line before releasing the SCL line (tRmax. + tSU:DAT = 1000 + 250
= 1250 ns : in the standard mode I2C bus specification)
5. Cb: Total capacitance of one bus line (unit: pF)
Data Sheet U12255EJ2V1DS
75
µPD784927, 784928, 784927Y, 784928Y
Other operations (TA = –10 to +70°C, VDD = AVDD = 4.5 to 5.5 V, VSS = AVSS = 0 V)
Parameter
Symbol
tWCTL
Condition
MIN.
MAX.
Unit
ns
Timer input signal low-level width
When DFGIN, CFGIN, DPGIN, REEL0IN,
or REEL1IN logic level is input
tCLK1
Timer input signal high-level width
tWCTH
When DFGIN, CFGIN, DPGIN, REEL0IN,
or REEL1IN logic level is input
tCLK1
ns
Timer input signal valid edge input cycle
CSYNCIN low-level width
tPERIN
When DFGIN, CFGIN, or DPGIN is input
2
µs
ns
ns
tWCR1L When digital noise rejection circuit is not used
When digital noise rejection circuit is used
(Bit 4 of INTM2 = 0)
8tCLK1
108tCLK1
When digital noise rejection circuit is used
(Bit 4 of INTM2 = 1)
180tCLK1
ns
CSYNCIN high-level width
tWCR1H When digital noise rejection circuit is not used
When digital noise rejection circuit is used
(Bit 4 of INTM2 = 0)
8tCLK1
ns
ns
108tCLK1
When digital noise rejection circuit is used
(Bit 4 of INTM2 = 1)
180tCLK1
ns
Digital noise
Rejected pulse width
Passed pulse width
tWSEP
Bit 4 of INTM2 = 0
104tCLK1
176tCLK1
ns
ns
ns
ns
µs
µs
ns
ns
ns
µs
ns
µs
ns
µs
µs
ms
µs
ns
µs
µs
ms
µs
µs
rejection circuit
Bit 4 of INTM2 = 1
Bit 4 of INTM2 = 0
108tCLK1
180tCLK1
10
Bit 4 of INTM2 = 1
NMI low-level width
tWNIL
tWNIH
tWIPL0
tWIPH0
tWIPL1
VDD = AVDD = 2.7 to 5.5 V
VDD = AVDD = 2.7 to 5.5 V
NMI high-level width
10
INTP0, INTP3 low-level widths
INTP0, INTP3 high-level widths
INTP1, KEY0-KEY4 low-level widths
2tCLK1
2tCLK1
2tCLK1
10
Mode other than STOP mode
In STOP mode, for releasing STOP mode
Mode other than STOP mode
INTP1, KEY0-KEY4 high-level widths
INTP2 low-level width
tWIPH1
2tCLK1
10
In STOP mode, for releasing STOP mode
tWIPL2
In normal mode,
with main clock
Normal mode,
with subclock
Sampling = fCLK
2tCLK1
Note
Sampling = fCLK/128
Sampling = fCLK
32
61
Note
Sampling = fCLK/128
7.9
In STOP mode, for releasing STOP mode
10
INTP2 high-level width
RESET low-level width
tWIPH2
In normal mode,
with main clock
Normal mode,
with subclock
Sampling = fCLK
2tCLK1
Note
Sampling = fCLK/128
Sampling = fCLK
32
61
Note
Sampling = fCLK/128
7.9
In STOP mode, for releasing STOP mode
10
10
tWRSL
Note If a high or low level is successively input two times during the sampling period, a high or low level is
detected.
Remark tCKL1: operating clock cycle time of peripheral circuit (125 ns)
76
Data Sheet U12255EJ2V1DS
µPD784927, 784928, 784927Y, 784928Y
Clock output operation (TA = –10 to +70°C, VDD = AVDD = 4.5 to 5.5 V, VSS = AVSS = 0 V)
Parameter
CLO cycle time
Symbol
tCYCL
tCLL
Condition
MIN.
125
MAX.
16000
8025
8025
25
Unit
ns
nT
CLO low-level width
CLO high-level width
CLO rise time
tCYCL/2 25
tCYCL/2 25
37.5
37.5
ns
tCLH
ns
tCLR
ns
CLO fall time
tCLF
25
ns
Remarks 1. n: system clock division
2. T = 1/fCLK
Data hold characteristics (TA = –10 to +70°C, VDD = AVDD = 2.5 to 5.5 V, VSS = AVSS = 0 V)
Parameter
Low-level input voltage
High-level input voltage
Symbol
VIL
Condition
MIN.
0
TYP.
MAX.
0.1 VDDDR
VDDDR
Unit
V
Special pins (pins in Note)
VIH
0.9 VDDDR
V
Note RESET, IC, NMI, INTP0-INTP2, P61/SCK1/BUZ, P63/SI1, SCK2, SI2/BUSY, P65/HWIN, P91/KEY0-P95/
KEY4
Watch function (TA = –10 to +70°C, VDD = AVDD = 2.7 to 5.5 V, VSS = AVSS = 0 V)
Parameter
Symbol
VDDXT
Condition
MIN.
2.7
MAX.
Unit
V
Subclock oscillation hold voltage
Hardware watch function operating voltage
VDDW
2.7
V
Subclock oscillation stop detection flag (TA = –10 to +70°C, VDD = AVDD = 4.5 to 5.5 V, VSS = AVSS = 0 V)
Parameter
Symbol
Condition
MIN.
45
MAX.
Unit
Oscillation stop detection width
tOSCF
µs
A/D converter characteristics (TA = –10 to +70°C, VDD = AVDD = AVREF = 4.5 to 5.5 V, VSS = AVSS = 0 V)
Parameter
Symbol
Condition
MIN.
8
TYP.
MAX.
Unit
bit
Resolution
Total error
AVREF = VDD
2.0
1/2
%
Quantization error
Conversion time
LSB
µs
tCONV
Bit 4 of ADM = 0
Bit 4 of ADM = 1
Bit 4 of ADM = 0
Bit 4 of ADM = 1
160tCLK1
80tCLK1
32tCLK1
16tCLK1
0
µs
Sampling time
tSAMP
µs
µs
Analog input voltage
Analog input impedance
AVREF current
VIAN
ZAN
AVREF
V
1000
0.4
MΩ
mA
AIREF
1.2
Data Sheet U12255EJ2V1DS
77
µPD784927, 784928, 784927Y, 784928Y
VREF amplifier (TA = 25°C, VDD = AVDD = 5 V, VSS = AVSS = 0 V)
Parameter
Reference voltage
Charge current
Symbol
VREF
Condition
MIN.
2.35
300
TYP.
2.50
MAX.
2.65
Unit
V
ICHG
Sets AMPM0.0 to 1
µA
(pins in Note)
Note RECCTL+, RECCTL–, CFGIN, CFGCPIN, DFGIN, DPGIN, CSYNCIN, REEL0IN, REEL1IN
CTL amplifier (TA = 25°C, VDD = AVDD = 5 V, VSS = AVSS = 0 V)
Parameter
CTL+, – input resistance
Feedback resistance
Symbol
RICTL
Condition
MIN.
2
TYP.
5
MAX.
10
Unit
kΩ
kΩ
kΩ
dB
dB
dB
dB
V
RFCTL
20
20
17
71
50
100
100
22
Bias resistance
RBCTL
50
Minimum voltage gain
Maximum voltage gain
Gain selecting step
GCTLMIN
GCTLMAX
SGAIN
20
75
1.77
50
Same phase signal elimination ratio
CMR DC, voltage gain: 20 dB
High comparator set voltage of waveform shaping VPBCTLHS
High comparator reset voltage of waveform shaping VPBCTLHR
Low comparator set voltage of waveform shaping VPBCTLLS
Low comparator reset voltage of waveform shaping VPBCTLLR
VREF + 0.47 VREF + 0.50 VREF + 0.53
VREF + 0.27 VREF 0.30 VREF + 0.33
+
V
VREF – 0.53 VREF – 0.50 VREF – 0.47
VREF – 0.33 VREF – 0.30 VREF – 0.27
V
V
Comparator Schmitt width of waveform shaping
High comparator voltage of CTL flag S
Low comparator voltage of CLT flag S
High comparator voltage of CTL flag L
Low comparator voltage of CTL flag L
VPBSH
VFSH
VFSL
VFLH
VFLL
150
200
250
mV
V
VREF + 1.00 VREF + 1.05 VREF + 1.10
VREF – 1.10 VREF – 1.05 VREF – 1.00
VREF + 1.40 VREF + 1.45 VREF + 1.50
VREF – 1.50 VREF – 1.45 VREF – 1.40
V
V
V
78
Data Sheet U12255EJ2V1DS
µPD784927, 784928, 784927Y, 784928Y
CFG amplifier (AC coupling) (TA = 25°C, VDD = AVDD = 5 V, VSS = AVSS = 0 V)
Parameter
Symbol
Condition
MIN.
50
TYP.
MAX.
Unit
dB
dB
mA
mA
V
Voltage gain 1
Voltage gain 2
GCFG1 fi = 2 kHz, open loop
GCFG2 fi = 30 kHz, open loop
34
CFGAMPO High-level output current
CFGAMPO Low-level output current
High comparator voltage
IOHCFG DC
IOLCFG DC
VCFGH
–1
0.1
VREF + 0.09 VREF + 0.12 VREF + 0.15
VREF – 0.15 VREF – 0.12 VREF – 0.09
Low comparator voltage
VCFGL
V
Duty accuracy
PDUTY
Note
49.7
50.0
50.3
%
Note The conditions include the following circuit and input signal.
Input signal : Sine wave input (5 mVp-p)
fi = 1 kHz
µPD784927
1 kΩ
Voltage gain: 50 dB
–
+
CFGIN
22µF
330 kΩ
CFGAMPO
0.01µ F
CFGCPIN
DFG amplifier (AC coupling) (TA = 25°C, VDD = AVDD = 5 V, VSS = AVSS = 0 V)
Parameter
Symbol
GDFG
Condition
MIN.
TYP.
MAX.
640
Unit
dB
kΩ
Ω
Voltage gain
fi = 900 Hz, open loop
50
Feedback resistance
RFDFG
RIDFG
VDFGH
VDFGL
160
400
150
Input protection resistance
High comparator voltage
Low comparator voltage
VREF + 0.07 VREF + 0.10 VREF + 0.14
VREF – 0.14 VREF – 0.10 VREF – 0.07
V
V
Caution Set the input resistance connected to the DFGIN pin to 16 kΩ or below. Connecting a resistor
exceeding that value may cause the DFG amp to oscillate.
Data Sheet U12255EJ2V1DS
79
µPD784927, 784928, 784927Y, 784928Y
DPG amplifier (AC coupling) (TA = 25°C, VDD = AVDD = 5 V, VSS = AVSS = 0 V)
Parameter
Symbol
GDPG
Condition
MIN.
TYP.
20
MAX.
Unit
dB
V
Voltage gain
fI = 30 Hz
High comparator voltage
VDPGH1 SELDPGHL0 = 0, SELDPGHL1 = 0 VREF + 0.02 VREF + 0.05 VREF + 0.08
VDPGH2 SELDPGHL0 = 1, SELDPGHL1 = 0 VREF + 0.56 VREF + 0.60 VREF + 0.64
VDPGH3 SELDPGHL0 = 0, SELDPGHL1 = 1 VREF – 0.44 VREF – 0.40 VREF – 0.36
VDPGL1 SELDPGHL0 = 0, SELDPGHL1 = 0 VREF – 0.08 VREF – 0.05 VREF – 0.02
VDPGL2 SELDPGHL0 = 1, SELDPGHL1 = 0 VREF + 0.36 VREF + 0.40 VREF + 0.44
VDPGL3 SELDPGHL0 = 0, SELDPGHL1 = 1 VREF – 0.64 VREF – 0.60 VREF – 0.56
V
V
Low comparator voltage
V
V
V
Caution When both the SELDPGHL0 and SELDPGHL1 are set to 0, the DPG amplifier is not used.
Therefore, be sure to set AMPC.7 (ENDPG) to 0.
Ternary separation circuit (TA = 25°C, VDD = AVDD = 5 V, VSS = AVSS = 0 V)
Parameter
Input impedance
Symbol
ZIPFG
Condition
MIN.
20
TYP.
50
MAX.
100
Unit
kΩ
V
High comparator voltage
Low comparator voltage
VPFGH
VPFGL
VREF + 0.5 VREF + 0.7 VREF + 0.9
VREF – 1.4 VREF – 1.2 VREF – 1.0
V
CSYNC comparator (AC coupling) (TA = 25°C, VDD = AVDD = 5 V, VSS = AVSS = 0 V)
Parameter
Input impedance
Symbol
ZICSYN
Condition
MIN.
20
TYP.
50
MAX.
100
Unit
kΩ
V
High comparator voltage
Low comparator voltage
VCSYNH
VCSYNL
VREF + 0.07 VREF + 0.10 VREF + 0.13
VREF – 0.13 VREF – 0.10 VREF – 0.07
V
Reel FG comparator (AC coupling) (TA = 25°C, VDD = AVDD = 5 V, VSS = AVSS = 0 V)
Parameter
Input impedance
Symbol
ZIRLFG
Condition
MIN.
20
TYP.
50
MAX.
100
Unit
kΩ
V
High comparator voltage
Low comparator voltage
VRLFGH
VRLFGL
VREF + 0.02 VREF + 0.05 VREF + 0.08
VREF – 0.08 VREF – 0.05 VREF – 0.02
V
RECCTL driver (TA = 25°C, VDD = AVDD = 5 V, VSS = AVSS = 0 V)
Parameter
Symbol
Condition
MIN.
TYP.
70
MAX.
Unit
V
RECCTL+, – high-level output voltage
RECCTL+, – low-level output voltage
CTLDLY internal resistance
CTLDLY charge current
VCHREC IOH = –4 mA
VOLREC IOL = 4 mA
RCTL
VDD – 0.8
0.8
V
40
–3
–3
140
kΩ
mA
mA
IOHCTL Use of internal resistor
IOLCTL
CTLDLY discharge current
80
Data Sheet U12255EJ2V1DS
µPD784927, 784928, 784927Y, 784928Y
Timing waveform
AC timing test point
0.8 VDD or 2.2 V
0.8 V
0.8 VDD or 2.2 V
Test point
0.8 V
Serial transfer timing (SIOn: n = 1 or 2)
t
WSKL
t
WSKH
SCKn
SIn
t
CYSK
t
SSSK
t
HSSK
Input data
t
DSSK
Output data
SOn
Data Sheet U12255EJ2V1DS
81
µPD784927, 784928, 784927Y, 784928Y
Serial transfer timing (SIO2 only)
No busy processing
tWSKL
tWSKH
SCK2
BUSY
7
8
9
10
1
2
t
CYSK
Active high
Busy invalid
tDSTRB
tWSTRB
STRB
Continuation of busy processing
tWSKL
tWSKH
SCK2
BUSY
STRB
7
8
9
10
10+n
t
CYSK
t
SBUSY
t
SBUSY
Active high
tDSTRB
t
WSTRB
End of busy processing
tWSKL
tWSKH
SCK2
7
8
9
10+n
11+n
1
tCYSK
tHBUSY
tLBUSY
BUSY
Active high
Caution When an external clock is selected as the serial clock, do not use the busy control or strobe
control.
82
Data Sheet U12255EJ2V1DS
µPD784927, 784928, 784927Y, 784928Y
I2C bus mode (µPD784928Y subseries only)
tLOW
tR
SCL
SDA
tF
t
HD : DAT
t
HIGH
tSU : STA
tHD : STA
tSP
tSU : STO
t
HD : STA
tSU : DAT
tBUF
Stop
condition
Start
condition
Restart
condition
Stop
condition
Data Sheet U12255EJ2V1DS
83
µPD784927, 784928, 784927Y, 784928Y
Super timer unit input timing
t
WCTH
t
WCTL
0.8 VDD
When DFGIN, CFGIN, DPGIN,
REEL0IN, or REEL1IN logic
level is input
0.8 V
t
WCR1H
t
WCR1L
0.8 VDD
When CSYNCIN logic level
is input
0.8 V
Interrupt request input timing
tWNIH
tWNIL
0.8 VDD
NMI
0.8 V
0.8 V
0.8 V
0.8 V
tWIPH0
tWIPH1
t
WIPH2
t
WIPL0
WIPL1
WIPL2
0.8 VDD
0.8 VDD
0.8 VDD
INTP0, INTP3
INTP1, KEY0-KEY4
INTP2
t
t
84
Data Sheet U12255EJ2V1DS
µPD784927, 784928, 784927Y, 784928Y
Reset input timing
tWRSL
RESET
0.8 V
Clock output timing
t
CLH
0.8 VDD
0.8 V
CLO
t
CLR
t
CLF
t
CLL
t
CYCL
Data Sheet U12255EJ2V1DS
85
µPD784927, 784928, 784927Y, 784928Y
7. PACKAGE DRAWING
100 PIN PLASTIC LQFP (FINE PITCH) (14×14)
A
B
75
76
51
50
detail of lead end
S
C
D
R
Q
100
1
26
25
F
M
H
I
J
G
K
L
P
M
N
NOTE
ITEM MILLIMETERS
INCHES
Each lead centerline is located within 0.08 mm (0.003 inch) of
its true position (T.P.) at maximum material condition.
A
16.00 0.20
0.630 0.008
+0.009
0.551
B
14.00 0.20
–0.008
+0.009
0.551
C
D
14.00 0.20
16.00 0.20
–0.008
0.630 0.008
F
1.00
1.00
0.039
0.039
G
+0.05
0.22
H
0.009 0.002
–0.04
I
0.08
0.003
J
0.50 (T.P.)
0.020 (T.P.)
+0.009
0.039
K
L
1.00 0.20
0.50 0.20
–0.008
+0.008
0.020
–0.009
+0.03
0.17
+0.001
0.007
M
–0.07
–0.003
N
P
Q
0.08
0.003
1.40 0.05
0.10 0.05
0.055 0.002
0.004 0.002
+7°
3°
+7°
3°
R
S
–3°
–3°
1.60 MAX.
0.063 MAX.
S100GC-50-8EU
Remark The package dimensions and materials of ES versions are the same as those of mass-production
versions.
86
Data Sheet U12255EJ2V1DS
µPD784927, 784928, 784927Y, 784928Y
100PIN PLASTIC QFP (14x20)
A
B
51
50
80
81
detail of lead end
C D
S
R
Q
31
30
100
1
F
J
G
M
H
I
P
K
M
N
L
NOTE
ITEM MILLIMETERS
INCHES
Each lead centerline is located within 0.15 mm (0.006 inch) of
its true position (T.P.) at maximum material condition.
A
23.6 0.4
0.929 0.016
+0.009
0.795
B
20.0 0.2
–0.008
+0.009
0.551
C
14.0 0.2
–0.008
D
F
17.6 0.4
0.8
0.693 0.016
0.031
G
0.6
0.024
+0.004
0.012
H
0.30 0.10
–0.005
I
0.15
0.006
J
0.65 (T.P.)
0.026 (T.P.)
+0.008
0.071
K
L
1.8 0.2
0.8 0.2
–0.009
+0.009
0.031
–0.008
+0.10
0.15
+0.004
0.006
M
–0.05
–0.003
N
P
0.10
0.004
+0.005
0.106
2.7 0.1
–0.004
Q
R
S
0.1 0.1
5° 5°
3.0 MAX.
0.004 0.004
5° 5°
0.119 MAX.
P100GF-65-3BA1-3
Remark The package dimensions and materials of ES versions are the same as those of mass-production
versions.
Data Sheet U12255EJ2V1DS
87
µPD784927, 784928, 784927Y, 784928Y
8. RECOMMENDED SOLDERING CONDITIONS
Solder this product under the following recommended conditions.
For technical information, see the following website.
Semiconductor Device Mount Manual (http://www.necel.com/pkg/en/mount/index.html)
Table 8-1. Surface Mount Type Soldering Conditions
(1) µPD784927GF-×××-3BA : 100-pin plastic QFP (14 × 20 mm)
µPD784928GF-×××-3BA : 100-pin plastic QFP (14 × 20 mm)
µPD784927YGF-×××-3BA : 100-pin plastic QFP (14 × 20 mm)
µPD784928YGF-×××-3BA : 100-pin plastic QFP (14 × 20 mm)
Soldering Method
Infrared reflow
VPS
Soldering Conditions
Recommended
Conditions Symbol
Package peak temperature: 235°C, Time: 30 secs. max. (210°C min.),
Number of times: three times max.
IR35-00-3
VP15-00-3
WS60-00-1
Package peak temperature: 215°C, Time: 40 secs. max. (200°C min.),
Number of times: three times max.
Wave soldering
Solder bath temperature: 260°C max., Time: 10 secs. max.,
Number of times: once,
Preheating temperature: 120°C max.(Package surface temperature)
Partial heating
Pin temperature: 350°C max., Time: three secs. max. (per device side)
—
Caution Do not use two or more soldering methods in combination (except partial heating).
(2) µPD784927GF-×××-3BA-A : 100-pin plastic QFP (14 × 20 mm)
µPD784928GF-×××-3BA-A : 100-pin plastic QFP (14 × 20 mm)
µPD784927YGF-×××-3BA-A : 100-pin plastic QFP (14 × 20 mm)
µPD784928YGF-×××-3BA-A : 100-pin plastic QFP (14 × 20 mm)
Soldering Method
Soldering Conditions
Recommended
Conditions Symbol
Infrared reflow
Package peak temperature: 260°C, Time: 60 seconds max. (at 220°C or
IR60-207-3
higher), Count: Three times or less,
Exposure limit: 7 daysNote (after that, prebake at 125°C for 20 to 72 hours)
For details, contact an NEC Electronics sales representative.
Wave soldering
Partial heating
—
—
Pin temperature: 350°C max., Time: 3 seconds. max. (per pin row))
Note After opening the dry pack, store it at 25°C or less and 65% RH or less for the allowable storage period.
Caution Do not use different soldering methods together (except for partial heating).
Remark Products that have the part numbers suffixed by “-A” are lead-free products.
88
Data Sheet U12255EJ2V1DS
µPD784927, 784928, 784927Y, 784928Y
APPENDIX A. DEVELOPMENT TOOLS
The following development tools are available for developing systems using the µPD784927.
Refer to (5) Cautions when the development tools are used.
(1) Language processing software
RA78K4
78K/IV series common assembler package
CC78K4
78K/IV series common C compiler package
Device file for the µPD784928, 784928Y subseries
78K/IV series common C compiler library source file
DF784928
CC78K4-L
(2) Flash memory writing tools
Flashpro II, III
Dedicated flash programmer
(Part number: FL-PR2,
FL-PR3, PG-FPIII)
FA-100GC
Adapter for writing 100-pin plastic LQFP (GC-8EU type) flash memory. Be sure to
connect depending on the target product.
FA-100GF
Adapter for writing 100-pin plastic QFP (GF-3BA type) flash memory. Be sure to
connect depending on the target product.
(3) Debugging tools
•
When using the IE-78K4-NS in-circuit emulator
IE-78K4-NS
78K/IV series common in-circuit emulator
Power supply unit for IE-78K4-NS
IE-70000-MC-PS-B
IE-70000-98-IF-C
Interface adapter necessary when a PC-9800 series computer (except notebook
personal computer) is used as host machine (C bus compatible)
IE-70000-CD-IF-A
IE-70000-PC-IF-C
PC card and interface cable necessary when a notebook personal computer is used as
host machine (PCMCIA socket compatible)
Interface adapter necessary when an IBM PC/ATTM compatible machine is used as host
machine (ISA bus compatible)
IE-784928-NS-EM1
EP-784915-GF-R
Emulation board for emulating the µPD784928, 784928Y subseries
Emulation probe for µPD784915 subseries common 100-pin plastic QFP (GC-3BA type)
and 100-pin plastic LQFP (GC-8EU type).
EV-9200GF-100
NQPACK100RB
Conversion socket to be mounted on the board of the target system for 100-pin plastic
QFP (GF-3BA type). It is used in LCC system.
Conversion socket to be mounted on the board of the target system for 100-pin plastic
QFP (GF-3BA type). It is used in QFP system.
ID78K4-NS
SM78K4
Integrated debugger for IE-78K4-NS
78K/IV series common system simulator
Device file for the µPD784928, 784928Y subseries
DF784928
Data Sheet U12255EJ2V1DS
89
µPD784927, 784928, 784927Y, 784928Y
•
When using the IE-784000-R in-circuit emulator
IE-784000-R
78K/IV series common in-circuit emulator
IE-70000-98-IF-C
Interface adapter necessary when a PC-9800 series computer (except notebook
personal computer) is used as host machine (C bus compatible)
IE-70000-PC-IF-C
Interface adapter necessary when an IBM PC/AT compatible machine is used
as host machine (ISA bus compatible)
IE-78000-R-SV3
Interface adapter and cable necessary when an EWS is used as host machine
IE-784928-NS-EM1
IE-784915-R-EM1
Emulation board for emulating the µPD784928, 784928Y subseries and µPD784915
subseries
IE-784000-R-EM
IE-78K4-R-EX3
78K/IV series common emulation board
Conversion board for 100-pin products necessary when the IE-784928-NS-EM1 is used
in the IE-784000-R. Not necessary when the IE-784915-R-EM1 is used.
EP-784915-GF-R
EV-9200GF-100
NQPACK100RB
Emulation probe for µPD784915 subseries common 100-pin plastic QFP (GC-3BA type)
and 100-pin plastic LQFP (GC-8EU type).
Conversion socket to be mounted on the board of the target system for 100-pin plastic
QFP (GF-3BA type). It is used in LCC system.
Conversion socket to be mounted on the board of the target system for 100-pin plastic
QFP (GF-3BA type). It is used in QFP system.
ID78K4
Integrated debugger for IE-784000-R
SM78K4
DF784928
78K/IV series common system simulator
Device file for the µPD784928, 784928Y subseries
(4) Real-time OS
RX78K/IV
MX78K4
Real-time OS for 78K/IV series
OS for 78K/IV series
90
Data Sheet U12255EJ2V1DS
µPD784927, 784928, 784927Y, 784928Y
(5) Cautions when the development tools are used
•
•
•
The ID78K4-NS, ID78K4, and SM78K4 are used in combination with the DF784928.
The CC78K4 and RX78K/IV are used in combination with the RA78K4 and DF784928.
FL-PR2, FL-PR3, FA-100GC, and FA-100GF are products of Naito Densei Machida Mfg. Co., Ltd. (TEL: 044-
822-3813). Contact an NEC distributor when purchasing these products.
NQPACK100RB is a product of Tokyo Eletech Corp.
•
•
Reference: Daimaru Kogyo, Ltd. Electronics Dept. (TEL: Tokyo 03-3820-7112)
Electronics 2nd Dept. (TEL: Osaka 06-6244-6672)
Host machines and OSs compatible with the software are as follows:
Host Machine [OS]
PC
EWS
PC-9800 Series [WindowsTM
]
HP9000 series 700TM [HP-UXTM
]
IBM PC/AT compatible machines
[Japanese/English Windows]
Note
SPARCstationTM [SunOSTM, SolarisTM
]
NEWSTM (RISC) [NEWS-OSTM
]
Software
RA78K4
CC78K4
Note
ID78K4-NS
ID78K4
–
–
SM78K4
RX78K/IV
MX78K4
Note
Note
Note DOS based software
Data Sheet U12255EJ2V1DS
91
µPD784927, 784928, 784927Y, 784928Y
APPENDIX B. RELATED DOCUMENTS
The documents referred to in this publication may include preliminary versions. However, preliminary versions are not marked
as such.
Device-related documents
Document
Document No.
Japanese
U12648J
English
U12648E
µPD784928, 784928Y Subseries User’s Manual - Hardware
µPD784927, 784928, 784927Y, 784928Y Data Sheet
µPD784928 Subseries Special Function Register Table
µPD78F4928 Preliminary Product Information
µPD784928Y Subseries Special Function Register Table
µPD78F4928Y Preliminary Product Information
µPD784915, 784928, 784928Y Subseries Application Note - VCR Servo
78K/IV Series User’s Manual - Instruction
U12255J
U12798J
U12188J
U12719J
U12271J
U11361J
U10905J
U10594J
U10595J
U10095J
This document
–
U12188E
–
U12271E
U11361E
U10905E
–
78K/IV Series Instruction Table
78K/IV Series Instruction Set
–
78K/IV Series Application Note - Software Basics
U10095E
Development tool-related documents (User’s Manuals)
Document
Document No.
Japanese
English
U11334E
RA78K4 Assembler Package
Operation
Language
U11334J
U11162J
U11743J
U11572J
U11571J
U13356J
U12903J
U13819J
U10931J
U10093J
U11162E
U11743E
U11572E
U11571E
U13356E
EEU-1534
U13819E
U10931E
U10093E
U10092E
RA78K4 Structured Assembler Preprocessor
CC78K4 C Compiler
Operation
Language
IE-78K4-NS
IE-784000-R
IE-784928-NS-EM1
IE-784915-R-EM1, EP-784915GF-R
SM78K4 System Simulator Windows Based
SM78K Series System Simulator
Reference
External Part User Open U10092J
Interface Specifications
ID78K4-NS Integrated Debugger
Reference
Reference
Reference
U12796J
U10440J
U11960J
U12796E
U10440E
U11960E
ID78K4 Integrated Debugger Windows Based
ID78K4 Integrated Debugger
HP-UX, SunOS, NEWS-OS Based
Caution The contents of the above related documents are subject to change without notice. Be sure to use
the latest edition of the document when designing your system.
92
Data Sheet U12255EJ2V1DS
µPD784927, 784928, 784927Y, 784928Y
Embedded software-related documents (User’s Manual)
Document
Document No.
Japanese
U10603J
English
U10603E
U10604E
78K/IV Series Real-Time OS
Fundamental
Installation
Debugger
U10604J
U10364J
U11779J
–
–
78K/IV Series OS, MX78K4
Fundamental
Other Related Documents
Document Name
Document No.
X13769X
SEMICONDUCTOR SELECTION GUIDE - Products and Packages -
Semiconductor Device Mount Manual
Note
Quality Grades on NEC Semiconductor Devices
NEC Semiconductor Device Reliability/Quality Control System
C11531E
C10983E
C11892E
Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD)
Note See the “Semiconductor Device Mount Manual” website (http://www.necel.com/pkg/en/mount/index.html)
Caution The contents of the above related documents are subject to change without notice. Be sure to
use the latest edition of the document when designing your system.
Data Sheet U12255EJ2V1DS
93
µPD784927, 784928, 784927Y, 784928Y
NOTES FOR CMOS DEVICES
1
VOLTAGE APPLICATION WAVEFORM AT INPUT PIN
Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the
CMOS device stays in the area between VIL (MAX) and VIH (MIN) due to noise, etc., the device may
malfunction. Take care to prevent chattering noise from entering the device when the input level is
fixed, and also in the transition period when the input level passes through the area between VIL (MAX)
and VIH (MIN).
HANDLING OF UNUSED INPUT PINS
2
Unconnected CMOS device inputs can be cause of malfunction. If an input pin is unconnected, it is
possible that an internal input level may be generated due to noise, etc., causing malfunction. CMOS
devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed
high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to VDD or
GND via a resistor if there is a possibility that it will be an output pin. All handling related to unused pins
must be judged separately for each device and according to related specifications governing the device.
3
PRECAUTION AGAINST ESD
A strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as
much as possible, and quickly dissipate it when it has occurred. Environmental control must be
adequate. When it is dry, a humidifier should be used. It is recommended to avoid using insulators that
easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static
container, static shielding bag or conductive material. All test and measurement tools including work
benches and floors should be grounded. The operator should be grounded using a wrist strap.
Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for
PW boards with mounted semiconductor devices.
4
STATUS BEFORE INITIALIZATION
Power-on does not necessarily define the initial status of a MOS device. Immediately after the power
source is turned ON, devices with reset functions have not yet been initialized. Hence, power-on does
not guarantee output pin levels, I/O settings or contents of registers. A device is not initialized until the
reset signal is received. A reset operation must be executed immediately after power-on for devices
with reset functions.
5
POWER ON/OFF SEQUENCE
In the case of a device that uses different power supplies for the internal operation and external
interface, as a rule, switch on the external power supply after switching on the internal power supply.
When switching the power supply off, as a rule, switch off the external power supply and then the
internal power supply. Use of the reverse power on/off sequences may result in the application of an
overvoltage to the internal elements of the device, causing malfunction and degradation of internal
elements due to the passage of an abnormal current.
The correct power on/off sequence must be judged separately for each device and according to related
specifications governing the device.
6
INPUT OF SIGNAL DURING POWER OFF STATE
Do not input signals or an I/O pull-up power supply while the device is not powered. The current
injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and
the abnormal current that passes in the device at this time may cause degradation of internal elements.
Input of signals during the power off state must be judged separately for each device and according to
related specifications governing the device.
94
Data Sheet U12255EJ2V1DS
µPD784927, 784928, 784927Y, 784928Y
EEPROM and FIP are trademarks of NEC Electronics Corporation.
Windows is either a registered trademark or a trademark of Microsoft Corporation in the
United States and/or other countries.
PC/AT and PC DOS are trademarks of IBM Corporation.
HP9000 Series 700 and HP-UX are trademarks of Hewlett-Packard Company.
SPARCstation is a trademark of SPARC International, Inc.
Solaris and SunOS are trademarks of Sun Microsystems, Inc.
NEWS and NEW-OS are trademarks of Sony Corporation.
Data Sheet U12255EJ2V1DS
95
µPD784927, 784928, 784927Y, 784928Y
Regional Information
Some information contained in this document may vary from country to country. Before using any NEC
Electronics product in your application, pIease contact the NEC Electronics office in your country to
obtain a list of authorized representatives and distributors. They will verify:
•
•
•
•
•
Device availability
Ordering information
Product release schedule
Availability of related technical literature
Development environment specifications (for example, specifications for third-party tools and
components, host computers, power plugs, AC supply voltages, and so forth)
•
Network requirements
In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary
from country to country.
[GLOBAL SUPPORT]
http://www.necel.com/en/support/support.html
NEC Electronics Hong Kong Ltd.
Hong Kong
Tel: 2886-9318
NEC Electronics America, Inc. (U.S.)
Santa Clara, California
Tel: 408-588-6000
NEC Electronics (Europe) GmbH
Duesseldorf, Germany
Tel: 0211-65030
800-366-9782
•
•
•
NEC Electronics Hong Kong Ltd.
Seoul Branch
Seoul, Korea
Sucursal en España
Madrid, Spain
Tel: 091-504 27 87
Tel: 02-558-3737
Succursale Française
Vélizy-Villacoublay, France
Tel: 01-30-67 58 00
NEC Electronics Shanghai Ltd.
Shanghai, P.R. China
Tel: 021-5888-5400
Filiale Italiana
Milano, Italy
Tel: 02-66 75 41
NEC Electronics Taiwan Ltd.
Taipei, Taiwan
Tel: 02-2719-2377
•
Branch The Netherlands
Eindhoven, TheNetherlands
Tel: 040-2654010
NEC Electronics Singapore Pte. Ltd.
Novena Square, Singapore
Tel: 6253-8311
•
•
Tyskland Filial
Taeby, Sweden
Tel: 08-63 87 200
United Kingdom Branch
Milton Keynes, UK
Tel: 01908-691-133
J05.6
96
Data Sheet U12255EJ2V1DS
µPD784927, 784928, 784927Y, 784928Y
These commodities, technology or software, must be exported in accordance
with the export administration regulations of the exporting country.
Diversion contrary to the law of that country is prohibited.
•
The information in this document is current as of August, 2005. The information is subject to
change without notice. For actual design-in, refer to the latest publications of NEC Electronics data
sheets or data books, etc., for the most up-to-date specifications of NEC Electronics products. Not
all products and/or types are available in every country. Please check with an NEC Electronics sales
representative for availability and additional information.
• No part of this document may be copied or reproduced in any form or by any means without the prior
written consent of NEC Electronics. NEC Electronics assumes no responsibility for any errors that may
appear in this document.
•
NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual
property rights of third parties by or arising from the use of NEC Electronics products listed in this document
or any other liability arising from the use of such products. No license, express, implied or otherwise, is
granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others.
Descriptions of circuits, software and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these
circuits, software and information in the design of a customer's equipment shall be done under the full
responsibility of the customer. NEC Electronics assumes no responsibility for any losses incurred by
customers or third parties arising from the use of these circuits, software and information.
•
• While NEC Electronics endeavors to enhance the quality, reliability and safety of NEC Electronics products,
customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To
minimize risks of damage to property or injury (including death) to persons arising from defects in NEC
Electronics products, customers must incorporate sufficient safety measures in their design, such as
redundancy, fire-containment and anti-failure features.
• NEC Electronics products are classified into the following three quality grades: "Standard", "Special" and
"Specific".
The "Specific" quality grade applies only to NEC Electronics products developed based on a customer-
designated "quality assurance program" for a specific application. The recommended applications of an NEC
Electronics product depend on its quality grade, as indicated below. Customers must check the quality grade of
each NEC Electronics product before using it in a particular application.
"Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio
and visual equipment, home electronic appliances, machine tools, personal electronic equipment
and industrial robots.
"Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support).
"Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems and medical equipment for life support, etc.
The quality grade of NEC Electronics products is "Standard" unless otherwise expressly specified in NEC
Electronics data sheets or data books, etc. If customers wish to use NEC Electronics products in applications
not intended by NEC Electronics, they must contact an NEC Electronics sales representative in advance to
determine NEC Electronics' willingness to support a given application.
(Note)
(1)
"NEC Electronics" as used in this statement means NEC Electronics Corporation and also includes its
majority-owned subsidiaries.
(2)
"NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as
defined above).
M8E 02. 11-1
相关型号：
UPD784927GF-A-A-A-3BA-A
16-BIT, MROM, 8MHz, MICROCONTROLLER, PQFP100, 14 X 20 MM, LEAD FREE, PLASTIC, QFP-100
RENESAS
UPD784927YGF-A-A-A-3BA
16-BIT, MROM, 8MHz, MICROCONTROLLER, PQFP100, 14 X 20 MM, PLASTIC, QFP-100
RENESAS
UPD784927YGF-A-A-A-3BA-A
16-BIT, MROM, 8MHz, MICROCONTROLLER, PQFP100, 14 X 20 MM, LEAD FREE, PLASTIC, QFP-100
RENESAS
UPD784928GC-A-A-A-8EU
16-BIT, MROM, 8MHz, MICROCONTROLLER, PQFP100, 14 X 14 MM, FINE PITCH, PLASTIC, LQFP-100
RENESAS
UPD784928GF-A-A-A-3BA
16-BIT, MROM, 8MHz, MICROCONTROLLER, PQFP100, 14 X 20 MM, PLASTIC, QFP-100
RENESAS
UPD784928GF-A-A-A-3BA-A
16-BIT, MROM, 8MHz, MICROCONTROLLER, PQFP100, 14 X 20 MM, LEAD FREE, PLASTIC, QFP-100
RENESAS
UPD784928GF-XXX-3BA
Microcontroller, 16-Bit, MROM, 8MHz, MOS, PQFP100, 14 X 20 MM, PLASTIC, QFP-100
NEC
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