UPD789167YGB-XXX-3BS [RENESAS]
8-BIT, MROM, MICROCONTROLLER, PQFP44, 10 X 10 MM, PLASTIC, QFP-44;
| 型号： | UPD789167YGB-XXX-3BS |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | 8-BIT, MROM, MICROCONTROLLER, PQFP44, 10 X 10 MM, PLASTIC, QFP-44 时钟 微控制器 光电二极管 外围集成电路 |
| 文件： | 总145页 (文件大小：592K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY PRODUCT INFORMATION
MOS INTEGRATED CIRCUIT
µPD789166Y,789167Y,789176Y,789177Y
8-BIT SINGLE-CHIP MICROCONTROLLER
The µPD789166Y, µPD789167Y, µPD789176Y, and µPD789177Y are µPD789167Y and µPD789177Y
sub-series products of the 78K/0S series.
These microcontrollers feature an 8-bit CPU, I/O ports, timers, a serial interface, A/D converters, and interrupt
control circuits.
In addition, a flash memory product (µPD78F9177Y) that can operate within the same voltage range as the
masked ROM models, and a range of related development tools are being developed.
The functions of these microcontrollers are described in the following user’s manuals. Refer to these
manuals when designing a system based on any of these microcontrollers.
µPD789177Y Sub-Series User’s Manual : To be created
78K/0S Series User’s Manual, Instruction: U11047E
FEATURES
•
ROM and RAM sizes
Item
Program memory
ROM
Data memory
Product name
Internal high-speed RAM
µPD789166Y
µPD789167Y
µPD789176Y
µPD789177Y
16 Kbytes
512 × 8 bits
24 Kbytes
16 Kbytes
24 Kbytes
•
Variable minimum instruction execution time: From high-speed (0.4 µs: With the main system clock running at
5.0 MHz) to very low-speed (122 µs: With the subsystem clock running at 32.768 kHz)
Eight A/D converters with 8-bit resolution (for µPD789166Y and µPD789167Y)
Eight A/D converters with an 10-bit resolution (for µPD789176Y and µPD789177Y)
31 I/O ports
•
•
•
•
Two serial interface channels:
•
•
Switchable between three-wire serial I/O and UART modes
System management bus (SMB)
•
Six timers:
•
•
•
•
16-bit timer counter
Three 8-bit timer/event counters
Clock timer
Watchdog timer
•
•
16-bit multiplier
Power supply voltage: VDD = 1.8 to 5.5 V
The information contained in this document is being issued in advance of the production cycle for the
device. The parameters for the device may change before final production or NEC Corporation, at its own
discretion, may withdraw the device prior to its production.
Document No. U13216EJ1V0PM00 (1st edition)
Date Published March 1998 J CP(K)
Printed in Japan
1998
©
U13216EJ1V0X100
July 1998 NS CP(K)
Supplement
[Document Name]
µ PD789166Y, 789167Y, 789176Y, 789177Y PRELIMINARY PRODUCT INFORMATION
[Document No., Date Published]
U13216EJ1V0PM00 (1st edition), March 1998 J CP(K)
before change
after change
µ PD789167,789177 Subseries
µ PD789167Y,789177Y Subseries
µ PD789166Y, 789167Y
µ PD789176Y, 789177Y
µ PD78F9177Y
Product Name
µ PD789166, 789167
µ PD789176, 789177
µ PD78F9177
42-pin plastic shrink DIP
44-pin plastic QFP
44-pin plastic QFP
Package
48-pin plastic TQFP
Part Number
µ PD789166YGB-xxx-3BS
µ PD789167YGB-xxx-3BS
µ PD789176YGB-xxx-3BS
µ PD789177YGB-xxx-3BS
µ PD78F9177YGB-3BS
On chip
µ PD789166GB-xxx-3BS-MTX
µ PD789167GB-xxx-3BS-MTX
µ PD789176GB-xxx-3BS-MTX
µ PD789177GB-xxx-3BS-MTX
µ PD78F9177GB-3BS-MTX
Not provided
SMB
µPD789166Y, 789167Y, 789176Y, 789177Y
APPLICATIONS
Power windows, keyless entries, battery management units, side air bags, etc.
ORDERING INFORMATION
Part number
Package
µPD789166YCU-×××
42-pin plastic shrink DIP (600 mil)
44-pin plastic QFP (10 × 10 mm)
48-pin plastic TQFP (fine pitch) (7 × 7 mm)
42-pin plastic shrink DIP (600 mil)
44-pin plastic QFP (10 × 10 mm)
48-pin plastic TQFP (fine pitch) (7 × 7 mm)
42-pin plastic shrink DIP (600 mil)
44-pin plastic QFP (10 × 10 mm)
48-pin plastic TQFP (fine pitch) (7 × 7 mm)
42-pin plastic shrink DIP (600 mil)
44-pin plastic QFP (10 × 10 mm)
48-pin plastic TQFP (fine pitch) (7 × 7 mm)
µPD789166YGB-×××-3BS
µPD789166YGA-×××-9EU
µPD789167YCU-×××
µPD789167YGB-×××-3BS
µPD789167YGA-×××-9EU
µPD789176YCU-×××
µPD789176YGB-×××-3BS
µPD789176YGA-×××-9EU
µPD789177YCU-×××
µPD789177YGB-×××-3BS
µPD789177YGA-×××-9EU
Remark ××× indicates ROM code suffix.
2
Preliminary Product Information
µPD789166Y, 789167Y, 789176Y, 789177Y
78K/0S SERIES DEVELOPMENT
The 78K/0S series products are shown below. The sub-series names are indicated in frames.
In production
Under development
For small-scale, general-
purpose applications
Device developed by enhancing the timers of the µPD789014 and
42/44-pin
28-pin
µPD789026
µPD789014
expanding ROM and RAM.
With built-in UART bus and capable of low-voltage (1.8 V) operation
For small-scale, general-purpose
applications and A/D function
44/48-pin
44/48-pin
RC oscillator version of the µPD789197Y
With built-in EEPROMTM in the µPD789177Y
Device developed by enhancing the A/D function of the PD789167Y
Device developed by enhancing the timers of the µPD789104, with
a built-in SMB
µPD789217Y
µPD789197Y
µPD789177Y
µPD789167Y
µPD789134
µPD789124
µPD789114
µPD789104
µ
42/44/48-pin
42/44/48-pin
28/30-pin
78K/0S
series
Device developed by enhancing the A/D function of the µPD789124
RC oscillator version of the PD789104
µ
28/30-pin
Device developed by enhancing the A/D function of the µPD789104
28/30-pin
28/30-pin
Device developed by adding the A/D function and multiplier to the
µ
PD789014
For LCD driving
µPD789417
Device developed by enhancing the A/D function of the µPD789407
80-pin
80-pin
Device developed by adding the A/D function and enhancing the
timers of the µPD789026
µPD789407
For ASSP
42/44-pin
5-pin
µPD789800
µPD789810
Device for a PC keyboard, with a built-in USB function
Device for an IC card, with a built-in security circuit
Preliminary Product Information
3
µPD789166Y, 789167Y, 789176Y, 789177Y
The following table lists the major differences in functions between the sub-series.
Function
Timer
8-bit
A/D
10-bit
A/D
Serial
Minimum
I/O
Remarks
ROM size
interface
VDD value
Sub-series
8-bit
1 ch
2 ch
3 ch
16-bit Clock WDT
Small-scale,
general
purpose
µPD789026
µPD789014
4 K-16 K
2 K-4 K
1 ch
−
−
1 ch
−
−
−
1 ch (UART: 1 ch)
34 pins
22 pins
1.8 V
−
applications
RC-oscillator
version, with
built-in
Small-scale,
general-
µPD789217Y 16 K-24 K
1 ch
1 ch
1 ch
8 ch 2 ch UART: 1 ch 31 pins
SMB : 1 ch
1.8 V
purpose
applications
and A/D
EEPROM
With built-in
EEPROM
µPD789197Y
function
µPD789177Y
µPD789167Y
−
8 ch
−
−
RC-oscillator
version
µPD789134
µPD789124
µPD789114
µPD789104
2 K-8 K
1 ch
−
4 ch 1 ch (UART: 1 ch)
20 pins
4 ch
−
−
4 ch
−
−
−
4 ch
−
−
LCD driving µPD789417
µPD789407
12 K-24 K
3 ch
1 ch
1 ch
1 ch
1 ch
7 ch 1 ch (UART: 1 ch)
43 pins
1.8 V
7 ch
−
−
2 ch (USB: 1 ch)
ASSP
µPD789800
µPD789810
8 K
6 K
2 ch
−
−
−
31 pins
1 pin
4.0 V
1.8 V
−
−
With built-in
EEPROM
4
Preliminary Product Information
µPD789166Y, 789167Y, 789176Y, 789177Y
FUNCTIONS
Product
µPD789166Y
µPD789167Y
µPD789176Y
µPD789177Y
Item
Internal memory
ROM
High-speed RAM
16 Kbytes
512 bytes
24 Kbytes
16 Kbytes
24 Kbytes
Minimum instruction execution time
• 0.4/1.6 µs (operation with main system clock (ceramic/crystal oscillation) running
at 5.0 MHz)
• 122 µs (operation with subsystem clock running at 32.768 kHz).
General-purpose registers
Instruction set
8 bits × 8 registers
• 16-bit operations
• Bit manipulations (such as set, reset, and test)
Multiplier
I/O ports
8 bits × 8 bits = 16 bits
Total of 31 port pins
• 8 CMOS input pins
• 17 CMOS input/output pins
• 6 N-channel open-drain pins
A/D converters
Serial interface
Eight channels with 8-bit resolution
Eight channels with 10-bit resolution
• Switchable between three-wire serial I/O and UART modes
• System management bus (SMB)
Timers
• 16-bit timer counter
• Three 8-bit timer/event counters
• Clock timer
• Watchdog timer
Timer output
Buzzer output
Four outputs
One output
Vectored interrupt
sources
Maskable
12 internal and 4 external interrupts
Internal interrupt
Nonmaskable
Power supply voltage
VDD = 1.8 to 5.5 V
TA = −40°C to +85°C
Operating ambient temperature
Package
42-pin plastic shrink DIP (600 mil)
44-pin plastic QFP (10 × 10 mm)
48-pin plastic TQFP (fine pitch) (7 × 7 mm)
Preliminary Product Information
5
µPD789166Y, 789167Y, 789176Y, 789177Y
CONTENTS
1. PIN CONFIGURATION (TOP VIEW) .................................................................................................
8
2. BLOCK DIAGRAM............................................................................................................................. 12
3. PIN FUNCTIONS................................................................................................................................ 13
3.1 Port Pins.................................................................................................................................................. 13
3.2 Non-Port Pins.......................................................................................................................................... 14
3.3 Pin Input/Output Circuits and Handling of Unused Pins .................................................................... 15
4. CPU ARCHITECTURE....................................................................................................................... 17
4.1 Memory Space ........................................................................................................................................ 17
4.2 Data Memory Addressing ...................................................................................................................... 18
4.3 Processor Registers............................................................................................................................... 19
5. PERIPHERAL HARDWARE FUNCTIONS ........................................................................................ 24
5.1 Ports ........................................................................................................................................................ 24
5.2 Clock Generator...................................................................................................................................... 31
5.3 16-Bit Timer Counter .............................................................................................................................. 36
5.4 8-Bit Timer/Event Counter ..................................................................................................................... 43
5.5 Clock Timer............................................................................................................................................. 50
5.6 Watchdog Timer ..................................................................................................................................... 53
5.7 A/D Converter.......................................................................................................................................... 57
5.8 Serial Interface........................................................................................................................................ 62
5.9 Multiplier.................................................................................................................................................. 91
6. INTERRUPT FUNCTIONS ................................................................................................................. 94
6.1 Interrupt Function Types ....................................................................................................................... 94
6.2 Interrupt Sources and Configuration.................................................................................................... 94
6.3 Interrupt Function Control Registers.................................................................................................... 97
7. STANDBY FUNCTION....................................................................................................................... 103
7.1 Standby Function ................................................................................................................................... 103
7.2 Standby Function Control Register ...................................................................................................... 106
8. RESET FUNCTIONS.......................................................................................................................... 107
9. MASK OPTIONS ................................................................................................................................ 110
10. INSTRUCTION SET OVERVIEW....................................................................................................... 111
10.1 Legend..................................................................................................................................................... 111
10.2 Operations............................................................................................................................................... 113
6
Preliminary Product Information
µPD789166Y, 789167Y, 789176Y, 789177Y
11. ELECTRICAL CHARACTERISTICS.................................................................................................. 118
12. PACKAGE DRAWINGS..................................................................................................................... 133
APPENDIX A DEVELOPMENT TOOLS................................................................................................. 136
APPENDIX B RELATED DOCUMENTS ................................................................................................ 138
Preliminary Product Information
7
µPD789166Y, 789167Y, 789176Y, 789177Y
1. PIN CONFIGURATION (TOP VIEW)
•
42-pin plastic shrink DIP (600 mil)
µPD789166YCU-×××
µPD789167YCU-×××
µPD789176YCU-×××
µPD789177YCU-×××
P51
P52
1
2
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
P50
P05
P53
3
P04
AVDD
4
P03
AVREF
5
P02
P60/ANI0
6
P01
P61/ANI1
7
P00
P62/ANI2
8
P26/TO80
P25/TI80/SS20
P63/ANI3
9
P64/ANI4
10
11
12
13
14
15
16
17
18
19
20
21
V
DD
SS
P65/ANI5
V
P66/ANI6
X1
P67/ANI7
X2
AVSS
RESET
XT1
P10
P11
XT2
P30/INTP0/TI81/CPT90
P31/INTP1/TO81
P32/INTP2/TO90
P33/INTP3/TO82/BZO90
P20/SCK20/ASCK20
IC
P24/SDA0
P23/SCL0
P22/SI20/R
X
D20
P21/SO20/T
X
D20
Cautions 1. Connect the IC (internally connected) pin directly to the VSS pin.
2. Connect the AVDD pin to the VDD pin.
3. Connect the AVSS pin to the VSS pin.
8
Preliminary Product Information
µPD789166Y, 789167Y, 789176Y, 789177Y
•
44-pin plastic QFP (10 × 10 mm)
µPD789166YGB-×××-3BS
µPD789167YGB-×××-3BS
µPD789176YGB-×××-3BS
µPD789177YGB-×××-3BS
44 43 42 41 40 39 38 37 36 35 34
P60/ANI0
P61/ANI1
P62/ANI2
P63/ANI3
P64/ANI4
P65/ANI5
P66/ANI6
P67/ANI7
AVSS
P01
1
33
32
31
30
29
28
27
26
25
24
23
P00
2
P26/TO80
P25/TI80/SS20
3
4
V
V
DD
5
SS
6
X1
7
X2
8
RESET
XT1
XT2
9
P10
10
11
P11
12 13 14 15 16 17 18 19 20 21 22
Cautions 1. Connect the IC (internally connected) pin directly to the VSS pin.
2. Connect the AVDD pin to the VDD pin.
3. Connect the AVSS pin to the VSS pin.
Preliminary Product Information
9
µPD789166Y, 789167Y, 789176Y, 789177Y
•
48-pin plastic TQFP (fine pitch) (7 × 7 mm)
µPD789166YGA-×××-9EU
µPD789167YGA-×××-9EU
µPD789176YGA-×××-9EU
µPD789177YGA-×××-9EU
48 47 46 45 44 43 42 41 40 39 38 37
1
36
35
34
33
32
31
30
29
28
27
26
25
P01
P60/ANI0
P61/ANI1
P62/ANI2
P63/ANI3
P64/ANI4
P65/ANI5
P66/ANI6
P67/ANI7
AVSS
2
P00
3
P26/TO80
P25/TI80/SS20
4
5
V
DD
6
NC
7
V
SS
8
X1
9
X2
10
11
12
RESET
XT1
XT2
P10
P11
NC
13 14 15 16 17 18 19 20 21 22 23 24
Cautions 1. Connect the IC (internally connected) pin directly to the VSS pin.
2. Connect the AVDD pin to the VDD pin.
3. Connect the AVSS pin to the VSS pin.
10
Preliminary Product Information
µPD789166Y, 789167Y, 789176Y, 789177Y
ANI0-ANI7
ASCK20
AVDD
: Analog Input
RESET
RxD20
SCK20
SCL0
: Reset
: Asynchronous Serial Input
: Analog Power Supply
: Analog Reference Voltage
: Analog Ground
: Receive Data
: Serial Clock (for SIO20)
: Serial Clock (for SMB0)
: Serial Data
AVREF
AVSS
SDA0
BZO90
CPT90
IC
: Buzzer Output
SI20
: Serial Input
: Capture Trigger Input
: Internally Connected
SO20
: Serial Output
: Chip Select Input
: Timer Input
SS20
INTP0-INTP3 : Interrupt from Peripherals
TI80, TI81
NC
: Non-connection
: Port 0
TO80-TO82, TO90 : Timer Output
P00-P05
P10, P11
P20-P26
P30-P33
P50-P53
P60-P67
TxD20
VDD
: Transmit Data
: Port 1
: Power Supply
: Port 2
VSS
: Ground
: Port 3
X1, X2
XT1, XT2
: Crystal (Main System Clock)
: Crystal (Subsystem Clock)
: Port 5
: Port 6
Preliminary Product Information
11
µPD789166Y, 789167Y, 789176Y, 789177Y
2. BLOCK DIAGRAM
TI80/SS20/P25
P00-P05
P10, P11
P20-P26
P30-P33
P50-P53
P60-P67
PORT0
PORT1
PORT2
PORT3
PORT5
PORT6
8-bit TIMER80
TO80/P26
TI81/INTP0/CPT90/P30
TO81/INTP1/P31
8-bit TIMER81
8-bit TIMER82
TO82/INTP3/BZO90/P33
CPT90/INTP0/TI81/P30
TO90/INTP2/P32
BZO90/INTP3/TO82/P33
16-bit TIMER90
78K/0S
CPU CORE
ROM
WATCH TIMER
WATCHDOG TIMER
RESET
X1
SCK20/ASCK20/P20
SO20/TXD20/P21
SI20/RXD20/P22
SS20/TI80/P25
SIO20
SMB0
SYSTEM
CONTROL
X2
RAM
XT1
XT2
SDA0/P24
SCL0/P23
INTP0/TI81/CPT90/P30
INTP1/TO81/P31
INTERRUPT
CONTROL
INTP2/TO90/P32
ANI0/P60-
ANI7/P67
INTP3/TO82/BZO90/P33
AVDD
AVSS
A/D CONVERTER
Multiplier
AVREF
VDD
VSS
IC
Remark The size of the internal ROM varies depending on the model.
12
Preliminary Product Information
µPD789166Y, 789167Y, 789176Y, 789177Y
3. PIN FUNCTIONS
3.1 Port Pins
Pin name
P00-P05
I/O
I/O
Function
When reset
Input
Also used as
Port 0
−
6-bit input/output port
Can be set to either input or output in 1-bit units
When used as an input port, whether the on-chip pull-up resistor is
to be used can be set by software.
P10, P11
I/O
I/O
Port 1
Input
Input
−
2-bit input/output port
Can be set to either input or output in 1-bit units
When used as an input port, whether the on-chip pull-up resistor is
to be used can be set by software.
Port 2
P20
P21
P22
P23
P24
P25
P26
P30
P31
P32
P33
P50-P53
SCK20/ASCK20
SO20/TxD20
SI20/RxD20
SCL0
7-bit input/output port
Can be set to either input or output in 1-bit units
For P20 to P22, P25, and P26, whether to use the on-chip pull-up
resistor can be set by software.
Only P23 and P24 can be used as N-channel open-drain
input/output port pins.
SDA0
TI80/SS20
TO80
Port 3
I/O
Input
INTP0/TI81/CPT90
INTP1/TO81
INTP2/TO90
INTP3/TO82/BZO90
−
4-bit input/output port
Can be set to either input or output in 1-bit units
Whether to use the on-chip pull-up resistor can be set by software.
I/O
Port 5
Input
Input
4-bit N-channel open-drain input/output port
Can be set to either input or output in 1-bit units
Whether to incorporate a pull-up resistor can be set by a mask
option.
P60-P67
Input
Port 6
ANI0-ANI7
8-bit input-only port
Preliminary Product Information
13
µPD789166Y, 789167Y, 789176Y, 789177Y
3.2 Non-Port Pins
Pin name
INTP0
I/O
Function
When reset
Input
Also used as
External interrupt input for which effective edges (rising and/or
falling edges) can be set
Input
P30/TI81/CPT90
INTP1
INTP2
INTP3
SI20
P31/TO81
P32/TO90
P33/TO82/BZO90
Input
Serial data input to serial interface
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
−
P22/RxD20
SO20
SCK20
ASCK20
RxD20
TxD20
SCL0
SDA0
SS20
TI80
Output Serial data output from serial interface
P21/TxD20
I/O
Serial clock input/output for serial interface
P20/ASCK20
Input
Input
Serial clock input to asynchronous serial interface
Serial data input to asynchronous serial interface
P20/SCK20
P22/SI20
Output Serial data output from asynchronous serial interface
P21/SO20
I/O
I/O
SMB0 clock input/output
P23
SMB0 data input/output
P24
Input
Input
Input
Chip select input to serial interface
External count clock input to 8-bit timer (TM80)
External count clock input to 8-bit timer (TM81)
P25/TI80
P25/SS20
TI81
P30/INTP0/CPT90
TO80
TO81
TO82
TO90
CPT90
BZO90
ANI0-ANI7
AVREF
AVSS
Output 8-bit timer (TM80) output
Output 8-bit timer (TM81) output
Output 8-bit timer (TM82) output
Output 16-bit timer (TM90) output
P26
P31/INTP1
P33/INTP3/BZO90
P32/INTP2
Input
Capture edge input
P30/INTP0/TI81
Output Buzzer output
P33/INTP3/TO82
Input
A/D converter analog input
P60-P67
−
A/D converter reference voltage
−
−
−
−
−
−
−
−
−
−
−
−
A/D converter ground potential
−
AVDD
−
Input
−
A/D converter analog power supply
Connected to crystal for main system clock oscillation
−
X1
−
X2
−
XT1
Input
−
Connected to crystal for subsystem clock oscillation
−
XT2
−
RESET
VDD
Input
−
System reset input
Positive supply voltage
Ground potential
Input
−
VSS
−
−
IC
−
This pin is internally connected. Connect this pin directly to the
VSS pin.
−
NC
−
This pin is not connected internally. Connect this pin to the VSS
pin (or leave this pin open).
−
−
14
Preliminary Product Information
µPD789166Y, 789167Y, 789176Y, 789177Y
3.3 Pin Input/Output Circuits and Handling of Unused Pins
Table 3-1 lists the types of input/output circuits for each pin and explains how unused pins are handled.
Figure 3-1 shows the configuration of each type of input/output circuit.
Table 3-1. Type of Input/Output Circuit for Each Pin and Handling of Unused Pins
Pin name
P00-P05
I/O circuit type
5-A
I/O
I/O
Recommended connection of unused pins
Connect these pins to the VDD or VSS pin via respective resistors.
P10, P11
P20/SCK20/ASCK20
P21/SO20/TxD20
P22/SI20/RxD20
P23/SCL0
8-A
13-AA
8-C
P24/SDA0
P25/TI80/SS20
P26/TO80
P30/INTP0/TI81/CPT90
P31/INTP1/TO81
P32/INTP2/TO90
P33/INTP3/TO82/BZO90
P50-P53
13-W
9-C
−
P60/ANI0-P67/ANI7
XT1
Input
Input
−
Connect this pin to the VSS pin.
Leave this pin open.
XT2
RESET
2
−
−
Input
−
−
IC
Connect this pin directly to the VSS pin.
NC
−
Preliminary Product Information
15
µPD789166Y, 789167Y, 789176Y, 789177Y
Figure 3-1. Pin Input/Output Circuits
Type 2
Type 9-C
Comparator
P-ch
N-ch
+
IN
Ð
IN
AVSS
VREF
(Threshold voltage)
Schmitt trigger input with hysteresis
Input
enable
Type 13-W
Type 5-A
VDD
VDD
Pull-up resistor
(mask option)
Pull-up
enable
P-ch
IN/OUT
VDD
P-ch
Output data
Output disable
N-ch
Data
IN/OUT
VSS
Output
disable
N-ch
Input enable
VSS
Input buffer with intermediate withstand voltage
Input
enable
Type 13-AA
Type 8-A
VDD
Pull-up
enable
P-ch
IN/OUT
VDD
Output data
N-ch
Output disable
Data
P-ch
VSS
IN/OUT
Input buffer with 5-V
Output
disable
N-ch
withstand voltage
VSS
Comparator
16
Preliminary Product Information
µPD789166Y, 789167Y, 789176Y, 789177Y
4. CPU ARCHITECTURE
4.1 Memory Space
The µPD789166Y, µPD789167Y, µPD789176Y, and µPD789177Y can each access up to 64 Kbytes of memory
space. Figure 4-1 shows the memory map.
Figure 4-1. Memory Map
F F F F H
Special function register
256 × 8 bits
F F 0 0 H
F E F F H
Internal high-speed RAM
512 × 8 bits
F D 0 0 H
F C F F H
Data memory space
n n n n H
Unusable
n n n n H + 1
n n n n H
Program area
0 0 8 0 H
0 0 7 F H
Program memory
space
Internal ROMNote
CALLT table area
0 0 4 0 H
0 0 3 F H
Program area
0 0 2 4 H
0 0 2 3 H
Vector table area
0 0 0 0 H
0 0 0 0 H
Note The size of the internal ROM varies depending on the model (see the following table).
Product name
Last address of internal ROM
nnnnH
µPD789166Y and µPD789176Y
µPD789167Y and µPD789177Y
3FFFH
5FFFH
Preliminary Product Information
17
µPD789166Y, 789167Y, 789176Y, 789177Y
4.2 Data Memory Addressing
Each of the µPD789166Y, µPD789167Y, µPD789176Y, and µPD789177Y is provided with a wide range of
addressing modes to make memory manipulation as efficient as possible. A data memory area (FD00H to FFFFH)
can be accessed using a unique addressing mode according to its use, such as a special function register (SFR).
Figure 4-2 illustrates the data memory addressing modes.
Figure 4-2. Data Memory Addressing Modes
F F F F H
Special function register (SFR)
SFR addressing
256 × 8 bits
F F 2 0 H
F F 1 F H
F F 0 0 H
F E F F H
Short direct addressing
Internal high-speed RAM
512 × 8 bits
F E 2 0 H
F E 1 F H
Direct addressing
Register indirect addressing
Based addressing
F D 0 0 H
F C F F H
Unusable
n n n n H + 1
n n n n H
Internal ROMNote
0 0 0 0 H
Note The size of internal ROM varies depending on the model (see the following table).
Product name
Last address of internal ROM
nnnnH
µPD789166Y and µPD789176Y
µPD789167Y and µPD789177Y
3FFFH
5FFFH
18
Preliminary Product Information
µPD789166Y, 789167Y, 789176Y, 789177Y
4.3 Processor Registers
4.3.1 Controller registers
(1) Program counter (PC)
The PC is a 16-bit register for holding address information that indicates the next program to be executed.
Figure 4-3. Program Counter Configuration
15
0
PC
PC13 PC12 PC11PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0
PC15 PC14
(2) Program status word (PSW)
The PSW is an 8-bit register for holding the status of the CPU according to the results of instruction execution.
Figure 4-4. Program Status Word Configuration
7
0
PSW
IE
Z
0
AC
0
0
1
CY
(a) Interrupt enable flag (IE)
IE is used to control whether interrupt requests are to be accepted by the CPU.
(b) Zero flag (Z)
Z is set (1) if the result of operation is zero. Otherwise, it is reset (0).
(c) Auxiliary carry flag (AC)
AC is set (1) if the result of the operation has a carry from bit 3 or a borrow to bit 3. Otherwise, it is reset (0).
(d) Carry flag (CY)
CY is used to indicate whether an overflow or underflow has occurred during the execution of a subtract or
add instruction.
(3) Stack pointer (SP)
SP is a 16-bit register for holding the start address of a stack area. The stack area can be specified only in an
area (FD00H to FEFFH) of internal high-speed RAM.
Figure 4-5. Stack Pointer Configuration
15
0
SP13
SP11
SP8
SP6 SP5
SP7 SP4 SP3 SP2 SP1 SP0
SP15 SP14
SP12
SP10 SP9
SP
Caution A RESET input makes the SP content undefined. Before executing an instruction, always
initialize the SP.
Preliminary Product Information
19
µPD789166Y, 789167Y, 789176Y, 789177Y
4.3.2 General-purpose registers
Each device has eight 8-bit general-purpose registers (X, A, C, B, E, D, L, and H).
These registers can be used as 16-bit registers (two 8-bit registers used in pairs like AX, BC, DE, and HL) as well
as ordinary 8-bit registers.
These registers are identified using functional register names (X, A, C, B, E, D, L, H, AX, BC, DE, and HL) and
absolute register names (R0 to R7 and RP0 to RP3).
Figure 4-6. General-Purpose Register Configuration
(a) Absolute register names
16-bit processing
RP3
8-bit processing
R7
R6
R5
R4
R3
R2
R1
R0
RP2
RP1
RP0
15
0
7
0
(b) Functional register names
16-bit processing
HL
8-bit processing
H
L
D
E
B
C
A
X
DE
BC
AX
15
0
7
0
20
Preliminary Product Information
µPD789166Y, 789167Y, 789176Y, 789177Y
4.3.3 Special function registers (SFRs)
The SFRs are used as peripheral hardware mode registers and control registers. They are mapped in a 256-byte
space, from FF00H to FFFFH.
Table 4-1. Special Function Registers (1/3)
Address Special function register (SFR) name
Symbol
R/W Number of bits manipulated simultaneously When reset
1 bit
Ο
8 bits
Ο
16 bits
FF00H Port 0
FF01H Port 1
FF02H Port 2
FF03H port 3
FF05H Port 5
FF06H Port 6
P0
P1
P2
P3
P5
P6
R/W
−
−
−
−
−
−
00H
Ο
Ο
Ο
Ο
Ο
Ο
Ο
Ο
R
R
Ο
Ο
ΟNote 2
ΟNote 3
Note 1
FF10H
−
Undefined
MUL0L
MUL0H
ADCR0
16-bit multiplication result storage
MUL0
register 0
FF11H
A/D conversion result register 0Note 4
FF14H
R
W
R
−
−
−
−
Ο
Ο
FF15H
ΟNote 2
ΟNote 2
ΟNote 2
ΟNote 3
ΟNote 3
ΟNote 3
Note 1
FF16H 16-bit compare register 90
FF17H
FFFFH
0000H
Undefined
FFH
CR90L
CR90H
TM90L
TM90H
TCP90L
TCP90H
PM0
CR90
Note 1
FF18H 16-bit timer register 90
FF19H
TM90
Note 1
FF1AH 16-bit capture register 90
FF1BH
TCP90
FF20H Port mode register 0
FF21H Port mode register 1
FF22H Port mode register 2
FF23H Port mode register 3
FF25H Port mode register 5
FF32H Pull-up resistor option register B2
FF33H Pull-up resistor option register B3
FF42H Timer clock selection register 2
R/W
Ο
Ο
Ο
Ο
Ο
Ο
Ο
Ο
Ο
Ο
Ο
Ο
Ο
Ο
Ο
Ο
−
−
−
−
−
−
−
−
PM1
PM2
PM3
PM5
PUB2
PUB3
TCL2
00H
Notes 1. MUL0, CR90, TM90, and TCP90 are those SFR symbols used only in 16-bit access mode.
2. MUL0, CR90, TM90, and TCP90 are designed only for 16-bit access. With direct addressing, however,
they can also be accessed in 8-bit mode.
3. 16-bit access is allowed only with short direct addressing.
4. When 8-bit A/D converters are used (for the µPD789166Y and µPD789167Y), this register can be
accessed only in 8-bit mode. In this case, the address is assumed to be FF15H.
When 10-bit A/D converters are used (for the µPD789176Y and µPD789177Y), this register can be
accessed only in 16-bit mode.
When the µPD78F9177Y is used as flash memory for the µPD789166Y or µPD789167Y, 8-bit access
is allowed. However, only those object files generated by an assembler used with the µPD789166Y or
µPD789167Y are supported for this access.
Preliminary Product Information
21
µPD789166Y, 789167Y, 789176Y, 789177Y
Table 4-1. Special Function Registers (2/3)
Address Special function register (SFR) name Symbol R/W Number of bits manipulated simultaneously When reset
1 bit
Ο
Ο
Ο
−
8 bits
Ο
16 bits
FF48H 16-bit timer mode control register 90 TMC90
R/W
−
−
−
−
−
−
−
−
−
−
−
−
−
00H
FF49H Buzzer output control register 90
FF4AH Clock timer mode control register
FF50H 8-bit compare register 80
FF51H 8-bit timer register 80
BZC90
WTM
CR80
TM80
Ο
Ο
W
R
Ο
Undefined
00H
−
Ο
FF53H 8-bit timer mode control register 80 TMC80
R/W
W
Ο
−
Ο
FF54H 8-bit compare register 81
FF55H 8-bit timer register 81
CR81
TM81
Ο
Undefined
00H
R
−
Ο
FF57H 8-bit timer mode control register 81 TMC81
R/W
W
Ο
−
Ο
FF58H 8-bit compare register 82
FF59H 8-bit timer register 82
CR82
TM82
Ο
Undefined
00H
R
−
Ο
FF5BH 8-bit timer mode control register 82 TMC82
R/W
Ο
Ο
Ο
FF70H Asynchronous serial interface mode ASIM20
register 20
Ο
FF71H Asynchronous serial interface
status register 20
ASIS20
R
−
Ο
−
FF72H Serial operation mode register 20
CSIM20
R/W
Ο
Ο
Ο
Ο
−
−
FF73H Baud rate generator control register BRGC20
20
FF74H Transmission shift register 20
Reception buffer register 20
SIO20
W
R
−
Ο
Ο
Ο
Ο
Ο
Ο
Ο
Ο
Ο
Ο
Ο
Ο
Ο
Ο
Ο
Ο
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
FFH
TXS20
−
Undefined
00H
RXB20
FF78H SMB control register 0
SMBC0
SMBS0
R/W
R
Ο
Ο
Ο
Ο
Ο
Ο
Ο
Ο
Ο
Ο
Ο
Ο
Ο
Ο
FF79H SMB status register 0
FF7AH SMB clock selection register 0
FF7BH SMB slave address register 0
FF7CH SMB mode register 0
SMBCL0
SMBSVA0
SMBM0
SMBVI0
SMB0
ADM0
ADS0
R/W
20H
00H
FF7DH SMB input level setting register 0
FF7EH SMB shift register 0
FF80H A/D converter mode register 0
FF84H A/D input selection register 0
FFD0H Multiplication data register A0
FFD1H Multiplication data register B0
FFD2H Multiplier control register 0
FFE0H Interrupt request flag register 0
FFE1H Interrupt request flag register 1
MRA0
MRB0
MULC0
IF0
W
Undefined
00H
R/W
IF1
22
Preliminary Product Information
µPD789166Y, 789167Y, 789176Y, 789177Y
Table 4-1. Special Function Registers (3/3)
Address Special function register (SFR) name
Symbol
R/W Number of bits manipulated simultaneously When reset
1 bit
Ο
Ο
−
8 bits
Ο
16 bits
FFE4H Interrupt mask flag register 0
FFE5H Interrupt mask flag register 1
FFECH External interrupt mode register 0
FFEDH External interrupt mode register 1
FFF0H Suboscillation mode register
FFF2H Subclock control register
MK0
R/W
−
−
−
−
−
−
−
−
−
FFH
00H
MK1
Ο
INTM0
INTM1
SCKM
CSS
Ο
−
Ο
Ο
Ο
Ο
Ο
−
Ο
Ο
FFF7H Pull-up resistor option register 0
FFF9H Watchdog timer mode register
PU0
Ο
WDTM
OSTS
Ο
FFFAH Oscillation settling time selection
register
Ο
04H
02H
FFFBH Processor clock control register
PCC
Ο
Ο
−
Preliminary Product Information
23
µPD789166Y, 789167Y, 789176Y, 789177Y
5. PERIPHERAL HARDWARE FUNCTIONS
5.1 Ports
5.1.1 Port functions
The µPD789166Y, µPD789167Y, µPD789176Y, and µPD789177Y are provided with the ports shown in Figure
5-1. These ports are used to enable several types of control. Table 5-1 lists the functions of each port.
These ports, while originally designed as digital input/output ports, can also be used for other functions, as
summarized in Chapter 3.
Figure 5-1. Port Types
P00
P05
P30
P33
P50
Port 3
Port 5
Port 0
Port 1
P10
P11
P53
P60
P20
Port 2
Port 6
P26
P67
24
Preliminary Product Information
µPD789166Y, 789167Y, 789176Y, 789177Y
Table 5-1. Port Functions
Port name
Port 0
Pin name
P00-P05
Description
Input/output port. Each bit of the port can be separately specified as being for input or output.
A port used for input can be connected to an on-chip pull-up resistor by means of software
specification.
Port 1
Port 2
P10, P11
P20-P26
Input/output port. Each bit of the port can be separately specified as being for input or output.
A port used for input can be connected to an on-chip pull-up resistor by means of software
specification.
Input/output port. Each bit of the port can be separately specified as being for input or output.
Each of P20 to P22, P25, and P26 can be connected to an on-chip pull-up resistor by means of
software specification.
(P23 and P24 are used as N-channel open-drain input/output ports (with 5-V withstand
voltage).)
Port 3
Port 5
P30-P33
P50-P53
Input/output port. Each bit of the port can be separately specified as being for input or output.
The port can be connected to an on-chip pull-up resistor by means of software specification.
N-channel open-drain input/output port. Each bit of the port can be separately specified as
being for input or output.
Whether the port itself is to contain a pull-up resistor is specified with a mask option.
Port 6
P60-P67
Input-only port
Preliminary Product Information
25
µPD789166Y, 789167Y, 789176Y, 789177Y
5.1.2 Port configuration
The hardware configuration of the ports is as follows.
Table 5-2. Port Configuration
Item
Configuration
Port mode register (PMm, where m = 0, 1, 2, 3, or 5)
Control register
Pull-up resistor option registers (PU0, PUB2, and PUB3)
Port pins
Total: 31 (17 CMOS input/output, 8 CMOS input-only, and 6 N-ch open-drain input/output pins)
Pull-up resistors
Total: 21 (on-chip pull-up resistors can be used as specified by software, and whether a port itself is
to contain pull-up resistors can be specified with a mask option)
Figure 5-2. Basic CMOS Port Configuration
VDD
WRPUm
Note
P-ch
WRPORTm
WRPORTm
Output latch
(Pmn)
Pmn
WRPMm
PMmn
Note Each bit of the pull-up resistor option registers (PU0, PUB2, and PUB3)
PU00 and PU01 for PU0
PUB20 to PUB22, PUB25, and PUB26 for PUB2
PUB30 to PUB33 for PUB3
For details, see (2) in Section 5.1.3.
Caution Figure 5-2 shows the basic configuration of the CMOS input/output ports. The configuration
differs depending on the functions assigned to the dual-function pins.
P23, P24, and port 5 are not included in the basic configuration because they are used as
N-channel open-drain input/output ports.
26
Preliminary Product Information
µPD789166Y, 789167Y, 789176Y, 789177Y
Remark PMmn : Bit n of port mode register m, where m = 0 to 3 and n = 0 to 7
Pmn : Bit n of port m
RD : Port read signal
WR : Port write signal
For details, see (2) in Section 5.1.3.
5.1.3 Port function control registers
The following two types of registers are used to control the ports.
•
•
Port mode registers (PM0 to PM3, and PM5)
Pull-up resistor option registers (PU0, PUB2, and PUB3)
(1) Port mode registers (PM0 to PM3, and PM5)
The port mode registers separately specify each port bit as being for input or output.
Each port mode register is manipulated using a 1-bit or 8-bit memory manipulation instruction.
A RESET input writes FFH into the port mode registers.
When port pins are used for secondary functions, the corresponding port mode register and output latch must
be set or reset as described in Table 5-3.
Caution When port 3 is acting as an output port, and its output level is changed, an interrupt
request flag is set, because this port is also used as the input for an external interrupt.
To use port 3 in output mode, therefore, the interrupt mask flag must be set to 1 in
advance.
Preliminary Product Information
27
µPD789166Y, 789167Y, 789176Y, 789177Y
Table 5-3. Port Mode Register and Output Latch Settings for Using Secondary Functions
Pin name
Secondary function
Name Input/output
PM××
P××
P23
SCL0
SDA0
TI80
Input/output
0
0
1
0
1
1
1
1
0
1
0
1
0
0
1
0
0
×
0
×
×
×
×
0
×
0
×
0
0
×
P24
P25
P26
P30
Input/output
Input
TO80
INTP0
TI81
Output
Input
Input
CPT90
INTP1
TO81
INTP2
TO90
INTP3
TO82
BZO90
Input
P31
P32
P33
Input
Output
Input
Output
Input
Output
Output
Input
P60-P67
ANI0-ANI7
Caution When port 2 is being used as a serial interface, it is necessary to specify whether the port is an
input or output port, and to set the output latch accordingly. See Table 5-13 for an explanation
of how to make this specification.
Remark
×
: Don’t care
PM×× : Port mode register
P×× : Port output latch
28
Preliminary Product Information
µPD789166Y, 789167Y, 789176Y, 789177Y
Figure 5-3. Format of Port Mode Register
Address When reset R/W
Symbol
PM0
7
6
1
5
4
3
2
1
0
1
PM05
PM04
PM03
PM02
PM01
PM00
FF20H
FFH
R/W
PM1
PM2
1
1
1
1
1
1
1
PM11
PM21
PM10
PM20
FF21H
FFH
R/W
FF22H
PM26
PM25
PM24
PM23
PM22
FFH
FFH
FFH
R/W
R/W
R/W
PM3
PM5
1
1
1
1
1
1
1
1
PM33
PM53
PM32
PM52
PM31
PM51
PM30
PM50
FF23H
FF25H
Pmn pin input/output mode selection
(m = 0 to 3 or 5; n = 0 to 7)
PMmn
0
1
Output mode (output buffer ON)
Input mode (output buffer OFF)
(2) Pull-up resistor option registers (PU0, PUB2, PUB3)
These registers are used to specify pull-up resistor connection on a port-by-port basis and bit-by-bit basis.
The method of pull-up resistor connection varies, depending on whether a connection is made on a port-by-
port basis or bit-by-bit basis as described below.
(a) Pull-up resistor option register (PU0)
This register is used for port-by-port specification. An on-chip pull-up resistor can be used only for those
bits set to the input mode of a port for which the use of the on-chip pull-up resistor is specified using PU0.
For those bits set to the output mode, on-chip pull-up resistors cannot be used, regardless of the setting
of PU0. This also applies to a dual-function pin used as an output pin.
A RESET input clears PU0 to 00H.
(b) Pull-up resistor option registers (PUB2, PUB3)
These registers are used for bit-by-bit specification. By setting PUB2 or PUB3, an on-chip pull-up resistor
can be used, regardless of the setting of the port mode register.
A RESET input clears PUB2 and PUB3 to 00H.
Preliminary Product Information
29
µPD789166Y, 789167Y, 789176Y, 789177Y
Figure 5-4. Format of Pull-Up Resistor Option Register 0
Symbol
PU0
7
0
6
0
5
0
4
0
3
0
1
0
Address When reset R/W
FFF7H 00H R/W
2
0
PU01
PU00
Pm on-chip pull-up resistor selectionNote
(m = 0 or 1)
PU0m
0
1
On-chip pull-up resistor not used
On-chip pull-up resistor used
Note For each port, PU0 selects whether on-chip pull-up resistors are to be used.
Caution Bits 2 to 7 must be fixed to 0.
Figure 5-5. Format of Pull-Up Resistor Option Register B2
1
Address When reset R/W
FF32H 00H R/W
Symbol
PUB2
7
0
4
0
3
0
0
5
2
6
PUB26
PUB25
PUB22
PUB21
PUB20
P2m on-chip pull-up resistor selectionNote
(m = 0 to 2, 5, or 6)
PUB2m
0
1
On-chip pull-up resistor not used
On-chip pull-up resistor used
Note PUB2 selects whether on-chip pull-up resistors are to be used in 1-bit units.
Caution Bits 3, 4, and 7 must be fixed to 0.
Figure 5-6. Format of Pull-Up Resistor Option Register B3
Address When reset R/W
FF33H 00H R/W
Symbol
PUB3
7
0
6
0
5
0
4
0
3
0
2
1
PUB33
PUB32
PUB31
PUB30
P3m on-chip pull-up resistor selectionNote
(m = 0 to 3)
PUB3m
0
1
On-chip pull-up resistor not used
On-chip pull-up resistor used
Note PUB3 selects whether on-chip pull-up resistors are to be used in 1-bit units.
Caution Bits 4 to 7 must be fixed to 0.
30
Preliminary Product Information
µPD789166Y, 789167Y, 789176Y, 789177Y
5.2 Clock Generator
5.2.1 Clock generator functions
The clock generator generates the clock pulse to be supplied to the CPU and peripheral hardware. There are two
types of system clock oscillators:
•
•
Main system clock oscillator (ceramic or crystal oscillation)
This circuit generates a frequency of 1.0 to 5.0 MHz. Oscillation can be stopped by executing the STOP
instruction or by using the processor clock control register.
Subsystem clock oscillator
This circuit generates 32.768 kHz. Oscillation can be stopped by using the suboscillation mode register.
5.2.2 Clock generator configuration
The clock generator consists of the following hardware.
Table 5-4. Clock Generator Configuration
Item
Configuration
Control register
Processor clock control register (PCC)
Suboscillation mode register (SCKM)
Subclock control register (CSS)
Oscillator
Main system clock oscillator
Subsystem clock oscillator
Preliminary Product Information
31
µPD789166Y, 789167Y, 789176Y, 789177Y
Figure 5-7. Block Diagram of Clock Generator
Internal bus
FRC SCC
Suboscillation mode register
(SCKM)
16-bit timer 90
8-bit timer 82
Clock timer
XT1
XT2
Subsystem
clock
oscillator
fXT
Prescaler
1/2
Clock for
peripheral
hardware
X1
X2
Main system
clock
oscillator
f
XT
Prescaler
2
f
X
f
X
22
Standby
Wait
CPU clock
controller
controller
(fCPU
)
STOP
MCC PCC1
CLS CSS0
Subclock control
register
(CSS)
Processor clock
control register
(PCC)
Internal bus
32
Preliminary Product Information
µPD789166Y, 789167Y, 789176Y, 789177Y
5.2.3 Clock generator control registers
The clock generator is controlled using the following registers.
•
•
•
Processor clock control register (PCC)
Suboscillation mode register (SCKM)
Subclock control register (CSS)
(1) Processor clock control register (PCC)
The PCC selects a CPU clock and specifies a corresponding frequency division ratio.
It is manipulated using a 1-bit or 8-bit memory manipulation instruction.
A RESET input loads 02H into the PCC.
Figure 5-8. Format of Processor Clock Control Register
Symbol
PCC
7
6
0
5
0
4
0
3
0
2
0
1
0
0
Address When reset
FFFBH 02H
R/W
R/W
MCC
PCC1
MCC
Control of main system clock oscillator operation
0
1
Operation enabled
Operation disabled
CSS0
PCC1
CPU clock (fCPU) selectionNote
0
0
1
1
0
1
0
1
f
f
f
X
(0.2µs)
X
/22 (0.8µs)
XT/2 (61 s)
µ
Note A CPU clock is selected by a combination of the PCC1 flag in the processor clock control register (PCC)
and the CSS0 flag in the subclock control register (CSS). (See (3) in Section 5.2.3.)
Cautions 1. Bit 0 and bits 2 to 6 must be fixed to 0.
2. MCC can be set only when the subsystem clock is selected as the CPU clock.
3. Never set MCC when an external clock is applied. This is because the X2 pin is pulled up to
VDD.
Remarks 1. fX : Main system clock oscillation frequency
2. fXT: Subsystem clock oscillation frequency
3. The parenthesized values apply to operation with fX = 5.0 MHz or fXT = 32.768 kHz.
4. Minimum instruction execution time: 2 fCPU
• fCPU = 0.2 µs : 0.4 µs
• fCPU = 0.8 µs : 1.6 µs
• fCPU = 61 µs : 122 µs
Preliminary Product Information
33
µPD789166Y, 789167Y, 789176Y, 789177Y
(2) Suboscillation mode register (SCKM)
The SCKM selects a feedback resistor for the subsystem clock, and controls the oscillation of the clock.
It is manipulated using a 1-bit or 8-bit memory manipulation instruction.
A RESET input clears SCKM to 00H.
Figure 5-9. Format of Suboscillation Mode Register
Symbol
SCKM
7
0
6
0
5
0
4
0
3
0
2
0
1
0
Address When reset
FFF0H 00H
R/W
R/W
FRC
SCC
FRC
Feedback resistor selection
0
1
Internal feedback resistor used
Internal feedback resistor not used
SCC
Control of subsystem clock oscillator operation
0
1
Operation enabled
Operation disabled
Caution Bits 2 to 7 must be fixed to 0.
34
Preliminary Product Information
µPD789166Y, 789167Y, 789176Y, 789177Y
(3) Subclock control register (CSS)
The CSS specifies whether the main system or subsystem clock oscillator is to be selected. It also specifies
how the CPU clock operates.
It is manipulated using a 1-bit or 8-bit memory manipulation instruction.
A RESET input clears CSS to 00H.
Figure 5-10. Format of Subclock Control Register
Symbol
CSS
7
0
6
0
5
4
3
0
2
0
1
0
0
0
Address When reset
FFF2H 00H
R/W
CLS
CSS0
R/WNote
CLS
0
CPU clock operation status
Operation based on the output of the divided main system clock
Operation based on the subsystem clock
1
CSS0
Selection of the main system or subsystem clock oscillator
Divided output from the main system clock oscillator
Output form the subsystem clock oscillator
0
1
Note Bit 5 is read-only.
Caution Bits 0 to 3, 6, and 7 must be fixed to 0.
Preliminary Product Information
35
µPD789166Y, 789167Y, 789176Y, 789177Y
5.3 16-Bit Timer Counter
5.3.1 16-Bit timer counter functions
16-bit timer counter 90 (TM90) has the following functions.
(1) Timer interrupt
An interrupt is generated if the TM90 count matches a comparison value.
(2) Timer output
The timer output can be controlled if the count matches a comparison value.
(3) Count capture
The count in TM90 is captured into the capture register in synchronization with a capture trigger.
(4) Buzzer output
The buzzer output can be controlled if the count matches the comparison value.
5.3.2 16-bit timer counter configuration
16-bit timer counter 90 (TM90) consists of the following hardware.
Table 5-5. 16-Bit Timer Counter 90 Configuration
Item
Timer register
Register
Configuration
16 bits × 1 (TM90)
Compare register 90 : 16 bits × 1 (CR90)
Capture register 90 : 16 bits × 1 (TCP90)
Timer output
1 (TO90)
Control register
16-bit timer mode control register 90 (TMC90)
Buzzer output control register 90 (BZC90)
Port mode register 2 (PM2)
36
Preliminary Product Information
Figure 5-11. Block Diagram of 16-Bit Timer Counter 90
Internal bus
16-bit timer mode control
register 90 (TMC90)
P32
output latch
PM32
TOF90CPT901CPT900TOC90 TCL901TCL900 TOE90
TO90/INTP2/
P32
16-bit compare register
(CR90)
Flip-
flop
TOD90
µ
µ
fX/22
fX/26
fX/27
Match
INTTM90
fXT
TO82 outputNote
OVF
BZO90/INTP3/
TO82/P33
16-bit timer register
(TM90)
3
CTP90/INTP0/
TI81/P30
P33
output latch
PM33
BCS902 BCS901 BCS900BZOE90
Buzzer output control
register (BZC90)
16-bit capture
register (TCP90)
16-bit counter
read buffer
Edge detection
circuit
Internal bus
Note See Figure 5-17.
µPD789166Y, 789167Y, 789176Y, 789177Y
(1) 16-bit compare register 90 (CR90)
A value specified in CR90 is compared with the count in 16-bit timer register 90 (TM90). If they match, an
interrupt request (INTTM90) is issued.
CR90 is manipulated using an 8-bit or 16-bit memory manipulation instruction. Any value from 0000H to FFFFH
can be set.
A RESET input loads FFFFH into CR90.
Cautions 1. CR90 is designed to be manipulated using a 16-bit memory manipulation instruction. It can
also be manipulated using 8-bit memory manipulation instructions, however. When an 8-bit
memory manipulation instruction is used to set CR90, it must be in a direct addressing
access mode.
2. To re-set CR90 during count operation, it is necessary to disable interrupts in advance, using
an interrupt mask flag register 1 (MK1). It is also necessary to disable inversion of the timer
output data, using 16-bit timer mode control register 90 (TMC90).
(2) 16-bit timer register 90 (TM90)
TM90 is used to count the number of pulses.
The contents of TM90 are read using an 8-bit or 16-bit memory manipulation instruction.
A RESET input clears TM90 to 0000H.
Cautions 1. The count becomes undefined when STOP mode is deselected, because the count
operation is performed before oscillation settles.
2. TM90 is designed to be manipulated using a 16-bit memory manipulation instruction. It
can also be manipulated using 8-bit memory manipulation instructions, however. When
an 8-bit memory instruction is used to manipulate TM90, it must be in a direct addressing
access mode.
3. When an 8-bit memory manipulation instruction is used to manipulate TM90, the lower and
upper bytes must be read as a pair, in this order.
(3) 16-bit capture register 90 (TCP90)
TCP90 captures the contents of 16-bit timer 90 (TM90).
It is manipulated using an 8-bit or 16-bit memory manipulation instruction.
A RESET input makes TCP90 undefined.
Caution TCP90 is designed to be manipulated using a 16-bit memory manipulation instruction. It can
also be manipulated using 8-bit memory manipulation instructions, however. When an 8-bit
memory manipulation instruction is used to manipulate TCP90, it must be in a direct
addressing access mode.
(4) 16-bit counter read buffer 90
This buffer is used to latch and hold the count for 16-bit timer 90 (TM90).
38
Preliminary Product Information
µPD789166Y, 789167Y, 789176Y, 789177Y
5.3.3 16-bit timer counter control registers
The following three types of registers are used to control 16-bit timer counter 90 (TM90).
•
•
•
16-bit timer mode control register 90 (TMC90)
Buzzer output control register 90 (BZC90)
Port mode register 2 (PM2)
(1) 16-bit timer mode control register 90 (TMC90)
TMC90 controls the count clock and capture edge settings.
It is manipulated using a 1-bit or 8-bit memory manipulation instruction.
A RESET input clears TMC90 to 00H.
Preliminary Product Information
39
µPD789166Y, 789167Y, 789176Y, 789177Y
Figure 5-12. Format of 16-Bit Timer Mode Control Register 90
Symbol
7
6
5
4
3
2
1
0
Address When reset
FF48H 00H
R/W
TMC90 TOD90 TOF90 CPT901CPT900 TOC90 TCL901 TCL900 TOE90
R/WNote
TOD90
Timer output data
Overflow flag control
Capture edge selection
0
1
Timer output of 0
Timer output of 1
TOF90
0
1
Reset or cleared by software
Set when the 16-bit timer overflows
CPT901CPT900
0
0
1
1
0
1
0
1
Capture operation disabled
Captured at the rising edge at the CPT90 pin
Captured at the falling edge at the CPT90 pin
Captured at both the rising and falling edges at the CPT90 pin
TOC90
Timer output data inversion control
0
1
Inversion disabled
Inversion enabled
TCL901 TCL900
16-bit timer counter 90 count clock selection
/22 (1.25 MHz)
/26 (78.125 kHz)
/27 (39.063 kHz)
0
0
1
1
0
1
0
1
f
f
f
f
X
X
X
XT (32.768 kHz)
TOE90
16-bit timer counter 90 output control
0
1
Output disabled (port mode)
Output enabled
Note Bit 7 is read-only.
Remarks 1. fX : Main system clock oscillation frequency
2. fXT : Subsystem clock oscillation frequency
3. The parenthesized values apply to operation at fX = 5.0 MHz or fXT = 32.768 kHz.
40
Preliminary Product Information
µPD789166Y, 789167Y, 789176Y, 789177Y
(2) Buzzer output control register (BZC90)
Based on the count clock (fcl) selected with the count clock selection bits (TCL901 and TCL900), this register
sets a buzzer frequency and controls square wave output.
BZC90 is manipulated using a 1-bit or 8-bit memory manipulation instruction.
A RESET input clears BZC90 to 00H.
Figure 5-13. Format of Buzzer Output Control Register
Address When reset R/W
FF49H 00H R/W
Symbol
BZC90
7
0
6
0
5
0
4
0
3
0
2
1
BCS902 BCS901 BCS900 BZOE90
BZOE90
0
Buzzer port output control
Disables buzzer port output.
Enables buzzer port output.Note
1
Buzzer frequency
BCS902 BCS901 BCS900
fcl = f
X
/22
fcl = f
X
/26
fcl = f
X
/27
fcl = fXT
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
fcl/24 (78.125 kHz) fcl/24 (4,883 Hz)
fcl/25 (39.063 kHz) fcl/25 (2,441 Hz)
fcl/24 (2,441 Hz)
fcl/25 (1,221 Hz)
fcl/28 (153 Hz)
fcl/29 (76 Hz)
fcl/210 (38 Hz)
fcl/211 (19 Hz)
fcl/212 (10 Hz)
fcl/213 (5 Hz)
fcl/24 (2,048 Hz)
fcl/25 (1,024 Hz)
fcl/28 (128 Hz)
fcl/29 (64 Hz)
fcl/210 (32 Hz)
fcl/211 (16 Hz)
fcl/212 (8 Hz)
fcl/28 (4,883 Hz)
fcl/29 (2,441 Hz)
fcl/210 (1,221 Hz)
fcl/211 (610 Hz)
fcl/212 (305 Hz)
fcl/213 (153 Hz)
fcl/28 (305 Hz)
fcl/29 (153 Hz)
fcl/210 (76 Hz)
fcl/211 (38 Hz)
fcl/212 (19 Hz)
fcl/213 (10 Hz)
fcl/213 (4 Hz)
Note When setting BZOE90 to 1, TOE82 must be fixed to 0. (See Figure 5-20.)
Cautions 1. Bits 4 to 7 must be fixed to 0.
2. If the subclock is selected as the count clock (TCL901 = 1, TCL900 = 1: see Figure 5-12), the
subclock is not synchronized when buzzer port output is enabled. In this case, the capture
function and TM90 register read function are disabled. In addition, the count value of the
TM90 register is undefined.
Remarks 1. fX : Main system clock oscillation frequency
2. fXT: Subsystem clock oscillation frequency
3. The parenthesized values apply to operation at fX = 5.0 MHz or fXT = 32.768 kHz.
Preliminary Product Information
41
µPD789166Y, 789167Y, 789176Y, 789177Y
(3) Port mode register 3 (PM3)
PM3 is used to specify port 3 input/output on a bit-by-bit basis.
When the P32/INTP2/TO90 pin is used for timer output, set 0 in the output latch of PM32 and P32. When the
P33/INTP3/TO82/BZO90 pin is used for buzzer outputNote, set 0 in the output latch of the PM33 and P33.
PM3 is manipulated using a 1-bit or 8-bit memory manipulation instruction.
A RESET input loads FFH into PM3.
Note Never output the TO82 and BZO90 signals at the same time.
Figure 5-14. Format of Port Mode Register 3
Address When reset R/W
FF23H FFH R/W
Symbol
PM3
7
1
6
1
5
1
4
1
3
0
2
1
PM33
PM32
PM31
PM30
P3n pin I/O mode (n = 2 or 3)
PM3n
0
1
Output mode (output buffer ON)
Input mode (output buffer OFF)
42
Preliminary Product Information
µPD789166Y, 789167Y, 789176Y, 789177Y
5.4 8-Bit Timer/Event Counter
5.4.1 8-bit timer/event counter functions
Devices of the µPD789166Y, µPD789167Y, µPD789176Y, and µPD789177Y have two timer/event counters
(TM80 and TM81) and one timer counter (TM82). Readers who are seeking a description of TM82 should read the
term “timer/event counter” as “timer counter.”
The 8-bit timer/event counters (TM80, TM81, and TM82) have the following functions.
(1) 8-bit interval timer (TM80, TM81, and TM82)
This timer causes interrupts to be issued at specified intervals.
(2) External event counter (TM80 and TM81)
This counter is used to count the number of pulses input from an external source.
(3) Square wave output (TM80, TM81, and TM82)
A square wave of any frequency can be output.
(4) PWM output (TM80, TM81, and TM82)
PWM output with an 8-bit resolution is supported.
Table 5-6. 8-Bit Timer/Event Counter Types and Functions
TM80
TM81
TM82
Type
Interval timer
One channel
One channel
One channel
External event counter
Timer output
Ο
Ο
Ο
Ο
Ο
Ο
Ο
Ο
Ο
Ο
×
Ο
Ο
Ο
Ο
Function
Square wave output
PWM output
Interrupt request
5.4.2 8-bit timer/event counter configuration
The 8-bit timer/event counter consists of the following hardware.
Table 5-7. 8-Bit Timer/Event Counter Configuration
Item
Timer register
Register
Configuration
8 bits × 3 (TM80, TM81, TM82)
Compare registers: 8 bits × 3 (CR80, CR81, CR82)
Timer output
Control register
3 (TO80, TO81, TO82)
8-bit timer mode control registers 80, 81, 82 (TMC80, TMC81, TMC82)
Port mode registers 2, 3 (PM2, PM3)
Preliminary Product Information
43
µPD789166Y, 789167Y, 789176Y, 789177Y
Figure 5-15. Block Diagram of 8-Bit Timer/Event Counter 80
Internal bus
8-bit compare
register 80 (CR80)
Match
INTTM80
TI80/P25/
SS20
CLEAR
8-bit timer counter
80 (TM80)
f
X
R
INV Q
f
/23
X
OVF
Q
S
TO80/P26
P26
output
latch
PM26
TCE80 PWME80TCL801TCL800TOE80
8-bit timer mode control register 80 (TMC80)
Internal bus
Figure 5-16. Block Diagram of 8-Bit Timer/Event Counter 81
Internal bus
8-bit compare
register 81 (CR81)
Match
INTTM81
TI81/CPT90/
P30/INTP0
CLEAR
8-bit timer counter
f
X
/24
/28
R
INV Q
81 (TM81)
f
X
OVF
Q
TO81/P31/
INTP1
S
P31
output
latch
PM31
TCE81 PWME81TCL811TCL810TOE81
8-bit timer mode control register 81 (TMC81)
Internal bus
44
Preliminary Product Information
µPD789166Y, 789167Y, 789176Y, 789177Y
Figure 5-17. Block Diagram of 8-Bit Timer Counter 82
Internal bus
8-bit compare
register 82 (CR82)
Match
INTTM82
BZO90
f
f
X
X
/25
/27
CLEAR
outputNote
8-bit timer counter
82 (TM82)
R
INV Q
f
XT
OVF
Q
TO82/BZO90/
P33/INTP3
S
P33
output
PM33
TCE82 PWME82TCL821TCL820TOE82
latch
8-bit timer mode control register 82 (TMC82)
Internal bus
Note See Figure 5-11.
(1) 8-bit compare register 8n (CR8n)
A value specified in CR8n is compared with the count in 8-bit timer register 8n (TM8n). If they match, an interrupt
request (INTTM8n) is issued.
CR8n is manipulated using an 8-bit memory manipulation instruction. Any value from 00H to FFH can be set.
A RESET input makes CR8n undefined.
Remark n = 0 to 2
(2) 8-bit timer register 8n (TM8n)
TM8n is used to count the number of pulses.
Its contents are read using an 8-bit memory manipulation instruction.
A RESET input clears TM8n to 00H.
Remark n = 0 to 2
Preliminary Product Information
45
µPD789166Y, 789167Y, 789176Y, 789177Y
5.4.3 8-bit timer/event counter control registers
The following two types of registers are used to control the 8-bit timer/event counter.
•
•
8-bit timer mode control registers 80, 81, and 82 (TMC80, TMC81, and TMC82)
Port mode registers 2 and 3 (PM2 and PM3)
(1) 8-bit timer mode control register 80 (TMC80)
TMC80 determines whether to enable or disable 8-bit timer register 80 (TM80) and specifies the count clock for
TM80. It also controls the operation of the output control circuit of 8-bit timer counter 80.
TMC80 is manipulated using a 1-bit or 8-bit memory manipulation instruction.
A RESET input clears TMC80 to 00H.
Figure 5-18. Format of 8-Bit Timer Mode Control Register 80
Symbol
7
6
5
0
4
0
3
0
2
1
0
Address When reset
FF53H 00H
R/W
R/W
TMC80 TCE80PWME80
TCL801TCL800TOE80
TCE80
8-bit timer register 80 operation control
0
1
Operation disabled (TM80 is cleared to 0.)
Operation enabled
PWME80
PWM output selection
0
1
Counter operation
PWM output
TCL801TCL800
8-bit timer register 80 count clock selection
0
0
1
1
0
1
0
1
f
f
X
X
(5.0 MHz)
/23 (625 kHz)
Rising edge of TI80
Falling edge of TI80
TOE80
8-bit timer counter 80 output control
0
1
Output disabled (port mode)
Output enabled
Cautions 1. Always stop the timer before setting TMC80.
2. For PWM mode operation, the interrupt mask flag (TMMK80) must be set.
Remarks 1. fX: Main system clock oscillation frequency
2. The parenthesized values apply to operation at fX = 5.0 MHz.
46
Preliminary Product Information
µPD789166Y, 789167Y, 789176Y, 789177Y
(2) 8-bit timer mode control register 81 (TMC81)
TMC81 determines whether to enable or disable 8-bit timer register 81 (TM81) and specifies the count clock for
TM81. It also controls the operation of the output control circuit of 8-bit timer counter 81.
TMC81 is manipulated using a 1-bit or 8-bit memory manipulation instruction.
A RESET input clears TMC81 to 00H.
Figure 5-19. Format of 8-Bit Timer Mode Control Register 81
Symbol
7
6
5
0
4
0
3
0
2
1
0
Address When reset
FF57H 00H
R/W
R/W
TMC81 TCE81PWME81
TCL811TCL810TOE81
TCE81
8-bit timer register 81 operation control
0
1
Operation disabled (TM81 is cleared to 0.)
Operation enabled
PWME81
PWM output selection
0
1
Counter operation
PWM output
TCL811TCL810
8-bit timer register 81 count clock selection
/24 (312.5 kHz)
/28 (19.5 kHz)
0
0
1
1
0
1
0
1
f
f
X
X
Rising edge of TI81
Falling edge of TI81
TOE81
8-bit timer counter 81 output control
0
1
Output disabled (port mode)
Output enabled
Cautions 1. Always stop the timer before setting TMC81.
2. For PWM mode operation, the interrupt mask flag (TMMK81) must be set.
Remarks 1. fX: Main system clock oscillation frequency
2. The parenthesized values apply to operation at fX = 5.0 MHz.
Preliminary Product Information
47
µPD789166Y, 789167Y, 789176Y, 789177Y
(3) 8-bit timer mode control register 82 (TMC82)
TMC82 determines whether to enable or disable 8-bit timer register 82 (TM82) and specifies the count clock for
TM82. It also controls the operation of the output control circuit of 8-bit timer counter 82.
TMC82 is manipulated using a 1-bit or 8-bit memory manipulation instruction.
A RESET input clears TMC82 to 00H.
Figure 5-20. Format of 8-Bit Timer Mode Control Register 82
Symbol
7
6
5
0
4
0
3
0
2
1
0
Address When reset
FF5BH 00H
R/W
R/W
TMC82 TCE82PWME82
TCL821TCL820TOE82
TCE82
8-bit timer register 82 operation control
0
1
Operation disabled (TM82 is cleared to 0.)
Operation enabled
PWME82
PWM output selection
0
1
Counter operation
PWM output
TCL821TCL820
8-bit timer register 82 count clock selection
/25 (156.25 kHz)
/27 (39.1 kHz)
0
0
1
1
0
1
0
1
f
f
f
X
X
XT (32.768 kHz)
Not to be set
TOE82
8-bit timer counter 82 output control
0
1
Output disabled (port mode)
Output enabledNote
Note When TOE82 is set to 1, BZOE90 must be set to 0 (see Figure 5-13).
Cautions 1. Always stop the timer before setting TMC82.
2. For PWM mode operation, the interrupt mask flag (TMMK82) must be set.
Remarks 1. fX : Main system clock oscillation frequency
2. fXT: Subsystem clock oscillation frequency
3. The parenthesized values apply to operation at fX = 5.0 MHz or fXT = 32.768 kHz.
48
Preliminary Product Information
µPD789166Y, 789167Y, 789176Y, 789177Y
(4) Port mode registers 2 and 3 (PM2 and PM3)
PM2 and PM3 specify whether each bit of port 2 and port 3 is used for input or output.
To use the P26/TO80 pin for timer output, the PM26 and P26 output latches must be reset to 0.
To use the P31/TO81/INTP1 pin for timer output, the PM31 and P31 output latches must be reset to 0.
To use the P33/INTP3/TO82/BZO90 pin for timer output, the PM33 and P33 output latches must be reset to 0.
PM2 and PM3 are manipulated using a 1-bit or 8-bit memory manipulation instruction.
A RESET input loads FFH into PM2 and PM3.
Figure 5-21. Format of Port Mode Register 2
Symbol
PM2
7
1
6
5
4
3
2
1
0
Address When reset
FF22H FFH
R/W
R/W
PM26
PM25
PM24
PM23
PM22
PM21
PM20
PM26
P26 pin input/output mode selection
0
1
Output mode (output buffer ON)
Input mode (output buffer OFF)
Figure 5-22. Format of Port Mode Register 3
Symbol
PM3
7
1
6
1
5
1
4
1
3
2
1
0
Address When reset
FF23H FFH
R/W
R/W
PM33
PM32
PM31
PM30
PM31
P31 pin input/output mode selection
0
1
Output mode (output buffer ON)
Input mode (output buffer OFF)
PM33
P33 pin input/output mode selection
0
1
Output mode (output buffer ON)
Input mode (output buffer OFF)
Preliminary Product Information
49
µPD789166Y, 789167Y, 789176Y, 789177Y
5.5 Clock Timer
5.5.1 Clock timer functions
The clock timer has the following functions.
•
•
Clock timer
Interval timer
The clock and interval timers can be used at the same time.
Figure 5-23 is a block diagram of the clock timer.
Figure 5-23. Block Diagram of Clock Timer
Clear
fX/27
fXT
5-bit counter
INTWT
INTWTI
9-bit prescaler
fW
fW
fW
fW
fW
fW
fW
Clear
24 25 26 27 28
29
WTM7 WTM6 WTM5 WTM4 WTM1 WTM0
Clock timer mode
control register (WTM)
Internal bus
50
Preliminary Product Information
µPD789166Y, 789167Y, 789176Y, 789177Y
(1) Clock timer
The 4.19-MHz main system clock or 32.768-kHz subsystem clock is used to issue an interrupt request
(INTWT) at 0.5-second intervals.
Caution When the main system clock is operating at 5.0 MHz, it cannot be used to generate a
0.5-second interval. In this case, the subsystem clock, which operates at 32.768 kHz,
should be used instead.
(2) Interval timer
The interval timer is used to generate an interrupt request (INTWTI) at specified intervals.
Table 5-8. Interval Generated Using the Interval Timer
Interval
Operation at fX = 5.0 MHz
409.6 µs
Operation at fX = 4.19 MHz
Operation at fXT = 32.768 kHz
24 × 1/fW
25 × 1/fW
26 × 1/fW
27 × 1/fW
28 × 1/fW
29 × 1/fW
489 µs
488 µs
819.2 µs
978 µs
977 µs
1.64 ms
1.96 ms
3.91 ms
7.82 ms
15.6 ms
1.95 ms
3.91 ms
7.81 ms
15.6 ms
3.28 ms
6.55 ms
13.1 ms
Remark fW : Clock timer clock frequency (fX/27 or fXT)
fX : Main system clock oscillation frequency
fXT : Subsystem clock oscillation frequency
5.5.2 Clock timer configuration
The clock timer consists of the following hardware.
Table 5-9. Clock Timer Configuration
Item
Counter
Configuration
5 bits
Prescaler
9 bits
Control register
Clock timer mode control register (WTM)
Preliminary Product Information
51
µPD789166Y, 789167Y, 789176Y, 789177Y
5.5.3 Clock timer control register
The clock timer mode control register (WTM) is used to control the clock timer.
•
Clock timer mode control register (WTM)
The WTM selects a count clock for the clock timer and specifies whether to enable clocking of the timer. It
also specifies the prescaler interval and how the 5-bit counter is controlled.
The WTM is manipulated using a 1-bit or 8-bit memory manipulation instruction.
A RESET input clears the WTM to 00H.
Figure 5-24. Format of Clock Timer Mode Control Register
Symbol
WTM
7
6
5
4
3
0
2
0
1
0
Address When reset
FF4AH 00H
R/W
R/W
WTM7
WTM6
WTM5
WTM4
WTM1
WTM0
WTM7
Clock timer count clock selection
0
1
f
f
X
/27
(39.1 kHz)
(32.768 kHz)
XT
WTM6
WTM5
WTM4
Prescaler interval selection
24/f
25/f
26/f
27/f
28/f
29/f
W
W
W
W
W
W
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
Other settings
Not to be set
WTM1
5-bit counter operation control
0
1
Cleared after stop
Started
WTM0
Clock timer operation
0
1
Operation disabled (both prescaler and timer cleared)
Operation enabled
Remarks 1. fW : Clock timer clock frequency (fX/27 or fXT)
2. fX : Main system clock oscillation frequency
3. fXT: Subsystem clock oscillation frequency
4. The parenthesized values apply to operation at fX = 5.0 MHz or fXT = 32.768 kHz.
52
Preliminary Product Information
µPD789166Y, 789167Y, 789176Y, 789177Y
5.6 Watchdog Timer
5.6.1 Watchdog timer functions
The watchdog timer has the following functions.
(1) Watchdog timer
The watchdog timer is used to detect unintended program loops. If an unintended program loop is detected, a
nonmaskable interrupt or RESET signal is generated.
(2) Interval timer
The interval timer is used to generate interrupts at specified intervals.
5.6.2 Watchdog timer configuration
The watchdog timer consists of the following hardware.
Table 5-10. Watchdog Timer Configuration
Item
Configuration
Control register
Timer clock selection register 2 (TCL2)
Watchdog timer mode register (WDTM)
Preliminary Product Information
53
µPD789166Y, 789167Y, 789176Y, 789177Y
Figure 5-25. Block Diagram of Watchdog Timer
Internal bus
f
X
TMMK4
Prescaler
24
f
X
f
X
f
X
RUN
Clear
7-bit counter
26
28
210
INTWDT
maskable
interrupt request
TMIF4
Control
circuit
RESET
INTWDT
nonmaskable
interrupt request
3
TCL22 TCL21 TCL20
WDTM4 WDTM3
Timer clock selection register 2
(TCL2)
Watchdog timer mode register
(WDTM)
Internal bus
54
Preliminary Product Information
µPD789166Y, 789167Y, 789176Y, 789177Y
5.6.3 Watchdog timer control registers
The following two types of registers are used to control the watchdog timer.
•
•
Timer clock selection register 2 (TCL2)
Watchdog timer mode register (WDTM)
(1) Timer clock selection register 2 (TCL2)
TCL2 specifies the count clock for the watchdog timer.
TCL2 is manipulated using an 8-bit memory manipulation instruction.
A RESET input clears TCL2 to 00H.
Figure 5-26. Format of Timer Clock Selection Register 2
Symbol
TCL2
7
0
6
0
5
0
4
0
3
0
2
1
0
Address When reset
R/W
R/W
TCL22 TCL21 TCL20
FF42H
00H
TCL22 TCL21 TCL20
Watchdog timer count clock selection
Interval time
/24 (312.5 kHz)
/26 (78.1 kHz)
/28 (19.5 kHz)
/210 (4.88 kHz)
211/f
X
X
X
X
(410 µs)
0
0
1
1
0
1
0
1
0
0
0
0
f
f
f
f
X
X
X
X
213/f
215/f
217/f
(1.64 ms)
(6.55 ms)
(26.2 ms)
Other settings
Not to be set
Remarks 1. fX: Main system clock oscillation frequency
2. The parenthesized values apply to operation at fX = 5.0 MHz.
Preliminary Product Information
55
µPD789166Y, 789167Y, 789176Y, 789177Y
(2) Watchdog timer mode register (WDTM)
The WDTM specifies the watchdog timer operation mode and whether to enable or disable counting.
The WDTM is manipulated using a 1-bit or 8-bit memory manipulation instruction.
A RESET input clears the WDTM to 00H.
Figure 5-27. Format of Watchdog Timer Mode Register
Symbol
7
6
0
5
0
4
3
2
0
1
0
0
0
Address When reset
FFF9H 00H
R/W
R/W
WDTM RUN
WDTM4 WDTM3
RUN
Watchdog timer operation selectionNote 1
0
1
Stops counting.
Clears the counter and causes it to start.
WDTM4 WDTM3
Watchdog timer operation mode selectionNote 2
0
0
1
1
0
1
0
1
Operation disabled
Internal timer mode (When an overflow occurs, a maskable interrupt is issued.)Note 3
Watchdog timer mode 1 (When an overflow occurs, a nonmaskable interrupt is issued.)
Watchdog timer mode 2 (When an overflow occurs, a reset operation is started.)
Notes 1. Once the RUN bit has been set (1), it is impossible to zero-clear it by software. So, once counting
begins, it cannot be stopped by any means other than a RESET input.
2. Once WDTM3 and WDTM4 have been set (1), it is impossible to zero-clear them by software.
3. The interval timer starts operating when the RUN bit is set to 1.
Cautions 1. If the RUN bit is set to 1, and the watchdog timer is cleared, the actual overflow time becomes
0.8% (maximum) less than the time specified in timer clock selection register 2.
2. To use watchdog timer mode 1 or 2, ensure that the interrupt request flag (TMIF4) is set to 0,
before setting WDTM4 to 1. If TMIF4 is set to 1, selecting mode 1 or 2 causes a nonmaskable
interrupt to be issued at the instant rewriting ends.
56
Preliminary Product Information
µPD789166Y, 789167Y, 789176Y, 789177Y
5.7 A/D Converter
A/D converters support different conversion resolutions, depending on the microcontroller model, as shown below:
•
•
A/D converters with an 8-bit resolution: for µPD789166Y and µPD789167Y
A/D converters with a 10-bit resolution: for µPD789176Y and µPD789177Y
5.7.1 A/D converter functions
The A/D converter converts input analog voltages to digital signals with an 8-bit or 10-bit resolution. It can control
up to eight analog input channels (ANI0 to ANI7).
A/D conversion can be started only by software.
One of analog inputs ANI0 to ANI7 is selected for A/D conversion. A/D conversion is performed repeatedly, with
an interrupt request (INTAD0) being issued each time an A/D conversion is completed.
Caution In standby mode, the A/D converter operation is disabled.
5.7.2 A/D converter configuration
The A/D converter consists of the following hardware.
Table 5-11. A/D Converter Configuration
Item
Analog input
Register
Configuration
8 channels (ANI0 to ANI7)
Successive approximation register (SAR)
A/D conversion result register 0 (ADCR0)
Control register
A/D converter mode register 0 (ADM0)
A/D input selection register 0 (ADS0)
Preliminary Product Information
57
µPD789166Y, 789167Y, 789176Y, 789177Y
Figure 5-28. Block Diagram of A/D Converter
ANI0
ANI1
ANI2
ANI3
ANI4
ANI5
ANI6
ANI7
AVDD
Sample-and-hold circuit
AVREF
Voltage comparator
AVSS
Successive
approximation
register (SAR)
AVSS
Control
circuit
INTAD
A/D conversion result
register 0 (ADCR0)
3
ADS02ADS01ADS00
ADCS0
0
FR02 FR01 FR00
0
0
0
A/D conveter mode register 0
(ADM0)
A/D input selection register 0
(ADS0)
Internal bus
(1) Successive approximation register (SAR)
The SAR receives the result of comparing an analog input voltage and a voltage at a voltage tap (comparison
voltage), received from the serial resistor string, starting from the most significant bit (MSB).
Upon receiving all the bits, down to the least significant bit (LSB), that is, upon the completion of A/D
conversion, the SAR sends its contents to the A/D conversion result register.
(2) A/D conversion result register 0 (ADCR0)
The ADCR holds the result of A/D conversion. Each time A/D conversion ends, the conversion result received
from the successive approximation register is loaded into the ADCR0.
For the µPD789166Y and µPD789167Y (featuring 8-bit A/D converters), the value of ADCR0 is read using an
8-bit memory manipulation instruction.
For the µPD789176Y and µPD789177Y (featuring 10-bit A/D converters), the value of ADCR0 is read using a
16-bit memory manipulation instruction.
A RESET input makes ADCR0 undefined.
Caution When 8-bit A/D converters are used (for the µPD789166Y and µPD789167Y), this register
can be accessed only in 8-bit mode. In this case, the address is assumed to be FF15H.
When 10-bit A/D converters are used (for the µPD789176Y and µPD789177Y), this register
can be accessed only in 16-bit mode.
When the µPD78F9177Y is used as flash memory for the µPD789166Y or µPD789167Y,
8-bit access is allowed. However, only those object files generated by an assembler used
with the µPD789166Y or µPD789167Y are supported for this access.
58
Preliminary Product Information
µPD789166Y, 789167Y, 789176Y, 789177Y
(3) Sample-and-hold circuit
The sample-and-hold circuit samples consecutive analog inputs from the input circuit, one by one, and sends
them to the voltage comparator. The sampled analog input voltage is held during A/D conversion.
(4) Voltage comparator
The voltage comparator compares an analog input with the voltage output by the serial resistor string.
(5) Serial resistor string
The serial resistor string is configured between AVREF and AVSS. It generates the reference voltages against
which analog inputs are compared.
(6) ANI0 to ANI7 pins
Pins ANI0 to ANI7 are 8-channel analog input pins for the A/D converter. They are used to receive the analog
signals to be subject to A/D conversion.
Caution Do not supply pins ANI0 to ANI7 with voltages that fall outside the rated range. If a
voltage greater than AVREF or less than AVSS (even if within the absolute maximum rating)
is supplied to any of these pins, the conversion value for the corresponding channel will
be undefined. Furthermore, the conversion values for the other channels may also be
affected.
(7) AVREF pin
The AVREF pin is a reference voltage pin for the A/D converter.
Signals received at pins ANI0 to ANI7 are converted to digital signals while referencing the voltage across the
AVREF and AVSS pins.
(8) AVSS pin
The AVSS pin is a ground potential pin for the A/D converter. This pin must be held at the same potential as
the VSS pin, even while the A/D converter is not being used.
(9) AVDD pin
The AVDD pin is an analog power supply pin for the A/D converter. This pin must be held at the same
potential as the VDD pin, even while the A/D converter is not being used.
Preliminary Product Information
59
µPD789166Y, 789167Y, 789176Y, 789177Y
5.7.3 A/D converter control registers
The following two types of registers are used to control the A/D converter.
•
•
A/D converter mode register 0 (ADM0)
A/D input selection register 0 (ADS0)
(1) A/D converter mode register 0 (ADM0)
ADM0 specifies the conversion time for analog inputs. It also specifies whether to enable conversion.
ADM0 is manipulated using a 1-bit or 8-bit memory manipulation instruction.
A RESET input clears ADM0 to 00H.
Figure 5-29. Format of A/D Converter Mode Register 0
Symbol
ADM0
7
6
0
5
4
3
2
0
1
0
0
0
Address When reset
FF80H 00H
R/W
R/W
ADCS0
FR02
FR01
FR00
ADCS0
A/D conversion control
0
1
Conversion disabled
Conversion enabled
FR02
FR01
FR00
A/D conversion time selectionNote 1
0
0
0
1
1
1
0
0
1
0
0
1
0
1
0
0
1
0
144/fx (28.8 µs)
120/fx (24 µs)
96/fx
72/fx
60/fx
48/fx
(19.2 µs)
(14.4 µs)
(Not to be setNote 2
(Not to be setNote 2
)
)
Other settings
Not to be set
Notes 1. The specifications of FR02, FR01, and FR00 must be such that the A/D conversion time is at least
14 µs.
2. These bit combinations must not be used, as the A/D conversion time will fall below 14 µs.
Cautions 1. The result of conversion performed immediately after bit 7 (ADCS0) is set is undefined.
2. Bits 0 to 2 and bit 6 must be fixed to 0.
Remarks 1. fX: Main system clock oscillation frequency
2. The parenthesized values apply to operation at fX = 5.0 MHz.
60
Preliminary Product Information
µPD789166Y, 789167Y, 789176Y, 789177Y
(2) A/D input selection register 0 (ADS0)
ADS0 specifies the port used to input the analog voltages to be converted to a digital signal. The ADS0 is
manipulated using a 1-bit or 8-bit memory manipulation instruction.
A RESET input clears ADS0 to 00H.
Figure 5-30. Format of A/D Input Selection Register 0
Symbol
ADS0
7
0
6
0
5
0
4
0
3
0
2
1
0
Address When reset
FF84H 00H
R/W
R/W
ADS02
ADS01
ADS00
Analog input channel specification
ADS02
ADS01
ADS00
ANI0
ANI1
ANI2
ANI3
ANI4
ANI5
ANI6
ANI7
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Caution Bits 3 to 7 must be fixed to 0.
Preliminary Product Information
61
µPD789166Y, 789167Y, 789176Y, 789177Y
5.8 Serial Interface
5.8.1 Serial interface 20
(1) Serial interface 20 functions
Serial interface 20 has the following three types of modes.
•
•
•
Operation stopped mode
Asynchronous serial interface (UART) mode
Three-wire serial I/O mode
(a) Operation stopped mode
This mode is used when serial transfer is not performed. Power consumption is minimized in this mode.
(b) Asynchronous serial interface (UART) mode
This mode is used to send and receive the one byte of data that follows a start bit. It supports full-duplex
communication.
Serial interface 20 contains a dedicated UART baud rate generator, enabling communication over a wide
range of baud rates. It is also possible to define baud rates by dividing the frequency of the input clock
pulse at the ASCK20 pin.
(c) Three-wire serial I/O mode (switchable between MSB-first and LSB-first transmission)
This mode is used to transmit 8-bit data, using three lines: a serial clock (SCK20) line and two serial data
lines (SI20 and SO20).
As it supports simultaneous transmission and reception, three-wire serial I/O mode requires less
processing time for data transmission than asynchronous serial interface mode.
Because, in three-wire serial I/O mode, it is possible to select whether 8-bit data transmission begins with
the MSB or LSB, serial interface 20 can be connected to any device regardless of whether that device is
designed for MSB-first or LSB-first transmission.
Three-wire serial I/O mode is useful for connecting peripheral I/O circuits and display controllers having
conventional clock synchronous serial interfaces, such as those of the 75X/XL, 78K, and 17K series
devices.
(2) Serial interface 20 configuration
Serial interface 20 consists of the following hardware.
Table 5-12. Serial Interface 20 Configuration
Item
Configuration
Register
Transmission shift register 20 (TXS20)
Reception shift register 20 (RXS20)
Reception buffer register 20 (RXB20)
Control register
Serial operation mode register 20 (CSIM20)
Asynchronous serial interface mode register 20 (ASIM20)
Asynchronous serial interface status register 20 (ASIS20)
Baud rate generator control register 20 (BRGC20)
62
Preliminary Product Information
Figure 5-31. Block Diagram of Serial Interface 20
Internal bus
Serial operation mode
register 20 (CSIM20)
Asynchronous serial interface
status register 20 (ASIS20)
Asynchronous serial interface
mode register 20 (ASIM20)
Reception buffer
register 20 (RXB20)
TXE20 RXE20 PS201 PS200 CL20 SL20
CSIE20 SSE20 DAP20 DIR20 CSCK20 CKP20
PE20 FE20 OVE20
Switching of the first bit
Transmission shift
register 20 (TXS20) Transmission
shift clock
Reception shift
register 20 (RXS20)
SI20/P22/
RxD20
Selector
CSIE20
DAP20
Reception
shift clock
Port mode
register (PM21)
µ
µ
Data phase
control
SO20/P21/
TxD20
Parity operation
Stop bit addition
INTST20
4
Transmission data counter
Parity operation
Stop bit addition
SL20, CL20, PS200, PS201
INTSR20/INTCSI20
Transmission
and reception
clock control
Reception data counter
Reception enabled
CSIE20
CSCK20
/2-f
/28
Baud rate
generatorNote
Reception clock
Start bit
detection
Detection clock
fX
X
Reception detected
4
SS20/P25/
TI80
CSIE20
TPS203
TPS202 TPS201 TPS200
Internal clock output
CSCK20
Baud rate generator
control register 20 (BRGC20)
Clock phase
control
SCK20/P20/
ASCK20
External clock input
Internal bus
Note See Figure 5-32 for the configuration of the baud rate generator.
Figure 5-32. Block Diagram of Baud Rate Generator 20
Reception detection clock
Transmission shift clock
Transmission
clock counter
1/2
f
X
/2
f
f
f
f
f
f
f
X
X
X
X
X
X
X
/22
/23
/24
/25
/26
/27
/28
1/2
Reception shift clock
Reception
clock counter
µ
µ
TXE20
SCK20/ASCK20/P20
RXE20
CSIE20
Reception detected
4
TPS203 TPS202 TPS201 TPS200
Baud rate generator control register 20
(BRGC20)
Internal bus
µPD789166Y, 789167Y, 789176Y, 789177Y
(a) Transmission shift register 20 (TXS20)
TXS20 is a register in which transmission data is prepared. The transmission data is output from the
TXS20 bit-serially.
When the data length is seven bits, bits 0 to 6 of the data in TXS20 will be transmission data. Writing
data to TXS20 triggers transmission.
TXS20 can be write-accessed, using an 8-bit memory manipulation instruction, but cannot be read-
accessed.
A RESET input loads FFH into TXS20.
Caution Do not write to TXS20 during transmission.
TXS20 and the reception buffer register 20 (RXB20) are mapped at the same address,
such that any attempt to read from TXS20 results in a value being read from the RXB.
(b) Reception shift register 20 (RXS20)
RXS20 is a register in which serial data, received at the RxD20 pin, is converted to parallel data. Once
one entire byte has been received, RXS20 feeds the reception data to the reception buffer register 20
(RXB20).
RXS20 cannot be manipulated directly by a program.
(c) Reception buffer register 20 (RXB20)
RXB20 is used to hold reception data. Once RXS20 has received one entire byte of data, it feeds that
data into RXB20.
When the data length is seven bits, the reception data is sent to bits 0 to 6 of RXB20, in which the MSB is
fixed to 0.
RXB20 can be read-accessed, using an 8-bit memory manipulation instruction, but cannot be write-
accessed.
A RESET input makes RXB20 undefined.
Caution RXB20 and the transmission shift register 20 (TXS20) are mapped at the same address,
such that any attempt to write to RXB20 results in a value being written to TXS20.
(d) Transmission control circuit
The transmission control circuit controls transmission. For example, it adds start, parity, and stop bits to
the data in the transmission shift register 20 (TXS20), according to the setting of the asynchronous serial
interface mode register 20 (ASIM20).
(e) Reception control circuit
The reception control circuit controls reception according to the setting of the asynchronous serial
interface mode register 20 (ASIM20). It also checks for errors, such as parity errors, during reception. If
an error is detected, the asynchronous serial interface status register 20 (ASIS20) is set according to the
status of the error.
Preliminary Product Information
65
µPD789166Y, 789167Y, 789176Y, 789177Y
(3) Serial interface 20 control registers
The following four types of registers are used to control serial interface 20.
•
•
•
•
Serial operation mode register 20 (CSIM20)
Asynchronous serial interface mode register 20 (ASIM20)
Asynchronous serial interface status register 20 (ASIS20)
Baud rate generator control register 20 (BRGC20)
(a) Serial operation mode register 20 (CSIM20)
CSIM20 is used to make the settings related to three-wire serial I/O mode.
CSIM20 is manipulated using a 1-bit or 8-bit memory manipulation instruction.
A RESET input clears CSIM20 to 00H.
Figure 5-33. Format of Serial Operation Mode Register 20
Symbol
7
6
5
0
4
0
3
2
1
0
Address When reset
FF72H 00H
R/W
R/W
CSIM20 CSIE20 SSE20
DAP20 DIR20 CSCK20 CKP20
CSIE20
Three-wire serial I/O mode operation control
0
1
Operation disabled
Operation enabled
SSE20
Communication status
Communication enabled
Functions of the SS20/P26 pin
SS20-pin selection
Port function
0
0
1
Not used
Used
Communication enabled
Communication disabled
1
DAP20
Three-wire serial I/O mode data phase selection
0
1
Outputs at the falling edge of SCK20.
Outputs at the rising edge of SCK20.
DIR20
First-bit specification
0
1
MSB
LSB
Three-wire serial I/O mode clock selection
External clock pulse input to the SCK20 pin
Output of the dedicated baud rate generator
CSCK20
0
1
CKP20
Three-wire serial I/O mode clock phase selection
0
1
Clock is low active; SCK20 is high in the idle state
Clock is high active; SCK20 is low in the idle state
Cautions 1. Bits 4 and 5 must be fixed to 0.
2. CSIM20 must be cleared to 00H, if UART mode is selected.
66
Preliminary Product Information
µPD789166Y, 789167Y, 789176Y, 789177Y
(b) Asynchronous serial interface mode register 20 (ASIM20)
ASIM20 is used to make the settings related to serial interface 20 used in asynchronous serial interface
mode.
ASIM20 is manipulated using a 1-bit or 8-bit memory manipulation instruction.
A RESET input clears ASIM20 to 00H.
Figure 5-34. Format of Asynchronous Serial Interface Mode Register 20
Symbol
7
6
5
4
3
2
1
0
0
0
Address When reset
FF70H 00H
R/W
R/W
ASIM20 TXE20 RXE20 PS201 PS200 CL20 SL20
TXE20
Transmission control
0
1
Transmission disabled
Transmission enabled
RXE20
Reception control
0
1
Reception disabled
Reception enabled
PS201 PS200
Parity bit specification
0
0
0
1
No parity
At transmission, the parity bit is fixed to 0.
At reception, a parity check is not made; no parity error is reported.
1
1
0
1
Odd parity
Even parity
CL20
Transmission data character length specification
0
1
7 bits
8 bits
SL20
Transmission data stop bit length
0
1
1 bit
2 bits
Cautions 1. Bits 0 and 1 must be fixed to 0.
2. If three-wire serial I/O mode is selected, ASIM20 must be cleared to 00H.
3. Switch operation mode from one mode to another after stopping both serial
transmission and reception.
Preliminary Product Information
67
µPD789166Y, 789167Y, 789176Y, 789177Y
Table 5-13. Serial Interface 20 Operation Mode Settings
(i) Operation stopped mode
P22/SI20/
RxD20 pin
function
P21/SO20/
TxD20 pin
function
P20/SCK20/
ASCK20 pin
function
ASIM20
CSIM20
First
bit
Shift
clock
PM20 P20
PM22 P22 PM21 P21
TXE20 RXE20 CSIE20 DIR20
CSCK20
Note 1 Note 1 Note 1 Note 1 Note 1 Note 1
0
0
0
×
×
-
-
P22
P21
P20
×
×
×
×
×
×
Other settings
Not to be set
(ii) Three-wire serial I/O mode
P22/SI20/
RxD20 pin
function
P21/SO20/
TxD20 pin
function
P20/SCK20/
ASCK20 pin
function
ASIM20
CSIM20
First
bit
Shift
clock
PM22 P22 PM21 P21 PM20 P20
TXE20 RXE20 CSIE20 DIR20
CSCK20
Note 2
×
1Note 2
SI20Note2
SO20
0
0
1
0
0
0
1
1
0
1
0
×
1
×
1
MSB
SCK20
input
External
clock
(CMOS
output)
1
0
1
SCK20
output
Internal
clock
1
1
LSB
SCK20
input
External
clock
SCK20
output
Internal
clock
Other settings
Not to be set
(iii) Asynchronous serial interface mode
P22/SI20/
RxD20 pin
function
P21/SO20/
TxD20 pin
function
P20/SCK20/
ASCK20 pin
function
ASIM20
CSIM20
First
bit
Shift
clock
PM22 P22 PM21 P21 PM20 P20
TXE20 RXE20 CSIE20 DIR20
CSCK20
Note 1 Note 1
TxD20
(CMOS
output)
1
0
1
0
1
1
0
0
0
0
0
0
0
0
1
1
×
LSB
P22
ASCK20
input
External
clock
×
×
Note 1 Note 1
P20
Internal
clock
×
×
×
×
Note 1 Note 1
0
0
1
1
×
×
1
×
RxD20
P21
ASCK20
input
External
clock
×
×
Note 1 Note 1
P20
Internal
clock
×
TxD20
(CMOS
output)
0
1
1
×
ASCK20
input
External
clock
Note 1 Note 1
P20
Internal
clock
×
Other settings
Not to be set
Notes 1. These pins can be used for port functions.
2. When only transmission is used, these pins can be used as P22 (CMOS input/output).
Remark ×: Don’t care.
68
Preliminary Product Information
µPD789166Y, 789167Y, 789176Y, 789177Y
(c) Asynchronous serial interface status register 20 (ASIS20)
ASIS20 is used to display the type of a reception error, if it occurs while asynchronous serial interface
mode is set.
ASIS20 is manipulated using an 8-bit memory manipulation instruction.
The contents of ASIS20 are undefined in three-wire serial I/O mode.
A RESET input clears ASIS20 to 00H.
Figure 5-35. Format of Asynchronous Serial Interface Status Register 20
Symbol
ASIS20
7
0
6
0
5
0
4
0
3
0
2
1
0
Address When reset
FF71H 00H
R/W
R
PE20 FE20 OVE20
PE20
Parity error flag
0
1
No parity error has occurred.
A parity error has occurred (parity mismatch in transmission data).
FE20
Framing error flag
No framing error has occurred.
0
1
A framing error has occurred (no stop bit detected).Note 1
OVE20
Overrun error flag
No overrun error has occurred.
0
1
An overrun error has occurredNote 2
(Before data was read from the reception buffer register, the subsequent recepiton sequence was
completed.)
Notes 1. Even if 2 is specified for the number of stop bits (using bit 2 (SL20) of ASIM20), only one stop bit is
detected at reception.
2. After an overrun occurs, read-access the reception buffer register 20 (RXB20). Otherwise, the overrun
error will recur each time data is received.
Preliminary Product Information
69
µPD789166Y, 789167Y, 789176Y, 789177Y
(d) Baud rate generator control register 20 (BRGC20)
BRGC20 is used to specify the serial clock for serial interface 20.
BRGC20 is manipulated using an 8-bit memory manipulation instruction.
A RESET input clears BRGC20 to 00H.
Figure 5-36. Format of Baud Rate Generator Control Register 20
Symbol
7
6
5
4
3
0
2
0
1
0
0
0
Address When reset
FF73H 00H
R/W
R/W
BRGC20 TPS203 TPS202 TPS201 TPS200
TPS203 TPS202 TPS201 TPS200
3-bit counter source clock selection
n
1
2
3
4
5
6
7
8
-
0
0
0
0
0
0
0
0
1
0
0
0
0
1
1
1
1
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
f
f
f
f
f
f
f
f
X
X
X
X
X
X
X
X
/2 (2.5 MHz)
/22 (1.25 MHz)
/23 (625 kHz)
/24 (313 kHz)
/25 (156 kHz)
/26 (78.1 kHz)
/27 (39.1 kHz)
/28 (19.5 kHz)
External clock pulse input at the ASCK20 pinNote
Not to be set
Other settings
Note An external clock can be used only in UART mode.
Cautions 1. Any attempt to write to BRGC20 during communication adversely affects the output of the
baud rate generator, thus hampering normal operation. Therefore, do not write to BRGC20
during communication.
2. Do not select n = 1 during operation at fX = 5.0 MHz, as n = 1 causes the rated baud rate to be
exceeded.
3. When the external input clock is selected, set port mode register 2 (PM2) in input mode.
Remarks 1. fX : Main system clock oscillation frequency
2. The parenthesized values apply to operation at fX = 5.0 MHz.
70
Preliminary Product Information
µPD789166Y, 789167Y, 789176Y, 789177Y
The transmission and reception clock pulses used to generate the baud rate are obtained by dividing the
frequency of the main system clock pulse or a signal input to the ASCK20 pin.
(i) Generating transmission and reception clock pulses for baud rates based on the main system
clock
The frequency of the main system clock is divided to generate the transmission and reception clock
pulses. The baud rate generated based on the main system clock is determined using the following
expression.
fX
[Baud rate] =
[Hz]
2n+1 × 8
fX : Main system clock oscillation frequency
Table 5-14. Relationships between Main System Clock Frequencies and Baud Rates (Example)
Error (%)
fX = 4.9152 MHz
Baud rate
(bps)
n
BRGC20 setting
fX = 5.0 MHz
1.73
1,200
2,400
8
7
6
5
4
3
2
70H
60H
50H
40H
30H
20H
10H
0
4,800
9,600
19,200
38,400
76,800
Caution Do not select n = 1 during operation at fX = 5.0 MHz, as n = 1 causes the rated baud rate to be
exceeded.
Preliminary Product Information
71
µPD789166Y, 789167Y, 789176Y, 789177Y
(ii) Generating transmission and reception clock pulses for baud rates based on an external clock
pulse received at the ASCK20 pin
The frequency of an external clock pulse received at the ASCK20 pin is used to generate the
transmission and reception clock pulses. The baud rate generated based on the external clock pulse
received at the ASCK20 pin is determined using the following expression.
fASCK
[Baud rate] =
[Hz]
16
fASCK: Frequency of clock pulse received at the ASCK20 pin
Table 5-15. Relationships between ASCK20 Pin Input Frequencies and Baud Rates (When BRGC20 = 80H)
Baud rate (bps)
75
ASCK20 pin input frequency (kHz)
1.2
2.4
150
300
4.8
600
9.6
1,200
2,400
4,800
9,600
19,200
31,250
38,400
19.2
38.4
76.8
153.6
307.2
500.0
614.4
72
Preliminary Product Information
µPD789166Y, 789167Y, 789176Y, 789177Y
5.8.2 SMB0 (system management bus)
(1) SMB0 functions
SMB0 has the following two types of modes.
•
•
Operation stopped mode
SMB mode (supporting multiple masters)
(a) Operation stopped mode
This mode is used when serial transfer is not performed. Power consumption is minimized in this mode.
(b) SMB mode (supporting multiple masters)
This mode is used for performing 8-bit data transmission to several devices, using a serial clock (SCL0)
line and a serial data bus (SDA0) line.
In this mode, which conforms to the SMB format, start conditions, data, stop conditions can be output on
the serial data bus during transmission. Moreover, these data can be automatically detected by hardware
during reception.
In SMB0, SCL0 and SDA0 are open-drain outputs, and therefore a pull-up resistor is required for the
serial clock line and serial data bus line.
I2C (Inter IC) bus standard mode or high-speed mode can be specified by software in SMB mode.
Figure 5-37 shows the block diagram of SMB0.
Preliminary Product Information
73
Figure 5-37. Block Diagram of SMB0
Internal bus
SMB clock selection register 0
(SMBCL0)
SMB control register 0 (SMBC0)
WTIM0 ACKE0
SCLCTL0
AWTIM0
CLD0 DAD0 SMC0 DFC0 CL01 CL00
SPIE0
SMBE0 LREL0 WREL0
STT0
SPT0
fX
Serial clock
control circuit
Serial clock wait
control circuit
Prescaler
fX/2
CL00,
CL01
Slave address register 0 (SMBSVA0)
EXC0
N-ch open-drain output
INTSMB0
Data hold
time correc-
tion circuit
µ
µ
D
Q
SMB shift register 0 (SMB0)
+
–
Acknowledge
detection circuit
Noise
eliminator
SCL0/
P23
Serial clock counter
fX/26
+
–
Noise
eliminator
SDA0/
P24
Timeout count
&
fX/27
fX/28
fXT
INTSMBOV0
Reference
generator
Start condi-
tion detection
circuit
Stop condi-
tion detection
circuit
Acknowledge
detection
circuit
control circuit
N-ch open-drain output
SCL
CTL0
ACKD0 STD0 SPD0
TOS02 TOS01 TOS00 SVIN0 LVL01 LVL00
MSTS0 ALD0 EXC0 COI0 TRC0
STIE0 TOEN0 TOCL01 TOCL00
SMB mode register 0 (SMBM0)
AWTIM0
SMB status register 0 (SMB0)
SMB input level setting register 0 (SMBVI0)
Internal bus
µPD789166Y, 789167Y, 789176Y, 789177Y
(2) SMB0 configuration
SMB0 consists of the following hardware.
Table 5-16. SMB0 Configuration
Item
Configuration
Register
SMB shift register 0 (SMB0)
Slave address register 0 (SMBSVA0)
Control register
SMB control register 0 (SMBC0)
SMB status register 0 (SMBS0)
SMB clock selection register 0 (SMBCL0)
SMB mode register 0 (SMBM0)
SMB input level setting register 0 (SMBVI0)
(a) SMB shift register 0 (SMB0)
SMB0 is a register that converts 8-bit serial data to 8-bit parallel data, and vice-versa. SMB0 is used both
for sending and receiving data.
Write and read operations for SMB0 control actual send and receive operations.
SMB0 is manipulated with an 8-bit memory manipulation instruction.
A RESET input clears SMB0 to 00H.
(b) Slave address register 0 (SMBSVA0)
This register is used to set a local address when used as a slave.
SMBSVA0 is manipulated with an 8-bit memory manipulation instruction.
A RESET input clears SMBSVA0 to 00H.
(c) SO latch
The SO latch is a latch that holds the SDA0 pin output level.
(d) Wakeup control circuit
This circuit generates an interrupt request when the address value set in slave address register 0
(SMBSVA0) and the received address match, or when an extension code is received.
(e) Clock selector
Selects the sampling clock to be used.
(f) Serial clock counter
Counts the serial clock output/input during send/receive operations, to check if 8-bit data has been sent or
received.
Preliminary Product Information
75
µPD789166Y, 789167Y, 789176Y, 789177Y
(g) Interrupt request signal generation circuit
Controls the generation of interrupt request signals.
SMB interrupts are generated with the following two triggers.
• 8th clock or 9th clock of serial clock (set with WTIM0 bitNote
)
• Generation of interrupt request at detection of stop condition (set with bit SPIE0Note
)
Note WTIM0 bit: SMB control register 0 (SMBC0) bit 3
SPIE0 bit: SMB control register 0 (SMBC0) bit 4
(h) Serial clock control circuit
In master mode, generates the clock to be output to the SCL0 pin from the sampling clock.
(i) Serial clock wait control circuit
Controls the wait timing.
(j) Acknowledge output circuit, stop condition detection circuit, start condition detection circuit,
acknowledge detection circuit
Perform output and detection of control signals.
(k) Data hold time correction circuit
Generates the data hold time from the falling edge of the serial clock.
76
Preliminary Product Information
µPD789166Y, 789167Y, 789176Y, 789177Y
(3) SMB0 control registers
The following five types of registers are used to control SMB0.
•
•
•
•
•
SMB control register 0(SMBC0)
SMB status register 0 (SMBS0)
SMB clock selection register 0 (SMBCL0)
SMB mode register 0 (SMBM0)
SMB input level setting register 0 (SMBVI0)
The following additional registers are also used.
•
•
SMB shift register 0 (SMB0)
Slave address register 0 (SMBSVA0)
(a) SMB control register 0 (SMBC0)
This register sets SMB operation enable/disable, the wait timing, and other SMB operations.
SMBC0 is manipulated with a 1-bit or 8-bit memory manipulation instruction.
A RESET input clears SMBC0 to 00H.
Caution In SMB mode, set port mode registers 2 (PM2×) to achieve the following statuses. Also, set each
output latch to 0.
• P23 (SCL0) is set to output mode (PM23 = 0).
• P24 (SDA0) is set to output mode (PM24 = 0).
Preliminary Product Information
77
µPD789166Y, 789167Y, 789176Y, 789177Y
Figure 5-38. Format of SMB Control Register 0 (1/4)
Symbol
7
6
5
4
3
2
1
0
Address When reset
FF78H 00H
R/W
R/W
SMBC0 SMBE0
LREL0
WREL0
SPIE0
WTIM0
ACKE0
STT0
SPT0
SMBE0
SMB operation
0
1
Operation disabled. Presets extension register (SMBS0). Internal operation also disabled.
Operation enabled
Clear conditions (SMBE0 = 0)
Set conditions (SMBE0 = 1)
• Set with instruction
• Cleared with instruction
• Cleared by RESET input
LREL0
Escape from transmission
0
1
Normal operation
Escapes from the current transmission and enters the standby status. Automatically cleared
after execution.
This bit is used when extension codes not relevant to the local station are received.
The SCL0 and SDA0 lines enter the high impedance status.
The following flags are cleared.
• STD0 • STT0 • SPT0 • ACKD0 • TRC0 • COI0 • EXC0 • MSTS0
The standby status continues until the following communication participation conditions are met.
• Startup as master after detection of stop condition
• Matching addresses or extension code reception after start condition
Clear conditions (LREL0 = 0)Note
Set conditions (LREL0 = 1)
• Set with instruction
• Automatically cleared after execution
• Cleared by RESET input
WREL0
Wait cancel
0
1
Does not cancel wait.
Cancels wait. Automatically cleared after wait cancellation.
Clear conditions (WREL0 = 0)Note
Set conditions (WREL0 = 1)
• Set with instruction
• Automatically cleared after execution
• Cleared by RESET input
SPIE0
Interrupt request generation at stop condition detection
0
1
Disabled
Enabled
Clear conditions (SPIE0 = 0)Note
Set conditions (SPIE0 = 1)
• Set with instruction
• Cleared with instruction
• Cleared by RESET input
Note This flag's signals are made invalid by setting SMBE0 = 0.
78
Preliminary Product Information
µPD789166Y, 789167Y, 789176Y, 789177Y
Figure 5-38. Format of SMB Control Register 0 (2/4)
WTIM0
0
Wait and interrupt request generation control
Generates interrupt request at falling edge of 8th clock.
In case of master: Waits with clock output at low level after 8 clocks have been output.
In case of slave: Waits master with clock set to low level after 8 clocks have been input.
1
Generates interrupt request at falling edge of 9th clock.
In case of master: Waits with clock at low level after 9 clocks have been output.
In case of slave: Waits master with clock set at low level after 9 clocks have been input.
The setting of this bit becomes invalid during address transmission, and becomes effective at the end of transmission.
During operation as master, a wait is inserted at the falling edge of the 9th clock during address transmission. A slave
that receives a local address enters the wait status at the falling edge of the 9th clock after generation of an acknowledge.
A slave that receives an extension code enters the wait status at the falling edge of the 8th clock.
Clear conditions (WTIM0 = 0)Note
Set conditions (WTIM0 = 1)
• Set with instruction
• Cleared with instruction
• Cleared by RESET input
ACKE0
Acknowledge control
0
1
Acknowledge disabled
Acknowledge enabled. SDA0 line set to low level during 9 clocks. However, invalid during address
transmission, and valid when EXC0 = 1.
Clear conditions (ACKE0 = 0)Note
Set conditions (ACKE0 = 1)
• Set with instruction
• Cleared with instruction
• Cleared by RESET input
Note This flag's signals are made invalid by setting SMBE0 = 0.
Preliminary Product Information
79
µPD789166Y, 789167Y, 789176Y, 789177Y
Figure 5-38. Format of SMB Control Register 0 (3/4)
STT0
Start condition trigger
0
1
Doesn't generate start condition.
When bus is released (stop status):
Generates start conditions (activation as master). Changes SDA0 line from high level to low level and
generates start condition. Then secures rated time and sets SCL0 to low level.
When not participating on bus:
Functions as start condition reservation flag. When set, automatically generates start condition after bus
is released.
Cautions regarding set timing
• Master receive operation: Setting during transmission is prohibited.
Set ACKE0 = 0; Can be set only after end of receive operation has been notified to slave.
• Master send operation: Note that start condition may not be generated normally during ACK period.
• Setting at the same time as SPT0 is prohibited.
Clear conditions (STT0 = 0)Note
Set conditions (STT0 = 1)
• Set with instruction
• Cleared with instruction
• Cleared upon defeat in arbitration
• Cleared after generation of start condition by master
• Cleared by RESET input
Note This flag's signals are made invalid by setting SMBE0 = 0.
80
Preliminary Product Information
µPD789166Y, 789167Y, 789176Y, 789177Y
Figure 5-38. Format of SMB Control Register 0 (4/4)
SPT0
Stop condition trigger
0
1
Does not generate stop condition.
Generates stop condition (end transmission as master).
After setting SDA0 line to low level, sets SCL0 line to high level, or maintains SCL0 line at high level.
Then, secures rated time, changes SDA0 line from low level to high level, and generates stop condition.
Cautions regarding set timing
• Master receive operation: Setting during transmission is prohibited.
Set ACKE0 = 0; Can be set only after end of receive operation has been notified to slave.
• Master send operation: Note that stop condition may not be generated normally during ACK period.
• Setting at the same time as STT0 is prohibited.
• Set SPT0 only during operation as master.Note 1
• Note that when WTIM0 = 0, if SPT0 is set during the wait period after 8-clock output, a stop condition is
generated during the high-level period of the 9th clock following wait release.
If it is necessary to output a 9th clock, change the setting of WTIM0 from 0 to 1 during the wait period
following 8-clock output, and set SPT0 during the wait period following the 9th clock output.
Clear conditions (SPT0 = 0)Note 2
Set conditions (SPT0 = 1)
• Cleared with instruction
• Set with instruction
• Cleared upon defeat in arbitration
• Cleared automatically after detection of stop condition
• Cleared by RESET input
Notes 1. Set STP0 only during operation as master. However, for master operation by the time a stop condition
is detected for the first time following operation enable, SPT0 must be set once to generate a stop
condition.
2. This flag's signals are made invalid by setting SMBE0 = 0.
Caution While SMB status register 0 (SMBS0) bit 3 (TRC0) = 1, when WREL0 is set at the 9th clock and
wait is released, TRC0 is cleared and the SDA0 line is placed in high impedance.
Remark STD0
: SMB status register 0 (SMBS0) bit 1
ACKD0 : SMB status register 0 (SMBS0) bit 2
TRC0
COI0
EXC0
: SMB status register 0 (SMBS0) bit 3
: SMB status register 0 (SMBS0) bit 4
: SMB status register 0 (SMBS0) bit 5
MSTS0 : SMB status register 0 (SMBS0) bit 7
Preliminary Product Information
81
µPD789166Y, 789167Y, 789176Y, 789177Y
(b) SMB status register 0 (SMBS0)
This register indicates the SMB status.
SMBS0 is manipulated with a 1-bit or 8-bit memory manipulation instruction. SMBS0 is a read-only
register.
A RESET input clears SMBS0 to 00H.
Figure 5-39. Format of SMB Status Register 0 (1/3)
7
6
5
4
3
2
1
0
Symbol
Address When reset
FF79H 00H
R/W
R
SMBS0 MSTS0
ALD0
EXC0
COI0
TRC0
ACKD0
STD0
SPD0
MSTS0
Master status
0
1
Slave status or communication wait status
Master transmission status
Clear conditions (MSTS0 = 0)
Set conditions (MSTS0 = 1)
• Cleared upon detection of stop condition
• Cleared when ALD0 = 1
• Set during generation of start condition
• Cleared when LREL0 = 1
• Cleared when SMBE0 changes from 1 to 0
• Cleared by RESET input
ALD0
Arbitration defeat detection
0
1
No arbitration, or won in arbitration.
Defeated in arbitration. MSTS0 cleared.
Clear conditions (ALD0 = 0)
Set conditions (ALD0 = 1)
• Automatically cleared after reading SMBS0Note
• Cleared when SMBE0 changes from 1 to 0
• Cleared by RESET input
• Set upon defeat in arbitration
EXC0
Extension code receive detection
0
1
Does not receive extension code.
Receives extension code.
Clear conditions (EXC0 = 0)
Set conditions (EXC0 = 1)
• Cleared upon detection of start condition
• Cleared upon detection of stop condition
• Cleared when LREL0 = 1
• Set when high-order 4 bits of received address are
0000 or 1111 (set at rising edge of 8th clock)
• Cleared when SMBE0 changes from 1 to 0
• Cleared by RESET input
Note The bit is also cleared when a bit manipulation instruction is executed for any of other bit of SMBS0.
82
Preliminary Product Information
µPD789166Y, 789167Y, 789176Y, 789177Y
Figure 5-39. Format of SMB Status Register 0 (2/3)
COI0
Matching address detection
0
1
Address does not match.
Address matches.
Clear conditions (COI0 = 0)
Set conditions (COI0 = 1)
• Cleared upon detection of start condition
• Cleared upon detection of stop condition
• Cleared when LREL0 = 1
• Set when received address matches local address
(SVA0) (set at rising edge of 8th clock)
• Cleared when SMBE0 changes from 1 to 0
• Cleared by RESET input
TRC0
Receive/send status detection
0
1
Receive status (when not in send status). Sets SDA0 line to high impedance.
Send status. Sets so that SO latch value can be output to SDA0 line (valid from falling edge of 9th
clock of 1st byte).
Clear conditions (TRC0 = 0)
Set conditions (TRC0 = 1)
• Cleared upon detection of stop condition
• Cleared when LREL0 = 1
In case of master:
• Upon generation of start condition
In case of slave:
• Cleared SMBE0 changes from 1 to 0
• Cleared when WREL0 = 1
• When "1" is input to 1st byte LSB (transmission
direction specification bit)
• Cleared when ALD0 changes from 0 to 1
• Cleared by RESET input
In case of master:
• When "1" is output to 1st byte LSB
(transmission direction specification bit)
In case of slave:
• Upon detection of start condition
In case of non-participation in communication
ACKD0
Acknowledge output
0
1
Does not detect acknowledge.
Detects acknowledge.
Clear conditions (ACKD0 = 0)
Set conditions (ACKD0 = 1)
• Cleared upon detection of stop condition
• Cleared at rising edge of 1st clock of following byte
• Cleared when LREL0 = 1
• Set when SDA0 line is low level at rising edge of 9th
clock of SCL0
• Cleared when SMBE0 changes from 1 to 0
• Cleared by RESET input
Preliminary Product Information
83
µPD789166Y, 789167Y, 789176Y, 789177Y
Figure 5-39. Format of SMB Status Register 0 (3/3)
STD0
Start condition detection
0
1
Does not detect start condition.
Detects start condition. Indicates that address transmission is in progress.
Clear conditions (STD0 = 0)
Set conditions (STD0 = 1)
• Cleared upon detection of stop condition
• Cleared at rising edge of 1st clock of byte following
address transmission
• Set upon detection of start condition
• Cleared when LREL0 = 1
• Cleared when SMBE0 changes from 1 to 0
• Cleared by RESET input
SPD0
Stop condition detection
0
1
Does not detect stop condition.
Detects stop condition. Transmission by master is completed and bus is released.
Clear conditions (SPD0 = 0)
Set conditions (SPD0 = 1)
• Cleared at rising edge of 1st clock of address transfer
byte following detection of start condition after this bit
has been set
• Set upon detection of stop condition
• Cleared when SMBE0 changes from 1 to 0
• Cleared by RESET input
Remark LREL0 : SMB control register 0 (SMBC0) bit 6
SMBE0: SMB control register 0 (SMBC0) bit 7
84
Preliminary Product Information
µPD789166Y, 789167Y, 789176Y, 789177Y
(c) SMB clock selection register 0 (SMBCL0)
This register sets the SMB transmission clock.
SMBCL0 is manipulated using a 1-bit or 8-bit memory manipulation instruction.
A RESET input clears SMBCL0 to 00H.
Figure 5-40. Format of SMB Clock Selection Register 0 (1/2)
Symbol
7
0
6
0
5
4
3
2
1
0
Address When reset
FF7AH 00H
R/W
SMBCL0
CLD0
DAD0
SMC0
DFC0
CL01
CL00
R/WNote 1
CLD0
SCL0 line level detection (valid only when SMBE0 = 1)
0
1
Detects that SCL0 line is low level.
Detects that SCL0 line is high level.
Clear conditions (CLD0 = 0)
Set conditions (CLD0 = 1)
• Cleared when SCL0 line is low level
• Cleared when SMBE0 = 0
• Cleared by RESET input
• Set when SCL0 line is high level
DAD0
SDA0 line level detection (valid only when SMBE0 = 1)
Detects that SDA0 line is low level.
Detects that SDA0 line is high level.
0
1
Clear conditions (DAD0 = 0)
Set conditions (DAD0 = 1)
• Cleared when SDA0 line is low level
• Cleared when SMBE0 = 0
• Cleared by RESET input
• Set when SDA0 line is high level
SMC0
Operating mode switching
IIC standard mode or SMB mode operation
IIC high-speed mode
0
1
Clear conditions (SMC0 = 0)
Set conditions (SMC0 = 1)
• Cleared with instruction
• Cleared by RESET input
• Set with instruction
DFC0
Digital filter operation controlNote 2
0
1
Digital filter OFF
Digital filter ON
Notes 1. Bits 4 and 5 are read-only.
2. The digital filter can be used in the high-speed mode. When used in the high-speed mode, the digital
filter provides a slower response.
Preliminary Product Information
85
µPD789166Y, 789167Y, 789176Y, 789177Y
Figure 5-40. Format of SMB Clock Selection Register 0 (2/2)
Selection clock
SMB/standard mode
CL01
CL00
High-speed mode
Note 1
Note 2
0
0
1
1
0
1
0
1
f
f
f
X
X
X
f
X
X
/2
f
/2Note 2
Not to be set
Notes 1. Available range: 1.0 MHz ≤ fX ≤ 4.19 MHz
2. Available range: fX ≥ 2.0 MHz
Caution Bits 6 and 7 must be fixed to 0.
Remark fX: Main system clock oscillation frequency
86
Preliminary Product Information
µPD789166Y, 789167Y, 789176Y, 789177Y
(d) SMB mode register 0 (SMBM0)
SMBM0 is used to specify SCL0 level control and interrupt control.
SMBM0 is manipulated using a 1-bit or 8-bit memory manipulation instruction.
A RESET input loads 20H into SMBM0.
Figure 5-41. Format of SMB Mode Register 0 (1/2)
Address When reset R/W
FF7CH 20H R/W
Symbol
SMBM0
7
0
6
0
5
4
3
1
0
2
SCLCTL0 AWTIM0
STIE0
TOEN0 TOCL01 TOCL00
SCL level controlNote 1
SCLCTL0
0
SCL0 is held low.
When SCL0 is high, SCL0 is held low after waiting until SCL0 is made low.
1
Normal operation
Start condition interrupt enable
Start condition interrupt generation is disabled.
Normal operation
STIE0
0
1
Wait and interrupt control when an address match is foundNotes 2, 3
AWTIM0
0
At the slave, an interrupt request is generated on the falling edge of the 9th clock period when an address
match (COI0 = 1) is found during address data reception.
The clock is pulled low to cause the master to wait.
1
At the slave, an interrupt request is generated on the falling edge of the 8th clock period when an address
match (COI0 = 1) is found during address data reception.
The clock is pulled low to cause the master to wait.
Notes 1. If SCL0 is made low with SCLCTL0, wait state cannot be released with WREL0.
2. When an extension code is received (EXC0 = 1), wait state is forcibly set in the 8th clock period.
3. During address transfer, the master waits in the 9th clock period.
Preliminary Product Information
87
µPD789166Y, 789167Y, 789176Y, 789177Y
Figure 5-41. Format of SMB Mode Register 0 (2/2)
Time-out count enable bitNote
The time-out count is cleared to 0, then count operation is disabled.
Time-out count operation is enabled.
TOEN0
0
1
Time-out clock selection bits
TOCL01 TOCL00
/26
/27
/28
0
0
1
1
0
1
0
1
(78.125 kHz)
(39.063 kHz)
f
f
X
X
(19.531 kHz)
(32.768 kHz)
f
f
X
XT
Note An interrupt (INTSMBOV0) is generated when the time-out counter overflows. The hardware does not
reset SMB operation. Ensure that SMB operation is reset by software after INTSMBOV0 generation.
Caution Bits 6 and 7 must be fixed to 0.
Remarks 1. fX : Main system clock oscillation frequency
2. fXT: Subsystem clock oscillation frequency
3. The parenthesized values apply to operation at fX = 5.0 MHz or fXT = 32.768 kHz.
88
Preliminary Product Information
µPD789166Y, 789167Y, 789176Y, 789177Y
(e) SMB input level setting register 0 (SMBVI0)
SMBVI0 is manipulated using a 1-bit or 8-bit memory manipulation instruction.
A RESET input clears SMBVI0 to 00H.
Figure 5-42. Format of SMB Input Level Setting Register 0
Address When reset R/W
FF7DH 00H R/W
Symbol
7
0
6
5
4
3
1
0
2
0
SMBVI0
TOS02
TOS01
TOS00
SVIN0
LVL01
LVL00
Time-out time setting bits
/27
TOS02
TOS01
TOS00
f
TO = f
X
/26
f
TO = f
X
f
TO = f
X
/28
fTO = fXT
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1,024/fTO (13.1 ms) 1,024/fTO (26.2 ms)
1,024/fTO (52.4 ms) 1,024/fTO (31.3 ms)
896/fTO (11.5 ms)
768/fTO (9.8 ms)
640/fTO (8.2 ms)
512/fTO (6.6 ms)
384/fTO (4.9 ms)
896/fTO (22.9 ms)
768/fTO (19.7 ms)
640/fTO (16.4 ms)
512/fTO (13.1 ms)
384/fTO (9.8 ms)
896/fTO (45.9 ms)
768/fTO (39.3 ms)
640/fTO (32.8 ms)
512/fTO (26.2 ms)
384/fTO (19.7 ms)
896/fTO (27.3 ms)
768/fTO (23.4 ms)
640/fTO (19.5 ms)
512/fTO (15.6 ms)
384/fTO (11.7 ms)
256/fTO (3.3 ms)
128/fTO (1.6 ms)
256/fTO (6.6 ms)
128/fTO (3.2 ms)
256/fTO (13.1 ms)
128/fTO (6.6 ms)
256/fTO (7.8 ms)
128/fTO (3.9 ms)
Input level selection bit
SVIN0
0
1
Same input level as the ordinary hysteresis
The voltage set with LVL01 and LVL00 is used as the SCL0 and SDA0 input level threshold.
LVL01
LVL00
Input level selection bitsNote
The input level is 0.1875 × VDD
0
0
1
1
0
1
0
1
.
The input level is 0.25 × VDD
The input level is 0.375 × VDD
The input level is 0.5 × VDD
.
.
.
Note Set an input level from 0.75 to 1.25 V.
Caution Bits 2 and 7 must be fixed to 0.
Remarks 1. fX : Main system clock oscillation frequency
2. fXT : Subsystem clock oscillation frequency
3. fTO : Clock selected using bits 0 and 1 (TOCL00, TOCL01) of SMB mode register 0 (SMBM0)
4. The parenthesized values apply to operation at fX = 5.0 MHz or fXT = 32.768 kHz.
Preliminary Product Information
89
µPD789166Y, 789167Y, 789176Y, 789177Y
(f) SMB shift register 0 (SMB0)
This register is used to perform serial send/receive (shift operation) in synchronization with the serial
clock.
Read/write operations can be performed in 8-bit units, but do not write data to the SMB0 during
transmission.
Symbol
SMB0
7
6
5
4
3
2
1
0
Address When reset
FF1BH 00H
R/W
R/W
(g) SMB slave address register 0 (SMBSVA0)
This register stores the SMB slave address.
It can be read/written in 8-bit units, but bit 0 is fixed to 0.
Symbol
7
6
5
4
3
2
1
0
Address When reset
FF7BH 00H
R/W
R/W
SMBSVA0
0
90
Preliminary Product Information
µPD789166Y, 789167Y, 789176Y, 789177Y
5.9 Multiplier
5.9.1 Multiplier function
The multiplier enables a calculation of 8 bits × 8 bits = 16 bits.
5.9.2 Multiplier configuration
(1) Multiplication result storage register 0 (MUL0)
This register stores 16-bit multiplication results.
This register holds the result of a multiplication after 16 CPU clock periods.
MUL0 is manipulated using a 16-bit memory manipulation instruction.
A RESET input makes MUL0 undefined.
Caution MUL0 is designed to be manipulated using a 16-bit memory manipulation instruction. It can
also be manipulated using 8-bit memory manipulation instructions, however. When an 8-bit
memory manipulation instruction is used to set MUL0, it must be in a direct addressing
access mode.
(2) Multiplication data registers A and B (MRA0, MRB0)
These registers store 8-bit multiplication data. The multiplier multiplies the value of MRA0 by the value of
MRB0.
MRA0 and MRB0 are set using an 8-bit memory manipulation instruction.
A RESET input makes these registers undefined.
Figure 5-43 shows the block diagram of the multiplier.
Preliminary Product Information
91
µPD789166Y, 789167Y, 789176Y, 789177Y
Figure 5-43. Block Diagram of Multiplier
Internal bus
Multiplication data register B
(MRB0)
Multiplication data register A
(MRA0)
Counter value
3
3-bit
counter
CPU clock
Selector
Start
Clear
16-bit adder
16-bit multiplication result storage
register (master) (MUL0)
16-bit multiplication result storage
register (slave)
Reset
0
0
0
0
0
0
0
MULST0
Multiplier control register (MULC0)
Internal bus
92
Preliminary Product Information
µPD789166Y, 789167Y, 789176Y, 789177Y
5.9.3 Multiplier control register
The following register is used to control the multiplier:
•
Multiplier control register 0 (MULC0)
MULC0 not only controls operations, but also indicates the operation status of the multiplier.
MULC0 is manipulated using a 1-bit or 8-bit memory manipulation instruction.
A RESET input clears MULC0 to 00H.
Figure 5-44. Format of Multiplier Control Register 0 (MULC0)
Address When reset R/W
FFD2H 00H R/W
Symbol
MULC0
7
0
6
0
5
0
4
0
3
0
1
0
0
2
0
MULST0
Multiplier operation status
Multiplier operation start control bit
MULST0
Operation is stopped after the counter is cleared to 0.
Operation is enabled.
0
1
Operation is stopped.
Operation is being executed.
Caution Bits 1 to 7 must be fixed to 0.
Preliminary Product Information
93
µPD789166Y, 789167Y, 789176Y, 789177Y
6. INTERRUPT FUNCTIONS
6.1 Interrupt Function Types
Two types of interrupt function are supported.
(1) Nonmaskable interrupt
A nonmaskable interrupt request is accepted unconditionally, that is, even when interrupts are disabled.
A nonmaskable interrupt takes precedence over all other interrupts; it is not subjected to interrupt priority control.
A nonmaskable interrupt causes the standby release signal to be generated.
The µPD789166Y, µPD789167Y, µPD789176Y, and µPD789177Y support one nonmaskable interrupt source
namely, the watchdog timer interrupt.
(2) Maskable interrupt
Maskable interrupts are those which are subjected to mask control. If two or more maskable interrupts occur
simultaneously, the default priority listed in Table 6-1 applies.
The maskable interrupts cause the standby release signal to be generated.
The maskable interrupts supported by the µPD789166Y, µPD789167Y, µPD789176Y, and µPD789177Y include
4 external interrupt sources and 12 internal interrupt sources.
6.2 Interrupt Sources and Configuration
The µPD789166Y, µPD789167Y, µPD789176Y, and µPD789177Y each support a total of 17 maskable and
nonmaskable interrupt sources. (See Table 6-1.)
94
Preliminary Product Information
µPD789166Y, 789167Y, 789176Y, 789177Y
Table 6-1. Interrupt Sources
PriorityNote 1
Interrupt type
Interrupt source
Trigger
Internal/external Vector table Basic configuration
typeNote 2
address
Name
Nonmaskable
interrupt
−
INTWDT
Watchdog timer overflow
(when watchdog timer mode 1 is
selected)
Internal
0004H
(A)
(B)
(C)
Maskable
interrupt
0
INTWDT
Watchdog timer overflow
(when the interval timer mode is
selected)
1
2
3
4
5
INTP0
INTP1
INTP2
INTP3
INTSR20
Pin input edge detection
External
Internal
0006H
0008H
000AH
000CH
000EH
End of UART reception on serial
interface 20
(B)
INTCSI20
INTST20
End of three-wire SIO transfer
reception on serial interface 20
6
End of UART transmission on
serial interface 20
0010H
7
8
9
INTWT
Clock timer interrupt
Interval timer interrupt
0012H
0014H
0016H
INTWTI
INTTM80
Generation of match signal for
8-bit timer/event counter 80
10
11
12
13
14
15
INTTM81
INTTM82
INTTM90
INTSMB0
Generation of match signal for
8-bit timer/event counter 81
0018H
001AH
001CH
001EH
0020H
0022H
Generation of match signal for
8-bit timer counter 82
Generation of match signal for
16-bit timer counter 90
System management bus
interrupt
INTSMBOV0 System management bus time-
out interrupt
INTAD0
A/D conversion completion signal
Notes 1. The priority regulates which maskable interrupt is higher, when two or more maskable interrupts are
requested simultaneously. Zero signifies the highest priority, while 15 is the lowest.
2. Basic configuration types (A), (B), and (C) correspond to (A), (B), and (C) in Figure 6-1, respectively.
Preliminary Product Information
95
µPD789166Y, 789167Y, 789176Y, 789177Y
Figure 6-1. Basic Configuration of Interrupt Functions
(A) Internal nonmaskable interrupt
Internal bus
Vector table address
generation circuit
Interrupt request
Standby release signal
(B) Internal maskable interrupt
Internal bus
MK
IE
Vector table address
generation circuit
IF
Interrupt request
Standby release signal
(C) External maskable interrupt
Internal bus
External interrupt mode
register (INTM0, INTM1)
MK
IE
Vector table address
generation circuit
Interrupt
request
Edge detection
circuit
IF
Standby release
signal
IF : Interrupt request flag
IE : Interrupt enable flag
MK : Interrupt mask flag
96
Preliminary Product Information
µPD789166Y, 789167Y, 789176Y, 789177Y
6.3 Interrupt Function Control Registers
The interrupt functions are controlled by the following registers.
•
•
•
•
Interrupt request flag registers (IF0 and IF1)
Interrupt mask flag registers (MK0 and MK1)
External interrupt mode registers (INTM0 and INTM1)
Program status word (PSW)
Table 6-2 lists interrupt requests, the corresponding interrupt request flags, and interrupt mask flags.
Table 6-2. Interrupt Request Signals and Corresponding Flags
Interrupt request signal
Interrupt request flag
Interrupt mask flag
INTWDT
INTP0
INTP1
INTP2
INTP3
TMIF4
PIF0
TMMK4
PMK0
PIF1
PMK1
PIF2
PMK2
PIF3
PMK3
INTSR20/INTCSI20
INTST20
SRIF20
STIF20
WTIF
SRMK20
STMK20
WTMK
INTWT
INTWTI
WTIFI
TMIF80
TMIF81
TMIF82
TMIF90
SMBIF0
WTMKI
TMMK80
TMMK81
TMMK82
TMMK90
SMBMK0
INTTM80
INTTM81
INTTM82
INTTM90
INTSMB0
INTSMBOV0
INTAD0
SMBOVIF0
ADIF0
SMBOVMK0
ADMK0
Preliminary Product Information
97
µPD789166Y, 789167Y, 789176Y, 789177Y
(1) Interrupt request flag registers (IF0 and IF1)
An interrupt request flag is set (1), when the corresponding interrupt request is issued, or when the related
instruction is executed. It is cleared (0), when the interrupt request is accepted, when a RESET signal is input, or
when a related instruction is executed.
IF0 and IF1 are manipulated using a 1-bit or 8-bit memory manipulation instruction.
A RESET input clears IF0 and IF1 to 00H.
Figure 6-2. Format of Interrupt Request Flag Register
7
6
5
4
3
2
1
0
Symbol
Address When reset
R/W
R/W
IF0 WTIF STIF20SRIF20 PIF3 PIF2 PIF1 PIF0 TMIF4
FFE0H
00H
7
6
5
4
3
2
1
0
IF1 ADIF0 SMBOVIF0SMBIF0TMIF90TMIF82TMIF81TMIF80 WTIIF
FFE1H
00H
R/W
XXIFX
Interrupt request flag
No interrupt request signal has been issued.
An interrupt request signal has been issued; an interrupt request has been made.
0
1
Cautions 1. The TMIF4 flag can be read- and write-accessed only when the watchdog timer is being
used as an interval timer. It must be cleared to 0 if the watchdog timer is used in watchdog
timer mode 1 or 2.
2. When port 3 is being used as an output port, and its output level is changed, an interrupt
request flag is set, because this port is also used as an external interrupt input. To use port 3
in output mode, therefore, the interrupt mask flag must be set to 1 in advance.
98
Preliminary Product Information
µPD789166Y, 789167Y, 789176Y, 789177Y
(2) Interrupt mask flag registers (MK0 and MK1)
The interrupt mask flags are used to enable and disable the corresponding maskable interrupts.
MK0 and MK1 are manipulated using a 1-bit or 8-bit memory manipulation instruction.
A RESET input loads FFH into MK0 and MK1.
Figure 6-3. Format of Interrupt Mask Flag Register
7
6
5
4
3
2
1
0
Symbol
Address When reset
R/W
R/W
MK0 WTMKSTMK20 SRMK20 PMK3 PMK2 PMK1 PMK0 TMMK4
FFE4H
FFH
7
6
5
4
3
2
1
0
MK1 ADMK0 SMBOVMK0 SMBMK0 TMMK90 TMMK82 TMMK81 TMMK80 WTIMK
FFE5H
FFH
R/W
XXMKX
Interrupt handling control
0
1
Enable interrupt handling.
Disable interrupt handling.
Cautions 1. When the watchdog timer is being used in watchdog timer mode 1 or 2, any attempt to read
TMMK4 flag results in an undefined value being detected.
2. When port 3 is being used as an output port, and its output level is changed, an interrupt
request flag is set, because this port is also used as an external interrupt input. To use port
3 in output mode, therefore, the interrupt mask flag must be set to 1 in advance.
Preliminary Product Information
99
µPD789166Y, 789167Y, 789176Y, 789177Y
(3) External interrupt mode register 0 (INTM0)
INTM0 is used to specify an effective edge for INTP0 to INTP2.
INTM0 is manipulated using an 8-bit memory manipulation instruction.
A RESET input clears INTM0 to 00H.
Figure 6-4. Format of External Interrupt Mode Register 0
Symbol
7
6
5
4
3
2
1
0
0
0
Address When reset
FFECH 00H
R/W
R/W
INTM0 ES21 ES20 ES11 ES10 ES01 ES00
ES21 ES20
INTP2 effective edge selection
INTP1 effective edge selection
INTP0 effective edge selection
0
0
1
1
0
1
0
1
Falling edge
Rising edge
Not to be set
Both rising and falling edges
ES11 ES10
0
0
1
1
0
1
0
1
Falling edge
Rising edge
Not to be set
Both rising and falling edges
ES01 ES00
0
0
1
1
0
1
0
1
Falling edge
Rising edge
Not to be set
Both rising and falling edges
Cautions 1. Bits 0 and 1 must be fixed to 0.
2. Before setting INTM0, set the corresponding interrupt mask flag register to 1 to disable
interrupts.
To enable interrupts, clear (0) the corresponding interrupt request flag, then the
corresponding interrupt mask flag register.
100
Preliminary Product Information
µPD789166Y, 789167Y, 789176Y, 789177Y
(4) External interrupt mode register 1 (INTM1)
INTM1 is used to specify an effective edge for INTP3.
INTM1 is manipulated using an 8-bit memory manipulation instruction.
A RESET input clears INTM1 to 00H.
Figure 6-5. Format of External Interrupt Mode Register 1
6
0
5
0
4
0
3
0
2
0
1
0
Address When reset
FFEDH 00H
R/W
R/W
Symbol
INTM1
7
0
ES31
ES30
ES31
ES30
INTP3 effective edge selection
0
0
1
1
0
1
0
1
Falling edge
Rising edge
Not to be set
Both rising and falling edges
Cautions 1. Bits 2 to 7 must be fixed to 0.
2. Before setting INTM1, set the corresponding interrupt mask flag register to 1 to disable
interrupts.
To enable interrupts, clear (0) the corresponding interrupt request flag, then the
corresponding interrupt mask flag register.
Preliminary Product Information
101
µPD789166Y, 789167Y, 789176Y, 789177Y
(5) Program status word (PSW)
The program status word is used to hold the instruction execution result and the current status of the interrupt
requests. The IE flag, used to enable and disable maskable interrupts, is mapped to the PSW.
The PSW can be read- and write-accessed in 8-bit units, as well as in 1-bit units when using bit manipulation
instructions and dedicated instructions (EI and DI). When a vector interrupt is accepted, the PSW is
automatically saved to a stack, and the IE flag is reset (0).
A RESET input loads 02H into the PSW.
Figure 6-6. Program Status Word Configuration
Symbol
PSW
7
6
Z
5
0
4
3
0
2
0
1
1
0
When reset
02H
IE
AC
CY
Used in the execution of ordinary instructions
IE
0
Whether to enable/disable interrupt acceptance
Disable
Enable
1
102
Preliminary Product Information
µPD789166Y, 789167Y, 789176Y, 789177Y
7. STANDBY FUNCTION
7.1 Standby Function
The standby function is supported to minimize the system’s power consumption. There are two standby modes:
HALT and STOP.
HALT and STOP modes are selected using the HALT and STOP instructions, respectively.
(1) HALT mode
In HALT mode, the CPU clock is stopped. Interleaving normal mode with HALT mode can reduce the average
power consumption.
(2) STOP mode
In STOP mode, the main system clock is stopped. As a result, main system clock-based operation is also
stopped, thus minimizing power consumption.
Caution Before shifting to STOP mode, first stop the operation of the hardware, then execute the
STOP instruction.
Preliminary Product Information
103
µPD789166Y, 789167Y, 789176Y, 789177Y
Table 7-1. Operation Statuses in HALT Mode
Item
HALT mode operation status while the main
system clock is running
HALT mode operation status while the
subsystem clock is running
While the subsystem
clock is running
While the subsystem
clock is not running
While the main
system clock is
running
While the main
system clock is not
running
Clock generator
CPU
Can operate with the main system clock.
Operation disabled
Does not run.
Port (output latch)
Remains in the state existing before the selection of HALT mode.
Operation enabledNote 1
Operation enabledNote 2
Operation enabledNote 3
Operation enabledNote 4
Operation enabledNote 2
16-bit timer counter
(TM90)
Operation enabled
Operation enabled
Operation enabled
Operation enabled
Operation enabled
8-bit timer/event counter
(TM80)
8-bit timer/event counter
(TM81)
Operation enabledNote 1
Operation enabledNote 1
8-bit timer counter
(TM82)
Operation enabled
Operation enabled
Operation enabledNote 2
Operation disabled
Clock timer
Operation enabled
Operation enabled
Operation enabled
Operation enabled
Operation disabled
Operation disabled
Operation enabledNote 7
Watchdog timer
Serial interface
SMB
Operation enabledNote 5
Operation enabledNote 6
A/D converter
Multiplier
External interrupt
Notes 1. Operation is enabled while the main system clock is selected.
2. Operation is enabled while the subsystem clock is selected.
3. Operation is enabled only when TI80 is selected as the count clock.
4. Operation is enabled only when TI81 is selected as the count clock.
5. Operation is enabled in both three-wire serial I/O and UART modes while an external clock is being
used.
6. While in slave mode, an interrupt can be generated when an address match is found.
7. Maskable interrupt that is not masked
104
Preliminary Product Information
µPD789166Y, 789167Y, 789176Y, 789177Y
Table 7-2. Operation Statuses in STOP Mode
Item
STOP mode operation status while the main system clock is running
While the subsystem clock is running While the subsystem clock is not running
Clock generator
CPU
Does not operate with the main system clock.
Operation disabled
Port (output latch)
Remains in the state existing before the selection of STOP mode.
Operation enabledNote 1
Operation disabled
16-bit timer counter
(TM90)
Operation enabledNote 2
Operation enabledNote 3
8-bit timer/event counter
(TM80)
8-bit timer/event counter
(TM81)
Operation enabledNote 1
Operation disabled
8-bit timer counter
(TM82)
Operation enabledNote 1
Operation disabled
Clock timer
Watchdog timer
Serial interface
SMB
Operation disabled
Operation enabledNote 4
Operation enabledNote 5
Operation disabled
A/D converter
Multiplier
Operation disabled
Operation enabledNote 6
External interrupt
Notes 1. Operation is enabled while the subsystem clock is selected.
2. Operation is enabled only when TI80 is selected as the count clock.
3. Operation is enabled only when TI81 is selected as the count clock.
4. Operation is enabled in both three-wire serial I/O and UART modes while an external clock is being
used.
5. While in slave mode, an interrupt can be generated when an address match is found.
6. Maskable interrupt that is not masked
Preliminary Product Information
105
µPD789166Y, 789167Y, 789176Y, 789177Y
7.2 Standby Function Control Register
The oscillation settling time selection register (OSTS) is used to control the wait time, from the time STOP mode is
deselected by an interrupt request, until oscillation settles.
The OSTS is manipulated using an 8-bit memory manipulation instruction.
A RESET input loads 04H into the OSTS. If a RESET input is used to deselect STOP mode, the time required for
oscillation to settle will be 215/fX, rather than 217/fX.
Figure 7-1. Format of Oscillation Settling Time Selection Register
Symbol
OSTS
7
0
6
0
5
0
4
3
0
2
1
0
Address When reset
FFFAH 04H
R/W
R/W
0
OSTS2 OSTS1 OSTS0
OSTS1 OSTS0
OSTS2
Oscillation settling time selection
212/fx (819
µs)
0
1
0
0
0
0
0
0
1
215/fx (6.55 ms)
217/fx (26.2 ms)
Not to be set
Other settings
Caution The wait time required to deselect STOP mode does not include the time (“a” in the following
figure) required for the clock oscillation to settle after STOP mode is deselected, regardless of
whether STOP mode is deselected by a RESET input or interrupt.
STOP mode release
X1 pin voltage
waveform
a
VSS
Remarks 1. fX: Main system clock oscillation frequency
2. The parenthesized values apply to operation at fX = 5.0 MHz.
106
Preliminary Product Information
µPD789166Y, 789167Y, 789176Y, 789177Y
8. RESET FUNCTIONS
The µPD789166Y, µPD789167Y, µPD789176Y, and µPD789177Y can be reset using the following signals.
(1) External reset signal input to the RESET pin
(2) Internal reset signal generated upon the elapse of the period set in the watchdog timer, used for detecting an
unintended program loop
The external and internal reset signals are functionally equivalent. When RESET is input, they cause program
execution to begin at the addresses indicated at addresses 0000H and 0001H, respectively.
If a low level signal is applied to the RESET pin, or if the watchdog timer overflows, a reset occurs, causing each
piece of the hardware to enter the states listed in Table 8-1. While a reset signal is being input, or while the
oscillation frequency is settling immediately after the end of a reset sequence, each pin remains in the high-
impedance state.
If a high level signal is applied to the RESET pin, a reset sequence is terminated, and program execution begins
once the oscillation settling time (215/fX) elapses. A watchdog timer overflow-based reset sequence is terminated
automatically. Similarly, program execution begins upon the elapse of the oscillation settling time (215/fX).
Cautions 1. To use an external reset sequence, supply a low level signal to the RESET pin and maintain
the signal for at least 10 µs.
2. When a reset is used to deselect STOP mode, the information related to STOP mode is held
during the reset sequence, that is, while the reset signal is applied. The port pins remain in
the high-impedance state, however.
Figure 8-1. Reset Function Block Diagram
RESET
Reset control circuit
Reset signal
Over-
flow
Count clock
Watchdog timer
Stop
Interrupt function
Preliminary Product Information
107
µPD789166Y, 789167Y, 789176Y, 789177Y
Table 8-1. State of the Hardware after a Reset (1/2)
Hardware
State after reset
Program counter (PC)Note 1
Loaded with the contents of
the reset vector table
(0000H, 0001H)
Stack pointer (SP)
Program status word (PSW)
RAM
Undefined
02H
UndefinedNote 2
Data memory
General-purpose register
UndefinedNote 2
Ports (P0 to P3, P5, P6) (output latch)
Port mode registers (PM0 to PM3, PM5)
Pull-up resistor option registers (PU0, PUB2, PUB3)
Processor clock control register (PCC)
Suboscillation mode register (SCKM)
00H
FFH
00H
02H
00H
Subclock control register (CSS)
00H
Oscillation settling time selection register (OSTS)
04H
16-bit timer/counter 90
Timer register (TM90)
0000H
FFFFH
Undefined
00H
Compare register (CR90)
Capture register (TCP90)
Mode control register (TMC90)
Buzzer output control register (BZC90)
Timer registers (TM80 to TM82)
Compare registers (CR80 to CR82)
Mode control registers (TMC80 to TMC82)
Mode control register (WTM)
00H
8-bit timer/event counters 80
to 82
00H
Undefined
00H
Clock timer
00H
Watchdog timer
Timer clock selection register (TCL2)
Mode register (WDTM)
00H
00H
A/D converter
Mode register (ADM0)
00H
A/D input selection register (ADS0)
A/D conversion result register (ADCR0)
Mode register (CSIM20)
00H
Undefined
00H
Serial interface 20
Asynchronous serial interface mode register (ASIM20)
Asynchronous serial interface status register (ASIS20)
Baud rate generator control register (BRGC20)
Transmission shift register (TXS20)
Reception buffer register (RXB20)
00H
00H
00H
FFH
Undefined
Notes 1. While a reset signal is being input, and during the oscillation settling period, the contents of the PC will
be undefined, while the remainder of the hardware will be the same as after the reset.
2. In standby mode, the RAM enters the hold state after a reset.
108
Preliminary Product Information
µPD789166Y, 789167Y, 789176Y, 789177Y
Table 8-1. State of the Hardware after a Reset (2/2)
Hardware
State after reset
SMB0
Control register (SMBC0)
00H
00H
00H
00H
20H
00H
00H
Status register (SMBS0)
Clock selection register (SMBCL0)
Slave address register (SMBSVA0)
Mode register (SMBM0)
Input level setting register (SMBVI0)
Shift register (SMB0)
Multiplier
Interrupts
16-bit multiplication result storage register (MUL0)
Multiplication data register (MRA0, MRB0)
Multiplier control register (MULC0)
Request flag registers (IF0, IF1)
Mask flag registers (MK0, MK1)
External interrupt mode registers (INTM0, INTM1)
Undefined
Undefined
00H
00H
FFH
00H
Preliminary Product Information
109
µPD789166Y, 789167Y, 789176Y, 789177Y
9. MASK OPTIONS
The µPD789166Y, µPD789167Y, µPD789176Y, and µPD789177Y have the following mask options.
•
Mask option for P50 to P53
This option is used to specify whether to incorporate a pull-up resistor, as follows:
<1> To indicate whether a pull-up resistor is to be incorporated, an individual bit is specified, independently of
the other bits.
<2> The specification of each bit indicates that a pull-up resistor is not to be incorporated.
110
Preliminary Product Information
µPD789166Y, 789167Y, 789176Y, 789177Y
10. INSTRUCTION SET OVERVIEW
The instruction set for the µPD789166Y, µPD789167Y, µPD789176Y, and µPD789177Y is listed later.
10.1 Legend
10.1.1 Operand formats and descriptions
The description made in the operand field of each instruction conforms to the operand format for the instructions
listed below (the details conform with the assembly specification). If more than one operand format is listed for an
instruction, one is selected. Uppercase letters, #, !, $, and a pair of [ and ] are used to specify keywords, which must
be written exactly as they appear. The meanings of these special characters are as follows:
•
•
•
•
#: Immediate data specification
$: Relative address specification
!: Absolute address specification
[ and ]: Indirect address specification
Immediate data should be described using appropriate values or labels. The specification of values and labels
must be accompanied by #, !, $, or a pair of [ and ].
Operand registers, expressed as r or rp in the formats, can be described using both functional names (X, A, C,
etc.) and absolute names (R0, R1, R2, and other names listed in Table 11-1).
Table 10-1. Operand Formats and Descriptions
Format
Description
r
X (R0), A (R1), C (R2), B (R3), E (R4), D (R5), L (R6), H (R7)
AX (RP0), BC (RP1), DE (RP2), HL (RP3)
Special function register symbol
rp
sfr
saddr
FE20H to FF1FH: Immediate data or label
saddrp
FE20H to FF1FH: Immediate data or label (even addresses only)
addr16
addr5
0000H to FFFFH: Immediate data or label
(only even address for 16-bit data transfer instructions)
0040H to 007FH: Immediate data or label (even addresses only)
word
byte
bit
16-bit immediate data or label
8-bit immediate data or label
3-bit immediate data or label
Remark For the special function register symbols, see Table 4-1.
Preliminary Product Information
111
µPD789166Y, 789167Y, 789176Y, 789177Y
10.1.2 Descriptions of the operation field
A
: A register (8-bit accumulator)
: X register
X
B
: B register
C
: C register
D
: D register
E
: E register
H
: H register
L
: L register
AX
BC
DE
HL
PC
SP
: AX register pair (16-bit accumulator)
: BC register pair
: DE register pair
: HL register pair
: Program counter
: Stack pointer
PSW : Program status word
CY
AC
Z
: Carry flag
: Auxiliary carry flag
: Zero flag
IE
: Interrupt request enable flag
NMIS : Flag to indicate that a nonmaskable interrupt is being handled
() : Contents of a memory location indicated by a parenthesized address or register name
XH, XL : Upper and lower 8 bits of a 16-bit register
^
: Logical product (AND)
: Logical sum (OR)
: Exclusive OR
: Inverted data
addr16 : 16-bit immediate data or label
jdisp8 : Signed 8-bit data (displacement value)
10.1.3 Description of the flag operation field
(blank) : No change
0
1
×
R
: To be cleared to 0
: To be set to 1
: To be set or cleared according to the result
: To be restored to the previous value
112
Preliminary Product Information
µPD789166Y, 789167Y, 789176Y, 789177Y
10.2 Operations
Mnemonic
Operand
Byte
Clock
Operation
Flag
Z
AC CY
MOV
r, #byte
saddr, #byte
3
3
3
2
6
6
6
4
r ← byte
(saddr) ← byte
sfr ← byte
A ← r
sfr, #byte
A, r
Note 1
Note 1
2
4
r ← A
r, A
A, saddr
saddr, A
A, sfr
2
2
2
2
3
3
3
2
2
1
1
1
1
2
2
1
2
4
4
4
4
8
8
6
4
4
6
6
6
6
6
6
4
6
A ← (saddr)
(saddr) ← A
A ← sfr
sfr, A
sfr ← A
A, !addr16
!addr16, A
PSW, #byte
A, PSW
PSW, A
A, [DE]
A ← (addr16)
(addr16) ← A
PSW ← byte
A ← PSW
PSW ← A
A ← (DE)
×
×
×
×
×
×
[DE], A
(DE) ← A
A, [HL]
A ← (HL)
[HL], A
(HL) ← A
A, [HL + byte]
[HL + byte], A
A, X
A ← (HL + byte)
(HL + byte) ← A
A ↔ X
XCH
Note 2
A ↔ r
A, r
A, saddr
A, sfr
2
2
1
1
2
3
2
2
1
6
6
8
8
8
6
6
8
4
A ↔ (saddr)
A ↔ (sfr)
A, [DE]
A ↔ (DE)
A, [HL]
A ↔ (HL)
A, [HL + byte]
rp, #word
AX, saddrp
saddrp, AX
A ↔ (HL + byte)
rp ← word
MOVW
AX ← (saddrp)
(saddrp) ← AX
AX ← rp
Note 3
Note 3
AX, rp
rp, AX
1
4
rp ← AX
Notes 1. Except when r = A.
2. Except when r = A or X.
3. Only when rp = BC, DE, or HL.
Remark The instruction clock cycle is based on the CPU clock (fCPU), specified in the processor clock controller
register (PCC).
Preliminary Product Information
113
µPD789166Y, 789167Y, 789176Y, 789177Y
Mnemonic
Operand
Byte
1
Clock
8
Operation
Flag
Z
AC CY
Note
XCHW
ADD
AX ↔ rp
AX, rp
A, #byte
2
3
2
2
3
1
2
2
3
2
2
3
1
2
2
3
2
2
3
1
2
2
3
2
2
3
1
2
2
3
2
2
3
1
2
4
6
4
4
8
6
6
4
6
4
4
8
6
6
4
6
4
4
8
6
6
4
6
4
4
8
6
6
4
6
4
4
8
6
6
A, CY ← A + byte
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
saddr, #byte
A, r
(saddr), CY ← (saddr) + byte
A, CY ← A + r
A, saddr
A, !addr16
A, [HL]
A, CY ← A + (saddr)
A, CY ← A + (addr16)
A, CY ← A + (HL)
A, [HL + byte]
A, #byte
saddr, #byte
A, r
A, CY ← A + (HL + byte)
A, CY ← A + byte + CY
(saddr), CY ← (saddr) + byte + CY
A, CY ← A + r + CY
ADDC
A, saddr
A, !addr16
A, [HL]
A, CY ← A + (saddr) + CY
A, CY ← A + (addr16) + CY
A, CY ← A + (HL) + CY
A, CY ← A + (HL + byte) + CY
A, CY ← A − byte
A, [HL + byte]
A, #byte
saddr, #byte
A, r
SUB
(saddr), CY ← (saddr) − byte
A, CY ← A − r
A, saddr
A, !addr16
A, [HL]
A, CY ← A − (saddr)
A, CY ← A − (addr16)
A, CY ← A − (HL)
A, [HL + byte]
A, #byte
saddr, #byte
A, r
A, CY ← A − (HL + byte)
A, CY ← A − byte − CY
(saddr), CY ← (saddr) − byte − CY
A, CY ← A − r − CY
SUBC
A, saddr
A, !addr16
A, [HL]
A, CY ← A − (saddr) − CY
A, CY ← A − (addr16) − CY
A, CY ← A − (HL) − CY
A, CY ← A − (HL + byte) − CY
A ← A byte
A, [HL + byte]
A, #byte
AND
saddr, #byte
A, r
(saddr) ← (saddr) byte
A ← A
r
A, saddr
A, !addr16
A, [HL]
A ← A (saddr)
A ← A (addr16)
A ← A (HL)
A, [HL + byte]
A ← A (HL + byte)
Note Only when rp = BC, DE, or HL.
Remark The instruction clock cycle is based on the CPU clock (fCPU), specified in the processor clock controller
register (PCC).
114
Preliminary Product Information
µPD789166Y, 789167Y, 789176Y, 789177Y
Mnemonic
Operand
Byte
Clock
Operation
Flag
Z
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
AC CY
OR
A, #byte
2
3
2
2
3
1
2
2
3
2
2
3
1
2
2
3
2
2
3
1
2
3
3
3
2
2
2
2
1
1
1
1
1
1
4
6
4
4
8
6
6
4
6
4
4
8
6
6
4
6
4
4
8
6
6
6
6
6
4
4
4
4
4
4
2
2
2
2
A ← A byte
(saddr) ← (saddr) byte
A ← A
saddr, #byte
A, r
r
A, saddr
A, !addr16
A, [HL]
A, [HL + byte]
A, #byte
saddr, #byte
A, r
A ← A (saddr)
A ← A (addr16)
A ← A (HL)
A ← A (HL + byte)
A ← A byte
XOR
(saddr) ← (saddr) byte
A ← A
r
A, saddr
A, !addr16
A, [HL]
A, [HL + byte]
A, #byte
saddr, #byte
A, r
A ← A (saddr)
A ← A (addr16)
A ← A (HL)
A ← A (HL + byte)
A − byte
CMP
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
(saddr) − byte
A − r
A, saddr
A, !addr16
A, [HL]
A, [HL + byte]
AX, #word
AX, #word
AX, #word
r
A − (saddr)
A − (addr16)
A − (HL)
A − (HL + byte)
ADDW
SUBW
CMPW
INC
AX, CY ← AX + word
AX, CY ← AX − word
AX − word
r ← r + 1
saddr
(saddr) ← (saddr) + 1
r ← r − 1
DEC
r
saddr
(saddr) ← (saddr) − 1
rp ← rp + 1
INCW
DECW
ROR
rp
rp
rp ← rp − 1
A, 1
(CY, A7 ← A0, Am−1 ← Am) × 1
(CY, A0 ← A7, Am+1 ← Am) × 1
(CY ← A0, A7 ← CY, Am−1 ← Am) × 1
(CY ← A7, A0 ← CY, Am+1 ← Am) × 1
×
×
×
×
ROL
A, 1
RORC
ROLC
A, 1
A, 1
Remark The instruction clock cycle is based on the CPU clock (fCPU), specified in the processor clock controller
register (PCC).
Preliminary Product Information
115
µPD789166Y, 789167Y, 789176Y, 789177Y
Mnemonic
SET1
Operand
Byte
Clock
Operation
Flag
Z
AC CY
saddr. bit
sfr. bit
A. bit
3
3
2
3
2
3
3
2
3
2
1
1
1
3
6
6
(saddr. bit) ← 1
sfr. bit ← 1
A. bit ← 1
4
PSW. bit
[HL]. bit
saddr. bit
sfr. bit
A. bit
6
PSW. bit ← 1
(HL). bit ← 1
(saddr. bit) ← 0
sfr. bit ← 0
A. bit ← 0
×
×
×
10
6
CLR1
6
4
PSW. bit
[HL]. bit
CY
6
PSW. bit ← 0
(HL). bit ← 0
CY ← 1
×
×
×
10
2
SET1
CLR1
NOT1
CALL
1
0
×
CY
2
CY ← 0
CY
2
CY ← CY
!addr16
6
(SP − 1) ← (PC + 3)H, (SP − 2) ← (PC + 3)L,
PC ← addr16, SP ← SP − 2
CALLT
[addr5]
1
8
(SP − 1) ← (PC + 1)H, (SP − 2) ← (PC + 1)L,
PCH ← (00000000, addr5 + 1),
PCL ← (00000000, addr5),
SP ← SP − 2
RET
1
1
6
8
PCH ← (SP + 1), PCL ← (SP),
SP ← SP + 2
RETI
PCH ← (SP + 1), PCL ← (SP),
PSW ← (SP + 2), SP ← SP + 3,
NMIS ← 0
R
R
R
PUSH
POP
PSW
rp
1
1
2
4
(SP − 1) ← PSW, SP ← SP − 1
(SP − 1) ← rpH, (SP − 2) ← rpL,
SP ← SP − 2
PSW
rp
1
1
4
6
PSW ← (SP), SP ← SP + 1
R
R
R
rpH ← (SP + 1), rpL ← (SP),
SP ← SP + 2
MOVW
BR
SP, AX
AX, SP
!addr16
$addr16
AX
2
2
3
2
1
8
6
6
6
6
SP ← AX
AX ← SP
PC ← addr16
PC ← PC + 2 + jdisp8
PCH ← A, PCL ← X
Remark The instruction clock cycle is based on the CPU clock (fCPU), specified in the processor clock controller
register (PCC).
116
Preliminary Product Information
µPD789166Y, 789167Y, 789176Y, 789177Y
Mnemonic
Operand
Byte
Clock
Operation
Flag
Z
AC CY
BC
$addr16
$addr16
$addr16
$addr16
2
2
2
2
4
6
6
PC ← PC + 2 + jdisp8 if CY = 1
PC ← PC + 2 + jdisp8 if CY = 0
PC ← PC + 2 + jdisp8 if Z = 1
PC ← PC + 2 + jdisp8 if Z = 0
BNC
BZ
6
BNZ
BT
6
saddr. bit, $addr16
10
PC ← PC + 4 + jdisp8
if (saddr. bit) = 1
sfr. bit, $addr16
A. bit, $addr16
4
3
4
4
10
8
PC ← PC + 4 + jdisp8 if sfr. bit = 1
PC ← PC + 3 + jdisp8 if A. bit = 1
PC ← PC + 4 + jdisp8 if PSW. bit = 1
PSW. bit, $addr16
saddr. bit, $addr16
10
10
BF
PC ← PC + 4 + jdisp8
if (saddr. bit) = 0
sfr. bit, $addr16
A. bit, $addr16
PSW. bit, $addr16
B, $addr16
4
3
4
2
10
8
PC ← PC + 4 + jdisp8 if sfr. bit = 0
PC ← PC + 3 + jdisp8 if A. bit = 0
PC ← PC + 4 + jdisp8 if PSW. bit = 0
10
6
DBNZ
B ← B − 1, then
PC ← PC + 2 + jdisp8 if B ≠ 0
C, $addr16
2
3
6
8
C ← C − 1, then
PC ← PC + 2 + jdisp8 if C ≠ 0
saddr, $addr16
(saddr) ← (saddr) − 1, then
PC ← PC + 3 + jdisp8 if (saddr) ≠ 0
NOP
EI
1
3
3
1
1
2
6
6
2
2
No Operation
IE ← 1 (Enable Interrupt)
IE ← 0 (Disable Interrupt)
Set HALT Mode
DI
HALT
STOP
Set STOP Mode
Remark The instruction clock cycle is based on the CPU clock (fCPU), specified in the processor clock controller
register (PCC).
Preliminary Product Information
117
µPD789166Y, 789167Y, 789176Y, 789177Y
11. ELECTRICAL CHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS (TA = 25°C)
Parameter
Supply voltage
Symbol
VDD
VI1
Conditions
Rated value
−0.3 to +7.0
−0.3 to VDD + 0.3
−0.3 to +13
−0.3 to VDD + 0.3
−10
Unit
V
Input voltage
Pins other than those for port 5
V
VI2
P50 to P53
N-ch open drain
V
Output voltage
VO
V
High-level output current
IOH
Each pin
mA
mA
mA
mA
°C
°C
Total for all pins
Each pin
−30
Low-level output current
IOL
30
Total for all pins
160
Operating ambient temperature
Storage temperature
TA
−40 to +85
−65 to +150
Tstg
Caution Absolute maximum ratings are rated values beyond which physical damage will be caused to
the product; if the rated value of any of the parameters in the above table is exceeded, even
momentarily, the quality of the product may deteriorate. Always use the product within its rated
values.
Remark The characteristic of a dual-function pin does not differ between the port function and the secondary
function, unless otherwise stated.
118
Preliminary Product Information
µPD789166Y, 789167Y, 789176Y, 789177Y
CHARACTERISTICS OF THE MAIN SYSTEM CLOCK OSCILLATION CIRCUIT
(TA = −40°C to +85°C, VDD = 1.8 to 5.5 V)
Resonator Recommended circuit
Parameter
Conditions
MIN. TYP. MAX. Unit
Ceramic
Oscillator frequency (fX)Note 1 VDD = oscillation voltage
range
1.0
1.0
5.0
MHz
X2
X1
resonator
C1
C2
Oscillation settling timeNotes 2, 3 Reset by RESET
215/fX
4
ms
Reset by an interrupt
Note 4
Crystal
Oscillator frequency (fX)Note 1
5.0
MHz
ms
X2
X1
C1
C2
Oscillation settling timeNote 2 VDD = 4.5 to 5.5 V
10
30
X1 input frequency (fX)Note 1
External
clock
1.0
85
5.0
MHz
ns
X1
X2
X1 input high/low level width
(tXH, tXL)
500
Notes 1. Only the characteristic of the oscillation circuit is indicated. See the description of the AC characteristic
for the instruction execution time.
2. Time required for oscillation to settle once a reset sequence ends or STOP mode is deselected.
3. Time after VDD reaches MIN. of the oscillation voltage range.
4. Bits 0 to 2 (OSTS0 to OSTS2) of the oscillation settling time selection register can be used to select
212/fX, 215/fX, or 217/fX.
Cautions 1. When using the main system clock oscillation circuit, observe the following conditions for
the wiring of that section enclosed in dotted lines in the above diagrams, so as to avoid the
influence of the wiring capacitance.
•
•
•
•
•
•
Keep the wiring as short as possible.
Do not allow signal wires to cross one another.
Keep the wiring away from wires that carry a high, non-stable current.
Keep the grounding point of the capacitors at the same level as VSS.
Do not connect the grounding point to a grounding wire that carries a high current.
Do not extract a signal from the oscillation circuit.
2. Before switching from the subsystem clock back to the main system clock, always allow
sufficient time for the oscillation to settle by specifying it in the program.
Preliminary Product Information
119
µPD789166Y, 789167Y, 789176Y, 789177Y
CHARACTERISTICS OF THE SUBSYSTEM CLOCK OSCILLATION CIRCUIT
(TA = −40°C to +85°C, VDD = 1.8 to 5.5 V)
Resonator Recommended circuit
Parameter
Conditions
MIN. TYP. MAX. Unit
Oscillator frequency (fXT)Note 1
Oscillation settling timeNote 2
XT1 input frequency (fXT)Note 1
Crystal
32
32.768
35
kHz
XT1
XT2
R
VDD = 4.5 to 5.5 V
1.2
2
s
C3
C4
10
35
External
clock
32
kHz
µs
XT1
XT2
XT1 input high/low level width
(tXTH, tXTL)
14.3
15.6
Notes 1. Only the characteristic of the oscillation circuit is indicated. See the description of the AC characteristic
for the instruction execution time.
2. Time required for oscillation to settle after VDD reaches the MIN. value of the oscillation voltage range.
Cautions 1. When using the subsystem clock oscillation circuit, observe the following conditions for the
wiring of that section enclosed in dotted lines in the above diagrams, so as to avoid the
influence of the wiring capacitance.
•
•
•
•
•
•
Keep the wiring as short as possible.
Do not allow signal wires to cross one another.
Keep the wiring away from wires that carry a high, non-stable current.
Keep the grounding point of the capacitors at the same level as VSS.
Do not connect the grounding point to a grounding wire that carries a high current.
Do not extract a signal from the oscillation circuit.
2. The subsystem clock oscillation circuit is designed to have a low amplification degree so as
to maintain a low current drain. Therefore, it is more likely to malfunction as a result of
noise than the main system clock oscillation circuit. When using the subsystem clock,
therefore, pay particularly careful attention to how it is wired.
120
Preliminary Product Information
µPD789166Y, 789167Y, 789176Y, 789177Y
DC CHARACTERISTICS (TA = −40°C to +85°C, VDD = 1.8 to 5.5 V)
Parameter
Symbol
IOL
Conditions
MIN.
TYP.
MAX.
Undefined
80
Unit
mA
mA
mA
mA
V
Each pin
All pins
Low-level output
current
IOH
Each pin
All pins
Undefined
−15
High-level output
current
VIH1
VIH2
VIH3
P00 to P05, P10, P11,
P60 to P67
VDD = 2.7 to 5.5 V
VDD = 2.7 to 5.5 V
VDD = 2.7 to 5.5 V
0.7VDD
VDD
High-level input
voltage
0.9VDD
VDD
V
P50 to P53
0.7VDD
12
V
0.9VDD
12
V
RESET,
0.8VDD
VDD
V
P20 to P26, P30 to P33
X1, X2
0.9VDD
VDD
V
VIH4
VIL1
VDD − 0.1
VDD
V
P00 to P05, P10, P11,
P60 to P67
VDD = 2.7 to 5.5 V
VDD = 2.7 to 5.5 V
VDD = 2.7 to 5.5 V
0
0.3VDD
0.1VDD
0.3VDD
0.1VDD
0.2VDD
0.1VDD
0.1
V
Low-level input
voltage
0
V
VIL2
P50 to P53
0
V
0
V
VIL3
RESET,
0
V
P20 to P26, P30 to P33
X1, X2
0
0
V
VIL4
VOH
V
VDD = 4.5 to 5.5 V,
VDD − 1.0
V
P00 to P05, P10, P11,
P20 to P22, P25, P26,
P30 to P33
High-level output
voltage
IOH = −1 mA
VDD = 1.8 to 5.5 V,
VDD − 0.5
V
V
IOH = −100 µA
Low-level output
voltage
VOL1
VOL2
LLIH1
Pins other than those for
port 5
VDD = 4.5 to 5.5 V,
IOL = 10 mA
1.0
0.5
1.0
0.4
3
VDD = 1.8 to 5.5 V,
V
IOL = 400 µA
P50 to P53
VDD = 4.5 to 5.5 V,
IOL = 10 mA
V
VDD = 1.8 to 5.5 V,
IOL = 1.6 mA
V
VIN = VDD
Pins other than the
X1 pin, X2 pin, or
those for port 5
µA
High-level input
leakage current
LLIH2
LLIH3
X1, X2
20
20
µA
µA
VIN = 12 V
VIN = 0 V
P50 to P53
(N-ch open drain)
Low-level input
leakage current
LLIL1
Pins other than the
X1 pin, X2 pin, or
those for port 5
−3
µA
LLIL2
LLIL3
X1, X2
−20
−30
µA
µA
P50 to P53
(N-ch open drain)
During input
instruction execution
Remark The characteristic of a dual-function pin does not differ between the port function and the secondary
function, unless otherwise stated.
Preliminary Product Information
121
µPD789166Y, 789167Y, 789176Y, 789177Y
DC CHARACTERISTICS (TA = −40°C to +85°C, VDD = 1.8 to 5.5 V)
Parameter
Symbol
ILOH
Conditions
MIN.
TYP.
MAX.
3
Unit
High-level output
leakage current
VOUT = VDD
VOUT = 0 V
µA
Low-level output
leakage current
ILOL
−3
200
60
µA
kΩ
kΩ
Software-specified
pull-up resistor
R1
VIN = 0 V, for pins other than those for P23, P24,
and P50 to P53
50
15
100
30
Mask option-
specified pull-up
resistor
R2
VIN = 0 V, P50 to P53
Note 3
IDD1
5.0-MHz crystal oscillation
operating mode
5.5
16.5
mA
Power supply
currentNote 1
VDD = 5.0 V ± 10%
0.7
0.4
1.2
0.5
0.3
100
70
2.1
1.2
3.6
1.5
0.9
200
140
100
55
mA
mA
mA
mA
mA
µA
µA
µA
µA
µA
µA
µA
µA
µA
mA
mA
mA
VDD = 3.0 V ± 10%
VDD = 2.0 V ± 10%
VDD = 5.0 V ± 10%
VDD = 3.0 V ± 10%
VDD = 2.0 V ± 10%
VDD = 5.0 V ± 10%
VDD = 3.0 V ± 10%
VDD = 2.0 V ± 10%
VDD = 5.0 V ± 10%
VDD = 3.0 V ± 10%
VDD = 2.0 V ± 10%
VDD = 5.0 V ± 10%
VDD = 3.0 V ± 10%
VDD = 2.0 V ± 10%
VDD = 5.0 V ± 10%
VDD = 3.0 V ± 10%
VDD = 2.0 V ± 10%
IDD2
IDD3
IDD4
IDD5
IDD6
5.0-MHz crystal oscillation
HALT mode
32.768-kHz crystal oscillation
operating modeNote 2
50
25
32.768-kHz crystal oscillation
HALT modeNote 2
5
25
2.5
0.1
0.05
0.05
6.1
1.3
1.0
12.5
30
32.768-kHz crystal stop
STOP mode
10
10
5.0-MHz crystal oscillation
A/D operating mode
18.3
2.9
3.0
Notes 1. The power supply current does not include AVREF, AVDD, or the port current (including the current
flowing through the built-in pull-up resistor).
2. When the main system clock is not running.
3. During high-speed mode operation (when the processor clock control register (PCC) is cleared to 00H.)
Remark The characteristic of a dual-function pin does not differ between the port function and the secondary
function, unless otherwise stated.
122
Preliminary Product Information
µPD789166Y, 789167Y, 789176Y, 789177Y
AC CHARACTERISTICS
(1) Basic operations (TA = −40°C to +85°C, VDD = 1.8 to 5.5 V)
Parameter
Cycle time
Symbol
TCY
Conditions
Operation based on the
main system clock
MIN.
0.4
TYP.
122
MAX.
Unit
VDD = 2.7 to 5.5 V
8
8
µs
µs
(minimum instruction
execution time)
1.6
Operation based on the subsystem clock
VDD = 2.7 to 5.5 V
µs
TI80 and TI81 input
high/low level width
tTIH, tTIL
0.1
1.8
0
µs
µs
MHz
kHz
fTI
VDD = 2.7 to 5.5 V
4
TI80 and TI81 input
frequency
0
275
Interrupt input
tINTH, tINTL INTP0 to INTP3
VDD = 2.7 to 5.5 V
10
20
10
20
µs
µs
µs
µs
high/low level width
RESET low level
width
tRSL
VDD = 2.7 to 5.5 V
TCY vs VDD (main system clock)
60
10
µ
Guaranteed
operating range
2.0
1.0
0.5
0.4
0.1
1
2
3
4
5
6
Supply voltage VDD [V]
Preliminary Product Information
123
µPD789166Y, 789167Y, 789176Y, 789177Y
SERIAL INTERFACE (TA = −40°C to +85°C, VDD = 1.8 to 5.5 V)
(a) Serial interface 20
(i) Three-wire serial I/O mode (SCK...Internal clock output)
Parameter
Symbol
tKCY1
Conditions
MIN.
800
TYP.
MAX.
Unit
SCK cycle time
VDD = 2.7 to 5.5 V
ns
ns
ns
ns
ns
ns
3,200
tKCY1/2−50
tKCY1/2−150
150
SCK high/low level
width
tKH1, tKL1 VDD = 2.7 to 5.5 V
tSIK1
tKSI1
tKSO1
VDD = 2.7 to 5.5 V
VDD = 2.7 to 5.5 V
SI setup time
(for SCK ↑)
500
SI hold time
400
ns
ns
ns
ns
(for SCK ↑)
600
Delay from SCK ↓
VDD = 2.7 to 5.5 V
0
250
R = 1 kΩ,
C = 100 pFNote
to SO output
0
1,000
Note R and C are the resistance and capacitance of the SO output line, respectively.
(ii) Three-wire serial I/O mode (SCK...External clock output)
Parameter
Symbol
tKCY2
Conditions
MIN.
800
3,200
400
1,600
100
150
400
600
0
TYP.
MAX.
Unit
SCK cycle time
VDD = 2.7 to 5.5 V
ns
ns
ns
ns
ns
ns
SCK high/low level
width
tKH2, tKL2 VDD = 2.7 to 5.5 V
tSIK2
tKSI2
tKSO2
VDD = 2.7 to 5.5 V
VDD = 2.7 to 5.5 V
SI setup time
(for SCK ↑)
SI hold time
ns
ns
ns
ns
(for SCK ↑)
Delay from SCK ↓
VDD = 2.7 to 5.5 V
300
R = 1 kΩ,
C = 100 pFNote
to SO output
0
1,000
Note R and C are the resistance and capacitance of the SO output line, respectively.
(iii) UART mode (internal clock output)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
78,125
19,531
Unit
bps
bps
Transfer rate
VDD = 2.7 to 5.5 V
124
Preliminary Product Information
µPD789166Y, 789167Y, 789176Y, 789177Y
(iv) UART mode (external clock input)
Parameter
Symbol
tKCY3
Conditions
MIN.
800
TYP.
MAX.
Unit
ASCK cycle time
VDD = 2.7 to 5.5 V
ns
ns
3,200
400
ASCK high/low
level width
tKH3, tKL3 VDD = 2.7 to 5.5 V
VDD = 2.7 to 5.5 V
tR, tF
ns
1,600
ns
bps
bps
Transfer rate
39,063
9,766
1
ASCK rising time,
falling time
µs
(b) SMB0
(i) DC characteristics
Parameter
Symbol
Conditions
MIN.
0.8VDD
0.9VDD
0
TYP.
MAX.
VDD
Unit
V
High-level input
voltage
VIH
SCL0, SDA0
2.7 V ≤ VDD < 5.5 V
(during hysteresis)
SCL0, SDA0
VDD
V
Low-level input
voltage
VIL
2.7 V ≤ VDD < 5.5 V
0.2VDD
0.1
V
(during hysteresis)
SCL0, SDA0
0
V
Low-level output
voltage
VOL
4.5 V ≤ VDD < 5.5 V
1.0
V
IOL = 10 mA
IOL = 400 µA
0.5
3
V
High-level input
leakage current
ILIH
SCL0, SDA0
SCL0, SDA0
VIN = VDD
µA
Low-level input
leakage current
ILIL
VIN = 0 V
−3
µA
(ii) DC characteristics (when the comparator is used)
Parameter Symbol Conditions
MIN.
0
TYP.
1.0
MAX.
5.5
Unit
V
Input range
Transfer level
V
SDA, VSCL 1.8 V ≤ VDD < 5.5 V
VISDA, VISCL
0.6
1.4
V
Preliminary Product Information
125
µPD789166Y, 789167Y, 789176Y, 789177Y
(iii) AC characteristics
Parameter
Symbol
SMB mode
I2C standard mode
I2C high-speed mode
Unit
MIN.
MAX.
100
−
MIN.
0
MAX.
100
−
MIN.
0
MAX.
400
−
SCL0 clock frequency
fCLK
tBUF
10
kHz
Bus free time (between stop-start
conditions)
4.7
4.7
1.3
µs
Hold timeNote 1
tHD:STA
4.0
−
4.0
−
0.6
−
µs
Start/restart condition setup time
Stop condition setup time
tSU:STA
tSU:STO
tHD:DAT
4.7
4.0
−
−
−
4.7
4.0
500
−
−
−
0.6
0.6
−
−
−
−
µs
µs
µs
Data
CBUS-compatible
master
hold time
0Note 2
900Note 3
SMB/IIC
300
250
−
−
−
ns
ns
100Note 4
Data setup time
tSU:DAT
−
250
−
SCL0 clock low level width
tLOW
tHIGH
tF
4.7
4.0
−
−
4.7
4.0
−
−
−
1.3
0.6
−
−
µs
µs
ns
ns
ns
SCL0 clock high level width
50
SCL0 and SDA0 signal falling time
SCL0 and SDA0 signal rising time
300
1,000
300
1,000
300
300
50
tR
−
−
−
Pulse width of spikes controlled by
the input filter
tSP
0
Time-out time
tTIMEOUT
25
35
25
−
−
−
−
−
−
−
−
ms
ms
SCL0 clock low level period total
extension time (slave)
tLOW:SEXT
−
Cumulative SCL0 clock low level
period total extension time
(master)
tLOW:MEXT
−
−
10
−
−
−
−
−
−
ms
pF
Capacitive load of each bus line
Cb
−
400
400
Notes 1. In the start condition, the first clock pulse is generated after this period of time.
2. To fill the undefined area of the SCL0 falling edge (at VIHmin. of the SCL0 signal), the device needs to
internally provide a hold time of at least 300 ns for the SDA0 signal.
3. If the device does not extend the low hold time (tLOW) of the SCL0 signal, the maximum data hold time
(tHD:DAT) only needs to be satisfied.
4. I2C high-speed mode can be used in SMB mode and I2C standard mode. In this case, the following
conditions must be satisfied:
•
•
When the device does not extend the low hold time of the SCL0 signal
tSU:DAT ≥ 250 ns
When the device extends the low hold time of the SCL0 signal
Before SCL0 is released (tRmax. + tSU:DAT = 1,000 + 250 = 1,250 ns: in SMB mode or I2C standard
mode), the next data bit must be sent onto the SDA0 line.
126
Preliminary Product Information
µPD789166Y, 789167Y, 789176Y, 789177Y
AC TIMING MEASUREMENT POINTS (except the X1 and XT1 inputs)
0.8VDD
0.2VDD
0.8VDD
0.2VDD
Measurement
points
CLOCK TIMING
1/f
X
t
XL
t
XH
V
IH4 (MIN.)
X1 input
VIL4 (MAX.)
1/fXT
t
XTL
t
XTH
V
IH5 (MIN.)
XT1 input
VIL5 (MAX.)
TI TIMING
t
TIL0, tTIL1
tTIH0, tTIH1
TI80, TI81
Preliminary Product Information
127
µPD789166Y, 789167Y, 789176Y, 789177Y
INTERRUPT INPUT TIMING
t
INTL
t
INTH
INTP0-INTP3
RESET INPUT TIMING
t
RSL
RESET
128
Preliminary Product Information
µPD789166Y, 789167Y, 789176Y, 789177Y
SERIAL TRANSFER TIMING
Three-Wire Serial I/O Mode:
tKCYm
tKLm
tKHm
SCK20
tSIKm
tKSIm
Input data
SI20
tKSOm
Output data
SO20
SS20
tKDS
tKAS
Output data
SO20
m = 1, 2
UART Mode (External Clock Input):
t
KCY3
t
KL3
t
KH3
t
R
t
F
ASCK20
Preliminary Product Information
129
µPD789166Y, 789167Y, 789176Y, 789177Y
SMB Mode:
t
LOW
t
R
SCL0
t
F
t
HD:DAT
t
HIGH
t
SU:STA
t
HD:STA
t
SP
t
SU:STO
t
SU:DAT
tHD:STA
SDA0
t
BUF
Restart
condition
Stop
condition
Stop
condition
Start
condition
130
Preliminary Product Information
µPD789166Y, 789167Y, 789176Y, 789177Y
8-BIT A/D CONVERTER CHARACTERISTICS (TA = −40°C to +85°C, AVDD = VDD = 1.8 to 5.5 V, AVSS = VSS = 0 V)
(For µPD789166Y and µPD789167Y only)
Parameter
Symbol
Conditions
MIN.
8
TYP.
8
MAX.
Unit
bit
Resolution
8
1
Total errorNote
4.5 V ≤ AVDD ≤ 5.5 V
0.5
LSB
2.7 V ≤ AVDD < 4.5 V
1.8 V ≤ AVDD < 2.7 V
4.5 V ≤ AVDD ≤ 5.5 V
2.7 V ≤ AVDD < 4.5 V
1.8 V ≤ AVDD < 2.7 V
1
1.75
LSB
LSB
µs
Undefined Undefined
Undefined
Conversion time
tCONV
Undefined
Undefined
Undefined
0
Undefined
µs
Undefined
µs
V
Analog input
voltage
VIAN
AVREF + 0.3
Reference voltage
AVREF
0
AVDD + 0.3
V
Note No quantization error (±1/2 LSB) is included.
10-BIT A/D CONVERTER CHARACTERISTICS (TA = −40°C to +85°C, AVDD = VDD = 1.8 to 5.5 V, AVSS = VSS = 0 V)
(For µPD789176Y and µPD789177Y only)
Parameter
Symbol
Conditions
MIN.
10
TYP.
10
MAX.
10
Unit
bit
Resolution
Total errorNote
4.5 V ≤ AVDD ≤ 5.5 V
2
4
LSB
2.7 V ≤ AVDD < 4.5 V
1.8 V ≤ AVDD < 2.7 V
4.5 V ≤ AVDD ≤ 5.5 V
2.7 V ≤ AVDD < 4.5 V
1.8 V ≤ AVDD < 2.7 V
4
7
LSB
LSB
µs
Undefined Undefined
Undefined
Conversion time
tCONV
Undefined
Undefined
Undefined
0
Undefined
µs
Undefined
µs
V
Analog input
voltage
VIAN
AVREF + 0.3
Reference voltage
AVREF
0
AVDD + 0.3
V
Note No quantization error (±1/2 LSB) is included.
DATA MEMORY STOP MODE LOW POWER SUPPLY VOLTAGE DATA HOLD CHARACTERISTICS
(T
A
= −40°C to +85°C)
Parameter
Symbol
VDDDR
Conditions
MIN.
1.8
TYP.
MAX.
5.5
Unit
V
Data hold supply
voltage
Release signal set time
tSREL
0
µs
Preliminary Product Information
131
µPD789166Y, 789167Y, 789176Y, 789177Y
DATA HOLD TIMING (STOP mode release by RESET)
Internal reset operation
STOP mode
Data hold mode
VDD
VDDDR
t
SREL
STOP instruction execution
RESET
132
Preliminary Product Information
µPD789166Y, 789167Y, 789176Y, 789177Y
12. PACKAGE DRAWINGS
42PIN PLASTIC SHRINK DIP (600 mil)
42
22
1
21
A
K
L
F
B
R
M
C
D
M
N
NOTES
ITEM MILLIMETERS
INCHES
1) Each lead centerline is located within 0.17 mm (0.007 inch) of
its true position (T.P.) at maximum material condition.
A
B
C
39.13 MAX.
1.78 MAX.
1.778 (T.P.)
1.541 MAX.
0.070 MAX.
0.070 (T.P.)
2) Item "K" to center of leads when formed parallel.
+0.004
0.020
D
0.50±0.10
–0.005
F
G
H
I
0.9 MIN.
3.2±0.3
0.035 MIN.
0.126±0.012
0.020 MIN.
0.170 MAX.
0.200 MAX.
0.600 (T.P.)
0.520
0.51 MIN.
4.31 MAX.
5.08 MAX.
15.24 (T.P.)
13.2
J
K
L
+0.004
0.010
+0.10
0.25
M
–0.003
–0.05
N
R
0.17
0.007
0~15°
0~15°
P42C-70-600A-1
Preliminary Product Information
133
µPD789166Y, 789167Y, 789176Y, 789177Y
44 PIN PLASTIC QFP ( 10)
A
B
23
33
34
detail of lead end
22
S
C
D
R
Q
12
11
44
1
F
J
M
G
H
I
P
K
M
ITEM MILLIMETERS
INCHES
N
S
L
+0.008
0.520
S
A
B
C
D
13.2±0.2
10.0±0.2
10.0±0.2
13.2±0.2
–0.009
+0.008
–0.009
0.394
0.394
0.520
NOTE
+0.008
–0.009
1. Controlling dimension
millimeter.
+0.008
–0.009
2. Each lead centerline is located within 0.16 mm (0.007 inch) of
its true position (T.P.) at maximum material condition.
F
1.0
1.0
0.039
0.039
G
+0.08
+0.003
–0.004
H
0.37
0.015
–0.07
I
0.16
0.007
J
0.8 (T.P.)
0.031 (T.P.)
K
L
1.6±0.2
0.063±0.008
+0.009
0.031
0.8±0.2
–0.008
+0.002
0.007
+0.06
0.17
M
–0.003
–0.05
N
P
0.10
0.004
+0.005
0.106
2.7±0.1
–0.004
Q
R
0.125±0.075
0.005±0.003
+7°
3°
+7°
3°
–3°
–3°
S
3.0 MAX.
0.119 MAX.
S44GB-80-3BS-1
134
Preliminary Product Information
µPD789166Y, 789167Y, 789176Y, 789177Y
48 PIN PLASTIC TQFP (FINE PITCH) ( 7)
A
B
36
37
25
24
detail of lead end
48
G
13
12
1
M
H
I
J
K
N
L
NOTE
ITEM MILLIMETERS
INCHES
Each lead centerline is located within 0.10 mm (0.004 inch) of
its true position (T.P.) at maximum material condition.
+0.009
A
B
C
D
9.0±0.2
7.0±0.2
7.0±0.2
9.0±0.2
0.354
0.276
0.276
0.354
–0.008
+0.008
–0.009
+0.008
–0.009
+0.009
–0.008
F
0.75
0.75
0.030
0.030
G
+0.05
H
0.22
0.009±0.002
–0.04
I
0.10
0.004
J
0.5 (T.P.)
0.020 (T.P.)
+0.009
0.039
K
L
1.0±0.2
–0.008
+0.008
0.020
0.5±0.2
–0.009
+0.055
M
0.145
0.10
0.006±0.002
–0.045
N
P
0.004
+0.005
0.039
1.0±0.1
–0.004
Q
R
S
0.1±0.05
0.004±0.002
+7°
3°
+7°
3°
–3°
–3°
1.27 MAX.
0.050 MAX.
S48GA-50-9EU-1
Preliminary Product Information
135
µPD789166Y, 789167Y, 789176Y, 789177Y
APPENDIX A DEVELOPMENT TOOLS
The following development tools are available for developing systems using the µPD789166Y, µPD789167Y,
µPD789176Y, and µPD789177Y.
LANGUAGE PROCESSING SOFTWARE
RA78K0SNotes 1, 2, 3
Assembler package common to the 78K/0S series
CC78K0SNotes 1, 2, 3
C compiler package common to the 78K/0S series
DF789177Notes 1, 2, 3, 5
Device file for the µPD789167Y and µPD789177Y sub-series
CC78K0S-LNotes 1, 2, 3, 5
C compiler library source file common to the 78K/0S series
FLASH MEMORY WRITE TOOLS
Flashpro llNote 4
Dedicated flash writer (formerly, Flashpro)
FA-42CUNote 4
Flash memory write adapter
FA-44GBNote 4
FA-48GANotes 4, 5
DEBUGGING TOOLS
IE-78K0S-NS
This in-circuit emulator is used to debug hardware or software when application
systems which use the 78K/0S series are developed. The IE-78K0S-NS supports the
integrated debugger (ID78K0S-NS). The IE-78K0S-NS is used in combination with an
interface adapter for connection to an AC adapter, emulation probe, or host machine.
In-circuit emulator
IE-70000-MC-PS-B
AC adapter
This adapter is used to supply power from a 100-VAC outlet.
IE-70000-98-IF-C
Interface adapter
This adapter is required when a PC-9800 series computer (other than a notebook type)
is used as the host machine for the IE-78K0S-NS.
IE-70000-CD-IF
PC card/interface
These PC card and interface cable are required when a PC-9800 series computer is
used as the host machine for the IE-78K0S-NS.
IE-70000-PC-IF-C
Interface adapter
This adapter is required when an IBM PC/AT or compatible is used as the host
machine for the IE-78K0S-NS.
IE-789177-NS-EM1Note 5
Emulation board
This board is used to emulate the peripheral hardware specific to the device. The
IE-789198-NS-EM1 is used in combination with the in-circuit emulator.
NP-42CUNote 4
This probe is used to connect an in-circuit emulator to the target system. The probe is
dedicated to the 42-pin plastic shrink DIP.
Emulation probe
NP-44GBNote 4
This probe is used to connect an in-circuit emulator to the target system. The probe is
dedicated to the 44-pin plastic QFP.
Emulation probe
NP-48GANotes 4, 5
Emulation probe
This probe is used to connect an in-circuit emulator to the target system. The probe is
dedicated to the 48-pin plastic TQFP.
SM78K0SNotes 1, 2
System simulator common to all 78K/0S series units
DF789177Notes 1, 2, 5
Device file for the µPD789167Y and µPD789177Y sub-series
136
Preliminary Product Information
µPD789166Y, 789167Y, 789176Y, 789177Y
REAL-TIME OS
MX78K0SNotes 1, 2, 5
OS for the 78K/0S series
Notes 1. Based on the PC-9800 series (MS-DOS + Windows
)
2. Based on the IBM PC/AT and compatibles (PC DOS /IBM DOS /MS-DOS + Windows)
3. Based on the HP9000 series 700
(HP-UX ), SPARCstation (SunOS ), and NEWS
(NEWS-OS
)
4. Product manufactured by and available from Naito Densei Machida Mfg. Co., Ltd. (044-822-3813).
5. Under development
Remark The RA78K0S, CC78K0S, and SM78K0S can be used in combination with the DF789177.
Preliminary Product Information
137
µPD789166Y, 789167Y, 789176Y, 789177Y
APPENDIX B RELATED DOCUMENTS
DOCUMENTS RELATED TO DEVICES
Document name
Document No.
Japanese
U13216J
English
This manual
To be created
To be created
U11047E
−
µPD789166Y, 789167Y, 789176Y, 789177Y Preliminary Product Information
µPD78F9177Y Preliminary Product Information
µPD789177Y Sub-Series User’s Manual
U13210J
To be created
U11047J
78K/0 Series User’s Manual, Instruction
78K/0S Series Instruction Summary Sheet
78K/0S Series Instruction Set
To be created
To be created
−
DOCUMENTS RELATED TO DEVELOPMENT TOOLS (USER’S MANUAL)
Document name
Document No.
English
Japanese
U11622J
RA78K0S Assembler Package
Operation
Language
U11622E
U11599J
U11599E
U11623E
Structured Assembly
Language
U11623J
CC78K/0S C Compiler
Operation
Language
Reference
U11816J
U11817J
U11489J
U10092J
U11816E
U11817E
U11489E
U10092E
SM78K0S System Simulator Windows Base
SM78K Series System Simulator
External Parts User Open
Interface Specifications
ID78K0S-NS Windows Base
Reference
U12901J
To be created
DOCUMENTS RELATED TO SOFTWARE TO BE INCORPORATED INTO THE PRODUCT
(USER’S MANUAL)
Document name
Document No.
Japanese
U12938J
English
OS for 78K/0S Series MX78K0S
Fundamental
U12938E
Caution The above documents may be revised without notice. Use the latest versions when you design
application systems.
138
Preliminary Product Information
µPD789166Y, 789167Y, 789176Y, 789177Y
OTHER DOCUMENTS
Document name
Document No.
Japanese
C10943X
English
IC PACKAGE MANUAL
Semiconductor Device Mounting Technology Manual
C10535J
C11531J
C10983J
C11892J
C12769J
U11416J
C10535E
Quality Grades on NEC Semiconductor Device
C11531E
C10983E
C11892E
−
NEC Semiconductor Device Reliability/Quality Control System
Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD)
Semiconductor Device Quality Control/Reliability Handbook
Guide for Products Related to Microcomputer: Other Companies
−
Caution The above documents may be revised without notice. Use the latest versions when you design
application systems.
Preliminary Product Information
139
µPD789166Y, 789167Y, 789176Y, 789177Y
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note: Strong electric field, when exposed to a MOS device, can cause destruction
of the gate oxide and ultimately degrade the device operation. Steps must
be taken to stop generation of static electricity as much as possible, and
quickly dissipate it once, when it has occurred. Environmental control must
be adequate. When it is dry, humidifier should be used. It is recommended
to avoid using insulators that easily build static electricity. Semiconductor
devices must be stored and transported in an anti-static container, static
shielding bag or conductive material. All test and measurement tools
including work bench and floor should be grounded. The operator should
be grounded using wrist strap. Semiconductor devices must not be touched
with bare hands. Similar precautions need to be taken for PW boards with
semiconductor devices on it.
2 HANDLING OF UNUSED INPUT PINS FOR CMOS
Note: No connection for CMOS device inputs can be cause of malfunction. If no
connection is provided to the input pins, it is possible that an internal input
level may be generated due to noise, etc., hence causing malfunction. CMOS
devices behave differently than Bipolar or NMOS devices. Input levels of
CMOS devices must be fixed high or low by using a pull-up or pull-down
circuitry. Each unused pin should be connected to VDD or GND with a
resistor, if it is considered to have a possibility of being an output pin. All
handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3 STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note: Power-on does not necessarily define initial status of MOS device. Production
process of MOS does not define the initial operation status of the device.
Immediately after the power source is turned ON, the devices with reset
function have not yet been initialized. Hence, power-on does not guarantee
out-pin levels, I/O settings or contents of registers. Device is not initialized
until the reset signal is received. Reset operation must be executed imme-
diately after power-on for devices having reset function.
140
Preliminary Product Information
µPD789166Y, 789167Y, 789176Y, 789177Y
EEPROM is a trademark of NEC Corporation.
MS-DOS and Windows are either registered trademarks or trademarks of Microsoft Corporation in the United
States and/or other countries.
IBM DOS, PC/AT, and PC DOS are trademarks of IBM Corporation.
HP9000 series 700 and HP-UX are trademarks of Hewlett-Packard Company.
SPARCstation is a trademark of SPARC International, Inc.
SunOS is a trademark of Sun Microsystems, Inc.
NEWS and NEWS-OS are trademarks of SONY Corporation.
Preliminary Product Information
141
µPD789166Y, 789167Y, 789176Y, 789177Y
Regional Information
Some information contained in this document may vary from country to country. Before using any NEC
product in your application, pIease contact the NEC office in your country to obtain a list of authorized
representatives and distributors. They will verify:
•
•
•
•
•
Device availability
Ordering information
Product release schedule
Availability of related technical literature
Development environment specifications (for example, specifications for third-party tools and
components, host computers, power plugs, AC supply voltages, and so forth)
•
Network requirements
In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary
from country to country.
NEC Electronics Inc. (U.S.)
Santa Clara, California
Tel: 408-588-6000
800-366-9782
NEC Electronics (Germany) GmbH NEC Electronics Hong Kong Ltd.
Benelux Office
Hong Kong
Eindhoven, The Netherlands
Tel: 040-2445845
Tel: 2886-9318
Fax: 2886-9022/9044
Fax: 408-588-6130
800-729-9288
Fax: 040-2444580
NEC Electronics Hong Kong Ltd.
Seoul Branch
Seoul, Korea
Tel: 02-528-0303
Fax: 02-528-4411
NEC Electronics (France) S.A.
Velizy-Villacoublay, France
Tel: 01-30-67 58 00
NEC Electronics (Germany) GmbH
Duesseldorf, Germany
Tel: 0211-65 03 02
Fax: 01-30-67 58 99
Fax: 0211-65 03 490
NEC Electronics Singapore Pte. Ltd.
United Square, Singapore 1130
Tel: 65-253-8311
NEC Electronics (France) S.A.
Spain Office
Madrid, Spain
NEC Electronics (UK) Ltd.
Milton Keynes, UK
Tel: 01908-691-133
Fax: 65-250-3583
Tel: 01-504-2787
Fax: 01908-670-290
Fax: 01-504-2860
NEC Electronics Taiwan Ltd.
Taipei, Taiwan
Tel: 02-719-2377
NEC Electronics Italiana s.r.1.
Milano, Italy
Tel: 02-66 75 41
NEC Electronics (Germany) GmbH
Scandinavia Office
Taeby, Sweden
Fax: 02-719-5951
Fax: 02-66 75 42 99
Tel: 08-63 80 820
NEC do Brasil S.A.
Cumbica-Guarulhos-SP, Brasil
Tel: 011-6465-6810
Fax: 08-63 80 388
Fax: 011-6465-6829
J98. 2
142
Preliminary Product Information
µPD789166Y, 789167Y, 789176Y, 789177Y
[MEMO]
Preliminary Product Information
143
µPD789166Y, 789167Y, 789176Y, 789177Y
The export of this product from Japan is regulated by the Japanese government. To export this product may be prohibited
without governmental license, the need for which must be judged by the customer. The export or re-export of this product
from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales
representative.
Caution This product contains an I2C bus interface circuit.
When using the I2C bus interface, notify its use to NEC when ordering custom code. NEC can
guarantee the following only when the customer informs NEC of the use of the interface:
Purchase of NEC I2C components conveys a license under the Philips I2C Patent Rights to use
these components in an I2C system, provided that the system conforms to the I2C Standard
Specification as defined by Philips.
No part of this document may be copied or reproduced in any form or by any means without the prior written
consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this
document.
NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual
property rights of third parties by or arising from use of a device described herein or any other liability arising
from use of such device. No license, either express, implied or otherwise, is granted under any patents,
copyrights or other intellectual property rights of NEC Corporation or others.
While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,
the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or
property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety
measures in its design, such as redundancy, fire-containment, and anti-failure features.
NEC devices are classified into the following three quality grades:
"Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on
a customer designated "quality assurance program" for a specific application. The recommended applications
of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each
device before using it in a particular application.
Standard: Computers, office equipment, communications equipment, test and measurement equipment,
audio and visual equipment, home electronic appliances, machine tools, personal electronic
equipment and industrial robots
Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems or medical equipment for life support, etc.
The quality grade of NEC devices is "Standard" unless otherwise specified in NEC’s Data Sheets or Data Books.
If customers intend to use NEC devices for applications other than those specified for Standard quality grade,
they should contact an NEC sales representative in advance.
Anti-radioactive design is not implemented in this product.
M4 96. 5
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