UPD78CP18GF(A)-3BE [RENESAS]
UPD78CP18GF(A)-3BE;
| 型号： | UPD78CP18GF(A)-3BE |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | UPD78CP18GF(A)-3BE 光电二极管 |
| 文件： | 总52页 (文件大小：464K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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DATA SHEET
MOS INTEGRATED CIRCUIT
µPD78CP18(A)
8-BIT SINGLE-CHIP MICROCOMPUTER
DESCRIPTION
The µPD78CP18(A) is a version of theµPD78C18(A) in which the internal mask ROM is replaced by one-time PROM.
The one-time PROM version can be programmed once only by users, and is ideally suited for small-scall of many
differnt products, and rapid development and time-to-market of a new product.
The detailed functions are descrived in the following user's manual. Read this manual before starting design
work.
87AD series µPD78C18 user's manual: IEU-1314
FEATURES
•
•
•
High reliability compared to the µPD78CP18
Compatible with the µPD78C11A(A), 78C12A(A), 78C14(A), 78C18(A)
Internal PROM: 32768 W × 8
• Internal PROM capacity can be changed by software to conform to the µPD78C11A(A), 78C12A(A), 78C14(A),
78C18(A).
•
•
•
PROM programming characteristics: µPD27C256A compatible
Power supply voltage range: 5 V ± 10 %
Supports QTOP microcomputer
★
Remark
QTOP microcomputer is the generic name of NEC's single-chip microcomputers for which NEC
provides total service including writing, marking, screening, and inspection.
ORDERING INFORMATION
Part Number
Package
Internal ROM
µPD78CP18GF(A)-3BE
µPD78CP18GQ(A)-36
64-pin plastic QFP (14 × 20 mm)
One-time PROM
One-time PROM
64-pin plastic QUIP
QUALITY GRADE
Part Number
Quality Grade
µPD78CP18GF(A)-3BE
µPD78CP18GQ(A)-36
Special
Special
Please refer to “Quality grade on NEC Semiconductor Devices” (Document number IEI-1209) published by
NEC Corporation to know the specification of quality grade on the devices and its recommended applications.
The information in this document is subject to change without notice.
The mark ★ shows major revised points.
Document No. IC-3233A
(O. D. No. IC-8702A)
Date Published March 1995 P
Printed in Japan
1
1993
©
µPD78CP18(A)
PIN CONFIGURATION (TOP VIEW)
A0/PA0
A1/PA1
A2/PA2
A3/PA3
A4/PA4
A5/PA5
A6/PA6
A7/PA7
PB0
1
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
V
DD
2
STOP/VPP
PD7/O7
PD6/O6
PD5/O5
PD4/O4
PD3/O3
PD2/O2
PD1/O1
PD0/O0
PF7
3
4
5
6
7
8
9
PB1
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
PB2
PB3
PF6/A14
PF5/A13
PF4/A12
PF3/A11
PF2/A10
PF1
µ
PB4
PB5
CE/PB6
OE/PB7
PC0/T
PC1/R
X
D
D
X
PF0/A8
ALE
PC2/SCK
PC3/INT2
PC4/TO
PC5/CI
PC6/CO0
PC7/CO1
A9/NMI
INT1
WR
RD
AVDD
V
AREF
AN7
AN6
AN5
AN4
AN3
AN2
AN1
AN0
AVSS
MODE1
RESET
MODE0
X2
X1
V
SS
2
µPD78CP18(A)
51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
52
O3/PD3
O4/PD4
O5/PD5
O6/PD6
O7/PD7
PP/STOP
32
31
30
29
28
27
26
25
24
23
22
21
20
AN4
AN3
AN2
AN1
AN0
AVSS
53
54
55
56
57
58
59
60
61
62
63
64
V
V
DD
V
SS
µPD78CP18GF(A)-3BE
A0/PA0
A1/PA1
A2/PA2
A3/PA3
A4/PA4
A5/PA5
X1
X2
MODE0
RESET
MODE1
INT1
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19
3
PF7/AB15
8
16
X1
X2
PF6/A14/AB14
to PF2/A10/AB10
PF1/AB9
OSC
LATCH
INC/DEC
PC
5
8
8
8
PF0/A8/AB8
SP
15
PC0/TXD
EA
8
8
SERIAL I/O
PC1/RXD
V
B
D
H
A
C
E
L
8
8
PC2/SCK
MAIN
G.R
16
PD7/O7/AD7
to PD0/O0/AD0
10
A9/NMI
INT1
PROM
(32-KBYTE)
EA'
Note
V'
B'
D'
H'
A'
C'
E'
L'
INT.
CONTROL
DATA
MEMORY
(1-KBYTE)
ALT
G.R
8
8
8
PC7 to PC0
4
BUFFER
8/16
PC3/INT2/TI
PC4/TO
8
8
TIMER
8
8
OE/PB7
CE/PB6
8
INTERNAL DATA BUS
8
PC5/CI
PC6/CO0
PC7/CO1
16
16
LATCH
6
8
PB5 to PB0
6
TIMER/EVENT
COUNTER
8
LATCH
PSW
INST. REG
AN7 to AN0
8
16
16
PA7/A7 to PA0/A0
A/D
CONVERTER
8
V
AREF
INST.
DECODER
ALU
(8/16)
AVDD
AVSS
16
READ/WRITE
CONTROL
SYSTEM
CONTROL
STANDBY
CONTROL
µ
RD
WR
ALE MODE1 MODE0 RESET
VPP/STOP
VDD
VSS
Note Can be used only when RAE bit of MM register is 1.
External memory is needed in case of 0.
µPD78CP18(A)
DIFFERENCES BETWEEN THE µPD78CP18(A) AND µPD78CP18
Product
Name
µPD78CP18(A)
µPD78CP18
Item
Special
Quality grade
Standard
Electrical
specifications
Input leakage current
AN7 to AN0; ±10 µA (MAX.)
Input leakage current
AN7 to AN0: ±1 µA (MAX.)
• 64-pin plastic QFP (14 × 20 mm)
• 64-pin plastic QUIP
Package
• 64-pin plastic shrink DIP (750 mil)
• 64-pin plastic QUIP
• 64-pin plastic QFP (14 × 20 mm)
• 64-pin ceramic shrink DIP with
window (750 mil)
• 64-pin ceramic WQFN
5
µPD78CP18(A)
CONTENTS
1. LIST OF PORT FUNCTIONS .......................................................................................................................7
1.1 PORT FUNCTIONS ...............................................................................................................................................7
1.2 NON-PORT FUNCTIONS (IN NORMAL OPERATION) .....................................................................................8
1.3 NON-PORT FUNCTIONS (DURING PROM WRITE/VERIFY AND READ).....................................................10
1.4 HANDLING OF UNUSED PINS .........................................................................................................................10
2. MEMORY CONFIGURATION....................................................................................................................11
3. MEMORY EXTENSION .............................................................................................................................16
3.1 MODE PINS ........................................................................................................................................................16
3.2 MEMORY MAPPING REGISTER (MM) ............................................................................................................17
4. PROM PROGRAMMING ...........................................................................................................................20
4.1 PROM PROGRAMMING OPERATING MODES...............................................................................................21
4.2 PROM WRITING PROCEDURE .........................................................................................................................22
4.3 PROM READING PROCEDURE .........................................................................................................................23
5. SCREENING OF ONE-TIME PROM VERSIONS......................................................................................24
6. ELECTRICAL SPECIFICATIONS................................................................................................................25
7. CHARACTERISTIC CURVES (REFERENCE VALUE) ..............................................................................39
8. PACKAGE DRAWINGS .............................................................................................................................42
9. RECOMMENDED SOLDERING CONDITIONS ........................................................................................44
10. DIFFERENCES BETWEEN THE µPD78CP18(A) AND µPD78C18(A) .....................................................45
APPENDIX. DEVELOPMENT TOOLS ..........................................................................................................46
6
µPD78CP18(A)
1. LIST OF PORT FUNCTIONS
1.1 PORT FUNCTIONS
Pin Name
I/O
Function
PA7 to PA0
(Port A)
Input/Output
8-bit input-output port, which can specify input/output bit-wise.
PB7 to PB0
(Port B)
PC7 to PC0
(Port C)
8-bit input-output port, which can specify input/output in byte units.
8-bit input-output port, which can specify input/output bit-wise.
PD7 to PD0
(Port D)
PF7 to PF0
(Port F)
Remark
These port pins have alternate function pins as shown in 1.2 “NON-PORT FUNCTIONS (IN NORMAL
OPERATION)” and 1.3 “NON-PORT FUNCTIONS (DURING PROM WRITE/VERIFY AND READ)”.
7
µPD78CP18(A)
1.2 NON-PORT FUNCTIONS (IN NORMAL OPERATION)
Alternate
Function
Pin Name
I/O
Output
Function Pin
PC0
TXD
Serial data output pin
Serial data input pin
(Transmit Data)
PC1
PC2
Input
RXD
(Receive Data)
Serial clock input/output pin. Output when internal clock is used, input
when external clock is used.
Input/output
SCK
(Serial Clock)
Edge trigger (falling edge) maskable interrupt input pin
Timer external clock input pin
INT2
(Interrupt Request)
Input
Input
PC3
TI
(Timer Input)
Input
AC input zero-cross detection pin
Zero-cross
TO
Output
PC4
PC5
During timer count time, square wave with one internal clock cycle as
one half cycle is output.
(Timer Output)
Input
Timer/event counter external pulse input pin
CI
(Counter Input)
CO0 and CO1
(Counter
Square wave output programmable by timer/event counter.
Output
PC6 and PC7
PD7 to PD0
PF7 to PF0
Output 0, 1)
AD7 to AD0
(Address/Data
Bus 7 to 0)
Multiplexed address/data bus when external memory is used
Address bus when external memory is used
Input/output
AB15 to AB8
(Address Bus
Output
Output
15 to 8)
Strobe signal which is output for write operation of external memory. It
becomes high in any cycle other than the data write machine cycle of
external memory. When RESET signal is either low or in the hardware
STOP mode, this signal becomes high-impedance.
WR
(Write Strobe)
Output
Output
RD
Strobe signal which is output for read operation of external memory. It
becomes high in any cycle other than the data read machine cycle of
external memory. When RESET signal is either low or in the hardware STOP
mode, this signal becomes output high-impedance.
(Read Strobe)
ALE
Strobe signal to latch externally the lower address information which is
output to PD7 to PD0 pins to access external memory. When RESET signal
is either low or in the hardware STOP mode, this signal becomes high-
impedance.
(Address
Latch Enable)
Set MODE0 pin to “0” (low level), and MODE1 pin to “1” (high level)Note
Input
Input/output
MODE0
MODE1
(Mode)
Input
Non-maskable interrupt input pin of the edge trigger (falling edge)
NMI
(Non-Maskable
Interrupt)
Note Pull-up. Pull-up resister R is 4 [kΩ] ≤ R ≤ 0.4 tCYC [kΩ] (tCYC is ns unit).
8
µPD78CP18(A)
Alternate
Function
Pin Name
I/O
Function Pin
Input
INT1
(Interrupt
Request)
A maskable interrupt input pin of the edge trigger (rising edge). Also, it can
be used as a zero-cross detection pin for AC input.
8 pins of analog input to A/D converter. AN7 to AN4 can be used as edge
detection (falling edge) input.
Input
Input
AN7 to AN0
(Analog Input)
A common pin serving both as a reference voltage input pin for A/D
converter and as a control pin for A/D converter operation.
VAREF
(Reference
Voltage)
Power supply pin for A/D converter.
GND pin for A/D converter.
AVDD
(Analog VDD)
AVSS
(Analog VSS)
X1, X2
(Crystal)
Crystal connection pins for system clock oscillation. X1 should be input
when a clock is supplied from outside. Inverted clock of X1 should be input
in X2.
Input
Input
Low-level active system reset input.
RESET
(Reset)
Hardware STOP mode control signal input pin. When the low level is input
to this pin, the oscillation stops.
STOP
(Stop)
VDD
Positive power supply pin.
GND pin.
VSS
9
µPD78CP18(A)
1.3 NON-PORT FUNCTIONS (DURING PROM WRITE/VERIFY AND READ)
Alternate
Function
Pin Name
A7 to A0
I/O
Function Pin
PA7 to PA0
Input
Input
Input
Address lower 8 bit input pins
Chip enable signal input pin
Output enable signal input pin
Data input/output pins
CE
PB6
PB7
OE
Input/output
Input
PD7 to PD0
O7 to O0
A14 to A10
A8
PF6 to PF2
PF0
Address higher 7 bit input pins
Input
Input
NMI
A9
MODE0
MODE1
Set MODE0 pin to “1” (high level), and MODE1 pin to “0” (low level).
Set to “0” (low level).
Input
RESET
VPP
High-voltage application pin
STOP
"1" (high level) is input when EPROM is read.
1.4 HANDLING OF UNUSED PINS
Pin
Recommended Connection
PA7 to PA0
PB7 to PB0
PC7 to PC0
PD7 to PD0
PF7 to PF0
Connect to VSS or VDD via resistor.
RD
WR
ALE
Leave open.
Connect to VDD.
STOP
INT1, NMI
AVDD
Connect to VSS or VDD.
Connect to VDD.
VAREF
AVSS
Connect to VSS.
AN7 to AN0
Connect to AVSS or AVDD.
10
µPD78CP18(A)
2. MEMORY CONFIGURATION
The µPD78CP18(A) memory can operate in the following 4 modes according to the mode specification.
● µPD78C11A mode (see Figure 2-1)
● µPD78C12A mode (see Figure 2-2)
● µPD78C14 mode (see Figure 2-3)
● µPD78C18 mode (see Figure 2-4)
In addition, the internal PROM and internal RAM address ranges can be specified for efficient mapping of external
memory (excluding PROM) (see 3.2 “MEMORY MAPPING REGISTER (MM)”).
The vector area and call table area are common to all modes.
Setting the hardware/software STOP mode or HALT mode enables internal RAM data to be retained at a low
consumption current.
11
µPD78CP18(A)
Figure 2-1. Memory Map (µPD78C11A Mode)
0000H
RESET
0000H
0004H
Internal PROM
NMI
4096W × 8
0008H
0010H
0018H
0020H
0028H
0060H
INTT0/INTT1
0FFFH
1000H
INT1/INT2
External Memory
61184W × 8
INTE0/INTE1
INTEIN/INTAD
INTSR/INTST
SOFTI
Vector
Area
FEFFH
FF00H
Internal RAM
256W × 8
FFFFH
LOW ADRS
HIGH ADRS
LOW ADRS
HIGH ADRS
0080H
0081H
t = 0
t = 1
0082H
0083H
Call
Table
Area
LOW ADRS
HIGH ADRS
00BEH
00BFH
00C0H
t = 31
USER'S AREA
0FFFH
12
µPD78CP18(A)
Figure 2-2. Memory Map (µPD78C12A Mode)
0000H
RESET
0000H
0004H
Internal PROM
NMI
8192W × 8
0008H
0010H
0018H
0020H
0028H
0060H
INTT0/INTT1
1FFFH
2000H
INT1/INT2
External Memory
57088W × 8
INTE0/INTE1
INTEIN/INTAD
INTSR/INTST
SOFTI
Vector
Area
FEFFH
FF00H
Internal RAM
256W × 8
FFFFH
LOW ADRS
HIGH ADRS
LOW ADRS
HIGH ADRS
0080H
0081H
t = 0
t = 1
0082H
0083H
Call
Table
Area
LOW ADRS
HIGH ADRS
00BEH
00BFH
00C0H
t = 31
USER'S AREA
1FFFH
13
µPD78CP18(A)
Figure 2-3. Memory Map (µPD78C14 Mode)
0000H
RESET
0000H
0004H
Internal PROM
NMI
16384W × 8
0008H
0010H
0018H
0020H
0028H
0060H
INTT0/INTT1
3FFFH
4000H
INT1/INT2
External Memory
48896W × 8
INTE0/INTE1
INTEIN/INTAD
INTSR/INTST
SOFTI
Vector
Area
FEFFH
FF00H
Internal RAM
256W × 8
FFFFH
LOW ADRS
HIGH ADRS
LOW ADRS
HIGH ADRS
0080H
0081H
t = 0
t = 1
0082H
0083H
Call
Table
Area
LOW ADRS
HIGH ADRS
00BEH
00BFH
00C0H
t = 31
USER'S AREA
3FFFH
14
µPD78CP18(A)
Figure 2-4. Memory Map (µPD78C18 Mode)
0000H
RESET
0000H
0004H
Internal PROM
NMI
32768W × 8
0008H
0010H
0018H
0020H
0028H
0060H
INTT0/INTT1
7FFFH
8000H
INT1/INT2
External Memory
31744W × 8
INTE0/INTE1
INTEIN/INTAD
INTSR/INTST
SOFTI
Vector
Area
FBFFH
FC00H
Internal RAM
1024W × 8
FFFFH
LOW ADRS
HIGH ADRS
LOW ADRS
HIGH ADRS
0080H
0081H
t = 0
t = 1
0082H
0083H
Call
Table
Area
LOW ADRS
HIGH ADRS
00BEH
00BFH
00C0H
t = 31
USER'S AREA
7FFFH
15
µPD78CP18(A)
3. MEMORY EXTENSION
The µPD78CP18(A) allows external memory extension by means of the MEMORY MAPPING register (MM) or the
MODE0 and MODE1 pins. Also, the internal PROM and internal RAM access areas can be specified by means of bits
MM7, MM6 and MM5 of the MEMORY MAPPING register.
3.1 MODE PINS
The µPD78CP18(A) can be switched between programming mode and normal operation mode according to the
specification of the MODE0 and MODE1 pins.
Table 3-1 shows the modes set by the MODE pins.
Table 3-1. Modes Set By MODE Pins
MODE1
MODE2
Operating Mode
Setting prohibited
L
L
L
H
L
Programming modeNote
Normal operation mode
Setting prohibited
H
H
H
Note See 4. “PROM PROGRAMMING”.
When MODE0 and MODE1 are driven high, a 4 [kΩ] ≤ R ≤ 0.4 tCYC [kΩ] pull-up resistor should be used (tCYC: ns units).
16
µPD78CP18(A)
3.2 MEMORY MAPPING REGISTER (MM)
The MEMORY MAPPING register is an 8-bit register which performs the following controls:
• Port/extension mode specification for PD7 to PD0 and PF7 to PF0
• Enabling/disabling of internal RAM accesses
• Specification of internal PROM and RAM access areas
The configuration of the MEMORY MAPPING register is shown in Figure 3-1.
(1) Bits MM2 to MM0
These bits control the PD7 to PD0 port/extension mode specification, input/output specification, and the PF7 to
PF0 address output specification.
As shown in Figure 3-1, there is a choice of four capacities for the connectable external memory:
• 256 bytes
• 4 Kbytes
• 16 Kbytes
• 32 K/48 K/56 K/60 Kbytes (set by bits MM7 to MM5)
Ports of PF7 to PF0 not used as address outputs can be used as general-purpose ports.
When RESET signal is input or in the hardware STOP mode, these bits are reset to (0) and PD7 to PD0 are set
to input port mode (high-impedance).
(2) MM3 bit (RAE)
This bit enables (RAE = 1) and disables (RAE = 0) internal RAM access. This bit should be set to “0” during standby
operation and when externally connected RAM, not internal RAM, is used.
In normal operation this bit retains its value when RESET signal is input. However, the RAE bit is undefined after
a power-on reset, and must therefore be initialized by an instruction.
(3) Bits MM7 to MM5
These bits specify the access area of the internal PROM.
When STOP or RESET signal is input, these bits are reset, selecting the 32-Kbyte mode (µPD78C18 mode).
These bits are only valid in the µPD78CG14, 78CP14, 78CP18, 78CP14(A), and 78CP18(A); if data is written to these
bits in the µPD78C11A(A), 78C12A(A), 78C14(A), or 78C18(A), it will be ignored. Therefore, a program developed
on the µPD78CP18(A) can be directly ported to mask ROM.
17
µPD78CP18(A)
Figure 3-1. MEMORY MAPPING Register Format
7
6
5
4
3
2
1
0
RAE
MM1
MM6
MM2
MM0
MM7
MM5
0
0
0
0
1
0
PD7 to PD0 = Input port
PF7 to PF0 = Port mode
PD7 to PD0 = Output port
PF7 to PF0 = Port mode
0
0
1
Port
mode
Singlechip
256 bytes
Exten-
sion
mode
PD7 to PD0 = Extension
mode
PF7 to PF0 = Port mode
1
1
1
0
0
1
Extension
mode
PF7 to PF4 = Port mode
Extension
mode
PF7 & PF6 = Port mode
0
1
1
PD7 to PD0 =
PF3 to PF0 =
4 Kbytes
16 Kbytes
PD7 to PD0 =
PF5 to PF0 =
Extension
mode
PD7 to PD0 =
PF7 to PF0 =
32 K/48 K/
56K/60KNote
bytes
Note Depends on MM7 to MM5 bit-setting
Internal RAM Access
0
1
Disable
Enable
Internal PROM/RAM Access Areas
Internal PROM
Internal RAM
Access Area
MM7 MM6 MM5
Access Area
0
0
0
1
0
0
1
0
0
1
1
1
0000H to 7FFFH
(32 Kbytes:
µPD78C18 mode)
FC00H to FFFFH
(1 Kbyte)
0000H to 3FFFH
(16 Kbytes:
µPD78C14 mode)
FF00H to FFFFH
(256 bytes)
0000H to 1FFFH
(8 Kbytes:
µPD78C12A mode)
FF00H to FFFFH
(256 bytes)
0000H to 0FFFH
(4 Kbytes:
FF00H to FFFFH
(256 bytes)
µPD78C11A mode)
Other than above
Setting Prohibited
18
µPD78CP18(A)
Figure 3-2. External Extension Modes Set by MEMORY MAPPING Register
Port Mode
256-Byte Extension Mode
4-KByte Extension Mode
0
0
0
Internal PROM
((44//88//1166//3322
KKBByytteess))
IInntteerrnnaall PPRROOMM
(4/8/16/32
KKBByytteess))
Internal PROM
(4/8/16/32
KKBByytteess))
Not Used
Not Used
Not Used
External Memory(4 KBytes)
Not Used
External Memory(256 Bytes)
Not Used
Internal RAM
IInntteerrnnaall RRAAMM
Internal RAM
64K
64K
64K
32-/48-/56-/60-KByte
Extension Mode
16-KByte Extension Mode
0
0
Internal PROM
(4/8/16/32
KKBByytteess))
IInntteerrnnaall PPRROOMM
(4/8/16/32
KKBByytteess))
EExxtteerrnnaall MMeemmoorryy
(16 KBytes)
External Memory
((3322//4488//5566//
6600 KKBByytteess))
Not Used
Internal RAM
Internal RAM
64K
64K
Caution
The internal PROM and internal RAM access areas are determined by MM7 to MM5.
19
µPD78CP18(A)
4. PROM PROGRAMMING
The µPD78CP18(A) incorporates 32768 × 8-bit PROM as a program memory. The pins shown in Table 4-1 are used
for write/verify operations on this PROM.
µPD78CP18(A) program timing is compatible with the µPD27C256A.
Please read the following in conjunction with documentation of the µPD27C256A.
Table 4-1. Pins Used in PROM Programming
Pin Name
RESET
Function
Low-level input (at write/verify and read)
High-level input (at write/verify and read)
Low-level input (at write/verify and read)
High-voltage input (at write/verify), high-level input (at read)
Chip enable input
MODE0
MODE1
Note
VPP
CENote
OENote
Output enable input
A14 to A0Note Address input
O7 to O0Note Data input (at write), data output (at verify, read)
Note
VDD
Supply voltage input
Note These pins correspond to the µPD27C256A.
Caution
The µPD78CP18(A) one-time PROM version is not equipped with an erasure window, and therefore
ultraviolet erasure cannot be performed on it.
20
µPD78CP18(A)
4.1 PROM PROGRAMMING OPERATING MODES
The PROM programming operating mode is set as shown in Table 4-2. Pins not used for programming should
be handled as shown in Table 4-3.
Table 4-2. PROM Programming Modes
Note
Note
Operating Mode
Program
CENote OENote
VPP
VDD
RESET
L
MODE0
H
MODE1
L
L
H
H
L
H
L
+12.5 V
+6 V
Program verify
Program inhibit
Read
H
L
+5 V
+5 V
Output disable
Standby
L
H
H
L/H
Note These pins correspond to the µPD27C256A.
Caution When +12.5 V is applied to VPP and +6 V is applied to VDD, setting both CE and OE to “L” is prohibited.
Table 4-3. Recommended Connection of Unused Pins (in PROM Programming Mode)
Pin
INT1
Recommended Connection
Connect to VSS.
X1
AN0 to AN7
VAREF
AVDD
AVSS
Pins other than the
above
Connect to VSS via individual resistor.
Leave open.
X2
21
µPD78CP18(A)
4.2 PROM WRITING PROCEDURE
The PROM writing procedure is as shown below, allowing high-speed writing.
(1) Connect unused pins to VSS via a pull-down resistor, and supply +6 V to VDD and +12.5 V to VPP.
(2) Provide the initial address.
(3) Provide the write data.
(4) Provide a 1-ms program pulse (active low) to the CE pin.
(5) Verify mode. If written, go to (7); if not written, repeat (3) to (5). If the write operation has failed 25 times, go
to (6).
(6) Halt write operation due to defective device.
(7) Provide write data and program pulse of X times x 3 ms (X; repeated times from (3) to (5)) (additional write).
(8) Increment the address.
(9) Repeat (3) to (8) until the final address.
Figure 4-1. PROM Write/Verify Timing
Repeated X Times
Write
Verify
Additional Write
A14/PF6-A10/PF2
A9/NMI
Address (Higher 7 Bits)
A8/PF0
A7/PA7-A0/PA0
Address (Lower 8 Bits)
Data Output
Data Input
Data Input
O7/PD7-O0/PD0
VPP
VPP
VIH
VDD + 1
VDD
VDD
VIH
CE/PB6
VIL
VIH
OE/PB7
VIL
22
µPD78CP18(A)
4.3 PROM READING PROCEDURE
PROM contents can be read onto the external data bus (O7 to O0) using the following procedure.
(1) Connect unused pins to VSS via a pull-down resistor.
(2) Supply +5 V to the VDD and VPP pins.
(3) Input address of data to be read to pins A14 to A0.
(4) Read mode
(5) Output data to pins O7 to O0.
Timing for steps (2) to (5) above is shown in Figure 4-2.
Figure 4-2. PROM Read Timing
A14/PF6-A10/PF2
A9/NMI
A8/PF0
Address Input
CE/PB6
OE/PB7
O7/PD7-O0/PD0
Data Output
23
µPD78CP18(A)
5. SCREENING OF ONE-TIME PROM VERSIONS
Because of their construction, one-time PROM versions cannot be fully tested by NEC before shipment. After the
necessary data has been written, it is recommended that screening be implemented in which PROM verification is
performed after high-temperature storage under the following conditions.
Storage Temperature
Storage Time
24 hours
125 °C
★
NEC provides writing, marking, screening, and inspection services for single-chip microcomputers labeld QTOP
microcomputers. For details, consult NEC.
24
µPD78CP18(A)
6. ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS (TA = 25 °C)
PARAMETER
SYMBOL
VDD
TEST CONDITIONS
RATINGS
–0.5 to +7.0
AVSS to VDD + 0.5
–0.5 to +0.5
–0.5 to +13.5
–0.5 to VDD + 0.5
–0.5 to +13.5
–0.5 to VDD + 0.5
4.0
UNIT
V
AVDD
AVSS
VPP
V
Power supply voltage
V
V
Other than NMI/A9 pin
NMI/A9 pin
V
Input voltage
VI
VO
IOL
V
Output voltage
Output current low
V
All output pins
mA
mA
mA
mA
Total of all output pins
All output pins
100
–2.0
Output current high
IOH
Total of all output pins
–50
A/D converter reference
input voltage
VAREF
–0.5 to AVDD + 0.3
V
Ambient operating temperature
TA
–40 to +85
°C
°C
★
★
Storage temperature
Tstg
–65 to +150
Caution
If the absolute maximum rating of even one of the above parameters is exceeded even momentarily,
the quality of the product may be degraded. The absolute maximum ratings, therefore, specify the
values exceeding which the product may be physically damaged. Be sure to use the product with these
rated values never exceeded.
25
µPD78CP18(A)
OSCILLATOR CHARACTERISTICS (TA = –40 to +85 °C, VDD = AVDD = +5.0 V ± 10 %, VSS = AVSS = 0 V,
VDD –0.8 V ≤ AVDD ≤ VDD, 3.4 V ≤ VAREF ≤ AVDD)
RESONATOR
RECOMMENDED CIRCUIT
PARAMETER
TEST CONDITIONS
MIN.
4
MAX.
15
UNIT
MHz
A/D converter not
used
X1
X2
Ceramic or
crystal
Oscillator frequency (fXX)
resonator
C1
C2
A/D converter used
5.8
4
15
15
A/D converter not
used
X1 input frequency (fX)
MHz
X1
X2
A/D converter used
5.8
0
15
20
External clock
X1 rise time,
fall time (tr, tf)
ns
ns
HCMOS
Inverter
X1 input high-, low-
level width (tΦH, tΦL)
20
250
Cautions 1. Place the oscillator as close as possible to the X1 and X2 pins.
2. Ensure that no other signal lines pass through the shaded area.
26
µPD78CP18(A)
CAPACITANCE (TA = 25 °C, VDD = VSS = 0 V)
PARAMETER
Input capacitance
SYMBOL
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
pF
CI
CO
CIO
10
20
20
fC = 1 MHz
Unmeasured pins
returned to 0 V
Output capacitance
Input-output capacitance
pF
pF
DC CHARACTERISTICS (TA = –40 to +85 °C, VDD = AVDD = +5.0 V ± 10 %, VSS = AVSS = 0 V)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN.
0
TYP.
MAX.
UNIT
V
All except RESET, STOP, NMI,
SCK, INT1, TI, AN4 to AN7
VIL1
0.8
Input voltage low
RESET, STOP, NMI, SCK, INT1,
TI, AN4 to AN7
VIL2
VIH1
0
0.2VDD
VDD
V
V
V
All except RESET, STOP, NMI,
SCK, INT1, TI, AN4 to AN7, X1, X2
2.2
Input voltage high
Output voltage low
Output voltage high
Input current
RESET, STOP, NMI, SCK, INT1,
TI, AN4 to AN7, X1, X2
VIH2
0.8 VDD
VDD
VOL
IOL = 2.0 mA
0.45
V
V
VDD
– 1.0
IOH = –1.0 mA
VOH
VDD
– 0.5
IOH = –100 µA
V
II
INT1Note1, TI(PC3)Note2 ; 0 V ≤ VI ≤ VDD
±200
±10
µA
µA
All except INT1, TI (PC3),
AN7 to AN0; 0 V ≤ VI ≤ VDD
Input leakage
current
ILI
AN7 to AN0; 0 V ≤ VI ≤ VDD
0 V ≤ VO ≤ VDD
±1
µA
µA
Output leakage
current
ILO
±10
AIDD1
AIDD2
IDD1
Operating mode fXX = 15 MHz
STOP mode
0.5
10
16
7
1.3
20
35
13
mA
µA
AVDD power supply
current
Operating mode fXX = 15 MHz
HALT mode fXX = 15 MHz
mA
mA
VDD power supply
current
IDD2
Data retention
voltage
VDDDR
IDDDR
Hardware/software STOP mode
2.5
V
Hardware/softwareNote3 VDDDR = 2.5 V
1
15
50
µA
µA
Data retention
current
STOP mode
VDDDR = 5 V ± 10 %
10
★
Notes 1. If self-bias should be generated by ZCM register.
2. If the control mode is set by MCC register, and self-bias should be generated by ZCM register.
3. If self-bias is not generated.
27
µPD78CP18(A)
AC CHARACTERISTICS (TA = –40 to +85 °C, VDD = AVDD = +5.0 V ± 10 %, VSS = AVSS = 0 V)
READ/WRITE OPERATION:
PARAMETER
SYMBOL
tCYC
tAL
TEST CONDITIONS
MIN.
66
MAX.
167
UNIT
ns
X1 input cycle time
Address setup time (to ALE↓ )
Address hold time (from ALE↓ )
RD↓ delay time from address
Address float time from RD↓
Data input time from address
Data input time from ALE↓
Data input time from RD↓
RD↓ delay time from ALE↓
Data hold time (from RD↑ )
ALE↑ delay time from RD↑
30
ns
tLA
fXX = 15 MHz, CL = 150 pF
35
ns
tAR
100
ns
tAFR
tAD
CL = 150 pF
20
250
135
120
ns
ns
tLDR
tRD
ns
fXX = 15 MHz, CL = 150 pF
ns
tLR
15
0
ns
tRDH
tRL
CL = 150 pF
ns
fXX = 15 MHz, CL = 150 pF
80
ns
In data read
fXX = 15 MHz, CL = 150 pF
215
415
ns
ns
RD low-level width
tRR
In OP code fetch
fXX = 15 MHz, CL = 150 pF
ALE high-level width
tLL
tAW
tLDW
tWD
tLW
fXX = 15 MHz, CL = 150 pF
fXX = 15 MHz, CL = 150 pF
CL = 150 pF
90
ns
ns
ns
ns
ns
ns
ns
ns
ns
WR↓ delay time from address
Data output time from ALE↓
Data output time from WR↓
WR↓ delay time from ALE↓
Data setup time (to WR↑ )
Data hold time (from WR↑ )
ALE↑ delay time from WR↑
WR low-level width
100
197
140
15
127
60
tDW
tWDH
tWL
fXX = 15 MHz, CL = 150 pF
80
tWW
215
ZERO-CROSS CHARACTERISTICS :
PARAMETER
Zero-cross detection input
Zero-cross accuracy
SYMBOL
TEST CONDITIONS
MIN.
1
MAX.
1.8
UNIT
VACP-P
mV
VZX
AZX
AC coupling
±135
60-Hz sine wave
Zero-cross detection input
frequency
fZX
0.05
1
kHz
28
µPD78CP18(A)
SERIAL OPERATION :
PARAMETER
SYMBOL
TEST CONDITIONS
Note1
MIN.
800
400
1.6
MAX.
UNIT
ns
ns
µs
SCK input
SCK output
SCK input
SCK output
SCK input
SCK cycle time
tCYK
Note2
Note1
Note2
335
160
700
335
160
700
80
ns
ns
ns
ns
ns
ns
ns
ns
ns
SCK low-level width
SCK high-level width
tKKL
Note1
Note2
tKKH
SCK output
Note1
RXD setup time (to SCK↑ )
RXD hold time (from SCK↑ )
TXD delay time from SCK↓
tRXK
tKRX
tKTX
Note1
80
Note1
210
Notes 1. If clock rate is × 1 in asynchronous mode, synchronous mode, or I/O interface mode.
2. If clock rate is × 16 or × 64 in asynchronous mode.
Remark
The numeric values in the table are those when fXX = 15 MHz, CL = 100 pF.
OTHER OPERATION :
PARAMETER
SYMBOL
TEST CONDITIONS
MIN.
6
MAX.
UNIT
TI high-, low-level width
tTIH, tTIL
tCYC
• Event counter mode
tCI1H, tCI1L
6
tCYC
tCYC
• Frequency test mode
• Pulse width test mode
• ECNT latch and clear input
• INTEIN set input
CI high-, low-level width
tCI2H, tCI2L
48
NMI high-, low-level width
INT1 high-, low-level width
INT2 high-, low-level width
AN4 to AN7, low-level width
RESET high-, low-level width
tNIH, tNIL
tI1H, tI1L
10
36
36
36
10
µs
tCYC
tCYC
tCYC
µs
tI2H, tI2L
tANH, tANL
tRSH, tRSL
29
µPD78CP18(A)
A/D CONVERTER CHARACTERISTICS (TA = –40 to +85 °C, VDD = +5.0 V ± 10 %, VSS = AVSS = 0 V,
VDD – 0.5 V ≤ AVDD ≤ VDD, 3.4 V ≤ VAREF ≤ AVDD)
PARAMETER
Resolution
SYMBOL
TEST CONDITIONS
MIN.
8
TYP.
MAX.
UNIT
Bits
3.4 V ≤ VAREF ≤ AVDD, 66 ns ≤ tCYC ≤ 167 ns
4.0 V ≤ VAREF ≤ AVDD, 66 ns ≤ tCYC ≤ 167 ns
±0.8 %
±0.6 %
FSR
FSR
Absolute accuracyNote
Conversion time
TA = –10 to +70 °C,
4.0 V ≤ VAREF ≤ AVDD, 66 ns ≤ tCYC ≤ 167 ns
±0.4 %
FSR
66 ns ≤ tCYC ≤ 110 ns
110 ns ≤ tCYC ≤ 167 ns
66 ns ≤ tCYC ≤ 110 ns
110 ns ≤ tCYC ≤ 167 ns
576
432
96
tCYC
tCYC
tCYC
tCYC
V
tCONV
tSAMP
Sampling time
72
Analog input voltage
VIAN
RAN
–0.3
V
AREF + 0.3
Analog input
impedance
50
MΩ
★
Reference voltage
VAREF
IAREF1
IAREF2
AIDD1
AIDD2
3.4
AVDD
3.0
1.5
1.3
20
V
Operating mode
STOP mode
1.5
0.7
0.5
10
mA
mA
mA
µA
VAREF current
AVDD power supply
current
Operating mode fXX = 15 MHz
STOP mode
Note Quantization error (±1/2 LSB) is not included.
AC Timing Test Point
VDD – 1.0 V
2.2 V
2.2 V
0.8 V
Test Points
0.8 V
0.45 V
30
µPD78CP18(A)
tCYC-Dependent AC Characteristics Expression
PARAMETER
EXPRESSION
MIN./MAX.
MIN.
UNIT
ns
tAL
tLA
tAR
tAD
tLDR
tRD
tLR
tRL
2T – 100
T – 30
MIN.
ns
3T – 100
7T – 220
5T – 200
4T – 150
T – 50
MIN.
ns
MAX.
MAX.
MAX.
MIN.
ns
ns
ns
ns
2T – 50
MIN.
ns
4T – 50 (In data read)
7T – 50 (In OP code fetch)
2T – 40
tRR
MIN.
ns
tLL
MIN.
MIN.
MAX.
MIN.
MIN.
MIN.
MIN.
MIN.
ns
ns
ns
ns
ns
ns
ns
ns
tAW
tLDW
tLW
3T – 100
T + 130
T – 50
tDW
tWDH
tWL
4T – 140
2T – 70
2T – 50
tWW
4T – 50
12T
(SCK input)Note1
(SCK input)Note2
(SCK output)
tCYK
tKKL
tKKH
6T
MIN.
MIN.
MIN.
ns
ns
ns
24T
5T + 5
2.5T + 5
(SCK input)Note1
(SCK input)Note2
12T – 100 (SCK output)
5T + 5
(SCK input)Note1
(SCK input)Note2
2.5T + 5
12T – 100 (SCK output)
Notes 1. If clock rate is ×1, in asynchronous mode, synchronous mode, or I/O interface mode.
2. If clock rate is ×16, ×64 in asynchronous mode.
Remarks 1. T = tCYC = 1/fXX
2. Other items which are not listed in this table are not dependent on oscillator frequency (fXX).
31
µPD78CP18(A)
Timing Waveforms
Read Operation
tCYC
X1
PF7 to PF0
PD7 to PD0
ALE
Address (Higher)
tAD
Read Data
Address (Lower)
tLDR
tRDH
tRL
tLL
tLA
tAFR
tAL
tRD
tRR
RD
tLR
tAR
Write Operation
X1
PF7 to PF0
PD7 to PD0
ALE
Address (Higher)
t
LDW
Write Data
Address (Lower)
t
DW
t
WDH
t
LL
t
LA
t
WD
t
WW
t
WL
t
AL
WR
t
LW
t
AW
32
µPD78CP18(A)
Serial Operation
tCYK
tKKL
tKKH
SCK
tKTX
TXD
RXD
tRXK
tKRX
Timer Input Timing
tTIH
tTIL
TI
Timer/Event Counter Input Timing
Event Counter Mode
tCI1H
tCI1L
CI
Pulse Width Test Mode
tCI2H
tCI2L
CI
33
µPD78CP18(A)
Interrupt Input Timing
tNIH
tI1L
tI2H
tNIL
tI1H
tI2L
NMI
INT1
INT2
Reset Input Timing
tRSH
tRSL
RESET
0.8VDD
0.2VDD
External Clock Timing
tφH
0.8VDD
X1
0.8 V
tr
tf
tφL
tCYC
34
µPD78CP18(A)
DATA MEMORY STOP MODE LOW POWER SUPPLY VOLTAGE DATA RETENTION CHARACTERISTICS (TA = –40
to +85 °C)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN.
2.5
TYP.
MAX.
5.5
UNIT
V
Data retention power
supply voltage
VDDDR
VDDDR = 2.5 V
1
15
50
µA
µA
µs
Data retention power
supply current
IDDDR
VDDDR = 5 V ± 10 %
10
★
VDD rise/fall time
tRVD, tFVD
tSSTVD
200
STOP setup time
(to VDD)
12T + 0.5
Note
µs
µs
STOP hold time
(from VDD)
12T + 0.5
Note
tHVDST
Note T= tCYC = 1/fXX
Data Retention Timing
90 %
10 %
VDD
VDDDR
tFVD
tRVD
tSSTVD
tHVDST
VIH2
VIL2
STOP
35
µPD78CP18(A)
DC PROGRAMMING CHARACTERISTICS (TA = 25 ± 5 °C, MODE1 = VIL, MODE0 = VIH, VSS = 0 V)
PARAMETER
SYMBOL SYMBOLNote
TEST CONDITIONS
MIN.
2.4
TYP.
MAX.
UNIT
V
VDDP
+ 0.3
Input voltage high
VIH
VIH
Input voltage low
VIL
VIL
ILI
–0.3
0.8
V
Input leakage current
ILIP
0 ≤ VI ≤ VDDP; except INT1, TI (PC3)
±10
µA
VDD
– 1.0
Output voltage high
Output voltage low
VOH
VOH
IOH = –1.0 mA
V
VOL
ILO
VOL
––
IOL = 2.0 mA
0.45
V
Output leakage
current
0 ≤ VO ≤ VDDP, OE = VIH
±10
µA
EPROM programming mode
EPROM read mode
5.75
4.5
6.0
6.25
5.5
V
V
VDDP supply voltage
VPP supply voltage
VDDP
VPP
VDD
VPP
5.0
12.5
EPROM programming mode
EPROM read mode
12.2
12.8
V
VPP = VDDP
5
V
EPROM programming mode
50
50
mA
VDDP supply current
VPP supply current
IDD
IPP
IDD
IPP
EPROM read mode
CE = VIL, VI = VIH
5
mA
EPROM programming mode
CE = VIL, OE = VIH
5
1
30
mA
EPROM read mode
100
µA
Note Corresponding µPD27C256A symbol
36
µPD78CP18(A)
AC PROGRAMMING CHARACTERISTICS (TA = 25 ± 5 °C, MODE1 = VIL, MODE0 = VIH, VSS = 0 V)
Note1
PARAMETER
SYMBOL SYMBOL
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
µs
Address setup time (to CE↓)
OE↓ delay time from data
Input data setup time (to CE↓)
Address hold time (from CE↑)
Input data hold time (from CE↑)
Output data hold time (from OE↑)
VPP setup time (to CE↓)
tSAC
tAS
2
2
tDDOO
tSIDC
tHCA
tOES
tDS
µs
2
µs
tAH
2
µs
tHCID
tHOOD
tSVPC
tSVDC
tWL1
tDH
2
µs
tDF
0
130
ns
tVPS
tVDS
tPW
tOPW
2
µs
VDDP setup time (to CE↓)
2
µs
Initial program pulse width
Additional program pulse width
0.95
2.85
1.0
1.05
ms
ms
tWL2
78.75
EPROM programming/read mode
tSMC
––
2
µs
setup time (to CE↓)Note2
Data output time from address
Data output time from CE↓
Data output time from OE↓
Data hold time (from OE↑)
Data hold time (from address)
tDAOD
tDCOD
tDOOD
tHCOD
tHAOD
tACC
tCE
OE = VIL
1
1
µs
µs
µs
ns
ns
tOE
tDF
1
0
0
130
tOH
OE = VIL
Notes 1. Corresponding µPD27C256A symbol
2. Indicates state in which MODE1 = VIL and MODE0 = VIH.
37
µPD78CP18(A)
PROM Programming Mode Timing
A12 to A0
Effective Address
tHOOD
tHCA
tSAC
Data Input
Data Output
Data Input
D7 to D0
tSIDC
tSMC
tSVPC
tHCID
tSIDC
tHCID
VIH
MODE1 = VIL
MODE0 = VIH
MODE1
MODE0
VIL
VPP
VDDP
VPP
VDDP + 1
VDDP
VDDP
tSVDC
VIH
VIL
CE
tDDOO
tWL1
tWL2
tDOOD
VIH
VIL
OE
Cautions 1. Ensure that VDDP is applied before VPP, and cut after VPP.
2. Ensure that VPP does not exceed +13 V including overshoot.
PROM Read Mode Timing
A12 to A0
Effective Address
CE
tDCOD
OE
t
HCOD
tDOOD
t
DAOD
tHAOD
Hi-Z
Hi-Z
Data Output
D7 to D0
Cautions 1. If you wish to read within the tDAOD range, the OE input delay time from the fall of CE should be a
maximum of tDAOD - tDOOD.
2. tHCOD is the time from the point at which OE or CE (whichever is first) reaches VIH.
38
µPD78CP18(A)
7. CHARACTERISTIC CURVES (REFERENCE VALUE)
IDD1, IDD2 vs. VDD
(TA = 25 ˚C, fXX = 15 MHz)
30
25
20
15
I
DD1 (TYP.)
10
5
I
DD2 (TYP.)
0
0
4.5
5.0
5.5
6.0
Power Supply Voltage VDD [V]
IDD1, IDD2 vs. fXX
(T = 25 ˚C, VDD = 5 V)
A
30
20
10
0
I
DD1 (TYP.)
I
DD2 (TYP.)
0
5
10
15
Oscillator Frequency fXX [MHz]
39
µPD78CP18(A)
IOL vs. VOL
(TA = 25 ˚C, VDD = 5 V)
2.5
2.0
1.5
TYP.
1.0
0.5
0
0
0.1
0.2
0.3
0.4
0.5
Output Voltage Low VOL [V]
IOH vs. VOH
(TA = 25 ˚C, VDD = 5 V)
–1.5
TYP.
–1.0
–0.5
0
0
0.1
0.2
0.3
0.4
0.5
Power Supply Voltage – Output Voltage High VDD – VOH [V]
40
µPD78CP18(A)
IDDDR vs. VDDDR
(TA = 25 ˚C)
10
8
µ
6
TYP.
4
2
0
0
2
3
4
5
6
Data Retention Power Supply Voltage VDDDR [V]
41
µPD78CP18(A)
8. PACKAGE DRAWINGS
64 PIN PLASTIC QUIP
A
64
33
32
1
W
X
M
N
H
I
M
J
K
P64GQ-100-36
NOTE
ITEM
MILLIMETERS
INCHES
Each lead centerline is located within 0.25 mm
(0.010 inch) of its true position (T.P.) at maxi-
mum material condition.
A
C
H
I
41.5 +0.3
+0.012
1.634
–0.008
–0.2
16.5
0.650
0.020
0.010
+0.10
+0.004
–0.005
–
0.50
0.25
J
2.54 (T.P.)
0.100 (T.P.)
K
1.27 (T.P.)
0.050 (T.P.)
+0.25
+0.011
M
N
P
1.1
0.043
–0.15
–0.006
+0.10
+0.004
0.25
0.010
–0.05
–0.003
4.0+–0.3
0.157
+0.013
–0.012
3.6+–0.1
+0.004
S
0.142
–0.005
0.950+–0.042
0.750+–0.042
W
X
24.13+–1.05
19.05+–1.05
42
µPD78CP18(A)
64 PIN PLASTIC QFP (14×20)
A
B
51
52
33
32
detail of lead end
64
20
19
1
G
M
N
H
I
J
K
L
P64GF-100-3B8,3BE,3BR-1
NOTE
ITEM
A
MILLIMETERS
23.6 0.4
20.0 0.2
14.0 0.2
17.6 0.4
1.0
INCHES
Each lead centerline is located within 0.20
mm (0.008 inch) of its true position (T.P.) at
maximum material condition.
0.929 0.016
+0.009
B
0.795
–0.008
+0.009
C
0.551
–0.008
D
F
0.693 0.016
0.039
G
H
I
1.0
0.039
+0.004
0.40 0.10
0.20
0.016
–0.005
0.008
J
1.0 (T.P.)
1.8 0.2
0.039 (T.P.)
+0.008
K
0.071
–0.009
+0.009
0.031
L
0.8 0.2
–0.008
+0.10
+0.004
0.15
M
N
P
0.006
–0.05
–0.003
0.12
0.005
2.7
0.106
Q
S
0.1 0.1
3.0 MAX.
0.004 0.004
0.119 MAX.
43
µPD78CP18(A)
★
9. RECOMMENDED SOLDERING CONDITIONS
The µPD78CP18(A) should be soldered and mounted under the following recommended conditions.
For details of recommended soldering conditions, refer to the information document "Semiconductor Device
Mounting Technology Manual (IEI-1207)".
For soldering methods and conditions other than those recommended below, contact an NEC representative.
Table 9-1. Surface Mount Type Soldering Conditions
µPD78CP18GF(A)-3BE: 64-Pin Plastic QFP (14 × 20 mm)
Recommended
Soldering Method
Infrared reflow
Soldering Conditions
Condition Symbol
Package peak temperature: 235 °C, Duration: 30 sec. max. (at 210 °C or higher),
IR35-00-2
Count: Twice or less
<Attention>
(1)
Perform the second reflow at the time the device temperature is lowered to
the room temperature from the heating by the first reflow.
(2)
Do not wash the soldered portion with the flux following the first reflow.
VPS
Package peak temperature: 215 °C, Duration: 40 sec. max. (at 200 °C or higher),
VP15-00-2
Count: Twice or less
<Attention>
(1)
Perform the second reflow at the time the device temperature is lowered to
the room temperature from the heating by the first reflow.
(2)
Do not wash the soldered portion with the flux following the first reflow.
Wave soldering
Partial heating
Solder bath temperature: 260 °C max., Duration: 10 sec. max., Count: Once
Preheating temperature: 120 °C max. (package surface temperature)
WS60-00-1
——
Pin temperature: 300 °C max., Duration: 3 sec. max. (per device side row of pins)
Caution
Use of more than one soldering method should be avoided (except in the case of pin part heating).
Table 9-2. Through-Hole Type Soldering Conditions
µPD78CP18GQ(A)-36: 64-Pin Plastic QUIP
Soldering Method
Soldering Conditions
Wave soldering
(pin part only)
Solder bath temperature: 260 °C max., Duration: 10 sec. max.
Pin temperature: 300 °C max., Duration: 3 sec. max. (per pin)
Partial heating
Caution
Wave soldering is used on the pin only, and care must be taken to prevent solder from coming into
direct contact with the body.
44
µPD78CP18(A)
10. DIFFERENCES BETWEEN THE µPD78CP18(A) AND µPD78C18(A)
Part Number
µPD78C18(A)
µPD78CP18(A)
Item
Internal ROM
32 K × 8 bits
32 K × 8 bits
(PROM)
(mask ROM)
Internal RAM
1 K × 8 bits
PB7/OE
1 K × 8 bits
PB7
Pin connection
PB6/CE
PB6
STOP/VPP
STOP
NMI/A9
NMI
PA7/A7 to PA0/A0
PF6/A14 to PF2/A10
PF0/A8
PA7 to PA0
PF6 to PF2
PF0
PD7/O7 to PD0/O0
PROM programming mode
PD7 to PD0
Mode set by MODE pins (when
MODE0 is set to 1, and MODE1
to 0)
• Operates as the µPD78C17(A)
(ROM-less mode)
• External memory 16 K extension
mode
MODE0 pin input/output function
Input onlyNote
Yes
Input/output
No
Internal memory access area
setting by MM register
Port A to Port C
Pull-up resistors not incorporated
Pull-up resistor incorporation
selectable bit-wise by mask
option
Note An emulation control signal is not output even if the MODE0 pin is pulled high.
45
µPD78CP18(A)
★
APPENDIX DEVELOPMENT TOOLS
The following development tools are available to develop a system which uses the µPD78CP18(A).
Language Processor
87AD series
This is a program which converts a program written in mnemonic to an object code for which
microcomputer execution is possible.
relocatable assembler
(RA87)
Moreover, it contains a function to automatically create a symbol/table, and optimize branch
instructions.
OS
Ordering Code (Product Name)
Host Machine
Supply Medium
3.5-inch 2HD
MS-DOSTM
Ver. 2.11
to
µS5A13RA87
PC-9800
series
µS5A10RA87
µS7B13RA87
µS7B10RA87
Ver. 5.00ANote
5-inch 2HD
3.5-inch 2HC
5-inch 2HC
PC DOSTM
(Ver. 3.1)
IBM PC/ATTM
PROM Write Tools
PG-1500
With a provided board and an optional programmer adapter connected, this PROM programmer
can manipulate from a stand-alone or host machine to perform programming on a single-chip
microcomputer which incorporates PROM.
It is also capable of programming a typical PROM ranging from 256 K to 4 M bits.
PA-78CP14GF/
GQ
PROM programmer adapter for the µPD78CP18(A). Used by connecting to the PG-1500.
For the µPD78CP18GF(A)-3BE
For the µPD78CP18GQ(A)-36
PA-78CP14GF
PA-78CP14GQ
Connects the PG-1500 to a host machine by using serial and parallel interface, to control the PG-
1500 on a host machine.
PG-1500
controller
OS
Ordering Code (Product Name)
Host Machine
Supply Medium
3.5-inch 2HD
MS-DOS
Ver. 2.11
to
µS5A13PG1500
PC-9800
series
µS5A10PG1500
µS7B10PG1500
Ver. 5.00ANote
5-inch 2HD
5-inch 2HC
PC DOS
IBM PC/AT
(Ver. 3.1)
Note Versions 5.00 and 5.00A have a task swap function, but this function cannot be used with this software.
Remark
The operations of the assembler and the PG-1500 controller are guaranteed only on the above host
machines and operating systems.
46
µPD78CP18(A)
Debugging Tools
An in-circuit emulator (IE-78C11-M) is available as a program debugging tool for theµPD78CP18(A). The following
table shows its system configuration.
IE-78C11-M
The IE-78C11-M is an in-circuit emulator which works with the 87AD series.
It can be connected to a host machine to perform efficient debugging.
IE-78C11-M
Connects the IE-78C11-M to host machine by using the RS-233C, to control the IE-78C11-M on
host machine.
control program
(IE controller)
OS
Ordering Code (Product Name)
Host Machine
Supply Medium
3.5-inch 2HD
MS-DOS
Ver. 2.11
to
µS5A13IE78C11
PC-9800
series
µS5A10IE78C11
µS7B10IE78C11
5-inch 2HD
5-inch 2HC
Ver. 3.30D
PC DOS
IBM PC/AT
(Ver. 3.1)
Remark
The operations of the IE controller are guaranteed only on the above host machines and operating
systems.
47
µPD78CP18(A)
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static
electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental
control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid
using insulators that easily build static electricity. Semiconductor devices must be stored and
transported in an anti-static container, static shielding bag or conductive material. All test and
measurement tools including work bench and floor should be grounded. The operator should be
grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar
precautions need to be taken for PW boards wiht semiconductor devices on it.
2 HANDLING OF UNUSED INPUT PINS FOR CMOS
Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of
being an output pin. All handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3 STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does
not define the initial operation status of the device. Immediately after the power source is turned
ON, the devices with reset function have not yet been initialized. Hence, power-on does not
guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.
48
µPD78CP18(A)
[MEMO]
No part of this document may be copied or reproduced in any form or by any means without the prior written
consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this
document.
NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual
property rights of third parties by or arising from use of a device described herein or any other liability arising
from use of such device. No license, either express, implied or otherwise, is granted under any patents,
copyrights or other intellectual property rights of NEC Corporation or others.
While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,
the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or
property arising from a defect in an NEC semiconductor device, customer must incorporate sufficient safety
measures in its design, such as redundancy, fire-containment, and anti-failure features.
NEC devices are classified into the following three quality grades:
“Standard“, “Special“, and “Specific“. The Specific quality grade applies only to devices developed based on
a customer designated “quality assurance program“ for a specific application. The recommended applications
of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each
device before using it in a particular application.
Standard: Computers, office equipment, communications equipment, test and measurement equipment,
audio and visual equipment, home electronic appliances, machine tools, personal electronic
equipment and industrial robots
Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems or medical equipment for life support, etc.
The quality grade of NEC devices in “Standard“ unless otherwise specified in NEC's Data Sheets or Data Books.
If customers intend to use NEC devices for applications other than those specified for Standard quality grade,
they should contact NEC Sales Representative in advance.
Anti-radioactive design is not implemented in this product.
M4 94.11
QTOP is a trademark of NEC Corporation.
MS-DOS is a trademark of Microsoft Corporation.
PC/AT and PC DOS are trademarks of IBM Corporation.
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