UPD78F0862MC(A)-5A4-A

User’s Manual

µPD780862 Subseries

8-Bit Single-Chip Microcontrollers

µPD780861

µPD780861(A1)

µPD780862(A1)

µPD78F0862A(A1)

µPD780861(A2)

µPD780862(A2)

µPD78F0862A(A2)

µPD780862

µPD78F0862

µPD78F0862A

µPD780861(A)

µPD780862(A)

µPD78F0862(A)

µPD78F0862A(A)

Document No. U16418EJ3V0UD00 (3rd edition)

Date Published July 2006 NS CP(K)

2002

Printed in Japan

[MEMO]

User’s Manual U16418EJ3V0UD

2

NOTES FOR CMOS DEVICES

VOLTAGE APPLICATION WAVEFORM AT INPUT PIN

1

Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the

CMOS device stays in the area between V^IL(MAX) and VIH (MIN) due to noise, etc., the device may

malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed,

and also in the transition period when the input level passes through the area between V^IL(MAX) and

VIH (MIN).

HANDLING OF UNUSED INPUT PINS

2

Unconnected CMOS device inputs can be cause of malfunction. If an input pin is unconnected, it is

possible that an internal input level may be generated due to noise, etc., causing malfunction. CMOS

devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed

high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to V^DDor GND

via a resistor if there is a possibility that it will be an output pin. All handling related to unused pins must

be judged separately for each device and according to related specifications governing the device.

3

PRECAUTION AGAINST ESD

A strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and

ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as

much as possible, and quickly dissipate it when it has occurred. Environmental control must be

adequate. When it is dry, a humidifier should be used. It is recommended to avoid using insulators that

easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static

container, static shielding bag or conductive material. All test and measurement tools including work

benches and floors should be grounded. The operator should be grounded using a wrist strap.

Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for

PW boards with mounted semiconductor devices.

4

STATUS BEFORE INITIALIZATION

Power-on does not necessarily define the initial status of a MOS device. Immediately after the power

source is turned ON, devices with reset functions have not yet been initialized. Hence, power-on does

not guarantee output pin levels, I/O settings or contents of registers. A device is not initialized until the

reset signal is received. A reset operation must be executed immediately after power-on for devices

with reset functions.

5

POWER ON/OFF SEQUENCE

In the case of a device that uses different power supplies for the internal operation and external

interface, as a rule, switch on the external power supply after switching on the internal power supply.

When switching the power supply off, as a rule, switch off the external power supply and then the

internal power supply. Use of the reverse power on/off sequences may result in the application of an

overvoltage to the internal elements of the device, causing malfunction and degradation of internal

elements due to the passage of an abnormal current.

The correct power on/off sequence must be judged separately for each device and according to related

specifications governing the device.

6

INPUT OF SIGNAL DURING POWER OFF STATE

Do not input signals or an I/O pull-up power supply while the device is not powered. The current

injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and

the abnormal current that passes in the device at this time may cause degradation of internal elements.

Input of signals during the power off state must be judged separately for each device and according to

related specifications governing the device.

User’s Manual U16418EJ3V0UD

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Windows and Windows NT are either registered trademarks or trademarks of Microsoft Corporation in the

United States and/or other countries.

PC/AT is a trademark of International Business Machines Corporation.

HP9000 series 700 and HP-UX are trademarks of Hewlett-Packard Company.

SPARCstation is a trademark of SPARC International, Inc.

Solaris and SunOS are trademarks of Sun Microsystems, Inc.

SuperFlash is a registered trademark of Silicon Storage Technology, Inc. in several countries including the

United States and Japan.

User’s Manual U16418EJ3V0UD

4

These commodities, technology or software, must be exported in accordance

with the export administration regulations of the exporting country.

Diversion contrary to the law of that country is prohibited.

Caution: This product uses SuperFlash^®technology licensed from Silicon Storage Technology, Inc.

•

The information in this document is current as of December, 2005. The information is subject to

change without notice. For actual design-in, refer to the latest publications of NEC Electronics data

sheets or data books, etc., for the most up-to-date specifications of NEC Electronics products. Not

all products and/or types are available in every country. Please check with an NEC Electronics sales

representative for availability and additional information.

• No part of this document may be copied or reproduced in any form or by any means without the prior

written consent of NEC Electronics. NEC Electronics assumes no responsibility for any errors that may

appear in this document.

•

NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual

property rights of third parties by or arising from the use of NEC Electronics products listed in this document

or any other liability arising from the use of such products. No license, express, implied or otherwise, is

granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others.

Descriptions of circuits, software and other related information in this document are provided for illustrative

purposes in semiconductor product operation and application examples. The incorporation of these

circuits, software and information in the design of a customer's equipment shall be done under the full

responsibility of the customer. NEC Electronics assumes no responsibility for any losses incurred by

customers or third parties arising from the use of these circuits, software and information.

•

• While NEC Electronics endeavors to enhance the quality, reliability and safety of NEC Electronics products,

customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To

minimize risks of damage to property or injury (including death) to persons arising from defects in NEC

Electronics products, customers must incorporate sufficient safety measures in their design, such as

redundancy, fire-containment and anti-failure features.

• NEC Electronics products are classified into the following three quality grades: "Standard", "Special" and

"Specific".

The "Specific" quality grade applies only to NEC Electronics products developed based on a customer-

designated "quality assurance program" for a specific application. The recommended applications of an NEC

Electronics product depend on its quality grade, as indicated below. Customers must check the quality grade of

each NEC Electronics product before using it in a particular application.

"Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio

and visual equipment, home electronic appliances, machine tools, personal electronic equipment

and industrial robots.

"Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster

systems, anti-crime systems, safety equipment and medical equipment (not specifically designed

for life support).

"Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life

support systems and medical equipment for life support, etc.

The quality grade of NEC Electronics products is "Standard" unless otherwise expressly specified in NEC

Electronics data sheets or data books, etc. If customers wish to use NEC Electronics products in applications

not intended by NEC Electronics, they must contact an NEC Electronics sales representative in advance to

determine NEC Electronics' willingness to support a given application.

(Note)

(1)

"NEC Electronics" as used in this statement means NEC Electronics Corporation and also includes its

majority-owned subsidiaries.

(2)

"NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as

defined above).

M8E 02. 11-1

User’s Manual U16418EJ3V0UD

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INTRODUCTION

Readers

This manual is intended for user engineers who wish to understand the functions of the

µPD780862 Subseries and design and develop application systems and programs for

these devices.

The target products are as follows.

µPD780862 Subseries: µPD780861, 780862, 78F0862, 78F0862A, 780861(A),

780862(A), 78F0862(A), 78F0862A(A), 780861(A1),

780862(A1), 78F0862A(A1), 780861(A2) , 780862(A2),

78F0862A(A2)

Purpose

This manual is intended to give users an understanding of the functions described in the

Organization below.

Organization

The µPD780862 Subseries manual is separated into two parts: this manual and the

instructions edition (common to the 78K/0 Series).

µPD780862 Subseries

User’s Manual

78K/0 Series

Instructions

User’s Manual

(This Manual)

• Pin functions

• CPU functions

• Internal block functions

• Interrupts

• Instruction set

• Explanation of each instruction

• Other on-chip peripheral functions

• Electrical specifications

How to Read This Manual It is assumed that the readers of this manual have general knowledge of electrical

engineering, logic circuits, and microcontrollers.

• When using this manual as the manual for (A) grade, (A1) grade, and (A2) grade

products:

→ Only the quality grade differs between standard products and (A) grade, (A1)

grade, and (A2) grade products. Read the part number as follows.

• µPD780861 → µPD780861(A), 780861(A1), 780861(A2)

• µPD780862 → µPD780862(A), 780862(A1), 780862(A2)

• µPD78F0862 → µPD78F0862(A)

• µPD78F0862A → µPD78F0862A(A), 78F0862A(A1), 78F0862A(A2)

• To gain a general understanding of functions:

→ Read this manual in the order of the CONTENTS. The mark “<R>” shows major

revised points. The revised points can be easily searched by copying an “<R>” in

the PDF file and specifying in the “Find what:” field.

• How to interpret the register format:

→ For a bit number enclosed in angle brackets, the bit name is defined as a

reserved word in the RA78K0, and is defined as an sfr variable using the

#pragma sfr directive in the CC78K0.

User’s Manual U16418EJ3V0UD

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• To check the details of a register when you know the register name:

→ Refer to APPENDIX C REGISTER INDEX.

• To know details of the 78K/0 Series instructions:

→ Refer to the separate document 78K/0 Series Instructions User’s Manual

(U12326E).

Caution Examples in this manual employ the “standard” quality grade for

general electronics. When using examples in this manual for the

“special” quality grade, review the quality grade of each part and/or

circuit actually used.

Conventions

Data significance:

Higher digits on the left and lower digits on the right

Active low representations: ××× (overscore over pin and signal name)

Note:

Footnote for item marked with Note in the text

Caution:

Remark:

Information requiring particular attention

Supplementary information

...

Numerical representations: Binary

Decimal

×××× or ××××B

××××

...

Hexadecimal

××××H

Other Documents

Document Name

SEMICONDUCTOR SELECTION GUIDE − Products and Packages −

Semiconductor Device Mount Manual

Document No.

X13769X

Note

Quality Grades on NEC Semiconductor Devices

C11531E

C10983E

C11892E

NEC Semiconductor Device Reliability/Quality Control System

Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD)

Note See the “Semiconductor Device Mount Manual” website (http://www.necel.com/pkg/en/mount/index.html).

Caution The related documents listed above are subject to change without notice. Be sure to use the latest

version of each document when designing.

User’s Manual U16418EJ3V0UD

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CONTENTS

CHAPTER 1 OUTLINE......................................................................................................................... 15

1.1 Features......................................................................................................................................... 15

1.2 Applications .................................................................................................................................. 16

1.3 Ordering Information.................................................................................................................... 16

1.4 Pin Configuration (Top View) ...................................................................................................... 18

1.5 Block Diagram............................................................................................................................... 20

1.6 Outline of Functions..................................................................................................................... 21

CHAPTER 2 PIN FUNCTIONS ........................................................................................................... 23

2.1 Pin Function List........................................................................................................................... 23

2.2 Description of Pin Functions....................................................................................................... 25

2.2.1 P00 to P02 (port 0).............................................................................................................................25

2.2.2 P10 to P15 (port 1).............................................................................................................................25

2.2.3 P20 to P23 (port 2).............................................................................................................................26

2.2.4 P130 (port 13) ....................................................................................................................................27

2.2.5 AVREF..................................................................................................................................................27

2.2.6 RESET ...............................................................................................................................................27

2.2.7 X1 and X2 ..........................................................................................................................................27

2.2.8 CL1 and CL2 ......................................................................................................................................27

2.2.9 VDD .....................................................................................................................................................27

2.2.10 VSS....................................................................................................................................................27

2.2.11 FLMD0 and FLMD1 (flash memory versions only) ...........................................................................27

2.2.12 IC (mask ROM versions only)...........................................................................................................28

2.3 Pin I/O Circuits and Recommended Connection of Unused Pins ........................................... 29

CHAPTER 3 CPU ARCHITECTURE .................................................................................................. 31

3.1 Memory Space .............................................................................................................................. 31

3.1.1 Internal program memory space.........................................................................................................35

3.1.2 Internal data memory space...............................................................................................................36

3.1.3 Special function register (SFR) area ..................................................................................................36

3.1.4 Data memory addressing ...................................................................................................................37

3.2 Processor Registers..................................................................................................................... 40

3.2.1 Control registers.................................................................................................................................40

3.2.2 General-purpose registers..................................................................................................................44

3.2.3 Special function registers (SFRs).......................................................................................................45

3.3 Instruction Address Addressing................................................................................................. 49

3.3.1 Relative addressing............................................................................................................................49

3.3.2 Immediate addressing........................................................................................................................50

3.3.3 Table indirect addressing ...................................................................................................................51

3.3.4 Register addressing ...........................................................................................................................51

3.4 Operand Address Addressing..................................................................................................... 52

3.4.1 Implied addressing .............................................................................................................................52

3.4.2 Register addressing ...........................................................................................................................53

3.4.3 Direct addressing ...............................................................................................................................54

3.4.4 Short direct addressing ......................................................................................................................55

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3.4.5 Special function register (SFR) addressing ....................................................................................... 56

3.4.6 Register indirect addressing .............................................................................................................. 57

3.4.7 Based addressing.............................................................................................................................. 58

3.4.8 Based indexed addressing ................................................................................................................ 59

3.4.9 Stack addressing............................................................................................................................... 60

CHAPTER 4 PORT FUNCTIONS........................................................................................................ 61

4.1 Port Functions............................................................................................................................... 61

4.2 Port Configuration ........................................................................................................................ 62

4.2.1 Port 0................................................................................................................................................. 63

4.2.2 Port 1................................................................................................................................................. 65

4.2.3 Port 2................................................................................................................................................. 70

4.2.4 Port 13............................................................................................................................................... 71

4.3 Registers Controlling Port Function........................................................................................... 71

4.4 Port Function Operations............................................................................................................. 77

4.4.1 Writing to I/O port .............................................................................................................................. 77

4.4.2 Reading from I/O port........................................................................................................................ 77

4.4.3 Operations on I/O port....................................................................................................................... 77

CHAPTER 5 CLOCK GENERATOR................................................................................................... 78

5.1 Functions of Clock Generator ..................................................................................................... 78

5.2 Configuration of Clock Generator............................................................................................... 78

5.3 Registers Controlling Clock Generator ...................................................................................... 80

5.4 System Clock Oscillator............................................................................................................... 86

5.4.1 High-speed system clock oscillator.................................................................................................... 86

5.4.2 Internal low-speed oscillator .............................................................................................................. 90

5.4.3 Prescaler ........................................................................................................................................... 90

5.5 Clock Generator Operation.......................................................................................................... 90

5.6 Time Required to Switch Between Internal Low-Speed Oscillation Clock and High-Speed

System Clock ................................................................................................................................ 95

5.7 Time Required for CPU Clock Switchover ................................................................................. 96

5.8 Clock Selection Flowchart and Register Settings..................................................................... 97

5.8.1 Changing to high-speed system clock from internal low-speed oscillation clock ............................... 97

5.8.2 Changing from high-speed system clock to internal low-speed oscillation clock ............................... 98

5.8.3 Register settings................................................................................................................................ 99

CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 ....................................................................... 100

6.1 Functions of 16-Bit Timer/Event Counter 00............................................................................ 100

6.2 Configuration of 16-Bit Timer/Event Counter 00 ..................................................................... 101

6.3 Registers Controlling 16-Bit Timer/Event Counter 00............................................................. 105

6.4 Operation of 16-Bit Timer/Event Counter 00............................................................................ 111

6.4.1 Interval timer operation.....................................................................................................................111

6.4.2 PPG output operation.......................................................................................................................114

6.4.3 Pulse width measurement operation ................................................................................................117

6.4.4 External event counter operation......................................................................................................125

6.4.5 Square-wave output operation..........................................................................................................128

6.4.6 One-shot pulse output operation ......................................................................................................130

6.5 Cautions for 16-Bit Timer/Event Counter 00 ............................................................................ 135

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CHAPTER 7 8-BIT TIMER 50.......................................................................................................... 138

7.1 Functions of 8-Bit Timer 50 ....................................................................................................... 138

7.2 Configuration of 8-Bit Timer 50................................................................................................. 139

7.3 Registers Controlling 8-Bit Timer 50 ........................................................................................ 140

7.4 Operations of 8-Bit Timer 50 ..................................................................................................... 143

7.4.1 Operation as interval timer ...............................................................................................................143

7.4.2 Operation as operating clock of TMH0 and UART6 ........................................................................145

7.5 Cautions on 8-Bit Timer 50........................................................................................................ 147

CHAPTER 8 8-BIT TIMERS H0 AND H1....................................................................................... 148

8.1 Functions of 8-Bit Timers H0 and H1........................................................................................ 148

8.2 Configuration of 8-Bit Timers H0 and H1 ................................................................................. 148

8.3 Registers Controlling 8-Bit Timers H0 and H1 ........................................................................ 152

8.4 Operation of 8-Bit Timers H0 and H1........................................................................................ 158

8.4.1 Operation as interval timer ...............................................................................................................158

8.4.2 Operation as PWM output mode ......................................................................................................162

8.4.3 Operation as carrier generator mode (8-bit timer H1 only)...............................................................168

CHAPTER 9 WATCHDOG TIMER ................................................................................................... 175

9.1 Functions of Watchdog Timer................................................................................................... 175

9.2 Configuration of Watchdog Timer ............................................................................................ 176

9.3 Registers Controlling Watchdog Timer.................................................................................... 177

9.4 Operation of Watchdog Timer................................................................................................... 180

9.4.1 Watchdog timer operation when “Internal low-speed Oscillator cannot be stopped” is selected by

mask option......................................................................................................................................180

9.4.2 Watchdog timer operation when “Internal low-speed oscillator can be stopped by software” is

selected by mask option...................................................................................................................181

9.4.3 Watchdog timer operation in STOP mode (when “Internal low-speed oscillator can be stopped by

software” is selected by mask option) ..............................................................................................182

9.4.4 Watchdog timer operation in HALT mode (when “Internal low-speed oscillator can be stopped by

software” is selected by mask option) ..............................................................................................184

CHAPTER 10 A/D CONVERTER ..................................................................................................... 185

10.1 Function of A/D Converter....................................................................................................... 185

10.2 Configuration of A/D Converter .............................................................................................. 187

10.3 Registers Used in A/D Converter............................................................................................ 188

10.4 A/D Converter Operations ....................................................................................................... 193

10.4.1 Basic operations of A/D converter..................................................................................................193

10.4.2 Input voltage and conversion results..............................................................................................195

10.4.3 A/D converter operation mode........................................................................................................196

10.5 How to Read A/D Converter Characteristics Table............................................................... 199

10.6 Cautions for A/D Converter ..................................................................................................... 201

CHAPTER 11 SERIAL INTERFACE UART6 .................................................................................. 206

11.1 Functions of Serial Interface UART6 ...................................................................................... 206

11.2 Configuration of Serial Interface UART6................................................................................ 210

11.3 Registers Controlling Serial Interface UART6....................................................................... 213

11.4 Operation of Serial Interface UART6 ...................................................................................... 221

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11.4.1 Operation stop mode......................................................................................................................221

11.4.2 Asynchronous serial interface (UART) mode..................................................................................222

11.4.3 Dedicated baud rate generator.......................................................................................................237

CHAPTER 12 SERIAL INTERFACE CSI10..................................................................................... 244

12.1 Functions of Serial Interface CSI10 ........................................................................................ 244

12.2 Configuration of Serial Interface CSI10.................................................................................. 244

12.3 Registers Controlling Serial Interface CSI10 ......................................................................... 246

12.4 Operation of Serial Interface CSI10......................................................................................... 248

12.4.1 Operation stop mode......................................................................................................................248

12.4.2 3-wire serial I/O mode ....................................................................................................................249

CHAPTER 13 MANCHESTER CODE GENERATOR...................................................................... 256

13.1 Functions of Manchester Code Generator............................................................................. 256

13.2 Configuration of Manchester Code Generator....................................................................... 256

13.3 Registers Controlling Manchester Code Generator.............................................................. 259

13.4 Operation of Manchester Code Generator ............................................................................. 262

13.4.1 Operation stop mode......................................................................................................................262

13.4.2 Manchester code generator mode..................................................................................................263

13.4.3 Bit sequential buffer mode..............................................................................................................273

CHAPTER 14 INTERRUPT FUNCTIONS......................................................................................... 282

14.1 Interrupt Function Types.......................................................................................................... 282

14.2 Interrupt Sources and Configuration...................................................................................... 282

14.3 Registers Controlling Interrupt Function ............................................................................... 285

14.4 Interrupt Servicing Operations................................................................................................ 292

14.4.1 Maskable interrupt request acknowledgment .................................................................................292

14.4.2 Software interrupt request acknowledgment...................................................................................294

14.4.3 Multiple interrupt servicing..............................................................................................................295

14.4.4 Interrupt request hold .....................................................................................................................298

CHAPTER 15 STANDBY FUNCTION............................................................................................... 299

15.1 Standby Function and Configuration ..................................................................................... 299

15.1.1 Standby function.............................................................................................................................299

15.1.2 Registers controlling standby function............................................................................................300

15.2 Standby Function Operation.................................................................................................... 303

15.2.1 HALT mode ....................................................................................................................................303

15.2.2 STOP mode....................................................................................................................................306

CHAPTER 16 RESET FUNCTION.................................................................................................... 310

16.1 Register for Confirming Reset Source ................................................................................... 316

CHAPTER 17 CLOCK MONITOR..................................................................................................... 317

17.1 Functions of Clock Monitor ..................................................................................................... 317

17.2 Configuration of Clock Monitor............................................................................................... 317

17.3 Registers Controlling Clock Monitor ...................................................................................... 318

17.4 Operation of Clock Monitor...................................................................................................... 319

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CHAPTER 18 POWER-ON-CLEAR CIRCUIT.................................................................................. 324

18.1 Functions of Power-on-Clear Circuit...................................................................................... 324

18.2 Configuration of Power-on-Clear Circuit................................................................................ 325

18.3 Operation of Power-on-Clear Circuit ...................................................................................... 325

18.4 Cautions for Power-on-Clear Circuit ...................................................................................... 326

CHAPTER 19 LOW-VOLTAGE DETECTOR ................................................................................... 328

19.1 Functions of Low-Voltage Detector........................................................................................ 328

19.2 Configuration of Low-Voltage Detector.................................................................................. 328

19.3 Registers Controlling Low-Voltage Detector......................................................................... 329

19.4 Operation of Low-Voltage Detector ........................................................................................ 331

19.5 Cautions for Low-Voltage Detector ........................................................................................ 335

CHAPTER 20 MASK OPTIONS/OPTION BYTE............................................................................. 339

20.1 Mask Options (Mask ROM Versions)...................................................................................... 339

20.2 Option Bytes (Flash Memory Versions) ................................................................................. 340

CHAPTER 21 FLASH MEMORY...................................................................................................... 341

21.1 Internal Memory Size Switching Register.............................................................................. 342

21.2 Writing with Flash Programmer .............................................................................................. 343

21.3 Programming Environment ..................................................................................................... 347

21.4 Communication Mode .............................................................................................................. 347

21.5 Handling of Pins on Board ...................................................................................................... 350

21.5.1 FLMD0 pin......................................................................................................................................350

21.5.2 FLMD1 pin......................................................................................................................................350

21.5.3 Serial interface pins........................................................................................................................351

21.5.4 RESET pin......................................................................................................................................352

21.5.5 Port pins.........................................................................................................................................353

21.5.6 Other signal pins ............................................................................................................................353

21.5.7 Power supply..................................................................................................................................353

21.6 Programming Method............................................................................................................... 354

21.6.1 Controlling flash memory................................................................................................................354

21.6.2 Flash memory programming mode.................................................................................................354

21.6.3 Selecting communication mode......................................................................................................355

21.6.4 Communication commands............................................................................................................356

CHAPTER 22 INSTRUCTION SET................................................................................................... 357

22.1 Conventions Used in Operation List ...................................................................................... 357

22.1.1 Operand identifiers and specification methods...............................................................................357

22.1.2 Description of operation column.....................................................................................................358

22.1.3 Description of flag operation column ..............................................................................................358

22.2 Operation List ........................................................................................................................... 359

22.3 Instructions Listed by Addressing Type................................................................................ 367

CHAPTER 23 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS, (A) GRADE

PRODUCTS)................................................................................................................. 370

CHAPTER 24 ELECTRICAL SPECIFICATIONS ((A1) GRADE PRODUCTS)................................. 385

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CHAPTER 25 ELECTRICAL SPECIFICATIONS ((A2) GRADE PRODUCTS) ................................. 400

CHAPTER 26 PACKAGE DRAWING............................................................................................... 415

CHAPTER 27 RECOMMENDED SOLDERING CONDITIONS ........................................................ 416

CHAPTER 28 CAUTIONS FOR WAIT............................................................................................. 418

28.1 Cautions for Wait ...................................................................................................................... 418

28.2 Peripheral Hardware That Generates Wait............................................................................. 419

28.3 Example of Wait Occurrence................................................................................................... 420

APPENDIX A DEVELOPMENT TOOLS........................................................................................... 421

A.1 Software Package....................................................................................................................... 423

A.2 Language Processing Software................................................................................................ 423

A.3 Control Software ........................................................................................................................ 424

A.4 Flash Memory Writing Tools ..................................................................................................... 424

A.5 Debugging Tools (Hardware).................................................................................................... 425

A.6 Debugging Tools (Software) ..................................................................................................... 426

APPENDIX B NOTES ON TARGET SYSTEM DESIGN ............................................................... 427

APPENDIX C REGISTER INDEX...................................................................................................... 429

C.1 Register Index (In Alphabetical Order with Respect to Register Names) ............................ 429

C.2 Register Index (In Alphabetical Order with Respect to Register Symbol) ........................... 432

APPENDIX D REVISION HISTORY.................................................................................................. 435

D.1 Major Revisions in This Edition................................................................................................ 435

D.2 Revision History of Preceding Editions................................................................................... 438

User’s Manual U16418EJ3V0UD

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CHAPTER 1 OUTLINE

1.1 Features

{ Minimum instruction execution time can be changed from high speed (0.2 µs: @ 10 MHz operation with high-

speed system clock) to low speed (3.2 µs: @ 10 MHz operation with high-speed system clock)

{ General-purpose registers: 8 bits × 32 registers (8 bits × 8 registers × 4 banks)

{ ROM, RAM capacities

Item

Program Memory

(ROM)

Data Memory

Part Number

µPD780861

µPD780862

(Internal High-Speed RAM)

Mask ROM

8 KB

512 bytes

768 bytes

16 KB

µPD78F0862, 78F0862A^{Note 1}

Flash memory 16 KB^{Note 2}

<R>

Notes 1. µPD78F0862 and 78F0862A differ only in the characteristics of a flash memory. For details, refer to

“Flash Memory Programming Characteristics” in the chapter of electrical specifications.

2. The internal flash memory and internal high-speed RAM capacities can be changed using the internal

memory size switching register (IMS).

{ On-chip power-on-clear (POC) circuit and low-voltage detector (LVI)

{ Short startup is possible via the CPU default start using the internal low-speed oscillator

{ On-chip clock monitor function using the internal low-speed oscillator

{ On-chip watchdog timer (operable with low-speed oscillation clock)

{ I/O ports: 14

{ Timer: 5 channels

{ Serial interface

UART (LIN (Local Interconnect Network)-bus supported): 1 channel

CSI1: 1 channel

{ On-chip Manchester code generator

{ 10-bit resolution A/D converter: 4 channels

{ Supply voltage: V^DD= 2.7 to 5.5 V^{Note 1}

{ Operating ambient temperature: T^A= –40 to +85°C (standard products, (A) grade products)^{Note 2}

TA = –40 to +110°C ((A1) grade products)

T^A= –40 to +125°C ((A2) grade products)

Notes 1. Use the product in a voltage range of 3.0 to 5.5 V because the detection voltage (V^POC) of the

power-on-clear (POC) circuit is 2.85 V 0.15 V.

<R>

2. Only the standard product and (A) grade product are available in µ PD78F0862.

15

User’s Manual U16418EJ3V0UD

CHAPTER 1 OUTLINE

1.2 Applications

{ Automotive equipment

•

System control for body electricals (power windows, keyless entry reception, etc.)

Sub-microcontrollers for control

{ Home audio, car audio

{ AV equipment

{ PC peripheral equipment (keyboards, etc.)

{ Household electrical appliances

•

Outdoor air conditioner units

Microwave ovens, electric rice cookers

{ Industrial equipment

•

Pumps

Vending machines

FA (Factory Automation)

1.3 Ordering Information

(1) Mask ROM versions

Part Number

Package

Quality Grade

µPD780861MC-×××-5A4

20-pin plastic SSOP (7.62 mm (300))

Standard

Special

<R>

µPD780861MC-×××-5A4-A

µPD780862MC-×××-5A4

µPD780862MC-×××-5A4-A

µPD780861MC(A)-×××-5A4

µPD780861MC(A)-×××-5A4-A

µPD780862MC(A)-×××-5A4

µPD780862MC(A)-×××-5A4-A

µPD780861MC(A1)-×××-5A4

µPD780861MC(A1)-×××-5A4-A

µPD780862MC(A1)-×××-5A4

µPD780862MC(A1)-×××-5A4-A

µPD780861MC(A2)-×××-5A4

µPD780861MC(A2)-×××-5A4-A

µPD780862MC(A2)-×××-5A4

µPD780862MC(A2)-×××-5A4-A

Remarks 1. ××× indicates ROM code suffix.

2. Products with -A at the end of the part number are lead-free products.

Please refer to "Quality Grades on NEC Semiconductor Devices" (Document No. C11531E) published by

NEC Electronics Corporation to know the specification of the quality grade on the device and its

recommended applications.

User’s Manual U16418EJ3V0UD

16

CHAPTER 1 OUTLINE

(2) Flash memory versions

Part Number

Package

Quality Grade

µPD78F0862MC-5A4

20-pin plastic SSOP (7.62 mm (300))

Standard

Special

µPD78F0862MC-5A4-A

µPD78F0862AMC-5A4

<R>

µPD78F0862AMC-5A4-A

µPD78F0862MC(A)-5A4

µPD78F0862MC(A)-5A4-A

µPD78F0862AMC(A)-5A4

µPD78F0862AMC(A)-5A4-A

µPD78F0862AMC(A1)-5A4

µPD78F0862AMC(A1)-5A4-A

µPD78F0862AMC(A2)-5A4

µPD78F0862AMC(A2)-5A4-A

<R>

Remark Products with -A at the end of the part number are lead-free products.

Please refer to "Quality Grades on NEC Semiconductor Devices" (Document No. C11531E) published by

NEC Electronics Corporation to know the specification of the quality grade on the device and its

recommended applications.

User’s Manual U16418EJ3V0UD

17

CHAPTER 1 OUTLINE

1.4 Pin Configuration (Top View)

•

20-pin plastic SSOP (7.62 mm (300))

Note 1

V

SS

1

AVREF

20

19

18

17

16

15

14

13

12

11

X1[CL1]

P02^{Note 2}/X2[CL2]

IC/FLMD0^{Note 3}

2

P20/ANI0

3

P21/ANI1

4

P22/ANI2

V

DD

5

P23/ANI3

RESET

P01/TI010/TO00/INTP2

P00/TI000/INTP0/MCGO

P10/SCK10/(INTP1)

P11/SI10/INTP3

6

P130

7

P15/TOH0/FLMD1^{Note 3}

P14/RxD6/<INTP0>

P13/TxD6/INTP1/(TOH1)/(MCGO)

P12/SO10/TOH1/(INTP3)

8

9

10

Notes 1. V^SSand AVSS are internally connected in the µPD780862 Subseries. Be sure to connect VSS to a

stabilized GND (= 0 V).

2. When the internal high-speed oscillation clock is selected as the high-speed system clock, P02 can be

used as a port input pin.

3. FLMD0 and FLMD1 are available only in the µPD78F0862 and 78F0862A.

Cautions 1. Connect the IC (Internally Connected) pin directly to V^SS.

2. Connect the AV^REFpin to VDD.

Remarks 1. Functions in parentheses ( ) can be assigned by setting the alternate-function pin switch register

(PSEL).

2. Functions in angle brackets < > can be assigned by setting the input switch control register (ISC).

3. Items in brackets [ ] are pin names when using external RC oscillation.

User’s Manual U16418EJ3V0UD

18

CHAPTER 1 OUTLINE

Pin Identification

ANI0 to ANI3:

AV^REF:

Analog input

RESET:

RxD6:

SCK10:

SI10:

Reset

Analog reference voltage

RC oscillator

Receive data

CL1, CL2:

Serial clock input/output

Serial data input

Serial data output

Timer input

FLMD0, FLMD1: Flash programming mode

IC: Internally connected

INTP0 to INTP3: External interrupt input

SO10:

TI000, TI010:

MCGO:

Manchester code output

TO00, TOH0, TOH1: Timer output

P00 to P02:

P10 to P15:

P20 to P23:

P130:

Port 0

Port 1

Port 2

Port 13

TxD6:

V^DD:

Transmit data

Power supply

VSS:

Ground

X1, X2:

Crystal oscillator (X1 input clock)

User’s Manual U16418EJ3V0UD

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CHAPTER 1 OUTLINE

1.5 Block Diagram

TO00/TI010/

P01/INTP2

P00 to P02^{Note 3}

P10 to P15

P20 to P23

P130

3

6

4

Port 0

Port 1

16-bit timer/

event counter 00

TI000/P00/

INTP0/MCGO

TOH0/P15/FLMD1^{Note 2}

8-bit timer H0

8-bit timer H1

Port 2

TOH1/P12/

SO10/(INTP3)

Port 13

(TOH1)/P13/TxD6/

INTP1/(MCGO)

Clock monitor

78K/0

CPU

core

ROM/

flash

memory

8-bit timer 50

Power on clear/

low voltage

indicator

POC/LVI

control

Watchdog timer

Reset control

MCGO/P00/

TI000/INTP0

INTP0/P00/TI000/

MCGO

Manchester code

generator

(MCGO)/P13/TxD6/

INTP1/(TOH1)

Internal

high-speed

RAM

<INTP0>/P14/RxD6

INTP1/P13/TxD6/

(TOH1)/(MCGO)

RxD6/P14/<INTP0>

Serial interface

UART6

Interrupt control

(INTP1)/P10/SCK10

TxD6/P13/INTP1/

(TOH1)/(MCGO)

INTP2/P01/TI010/

TO00

SI10/P11/INTP3

INTP3/P11/SI10

SO10/P12/TOH1/

(INTP3)

Serial interface

CSI10

(INTP3)/P12/SO10/

TOH1

SCK10/P10/(INTP1)

RESET

X1[CL1]

System control

ANI0/P20 to

4

ANI3/P23

A/D converter

AVREF

X2[CL2]/P02^{Note 1}

Internal high-speed

oscillator

Internal low-speed

oscillator

Note 3

V

DD

V

SS

IC

FLMD0^{Note 2}

FLMD1^{Note 2}

Notes 1. When the internal high-speed oscillation clock is selected as the high-speed system clock, P02 can be

used as a port input pin.

2. FLMD0 and FLMD1 are available only in the µPD78F0862 and 78F0862A.

3. V^SSand AVSS are internally connected in the µPD780862 Subseries. Be sure to connect VSS to a

stabilized GND (= 0 V).

Remarks 1. Functions in parentheses ( ) can be assigned by setting the alternate-function pin switch register

(PSEL).

2. Functions in angle brackets < > can be assigned by setting the input switch control register (ISC).

3. Items in brackets [ ] are pin names when using external RC oscillation.

User’s Manual U16418EJ3V0UD

20

CHAPTER 1 OUTLINE

1.6 Outline of Functions

(1/2)

PD78F0862, 78F0862A^{Note 1}

µ

Item

µ PD780861

µ PD780862

Internal memory

ROM

8 KB

16 KB

(flash memory)

High-speed RAM 512 bytes

64 KB

768 bytes

Memory space

High-speed

system clock

(oscillation

frequency)

Standard

• Ceramic/crystal/external clock oscillation

<R>

products, (A)

(2 to 10 MHz: V^DD= 4.0 to 5.5 V, 2 to 8.38 MHz: VDD = 3.3 to 5.5 V,

2 to 5 MHz: V^DD= 2.7 to 5.5 V)

grade products

Note 2

• External RC/external clock oscillation

(3 to 4 MHz: V^DD= 2.7 to 5.5 V)

• Internal high-speed oscillation

(8 MHz (TYP.): V^DD= 4.0 to 5.5 V)

(A1) grade

products

• Ceramic/crystal/external clock oscillation

(2 to 10 MHz: V^DD= 4.0 to 5.5 V, 2 to 5 MHz: VDD = 2.7 to 5.5 V)

• External RC/external clock oscillation

(3 to 4 MHz: V^DD= 2.7 to 5.5 V)

• Internal high-speed oscillation

(8 MHz (TYP.): V^DD= 4.0 to 5.5 V)

(A2) grade

products

• Ceramic/crystal/external clock oscillation

(2 to 9.2 MHz: V^DD= 4.0 to 5.5 V, 2 to 5 MHz: VDD = 2.7 to 5.5 V)

• External RC/external clock oscillation

(3 to 4 MHz: V^DD= 2.7 to 5.5 V)

• Internal high-speed oscillation

(8 MHz (TYP.): V^DD= 4.0 to 5.5 V)

Internal low-speed oscillation clock

(oscillation frequency)

• Internal low-speed oscillation

(240 kHz (TYP.): V^DD= 2.7 to 5.5 V)

General-purpose registers

8 bits × 32 registers (8 bits × 8 registers × 4 banks)

Minimum instruction execution time

0.2 µs/0.4 µs/0.8 µs/1.6 µs/3.2 µs (high-speed system clock: @ fXH = 10 MHz operation)

8.3 µs/16.7 µs (TYP.) (internal low-speed oscillation clock: @ fR = 240 kHz (TYP.)

operation)

Instruction set

I/O ports

• 16-bit operation

• Multiply/divide (8 bits × 8 bits, 16 bits ÷ 8 bits)

• Bit manipulate (set, reset, test, and Boolean operation) • BCD adjust, etc.

Total:

14

CMOS I/O

8

5

1

CMOS input

CMOS output

Timers

• 16-bit timer/event counter: 1 channel

• 8-bit timer:

3 channels

1 channel

• Watchdog timer:

A/D converter

10-bit resolution × 4 channels

<R>

Notes 1. µ PD78F0862 and µ PD78F0862A differ only in the characteristics of a flash memory. For details, refer to

“Flash Memory Programming Characteristics” in the chapter of electrical specifications.

2. Only the standard product and (A) grade product are available in µ PD78F0862.

User’s Manual U16418EJ3V0UD

21

CHAPTER 1 OUTLINE

(2/2)

PD78F0862, 78F0862A^{Note 1}

µ

Item

µ PD780861

µ PD780862

Serial interface

• UART mode supporting LIN-bus:

• 3-wire serial I/O mode:

1 channel

Manchester code generator

Vectored interrupt Internal

1 channel

12

4

sources

External

Reset

• Reset using RESET pin

• Internal reset by watchdog timer

• Internal reset by clock monitor

• Internal reset by power-on-clear

• Internal reset by low-voltage detector

VDD = 2.7 to 5.5 V^{Note 2}

Supply voltage

Operating ambient temperature

Standard products, (A) grade products^{Note 3}

(A1) grade products:

:

TA = −40 to +85°C

T^A= −40 to +110°C

T^A= −40 to +125°C

(A2) grade products:

Package

20-pin plastic SSOP (7.62 mm (300))

<R> Notes 1. µ PD78F0862 and µ PD78F0862A differ only in the characteristics of a flash memory. For details, refer to

“Flash Memory Programming Characteristics” in the chapter of electrical specifications.

2. Use the product in a voltage range of 3.0 to 5.5 V because the detection voltage (V^POC) of the power-on-

clear (POC) circuit is 2.85 V 0.15 V.

<R>

3. Only the standard product and (A) grade product are available in µ PD78F0862.

An outline of the timer is shown below.

16-Bit Timer/

8-Bit Timer 50

8-Bit Timers H0 and H1

Watchdog Timer

Event Counter 00

TMH0

TMH1

Operation Interval timer

mode

1 channel

−

1 channel

−

External event counter

−

1

−

Watchdog timer

Timer output

−

1 channel

Function

1 output

−

1 output

−

PPG output

−

PWM output

1 output

Pulse width measurement

Square-wave output

Interrupt source

2 inputs

1 output

2

−

1

−

1

User’s Manual U16418EJ3V0UD

22

CHAPTER 2 PIN FUNCTIONS

2.1 Pin Function List

There are two types of pin I/O buffer power supplies: AV^REFand VDD. The relationship between these power

supplies and the pins is shown below.

Table 2-1. Pin I/O Buffer Power Supplies

Power Supply

AVREF

Corresponding Pins

P20 to P23

Pins other than P20 to P23

VDD

(1) Port pins

Pin Name

P00

I/O

Function

Input/output can be specified in 1-bit units.

After Reset

Input

Alternate Function

TI000/INTP0/MCGO

TI010/TO00/INTP2

Port 0.

3-bit I/O port. Use of an on-chip pull-up resistor can be

specified by a software setting.

P01

P02^{Note 1}

P10

Input

I/O

Input-only

Input

X2[CL2]

Port 1.

SCK10/(INTP1)

SI10/INTP3

6-bit I/O port.

P11

Input/output can be specified in 1-bit units.

Use of an on-chip pull-up resistor can be specified by a

software setting.

P12

SO10/TOH1/(INTP3)

TxD6/INTP1/(TOH1)/(MCGO)

RxD6/<INTP0>

TOH0/FLMD1^{Note 2}

ANI0 to ANI3

P13

P14

P15

P20 to P23

Input

Port 2.

Input

4-bit input-only port.

P130

Output

Port 13.

Output

−

1-bit output-only port.

Notes 1. When the internal high-speed oscillation clock is selected as the high-speed system clock, this pin can be

used as a port input pin.

2. FLMD1 is available only in the µPD78F0862 and 78F0862A.

Remarks 1. Functions in parentheses ( ) can be assigned by setting the alternate-function pin switch register (PSEL).

2. Functions in angle brackets < > can be assigned by setting the input switch control register (ISC).

3. Items in brackets [ ] are pin names when using external RC oscillation.

23

User’s Manual U16418EJ3V0UD

CHAPTER 2 PIN FUNCTIONS

(2) Non-port pins

Pin Name

INTP0

<INTP0>

INTP1

(INTP1)

INTP2

INTP3

(INTP3)

SI10

I/O

Function

After Reset

Input

Alternate Function

P00/TI000/MCGO

Input

External interrupt request input for which the valid edge

(rising edge, falling edge, or both rising and falling edges)

can be specified

P14/RxD6

P13/TxD6/(TOH1)/(MCGO)

P10/SCK10

P01/TI010/TO00

P11/SI10

P12/SO10/TOH1

P11/INTP3

Input

Serial data input to serial interface

Input

SO10

Output

I/O

Serial data output from serial interface

Clock input/output for serial interface

Serial data input to asynchronous serial interface

Serial data output from asynchronous serial interface

Manchester code output

P12/TOH1/(INTP3)

P10/(INTP1)

SCK10

RxD6

Input

P14/<INTP0>

TxD6

Output

P13/INTP1/(TOH1)/(MCGO)

P00/TI000/INTP0

P13/TxD6/INTP1/(TOH1)

P00/INTP0/MCGO

MCGO

(MCGO)

TI000

Input

External count clock input to 16-bit timer/event counter 00 Input

Capture trigger input to capture registers (CR000, CR010)

of 16-bit timer/event counter 00

TI010

Capture trigger input to capture register (CR000) of 16-bit

timer/event counter 00

P01/TO00/INTP2

TO00

Output

16-bit timer/event counter 00 output

8-bit timer H output

Input

P01/TI010/INTP2

P15/FLMD1^{Note 1}

P12/SO10/(INTP3)

P13/TxD6/INTP1/(MCGO)

P20 to P23

TOH0

TOH1

(TOH1)

ANI0 to ANI3 Input

A/D converter analog input

Input

AVREF

Input

A/D converter reference voltage input and positive power

supply for port 2

−

RESET

X1 [CL1]

X2 [CL2]

VDD

Input

System reset input

−

Input

Connecting resonator for high-speed system clock

[Connecting RC for high-speed system clock]

−

P02

Positive power supply

−

Note 2

VSS

Ground potential

−

IC

Internally connected. Connect directly to VSS.

Flash memory programming mode lead-in.

−

FLMD0^{Note 1}

FLMD1^{Note 1}

P15/TOH0

Notes 1. FLMD0 and FLMD1 are available only in the µPD78F0862 and 78F0862A.

2. V^SSand AVSS are internally connected in the µPD780862 Subseries. Be sure to connect VSS to a

stabilized GND (= 0 V).

Remarks 1. Functions in parentheses ( ) can be assigned by setting the alternate-function pin switch register (PSEL).

2. Functions in angle brackets < > can be assigned by setting the input switch control register (ISC).

3. Items in brackets [ ] are pin names when using external RC oscillation.

User’s Manual U16418EJ3V0UD

24

CHAPTER 2 PIN FUNCTIONS

2.2 Description of Pin Functions

2.2.1 P00 to P02 (port 0)

P00 to P02 function as a 3-bit I/O port. These pins also function as external interrupt request input, Manchester

code output, timer I/O, and crystal/ceramic resonator connection [RC connection] for high-speed system clock

oscillation.

The following operation modes can be specified in 1-bit units.

Caution When the internal high-speed oscillation clock is selected as the high-speed system clock, P02

can be used as a port input pin.

(1) Port mode

P00 and P01 function as an I/O port, and P02 functions as an input-only port. P00 and P01 can be set to input or

output in 1-bit units using port mode register 0 (PM0). Use of an on-chip pull-up resistor can be specified by pull-

up resistor option register 0 (PU0).

(2) Control mode

P00 to P02 function as external interrupt request input, Manchester code output, timer I/O, and crystal/ceramic

resonator connection [RC connection] for high-speed system clock oscillation.

(a) INTP0 and INTP2

These are external interrupt request input pins for which the valid edge (rising edge, falling edge, or both

rising and falling edges) can be specified.

(b) MCGO

This is a Manchester code output pin.

(c) TI000

This is the pin for inputting an external count clock to 16-bit timer/event counter 00 and a capture trigger

signal to the capture registers (CR000, CR010) of 16-bit timer/event counter 00.

(d) TI010

This is the pin for inputting a capture trigger signal to the capture register (CR000) of 16-bit timer/event

counter 00.

(e) TO00

This is a timer output pin.

(f) X2 [CL2]

This is the pin for crystal/ceramic resonator connection [RC connection] for high-speed system clock

oscillation.

2.2.2 P10 to P15 (port 1)

P10 to P15 function as a 6-bit I/O port. These pins also function as pins for external interrupt request input, serial

interface data I/O, clock I/O, timer output, and flash memory programming mode lead-in.

P10 to P15 can be assigned as external interrupt request input, timer output, and Manchester code output by

setting the alternate-function pin switch register (PSEL) and input switch control register (ISC).

The following operation modes can be specified in 1-bit units.

User’s Manual U16418EJ3V0UD

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CHAPTER 2 PIN FUNCTIONS

(1) Port mode

P10 to P15 function as a 6-bit I/O port. P10 to P15 can be set to input or output in 1-bit units using port mode

register 1 (PM1). Use of an on-chip pull-up resistor can be specified by pull-up resistor option register 1 (PU1).

(2) Control mode

P10 to P15 function as external interrupt request input, serial interface data I/O, clock I/O, timer output, flash

memory programming mode leading-in, and Manchester code output.

(a) SI10

This is a serial data input pin of the serial interface.

(b) SO10

This is a serial data output pin of the serial interface.

(c) SCK10

This is a serial clock I/O pin of the serial interface.

(d) INTP0, INTP1, and INTP3

These are external interrupt request input pins for which the valid edge (rising edge, falling edge, or both

rising and falling edges) can be specified.

(e) RxD6

This is a serial data input pin of the asynchronous serial interface.

(f) TxD6

This is a serial data output pin of the asynchronous serial interface.

(g) TOH0 and TOH1

These are timer output pins.

(h) MCGO

This is a Manchester code output pin.

(i) FLMD1^Note

This is a flash memory programming mode lead-in pin.

Note FLMD1 is available only in the µPD78F0862 and 78F0862A.

2.2.3 P20 to P23 (port 2)

P20 to P23 function as a 4-bit input-only port. These pins also function as pins for A/D converter analog input.

The following operation modes can be specified in 1-bit units.

(1) Port mode

P20 to P23 function as a 4-bit input-only port.

(2) Control mode

P20 to P23 function as A/D converter analog input pins (ANI0 to ANI3). When using these pins as analog input

pins, see (5) ANI0/P20 to ANI3/P23 in 10.6 Cautions for A/D Converter.

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CHAPTER 2 PIN FUNCTIONS

2.2.4 P130 (port 13)

P130 functions as a 1-bit output-only port.

2.2.5 AV^REF

This is an A/D converter reference voltage input pin and a positive power supply pin.

When A/D converter is not used, connect this pin directly to V^DD.

2.2.6 RESET

This is an active-low system reset input pin.

2.2.7 X1 and X2

These are the pins for connecting a resonator for high-speed system clock.

When supplying an external clock, input a signal to the X1 pin and input the inverse signal to the X2 pin.

Remark When the internal high-speed oscillation clock is selected as the high-speed system clock, the X2 [CL2]

pin can be used as a port input pin (P02).

2.2.8 CL1 and CL2

These are the pins for connecting a resistor (R) and capacitor (C) for high-speed system clock.

When supplying an external clock, input a signal to CL1 and input the inverse signal to CL2.

Remark When the internal high-speed oscillation clock is selected as the high-speed system clock, the X2 [CL2]

pin can be used as a port input pin (P02).

2.2.9 V^DD

This is a positive power supply pin.

2.2.10 V^SS

This is a ground potential pin.

Caution V^SSand AVSS are internally connected in the µPD780862 Subseries. Be sure to connect VSS to a

stabilized GND (= 0 V).

2.2.11 FLMD0 and FLMD1 (flash memory versions only)

These are pins for flash memory programming mode lead-in.

Connect FLMD0 to V^SSin the normal operation mode (FLMD1 is not used in the normal operation mode).

Be sure to connect these pins to the flash programmer in the flash memory programming mode.

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CHAPTER 2 PIN FUNCTIONS

2.2.12 IC (mask ROM versions only)

The IC (Internally Connected) pin is provided to set the test mode to check the µPD780862 Subseries at shipment.

Connect it directly to VSS with the shortest possible wire in the normal operation mode.

When a potential difference is produced between the IC pin and the V^SSpin because the wiring between these two

pins is too long or external noise is input to the IC pin, the user’s program may not operate normally.

• Connect the IC pin directly to V^SS.

VSS IC

As short as possible

User’s Manual U16418EJ3V0UD

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CHAPTER 2 PIN FUNCTIONS

2.3 Pin I/O Circuits and Recommended Connection of Unused Pins

Table 2-2 shows the types of pin I/O circuits and the recommended connections of unused pins.

Refer to Figure 2-1 for the configuration of the I/O circuits of each type.

Table 2-2. Pin I/O Circuit Types

Pin Name

P00/TI000/INTP0/MCGO

P01/TI010/TO00/INTP2

P02^{Note 1}/X2 [CL2]

P10/SCK10/(INTP1)

P11/SI10/INTP3

P12/SO10/TOH1/(INTP3)

P13/TxD6/INTP1/(TOH1)/(MCGO)

P14/RxD6/<INTP0>

P15/TOH0/FLMD1^{Note 2}

P20/ANI0 to P23/ANI3

P130

I/O Circuit Type

8-A

I/O

Recommended Connection of Unused Pins

I/O

Input: Independently connect to V^DDor VSS via a resistor.

Output: Leave open.

16

Input

I/O

Connect directly to VSS.

8-A

Input: Independently connect to VDD or VSS via a resistor.

Output: Leave open.

5-A

8-A

5-A

9-C

3-C

2

Input

Output

Input

−

Connect directly to AVREF or VSS.

Leave open.

RESET

−

AVREF

−

Connect directly to V^DD.

X1 [CL1]

16

IC

Connect directly to VSS.

Connect to VSS.

FLMD0^{Note 2}

Notes 1. When the internal high-speed oscillation clock is selected as the high-speed system clock, this pin can be

used as a port input pin.

2. FLMD0 and FLMD1 are available only in the µPD78F0862 and PD78F0862A.

Remarks 1. Functions in parentheses ( ) can be assigned by setting the alternate-function pin switch register (PSEL).

2. Functions in angle brackets < > can be assigned by setting the input switch control register (ISC).

3. Items in brackets [ ] are pin names when using external RC oscillation.

User’s Manual U16418EJ3V0UD

29

CHAPTER 2 PIN FUNCTIONS

Figure 2-1. Pin I/O Circuit List

Type 2

Type 8-A

V^DD

Pull-up

enable

P-ch

IN

V^DD

P-ch

Data

IN/OUT

Schmitt-triggered input with hysteresis characteristics

Output

disable

N-ch

Type 3-C

Type 9-C

VDD

Comparator

+

P-ch

N-ch

IN

P-ch

–

AV^SS

Data

OUT

V^REF

(threshold voltage)

N-ch

Input

enable

Type 5-A

Type 16

V^DD

Feedback

cut-off

Pull-up

enable

P-ch

V^DD

P-ch

Data

IN/OUT

Output

disable

N-ch

X1

X2

Input

enable

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CHAPTER 3 CPU ARCHITECTURE

3.1 Memory Space

Products in the µPD780862 Subseries can each access a 64 KB memory space. Figures 3-1 to 3-3 show the

memory maps.

Caution Regardless of the internal memory capacity, the initial values of the internal memory size

switching register (IMS) of all products in the µPD780862 Subseries are fixed (CFH). Therefore,

set the value corresponding to each product as indicated below.

Table 3-1. Internal Memory Size Switching Register (IMS) Set Value

Internal Memory Size Switching Register (IMS)

µPD780861

42H

µPD780862

04H

µPD78F0862, 78F0862A

Value corresponding to mask ROM version

31

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CHAPTER 3 CPU ARCHITECTURE

Figure 3-1. Memory Map (µPD780861)

FFFFH

Special function registers

(SFR)

256 × 8 bits

FF0 0H

FEFFH

General-purpose

registers

32 × 8 bits

FEE0H

FEDFH

Internal high-speed RAM

512 × 8 bits

1FFFH

FD0 0H

FCFF

H

Program area

CALLF entry area

Program area

Data memory

space

1 0 0 0H

0FFFH

0 8 0 0

H

Reserved

0

7FFH

0 0 8 0H

0 0 7FH

2 0 0 0

1FFF

H

CALLT table area

Vector table area

0 0 4 0H

0 0 3FH

Program

Internal ROM

8192 × 8 bits

memory space

0 0 0 0

0 0 0 0H

H

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CHAPTER 3 CPU ARCHITECTURE

Figure 3-2. Memory Map (µPD780862)

FFFFH

Special function registers

(SFR)

256 × 8 bits

FF0 0H

FEFFH

General-purpose

registers

32 × 8 bits

FEE0H

FEDFH

Internal high-speed RAM

768 × 8 bits

3FFFH

FC0 0

FBFF

Program area

CALLF entry area

Program area

H

Data memory

space

1 0 0 0H

0FFFH

0 8 0 0

H

Reserved

0

7FFH

0 0 8 0H

0 0 7FH

CALLT table area

Vector table area

4 0 0 0

3FFF

H

0 0 4 0H

0 0 3FH

Program

Internal ROM

16384 × 8 bits

memory space

0 0 0 0H

0 0 0 0

H

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CHAPTER 3 CPU ARCHITECTURE

Figure 3-3. Memory Map (µPD78F0862, 78F0862A)

FFFFH

Special function registers

(SFR)

256 × 8 bits

FF0 0H

FEFFH

General-purpose

registers

32 × 8 bits

FEE0H

FEDFH

Internal high-speed RAM

768 × 8 bits

3FFFH

Program area

FC0 0H

FBFF

H

Data memory

space

1 0 0 0H

0FFFH

CALLF entry area

0 8 0 0

H

0

7FFH

Reserved

Program area

0 0 8 1H

0 0 8 0H

0 0 7FH

Option byte area

4 0 0 0

3FFF

CALLT table area

Vector table area

H

0 0 4 0H

0 0 3FH

Program

Flash memory

16384 × 8 bits

memory space

0 0 0 0H

0 0 0 0

H

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CHAPTER 3 CPU ARCHITECTURE

3.1.1 Internal program memory space

The internal program memory space stores the program and table data. Normally, it is addressed with the program

counter (PC).

µPD780862 Subseries products incorporate internal ROM (mask ROM or flash memory), as shown below.

Table 3-2. Internal Memory Capacity

Part Number

Internal ROM

Structure

Capacity

µPD780861

Mask ROM

8192 × 8 bits (0000H to 1FFFH)

µPD780862

16384 × 8 bits

(0000H to 3FFFH)

µPD78F0862, 78F0862A

Flash memory

The internal program memory space is divided into the following areas.

(1) Vector table area

The 64-byte area 0000H to 003FH is reserved as a vector table area. The program start addresses for branch

upon reset input or generation of each interrupt request are stored in the vector table area.

Of the 16-bit address, the lower 8 bits are stored at even addresses and the higher 8 bits are stored at odd

addresses.

Table 3-3. Vector Table

Vector Table Address

0000H

Interrupt Source

Vector Table Address

0014H

Interrupt Source

INTSR6

RESET input, POC, LVI,

clock monitor, WDT

0016H

INTST6

0004H

0006H

0008H

000AH

000CH

000EH

0012H

INTLVI

INTP0

0018H

INTCSI10

INTTMH1

INTTMH0

INTTM50

INTTM000

INTTM010

INTAD

001AH

INTP1

001CH

INTP2

001EH

INTP3

0020H

INTMCG

INTSRE6

0022H

0024H

(2) CALLT instruction table area

The 64-byte area 0040H to 007FH can store the subroutine entry address of a 1-byte call instruction (CALLT).

(3) Option byte area (flash memory version only)

The option byte area is assigned to the 1-byte area of 0080H. For details, refer to CHAPTER 20 MASK

OPTIONS/OPTION BYTE.

(4) CALLF instruction entry area

The area 0800H to 0FFFH can perform a direct subroutine call with a 2-byte call instruction (CALLF).

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CHAPTER 3 CPU ARCHITECTURE

3.1.2 Internal data memory space

µPD780862 Subseries products incorporate the following internal high-speed RAM.

Table 3-4. Internal High-Speed RAM Capacity

Part Number

µPD780861

Internal High-Speed RAM

512 × 8 bits (FD00H to FEFFH)

768 × 8 bits (FC00H to FEFFH)

µPD780862

µPD78F0862, 78F0862A

The 32-byte area FEE0H to FEFFH is assigned to four general-purpose register banks consisting of eight 8-bit

registers per bank.

This area cannot be used as a program area in which instructions are written and executed.

The internal high-speed RAM can also be used as a stack memory.

3.1.3 Special function register (SFR) area

On-chip peripheral hardware special function registers (SFRs) are allocated in the area FF00H to FFFFH (refer to

Table 3-5 Special Function Register List in 3.2.3 Special function registers (SFRs)).

Caution Do not access addresses to which SFRs are not assigned.

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CHAPTER 3 CPU ARCHITECTURE

3.1.4 Data memory addressing

Addressing refers to the method of specifying the address of the instruction to be executed next or the address of

the register or memory relevant to the execution of instructions. The address of the instruction to be executed next is

addressed by the program counter (PC) (for details, refer to 3.3 Instruction Address Addressing).

Several addressing modes are provided for addressing the memory relevant to the execution of instructions for the

µPD780862 Subseries, based on operability and other considerations. For areas containing data memory in

particular, special addressing methods designed for the functions of special function registers (SFR) and general-

purpose registers are available for use. Data memory addressing is illustrated in Figures 3-4 to 3-6. For details of

each addressing mode, refer to 3.4 Operand Address Addressing.

Figure 3-4. Data Memory Addressing (µPD780861)

FFFFH

Special function registers (SFR)

SFR addressing

256 × 8 bits

FF2 0H

FF1F

H

FF0 0H

FEFFH

General-purpose registers

Register addressing

32 × 8 bits

Short direct

addressing

FEE0H

FEDFH

Internal high-speed RAM

512 × 8 bits

FE2 0H

FE1F

H

FD0 0H

FCFF

H

Direct addressing

Register indirect addressing

Based addressing

Based indexed addressing

Reserved

2 0 0 0

1FFF

H

Internal ROM

8192 × 8 bits

0 0 0 0

H

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CHAPTER 3 CPU ARCHITECTURE

Figure 3-5. Data Memory Addressing (µPD780862)

FFFFH

FF2 0H

Special function registers (SFR)

SFR addressing

256 × 8 bits

FF1F

H

FF0 0H

FEFFH

General-purpose registers

Register addressing

32 × 8 bits

Short direct

addressing

FEE0H

FEDFH

Internal high-speed RAM

768 × 8 bits

FE2 0H

FE1F

H

Direct addressing

FC0 0H

FBFF

H

Register indirect addressing

Based addressing

Based indexed addressing

Reserved

4 0 0 0

3FFF

H

Internal ROM

16384 × 8 bits

0 0 0 0

H

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CHAPTER 3 CPU ARCHITECTURE

Figure 3-6. Data Memory Addressing (µPD78F0862, 78F0862A)

FFFFH

FF2 0H

Special function registers (SFR)

SFR addressing

256 × 8 bits

FF1F

H

FF0 0H

FEFFH

General-purpose registers

Register addressing

32 × 8 bits

Short direct

addressing

FEE0H

FEDFH

Internal high-speed RAM

768 × 8 bits

FE2 0H

FE1F

H

Direct addressing

FC0 0H

FBFF

H

Register indirect addressing

Based addressing

Based indexed addressing

Reserved

4 0 0 0

3FFF

H

Flash memory

16384 × 8 bits

0 0 0 0

H

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CHAPTER 3 CPU ARCHITECTURE

3.2 Processor Registers

µPD780862 Subseries products incorporate the following processor registers.

3.2.1 Control registers

The control registers control the program sequence, statuses, and stack memory. The control registers consist of

a program counter (PC), a program status word (PSW), and a stack pointer (SP).

(1) Program counter (PC)

The program counter is a 16-bit register that holds the address information of the next program to be executed.

In normal operation, the PC is automatically incremented according to the number of bytes of the instruction to be

fetched. When a branch instruction is executed, immediate data and register contents are set.

RESET input sets the reset vector table values at addresses 0000H and 0001H to the program counter.

Figure 3-7. Format of Program Counter

15

0

PC

PC15 PC14 PC13 PC12 PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0

(2) Program status word (PSW)

The program status word is an 8-bit register consisting of various flags to be set/reset by instruction execution.

Program status word contents are automatically stacked upon interrupt request generation or PUSH PSW

instruction execution and are restored upon execution of the RETB, RETI, and POP PSW instructions.

RESET input sets the PSW to 02H.

Figure 3-8. Format of Program Status Word

7

0

PSW

IE

Z

RBS1

AC

RBS0

0

ISP

CY

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CHAPTER 3 CPU ARCHITECTURE

(a) Interrupt enable flag (IE)

This flag controls the interrupt request acknowledgment operations of the CPU.

When 0, the IE is set to the interrupt disabled (DI) state, and maskable interrupt requests are all disabled.

When 1, the IE is set to the interrupt enabled (EI) state and interrupt request acknowledgment is controlled

with an in-service priority flag (ISP), an interrupt mask flag for various interrupt sources and a priority

specification flag.

The IE is reset (0) upon DI instruction execution or interrupt acknowledgment and is set (1) upon EI

instruction execution.

(b) Zero flag (Z)

When the operation result is zero, this flag is set (1). It is reset (0) in all other cases.

(c) Register bank select flags (RBS0 and RBS1)

These are 2-bit flags to select one of the four register banks.

In these flags, the 2-bit information that indicates the register bank selected by SEL RBn instruction

execution is stored.

(d) Auxiliary carry flag (AC)

If the operation result has a carry from bit 3 or a borrow at bit 3, this flag is set (1). It is reset (0) in all other

cases.

(e) In-service priority flag (ISP)

This flag manages the priority of acknowledgeable maskable vectored interrupts. When this flag is 0, low-

level vectored interrupt requests specified with a priority specification flag register (PR0L, PR0H, PR1L)

(refer to 14.3 (3) Priority specification flag registers (PR0L, PR0H, PR1L)) are disabled for

acknowledgment. Actual interrupt request acknowledgment is controlled with the interrupt enable flag (IE).

(f) Carry flag (CY)

This flag stores overflow and underflow upon add/subtract instruction execution. It stores the shift-out value

upon rotate instruction execution and functions as a bit accumulator during bit manipulation instruction

execution.

(3) Stack pointer (SP)

This is a 16-bit register to hold the start address of the memory stack area. Only the internal high-speed RAM

area can be set as the stack area.

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CHAPTER 3 CPU ARCHITECTURE

Figure 3-9. Format of Stack Pointer

15

0

SP

SP15 SP14 SP13 SP12 SP11 SP10 SP9 SP8 SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0

The SP is decremented ahead of write (save) to the stack memory and is incremented after read (restore) from

the stack memory.

Each stack operation saves/restores data as shown in Figures 3-10 and 3-11.

Caution Since RESET input makes the SP contents undefined, be sure to initialize the SP before using

the stack.

Figure 3-10. Data to Be Saved to Stack Memory

(a) PUSH rp instruction (when SP = FEE0H)

FEE0H

FEDEH

FEE0H

FEDFH

FEDEH

SP

Register pair upper

Register pair lower

(b) CALL, CALLF, CALLT instructions (when SP = FEE0H)

FEE0H

FEDEH

FEE0H

FEDFH

FEDEH

SP

PC15-PC8

PC7-PC0

(c) Interrupt, BRK instructions (when SP = FEE0H)

FEE0H

FEDFH

FEDEH

FEDDH

SP

PSW

PC15-PC8

PC7-PC0

FEDDH

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CHAPTER 3 CPU ARCHITECTURE

Figure 3-11. Data to Be Restored from Stack Memory

(a) POP rp instruction (when SP = FEDEH)

FEE0H

FEDEH

FEE0H

FEDFH

FEDEH

SP

Register pair upper

Register pair lower

(b) RET instruction (when SP = FEDEH)

FEE0H

FEDEH

FEE0H

FEDFH

FEDEH

SP

PC15-PC8

PC7-PC0

(c) RETI, RETB instructions (when SP = FEDDH)

FEE0H

FEDFH

FEDEH

FEDDH

SP

PSW

PC15-PC8

PC7-PC0

FEDDH

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CHAPTER 3 CPU ARCHITECTURE

3.2.2 General-purpose registers

General-purpose registers are mapped at particular addresses (FEE0H to FEFFH) of the data memory. The

general-purpose registers consists of 4 banks, each bank consisting of eight 8-bit registers (X, A, C, B, E, D, L, and H).

Each register can be used as an 8-bit register, and two 8-bit registers can also be used in a pair as a 16-bit register

(AX, BC, DE, and HL).

These registers can be described in terms of function names (X, A, C, B, E, D, L, H, AX, BC, DE, and HL) and

absolute names (R0 to R7 and RP0 to RP3).

Register banks to be used for instruction execution are set with the CPU control instruction (SEL RBn). Because of

the 4-register bank configuration, an efficient program can be created by switching between a register for normal

processing and a register for interrupts for each bank.

Figure 3-12. Configuration of General-Purpose Registers

(a) Absolute name

16-bit processing

RP3

8-bit processing

R7

FEFFH

FEF8H

BANK0

BANK1

BANK2

BANK3

R6

R5

R4

R3

R2

R1

R0

RP2

RP1

RP0

FEF0H

FEE8H

FEE0H

15

0

7

0

(b) Function name

16-bit processing

8-bit processing

H

FEFFH

FEF8H

BANK0

BANK1

BANK2

BANK3

HL

DE

BC

AX

L

D

E

B

C

A

X

FEF0H

FEE8H

FEE0H

15

0

7

0

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CHAPTER 3 CPU ARCHITECTURE

3.2.3 Special function registers (SFRs)

Unlike a general-purpose register, each special function register has a special function.

SFRs are allocated in the FF00H to FFFFH area.

The special function registers can be manipulated like the general-purpose registers, using operation, transfer, and

bit manipulation instructions. The manipulatable bit units, 1, 8, and 16, depend on the special function register type.

Each manipulation bit unit can be specified as follows.

•

1-bit manipulation

Describe the symbol reserved by the assembler for the 1-bit manipulation instruction operand (sfr.bit).

This manipulation can also be specified with an address.

8-bit manipulation

Describe the symbol reserved by the assembler for the 8-bit manipulation instruction operand (sfr).

This manipulation can also be specified with an address.

16-bit manipulation

Describe the symbol reserved by the assembler for the 16-bit manipulation instruction operand (sfrp).

When specifying an address, describe an even address.

Table 3-5 gives a list of the special function registers. The meanings of items in the table are as follows.

•

Symbol

Symbol indicating the address of a special function register. It is a reserved word in the RA78K0, and is

definedas an sfr variable using the #pragma sfr directive in the CC78K0. When using the RA78K0, ID78K0-NS,

ID78K0, or SM78K0, symbols can be written as an instruction operand.

R/W

<R>

•

Indicates whether the corresponding special function register can be read or written.

R/W: Read/write enable

R:

Read only

W: Write only

•

Manipulatable bit units

Indicates the manipulatable bit unit (1, 8, or 16). “−” indicates a bit unit for which manipulation is not possible.

After reset

Indicates each register status upon RESET input.

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CHAPTER 3 CPU ARCHITECTURE

Table 3-5. Special Function Register List (1/3)

Address

Special Function Register (SFR) Name

Symbol

R/W

Manipulatable Bit Unit

After

Reset

1 Bit

8 Bits

16 Bits

FF00H

FF01H

FF02H

FF08H

FF09H

FF0AH

FF0BH

FF0DH

FF0FH

FF10H

FF11H

FF12H

FF13H

FF14H

FF15H

FF16H

FF17H

FF18H

FF19H

FF1AH

FF1BH

FF20H

FF21H

FF28H

FF29H

FF2AH

FF2BH

FF30H

FF31H

FF48H

FF49H

FF4FH

FF50H

Port register 0

P0

P1

P2

R/W

R

√

−

√

−

√

00H

Port register 1

Port register 2

00H

A/D conversion result register

ADCR

R

Undefined

Receive buffer register 6

Transmit buffer register 6

Port register 13

RXB6

TXB6

P13

R

R/W

R

−

√

−

√

−

√

FFH

00H

Serial I/O shift register 10

16-bit timer counter 00

SIO10

TM00

00H

R

0000H

16-bit timer capture/compare register 000

16-bit timer capture/compare register 010

CR000

CR010

R/W

−

√

0000H

8-bit timer counter 50

TM50

CR50

CMP00

CMP10

CMP01

CMP11

PM0

R

−

√

−

√

−

00H

FFH

00H

01H

8-bit timer compare register 50

8-bit timer H compare register 00

8-bit timer H compare register 10

8-bit timer H compare register 01

8-bit timer H compare register 11

Port mode register 0

R/W

Port mode register 1

PM1

A/D converter mode register

ADM

ADS

Analog input channel specification register

Power-fail comparison mode register

Power-fail comparison threshold register

Pull-up resistor option register 0

Pull-up resistor option register 1

External interrupt rising edge enable register

External interrupt falling edge enable register

Input switch control register

PFM

PFT

PU0

PU1

EGP

EGN

ISC

Asynchronous serial interface operation mode

register 6

ASIM6

FF53H

FF55H

Asynchronous serial interface reception error

status register 6

ASIS6

ASIF6

R

−

√

−

00H

Asynchronous serial interface transmission

status register 6

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CHAPTER 3 CPU ARCHITECTURE

Table 3-5. Special Function Register List (2/3)

Address

Special Function Register (SFR) Name

Symbol

R/W

Manipulatable Bit Unit

After

Reset

1 Bit

8 Bits

√

16 Bits

FF56H

FF57H

FF58H

FF60H

FF61H

FF62H

FF63H

FF64H

FF65H

FF69H

FF6AH

FF6BH

FF6CH

FF6DH

FF70H

FF71H

FF80H

FF81H

FF84H

FF98H

FF99H

FFA0H

FFA1H

FFA2H

FFA3H

Clock selection register 6

CKSR6

R/W

R

−

√

−

√

−

√

−

√

−

√

−

√

00H

FFH

16H

10H

00H

1FH

00H

FFH

07H

00H

Undefined

67H

9AH

00H

Baud rate generator control register 6

Asynchronous serial interface control register 6

MCG control register 0

BRGC6

ASICL6

MC0CTL0

MC0CTL1

MC0CTL2

MC0STR

MC0TXBW MC0TX

MC0BIT

√

MCG control register 1

√

MCG control register 2

√

MCG status register

√

MCG transmit buffer register

MCG transmit bit count specification register

8-bit timer H mode register 0

Timer clock selection register 50

8-bit timer mode control register 50

8-bit timer H mode register 1

8-bit timer H carrier control register 1

Alternate-function pin switch register

Timer clock switch control register

Serial operation mode register 10

Serial clock selection register 10

Transmit buffer register 10

R/W

R

√

TMHMD0

TCL50

√

−

√

TMC50

TMHMD1

TMCYC1

PSEL

√

CSEL

√

CSIM10

CSIC10

SOTB10

WDTM

√

Watchdog timer mode register

Watchdog timer enable register

Internal low-speed oscillation mode register

Main clock mode register

√

WDTE

√

RCM

√

MCM

√

Main OSC control register

MOC

√

Oscillation stabilization time counter status

register

OSTC

√

FFA4H

FFA9H

FFACH

FFBAH

FFBBH

FFBCH

FFBDH

FFBEH

FFBFH

Oscillation stabilization time select register

Clock monitor mode register

OSTS

CLM

R/W

R

−

√

−

√

−

√

−

05H

00H

Reset control flag register

RESF

TMC00

PRM00

CRC00

TOC00

LVIM

00H^Note

16-bit timer mode control register 00

Prescaler mode register 00

R/W

00H

Capture/compare control register 00

16-bit timer output control register 00

Low-voltage detection register

00H

Low-voltage detection level selection register

LVIS

00H

Note This value varies depending on the reset source.

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CHAPTER 3 CPU ARCHITECTURE

Table 3-5. Special Function Register List (3/3)

Address

Special Function Register (SFR) Name

Symbol

R/W

Manipulatable Bit Unit

After

Reset

1 Bit

8 Bits

16 Bits

FFE0H

FFE1H

FFE2H

FFE4H

FFE5H

FFE6H

FFE8H

FFE9H

FFEAH

FFF0H

FFFBH

Interrupt request flag register 0L

Interrupt request flag register 0H

Interrupt request flag register 1L

Interrupt mask flag register 0L

IF0

IF0L R/W

IF0H R/W

R/W

√

−

√

00H

FFH

CFH

00H

1F1L

−

√

MK0 MK0L R/W

MK0H R/W

Interrupt mask flag register 0H

Interrupt mask flag register 1L

MK1L

R/W

−

√

Priority specification flag register 0L

Priority specification flag register 0H

Priority specification flag register 1L

Internal memory size switching register^Note

Processor clock control register

PR0 PR0L R/W

PR0H R/W

PR1L

IMS

R/W

−

PCC

Note The default value of IMS is fixed (CFH) in all products in the µPD780862 Subseries regardless of the internal

memory capacity. Therefore, set the following value to each product.

Internal Memory Size Switching Register (IMS)

µPD780861

42H

µPD780862

04H

µPD78F0862, 78F0862A

Value corresponding to mask ROM version

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CHAPTER 3 CPU ARCHITECTURE

3.3 Instruction Address Addressing

An instruction address is determined by program counter (PC) contents and is normally incremented (+1 for each

byte) automatically according to the number of bytes of an instruction to be fetched each time another instruction is

executed. When a branch instruction is executed, the branch destination information is set to the PC and branched by

the following addressing (for details of instructions, refer to 78K/0 Series Instructions User’s Manual (U12326E)).

3.3.1 Relative addressing

[Function]

The value obtained by adding 8-bit immediate data (displacement value: jdisp8) of an instruction code to the

start address of the following instruction is transferred to the program counter (PC) and branched. The

displacement value is treated as signed two’s complement data (−128 to +127) and bit 7 becomes a sign bit.

In other words, relative addressing consists of relative branching from the start address of the following

instruction to the −128 to +127 range.

This function is carried out when the BR $addr16 instruction or a conditional branch instruction is executed.

[Illustration]

15

0

PC indicates the start address

of the instruction after the BR instruction.

...

PC

+

8

7

6

S

α

jdisp8

15

0

PC

When S = 0, all bits of

When S = 1, all bits of

α

are 0.

are 1.

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CHAPTER 3 CPU ARCHITECTURE

3.3.2 Immediate addressing

[Function]

Immediate data in the instruction word is transferred to the program counter (PC) and branched.

This function is carried out when the CALL !addr16 or BR !addr16 or CALLF !addr11 instruction is executed.

CALL !addr16 and BR !addr16 instructions can be branched to the entire memory space. The CALLF !addr11

instruction is branched to the 0800H to 0FFFH area.

[Illustration]

In the case of CALL !addr16 and BR !addr16 instructions

7

0

CALL or BR

Low Addr.

High Addr.

15

8 7

0

PC

In the case of CALLF !addr11 instruction

7

6

4

3

0

fa^10–8

CALLF

fa^7–0

15

11 10

1

8 7

0

PC

0

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CHAPTER 3 CPU ARCHITECTURE

3.3.3 Table indirect addressing

[Function]

Table contents (branch destination address) of the particular location to be addressed by bits 1 to 5 of the

immediate data of an operation code are transferred to the program counter (PC) and branched.

This function is carried out when the CALLT [addr5] instruction is executed.

This instruction references the address stored in the memory table from 40H to 7FH, and allows branching to

the entire memory space.

[Illustration]

7

6

1

5

1

0

1

Operation code

1

ta4–0

15

8

0

7

0

6

1

5

1

0

Effective address

0

7

Memory (Table)

Low Addr.

0

High Addr.

Effective address+1

15

8

7

0

PC

3.3.4 Register addressing

[Function]

Register pair (AX) contents to be specified with an instruction word are transferred to the program counter (PC)

and branched.

This function is carried out when the BR AX instruction is executed.

[Illustration]

7

0

8

7

0

rp

A

X

15

PC

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CHAPTER 3 CPU ARCHITECTURE

3.4 Operand Address Addressing

The following various methods are available to specify the register and memory (addressing) to undergo

manipulation during instruction execution.

3.4.1 Implied addressing

[Function]

The register which functions as an accumulator (A and AX) among the general-purpose registers is

automatically (implicitly) addressed.

Of the µPD780862 Subseries instruction words, the following instructions employ implied addressing.

Instruction

MULU

Register to Be Specified by Implied Addressing

A register for multiplicand and AX register for product storage

AX register for dividend and quotient storage

DIVUW

ADJBA/ADJBS

ROR4/ROL4

A register for storage of numeric values which become decimal correction targets

A register for storage of digit data which undergoes digit rotation

[Operand format]

Because implied addressing can be automatically employed with an instruction, no particular operand format is

necessary.

[Description example]

In the case of MULU X

With an 8-bit × 8-bit multiply instruction, the product of A register and X register is stored in AX. In this example,

the A and AX registers are specified by implied addressing.

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CHAPTER 3 CPU ARCHITECTURE

3.4.2 Register addressing

[Function]

The general-purpose register to be specified is accessed as an operand with the register bank select flags

(RBS0 and RBS1) and the register specify codes (Rn and RPn) of an operation code.

Register addressing is carried out when an instruction with the following operand format is executed. When an

8-bit register is specified, one of the eight registers is specified with 3 bits in the operation code.

[Operand format]

Identifier

Description

X, A, C, B, E, D, L, H

AX, BC, DE, HL

r

rp

‘r’ and ‘rp’ can be described by absolute names (R0 to R7 and RP0 to RP3) as well as function names (X, A, C,

B, E, D, L, H, AX, BC, DE, and HL).

[Description example]

MOV A, C; when selecting C register as r

Operation code

0

1

0

1

0

Register specify code

INCW DE; when selecting DE register pair as rp

Operation code

1

0

1

0

Register specify code

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CHAPTER 3 CPU ARCHITECTURE

3.4.3 Direct addressing

[Function]

The memory to be manipulated is directly addressed with immediate data in an instruction word becoming an

operand address.

[Operand format]

Identifier

addr16

Description

Label or 16-bit immediate data

[Description example]

MOV A, !0FE00H; when setting !addr16 to FE00H

Operation code

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

OP code

00H

FEH

[Illustration]

7

0

OP code

addr16 (lower)

addr16 (upper)

Memory

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CHAPTER 3 CPU ARCHITECTURE

3.4.4 Short direct addressing

[Function]

The memory to be manipulated in the fixed space is directly addressed with 8-bit data in an instruction word.

This addressing is applied to the 256-byte space FE20H to FF1FH. Internal RAM and special function registers

(SFR) are mapped at FE20H to FEFFH and FF00H to FF1FH, respectively.

The SFR area (FF00H to FF1FH) where short direct addressing is applied is a part of the overall SFR area.

Ports that are frequently accessed in a program and compare and capture registers of the timer/event counter

are mapped in this area, allowing SFRs to be manipulated with a small number of bytes and clocks.

When 8-bit immediate data is at 20H to FFH, bit 8 of an effective address is cleared to 0. When it is at 00H to

1FH, bit 8 is set to 1. Refer to the [Illustration] shown below.

[Operand format]

Identifier

saddr

Description

Immediate data that indicate label or FE20H to FF1FH

saddrp

Immediate data that indicate label or FE20H to FF1FH (even

address only)

[Description example]

MOV 0FE30H, A; when transferring value of A register to saddr (FE30H)

Operation code

1

0

1

0

1

0

1

0

OP code

30H (saddr-offset)

[Illustration]

7

0

OP code

saddr-offset

Short direct memory

15

1

8 7

0

Effective address

1

α

When 8-bit immediate data is 20H to FFH, α = 0

When 8-bit immediate data is 00H to 1FH, α = 1

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CHAPTER 3 CPU ARCHITECTURE

3.4.5 Special function register (SFR) addressing

[Function]

A memory-mapped special function register (SFR) is addressed with 8-bit immediate data in an instruction word.

This addressing is applied to the 240-byte spaces FF00H to FFCFH and FFE0H to FFFFH. However, the SFRs

mapped at FF00H to FF1FH can be accessed with short direct addressing.

[Operand format]

Identifier

sfr

Description

Special function register name

sfrp

16-bit manipulatable special function register name (even address

only)

[Description example]

MOV PM0, A; when selecting PM0 (FF20H) as sfr

Operation code

1

0

1

0

1

0

1

0

1

0

OP code

20H (sfr-offset)

[Illustration]

7

0

OP code

sfr-offset

SFR

15

1

8 7

0

Effective address

1

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CHAPTER 3 CPU ARCHITECTURE

3.4.6 Register indirect addressing

[Function]

Register pair contents specified by a register pair specify code in an operation code and by the register bank

select flags (RBS0 and RBS1) serve as an operand address for addressing the memory. This addressing can

be carried out for all the memory spaces.

[Operand format]

Identifier

Description

−

[DE], [HL]

[Description example]

MOV A, [DE]; when selecting [DE] as register pair

Operation code

1

0

1

0

1

[Illustration]

16

8

7

0

DE

D

E

The memory address

specified with the

register pair DE

Memory

The contents of the memory

addressed are transferred.

7

0

A

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CHAPTER 3 CPU ARCHITECTURE

3.4.7 Based addressing

[Function]

8-bit immediate data is added as offset data to the contents of the base register, that is, the HL register pair in

the register bank specified by the register bank select flags (RBS0 and RBS1) and the sum is used to address

the memory. Addition is performed by expanding the offset data as a positive number to 16 bits. A carry from

the 16th bit is ignored. This addressing can be carried out for all the memory spaces.

[Operand format]

Identifier

Description

−

[HL + byte]

[Description example]

MOV A, [HL + 10H]; when setting byte to 10H

Operation code

1

0

1

0

1

0

1

0

1

0

[Illustration]

16

8

7

0

HL

H

L

+10

Memory

The contents of the memory

addressed are transferred.

7

0

A

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CHAPTER 3 CPU ARCHITECTURE

3.4.8 Based indexed addressing

[Function]

The B or C register contents specified in an instruction word are added to the contents of the base register, that

is, the HL register pair in the register bank specified by the register bank select flags (RBS0 and RBS1), and the

sum is used to address the memory. Addition is performed by expanding the B or C register contents as a

positive number to 16 bits. A carry from the 16th bit is ignored. This addressing can be carried out for all the

memory spaces.

[Operand format]

Identifier

Description

−

[HL + B], [HL + C]

[Description example]

MOV A, [HL + B]; when selecting B register

Operation code

1

0

1

0

1

0

1

[Illustration]

16

8

7

0

HL

H

L

+

7

0

B

Memory

The contents of the memory

addressed are transferred.

7

0

A

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CHAPTER 3 CPU ARCHITECTURE

3.4.9 Stack addressing

[Function]

The stack area is indirectly addressed with the stack pointer (SP) contents.

This addressing method is automatically employed when the PUSH, POP, subroutine call, and return

instructions are executed or the register is saved/restored upon generation of an interrupt request.

With stack addressing, only the internal high-speed RAM area can be accessed.

[Description example]

PUSH DE; when saving DE register

Operation code

1

0

1

0

1

0

1

[Illustration]

7

Memory

0

FEE0H

FEDEH

FEE0H

FEDFH

FEDEH

SP

D

E

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CHAPTER 4 PORT FUNCTIONS

4.1 Port Functions

There are two types of pin I/O buffer power supplies: AV^REFand VDD. The relationship between these power

supplies and the pins is shown below.

Table 4-1. Pin I/O Buffer Power Supplies

Power Supply

AVREF

Corresponding Pins

P20 to P23

Pins other than P20 to P23

VDD

µPD780862 Subseries products are provided with the ports shown in Figure 4-1, which enable variety of control

operations. The functions of each port are shown in Table 4-2.

In addition to the function as digital I/O ports, these ports have several alternate functions. For details of the

alternate functions, refer to CHAPTER 2 PIN FUNCTIONS.

Figure 4-1. Port Types

P00

P02

P20

P23

Port 0

Port 1

Port 2

P10

P15

Port 13

P130

61

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Table 4-2. Port Functions

Pin Name

P00

I/O

Function

After Reset

Input

Alternate Function

TI000/INTP0/MCGO

TI010/TO00/INTP2

I/O

Port 0.

3-bit I/O

port.

Input/output can be specified in 1-bit units.

Use of an on-chip pull-up resistor can be

specified by a software setting.

P01

P02^{Note 1}

P10

Input

I/O

Input-only

Input

X2 [CL2]

Port 1.

SCK10/(INTP1)

SI10/INTP3

6-bit I/O port.

P11

Input/output can be specified in 1-bit units.

Use of an on-chip pull-up resistor can be specified by a

software setting.

P12

SO10/TOH1/(INTP3)

TxD6/INTP1/(TOH1)/(MCGO)

RxD6/<INTP0>

TOH0/FLMD1^{Note 2}

ANI0 to ANI3

P13

P14

P15

P20 to P23

Input

Port 2.

Input

4-bit input-only port.

P130

Output

Port 13.

Output

−

1-bit output-only port.

Notes 1. When the internal high-speed oscillation clock is selected as the high-speed system clock, this pin can be

used as a port input pin.

2. FLMD1 is available only in the µPD78F0862 and 78F0862A.

Remarks 1. Functions in parentheses ( ) can be assigned by setting the alternate-function pin switch register (PSEL).

2. Functions in angle brackets < > can be assigned by setting the input switch control register (ISC).

3. Items in brackets [ ] are pin names when using external RC oscillation.

4.2 Port Configuration

A port includes the following hardware.

Table 4-3. Port Configuration

Item

Control registers

Configuration

Port mode register (PM0, PM1)

Port register (P0 to P2, P13)

Pull-up resistor option register (PU0, PU1)

Alternate-function pin switch register (PSEL)

Input switch control register (ISC)

Ports

Total: 14 (CMOS I/O: 8, CMOS input: 5, CMOS output: 1)

Total: 8 (software control only)

Pull-up resistors

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CHAPTER 4 PORT FUNCTIONS

4.2.1 Port 0

Port 0 is a 3-bit I/O port with an output latch. The P00 and P01 pins can be set to the input mode or output mode

in 1-bit units using port mode register 0 (PM0). The P02 pin is input-only. When the P00 and P01 pins are used as

an input port, use of an on-chip pull-up resistor can be specified by pull-up resistor option register 0 (PU0).

This port can also be used for external interrupt request input, Manchester code output, timer I/O, and

crystal/ceramic resonator connection [RC connection] for high-speed system clock oscillation.

RESET input sets port 0 to input mode.

Figures 4-2 and 4-3 show block diagrams of port 0.

Caution When the internal high-speed oscillation clock is selected as the high-speed system clock by a

mask option (option byte when using a flash memory version), P02 can be used as an input-only

port pin (when a crystal/ceramic or external RC oscillation is selected as the high-speed system

clock by a mask option, P02 becomes a resonator connection pin).

Figure 4-2. Block Diagram of P00 and P01

VDD

WR^PU

PU0

PU00, PU01

P-ch

Alternate

function

RD

WR^PORT

Output latch

(P00, P01)

P00/TI000/INTP0/MCGO

P01/TI010/TO00/INTP2

WRPM

PM0

PM00, PM01

Alternate

function

PU0:

PM0:

RD:

Pull-up resistor option register 0

Port mode register 0

Read signal

WR××: Write signal

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CHAPTER 4 PORT FUNCTIONS

Figure 4-3. Block Diagram of P02

RD

P02/X2[CL2]

RD:

Read signal

Caution If a read instruction is executed while this pin is being used as its alternate function (X2 [CL2]),

the read data is undefined.

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CHAPTER 4 PORT FUNCTIONS

4.2.2 Port 1

Port 1 is a 6-bit I/O port with an output latch. Port 1 can be set to the input mode or output mode in 1-bit units

using port mode register 1 (PM1). When the P10 to P15 pins are used as an input port, use of an on-chip pull-up

resistor can be specified by pull-up resistor option register 1 (PU1).

This port can also be used for external interrupt request input, serial interface data I/O, clock I/O, timer output, and

flash memory programming mode lead-in. P10 to P15 can be assigned as external interrupt request input, timer

output, and Manchester code output by setting the alternate-function pin switch register (PSEL) and input switch

control register (ISC).

RESET input sets port 1 to input mode.

Figures 4-4 to 4-8 show block diagrams of port 1.

Caution To use P10/SCK10/(INTP1), and P12/SO10/TOH1/(INTP3) as general-purpose ports, set serial

operation mode register 10 (CSIM10) and serial clock selection register 10 (CSIC10) to the default

status (00H).

<R>

Figure 4-4. Block Diagram of P10

V

DD

WR^PU

PU1

PU10

P-ch

Alternate

function

RD

WR^PORT

Output latch

(P10)

P10/SCK10/(INTP1)

WRPM

PM1

PM10

Alternate

function

PU1:

PM1:

RD:

Pull-up resistor option register 1

Port mode register 1

Read signal

WR××: Write signal

Remark Functions in parentheses ( ) can be assigned by setting the alternate-function pin switch register (PSEL).

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CHAPTER 4 PORT FUNCTIONS

Figure 4-5. Block Diagram of P11 and P14

VDD

WR^PU

PU1

PU11, PU14

P-ch

Alternate

function

RD

WR^PORT

Output latch

(P11, P14)

P11/SI10/INTP3,

P14/RxD6/<INTP0>

WRPM

PM1

PM11, PM14

PU1:

PM1:

RD:

Pull-up resistor option register 1

Port mode register 1

Read signal

WR××: Write signal

Remark Functions in angle brackets < > can be assigned by setting the input switch control register (ISC).

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CHAPTER 4 PORT FUNCTIONS

Figure 4-6. Block Diagram of P12

VDD

WR^PU

PU1

PU12

P-ch

Alternate

function

RD

WR^PORT

Output latch

(P12)

P12/SO10/TOH1/(INTP3)

WRPM

PM1

PM12

Alternate

function

PU1:

PM1:

RD:

Pull-up resistor option register 1

Port mode register 1

Read signal

WR××: Write signal

Remark Functions in parentheses ( ) can be assigned by setting the alternate-function pin switch register (PSEL).

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CHAPTER 4 PORT FUNCTIONS

Figure 4-7. Block Diagram of P13

V

DD

WR^PU

PU1

PU13

P-ch

Alternate

function (INTP1)

RD

WR^PORT

Output latch

(P13)

P13/TxD6/INTP1/

(TOH1)/(MCGO)

WRPM

PM1

PM13

Alternate

function (TxD6)

Alternate

function (TOH1)

Alternate

function (MCGO)

PU1:

PM1:

RD:

Pull-up resistor option register 1

Port mode register 1

Read signal

WR××: Write signal

Remark Functions in parentheses ( ) can be assigned by setting the alternate-function pin switch register (PSEL).

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CHAPTER 4 PORT FUNCTIONS

Figure 4-8. Block Diagram of P15

VDD

WRPU

RD

PU1

PU15

P-ch

WR^PORT

Output latch

(P15)

P15/TOH0/FLMD1^Note

WRPM

PM1

PM15

Alternate

function

PU1:

PM1:

RD:

Pull-up resistor option register 1

Port mode register 1

Read signal

WR××: Write signal

Note FLMD1 is available only in the µPD78F0862 and 78F0862A.

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CHAPTER 4 PORT FUNCTIONS

4.2.3 Port 2

Port 2 is a 4-bit input-only port.

This port can also be used for A/D converter analog input.

Figure 4-9 shows a block diagram of port 2.

Figure 4-9. Block Diagram of P20 to P23

RD

+

–

P20/ANI0 to P23/ANI3

A/D converter

V

REF

RD:

Read signal

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CHAPTER 4 PORT FUNCTIONS

4.2.4 Port 13

Port 13 is a 1-bit output-only port.

Figure 4-10 shows a block diagram of port 13.

Figure 4-10. Block Diagram of P130

RD

WR^PORT

Output latch

(P130)

P130

RD:

Read signal

WR××: Write signal

Remark P130 outputs a low level at reset, so the output from P130 can be output as a pseudo-CPU reset signal

if P130 is set to output a high level before reset is effected.

4.3 Registers Controlling Port Function

Port functions are controlled by the following five types of registers.

•

Port mode registers (PM0, PM1)

Port registers (P0 to P2, P13)

Pull-up resistor option registers (PU0, PU1)

Alternate-function pin switch register (PSEL)

Input switch control register (ISC)

(1) Port mode registers (PM0 and PM1)

These registers specify input or output mode for the port in 1-bit units.

These registers can be set by a 1-bit or 8-bit memory manipulation instruction.

RESET input sets these registers to FFH.

When port pins are used as alternate-function pins, set the port mode register and output latch as shown in Table

4-4.

Cautions 1. Because P00, P01, P11, and P13 can also be used as external interrupt input pins and P10,

P12, and P14 can be assigned as an external interrupt input by setting the alternate-function

pin switch register (PSEL), when port function output mode is specified to change the

output level, the interrupt request flag is set. Therefore, when these pins are used in output

mode, preset the interrupt mask flags (PMK0 to PMK3) to 1.

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CHAPTER 4 PORT FUNCTIONS

Cautions 2. P02 is an input-only pin. When the internal high-speed oscillation clock is selected as the

high-speed system clock, P02 can be used as a port input pin.

3. When writing to PM0 using an 8-bit memory manipulation instruction, be sure to set bits 2

to 7 to 1.

When writing to PM1 using an 8-bit memory manipulation instruction, be sure to set bits 6

and 7 to 1.

Figure 4-11. Format of Port Mode Register

Symbol

PM0

7

1

6

1

5

1

4

1

3

1

2

1

0

Address After reset R/W

PM01

PM00

FF20H

FFH

R/W

PM1

1

PM15

PM14

PM13

PM12

PM11

PM10

FF21H

FFH

R/W

PMmn

Pmn pin I/O mode selection

(m = 0, 1; n = 0 to 5)

0

1

Output mode (output buffer on)

Input mode (output buffer off)

Table 4-4. Settings of Port Mode Register and Output Latch When Alternate-Function Is Used

Pin Name

Alternate Function

Name

PM××

P××

I/O

P00

P01

P10

TI000

INTP0

MCGO

TI010

TO00

Input

1

0

1

0

1

0

1

0

1

0

1

0

1

0

×

0

×

0

×

1

×

0

×

1

×

0

×

0

Output

Input

Output

Input

INTP2

SCK10

Input

Output

Input

(INTP1)

SI10

P11

P12

Input

INTP3

SO10

Input

Output

Input

TOH1

(INTP3)

TxD6

P13

Output

Input

INTP1

(TOH1)

(MCGO)

RxD6

Output

Input

P14

P15

<INTP0>

TOH0

Input

Output

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CHAPTER 4 PORT FUNCTIONS

Remarks 1. Functions in parentheses ( ) can be assigned by setting the alternate-function pin switch register (PSEL).

2. Functions in angle brackets < > can be assigned by setting the input switch control register (ISC).

3. ×:

Don’t care

PM××: Port mode register

P××: Port output latch

(2) Port registers (P0 to P2, P13)

These registers write the data that is output from the chip when data is output from a port.

If the data is read in the input mode, the pin level is read. If it is read in the output mode, the value of the output

latch is read.

These registers can be set by a 1-bit or 8-bit memory manipulation instruction.

RESET input clears these registers to 00H (but P2 is undefined).

Figure 4-12. Format of Port Register

Symbol

P0

7

0

6

0

5

0

4

0

3

0

2

1

0

Address

FF00H

After reset

R/W

P02^Note

P01

P00

00H (output latch) R/W

7

0

6

0

5

4

3

2

1

0

P1

P15

P14

P13

P12

P11

P10

FF01H

00H (output latch) R/W

7

0

6

0

5

0

4

0

3

2

1

0

P2

P23

P22

P21

P20

FF02H

FF0DH

Undefined

R

7

0

6

0

5

0

4

0

3

0

2

0

1

0

P13

P130

00H (output latch) R/W

Pmn

m = 0 to 2, 13; n = 0 to 7

Output data control (in output mode) Input data read (in input mode)

Input low level

Input high level

0

1

Output 0

Output 1

Note When the internal high-speed oscillation clock is selected as the high-speed system clock, P02 can

be used as a port input pin.

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CHAPTER 4 PORT FUNCTIONS

(3) Pull-up resistor option registers (PU0 and PU1)

These registers specify whether the on-chip pull-up resistors of P00, P01, or P10 to P15 are to be used or not.

An on-chip pull-up resistor can be used in 1-bit units only for the bits set to input mode of the pins of PU0 or PU1

to which the use of an on-chip pull-up resistor has been specified. On-chip pull-up resistors cannot be used for

bits set to output mode and bits used as alternate-function output pins, regardless of the settings of PU0 and PU1.

These registers can be set by a 1-bit or 8-bit memory manipulation instruction.

RESET input clears these registers to 00H.

Caution The P02 pin does not incorporate a pull-up resistor.

Figure 4-13. Format of Pull-up Resistor Option Register

Symbol

PU0

7

0

7

0

6

0

6

0

5

0

4

0

3

0

2

0

1

0

Address After reset R/W

PU01

1

PU00

0

FF30H

00H

R/W

5

4

3

2

PU1

PU15

PU14

PU13

PU12

PU11

PU10

FF31H

00H

R/W

PUmn

Pmn pin on-chip pull-up resistor selection

(m = 0, 1; n = 0 to 5)

0

1

On-chip pull-up resistor not connected

On-chip pull-up resistor connected

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CHAPTER 4 PORT FUNCTIONS

(4) Alternate-function pin switch register (PSEL)

This register is used to select the TOH1, INTP1, INTP3, and MCGO pins.

This register can be set by a 1-bit or 8-bit memory manipulation instruction.

RESET input clears this register to 00H.

Figure 4-14. Format of Alternate-Function Pin Switch Register (PSEL)

Address: FF70H After reset: 00H R/W

Symbol

PSEL

7

0

6

0

<5>

<4>

3

0

2

0

<1>

<0>

TOH1SL

MCGSL

INTP1SL

INTP3SL

TOH1SL

TOH1 pin selection

MCGO pin selection

INTP1 pin selection

INTP3 pin selection

0

1

P12/SO10/TOH1/(INTP3)

P13/TxD6/INTP1/(TOH1)/(MCGO)

MCGSL

0

1

P00/TI000/INTP0/MCGO

P13/TxD6/INTP1/(TOH1)/(MCGO)

INTP1SL

0

1

P13/TxD6/INTP1/(TOH1)/(MCGO)

P10/SCK10/(INTP1)

INTP3SL

0

1

P11/SI10/INTP3

P12/SO10/TOH1/(INTP3)

Cautions 1. Set bit 7 (TMHE1) of 8-bit timer H mode register 1 (TMHMD1) to 0 before

rewriting the TOH1SL bit.

2. Set bit 7 (MC0PWR) of MCG control register 0 (MC0CTL0) to 0 before rewriting

the MCGSL bit.

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(5) Input switch control register (ISC)

<R>

The input switch control register (ISC) is used to receive a status signal transmitted from the master during LIN

(Local Interconnect Network) reception. The input source is switched by setting ISC.

This register can be set by a 1-bit or 8-bit memory manipulation instruction.

RESET input clears this register to 00H.

Figure 4-15. Format of Input Switch Control Register (ISC)

Address: FF4FH After reset: 00H R/W

Symbol

ISC

7

0

6

0

5

0

4

0

3

0

2

0

1

0

ISC1

ISC0

ISC1

TI000 input source selection

0

1

TI000 (P00)

RxD6 (P14)

ISC0

INTP0 input source selection

0

1

INTP0 (P00)

RxD6 (P14)

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4.4 Port Function Operations

Port operations differ depending on whether the input or output mode is set, as shown below.

Caution In the case of 1-bit memory manipulation instruction, although a single bit is manipulated, the

port is accessed as an 8-bit unit. Therefore, on a port with a mixture of input and output pins, the

output latch contents for pins specified as input are undefined, even for bits other than the

manipulated bit.

4.4.1 Writing to I/O port

(1) Output mode

A value is written to the output latch by a transfer instruction, and the output latch contents are output from the pin.

Once data is written to the output latch, it is retained until data is written to the output latch again.

The data of the output latch is cleared by reset.

(2) Input mode

A value is written to the output latch by a transfer instruction, but since the output buffer is off, the pin status does

not change.

Once data is written to the output latch, it is retained until data is written to the output latch again.

4.4.2 Reading from I/O port

(1) Output mode

The output latch contents are read by a transfer instruction. The output latch contents do not change.

(2) Input mode

The pin status is read by a transfer instruction. The output latch contents do not change.

4.4.3 Operations on I/O port

(1) Output mode

An operation is performed on the output latch contents, and the result is written to the output latch. The output

latch contents are output from the pins.

Once data is written to the output latch, it is retained until data is written to the output latch again.

The data of the output latch is cleared by reset.

(2) Input mode

The pin level is read and an operation is performed on its contents. The result of the operation is written to the

output latch, but since the output buffer is off, the pin status does not change.

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5.1 Functions of Clock Generator

The clock generator generates the clock to be supplied to the CPU and peripheral hardware.

The following two system clock oscillators are available.

•

High-speed system clock oscillator

The following three high-speed system clock oscillators are available.

• Crystal/ceramic oscillator:

• External RC oscillator:

Oscillates a clock of 2 to 10 MHz.

Oscillates a clock of 3 to 4 MHz.

Oscillates a clock of 8.0 MHz (TYP.).

• Internal high-speed oscillator:

High-speed system clock oscillation can be selected by a mask option when using a mask ROM version or by

an option byte when using a flash memory version.

For details, refer to CHAPTER 20

MASK

OPTIONS/OPTION BYTE.

Oscillation of the high-speed system clock oscillator is stopped by executing the STOP instruction or setting the

main OSC control register (MOC).

•

Internal low-speed oscillator

The Internal low-speed oscillator oscillates a clock of 240 kHz (TYP.). Oscillation can be stopped by setting the

internal low-speed oscillation mode register (RCM) when “Can be stopped by software” is set by a mask option

(option byte if using a flash memory version) and the high-speed system clock is used as the CPU clock.

5.2 Configuration of Clock Generator

The clock generator includes the following hardware.

Table 5-1. Configuration of Clock Generator

Item

Configuration

Control registers

Processor clock control register (PCC)

Internal low-speed oscillation mode register (RCM)

Main clock mode register (MCM)

Main OSC control register (MOC)

Oscillation stabilization time counter status register (OSTC)

Oscillation stabilization time select register (OSTS)

Oscillators

High-speed system clock oscillator

Internal low-speed oscillator

78

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Figure 5-1. Block Diagram of Clock Generator

Internal bus

Oscillation

Processor clock

control register

(PCC)

Main clock

mode register

(MCM)

Main OSC

control register

(MOC)

stabilization time

select register

(OSTS)

OSTS2 OSTS1 OSTS0

PCC2 PCC1 PCC0

MCS MCM0

MSTOP

STOP

3

Control

signal

High-speed system

clock oscillation

stabilization time counter

Controller

Oscillation

stabilization

time counter

status register

(OSTC)

C

P

U

CPU clock

(f^CPU

MOST MOST MOST MOST MOST

)

11

13

14

15

16

High-speed system

clock oscillator

X1[CL1]

Crystal/ceramic

oscillation^Note

3

f

X

External RC

oscillation^Note

fXH

Prescaler

Operation

X2[CL2]/P02

clock switch

Internal high-speed

oscillation ^Note

f

2

X

f

X

f

X

fX

2²2³2⁴

Internal

low-speed

oscillator

fCPU

fR

Prescaler

Clock to peripheral

hardware

Mask option or option byte

1: Cannot be stopped

0: Can be stopped

Prescaler

8-bit timer H1,

watchdog timer

RSTOP

Internal low-speed

oscillation mode

register (RCM)

Internal bus

Note Select one of these as the high-speed system clock oscillation by a mask option when using a mask ROM

version or by an option byte when using a flash memory version.

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5.3 Registers Controlling Clock Generator

The following six registers are used to control the clock generator.

•

Processor clock control register (PCC)

Internal low-speed oscillation mode register (RCM)

Main clock mode register (MCM)

Main OSC control register (MOC)

Oscillation stabilization time counter status register (OSTC)

Oscillation stabilization time select register (OSTS)

(1) Processor clock control register (PCC)

This register sets the division ratio of the CPU clock.

PCC can be set by a 1-bit or 8-bit memory manipulation instruction.

RESET input clears this register to 00H.

Figure 5-2. Format of Processor Clock Control Register (PCC)

Address: FFFBH After reset: 00H R/W

Symbol

PCC

7

0

6

0

5

0

4

0

3

0

2

1

0

PCC2

PCC1

PCC0

PCC2

PCC1

PCC0

CPU clock selection (fCPU)

MCM0 = 0

MCM0 = 1

0

1

0

1

0

1

0

fX

fR

fXH

0

fX/2

fX/2²

fX/2³

fX/2⁴

fR/2^Note

fXH/2

1

Setting prohibited

fXH/2²

fXH/2³

fXH/2⁴

0

Other

Setting prohibited

Note Setting is prohibited for (A1) grade products and (A2) grade products.

Remarks 1. MCM0: Bit 0 of the main clock mode register (MCM)

2. f^X:

Main system clock oscillation frequency (high-speed system clock oscillation

frequency or Internal low-speed oscillation frequency)

Internal low-speed oscillation frequency

3. f^R:

4. f^XH:

High-speed system clock oscillation frequency

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The fastest instruction can be executed in 2 clocks of the CPU clock in the µPD780862 Subseries. Therefore, the

relationship between the CPU clock (f^CPU) and minimum instruction execution time is as shown in Table 5-2.

Table 5-2. Relationship Between CPU Clock and Minimum Instruction Execution Time

CPU Clock (fCPU)^{Note 1}

Minimum Instruction Execution Time: 2/fCPU

High-Speed System Clock Internal Low-Speed Oscillation

(at 10 MHz Operation^{Note 2}

0.2 µs

)

Clock (at 240 kHz (TYP.) Operation)

8.3 µs (TYP.)

fX

fX/2

0.4 µs

0.8 µs

1.6 µs

3.2 µs

16.6 µs (TYP.)^{Note 3}

fX/2²

fX/2³

fX/2⁴

Setting prohibited

Notes 1. The main clock mode register (MCM) is used to set the CPU clock (high-speed system

clock/internal low-speed oscillation clock) (see Figure 5-4).

2. When crystal/ceramic oscillation is used.

3. Setting is prohibited for (A1) grade products and (A2) grade products.

(2) Internal low-speed oscillation mode register (RCM)

This register sets the operation mode of the internal low-speed oscillator.

This register is valid when “Can be stopped by software” is set for the internal low-speed oscillator by a mask

option, and the high-speed system clock is input as the CPU clock. If “Cannot be stopped” is selected for the

internal low-speed oscillator by a mask option, settings for this register are invalid.

RCM can be set by a 1-bit or 8-bit memory manipulation instruction.

RESET input clears this register to 00H.

Figure 5-3. Format of Internal low-Speed oscillation Mode Register (RCM)

Address: FFA0H After reset: 00H R/W

Symbol

RCM

7

0

6

0

5

0

4

0

3

0

2

0

1

0

<0>

RSTOP

Internal low-speed oscillator oscillating/stopped

0

1

Internal low-speed oscillator oscillating

Internal low-speed oscillator stopped

Caution Make sure that bit 1 (MCS) of the main clock mode register (MCM) is 1 before setting

RSTOP.

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(3) Main clock mode register (MCM)

This register sets the CPU clock (high-speed system clock/internal low-speed oscillation clock).

MCM can be set by a 1-bit or 8-bit memory manipulation instruction.

RESET input clears this register to 00H.

Figure 5-4. Format of Main Clock Mode Register (MCM)

Address: FFA1H After reset: 00H R/W

Symbol

MCM

7

0

6

0

5

0

4

0

3

0

2

0

<1>

<0>

MCS

MCM0

MCS

CPU clock status

0

1

Operates with internal low-speed oscillation clock

Operates with high-speed system clock

MCM0

Selection of clock supplied to CPU

Internal low-speed oscillation clock

High-speed system clock

0

1

Caution When the internal low-speed oscillation clock is selected as the clock to be supplied

to the CPU, the divided clock of the internal low-speed oscillator output (f^X) is

supplied to the peripheral hardware (f^X= 240 kHz (TYP.)).

Operation of the peripheral hardware with the internal low-speed oscillation clock

cannot be guaranteed. Therefore, when the internal low-speed oscillation clock is

selected as the clock supplied to the CPU, do not use peripheral hardware. In

addition, stop the peripheral hardware before switching the clock supplied to the

CPU from the high-speed system clock to the internal low-speed oscillation clock.

Note, however, that the following peripheral hardware can be used when the CPU

operates on the internal low-speed oscillation clock.

• Watchdog timer

• Clock monitor

• 8-bit timer H1 when f^R/2⁷is selected as count clock

• Peripheral hardware selecting external clock as the clock source

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(4) Main OSC control register (MOC)

This register selects the operation mode of the high-speed system clock.

This register is used to stop the high-speed system clock when the CPU is operating with the internal low-speed

oscillation clock. Therefore, this register is valid only when the CPU is operating with the internal low-speed

oscillation clock.

MOC can be set by a 1-bit or 8-bit memory manipulation instruction.

RESET input clears this register to 00H.

Figure 5-5. Format of Main OSC Control Register (MOC)

Address: FFA2H After reset: 00H R/W

Symbol

MOC

<7>

6

0

5

0

4

0

3

0

2

0

1

0

MSTOP

Control of high-speed system clock oscillation

0

1

High-speed system clock oscillating

High-speed system clock stopped

Caution Make sure that bit 1 (MCS) of the main clock mode register (MCM) is 0 before setting

MSTOP.

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(5) Oscillation stabilization time counter status register (OSTC)

This is the status register of the high-speed system clock oscillation stabilization time counter. If the internal low-

speed oscillation clock is used as the CPU clock, the high-speed system clock oscillation stabilization time can be

checked.

OSTC can be read by a 1-bit or 8-bit memory manipulation instruction.

When a reset is released (reset by RESET input, POC, LVI, clock monitor, or WDT), the STOP instruction and

MSTOP (bit 7 of MOC register) = 1 clear OSTC to 00H.

Caution Waiting for the oscillation stabilization time is not required when the external RC oscillation

clock or the internal high-speed oscillation clock is selected as the high-speed system clock by

a mask option (option byte when using a flash memory version). Therefore, the CPU clock can

be switched without reading the OSTC value.

Figure 5-6. Format of Oscillation Stabilization Time Counter Status Register (OSTC)

Address: FFA3H After reset: 00H

R

Symbol

OSTC

7

0

6

0

5

0

4

3

2

1

0

MOST11

MOST13

MOST14

MOST15

MOST16

MOST11

MOST13

MOST14

MOST15

MOST16

Oscillation stabilization time status

2¹¹/fXH min. (204.8 µs min.)

2¹³/fXH min. (819.2 µs min.)

2¹⁴/fXH min. (1.64 ms min.)

2¹⁵/fXH min. (3.28 ms min.)

2¹⁶/fXH min. (6.55 ms min.)

1

0

1

0

1

0

1

0

1

Cautions 1. After the above time has elapsed, the bits are set to 1 in order from MOST11 and

remain 1.

2. If the STOP mode is entered and then released while the internal low-speed

oscillation clock is being used as the CPU clock, set the oscillation stabilization

time as follows.

•

Desired OSTC oscillation stabilization time ≤ Oscillation stabilization time

set by OSTS

The high-speed system clock oscillation stabilization time counter counts only

during the oscillation stabilization time set by OSTS. Therefore, note that only

the statuses during the oscillation stabilization time set by OSTS are set to

OSTC after STOP mode has been released.

3. The wait time when STOP mode is released does not include the time after

STOP mode release until clock oscillation starts (“a” below) regardless of

whether STOP mode is released by RESET input or interrupt generation.

STOP mode release

X1 pin voltage

waveform

a

Remarks 1. Values in parentheses are reference values for operation with f^XH= 10 MHz.

2. f^XH: High-speed system clock oscillation frequency

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(6) Oscillation stabilization time select register (OSTS)

This register is used to select the oscillation stabilization wait time of the high-speed system clock when STOP

mode is released. The wait time set by OSTS is valid only after the STOP mode is released while the high-speed

system clock is selected as the CPU clock. Check the oscillation stabilization time by OSTC after the STOP

mode is released when the internal low-speed oscillation clock is selected as the CPU clock.

OSTS can be set by an 8-bit memory manipulation instruction.

RESET input sets OSTS to 05H.

Figure 5-7. Format of Oscillation Stabilization Time Select Register (OSTS)

Address: FFA4H After reset: 05H R/W

Symbol

OSTS

7

0

6

0

5

0

4

0

3

0

2

1

0

OSTS2

OSTS1

OSTS0

OSTS2

OSTS1

OSTS0

Oscillation stabilization time selection

0

1

0

1

0

1

0

1

2¹¹/fXH (204.8 µs)

2¹³/fXH (819.2 µs)

2¹⁴/fXH (1.64 ms)

2¹⁵/fXH (3.28 ms)

2¹⁶/fXH (6.55 ms)

Setting prohibited

1

0

Other than above

<R>

Cautions 1. To set the STOP mode when the X1 clock is used as the CPU clock, set OSTS

before executing the STOP instruction.

2. Execute the OSTS setting after confirming that the oscillation stabilization time

has elapsed as expected in OSTC.

3. If the STOP mode is entered and then released while the internal low-speed

oscillation clock is being used as the CPU clock, set the oscillation stabilization

time as follows.

•

Desired OSTC oscillation stabilization time ≤ Oscillation stabilization time

set by OSTS

The high-speed system clock oscillation stabilization time counter counts only

during the oscillation stabilization time set by OSTS. Therefore, note that only

the statuses during the oscillation stabilization time set by OSTS are set to

OSTC after STOP mode has been released.

4. The wait time when STOP mode is released does not include the time after STOP

mode release until clock oscillation starts (“a” below) regardless of whether

STOP mode is released by RESET input or interrupt generation.

STOP mode release

X1 pin voltage

waveform

a

Remarks 1. Values in parentheses are reference values for operation with f^XH= 10 MHz.

2. f^XH: High-speed system clock oscillation frequency

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5.4 System Clock Oscillator

5.4.1 High-speed system clock oscillator

The following three high-speed system clock oscillators are available.

•

Crystal/ceramic oscillator:

External RC oscillator:

Oscillates a clock of 2 to 10 MHz.

Oscillates a clock of 3 to 4 MHz.

Oscillates a clock of 8.0 MHz (TYP.).

Internal high-speed oscillator:

High-speed system clock oscillation can be selected by a mask option when using a mask ROM version or by an

option byte when using a flash memory version. For details, refer to CHAPTER 20 MASK OPTIONS/OPTION BYTE.

(1) Crystal/ceramic oscillator

The crystal/ceramic oscillator oscillates via a crystal resonator or ceramic resonator connected to the X1 and X2

pins.

An external clock can be input to the crystal/ceramic oscillator. In this case, input the clock signal to the X1 pin

and input the inverse signal to the X2 pin.

Figure 5-8 shows the external circuit of the crystal/ceramic oscillator.

Figure 5-8. External Circuit of Crystal/Ceramic Oscillator

(a) Crystal/ceramic oscillation

(b) External clock

V

SS

X1

External

clock

X1

X2

Crystal resonator or

ceramic resonator

Caution When using the crystal/ceramic oscillator, wire as follows in the area enclosed by the broken

lines in Figure 5-9 to avoid an adverse effect from wiring capacitance.

•

Keep the wiring length as short as possible.

Do not cross the wiring with the other signal lines. Do not route the wiring near a signal line

through which a high fluctuating current flows.

•

Always make the ground point of the oscillator capacitor the same potential as V^SS. Do not

ground the capacitor to a ground pattern through which a high current flows.

Do not fetch signals from the oscillator.

Figure 5-9 shows examples of incorrect resonator connection.

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Figure 5-9. Examples of Incorrect Resonator Connection

(a) Too long wiring

(b) Crossed signal line

PORT

X2

VSS

X1

X2

VSS

X1

(c) Wiring near high fluctuating current

(d) Current flowing through ground line of oscillator

(potential at points A, B, and C fluctuates)

VDD

PORT

X2

VSS

X1

X2

X1

VSS

High current

A

B

C

High current

(e) Signals are fetched

VSS

X1

X2

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(2) External RC oscillator

The external RC oscillator is oscillated by the resistor (R) and capacitor (C) connected across the CL1 and CL2

pins.

An external clock can also be input to the circuit. In this case, input the clock signal to the CL1 pin, and input the

inverted signal to the CL2 pin.

Figure 5-10 shows the external circuit of the external RC oscillator.

Figure 5-10. External Circuit of External RC Oscillator

(a) RC oscillation

(b) External clock

External

clock

CL1

V

CL1

SS

C

R

CL2

Caution When using the system clock oscillator, wire as follows in the area enclosed by the broken lines

in Figure 5-10 to avoid an adverse effect from wiring capacitance.

•

Keep the wiring length as short as possible.

Do not cross the wiring with the other signal lines. Do not route the wiring near a signal line

through which a high fluctuating current flows.

•

Always make the ground point of the oscillator capacitor the same potential as V^SS. Do not

ground the capacitor to a ground pattern through which a high current flows.

Do not fetch signals from the oscillator.

Figure 5-11 shows examples of incorrect resonator connection.

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Figure 5-11. Examples of Incorrect Resonator Connection

(a) Too long wiring

(b) Crossed signal line

PORT

CL2

VSS

CL1

CL2

V

SS

CL1

(c) Wiring near high fluctuating current

(d) Current flowing through ground line of oscillator

(potential at points A and B fluctuates)

VDD

PORT

CL2

VSS

CL1

CL2

V

SS

CL1

High current

A

B

High current

(e) Signal is fetched

VSS

CL1

CL2

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(3) Internal high-speed oscillator

The µPD780862 Subseries incorporates an internal high-speed oscillator.

When using the internal high-speed oscillator, handle the X1[CL1] and X2[CL2] pins as follows.

X1[CL1]: Connect directly to V^DD.

X2[CL2]: Connect directly to V^SS.

Remark The X2[CL2] pin can be used as an input-only pin (P02).

5.4.2 Internal low-speed oscillator

An internal low-speed oscillator is incorporated in the µPD780862 Subseries.

“Can be stopped by software” or “Cannot be stopped” can be selected by a mask option. The internal low-speed

oscillation clock always oscillates after RESET release (240 kHz (TYP.)).

5.4.3 Prescaler

The prescaler generates various clocks by dividing the high-speed system clock oscillator output (f^X) when the

high-speed system clock is selected as the clock to be supplied to the CPU.

Caution When the internal low-speed oscillation clock is selected as the clock supplied to the CPU, the

prescaler generates various clocks by dividing the internal low-speed oscillator (f^X) (fX = 240 kHz

(TYP.)).

5.5 Clock Generator Operation

The clock generator generates the following clocks and controls the operation modes of the CPU, such as standby

mode.

•

High-speed system clock f^XH

Internal low-speed oscillation clock f^R

CPU clock fCPU

Clock to peripheral hardware

The internal low-speed oscillation clock via the internal low-speed oscillator is used as the CPU clock after reset

release in the µPD780862 Subseries, thus enabling the following.

(1) Enhancement of security function

When the high-speed system clock is set as the CPU clock by the default setting, the device cannot operate if the

high-speed system clock is damaged or badly connected and therefore does not operate after reset is released.

However, the start clock of the CPU is the internal low-speed oscillation clock, so the device can be started by the

internal low-speed oscillation clock after reset release by the clock monitor (detection of high-speed system clock

stop). Consequently, the system can be safely shut down by performing a minimum operation, such as

acknowledging a reset source by software or performing safety processing when there is a malfunction.

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(2) Improvement of performance

Because the CPU can be started without waiting for the high-speed system clock oscillation stabilization time, the

total performance can be improved.

A timing diagram of the CPU default start using the internal low-speed oscillation clock is shown in Figure 5-12.

Figure 5-12. Timing Diagram of CPU Default Start Using Internal Low-Speed Oscillation Clock

High-speed system

clock (f^XH

)

Internal low-speed

oscillation clock (f )

R

RESET

Switched by software

CPU clock

Internal low-speed oscillation clock

High-speed system clock

Operation

stopped: 17/f

R

High-speed system clock oscillation stabilization time:

2¹¹/fXH to 2¹⁶/fXH

Note

Note Check using the oscillation stabilization time counter status register (OSTC).

Waiting for the oscillation stabilization time is not required when the external RC oscillation clock or the

internal high-speed oscillation clock is selected as the high-speed system clock by a mask option (option

byte when using a flash memory version). Therefore, the CPU clock can be switched without reading the

OSTC value.

(a) When the RESET signal is generated, bit 0 of the main clock mode register (MCM) is set to 0 and the internal

low-speed oscillation clock is set as the CPU clock. However, a clock is supplied to the CPU after 17 clocks

of the internal low-speed oscillation clock have elapsed after RESET release (i.e., clock supply to the CPU

stops for 17 clocks). During the RESET period, oscillation of the high-speed system clock and the internal

low-speed oscillation clock is stopped.

(b) After RESET release, the CPU clock can be switched from the internal low-speed oscillation clock to the

high-speed system clock using bit 0 (MCM0) of the main clock mode register (MCM) after the high-speed

system clock oscillation stabilization time has elapsed. At this time, check the oscillation stabilization time

using the oscillation stabilization time counter status register (OSTC) before switching the CPU clock. The

CPU clock status can be checked using bit 1 (MCS) of MCM.

(c) Internal low-speed oscillator can be set to stopped/oscillating using the internal low-speed oscillation mode

register (RCM) when “Can be stopped by software” is selected for the internal low-speed oscillator by a mask

option (option byte when using a flash memory version), if the high-speed system clock is used as the CPU

clock. Make sure that MCS is 1 at this time.

(d) When the internal low-speed oscillation clock is used as the CPU clock, the high-speed system clock can be

set to stopped/oscillating using the main OSC control register (MOC). Make sure that MCS is 0 at this time.

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CHAPTER 5 CLOCK GENERATOR

(e) Select the high-speed system clock oscillation stabilization time (2¹¹/fXH, 2¹³/fXH, 2¹⁴/fXH, 2¹⁵/fXH, 2¹⁶/fXH) using

the oscillation stabilization time select register (OSTS) when releasing STOP mode while the high-speed

system clock is being used as the CPU clock. In addition, when releasing STOP mode while RESET is

released and the internal low-speed oscillation clock is being used as the CPU clock, check the high-speed

system clock oscillation stabilization time using the oscillation stabilization time counter status register

(OSTC).

A status transition diagram of this product is shown in Figure 5-13, and the relationship between the operation

clocks in each operation status and between the oscillation control flag and oscillation status of each clock are shown

in Tables 5-3 and 5-4, respectively.

Figure 5-13. Status Transition Diagram (1/2)

(1) When “Internal low-speed oscillator can be stopped by software” is selected by mask option

HALT^{Note 4}

HALT instruction

Interrupt

HALT

instruction

Interrupt

HALT

instruction

HALT

Interrupt

instruction

Status 4

CPU clock: f^XH

XH: Oscillating

: Oscillation stopped

MSTOP = 1^{Note 3}

Status 3

CPU clock: f^XH

XH: Oscillating

Status 1

CPU clock: f

XH: Oscillation stopped

RSTOP = 0

MCM0 = 0

Status 2

R

CPU clock: f

XH: Oscillating

: Oscillating

R

f

R

RSTOP = 1^{Note 1}

MCM0 = 1^{Note 2}

MSTOP = 0

STOP

R

: Oscillating

f : Oscillating

R

Interrupt

instruction

STOP

Interrupt

STOP

instruction

Interrupt

STOP

instruction

STOP^{Note 4}

Reset release

Reset^{Note 5}

Notes 1. When shifting from status 3 to status 4, make sure that bit 1 (MCS) of the main clock mode register

(MCM) is 1.

2. Before shifting from status 2 to status 3 after reset and STOP are released, check the high-speed

system clock oscillation stabilization time status using the oscillation stabilization time counter status

register (OSTC).

Waiting for the oscillation stabilization time is not required when the external RC oscillation clock or

the internal high-speed oscillation clock is selected as the high-speed system clock by a mask option

(option byte when using a flash memory version). Therefore, the CPU clock can be switched without

reading the OSTC value.

3. When shifting from status 2 to status 1, make sure that MCS is 0.

4. When “Internal low-speed oscillator can be stopped by software” is selected by a mask option (option

byte when using a flash memory version), the watchdog timer stops operating in the HALT and STOP

modes, regardless of the source clock of the watchdog timer. However, the internal low-speed

oscillator does not stop even in the HALT and STOP modes if RSTOP = 0.

5. All reset sources (RESET input, POC, LVI, clock monitor, and WDT)

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CHAPTER 5 CLOCK GENERATOR

Figure 5-13. Status Transition Diagram (2/2)

(2) When “Internal low-speed oscillator cannot be stopped” is selected by mask option

HALT

instruction

Interrupt

HALT instruction

Interrupt

HALT

instruction

Status 3

CPU clock: f^XH

XH: Oscillating

: Oscillating

Status 1

CPU clock: f

fXH: Oscillation stopped

Status 2

CPU clock: f

XH: Oscillating

: Oscillating

MCM0 = 0

MSTOP = 1^{Note 2}

R

f

MCM0 = 1^{Note 1}

MSTOP = 0

R

f : Oscillating

R

STOP

instruction

Interrupt

STOP

instruction

Interrupt

instruction

STOP^{Note 3}

Reset release

Reset^{Note 4}

Notes 1. Before shifting from status 2 to status 3 after reset and STOP are released, check the high-speed

system clock oscillation stabilization time status using the oscillation stabilization time counter status

register (OSTC).

Waiting for the oscillation stabilization time is not required when the external RC oscillation clock or

the internal high-speed oscillation clock is selected as the high-speed system clock by a mask option

(option byte when using a flash memory version). Therefore, the CPU clock can be switched without

reading the OSTC value.

2. When shifting from status 2 to status 1, make sure that MCS is 0.

3. The watchdog timer operates using the internal low-speed oscillation clock even in STOP mode if

“Internal low-speed oscillator cannot be stopped” is selected by a mask option (option byte when

using a flash memory version). Internal low-speed oscillation division can be selected as the count

source of 8-bit timer H1 (TMH1), so clear the watchdog timer using the TMH1 interrupt request before

watchdog timer overflow. If this processing is not performed, an internal reset signal is generated at

watchdog timer overflow after STOP instruction execution.

4. All reset sources (RESET input, POC, LVI, clock monitor, and WDT)

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Table 5-3. Relationship Between Operation Clocks in Each Operation Status

Status

High-Speed

System Clock

Oscillator

Internal Low-Speed Oscillator

CPU Clock

After

Prescaler Clock Supplied to

Peripherals

Release

Note 1

Note 2

RSTOP = 0 RSTOP = 1

MCM0 = 0

MCM0 = 1

Operation

Mode

Reset

Stopped

Internal Low- Stopped

speed

oscillation

clock

STOP

HALT

Oscillating

Stopped

Note 3

Note 4

Stopped

Internal Low- High-speed

Oscillating

speed

system clock

Oscillation

clock

Notes 1. When “Cannot be stopped” is selected for the internal low-speed oscillator by a mask option (option byte

when using a flash memory version).

2. When “Can be stopped by software” is selected for the internal low-speed oscillator by a mask option

(option byte when using a flash memory version).

3. Operates using the CPU clock at STOP instruction execution.

4. Operates using the CPU clock at HALT instruction execution.

Caution The RSTOP setting is valid only when “Can be stopped by software” is set for the internal low-

speed oscillator by a mask option (option byte when using a flash memory version).

Remark RSTOP: Bit 0 of the internal low-speed oscillation mode register (RCM)

MCM0: Bit 0 of the main clock mode register (MCM)

Table 5-4. Oscillation Control Flags and Clock Oscillation Status

High-Speed System Clock

Internal Low-Speed Oscillation

Clock

MSTOP = 1 RSTOP = 0

RSTOP = 1

Stopped

Oscillating

Setting prohibited

Oscillating

MSTOP = 0 RSTOP = 0

RSTOP = 1

Oscillating

Stopped

Caution The RSTOP setting is valid only when “Can be stopped by software” is set for the internal

low-speed oscillator by a mask option (option byte when using a flash memory version).

Remark MSTOP: Bit 7 of the main OSC control register (MOC)

RSTOP: Bit 0 of the internal low-speed oscillation mode register (RCM)

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CHAPTER 5 CLOCK GENERATOR

5.6 Time Required to Switch Between Internal Low-Speed Oscillation Clock and High-Speed

System Clock

Bit 0 (MCM0) of the main clock mode register (MCM) is used to switch between the Internal low-speed oscillation

clock and high-speed system clock.

In the actual switching operation, switching does not occur immediately after MCM0 rewrite; several instructions

are executed using the pre-switch clock after switching MCM0 (see Table 5-5).

Bit 1 (MCS) of MCM is used to judge that operation is performed using either the internal low-speed oscillation

clock or high-speed system clock.

To stop the original clock after changing the clock, wait for the number of clocks shown in Table 5-5 before

stopping.

Table 5-5. Maximum Time Required to Switch Between Internal Low-Speed Oscillation Clock

and High-Speed System Clock

PCC

Maximum Time Required for Switching

PCC2

PCC1

PCC0

High-Speed System Clock → Internal Low-Speed Oscillation

Internal Low-Speed Oscillation Clock → High-Speed System

Clock

fXH/fR + 1 clock

fXH/2fR + 1 clock^Note

Clock

0

1

2 clocks

2 clocks^Note

Note When the internal low-speed oscillation clock is used, setting is prohibited for (A1) grade products

and (A2) grade products.

Caution To calculate the maximum time, set f^Rto 120 kHz.

Remarks 1. PCC: Processor clock control register

2. f^XH: High-speed system clock oscillation frequency

3. f^R: Internal low-speed oscillation frequency

4. The maximum time is the number of clocks of the CPU clock before switching.

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5.7 Time Required for CPU Clock Switchover

The CPU clock can be switched using bits 0 to 2 (PCC0 to PCC2) of the processor clock control register (PCC).

The actual switchover operation is not performed immediately after rewriting to the PCC; operation continues on

the pre-switchover clock for several instructions (see Table 5-6).

Table 5-6. Maximum Time Required for CPU Clock Switchover

Set Value Before

Switchover

Set Value After Switchover

PCC2 PCC1 PCC0 PCC2 PCC1 PCC0 PCC2 PCC1 PCC0 PCC2 PCC1 PCC0 PCC2 PCC1 PCC0 PCC2 PCC1 PCC0

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

16 clocks

8 clocks

16 clocks

8 clocks

4 clocks

16 clocks

8 clocks

4 clocks

2 clocks

8 clocks

4 clocks

2 clocks

1 clock

4 clocks

2 clocks

1 clock

2 clocks

1 clock

Caution When the CPU is operating on the internal low-speed oscillation clock, setting the following

values is prohibited.

• PCC2, PCC1, PCC0 = 0, 0, 1 (setting is permitted only for standard products and (A) grade

products)

• PCC2, PCC1, PCC0 = 0, 1, 0

• PCC2, PCC1, PCC0 = 0, 1, 1

• PCC2, PCC1, PCC0 = 1, 0, 0

Remark The maximum time is the number of clocks of the CPU clock before switching.

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5.8 Clock Selection Flowchart and Register Settings

5.8.1 Changing to high-speed system clock from internal low-speed oscillation clock

Figure 5-14. Changing to High-Speed System Clock from Internal Low-Speed Oscillation Clock (Flowchart)

After releasing reset

PCC = 00H

RCM = 00H

;fCPU = fR

;Oscillating the internal low-speed oscillator

;Operating with the internal low-speed oscillation clock

;Oscillating the high-speed system clock

;Oscillation stabilization time status: 0 s

;Oscillation stabilization time: f^XH/2¹⁶

MCM = 00H

Default value of

register after reset

MOC = 00H

OSTC = 00H

OSTS = 05H^{Note 1}

Processing

OSTC check^{Note 2}

;Checking the high-speed system clock

oscillation stabilization time status

Before lapse of

Internal low-speed

oscillation clock

operation

the high-speed

system clock oscillation

stabilization time

Lapse of the high-speed system clock

oscillation stabilization time

PCC setting

Internal low-speed

oscillation clock

operation

(division operation

of set PCC)

MCM.0←1

MCM.1 (MCS) changes from 0 to 1.

High-speed system clock operation

High-speed

system clock

operation

Notes 1. Setting the OSTS register is valid only when the STOP mode has been released with the system

operating on the high-speed system clock.

2. Check the oscillation stabilization time of the high-speed system clock oscillator using the OSTC

register after the reset signal has been released and select the high-speed system clock operation

after the lapse of specified oscillation stabilization time. Waiting for the oscillation stabilization time is

not required when the external RC oscillation clock or internal high-speed oscillation clock is selected

as the high-speed system clock by a mask option (option byte when using a flash memory version).

Therefore, the CPU clock can be switched without reading the OSTC value.

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5.8.2 Changing from high-speed system clock to internal low-speed oscillation clock

Figure 5-15. Changing from High-Speed System Clock to Internal Low-Speed Oscillation Clock (Flowchart)

Register setting

MCM = 03H

;High-speed system clock operation

with the high-speed

system clock

Yes:RSTOP = 1

RSTOP = 0

High-speed

system clock

operation

RCM.0^Note

;Internal low-speed oscillator stopped?

(RSTOP) = 1?

No:RSTOP = 0

MCM0←0

;Internal low-speed oscillation clock operation

MCM.1 (MCS) changes from 1 to 0.

Internal

low-speed

oscillation clock

operation

Internal low-speed oscillation clock operation

Note This is necessary only when “clock can be stopped by software” is selected for the internal low-speed

oscillator by a mask option (option byte when using a flash memory version).

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5.8.3 Register settings

Table 5-7. Clock and Register Settings

Setting Flag

Status Flag

fCPU

Mode

MCM Register MOC Register RCM Register MCM Register

MCM0

1

MSTOP

0

RSTOP^{Note 1}

0

MCS

1

High-speed

system clock^{Note 2}

Internal low-speed Oscillation clock

oscillating

Internal low-speed Oscillation clock

stopped

1

0

1

Internal low-

speed oscillation

clock

High-speed system clock oscillating

High-speed system clock stopped

0

1

0

Notes 1. This is valid only when “clock can be stopped by software” is selected for the internal low-speed

oscillator by mask option (option byte when using a flash memory version).

2. Do not set MSTOP to 1 during high-speed system clock operation (oscillation of high-speed system

clock is not stopped even when MSTOP = 1).

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CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00

6.1 Functions of 16-Bit Timer/Event Counter 00

16-bit timer/event counter 00 has the following functions.

•

Interval timer

PPG output

Pulse width measurement

External event counter

Square-wave output

One-shot pulse output

(1) Interval timer

16-bit timer/event counter 00 generates an interrupt request at the preset time interval.

(2) PPG output

16-bit timer/event counter 00 can output a rectangular wave whose frequency and output pulse width can be set

freely.

(3) Pulse width measurement

16-bit timer/event counter 00 can measure the pulse width of an externally input signal.

(4) External event counter

16-bit timer/event counter 00 can measure the number of pulses of an externally input signal.

(5) Square-wave output

16-bit timer/event counter 00 can output a square wave with any selected frequency.

(6) One-shot pulse output

16-bit timer/event counter 00 can output a one-shot pulse whose output pulse width can be set freely.

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6.2 Configuration of 16-Bit Timer/Event Counter 00

16-bit timer/event counter 00 includes the following hardware.

Table 6-1. Configuration of 16-Bit Timer/Event Counter 00

Item

Timer counter

Configuration

16 bits (TM00)

Register

16-bit timer capture/compare register: 16 bits (CR000, CR010)

Timer input

Timer output

Control registers

TI000, TI010

TO00, output controller

16-bit timer mode control register 00 (TMC00)

Capture/compare control register 00 (CRC00)

16-bit timer output control register 00 (TOC00)

Prescaler mode register 00 (PRM00)

Port mode register 0 (PM0)

Port register 0 (P0)

Figure 6-1 shows the block diagram.

Figure 6-1. Block Diagram of 16-Bit Timer/Event Counter 00

Internal bus

Capture/compare control

register 00 (CRC00)

CRC002CRC001 CRC000

INTTM000

16-bit timer capture/compare

register 000 (CR000)

Noise

elimi-

nator

TI010/TO00/

P01/INTP2

Match

fX

f

X

/2²

/2⁸

16-bit timer counter 00

(TM00)

Clear

Output

TO00/TI010/

P01/INTP2

controller

Match

Noise

elimi-

nator

2

f

X

Output latch

(P01)

PM01

Noise

elimi-

nator

16-bit timer capture/compare

register 010 (CR010)

TI000/P00/

INTP0/MCGO

INTTM010

CRC002

PRM001

TMC003 TMC002 TMC001OVF00 OSPT00 OSPE00 TOC004 LVS00 LVR00 TOC001 TOE00

PRM000

16-bit timer output

control register 00

(TOC00)

16-bit timer mode

control register 00

(TMC00)

Prescaler mode

register 00 (PRM00)

Internal bus

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(1) 16-bit timer counter 00 (TM00)

TM00 is a 16-bit read-only register that counts count pulses.

The counter is incremented in synchronization with the rising edge of the input clock.

Figure 6-2. Format of 16-Bit Timer Counter 00 (TM00)

Address: FF10H, FF11H

Symbol

After reset: 0000H

FF11H

R

FF10H

TM00

The count value is reset to 0000H in the following cases.

<1> At RESET input

<2> If TMC003 and TMC002 are cleared

<3> If the valid edge of TI000 is input in the mode in which clear & start occurs when inputting the valid edge of

TI000

<4> If TM00 and CR000 match in the mode in which clear & start occurs on a match of TM00 and CR000

<5> OSPT00 is set in one-shot pulse output mode

(2) 16-bit timer capture/compare register 000 (CR000)

CR000 is a 16-bit register that has the functions of both a capture register and a compare register. Whether it is

used as a capture register or as a compare register is set by bit 0 (CRC000) of capture/compare control register

00 (CRC00).

CR000 can be set by a 16-bit memory manipulation instruction.

RESET input clears CR000 to 0000H.

Figure 6-3. Format of 16-Bit Timer Capture/Compare Register 000 (CR000)

Address: FF12H, FF13H

Symbol

After reset: 0000H

FF13H

R/W

FF12H

CR000

•

When CR000 is used as a compare register

The value set in CR000 is constantly compared with the 16-bit timer counter 00 (TM00) count value, and an

interrupt request (INTTM000) is generated if they match. The set value is held until CR000 is rewritten.

When CR000 is used as a capture register

It is possible to select the valid edge of the TI000 pin or the TI010 pin as the capture trigger. The TI000 or

TI010 pin valid edge is set using prescaler mode register 00 (PRM00) (see Table 6-2).

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Table 6-2. CR000 Capture Trigger and Valid Edges of TI000 and TI010 Pins

(1) TI000 pin valid edge selected as capture trigger (CRC001 = 1, CRC000 = 1)

CR000 Capture Trigger

TI000 Pin Valid Edge

ES001

ES000

Falling edge

Rising edge

0

1

0

1

Rising edge

Falling edge

No capture operation

Both rising and falling edges

(2) TI010 pin valid edge selected as capture trigger (CRC001 = 0, CRC000 = 1)

CR000 Capture Trigger

TI010 Pin Valid Edge

ES101

ES100

Falling edge

0

1

0

1

Rising edge

Both rising and falling edges

Remarks 1. Setting ES001, ES000 = 1, 0 and ES101, ES100 = 1, 0 is prohibited.

2. ES001, ES000:

Bits 5 and 4 of prescaler mode register 00 (PRM00)

Bits 7 and 6 of prescaler mode register 00 (PRM00)

ES101, ES100:

CRC001, CRC000: Bits 1 and 0 of capture/compare control register 00 (CRC00)

Cautions 1. Set a value other than 0000H in CR000 in the mode in which clear & start occurs on a match of

TM00 and CR000.

2. In the free-running mode and in the clear mode using the valid edge of TI000, if CR000 is cleared

to 0000H, an interrupt request (INTTM000) is generated when the value of CR000 changes from

0000H to 0001H following TM00 overflow (FFFFH). INTTM000 is generated after TM00 and CR000

match, after the valid edge of the TI010 pin is detected, or after the timer is cleared by a one-shot

trigger.

3. When the valid edge of the TI010 pin is used, P01 cannot be used as the timer output pin (TO00).

When P01 is used as the TO00 pin, the valid edge of the TI010 pin cannot be used.

4. When CR000 is used as a capture register, read data is undefined if the register read time and

capture trigger input conflict (the capture data itself is the correct value).

If a timer count stop and capture trigger input conflict, the captured data is undefined.

5. Do not rewrite CR000 during TM00 operation.

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(3) 16-bit timer capture/compare register 010 (CR010)

CR010 is a 16-bit register that has the functions of both a capture register and a compare register. Whether it is

used as a capture register or a compare register is set by bit 2 (CRC002) of capture/compare control register 00

(CRC00).

CR010 can be set by a 16-bit memory manipulation instruction.

RESET input clears CR010 to 0000H.

Figure 6-4. Format of 16-Bit Timer Capture/Compare Register 010 (CR010)

Address: FF14H, FF15H

Symbol

After reset: 0000H

FF15H

R/W

FF14H

CR010

•

When CR010 is used as a compare register

The value set in CR010 is constantly compared with the 16-bit timer counter 00 (TM00) count value, and an

interrupt request (INTTM010) is generated if they match. The set value is held until CR010 is rewritten.

When CR010 is used as a capture register

It is possible to select the valid edge of the TI000 pin as the capture trigger. The TI000 valid edge is set by

prescaler mode register 00 (PRM00) (see Table 6-3).

Table 6-3. CR010 Capture Trigger and Valid Edge of TI000 Pin (CRC002 = 1)

CR010 Capture Trigger

TI000 Pin Valid Edge

ES001

ES000

Falling edge

0

1

0

1

Rising edge

Both rising and falling edges

Remarks 1. Setting ES001, ES000 = 1, 0 is prohibited.

2. ES001, ES000: Bits 5 and 4 of prescaler mode register 00 (PRM00)

CRC002: Bit 2 of capture/compare control register 00 (CRC00)

Cautions 1. If CR010 is cleared to 0000H, an interrupt request (INTTM010) is generated when the value of

CR010 changes from 0000H to 0001H following TM00 overflow (FFFFH).

INTTM010 is generated after TM00 and CR010 match, after the valid edge of the TI000 pin is

detected, or after the timer is cleared by a one-shot trigger.

2. When CR010 is used as a capture register, read data is undefined if the register read time

and capture trigger input conflict (the capture data itself is the correct value).

If a timer count stop and capture trigger input conflict, the captured data is undefined.

3. CR010 can be rewritten during TM00 operation. For details, see Caution 2 in Figure 6-15.

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6.3 Registers Controlling 16-Bit Timer/Event Counter 00

The following six registers are used to control 16-bit timer/event counter 00.

•

16-bit timer mode control register 00 (TMC00)

Capture/compare control register 00 (CRC00)

16-bit timer output control register 00 (TOC00)

Prescaler mode register 00 (PRM00)

Port mode register 0 (PM0)

Port register 0 (P0)

(1) 16-bit timer mode control register 00 (TMC00)

This register sets the 16-bit timer operating mode, the 16-bit timer counter 00 (TM00) clear mode, and output

timing, and detects an overflow.

TMC00 can be set by a 1-bit or 8-bit memory manipulation instruction.

RESET input clears TMC00 to 00H.

Caution 16-bit timer counter 00 (TM00) starts operation at the moment TMC002 and TMC003 are set to

values other than 0, 0 (operation stop mode), respectively. Set TMC002 and TMC003 to 0, 0 to

stop the operation.

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Figure 6-5. Format of 16-Bit Timer Mode Control Register 00 (TMC00)

Address: FFBAH After reset: 00H R/W

Symbol

TMC00

7

0

6

0

5

0

4

0

3

2

1

<0>

TMC003TMC002TMC001 OVF00

<R>

TMC003 TMC002 TMC001

Operating mode and clear

mode selection

TO00 inversion timing selection

No change

Interrupt request generation

Not generated

0

1

0

1

0

Operation stop

(TM00 cleared to 0)

Free-running mode

Match between TM00 and

CR000 or match between

TM00 and CR010

<When used as compare

register>

Generated on match between

TM00 and CR000, or match

between TM00 and CR010

0

1

Match between TM00 and

CR000, match between TM00

and CR010 or TI000 valid edge

<When used as capture

register>

1

0

1

0

1

0

Clear & start occurs on TI000

valid edge

−

Generated on TI000 valid edge

or TI010 valid edge

Clear & start occurs on match

between TM00 and CR000

Match between TM00 and

CR000 or match between

TM00 and CR010

1

Match between TM00 and

CR000, match between TM00

and CR010 or TI000 valid edge

OVF00

16-bit timer counter 00 (TM00) overflow detection

0

1

Overflow not detected

Overflow detected

Cautions 1. Timer operation must be stopped before writing to bits other than the OVF00 flag.

2. Set the valid edge of the TI000 pin using prescaler mode register 00 (PRM00).

3. If any of the following modes: the mode in which clear & start occurs on match between

TM00 and CR000, the mode in which clear & start occurs at the TI000 valid edge, or free-

running mode is selected, when the set value of CR000 is FFFFH and the TM00 value changes

from FFFFH to 0000H, the OVF00 flag is set to 1.

Remark TO00: 16-bit timer/event counter 00 output pin

TI000: 16-bit timer/event counter 00 input pin

TM00: 16-bit timer counter 00

CR000: 16-bit timer capture/compare register 000

CR010: 16-bit timer capture/compare register 010

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CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00

(2) Capture/compare control register 00 (CRC00)

This register controls the operation of the 16-bit timer capture/compare registers (CR000, CR010).

CRC00 can be set by a 1-bit or 8-bit memory manipulation instruction.

RESET input clears CRC00 to 00H.

Figure 6-6. Format of Capture/Compare Control Register 00 (CRC00)

Address: FFBCH After reset: 00H R/W

Symbol

CRC00

7

0

6

0

5

0

4

0

3

0

2

1

0

CRC002

CRC001

CRC000

CRC002

CR010 operating mode selection

0

1

Operates as compare register

Operates as capture register

CRC001

CR000 capture trigger selection

0

1

Captures on valid edge of TI010

Captures on valid edge of TI000 by reverse phase ^Note

CRC000

CR000 operating mode selection

0

1

Operates as compare register

Operates as capture register

Note The capture operation is not performed if both the rising and falling edges are specified as the valid

edge of TI000.

Cautions 1. Timer operation must be stopped before setting CRC00.

2. When the mode in which clear & start occurs on a match between TM00 and CR000 is

selected with 16-bit timer mode control register 00 (TMC00), CR000 should not be specified

as a capture register.

3. To ensure that the capture operation is performed properly, the capture trigger requires a

pulse two cycles longer than the count clock selected by prescaler mode register 00 (PRM00).

(3) 16-bit timer output control register 00 (TOC00)

This register controls the operation of the 16-bit timer/event counter 00 output controller. It sets/resets the timer

output F/F (LV00), enables/disables output inversion and 16-bit timer/event counter 00 timer output,

enables/disables the one-shot pulse output operation, and sets the one-shot pulse output trigger via software.

TOC00 can be set by a 1-bit or 8-bit memory manipulation instruction.

RESET input clears TOC00 to 00H.

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Figure 6-7. Format of 16-Bit Timer Output Control Register 00 (TOC00)

Address: FFBDH After reset: 00H R/W

Symbol

TOC00

7

0

<6>

<5>

4

<3>

<2>

1

<0>

OSPT00

OSPE00

TOC004

LVS00

LVR00

TOC001

TOE00

OSPT00

One-shot pulse output trigger control via software

0

1

No one-shot pulse trigger

One-shot pulse trigger

OSPE00

One-shot pulse output operation control

0

1

Successive pulse output mode

One-shot pulse output mode^Note

TOC004

Timer output F/F control using match of CR010 and TM00

0

1

Disables inversion operation

Enables inversion operation

LVS00

LVR00

Timer output F/F status setting

0

1

0

1

0

1

No change

Timer output F/F reset (0)

Timer output F/F set (1)

Setting prohibited

TOC001

Timer output F/F control using match of CR000 and TM00

0

1

Disables inversion operation

Enables inversion operation

TOE00

Timer output control

0

1

Disables output (output fixed to level 0)

Enables output

Note The one-shot pulse output mode operates correctly only in the free-running mode and the mode in which

clear & start occurs at the TI000 valid edge. In the mode in which clear & start occurs on a match between

the TM00 register and CR000 register, one-shot pulse output is not possible because an overflow does not

occur.

Cautions 1. Timer operation must be stopped before setting other than TOC004.

2. LVS00 and LVR00 are 0 when they are read.

3. OSPT00 is automatically cleared after data is set, so 0 is read.

4. Do not set OSPT00 to 1 other than in one-shot pulse output mode.

5. A write interval of two cycles or more of the count clock selected by prescaler mode register

00 (PRM00) is required to write to OSPT00 successively.

6. Do not set LVS00 to 1 before TOE00, and do not set LVS00 and TOE00 to 1 simultaneously.

7. Perform <1> and <2> below in the following order, not at the same time.

<1> Set TOC001, TOC004, TOE00, and OSPE00: Timer output operation setting

<2> Set LVS00 and LVR00:

Timer output F/F setting

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(4) Prescaler mode register 00 (PRM00)

This register is used to set the 16-bit timer counter 00 (TM00) count clock and TI000 and TI010 input valid edges.

PRM00 can be set by a 1-bit or 8-bit memory manipulation instruction.

RESET input clears PRM00 to 00H.

Figure 6-8. Format of Prescaler Mode Register 00 (PRM00)

Address: FFBBH After reset: 00H R/W

Symbol

PRM00

7

6

5

4

3

0

2

0

1

0

ES101

ES100

ES001

ES000

PRM001

PRM000

ES101

ES100

TI010 valid edge selection

0

1

0

1

0

1

Falling edge

Rising edge

Setting prohibited

Both falling and rising edges

ES001

ES000

TI000 valid edge selection

0

1

0

1

0

1

Falling edge

Rising edge

Setting prohibited

Both falling and rising edges

PRM001

PRM000

Count clock selection

0

1

0

1

0

1

fX (10 MHz)

fX/2²(2.5 MHz)

fX/2⁸(39.06 kHz)

TI000 valid edge^Note

Note The external clock requires a pulse two cycles longer than the internal clock (f^X).

Cautions 1. When the internal low-speed oscillation clock is selected as the clock to be supplied to the

CPU, the clock of the internal low-speed oscillator is divided and supplied as the count clock.

If the count clock is the internal low-speed oscillation clock, the operation of 16-bit

timer/event counter 00 is not guaranteed. When an external clock is used and when the

internal low-speed oscillation clock is selected and supplied to the CPU, the operation of 16-

bit timer/event counter 00 is not guaranteed, either, because the internal low-speed

oscillation clock is supplied as the sampling clock to eliminate noise.

2. Always set data to PRM00 after stopping the timer operation.

3. If the valid edge of TI000 is to be set for the count clock, do not set the clear & start mode

using the valid edge of TI000 and the capture trigger.

4. If the TI000 or TI010 pin is high level immediately after system reset, the rising edge is

immediately detected after the rising edge or both the rising and falling edges are set as the

valid edge(s) of the TI000 pin or TI010 pin to enable the operation of 16-bit timer counter 00

(TM00). Care is therefore required when pulling up the TI000 or TI010 pin. if the TI000 or

TI010 pin is high level when re-enabling operation after the operation has been stopped, the

rising edge is not detected.

<R>

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Caution 5. When the valid edge of the TI010 pin is used, P01 cannot be used as the timer output pin

(TO00). When P01 is used as the TO00 pin, the valid edge of the TI010 pin cannot be used.

Remarks 1. f^X: High-speed system clock oscillation frequency

2. TI000, TI010: 16-bit timer/event counter 00 input pin

3. Figures in parentheses are for operation with f^X= 10 MHz.

(5) Port mode register 0 (PM0)

This register sets port 0 input/output in 1-bit units.

When using the P01/TO00/TI010/INTP2 pin for timer output, set PM01 and the output latch of P01 to 0.

When using the P01/TO00/TI010/INTP2 pin for timer input, set PM01 to 1. The output latch of P01 at this time

may be 0 or 1.

PM0 can be set by a 1-bit or 8-bit memory manipulation instruction.

RESET input sets PM0 to FFH.

Figure 6-9. Format of Port Mode Register 0 (PM0)

Address: FF20H After reset: FFH R/W

Symbol

PM0

7

1

6

1

5

1

4

1

3

1

2

1

0

PM01 PM00

PM0n

P0n pin I/O mode selection (n = 0, 1)

0

1

Output mode (output buffer on)

Input mode (output buffer off)

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6.4 Operation of 16-Bit Timer/Event Counter 00

6.4.1 Interval timer operation

Setting 16-bit timer mode control register 00 (TMC00) and capture/compare control register 00 (CRC00) as shown

in Figure 6-10 allows operation as an interval timer.

Setting

The basic operation setting procedure is as follows.

<1> Set the CRC00 register (see Figure 6-10 for the set value).

<2> Set any value to the CR000 register.

<3> Set the count clock by using the PRM000 register.

<4> Set the TMC00 register to start the operation (see Figure 6-10 for the set value).

Caution Do not rewrite CR000 during TM00 operation.

Remark For how to enable the INTTM000 interrupt, see CHAPTER 14 INTERRUPT FUNCTIONS.

Interrupt requests are generated repeatedly using the count value preset in 16-bit timer capture/compare register

000 (CR000) as the interval.

When the count value of 16-bit timer counter 00 (TM00) matches the value set in CR000, counting continues with

the TM00 value cleared to 0 and the interrupt request signal (INTTM000) is generated.

The count clock of 16-bit timer/event counter 00 can be selected with bits 0 and 1 (PRM000, PRM001) of prescaler

mode register 00 (PRM00).

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Figure 6-10. Control Register Settings for Interval Timer Operation

(a) 16-bit timer mode control register 00 (TMC00)

7

0

6

0

5

0

4

0

TMC003 TMC002 TMC001 OVF00

TMC00

1

0/1

0

Clears and starts on match between TM00 and CR000.

(b) Capture/compare control register 00 (CRC00)

7

0

6

0

5

0

4

0

3

0

CRC002 CRC001 CRC000

CRC00

0/1

0

CR000 used as compare register

(c) Prescaler mode register 00 (PRM00)

ES101 ES100 ES001 ES000

PRM00 0/1 0/1 0/1 0/1

3

0

2

0

PRM001 PRM000

0/1

Selects count clock.

Setting invalid (setting “10” is prohibited.)

Remark 0/1: Setting 0 or 1 allows another function to be used simultaneously with the interval timer. See the

description of the respective control registers for details.

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Figure 6-11. Interval Timer Configuration Diagram

16-bit timer capture/compare

register 000 (CR000)

INTTM000

f

X

f

X

/2²

/2⁸

16-bit timer counter 00

(TM00)

OVF00^Note

TI000/P00/

INTP0/MCGO

Noise

eliminator

Clear

circuit

fX

Note OVF00 is set to 1 only when CR000 is set to FFFFH.

Figure 6-12. Timing of Interval Timer Operation

t

Count clock

TM00 count value

0000H

0001H

N

0000H 0001H

N

0000H 0001H

N

Timer operation enabled

N

Clear

N

CR000

INTTM000

Interrupt acknowledged

Remark Interval time = (N + 1) × t

N = 0001H to FFFFH (settable range)

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6.4.2 PPG output operation

Setting 16-bit timer mode control register 00 (TMC00) and capture/compare control register 00 (CRC00) as shown

in Figure 6-13 allows operation as PPG (Programmable Pulse Generator) output.

Setting

The basic operation setting procedure is as follows.

<1> Set the CRC00 register (see Figure 6-13 for the set value).

<2> Set any value to the CR000 register as the cycle.

<3> Set any value to the CR010 register as the duty factor.

<4> Set the TOC00 register (see Figure 6-13 for the set value).

<5> Set the count clock by using the PRM00 register.

<6> Set the TMC00 register to start the operation (see Figure 6-13 for the set value).

Caution To change the value of the duty factor (the value of the CR010 register) during operation, see

Caution 2 in Figure 6-15 PPG Output Operation Timing.

Remarks 1. For the setting of the TO00 pin, see 6.3 (5) Port mode register 0 (PM0).

2. For how to enable the INTTM000 interrupt, see CHAPTER 14 INTERRUPT FUNCTIONS.

In the PPG output operation, rectangular waves are output from the TO00 pin with the pulse width and the cycle

that correspond to the count values preset in 16-bit timer capture/compare register 010 (CR010) and in 16-bit timer

capture/compare register 000 (CR000), respectively.

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Figure 6-13. Control Register Settings for PPG Output Operation

(a) 16-bit timer mode control register 00 (TMC00)

7

0

6

0

5

0

4

0

TMC003 TMC002 TMC001 OVF00

TMC00

1

0

Clears and starts on match between TM00 and CR000.

(b) Capture/compare control register 00 (CRC00)

7

0

6

0

5

0

4

0

3

0

CRC002 CRC001 CRC000

CRC00

0

×

0

CR000 used as compare register

CR010 used as compare register

(c) 16-bit timer output control register 00 (TOC00)

7

OSPT00 OSPE00 TOC004 LVS00 LVR00 TOC001 TOE00

TOC00

0

1

0/1

1

Enables TO00 output

Inverts output on match between TM00 and CR000

Specifies initial value of TO00 output F/F (setting “11” is prohibited.)

Inverts output on match between TM00 and CR010

Disables one-shot pulse output

(d) Prescaler mode register 00 (PRM00)

ES101 ES100 ES001 ES000

PRM00 0/1 0/1 0/1 0/1

3

0

2

PRM001 PRM000

0

0/1

Selects count clock.

Setting invalid (setting “10” is prohibited.)

Cautions 1. Values in the following range should be set in CR000 and CR010:

0000H ≤ CR010 < CR000 ≤ FFFFH

2. The cycle of the pulse generated through PPG output (CR000 setting value + 1) has a duty of

(CR010 setting value + 1)/(CR000 setting value + 1).

Remark ×: Don’t care

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Figure 6-14. Configuration Diagram of PPG Output

16-bit timer capture/compare

register 000 (CR000)

fX

f

X

/2²

/2⁸

Clear

circuit

16-bit timer counter 00

(TM00)

f

Noise

eliminator

TI000/P00/

INTP0/MCGO

TO00/TI010/

P01/INTP2

f

X

16-bit timer capture/compare

register 010 (CR010)

Figure 6-15. PPG Output Operation Timing

t

Count clock

TM00 count value

0000H 0001H

M − 1

M

0000H 0001H

N

N − 1

N

Clear

CR000 capture value

CR010 capture value

TO00

N

M

Pulse width: (M + 1) × t

1 cycle: (N + 1) × t

Cautions 1. Do not rewrite CR000 during TM00 operation.

2. In the PPG output operation, change the pulse width (rewrite CR010) during TM00 operation

using the following procedure.

<1> Disable the timer output inversion operation by match of TM00 and CR010 (TOC004 = 0)

<2> Disable the INTTM010 interrupt (TMMK010 = 1)

<3> Rewrite CR010

<4> Wait for 1 cycle of the TM00 count clock

<5> Enable the timer output inversion operation by match of TM00 and CR010 (TOC004 = 1)

<6> Clear the interrupt request flag of INTTM010 (TMIF010 = 0)

<7> Enable the INTTM010 interrupt (TMMK010 = 0)

Remark 0000H ≤ M < N ≤ FFFFH

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6.4.3 Pulse width measurement operation

It is possible to measure the pulse width of the signals input to the TI000 pin and TI010 pin using 16-bit timer

counter 00 (TM00).

There are two measurement methods: measuring with TM00 used in free-running mode, and measuring by

restarting the timer in synchronization with the edge of the signal input to the TI000 pin.

When an interrupt occurs, read the valid value of the capture register, check the overflow flag, and then calculate

the necessary pulse width. Clear the overflow flag after checking it.

The capture operation is not performed until the signal pulse width is sampled in the count clock cycle selected by

prescaler mode register 00 (PRM00) and the valid level of the TI000 or TI010 pin is detected twice, thus eliminating

noise with a short pulse width.

Figure 6-16. CR010 Capture Operation with Rising Edge Specified

Count clock

TM00

N − 3

N − 2

N − 1

N

N + 1

TI000

Rising edge detection

N

CR010

INTTM010

Setting

The basic operation setting procedure is as follows.

<1> Set the CRC00 register (see Figures 6-17, 6-20, 6-22, and 6-24 for the set value).

<2> Set the count clock by using the PRM00 register.

<3> Set the TMC00 register to start the operation (see Figures 6-17, 6-20, 6-22, and 6-24 for the set value).

Caution To use two capture registers, set the TI000 and TI010 pins.

Remarks 1. For the setting of the TI000 (or TI010) pin, see 6.3 (5) Port mode register 0 (PM0).

2. For how to enable the INTTM000 (or INTTM010) interrupt, see CHAPTER 14 INTERRUPT

FUNCTIONS.

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(1) Pulse width measurement with free-running counter and one capture register

When 16-bit timer counter 00 (TM00) is operated in free-running mode, and the edge specified by prescaler mode

register 00 (PRM00) is input to the TI000 pin, the value of TM00 is taken into 16-bit timer capture/compare

register 010 (CR010) and an external interrupt request signal (INTTM010) is set.

Specify both the rising and falling edges by using bits 4 and 5 (ES000 and ES001) of PRM00.

Sampling is performed using the count clock selected by PRM00, and a capture operation is only performed

when the valid level of the TI000 pin is detected twice, thus eliminating noise with a short pulse width.

Figure 6-17. Control Register Settings for Pulse Width Measurement with Free-Running Counter

and One Capture Register (When TI000 and CR010 Are Used)

(a) 16-bit timer mode control register 00 (TMC00)

7

0

6

0

5

0

4

0

TMC003 TMC002 TMC001 OVF00

TMC00

0

1

0/1

0

Free-running mode

(b) Capture/compare control register 00 (CRC00)

7

0

6

0

5

0

4

0

3

0

CRC002 CRC001 CRC000

CRC00

1

0/1

0

CR000 used as compare register

CR010 used as capture register

(c) Prescaler mode register 00 (PRM00)

ES101 ES100 ES001 ES000

PRM00 0/1 0/1

3

0

2

0

PRM001 PRM000

1

0/1

Selects count clock (setting “11” is prohibited).

Specifies both edges for pulse width detection.

Setting invalid (setting “10” is prohibited.)

Remark 0/1: Setting 0 or 1 allows another function to be used simultaneously with pulse width measurement.

See the description of the respective control registers for details.

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Figure 6-18. Configuration Diagram for Pulse Width Measurement with Free-Running Counter

fX

/2²

/2⁸

16-bit timer counter 00

(TM00)

f

X

OVF00

f

16-bit timer capture/compare

register 010 (CR010)

TI000

INTTM010

Internal bus

Figure 6-19. Timing of Pulse Width Measurement Operation with Free-Running Counter

and One Capture Register (with Both Edges Specified)

t

Count clock

0000H 0001H

D0 D0 + 1

D1 D1 + 1

FFFFH 0000H

D2

D3

TM00 count value

TI000 pin input

CR010 capture value

INTTM010

D0

D1

D2

D3

Note

OVF00

(D1 – D0) × t

(10000H – D1 + D2) × t

(D3 – D2) × t

Note Clear OVF00 by software.

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(2) Measurement of two pulse widths with free-running counter

When 16-bit timer counter 00 (TM00) is operated in free-running mode, it is possible to simultaneously measure

the pulse widths of the two signals input to the TI000 pin and the TI010 pin.

When the edge specified by bits 4 and 5 (ES000 and ES001) of prescaler mode register 00 (PRM00) is input to

the TI000 pin, the value of TM00 is taken into 16-bit timer capture/compare register 010 (CR010) and an interrupt

request signal (INTTM010) is set.

Also, when the edge specified by bits 6 and 7 (ES100 and ES101) of PRM00 is input to the TI010 pin, the value

of TM00 is taken into 16-bit timer capture/compare register 000 (CR000) and an interrupt request signal

(INTTM000) is set.

Specify both the rising and falling edges as the edges of the TI000 and TI010 pins, by using bits 4 and 5 (ES000

and ES001) and bits 6 and 7 (ES100 and ES101) of PRM00.

Sampling is performed at the interval selected by prescaler mode register 00 (PRM00), and a capture operation is

only performed when the valid level of the TI000 pin or TI010 pin is detected twice, thus eliminating noise with a

short pulse width.

Figure 6-20. Control Register Settings for Measurement of Two Pulse Widths with Free-Running Counter

(a) 16-bit timer mode control register 00 (TMC00)

7

0

6

0

5

0

4

0

TMC003 TMC002 TMC001 OVF00

TMC00

0

1

0/1

0

Free-running mode

(b) Capture/compare control register 00 (CRC00)

7

0

6

0

5

0

4

0

3

0

CRC002 CRC001 CRC000

CRC00

1

0

1

CR000 used as capture register

Captures valid edge of TI010 pin to CR000

CR010 used as capture register

(c) Prescaler mode register 00 (PRM00)

ES101 ES100 ES001 ES000

3

0

2

0

PRM001 PRM000

PRM00

1

0/1

Selects count clock (setting “11” is prohibited).

Specifies both edges for pulse width detection.

Remark 0/1: Setting 0 or 1 allows another function to be used simultaneously with pulse width measurement.

See the description of the respective control registers for details.

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Figure 6-21. Timing of Pulse Width Measurement Operation with Free-Running Counter

(with Both Edges Specified)

t

Count clock

0000H 0001H

D0 D0 + 1

D1 D1 + 1

FFFFH 0000H

D2 D2 + 1 D2 + 2

D3

TM00 count value

TI000 pin input

D0

D1

D2

CR010 capture value

INTTM010

TI010 pin input

CR000 capture value

INTTM000

D1

D2 + 1

Note

OVF00

(D1 – D0) × t

(10000H – D1 + D2) × t

(D3 – D2) × t

(10000H – D1 + (D2 + 1)) × t

Note Clear OVF00 by software.

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(3) Pulse width measurement with free-running counter and two capture registers

When 16-bit timer counter 00 (TM00) is operated in free-running mode, it is possible to measure the pulse width

of the signal input to the TI000 pin.

When the rising or falling edge specified by bits 4 and 5 (ES000 and ES001) of prescaler mode register 00

(PRM00) is input to the TI000 pin, the value of TM00 is taken into 16-bit timer capture/compare register 010

(CR010) and an interrupt request signal (INTTM010) is set.

Also, when the inverse edge to that of the capture operation is input into CR010, the value of TM00 is taken into

16-bit timer capture/compare register 000 (CR000).

Sampling is performed at the interval selected by prescaler mode register 00 (PRM00), and a capture operation is

only performed when the valid level of the TI000 pin is detected twice, thus eliminating noise with a short pulse

width.

Figure 6-22. Control Register Settings for Pulse Width Measurement with Free-Running Counter and

Two Capture Registers (with Rising Edge Specified)

(a) 16-bit timer mode control register 00 (TMC00)

7

0

6

0

5

0

4

0

TMC003 TMC002 TMC001 OVF00

TMC00

0

1

0/1

0

Free-running mode

(b) Capture/compare control register 00 (CRC00)

7

0

6

0

5

0

4

0

3

0

CRC002 CRC001 CRC000

CRC00

1

CR000 used as capture register

Captures to CR000 at inverse edge

to valid edge of TI000.

CR010 used as capture register

(c) Prescaler mode register 00 (PRM00)

ES101 ES100 ES001 ES000

PRM00 0/1 0/1

3

0

2

0

PRM001 PRM000

0

1

0/1

Selects count clock (setting “11” is prohibited).

Specifies rising edge for pulse width detection.

Setting invalid (setting “10” is prohibited.)

Remark 0/1: Setting 0 or 1 allows another function to be used simultaneously with pulse width measurement.

See the description of the respective control registers for details.

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Figure 6-23. Timing of Pulse Width Measurement Operation with Free-Running Counter

and Two Capture Registers (with Rising Edge Specified)

t

Count clock

TM00 count value

TI000 pin input

0000H 0001H

D0 D0 + 1

D1 D1 + 1

FFFFH 0000H

D2 D2 + 1

D3

CR010 capture value

CR000 capture value

INTTM010

D0

D2

D1

D3

Note

OVF00

(D1 – D0) × t

(10000H – D1 + D2) × t

(D3 – D2) × t

Note Clear OVF00 by software.

(4) Pulse width measurement by means of restart

When input of a valid edge to the TI000 pin is detected, the count value of 16-bit timer counter 00 (TM00) is taken

into 16-bit timer capture/compare register 010 (CR010), and then the pulse width of the signal input to the TI000

pin is measured by clearing TM00 and restarting the count operation.

Either of two edgesrising or fallingcan be selected using bits 4 and 5 (ES000 and ES001) of prescaler mode

register 00 (PRM00).

Sampling is performed using the count clock cycle selected by prescaler mode register 00 (PRM00) and a

capture operation is only performed when the valid level of the TI000 pin is detected twice, thus eliminating noise

with a short pulse width.

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Figure 6-24. Control Register Settings for Pulse Width Measurement by Means of Restart

(with Rising Edge Specified)

(a) 16-bit timer mode control register 00 (TMC00)

7

0

6

0

5

0

4

0

TMC003 TMC002 TMC001 OVF00

TMC00

1

0

0/1

0

Clears and starts at valid edge of TI000 pin.

(b) Capture/compare control register 00 (CRC00)

7

6

5

0

4

0

3

0

CRC002 CRC001 CRC000

CRC00

0

1

CR000 used as capture register

Captures to CR000 at inverse edge to valid edge of TI000.

CR010 used as capture register

(c) Prescaler mode register 00 (PRM00)

ES101 ES100 ES001 ES000

PRM00 0/1 0/1

3

0

2

0

PRM001 PRM000

0

1

0/1

Selects count clock (setting “11” is prohibited).

Specifies rising edge for pulse width detection.

Setting invalid (setting “10” is prohibited.)

Figure 6-25. Timing of Pulse Width Measurement Operation by Means of Restart

(with Rising Edge Specified)

t

Count clock

0000H 0001H

D0 0000H 0001H D1

D2 0000H 0001H

TM00 count value

TI000 pin input

CR010 capture value

D0

D2

D1

CR000 capture value

INTTM010

D1 × t

D2 × t

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CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00

6.4.4 External event counter operation

Setting

The basic operation setting procedure is as follows.

<1> Set the CRC00 register (see Figure 6-26 for the set value).

<2> Set the count clock by using the PRM00 register.

<3> Set any value to the CR000 register (0000H cannot be set).

<4> Set the TMC00 register to start the operation (see Figure 6-26 for the set value).

Remarks 1. For the setting of the TI000 pin, see 6.3 (5) Port mode register 0 (PM0).

2. For how to enable the INTTM000 interrupt, see CHAPTER 14 INTERRUPT FUNCTIONS.

The external event counter counts the number of external clock pulses input to the TI000 pin using 16-bit timer

counter 00 (TM00).

TM00 is incremented each time the valid edge specified by prescaler mode register 00 (PRM00) is input.

When the TM00 count value matches the 16-bit timer capture/compare register 000 (CR000) value, TM00 is

cleared to 0 and the interrupt request signal (INTTM000) is generated.

Input a value other than 0000H to CR000 (a count operation with 1-bit pulse cannot be carried out).

Any of three edgesrising, falling, or both edgescan be selected using bits 4 and 5 (ES000 and ES001) of

prescaler mode register 00 (PRM00).

Sampling is performed using the internal clock (f^X) and an operation is only performed when the valid level of the

TI000 pin is detected twice, thus eliminating noise with a short pulse width.

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Figure 6-26. Control Register Settings in External Event Counter Mode (with Rising Edge Specified)

(a) 16-bit timer mode control register 00 (TMC00)

7

0

6

0

5

0

4

0

TMC003 TMC002 TMC001 OVF00

TMC00

1

0/1

0

Clears and starts on match between TM00 and CR000.

(b) Capture/compare control register 00 (CRC00)

7

0

6

0

5

0

4

0

3

0

CRC002 CRC001 CRC000

CRC00

0/1

0

CR000 used as compare register

(c) Prescaler mode register 00 (PRM00)

ES101 ES100 ES001 ES000

PRM00 0/1 0/1

3

0

2

0

PRM001 PRM000

0

1

Selects external clock.

Specifies rising edge for pulse width detection.

Setting invalid (setting “10” is prohibited.)

Remark 0/1: Setting 0 or 1 allows another function to be used simultaneously with the external event counter.

See the description of the respective control registers for details.

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Figure 6-27. Configuration Diagram of External Event Counter

Internal bus

16-bit timer capture/compare

register 000 (CR000)

Match

Clear

INTTM000

OVF00^Note

Noise eliminator

fX

16-bit timer counter 00 (TM00)

Valid edge of TI000

Note OVF00 is set to 1 only when CR000 is set to FFFFH.

Figure 6-28. External Event Counter Operation Timing (with Rising Edge Specified)

TI000 pin input

TM00 count value

CR000

0000H 0001H 0002H 0003H 0004H 0005H

N − 1

N

0000H 0001H 0002H 0003H

N

INTTM000

Caution When reading the external event counter count value, TM00 should be read.

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CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00

6.4.5 Square-wave output operation

Setting

The basic operation setting procedure is as follows.

<1> Set the count clock by using the PRM00 register.

<2> Set the CRC00 register (see Figure 6-29 for the set value).

<3> Set the TOC00 register (see Figure 6-29 for the set value).

<4> Set any value to the CR000 register (0000H cannot be set).

<5> Set the TMC00 register to start the operation (see Figure 6-29 for the set value).

Caution Do not rewrite CR000 during TM00 operation.

Remarks 1. For the setting of the TO00 pin, see 6.3 (5) Port mode register 0 (PM0).

2. For how to enable the INTTM000 interrupt, see CHAPTER 14 INTERRUPT FUNCTIONS.

A square wave with any selected frequency can be output at intervals determined by the count value preset to 16-

bit timer capture/compare register 000 (CR000).

The TO00 pin output status is inverted at intervals determined by the count value preset to CR000 +1 by setting bit

0 (TOE00) and bit 1 (TOC001) of 16-bit timer output control register 00 (TOC00) to 1. This enables a square wave

with any selected frequency to be output.

Figure 6-29. Control Register Settings in Square-Wave Output Mode (1/2)

(a) 16-bit timer mode control register 00 (TMC00)

7

0

6

0

5

0

4

0

TMC003 TMC002 TMC001 OVF00

TMC00

1

0

Clears and starts on match between TM00 and CR000.

(b) Capture/compare control register 00 (CRC00)

7

0

6

0

5

0

4

0

3

0

CRC002 CRC001 CRC000

CRC00

0/1

0

CR000 used as compare register

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CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00

Figure 6-29. Control Register Settings in Square-Wave Output Mode (2/2)

(c) 16-bit timer output control register 00 (TOC00)

7

0

OSPT00 OSPE00 TOC004 LVS00 LVR00 TOC001 TOE00

TOC00

0

0/1

1

Enables TO00 output.

Inverts output on match between TM00 and CR000.

Specifies initial value of TO00 output F/F (setting “11” is prohibited).

Does not invert output on match between TM00 and CR010.

Disables one-shot pulse output.

(d) Prescaler mode register 00 (PRM00)

ES101 ES100 ES001 ES000

PRM00 0/1 0/1 0/1 0/1

3

0

2

0

PRM001 PRM000

0/1

Selects count clock.

Setting invalid (setting “10” is prohibited.)

Remark 0/1: Setting 0 or 1 allows another function to be used simultaneously with square-wave output. See the

description of the respective control registers for details.

Figure 6-30. Square-Wave Output Operation Timing

Count clock

TM00 count value

CR000

0000H 0001H 0002H

N − 1

N

0000H 0001H 0002H

N − 1

N

0000H

N

INTTM000

TO00 pin output

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CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00

6.4.6 One-shot pulse output operation

16-bit timer/event counter 00 can output a one-shot pulse in synchronization with a software trigger or an external

trigger (TI000 pin input).

Setting

The basic operation setting procedure is as follows.

<1> Set the count clock by using the PRM00 register.

<2> Set the CRC00 register (see Figures 6-31 and 6-33 for the set value).

<3> Set the TOC00 register (see Figures 6-31 and 6-33 for the set value).

<4> Set any value to the CR000 and CR010 registers (0000H cannot be set).

<5> Set the TMC00 register to start the operation (see Figures 6-31 and 6-33 for the set value).

Remarks 1. For the setting of the TO00 pin, see 6.3 (5) Port mode register 0 (PM0).

2. For how to enable the INTTM000 (if necessary, INTTM010) interrupt, see CHAPTER 14

INTERRUPT FUNCTIONS.

(1) One-shot pulse output with software trigger

A one-shot pulse can be output from the TO00 pin by setting 16-bit timer mode control register 00 (TMC00),

capture/compare control register 00 (CRC00), and 16-bit timer output control register 00 (TOC00) as shown in

Figure 6-31, and by setting bit 6 (OSPT00) of the TOC00 register to 1 by software.

By setting the OSPT00 bit to 1, 16-bit timer/event counter 00 is cleared and started, and its output becomes

active at the count value (N) set in advance to 16-bit timer capture/compare register 010 (CR010). After that, the

output becomes inactive at the count value (M) set in advance to 16-bit timer capture/compare register 000

(CR000)^Note

.

Even after the one-shot pulse has been output, the TM00 register continues its operation. To stop the TM00

register, the TMC003 and TMC002 bits of the TMC00 register must be set to 00.

Note The case where N < M is described here. When N > M, the output becomes active with the CR000

register and inactive with the CR010 register. Do not set N to M.

<R>

Cautions 1. Do not set the OSPT00 bit to 1 again while the one-shot pulse is being output. To output the

one-shot pulse again, wait until the current one-shot pulse output is completed.

2. When using the one-shot pulse output of 16-bit timer/event counter 00 with a software

trigger, do not change the level of the TI000 pin or its alternate-function port pin.

Because the external trigger is valid even in this case, the timer is cleared and started even

at the level of the TI000 pin or its alternate-function port pin, resulting in the output of a

pulse at an undesired timing.

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CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00

Figure 6-31. Control Register Settings for One-Shot Pulse Output with Software Trigger

(a) 16-bit timer mode control register 00 (TMC00)

7

0

6

0

5

0

4

0

TMC003 TMC002 TMC001 OVF00

TMC00

0

1

0

Free-running mode

(b) Capture/compare control register 00 (CRC00)

7

6

5

0

4

0

3

0

CRC002 CRC001 CRC000

CRC00

0

0/1

0

CR000 used as compare register

CR010 used as compare register

(c) 16-bit timer output control register 00 (TOC00)

7

0

OSPT00 OSPE00 TOC004 LVS00

LVR00 TOC001 TOE00

TOC00

0

1

0/1

1

Enables TO00 output

Inverts output upon match

between TM00 and CR000

Specifies initial value of TO00

output F/F (setting “11” is prohibited.)

Inverts output upon match

between TM00 and CR010

Sets one-shot pulse output mode

Set to 1 for output

(d) Prescaler mode register 00 (PRM00)

ES101

0/1

ES100

0/1

ES001

0/1

ES000

0/1

3

0

2

0

PRM001 PRM000

0/1 0/1

PRM00

Selects count clock.

Setting invalid

(setting “10” is prohibited.)

Setting invalid

(setting “10” is prohibited.)

Caution Do not set the CR000 and CR010 registers to 0000H.

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CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00

Figure 6-32. Timing of One-Shot Pulse Output Operation with Software Trigger

Set TMC00 to 04H

(TM00 count starts)

Count clock

TM00 count

CR010 set value

CR000 set value

0000H 0001H

N

N + 1 0000H

N – 1

N

M – 1

M

M + 1 M + 2

N

M

OSPT00

INTTM010

INTTM000

TO00 pin output

Caution 16-bit timer counter 00 starts operating as soon as the TMC003 and TMC002 bits are set to a

value other than 00 (operation stop mode).

Remark N < M

(2) One-shot pulse output with external trigger

A one-shot pulse can be output from the TO00 pin by setting 16-bit timer mode control register 00 (TMC00),

capture/compare control register 00 (CRC00), and 16-bit timer output control register 00 (TOC00) as shown in

Figure 6-33, and by using the valid edge of the TI000 pin as an external trigger.

The valid edge of the TI000 pin is specified by bits 4 and 5 (ES000, ES001) of prescaler mode register 00

(PRM00). The rising, falling, or both the rising and falling edges can be specified.

When the valid edge of the TI000 pin is detected, the 16-bit timer/event counter is cleared and started, and the

output becomes active at the count value set in advance to 16-bit timer capture/compare register 010 (CR010).

After that, the output becomes inactive at the count value set in advance to 16-bit timer capture/compare register

000 (CR000)^Note

.

Note The case where N < M is described here. When N > M, the output becomes active with the CR000

register and inactive with the CR010 register. Do not set N to M.

<R>

Caution Do not input the external trigger again while the one-shot pulse is being output. To output the

one-shot pulse again, wait until the current one-shot pulse output is completed

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Figure 6-33. Control Register Settings for One-Shot Pulse Output with External Trigger

(with Rising Edge Specified)

(a) 16-bit timer mode control register 00 (TMC00)

7

0

6

0

5

0

4

0

TMC003 TMC002 TMC001 OVF00

TMC00

1

0

Clears and starts at

valid edge of TI000 pin

(b) Capture/compare control register 00 (CRC00)

7

6

5

0

4

0

3

0

CRC002 CRC001 CRC000

0/1

CRC00

0

CR000 used as compare register

CR010 used as compare register

(c) 16-bit timer output control register 00 (TOC00)

OSPT00 OSPE00 TOC004 LVS00

LVR00 TOC001 TOE00

0/1

7

TOC00

0

1

0/1

1

Enables TO00 output

Inverts output upon match

between TM00 and CR000

Specifies initial value of

TO00 output F/F (setting “11” is prohibited.)

Inverts output upon match

between TM00 and CR010

Sets one-shot pulse output mode

(d) Prescaler mode register 00 (PRM00)

ES101

0/1

ES100

0/1

ES001

0

ES000

1

3

0

2

0

PRM001 PRM000

0/1 0/1

PRM00

Selects count clock

(setting “11” is prohibited).

Specifies the rising edge

for pulse width detection.

Setting invalid

(setting “10” is prohibited.)

Caution Do not set the CR000 and CR010 registers to 0000H.

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CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00

Figure 6-34. Timing of One-Shot Pulse Output Operation with External Trigger (with Rising Edge Specified)

When TMC00 is set to 08H

(TM00 count starts)

t

Count clock

TM00 count value

CR010 set value

CR000 set value

0000H 0001H

0000H

N

N + 1 N + 2

M − 2 M − 1

M

M + 1 M + 2

N

M

TI000 pin input

INTTM010

INTTM000

TO00 pin output

Caution 16-bit timer counter 00 starts operating as soon as the TMC002 and TMC003 bits are set to a

value other than 00 (operation stop mode).

Remark N < M

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CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00

6.5 Cautions for 16-Bit Timer/Event Counter 00

(1) Timer start errors

An error of up to one clock may occur in the time required for a match signal to be generated after timer start.

This is because 16-bit timer counter 00 (TM00) is started asynchronously to the count clock.

Figure 6-35. Start Timing of 16-Bit Timer Counter 00 (TM00)

Count clock

0000H

0001H

0002H

0003H

0004H

TM00 count value

Timer start

(2) Setting of 16-bit timer capture/compare register 000

In the mode in which clear & start occurs on match between TM00 and CR000, set 16-bit timer capture/compare

register 000 (CR000) to a value other than 0000H. This means a 1-pulse count operation cannot be performed

when 16-bit timer/event counter 00 is used as an external event counter.

(3) Capture register data retention timing

The values of 16-bit timer capture/compare registers 000 and 010 (CR000 and CR010) are not guaranteed after

16-bit timer/event counter 00 has been stopped.

(4) Valid edge setting

Set the valid edge of the TI000 pin after setting bits 2 and 3 (TMC002 and TMC003) of 16-bit timer mode control

register 00 (TMC00) to 0, 0, respectively, and then stopping timer operation. The valid edge is set using bits 4

and 5 (ES000 and ES001) of prescaler mode register 00 (PRM00).

(5) Re-triggering one-shot pulse

(a) One-shot pulse output by software

Do not set the OSPT00 bit to 1 again while a one-shot pulse is being output.

To output the one-shot pulse again, wait until the current one-shot pulse output is completed.

<R>

(b) One-shot pulse output with external trigger

Do not input the external trigger again while a one-shot pulse is being output.

To output the one-shot pulse again, wait until the current one-shot pulse output is completed.

(c) One-shot pulse output function

When using the one-shot pulse output of 16-bit timer/event counter 00 with a software trigger, do not change

the level of the TI000 pin or its alternate function port pin.

Because the external trigger is valid even in this case, the timer is cleared and started even at the level of the

TI000 pin or its alternate function port pin, resulting in the output of a pulse at an undesired timing.

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CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00

(6) Operation of OVF00 flag

<1> The OVF00 flag is also set to 1 in the following case.

When any of the following modes: the mode in which clear & start occurs on a match between TM00 and

CR000, the mode in which clear & start occurs on a TI000 valid edge, or the free-running mode, is selected

↓

CR000 is set to FFFFH

↓

TM00 is counted up from FFFFH to 0000H.

Figure 6-36. Operation Timing of OVF00 Flag

Count clock

CR000

TM00

FFFFH

FFFEH

FFFFH

0000H

0001H

OVF00

INTTM000

<2> Even if the OVF00 flag is cleared before the next count clock is counted (before TM00 becomes 0001H)

after the occurrence of TM00 overflow, the OVF00 flag is re-set newly and clear is disabled.

(7) Conflicting operations

When a read period of the 16-bit timer capture/compare register (CR000/CR010) and a capture trigger

input(CR000/CR010 used as capture register) conflict, the priority is given to the capture trigger input. The data

read from CR000/CR010 is undefined.

Figure 6-37. Capture Register Data Retention Timing

Count clock

TM00 count value

Edge input

N

N + 1

N + 2

M

M + 1

M + 2

INTTM010

Capture read signal

CR010 capture value

X

N + 2

M + 1

Capture

Capture, but

read value is

not guaranteed

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CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00

(8) Timer operation

<1> Even if 16-bit timer counter 00 (TM00) is read, the value is not captured by 16-bit timer capture/compare

register 010 (CR010).

<2> Regardless of the CPU’s operation mode, when the timer stops, the input signals to the TI000/TI010 pins

are not acknowledged.

<3> The one-shot pulse output mode operates correctly only in the free-running mode and the mode in which

clear & start occurs at the TI000 valid edge. In the mode in which clear & start occurs on a match between

TM00 and CR000, one-shot pulse output is not possible because an overflow does not occur.

(9) Capture operation

<1> If TI000 valid edge is specified as the count clock, a capture operation by the capture register specified as

the trigger for TI000 is not possible.

<2> To ensure the reliability of the capture operation, the capture trigger requires a pulse two cycles longer than

the count clock selected by prescaler mode register 00 (PRM00).

<3> The capture operation is performed at the falling edge of the count clock. An interrupt request input

(INTTM000/INTTM010), however, is generated at the rise of the next count clock.

(10) Compare operation

A capture operation may not be performed for CR000/CR010 set in compare mode even if a capture trigger has

been input.

(11) Edge detection

<1> If the TI000 or TI010 pin is high level immediately after system reset and the rising edge or both the rising

and falling edges are specified as the valid edge of the TI000 or TI010 pin to enable the 16-bit timer counter

00 (TM00) operation, a rising edge is detected immediately after the operation is enabled. Be careful

therefore when pulling up the TI000 or TI010 pin. However, if the TI000 or TI010 pin is high level when

reenabling operation after the operation has been stopped, the rising edge is not detected.

<R>

<2> The sampling clock used to eliminate noise differs when the TI000 valid edge is used as the count clock

and when it is used as a capture trigger. In the former case, the count clock is f^X, and in the latter case the

count clock is selected by prescaler mode register 00 (PRM00). The capture operation is started only after

a valid level is detected twice by sampling the valid edge, thus eliminating noise with a short pulse width.

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CHAPTER 7 8-BIT TIMER 50

7.1 Functions of 8-Bit Timer 50

8-bit timer 50 can be used as an interval timer or operating clock of TMH0 and UART6.

Figure 7-1 shows the block diagram of 8-bit timer 50.

Figure 7-1. Block Diagram of 8-Bit Timer 50

Internal bus

8-bit timer compare

register 50 (CR50)

Selector

Note 1

INTTM50

f

X

Match

f

X

/2

f

/2²

/2⁴

/2⁶

/2⁸

f^X

X

S

INV

Q

f

X

8-bit timer

counter 50 (TM50)

To TMH0

To UART6

OVF

f

X

/2¹¹

/2¹³

R

f

X

f

Clear

Note 2

S

R

Invert

level

3

Selector

TCE50 TMC506 LVS50 LVR50 TMC501

TCL502 TCL501 TCL500

8-bit timer mode control

register 50 (TMC50)

Timer clock selection

register 50 (TCL50)

Internal bus

Notes 1. Timer output F/F

2. PWM output F/F

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CHAPTER 7 8-BIT TIMER 50

7.2 Configuration of 8-Bit Timer 50

8-bit timer 50 includes the following hardware.

Table 7-1. Configuration of 8-Bit Timer 50

Item

Configuration

8-bit timer counter 50 (TM50)

Timer register

Register

8-bit timer compare register 50 (CR50)

Control registers

Timer clock selection register 50 (TCL50)

Timer clock switch control register (CSEL)

8-bit timer mode control register 50 (TMC50)

(1) 8-bit timer counter 50 (TM50)

TM50 is an 8-bit register that counts the count pulses and is read-only.

The counter is incremented is synchronization with the rising edge of the count clock.

Figure 7-2. Format of 8-Bit Timer Counter 50 (TM50)

Address: FF16H

After reset: 00H

R

Symbol

TM50

In the following situations, the count value is cleared to 00H.

<1> RESET input

<2> When TCE50 is cleared

<3> When TM50 and CR50 match in clear & start mode if this mode was entered upon a match of TM50 and

CR50 values.

(2) 8-bit timer compare register 50 (CR50)

CR50 can be read and written by an 8-bit memory manipulation instruction.

The value set in CR50 is constantly compared with the 8-bit timer counter 50 (TM50) count value, and an

interrupt request (INTTM50) is generated if they match.

The value of CR50 can be set within 00H to FFH.

RESET input clears this register to 00H.

Figure 7-3. Format of 8-Bit Timer Compare Register 50 (CR50)

Address: FF17H

After reset: 00H

R/W

Symbol

CR50

Cautions 1. In the clear & start mode entered on a match of TM50 and CR50 (TMC506 = 0), do not write

other values to CR50 during operation.

2. In PWM mode, make the CR50 rewrite period 3 count clocks of the count clock (clock

selected by TCL50) or more.

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CHAPTER 7 8-BIT TIMER 50

7.3 Registers Controlling 8-Bit Timer 50

The following three registers are used to control 8-bit timer 50.

•

Timer clock selection register 50 (TCL50)

Timer clock switch control register (CSEL)

8-bit timer mode control register 50 (TMC50)

(1) Timer clock selection register 50 (TCL50)

This register sets the count clock of 8-bit timer 50.

TCL50 can be set by an 8-bit memory manipulation instruction.

RESET input clears this register to 00H.

Figure 7-4. Format of Timer Clock Selection Register 50 (TCL50)

Address: FF6AH After reset: 00H R/W

Symbol

TCL50

7

0

6

0

5

0

4

0

3

0

2

1

0

TCL502

TCL501

TCL500

TCL502

TCL501

TCL500

Count clock selection

0

1

0

1

0

1

0

1

0

Count stopped

fX (10 MHz)

fX/2 (5 MHz)

fX/2²(2.5 MHz)

f^X/2⁴(625 kHz)

fX/2⁶(156.25 kHz)

fX/2⁸(39.06 kHz)

f^X/2¹¹(4.88 kHz)

fX/2¹³(1.22 kHz)

When CSEL2^{Note 1}= 0

When CSEL2^{Note 1}= 1

1

0

1

0

When CSEL3^{Note 2}= 0

When CSEL3^{Note 2}= 1

1

Notes 1. Check the setting of bit 2 (CSEL2) of the timer clock switch control register (CSEL) before setting

TCL502, TCL501, and TCL500 to 1, 0, and 0, respectively (refer to Figure 7-5 Format of Timer

Clock Switch Control Register (CSEL)). Do not rewrite CSEL2 during timer operation while TCL502,

TCL501, and TCL500 are set to 1, 0, and 0, respectively.

2. Check the setting of bit 3 (CSEL3) of the timer clock switch control register (CSEL) before setting

TCL502, TCL501, and TCL500 to 1, 1, and 0, respectively (refer to Figure 7-5 Format of Timer

Clock Switch Control Register (CSEL)). Do not rewrite CSEL3 during timer operation while TCL502,

TCL501, and TCL500 are set to 1, 1, and 0, respectively.

Cautions 1. When rewriting TCL50 to other data, stop the timer operation beforehand.

2. Be sure to set bits 3 to 7 to 0.

Remarks 1. f^X: High-speed system clock oscillation frequency

2. Figures in parentheses apply to operation at f^X= 10 MHz.

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CHAPTER 7 8-BIT TIMER 50

(2) Timer clock switch control register (CSEL)

This register is used to switch the selection clock.

This register can be set by a 1-bit or 8-bit memory manipulation instruction.

RESET input clears this register to 00H.

Figure 7-5. Format of Timer Clock Switch Control Register (CSEL)

Address: FF71H

Symbol

After reset: 00H R/W

7

0

6

0

5

0

4

0

3

2

1

0

CSEL

CSEL3

CSEL2

CSEL1

CSEL0

CSEL3

Count clock when TCL502, TCL501, TCL500 = 1, 1, 0

Count clock when TCL502, TCL501, TCL500 = 1, 0, 0

0

1

fX/2⁸

fX/2¹¹(4.88 kHz)

(39.06 kHz)

CSEL2

0

1

fX/2²

fX/2⁴

(2.5 MHz)

(625 kHz)

Remarks 1. f^X: High-speed system clock oscillation frequency

2. Bits 1 (CSEL1) and 0 (CSEL0) of CSEL are used to switch the selection clock of the 8-bit timer H1

and H0, respectively (see 8.3 (2) Timer clock switch control register).

<R>

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CHAPTER 7 8-BIT TIMER 50

(3) 8-bit timer mode control register 50 (TMC50)

TMC50 is a register that performs the following four types of settings.

<1> 8-bit timer counter 50 (TM50) count operation control

<2> 8-bit timer counter 50 (TM50) operating mode selection

<3> Timer output F/F (flip-flop) status setting

<4> Active level selection in timer F/F control or PWM (free-running) mode

TMC50 can be set by a 1-bit or 8-bit memory manipulation instruction.

RESET input clears this register to 00H.

Figure 7-6. Format of 8-Bit Timer Mode Control Register 50 (TMC50)

Address: FF6BH

Symbol

After reset: 00H R/W

6

<7>

5

0

4

0

<3>

<2>

1

0

TMC50

TCE50

TMC506

LVS50

LVR50

TMC501

TCE50

TM50 count operation control

0

1

After clearing to 0, count operation disabled (counter stopped)

Count operation start

TMC506

TM50 operating mode selection

Clear & start mode by match between TM50 and CR50

PWM (free-running) mode

0

1

LVS50

LVR50

Timer output F/F status setting

0

1

0

1

0

1

No change

Timer output F/F reset (0)

Timer output F/F set (1)

Setting prohibited

TMC501

In other modes (TMC506 = 0)

Timer F/F control

In PWM mode (TMC506 = 1)

Active level selection

0

1

Inversion operation disabled

Inversion operation enabled

Active high

Active low

Cautions 1. The settings of LVS50 and LVR50 are valid in other than PWM mode.

2. Perform <1> to <3> below in the following order, not at the same time.

<1> Set TMC501 and TMC506:

Operating mode setting

<2> Set LVS50 and LVR50 (Caution 1): Timer output F/F setting

<3> Set TCE50

3. Stop operation before rewriting TMC506.

Remarks 1. In PWM mode, PWM output is made inactive by setting TCE50 to 0.

2. If LVS50 and LVR50 are read, 0 is read.

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CHAPTER 7 8-BIT TIMER 50

7.4 Operations of 8-Bit Timer 50

7.4.1 Operation as interval timer

8-bit timer 50 operates as an interval timer that generates interrupt requests repeatedly at intervals of the count

value preset to 8-bit timer compare register 50 (CR50).

When the count value of 8-bit timer counter 50 (TM50) matches the value set to CR50, counting continues with the

TM50 value cleared to 0 and an interrupt request signal (INTTM50) is generated.

The count clock of TM50 can be selected with bits 0 to 2 (TCL500 to TCL502) of timer clock selection register 50

(TCL50) and bits 2 and 3 (CSEL2, CSEL3) of timer clock switch control register (CSEL).

Setting

<1> Set each register.

•

TCL50, CSEL: Select the count clock.

CR50:

Compare value

TMC50:

Select count operation stop. (TMC50 = 000000×0B × = Don’t care)

<2> After TCE50 = 1 is set, the count operation starts.

<3> If the values of TM50 and CR50 match, INTTM50 is generated (TM50 is cleared to 00H).

<4> INTTM50 is generated repeatedly at the same interval. Set TCE50 to 0 to stop the count operation.

Caution Do not write other values to CR50 during operation.

Figure 7-7. Interval Timer Operation Timing (1/2)

(a) Basic operation

t

Count clock

TM50 count value

CR50

00H 01H

Count start

N

00H 01H

N

00H 01H

N

Clear

N

TCE50

INTTM50

Interrupt acknowledged

Interval time

Interrupt acknowledged

Interval time

Remark Interval time = (N + 1) × t

N = 01H to FFH

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CHAPTER 7 8-BIT TIMER 50

Figure 7-7. Interval Timer Operation Timing (2/2)

(b) When CR50 = 00H

t

Count clock

TM50 00H

CR50

00H 00H

TCE50

INTTM50

Interval time

(c) When CR50 = FFH

t

Count clock

TM50

01

FE

FF

00

FE

FF

00

CR50

FF

TCE50

INTTM50

Interrupt request acknowledged

Interval time

Interrupt request

acknowledged

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CHAPTER 7 8-BIT TIMER 50

7.4.2 Operation as operating clock of TMH0 and UART6

8-bit timer 50 can be used as the operating clock of TMH0 and UART6.

(1) In clear & start mode entered on match of TM50 and CR50 (TMC506 = 0)

The timer output F/F is inverted at intervals determined by the count value preset to CR50. This enables a

square wave with any selected frequency to be output (duty = 50%).

Setting

<1> Set each register.

•

TCL50: Select the count clock.

CR50: Compare value

TMC50: Stop the count operation, select clear & start mode entered on a match of TM50 and CR50.

LVS50 LVR50

Timer Output F/F Status Setting

High-level output

Low-level output

1

0

1

Timer output F/F inversion enabled

(TMC50 = 00001010B or 00000110B)

<2> After TCE50 = 1 is set, the count operation starts.

<3> The timer output F/F is inverted by a match of TM50 and CR50.

After INTTM50 is generated, TM50 is cleared to 00H.

<4> After these settings, the timer output F/F is inverted at the same interval and a square wave is output.

The frequency is as follows.

Frequency = 1/2t (N + 1)

(N: 00H to FFH)

Caution Do not write other values to CR50 during operation.

Figure 7-8. Square-Wave Output Operation Timing

t

Count clock

TM50 count value

00H 01H 02H

Count start

N − 1

N

00H 01H 02H

N − 1

N

00H

CR50

N

Square-wave

output^Note

Note The initial value of square-wave output can be set by bits 2 and 3 (LVR50, LVS50) of 8-bit timer mode

control register 50 (TMC50).

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CHAPTER 7 8-BIT TIMER 50

(2) In PWM mode (TMC506 = 1)

The duty pulse is determined by the value set to 8-bit timer compare register 50 (CR50).

Set the active level width of the PWM pulse with CR50 (CR50 = 80H) so that the duty will be 50%; the active level

can be selected with bit 1 of TMC50 (TMC501).

The count clock can be selected with bits 0 to 2 (TCL500 to TCL502) of timer clock selection register 50 (TCL50).

Caution In PWM mode, make the CR50 rewrite period 3 count clocks of the count clock (clock selected

by TCL50) or more.

Setting

<1> Set each register.

•

TCL50: Select the count clock.

CR50: Compare value (80H)

TMC50: Stop the count operation, select PWM mode.

The timer output F/F is not changed.

TMC501

Active Level Selection

0

1

Active-high

Active-low

(TMC50 = 01000000B or 01000010B)

<2> The count operation starts when TCE50 = 1.

Set TCE50 to 0 to stop the count operation.

PWM output operation

<1> PWM output outputs an inactive level until an overflow occurs.

<2> When an overflow occurs, the active level is output.

The active level is output until CR50 matches the count value of 8-bit timer counter 50 (TM50).

<3> After the CR50 matches the count value, the inactive level is output until an overflow occurs again.

<4> Operations <2> and <3> are repeated until the count operation stops.

<5> When the count operation is stopped with TCE50 = 0, PWM output becomes inactive.

For details of timing, see Figure 7-9.

The cycle, active-level width, and duty are as follows.

•

Cycle = 2⁸t

Active-level width = Nt

Duty = N/2⁸

(N = 80H)

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CHAPTER 7 8-BIT TIMER 50

Figure 7-9. PWM Output Operation Timing (CR50 = 80H, Active Level = H)

t

Count clock

TM50

00H 01H

80H

FFH 00H 01H 02H

80H 81H

FFH 00H 01H 02H

M

00H

CR50

TCE50

INTTM50

PWM output

<1>

<5>

<2> Active level

<3> Inactive level

Active level

Remark <1> to <3> and <5> in Figure 7-9 correspond to <1> to <3> and <5> in PWM output operation in 7.4.2

(2) In PWM mode (TMC506 = 1).

7.5 Cautions on 8-Bit Timer 50

(1) Timer start errors

An error of up to one clock may occur in the time required for a match signal to be generated after timer start.

This is because 8-bit timer counter 50 (TM50) is started asynchronously to the count clock.

Figure 7-10. 8-Bit Timer Counter 50 Start Timing

Count clock

TM50 count value

00H

Timer start

01H

02H

03H

04H

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CHAPTER 8 8-BIT TIMERS H0 AND H1

8.1 Functions of 8-Bit Timers H0 and H1

8-bit timers H0 and H1 have the following functions.

•

Interval timer

PWM output mode

Square-wave output

Carrier generator mode (8-bit timer H1 only)

8.2 Configuration of 8-Bit Timers H0 and H1

8-bit timers H0 and H1 include the following hardware.

Table 8-1. Configuration of 8-Bit Timers H0 and H1

Item

Timer register

Registers

Configuration

8-bit timer counter Hn

8-bit timer H compare register 0n (CMP0n)

8-bit timer H compare register 1n (CMP1n)

Timer output

TOHn

Control registers

8-bit timer H mode register n (TMHMDn)

Timer clock switch control register (CSEL)

8-bit timer H carrier control register 1 (TMCYC1)^Note

Alternate-function pin switch register (PSEL)^Note

Port mode register 1 (PM1)

Port register 1 (P1)

Note 8-bit timer H1 only

Remark n = 0, 1

Figures 8-1 and 8-2 show the block diagrams.

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(1) 8-bit timer H compare register 0n (CMP0n)

This register can be read/written by an 8-bit memory manipulation instruction.

RESET input clears this register to 00H.

Figure 8-3. Format of 8-Bit Timer H Compare Register 0n (CMP0n)

Address: FF18H (CMP00), FF1AH (CMP01) After reset: 00H R/W

Symbol

7

5

3

2

1

0

6

4

CMP0n

(n = 0, 1)

Caution CMP0n cannot be rewritten during timer count operation.

(2) 8-bit timer H compare register 1n (CMP1n)

This register can be read/written by an 8-bit memory manipulation instruction.

RESET input clears this register to 00H.

Figure 8-4. Format of 8-Bit Timer H Compare Register 1n (CMP1n)

Address: FF19H (CMP10), FF1BH (CMP11) After reset: 00H R/W

Symbol

7

5

3

2

1

0

6

4

CMP1n

(n = 0, 1)

The CMP1n register can be rewritten during timer count operation.

In the carrier generator mode, an interrupt request signal (INTTMHn) is generated if the timer count value and

CMP1n value match after setting CMP1n. The timer count value is cleared at the same time. If the CMP1n value is

rewritten during timer operation, transfer is performed at the timing at which the count value and CMP1n value match.

If the transfer timing and writing from CPU to CMP1n conflict, transfer is not performed.

Caution In the PWM output mode and carrier generator mode, be sure to set CMP1n when starting the

timer count operation (TMHEn = 1) after the timer count operation was stopped (TMHEn = 0) (be

sure to set again even if setting the same value to CMP1n).

Remark n = 0, 1

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8.3 Registers Controlling 8-Bit Timers H0 and H1

8-bit timers H0 and H1 are controlled by the following six types of registers.

• 8-bit timer H mode register n (TMHMDn)

• Timer clock switch control register (CSEL)

• 8-bit timer H carrier control register 1 (TMCYC1)^Note

• Alternate-function pin switch register (PSEL)^Note

• Port mode register 1 (PM1)

• Port register 1 (P1)

Note 8-bit timer H1 only

(1) 8-bit timer H mode register n (TMHMDn)

This register controls the mode of timer H.

This register can be set by a 1-bit or 8-bit memory manipulation instruction.

RESET input clears this register to 00H.

Remark n = 0, 1

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Figure 8-5. Format of 8-Bit Timer H Mode Register 0 (TMHMD0)

Address: FF69H After reset: 00H R/W

<7>

5

3

2

<1>

<0>

6

4

TMHMD0

TMHE0 CKS02

CKS01 CKS00 TMMD01 TMMD00 TOLEV0 TOEN0

TMHE0

Timer operation enable

0

1

Stops timer count operation (counter is cleared to 0)

Enables timer count operation (count operation started by inputting clock)

CKS02

CKS01

CKS00

Count clock (f^CNT) selection

(10 MHz)

0

1

0

1

0

1

0

1

0

1

f

X

/2

(5 MHz)

/2²

/2⁶

(2.5 MHz)

(156.25 kHz)

/2¹⁰(9.77 kHz)

When CSEL0^{Note 2}= 0

When CSEL0^{Note 2}= 1

TM50 output^{Note 1}

/2¹³(1.22 kHz)

Setting prohibited

fX

Other than above

TMMD01 TMMD00

Timer operation mode

0

1

0

Interval timer mode

PWM output mode

Other than above Setting prohibited

TOLEV0

Timer output level control (in default mode)

0

1

Low level

High level

TOEN0

Timer output control

0

1

Disables output

Enables output

Notes 1. When the TM50 output is selected as the count clock, observe the following.

• PWM mode (TMC506 = 1)

Set the clock so that the duty will be 50% and start the operation of 8-bit timer/event counter 50 in

advance.

• Clear & start mode entered on match of TM50 and CR50 (TMC506 = 0)

Enable the timer F/F inversion operation (TMC501 = 1) and start the operation of 8-bit timer/event

counter 50 in advance.

2. Check the setting of bit 0 (CSEL0) of the timer clock switch control register (CSEL) before setting

CKS02, CKS01, and CKS00 to 1, 0, and 1, respectively (refer to Figure 8-7 Format of Timer Clock

Switch Control Register (CSEL)). Do not rewrite CSEL0 during timer operation while CKS02, CKS01,

and CKS00 are set to 1, 0, and 1, respectively.

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Cautions 1. When the internal low-speed oscillation clock is selected as the clock to be supplied to the

CPU, the clock of the internal low-speed oscillator is divided and supplied as the count clock.

If the count clock is the internal low-speed oscillation clock, the operation of 8-bit timer H0 is

not guaranteed.

2. When TMHE0 = 1, setting the other bits of TMHMD0 is prohibited.

3. In the PWM output mode, be sure to set 8-bit timer H compare register 10 (CMP10) when

starting the timer count operation (TMHE0 = 1) after the timer count operation was stopped

(TMHE0 = 0) (be sure to set again even if setting the same value to CMP10).

Remarks 1. f^X: High-speed system clock oscillation frequency

2. Figures in parentheses apply to operation at f^X= 10 MHz.

3. TMC506: Bit 6 of 8-bit timer mode control register 50 (TMC50)

TMC501: Bit 1 of TMC50

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Figure 8-6. Format of 8-Bit Timer H Mode Register 1 (TMHMD1)

Address: FF6CH After reset: 00H R/W

<7>

5

3

2

<1>

<0>

6

4

TMHMD1

TMHE1 CKS12

CKS11 CKS10 TMMD11 TMMD10 TOLEV1 TOEN1

TMHE1

Timer operation enable

0

1

Stops timer count operation (counter is cleared to 0)

Enables timer count operation (count operation started by inputting clock)

CKS12

CKS11

CKS10

Count clock (f^CNT) selection

(10 MHz)

0

1

f

X

When CSEL1^Note= 0

When CSEL1^Note= 1

/2²

/2

(2.5 MHz)

(5 MHz)

/2⁴

/2⁶

(625 kHz)

0

1

0

1

0

1

(156.25 kHz)

/2¹²(2.44 kHz)

/2⁷

(1.88 kHz (TYP.))

R

Other than above

Setting prohibited

TMMD11 TMMD10

Timer operation mode

0

1

0

1

0

1

Interval timer mode

Carrier generator mode

PWM output mode

Setting prohibited

TOLEV1

Timer output level control (in default mode)

0

1

Low level

High level

TOEN1

Timer output control

0

1

Disables output

Enables output

Note Check the setting of bit 1 (CSEL1) of the timer clock switch control register (CSEL) before setting CKS12,

CKS11, and CKS10 to 0, 0, and 1, respectively (refer to Figure 8-7 Format of Timer Clock Switch

Control Register (CSEL)). Do not rewrite CSEL1 during timer operation while CKS12, CKS11, and CKS10

are set to 0, 0, and 1, respectively.

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Cautions 1. When the internal low-speed oscillation clock is selected as the clock to be supplied to the

CPU, the clock of the internal low-speed oscillator is divided and supplied as the count clock.

If the count clock is the internal low-speed oscillation clock, the operation of 8-bit timer H1 is

not guaranteed (except when CKS12, CKS11, CKS10 = 1, 0, 1 (f^R/2⁷)).

2. When TMHE1 = 1, setting the other bits of TMHMD1 is prohibited.

3. In the PWM output mode and carrier generator mode, be sure to set 8-bit timer H compare

register 11 (CMP11) when starting the timer count operation (TMHE1 = 1) after the timer count

operation was stopped (TMHE1 = 0) (be sure to set again even if setting the same value to the

CMP11 register).

4. When the carrier generator mode is used, set so that the count clock frequency of TMH1

becomes more than 6 times the count clock frequency of TM50.

Remarks 1. f^X: High-speed system clock oscillation frequency

2. f^R: Internal low-speed oscillation clock oscillation frequency

3. Figures in parentheses apply to operation at f^X= 10 MHz, fR = 240 kHz (TYP.).

(2) Timer clock switch control register (CSEL)

This register is used to switch the selection clock.

This register can be set by a 1-bit or 8-bit memory manipulation instruction.

RESET input clears this register to 00H.

Figure 8-7. Format of Timer Clock Switch Control Register (CSEL)

Address: FF71H After reset: 00H R/W

7

0

6

0

5

0

4

0

3

2

1

0

CSEL

CSEL3 CSEL2

CSEL1

CSEL0

CSEL1

Count clock when CKS12, CKS11, CKS10 = 0, 0, 1

0

1

f

X

/2²(2.5 MHz)

/2 (5 MHz)

CSEL0

Count clock when CKS02, CKS01, CKS00 = 1, 0, 1

TM50 output

/2¹³(1.22 kHz)

0

1

f

X

Remarks 1. CKS12, CKS11, and CKS10: Bits 6 to 4 of 8-bit timer H mode register 1 (TMHMD1)

CKS02, CKS01, and CKS00: Bits 6 to 4 of 8-bit timer H mode register 0 (TMHMD0)

2. f^X: High-speed system clock oscillation frequency

<R>

3. Bits 3 (CSEL3) and 2 (CSEL2) of CSEL are used to switch the selection clock of the 8-bit timer 50

(see 7.3 (2) Timer clock switch control register).

4. Figures in parentheses apply to operation at f^X= 10 MHz.

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(3) 8-bit timer H carrier control register 1 (TMCYC1)

This register controls the remote control output and carrier pulse output status of 8-bit timer H1.

This register can be set by a 1-bit or 8-bit memory manipulation instruction.

RESET input clears this register to 00H.

Figure 8-8. Format of 8-Bit Timer H Carrier Control Register 1 (TMCYC1)

Address: FF6DH After reset: 00H R/W^Note

7

0

6

0

5

0

4

0

3

0

2

1

<0>

TMCYC1

RMC1

NRZB1

NRZ1

RMC1

NRZB1

Remote control output

0

1

0

1

0

1

Low-level output

High-level output at rising edge of INTTM50 signal input

Low-level output

<R>

Carrier pulse output at rising edge of INTTM50 signal input

NRZ1

Carrier pulse output status flag

0

1

Carrier output disabled status (low-level status)

Carrier output enabled status

(RMC1 = 1: Carrier pulse output, RMC1 = 0: High-level status)

Note Bit 0 is read-only.

(4) Alternate-function pin switch register (PSEL)

This register is used to select the TOH1 pin.

This register can be set by a 1-bit or 8-bit memory manipulation instruction.

RESET input clears this register to 00H.

Figure 8-9. Format of Alternate-Function Pin Switch Register (PSEL)

Address: FF70H After reset: 00H R/W

7

0

6

0

<5>

<4>

3

0

2

0

<1>

<0>

PSEL

TOH1SL MCGSL

INTP1SL INTP3SL

TOH1SL

TOH1 pin selection

0

1

P12/SO10/TOH1/(INTP3)

P13/TxD6/INTP1/(TOH1)/(MCGO)

Caution Set bit 7 (TMHE1) of 8-bit timer H mode register 1 (TMHMD1) to 0 before rewriting the TOH1SL

bit.

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(5) Port mode register 1 (PM1)

This register is used to set input/output for port 1 in 1-bit units.

This register can be set by a 1-bit or 8-bit memory manipulation instruction.

RESET input sets this register to FFH.

Figure 8-10. Format of Port Mode Register 1 (PM1)

Address: FF21H After reset: FFH R/W

7

1

6

1

5

4

3

2

1

0

PM1

PM15

PM14

PM13

PM12

PM11

PM10

PM1n

P1n pin I/O mode selection (n = 0 to 5)

0

1

Output mode (output buffer on)

Input mode (output buffer off)

When using the P12/TOH1/SO10/(INTP3), P13/(TOH1)/TxD6/INTP1/(MCGO), or P15/TOH0/FLMD1 pin as a

timer output, set the port mode register and port output latch as follows.

• P12/TOH1/SO10/(INTP3) is used as timer output (bit 5 (TOH1SL) of PSEL register = 0)

Bit 2 (PM12) of port mode register 1: Cleared to 0

Bit 2 (P12) of port 1:

Cleared to 0

• P13/(TOH1)/TxD6/INTP1/(MCGO) is used as timer output (bit 5 (TOH1SL) of PSEL register = 1)

Bit 3 (PM13) of port mode register 1: Cleared to 0

Bit 3 (P13) of port 1:

Cleared to 0

• P15/TOH0/FLMD1 is used as timer output (setting of PSEL register is not necessary)

Bit 5 (PM15) of port mode register 1: Cleared to 0

Bit 5 (P15) of port 1:

Cleared to 0

8.4 Operation of 8-Bit Timers H0 and H1

8.4.1 Operation as interval timer

When 8-bit timer counter Hn and compare register 0n (CMP0n) match, an interrupt request signal (INTTMHn) is

generated and 8-bit timer counter Hn is cleared to 00H.

Compare register 1n (CMP1n) is not used in interval timer mode. Since a match of 8-bit timer counter Hn and the

CMP1n register is not detected even if the CMP1n register is set, timer output is not affected.

By setting bit 0 (TOENn) of timer H mode register n (TMHMDn) to 1, a square wave of any frequency (duty = 50%)

is output from TOHn.

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(1) Usage

Generates the INTTMHn signal repeatedly at the same interval.

<1> Set each register.

Figure 8-11. Register Setting During Interval Timer/Square-Wave Output Operation

(i) Setting timer H mode register n (TMHMDn)

TMHEn

0

CKSn2 CKSn1

0/1 0/1

CKSn0 TMMDn1 TMMDn0 TOLEVn TOENn

0/1 0/1 0/1

TMHMDn

0

Timer output setting

Timer output level inversion setting

Interval timer mode setting

Count clock (f^CNT) selection^Note

Count operation stopped

Note Check the setting of bit 0 (CSEL0) of the timer clock switch control register (CSEL) before

setting CKS02, CKS01, and CKS00 to 1, 0, and 1, respectively, and check the setting of bit 1

(CSEL1) of the CSEL register before setting CKS12, CKS11, and CKS10 to 0, 0, and 1,

respectively (refer to Figure 8-7 Format of Timer Clock Switch Control Register (CSEL)).

(ii) CMP0n register setting

•

Compare value (N)

<2> Count operation starts when TMHEn = 1.

<3> When the values of 8-bit timer counter Hn and the CMP0n register match, the INTTMHn signal is generated

and 8-bit timer counter Hn is cleared to 00H.

Interval time = (N +1)/f^CNT

<4> Subsequently, the INTTMHn signal is generated at the same interval. To stop the count operation, set

TMHEn to 0.

Remark n = 0, 1

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(2) Timing chart

The timing of the interval timer/square-wave output operation is shown below.

Figure 8-12. Timing of Interval Timer/Square-Wave Output Operation (1/2)

(a) Basic operation

Count clock

Count start

00H

01H

N

00H

Clear

01H

N

00H 01H 00H

Clear

8-bit timer counter Hn

CMP0n

TMHEn

INTTMHn

TOHn

Interval time

<1>

<2>

Level inversion,

<3>

<2>

Level inversion,

match interrupt occurrence,

8-bit timer counter Hn clear

match interrupt occurrence,

8-bit timer counter Hn clear

<1> The count operation is enabled by setting the TMHEn bit to 1. The count clock starts counting no more than

1 clock after the operation is enabled.

<2> When the values of 8-bit timer counter Hn and the CMP0n register match, the value of 8-bit timer counter Hn

is cleared, the TOHn output level is inverted, and the INTTMHn signal is output.

<3> The INTTMHn signal and TOHn output become inactive by setting the TMHEn bit to 0 during timer Hn

operation. If these are inactive from the first, the level is retained.

Remark n = 0, 1

N = 01H to FEH

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Figure 8-12. Timing of Interval Timer/Square-Wave Output Operation (2/2)

(b) Operation when CMP0n = FFH

Count clock

Count start

00H

01H

FEH

FFH

00H

FEH

FFH

8-bit timer counter Hn

Clear

FFH

CMP0n

TMHEn

INTTMHn

TOHn

Interval time

<R>

(c) Operation when CMP0n = 00H

Count clock

Count start

8-bit timer counter Hn

CMP0n

00H

TMHEn

INTTMHn

TOHn

Interval time

Remark n = 0, 1

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8.4.2 Operation as PWM output mode

In PWM output mode, a pulse with an arbitrary duty and arbitrary cycle can be output.

8-bit timer compare register 0n (CMP0n) controls the cycle of timer output (TOHn). Rewriting the CMP0n register

during timer operation is prohibited.

8-bit timer compare register 1n (CMP1n) controls the duty of timer output (TOHn). Rewriting the CMP1n register

during timer operation is possible.

The operation in PWM output mode is as follows.

TOHn output becomes active and 8-bit timer counter Hn is cleared to 0 when 8-bit timer counter Hn and the

CMP0n register match after the timer count is started. TOHn output becomes inactive when 8-bit timer counter Hn

and the CMP1n register match.

(1) Usage

In PWM output mode, a pulse for which an arbitrary duty and arbitrary cycle can be set is output.

<1> Set each register.

Figure 8-13. Register Setting in PWM Output Mode

(i) Setting timer H mode register n (TMHMDn)

TMHEn

0

CKSn2 CKSn1

0/1 0/1

CKSn0 TMMDn1 TMMDn0 TOLEVn TOENn

0/1 0/1

TMHMDn

1

0

1

Timer output enabled

Timer output level inversion setting

PWM output mode selection

Count clock (fCNT) selection^Note

Count operation stopped

Note Check the setting of bit 0 (CSEL0) of the timer clock switch control register (CSEL) before setting

CKS02, CKS01, and CKS00 to 1, 0, and 1, respectively, and check the setting of bit 1 (CSEL1) of

the CSEL register before setting CKS12, CKS11, and CKS10 to 0, 0, and 1, respectively (refer to

Figure 8-7 Format of Timer Clock Switch Control Register (CSEL)).

(ii) Setting CMP0n register

•

Compare value (N): Cycle setting

(iii) Setting CMP1n register

•

Compare value (M): Duty setting

Remarks 1. n = 0, 1

2. 00H ≤ CMP1n (M) < CMP0n (N) ≤ FFH

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<2> The count operation starts when TMHEn = 1.

<3> The CMP0n register is the compare register that is to be compared first after counter operation is enabled.

When the values of 8-bit timer counter Hn and the CMP0n register match, 8-bit timer counter Hn is cleared,

an interrupt request signal (INTTMHn) is generated, and TOHn output becomes active. At the same time,

the compare register to be compared with 8-bit timer counter Hn is changed from the CMP0n register to the

CMP1n register.

<4> When 8-bit timer counter Hn and the CMP1n register match, TOHn output becomes inactive and the

compare register to be compared with 8-bit timer counter Hn is changed from the CMP1n register to the

CMP0n register. At this time, 8-bit timer counter Hn is not cleared and the INTTMHn signal is not

generated.

<5> By performing procedures <3> and <4> repeatedly, a pulse with an arbitrary duty can be obtained.

<6> To stop the count operation, set TMHEn = 0.

If the setting value of the CMP0n register is N, the setting value of the CMP1n register is M, and the count clock

frequency is f^CNT, the PWM pulse output cycle and duty are as follows.

PWM pulse output cycle = (N + 1)/f^CNT

Duty = Active width : Total width of PWM = (M + 1) : (N + 1)

Cautions 1. In PWM output mode, three operation clocks (signal selected using the CKSn2 to CKSn0

bits of the TMHMDn register) are required to transfer the CMP1n register value after

rewriting the register.

2. Be sure to set the CMP1n register when starting the timer count operation (TMHEn = 1) after

the timer count operation was stopped (TMHEn = 0) (be sure to set again even if setting the

same value to the CMP1n register).

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(2) Timing chart

The operation timing in PWM output mode is shown below.

Caution Make sure that the CMP1n register setting value (M) and CMP0n register setting value (N) are

within the following range.

00H ≤ CMP1n (M) < CMP0n (N) ≤ FFH

Remark n = 0, 1

Figure 8-14. Operation Timing in PWM Output Mode (1/4)

(a) Basic operation

Count clock

00H 01H

A5H 00H 01H 02H

A5H 00H

8-bit timer counter Hn

A5H

01H

CMP0n

CMP1n

TMHEn

INTTMHn

TOHn

(TOLEVn = 0)

<4>

<2>

<3>

<1>

TOHn

(TOLEVn = 1)

<1> The count operation is enabled by setting the TMHEn bit to 1. Start 8-bit timer counter Hn by masking one

count clock to count up. At this time, TOHn output remains inactive (when TOLEVn = 0).

<2> When the values of 8-bit timer counter Hn and the CMP0n register match, the TOHn output level is inverted,

the value of 8-bit timer counter Hn is cleared, and the INTTMHn signal is output.

<3> When the values of 8-bit timer counter Hn and the CMP1n register match, the level of the TOHn output is

returned. At this time, the value of 8-bit timer counter Hn is not cleared and the INTTMHn signal is not output.

<4> Setting the TMHEn bit to 0 during timer Hn operation makes the INTTMHn signal and TOHn output inactive.

Remark n = 0, 1

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Figure 8-14. Operation Timing in PWM Output Mode (2/4)

(b) Operation when CMP0n = FFH, CMP1n = 00H

Count clock

8-bit timer counter Hn

00H 01H

FFH 00H 01H 02H

FFH 00H

FFH

00H

CMP0n

CMP1n

TMHEn

INTTMHn

TOHn

(TOLEVn = 0)

(c) Operation when CMP0n = FFH, CMP1n = FEH

Count clock

00H 01H

FEH FFH 00H 01H

FEH FFH 00H

8-bit timer counter Hn

FFH

FEH

CMP0n

CMP1n

TMHEn

INTTMHn

TOHn

(TOLEVn = 0)

Remark n = 0, 1

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Figure 8-14. Operation Timing in PWM Output Mode (3/4)

(d) Operation when CMP0n = 01H, CMP1n = 00H

Count clock

00H 01H 00H 01H 00H

00H 01H 00H 01H

8-bit timer counter Hn

CMP0n

01H

00H

CMP1n

TMHEn

INTTMHn

TOHn

(TOLEVn = 0)

Remark n = 0, 1

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Figure 8-14. Operation Timing in PWM Output Mode (4/4)

(e) Operation by changing CMP1n (CMP1n = 01H → 03H, CMP0n = A5H)

Count clock

8-bit timer counter Hn

00H 01H 02H

A5H 00H 01H 02H 03H

A5H 00H

A5H

03H

CMP0n

CMP1n

01H

01H (03H)

<2>'

<2>

TMHEn

INTTMHn

TOHn

(TOLEVn = 0)

<3>

<4>

<6>

<1>

<5>

<1> The count operation is enabled by setting TMHEn = 1. Start 8-bit timer counter Hn by masking one count

clock to count up. At this time, the TOHn output remains inactive (when TOLEVn = 0).

<2> The CMP1n register value can be changed during timer counter operation. This operation is asynchronous

to the count clock.

<3> When the values of 8-bit timer counter Hn and the CMP0n register match, the value of 8-bit timer counter Hn

is cleared, the TOHn output becomes active, and the INTTMHn signal is output.

<4> If the CMP1n register value is changed, the value is latched and not transferred to the register. When the

values of 8-bit timer counter Hn and the CMP1n register before the change match, the value is transferred to

the CMP1n register and the CMP1n register value is changed (<2>’).

However, three count clocks or more are required from when the CMP1n register value is changed to when

the value is transferred to the register. If a match signal is generated within three count clocks, the changed

value cannot be transferred to the register.

<5> When the values of 8-bit timer counter Hn and the CMP1n register after the change match, the TOHn output

becomes inactive. 8-bit timer counter Hn is not cleared and the INTTMHn signal is not generated.

<6> Setting the TMHEn bit to 0 during timer Hn operation makes the INTTMHn signal and TOHn output inactive.

Remark n = 0, 1

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8.4.3 Operation as carrier generator mode (8-bit timer H1 only)

The carrier clock generated by 8-bit timer H1 is output in the cycle set by 8-bit timer 50.

In carrier generator mode, the output of the 8-bit timer H1 carrier pulse is controlled by 8-bit timer 50, and the

carrier pulse is output from the TOH1 output.

(1) Carrier generation

In carrier generator mode, 8-bit timer H compare register 01 (CMP01) generates a low-level width carrier pulse

waveform and 8-bit timer H compare register 11 (CMP11) generates a high-level width carrier pulse waveform.

Rewriting the CMP11 register during 8-bit timer H1 operation is possible but rewriting the CMP01 register is

prohibited.

(2) Carrier output control

Carrier output is controlled by the interrupt request signal (INTTM50) of 8-bit timer 50 and the NRZB1 and RMC1

bits of 8-bit timer H carrier control register 1 (TMCYC1). The relationship between the outputs is shown below.

RMC1 Bit

NRZB1 Bit

Output

Low-level output

0

1

High-level output at rising edge

of INTTM50 signal input

<R>

1

0

1

Low-level output

Carrier pulse output at rising

edge of INTTM50 signal input

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To control the carrier pulse output during a count operation, the NRZ1 and NRZB1 bits of the TMCYC1 register

have a master and slave bit configuration. The NRZ1 bit is read-only but the NRZB1 bit can be read and written.

The INTTM50 signal is synchronized with the 8-bit timer H1 count clock and output as the INTTM5H0 signal. The

INTTM5H0 signal becomes the data transfer signal of the NRZ1 bit, and the NRZB1 bit value is transferred to the

NRZ1 bit. The timing for transfer from the NRZB1 bit to the NRZ1 bit is as shown below.

Figure 8-15. Transfer Timing

TMHE1

8-bit timer H0

count clock

INTTM50

INTTM5H0

<1>

0

1

0

NRZ1

NRZB1

RMC1

<2>

1

0

1

<1> The INTTM50 signal is synchronized with the count clock of 8-bit timer H1 and is output as the INTTM5H0

signal.

<2> The value of the NRZB1 bit is transferred to the NRZ1 bit at the second clock from the rising edge of the

INTTM5H0 signal.

Cautions 1. Do not rewrite the NRZB1 bit again until at least the second clock after it has been rewritten,

or else the transfer from the NRZB1 bit to the NRZ1 bit is not guaranteed.

2. When 8-bit timer 50 is used in the carrier generator mode, an interrupt is generated at the

timing of <1>. When 8-bit timer 50 is used in a mode other than the carrier generator mode,

the timing of the interrupt generation differs.

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(3) Usage

Outputs an arbitrary carrier clock from the TOH1 pin.

<1> Set each register.

Figure 8-16. Register Setting in Carrier Generator Mode

(i) Setting 8-bit timer H mode register 1 (TMHMD1)

TMHE1

0

CKS12 CKS11

0/1 0/1

CKS10 TMMD11 TMMD10 TOLEV1 TOEN1

0/1 0/1

TMHMD1

0

1

Timer output enabled

Timer output level inversion setting

Carrier generator mode selection

Count clock (f^CNT) selection^Note

Count operation stopped

Note Check the setting of bit 1 (CSEL1) of the timer clock switch control register (CSEL) before

setting CKS12, CKS11, and CKS10 to 0, 0, and 1, respectively (refer to Figure 8-7 Format of

Timer Clock Switch Control Register (CSEL)).

(ii) CMP01 register setting

• Compare value

(iii) CMP11 register setting

• Compare value

(iv) TMCYC1 register setting

• RMC1 = 1 ... Remote control output enable bit

• NRZB1 = 0/1 ... Carrier output enable bit

(v) TCL50 and TMC50 register setting

• Refer to 7.3 Registers Controlling 8-Bit Timer 50.

<2> When TMHE1 = 1, 8-bit timer H1 starts counting.

<3> When TCE50 of 8-bit timer mode control register 50 (TMC50) is set to 1, 8-bit timer 50 starts counting.

<4> After the count operation is enabled, the first compare register to be compared is the CMP01 register.

When the count value of 8-bit timer counter H1 and the CMP01 register value match, the INTTMH1 signal

is generated, 8-bit timer counter H1 is cleared, and at the same time, the compare register to be compared

with 8-bit timer counter H1 is switched from the CMP01 register to the CMP11 register.

<5> When the count value of 8-bit timer counter H1 and the CMP11 register value match, the INTTMH1 signal

is generated, 8-bit timer counter H1 is cleared, and at the same time, the compare register to be compared

with 8-bit timer counter H1 is switched from the CMP11 register to the CMP01 register.

<6> By performing procedures <4> and <5> repeatedly, a carrier clock is generated.

<7> The INTTM50 signal is synchronized with the count clock of 8-bit timer H1 and output as the INTTM5H0

signal. The INTTM5H0 signal becomes the data transfer signal for the NRZB1 bit, and the NRZB1 bit value

is transferred to the NRZ1 bit.

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<8> When the NRZ1 bit is high level, a carrier clock is output from the TOH1 pin.

<9> By performing the procedures above, an arbitrary carrier clock is obtained. To stop the count operation, set

TMHE1 to 0.

If the setting value of the CMP01 register is N, the setting value of the CMP11 register is M, and the count clock

frequency is f^CNT, the carrier clock output cycle and duty are as follows.

Carrier clock output cycle = (N + M + 2)/fCNT

Duty = High-level width : Carrier clock output width = (M + 1) : (N + M + 2)

Cautions 1. Be sure to set the CMP11 register when starting the timer count operation (TMHE1 = 1) after

the timer count operation was stopped (TMHE1 = 0) (be sure to set again even if setting the

same value to the CMP11 register).

2. Set so that the count clock frequency of TMH1 becomes more than 6 times the count clock

frequency of TM50.

(4) Timing chart

The carrier output control timing is shown below.

Cautions 1. Set the values of the CMP01 and CMP11 registers in a range of 01H to FFH.

2. In the carrier generator mode, three operating clocks (signal selected by CKS12 to CKS10

bits of TMHMD1 register) or more are required from when the CMP11 register value is

changed to when the value is transferred to the register.

3. Be sure to set the RMC1 bit before the count operation is started.

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Figure 8-17. Carrier Generator Mode Operation Timing (1/3)

(a) Operation when CMP01 = N, CMP11 = N

8-bit timer H1

count clock

8-bit timer counter

H1 count value

00H

N

00H

N

00H

N

00H

N

00H

N

00H

N

CMP01

CMP11

N

TMHE1

INTTMH1

Carrier clock

<3>

<4>

<1> <2>

00H 01H

8-bit timer 50

count clock

TM50 count value

L

00H 01H

L

00H 01H

L

00H 01H

L

00H 01H

CR50

TCE50

<5>

INTTM50

INTTM5H0

0

1

0

1

0

NRZB1

<6>

0

1

0

1

0

NRZ1

Carrier clock

<7>

TOH1

<1> When TMHE1 = 0 and TCE50 = 0, 8-bit timer counter H1 operation is stopped.

<2> When TMHE1 = 1 is set, 8-bit timer counter H1 starts a count operation. At that time, the carrier clock is held

at the inactive level.

<3> When the count value of 8-bit timer counter H1 matches the CMP01 register value, the first INTTMH1 signal

is generated, the carrier clock signal is inverted, and the compare register to be compared with 8-bit timer

counter H1 is switched from the CMP01 register to the CMP11 register. 8-bit timer counter H1 is cleared to

00H.

<4> When the count value of 8-bit timer counter H1 matches the CMP11 register value, the INTTMH1 signal is

generated, the carrier clock signal is inverted, and the compare register to be compared with 8-bit timer

counter H1 is switched from the CMP11 register to the CMP01 register. 8-bit timer counter H1 is cleared to

00H. By performing procedures <3> and <4> repeatedly, a carrier clock with duty fixed to 50% is generated.

<5> When the INTTM50 signal is generated, it is synchronized with 8-bit timer H1 count clock and output as the

INTTM5H0 signal.

<6> The INTTM5H0 signal becomes the data transfer signal for the NRZB1 bit, and the NRZB1 bit value is

transferred to the NRZ1 bit.

<7> When NRZ1 = 0 is set, the TOH1 output becomes low level.

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Figure 8-17. Carrier Generator Mode Operation Timing (2/3)

(b) Operation when CMP01 = N, CMP11 = M

8-bit timer H1

count clock

8-bit timer counter

H1 count value

00H

N

00H 01H

M

00H

N

00H 01H

M

00H

N

00H

N

CMP01

CMP11

M

TMHE1

INTTMH1

Carrier clock

<3>

<4>

<1> <2>

00H 01H

8-bit timer 50

count clock

TM50 count value

L

00H 01H

L

00H 01H

L

00H 01H

L

00H 01H

CR50

TCE50

<5>

INTTM50

INTTM5H0

0

1

0

1

0

NRZB1

0

1

0

1

0

NRZ1

Carrier clock

<6>

<7>

TOH1

<1> When TMHE1 = 0 and TCE50 = 0, 8-bit timer counter H1 operation is stopped.

<2> When TMHE1 = 1 is set, 8-bit timer counter H1 starts a count operation. At that time, the carrier clock is held

at the inactive level.

<3> When the count value of 8-bit timer counter H1 matches the CMP01 register value, the first INTTMH1 signal

is generated, the carrier clock signal is inverted, and the compare register to be compared with 8-bit timer

counter H1 is switched from the CMP01 register to the CMP11 register. 8-bit timer counter H1 is cleared to

00H.

<4> When the count value of 8-bit timer counter H1 matches the CMP11 register value, the INTTMH1 signal is

generated, the carrier clock signal is inverted, and the compare register to be compared with 8-bit timer

counter H1 is switched from the CMP11 register to the CMP01 register. 8-bit timer counter H1 is cleared to

00H. By performing procedures <3> and <4> repeatedly, a carrier clock with duty fixed to other than 50% is

generated.

<5> When the INTTM50 signal is generated, it is synchronized with 8-bit timer H1 count clock and output as the

INTTM5H0 signal.

<6> A carrier signal is output at the first rising edge of the carrier clock if NRZ1 is set to 1.

<7> When NRZ1 = 0, the TOH1 output is held at the high level and is not changed to low level while the carrier

clock is high level (from <6> and <7>, the high-level width of the carrier clock waveform is guaranteed).

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Figure 8-17. Carrier Generator Mode Operation Timing (3/3)

(c) Operation when CMP11 is changed

8-bit timer H1

count clock

8-bit timer counter

H1 count value

00H 01H

N

00H 01H

00H

N

00H 01H

L

00H

M

CMP01

CMP11

TMHE1

<3>

<3>’

L

M

M (L)

INTTMH1

<4>

<5>

<2>

Carrier clock

<1>

<1> When TMHE1 = 1 is set, 8-bit timer counter H1 starts a count operation. At that time, the carrier clock is held

at the inactive level.

<2> When the count value of 8-bit timer counter H1 matches the CMP01 register value, 8-bit timer counter H1 is

cleared and the INTTMH1 signal is output.

<3> The CMP11 register can be rewritten during 8-bit timer H1 operation, however, the changed value (L) is

latched. The CMP11 register is changed when the count value of 8-bit timer counter H1 and the CMP11

register value before the change (M) match (<3>’).

<4> When the count value of 8-bit timer counter H1 and the CMP11 register value before the change (M) match,

the INTTMH1 signal is output, the carrier signal is inverted, and 8-bit timer counter H1 is cleared to 00H.

<5> The timing at which the count value of 8-bit timer counter H1 and the CMP11 register value match again is

indicated by the value after the change (L).

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9.1 Functions of Watchdog Timer

The watchdog timer is used to detect an inadvertent program loop. If a program loop is detected, an internal reset

signal is generated.

When a reset occurs due to the watchdog timer, bit 4 (WDTRF) of the reset control flag register (RESF) is set to 1.

For details of RESF, refer to CHAPTER 16 RESET FUNCTION.

<R>

Table 9-1. Loop Detection Time of Watchdog Timer

Loop Detection Time

During Internal Low-Speed Oscillation

Clock Operation

During High-Speed System

Clock Operation

2¹¹/fR (4.27 ms)

2¹²/fR (8.53 ms)

2¹³/fR (17.07 ms)

2¹⁴/fR (34.13 ms)

2¹⁵/fR (68.27 ms)

2¹⁶/fR (136.53 ms)

2¹⁷/fR (273.07 ms)

2¹⁸/fR (546.13 ms)

2¹³/fXH (819.2 µs)

2¹⁴/fXH (1.64 ms)

2¹⁵/fXH (3.28 ms)

2¹⁶/fXH (6.55 ms)

2¹⁷/fXH (13.11 ms)

2¹⁸/fXH (26.21 ms)

2¹⁹/fXH (52.43 ms)

2²⁰/fXH (104.86 ms)

Remarks 1. fR: Internal low-speed oscillation clock frequency

2. f^XH: High-speed system clock oscillation frequency

3. Figures in parentheses apply to operation at f^R= 480 kHz (MAX.), fXH = 10 MHz.

The operation mode of the watchdog timer (WDT) is switched according to the mask option (option byte if using a

flash memory version) setting of the internal low-speed oscillation clock as shown in Table 9-2.

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Table 9-2. Mask Option Setting and Watchdog Timer Operation Mode

Mask Option

Internal Low-Speed Oscillator Cannot Be

Internal Low-Speed Oscillator Can Be Stopped

Stopped

by Software

Note 1

Watchdog timer clock

source

Fixed to f^R

.

• Selectable by software (f^XH, fR or stopped)

• When reset is released: f^R

Operation after reset

Operation mode selection

Features

Operation starts with the maximum interval

(2¹⁸/fR).

Operation starts with the maximum interval

(2¹⁸/fR).

The interval can be changed only once.

The clock selection/interval can be changed

only once.

The watchdog timer cannot be stopped.

The watchdog timer can be stopped in standby

mode^{Note 2}

.

Notes 1. As long as power is being supplied, the internal low-speed oscillator absolutely cannot be stopped (except

during reset).

2. The conditions under which clock supply to the watchdog timer is stopped differ depending on the clock

source of the watchdog timer.

<1>If the clock source is f^XH, clock supply to the watchdog timer is stopped under the following conditions.

• When fXH is stopped

• In HALT/STOP mode

• During oscillation stabilization time

<2> If the clock source is f^R, clock supply to the watchdog timer is stopped under the following conditions.

• If the CPU clock is f^XHand if fR is stopped by software before execution of the STOP instruction

• In HALT/STOP mode

Remarks 1. f^R: Internal low-speed oscillation clock frequency

2. f^XH: High-speed system clock oscillation frequency

9.2 Configuration of Watchdog Timer

The watchdog timer includes the following hardware.

Table 9-3. Configuration of Watchdog Timer

Item

Configuration

Control registers

Watchdog timer mode register (WDTM)

Watchdog timer enable register (WDTE)

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CHAPTER 9 WATCHDOG TIMER

Figure 9-1. Block Diagram of Watchdog Timer

2¹¹/f

2¹⁸/f

R

to

f

/2²

R

Clock

input

controller

Output

controller

16-bit

counter

Selector

Internal reset signal

f

XH/2⁴

or

2¹³/fXH to

2²⁰/fXH

2

3

Clear

Mask option or option byte

(to set “internal low-speed

0

1

WDCS4 WDCS3 WDCS2 WDCS1 WDCS0

oscillator cannot be stopped” or

“internal low-speed oscillator

can be stopped by software”)

Watchdog timer enable

register (WDTE)

Watchdog timer mode

register (WDTM)

Internal bus

9.3 Registers Controlling Watchdog Timer

The watchdog timer is controlled by the following two registers.

•

Watchdog timer mode register (WDTM)

Watchdog timer enable register (WDTE)

(1) Watchdog timer mode register (WDTM)

This register sets the overflow time and operation clock of the watchdog timer.

This register can be set by an 8-bit memory manipulation instruction and can be read many times, but can be

written only once after reset is released.

RESET input sets this register to 67H.

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CHAPTER 9 WATCHDOG TIMER

Figure 9-2. Format of Watchdog Timer Mode Register (WDTM)

Address: FF98H After reset: 67H R/W

7

0

6

1

5

1

4

3

2

1

0

Symbol

WDTM

WDCS4

WDCS3

WDCS2

WDCS1

WDCS0

WDCS4^{Note 1}WDCS3^{Note 1}

Operation clock selection

0

1

0

1

×

Internal low-speed oscillation clock (fR)

High-speed system clock (fXH)

Watchdog timer operation stopped

WDCS2^{Note 2}WDCS1^{Note 2}WDCS0^{Note 2}

Overflow time setting

<R>

During internal low-speed

oscillation clock operation

During high-speed system

clock operation

0

1

0

1

0

1

0

1

0

1

0

1

0

1

2¹¹/fR (4.27 ms)

2¹²/fR (8.53 ms)

2¹³/fR (17.07 ms)

2¹⁴/fR (34.13 ms)

2¹⁵/fR (68.27 ms)

2¹⁶/fR (136.53 ms)

2¹⁷/fR (273.07 ms)

2¹⁸/fR (546.13 ms)

2¹³/fXH (819.2 µs)

2¹⁴/fXH (1.64 ms)

2¹⁵/fXH (3.28 ms)

2¹⁶/fXH (6.55 ms)

2¹⁷/fXH (13.11 ms)

2¹⁸/fXH (26.21 ms)

2¹⁹/fXH (52.43 ms)

2²⁰/fXH (104.86 ms)

Notes 1. If “internal low-speed oscillator cannot be stopped” is specified by a mask option, this cannot

be set. The internal low-speed oscillation clock will be selected no matter what value is

written.

2. Reset is released at the maximum cycle (WDCS2, WDCS1, WDCS0 = 1, 1, 1).

Cautions 1. If data is written to WDTM, a wait cycle is generated. For details, refer to CHAPTER

28 CAUTIONS FOR WAIT.

2. Set bits 7, 6, and 5 to 0, 1, and 1, respectively (when “internal low-speed oscillator

clock cannot be stopped” is selected by a mask option, other values are ignored).

3. After reset is released, WDTM can be written only once by an 8-bit memory

manipulation instruction. If writing attempted a second time, an internal reset signal

is generated. If the source clock of the watchdog timer is stopped, however, an

internal reset signal is generated when the source clock of the watchdog timer starts

operating again.

4. WDTM cannot be set by a 1-bit memory manipulation instruction.

5. When “internal low-speed oscillator can be stopped by software” is selected by a

mask option and the watchdog timer is stopped by setting WDCS4 to 1, the

watchdog timer does not operate even if WDCS4 is cleared to 0 again. An internal

reset signal is not generated.

Remarks 1. f^R: Internal low-speed oscillation clock frequency

2. f^XH: High-speed system clock oscillation frequency

3. ×: Don’t care

4. Figures in parentheses apply to operation at f^R= 480 kHz (MAX.), fXH = 10 MHz.

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CHAPTER 9 WATCHDOG TIMER

(2) Watchdog timer enable register (WDTE)

Writing ACH to WDTE clears the watchdog timer counter and starts counting again.

This register can be set by an 8-bit memory manipulation instruction.

RESET input sets this register to 9AH.

Figure 9-3. Format of Watchdog Timer Enable Register (WDTE)

Address: FF99H After reset: 9AH R/W

7

6

5

4

3

2

1

0

Symbol

WDTE

Cautions 1. If a value other than ACH is written to WDTE, an internal reset signal is generated. If

the source clock of the watchdog timer is stopped, however, an internal reset signal

is generated when the source clock of the watchdog timer starts operating again.

2. If a 1-bit memory manipulation instruction is executed for WDTE, an internal reset

signal is generated. If the source clock of the watchdog timer is stopped, however,

an internal reset signal is generated when the source clock of the watchdog timer

starts operating again.

3. The value read from WDTE is 9AH (this differs from the written value (ACH)).

The relationship between the watchdog timer operation and the internal reset signal generated by the watchdog

timer is shown below.

Table 9-4. Relationship Between Watchdog Timer Operation and Internal Reset Signal Generated by

Watchdog Timer

Operation

“Internal low-Speed

Oscillator Cannot Be

Stopped” Is Set by Mask

Option (Watchdog Timer

Always Operating)

“Internal low-Speed Oscillator Can Be Stopped by Software” Is Set by Mask

Option

During Watchdog Timer

Operation

Watchdog Timer Stopped

Internal

Set WDCS4 to 1

Source Clock of

Reset Signal

Watchdog Timer Stopped

Generation Source

Watchdog timer

overflow

An internal reset signal

is generated.

An internal reset signal

is generated.

−

Writing to WDTM for

second time

An internal reset signal

is generated.

An internal reset signal

is generated.

An internal reset signal

is not generated.

An internal reset signal

is generated when the

source clock of the

watchdog timer starts

operating again.

Watchdog timer does

not resume operation.

Writing value other than An internal reset signal

An internal reset signal

is generated.

An internal reset signal

is not generated.

An internal reset signal

is generated when the

source clock of the

watchdog timer starts

operating again.

ACH to WDTE

is generated.

Accessing WDTE using

1-bit memory

manipulation instruction

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CHAPTER 9 WATCHDOG TIMER

9.4 Operation of Watchdog Timer

9.4.1 Watchdog timer operation when “Internal low-speed Oscillator cannot be stopped” is selected by mask

option

The operation clock of watchdog timer is fixed to the internal low-speed oscillation clock.

After reset is released, operation is started at the maximum cycle (bits 2, 1, and 0 (WDCS2, WDCS1, WDCS0) of

the watchdog timer mode register (WDTM) = 1, 1, 1). The watchdog timer operation cannot be stopped.

The following shows the watchdog timer operation after reset release.

1. The status after reset release is as follows.

•

Operation clock: Internal low-speed oscillation clock

Cycle: 2¹⁸/ fR (543.13 ms: At operation with fR = 480 kHz (MAX.))

Counting starts

2. The following should be set in the watchdog timer mode register (WDTM) by an 8-bit memory manipulation

instruction^{Notes 1, 2}

Cycle: Set using bits 2 to 0 (WDCS2 to WDCS0)

.

•

3. After the above procedures are executed, writing ACH to WDTE clears the count to 0, enabling recounting.

Notes 1. The operation clock (internal low-speed oscillation clock) cannot be changed. If any value is written to

bits 3 and 4 (WDCS3, WDCS4) of WDTM, it is ignored.

2. As soon as WDTM is written, the counter of the watchdog timer is cleared.

Caution In this mode, operation of the watchdog timer absolutely cannot be stopped even during STOP

instruction execution. For 8-bit timer H1 (TMH1), a division of the internal low-speed oscillation

clock can be selected as the count source, so after STOP instruction execution, clear the

watchdog timer using the interrupt request of TMH1 before the watchdog timer overflows. If this

processing is not performed, an internal reset signal is generated when the watchdog timer

overflows after STOP instruction execution.

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9.4.2 Watchdog timer operation when “Internal low-speed oscillator can be stopped by software” is selected

by mask option

The operation clock of the watchdog timer can be selected as either the internal low-speed oscillation clock or the

high-speed system clock.

After reset is released, operation is started at the maximum cycle of the internal low-speed oscillation clock (bits 2,

1, and 0 (WDCS2, WDCS1, WDCS0) of the watchdog timer mode register (WDTM) = 1, 1, 1).

The following shows the watchdog timer operation after reset release.

1. The status after reset release is as follows.

•

Operation clock: Internal low-speed oscillation clock frequency (f^R)

Cycle: 2¹⁸/ fR (546.13 ms: At operation with fR = 480 kHz (MAX.))

Counting starts

2. The following should be set in the watchdog timer mode register (WDTM) by an 8-bit memory manipulation

instruction^{Notes 1, 2, 3}

.

•

Operation clock: Any of the following can be selected using bits 3 and 4 (WDCS3 and WDCS4).

Internal low-speed oscillation clock (f^R)

High-speed system clock (fXH)

Watchdog timer operation stopped

•

Cycle: Set using bits 2 to 0 (WDCS2 to WDCS0)

3. After the above procedures are executed, writing ACH to WDTE clears the count to 0, enabling recounting.

Notes 1. As soon as WDTM is written, the counter of the watchdog timer is cleared.

2. Set bits 7, 6, and 5 to 0, 1, 1, respectively. Do not set the other values.

3. If the watchdog timer is stopped by setting WDCS4 and WDCS3 to 1 and ×, respectively, an internal

reset signal is not generated even if the following processing is performed.

•

WDTM is written a second time.

A 1-bit memory manipulation instruction is executed to WDTE.

A value other than ACH is written to WDTE.

Caution In this mode, watchdog timer operation is stopped during HALT/STOP instruction execution.

After HALT/STOP mode is released, counting is started again using the operation clock of the

watchdog timer set before HALT/STOP instruction execution by WDTM. At this time, the counter

is not cleared to 0 but holds its value.

For the watchdog timer operation during STOP mode and HALT mode in each status, refer to 9.4.3 Watchdog

timer operation in STOP mode and 9.4.4 Watchdog timer operation in HALT mode.

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CHAPTER 9 WATCHDOG TIMER

9.4.3 Watchdog timer operation in STOP mode (when “Internal low-speed oscillator can be stopped by

software” is selected by mask option)

The watchdog timer stops counting during STOP instruction execution regardless of whether the high-speed

system clock or the internal low-speed oscillation clock is being used.

(1) When the CPU clock and the watchdog timer operation clock are the high-speed system clock (f^XH) when

the STOP instruction is executed

When the STOP instruction is executed, operation of the watchdog timer is stopped. After STOP mode is

released, counting stops for the oscillation stabilization time set by the oscillation stabilization time select register

(OSTS) and then counting is started again using the operation clock before the operation was stopped. At this

time, the counter is not cleared to 0 but holds its value.

Figure 9-4. Operation in STOP Mode (CPU Clock and WDT Operation Clock: High-Speed System Clock)

Normal

operation

Oscillation stabilization time

CPU operation

STOP

Normal operation

f

XH

Oscillation

stopped

Oscillation stabilization time

(set by OSTS register)

fR

Watchdog timer

Operating

Operation stopped

Operating

(2) When the CPU clock is the high-speed system clock (f^XH) and the watchdog timer operation clock is the

internal low-speed oscillation clock (f^R) when the STOP instruction is executed

When the STOP instruction is executed, operation of the watchdog timer is stopped. After STOP mode is

released, counting is started again using the operation clock before the operation was stopped. At this time, the

counter is not cleared to 0 but holds its value.

Figure 9-5. Operation in STOP Mode

(CPU Clock: High-Speed System Clock, WDT Operation Clock: Internal Low-Speed Oscillation Clock)

Normal

operation

Oscillation stabilization time

Normal operation

CPU operation

STOP

fXH

Oscillation

stopped

Oscillation stabilization time

(set by OSTS register)

fR

Watchdog timer

Operating Operation stopped

Operating

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CHAPTER 9 WATCHDOG TIMER

(3) When the CPU clock is the internal low-speed oscillation clock (fR) and the watchdog timer operation

clock is the high-speed system clock (f^XH) when the STOP instruction is executed

When the STOP instruction is executed, operation of the watchdog timer is stopped. After STOP mode is

released, counting is stopped until the timing of <1> or <2>, whichever is earlier, and then counting is started

using the operation clock before the operation was stopped. At this time, the counter is not cleared to 0 but holds

its value.

<1> The oscillation stabilization time set by the oscillation stabilization time select register (OSTS) elapses.

<2> The CPU clock is switched to the high-speed system clock (f^XH).

Figure 9-6. Operation in STOP Mode

(CPU Clock: Internal Low-Speed Oscillation Clock, WDT Operation Clock: High-Speed System Clock)

<1> Timing when counting is started after the oscillation stabilization time set by the oscillation stabilization time

select register (OSTS) has elapsed

Normal operation

(internal low-speed

oscillation clock)

STOP

Clock supply stopped

Normal operation (internal low-speed oscillation clock)

CPU operation

f

XH

Oscillation

stopped

Oscillation stabilization time

(set by OSTS register)

f

R

17 clocks

Watchdog timer

Operating

Operation stopped

Operating

<2> Timing when counting is started after the CPU clock is switched to the high-speed system clock (f^XH)

Normal operation (Internal low-speed oscillation clock)

Normal operation

CPU clock

Note

fR → fXH

(internal low-speed

oscillation clock)

Clock supply

Normal operation (high-speed system clock)

STOP

stopped

CPU operation

f

XH

Oscillation

stopped

Oscillation stabilization time

(set by OSTS register)

fR

17 clocks

Operating

Operation stopped

Operating

Note Confirm the oscillation stabilization time of f^XHusing the oscillation stabilization time counter status register

(OSTC).

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CHAPTER 9 WATCHDOG TIMER

(4) When the CPU clock and the watchdog timer operation clock are the internal low-speed oscillator clock

(f^R) when the STOP instruction is executed

When the STOP instruction is executed, operation of the watchdog timer is stopped. After STOP mode is

released, counting is started again using the operation clock before the operation was stopped. At this time, the

counter is not cleared to 0 but holds its value.

Figure 9-7. Operation in STOP Mode

(CPU Clock and WDT Operation Clock: Internal Low-Speed Oscillation Clock)

Normal operation

(internal low-speed

oscillation clock)

STOP

Clock supply stopped

Normal operation (internal low-speed oscillation clock)

CPU operation

f

XH

Oscillation

stopped

Oscillation stabilization time

(set by OSTS register)

f

R

17 clocks

Operating

Watchdog timer

Operating

Operation stopped

9.4.4 Watchdog timer operation in HALT mode (when “Internal low-speed oscillator can be stopped by

software” is selected by mask option)

The watchdog timer stops counting during HALT instruction execution regardless of whether the CPU clock is the

high-speed system clock (f^XH) or the internal low-speed oscillation clock (fR), or whether the operation clock of the

watchdog timer is the high-speed system clock (f^XH) or the internal low-speed oscillation clock (fR). After HALT mode

is released, counting is started again using the operation clock before the operation was stopped. At this time, the

counter is not cleared to 0 but holds its value.

Figure 9-8. Operation in HALT Mode

Normal operation

HALT

Normal operation

CPU operation

fXH

fR

Watchdog timer

Operating Operation stopped

Operating

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CHAPTER 10 A/D CONVERTER

10.1 Function of A/D Converter

The A/D converter converts an analog input signal into a digital value, and consists of up to four channels (ANI0 to

ANI3) with a resolution of 10 bits.

The A/D converter has the following two functions.

(1) 10-bit resolution A/D conversion

10-bit resolution A/D conversion is carried out repeatedly for one channel selected from analog inputs ANI0 to

ANI3. Each time an A/D conversion operation ends, an interrupt request (INTAD) is generated.

(2) Power-fail detection function

This function is used to detect a voltage drop in a battery. The values of the A/D conversion result (ADCR

register value) and power-fail comparison threshold register (PFT) are compared. INTAD is generated only when

a comparative condition has been matched.

185

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Figure 10-1. Block Diagram of A/D Converter

AVREF

ADCS bit

ANI0/P20

ANI1/P21

ANI2/P22

ANI3/P23

Sample & hold circuit

Voltage comparator

Successive

Note

approximation

register (SAR)

V

SS

INTAD

Controller

Comparator

A/D conversion result

register (ADCR)

Power-fail comparison

threshold register (PFT)

2

ADS1 ADS0

ADCS

FR2

FR1

FR0

ADCE

PFEN PFCM

Power-fail comparison

mode register (PFM)

Analog input channel

specification register

(ADS)

A/D converter mode

register (ADM)

Internal bus

Note VSS and AVSS are internally connected in the µPD780862 Subseries. Be sure to connect VSS to a stabilized

GND (= 0 V).

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10.2 Configuration of A/D Converter

The A/D converter includes the following hardware.

Table 10-1. Registers of A/D Converter Used on Software

Item

Registers

Configuration

A/D conversion result register (ADCR)

A/D converter mode register (ADM)

Analog input channel specification register (ADS)

Power-fail comparison mode register (PFM)

Power-fail comparison threshold register (PFT)

(1) ANI0 to ANI3 pins

These are the analog input pins of the 4-channel A/D converter. They input analog signals to be converted into

digital signals. Pins other than the one selected as the analog input pin by the analog input channel specification

register (ADS) can be used as input port pins.

(2) Sample & hold circuit

The sample & hold circuit samples the input signal of the analog input pin selected by the selector when A/D

conversion is started, and holds the sampled analog input voltage value during A/D conversion.

(3) Series resistor string

The series resistor string is connected between AV^REFand VSS, and generates a voltage to be compared with the

analog input signal.

Figure 10-2. Circuit Configuration of Series Resistor String

AV^REF

P-ch

ADCS

Series resistor string

V^SS

(4) Voltage comparator

The voltage comparator compares the sampled analog input voltage and the output voltage of the series resistor

string.

(5) Successive approximation register (SAR)

This register compares the sampled analog voltage and the voltage of the series resistor string, and converts the

result, starting from the most significant bit (MSB).

When the voltage value is converted into a digital value down to the least significant bit (LSB) (end of A/D

conversion), the contents of the SAR register are transferred to the A/D conversion result register (ADCR).

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CHAPTER 10 A/D CONVERTER

(6) A/D conversion result register (ADCR)

The result of A/D conversion is loaded from the successive approximation register (SAR) to this register each

time A/D conversion is completed, and the ADCR register holds the result of A/D conversion in its higher 10 bits

(the lower 6 bits are fixed to 0).

(7) Controller

When A/D conversion has been completed or when the power-fail detection function is used, this controller

compares the result of A/D conversion (value of the ADCR register) and the value of the power-fail comparison

threshold register (PFT). It generates the interrupt INTAD only if a specified comparison condition is satisfied as

a result.

(8) AV^REFpin

This pin inputs an analog power/reference voltage to the A/D converter. Always use this pin at the same potential

as that of the V^DDpin even when the A/D converter is not used.

The signal input to ANI0 to ANI3 is converted into a digital signal, based on the voltage applied across AVREF and

V^SS.

(9) V^SSpin

The V^SSpin is the ground potential pin.

Caution V^SSand AVSS are internally connected in the µPD780862 Subseries. Be sure to connect VSS to a

stabilized GND (= 0 V).

(10) A/D converter mode register (ADM)

This register is used to set the conversion time of the analog input signal to be converted, and to start or stop the

conversion operation.

(11) Analog input channel specification register (ADS)

This register is used to specify the port that inputs the analog voltage to be converted into a digital signal.

(12) Power-fail comparison mode register (PFM)

This register is used to set the power-fail monitor mode.

(13) Power-fail comparison threshold register (PFT)

This register is used to set the threshold value that is to be compared with the value of the A/D conversion result

register (ADCR).

10.3 Registers Used in A/D Converter

The A/D converter uses the following five registers.

•

A/D converter mode register (ADM)

Analog input channel specification register (ADS)

A/D conversion result register (ADCR)

Power-fail comparison mode register (PFM)

Power-fail comparison threshold register (PFT)

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CHAPTER 10 A/D CONVERTER

(1) A/D converter mode register (ADM)

This register sets the conversion time for analog input to be A/D converted, and starts/stops conversion.

ADM can be set by a 1-bit or 8-bit memory manipulation instruction.

RESET input clears this register to 00H.

Figure 10-3. Format of A/D Converter Mode Register (ADM)

Address: FF28H After reset: 00H R/W

Symbol

<7>

6

0

5

4

3

2

0

1

0

<0>

ADM ADCS

FR2

FR1

FR0

ADCE

ADCS

A/D conversion operation control

0

1

Stops conversion operation

Enables conversion operation

Conversion time selection^{Note 1}

= 10 MHz

FR2

FR1

FR0

fX

= 2 MHz

f = 8.38 MHz

X

288/f

240/f

192/f

144/f

120/f

X

144

120

µ

s

0

1

0

1

0

1

0

1

0

1

0

34.3

28.6

22.9

17.2

14.3

11.5

µ

s

28.8

24.0

19.2

14.4

12.0

µ

s

96

72

60

48

s

µ

96/f

X

9.6

µ

Other than above

Setting prohibited

ADCE

Boost reference voltage generator operation control^{Note 2}

Stops operation of reference voltage generator

0

1

Enables operation of reference voltage generator

Notes 1. Set so that the A/D conversion time is as follows.

• Standard products, (A) grade products: 14 µs or longer but less than 100 µs

• (A1) grade products:

• (A2) grade products:

14 µs or longer but less than 60 µs

16 µs or longer but less than 48 µs

2. A booster circuit is incorporated to realize low-voltage operation. The operation of the circuit that

generates the reference voltage for boosting is controlled by ADCE, and it takes 14 µs from operation

start to operation stabilization. Therefore, when ADCS is set to 1 after 14 µs or more has elapsed

from the time ADCE is set to 1, the conversion result at that time has priority over the first conversion

result.

Remark f^X: High-speed system clock oscillation frequency

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CHAPTER 10 A/D CONVERTER

Table 10-2. Settings of ADCS and ADCE

ADCS

ADCE

A/D Conversion Operation

0

1

0

1

0

1

Stop status (DC power consumption path does not exist)

Conversion waiting mode (only reference voltage generator consumes power)

Conversion mode (reference voltage generator operation stopped^Note

)

Conversion mode (reference voltage generator operates)

Note Data of first conversion cannot be used.

Figure 10-4. Timing Chart When Boost Reference Voltage Generator Is Used

Boost reference voltage generator: operating

ADCE

Boost reference voltage

Conversion

operation

Conversion

waiting

Conversion

operation

Conversion stopped

ADCS

Note

Note The time from the rising of the ADCE bit to the rising of the ADCS bit must be 14 µs or longer to stabilize the

reference voltage.

Cautions 1. A/D conversion must be stopped before rewriting bits FR0 to FR2 to values other than the

identical data.

2. For the A/D converter sampling time and A/D conversion start delay time, refer to 10.6

Cautions for A/D Converter (11).

3. If data is written to ADM, a wait cycle is generated. For details, refer to CHAPTER 28

CAUTIONS FOR WAIT.

Remark f^X: High-speed system clock oscillation frequency

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CHAPTER 10 A/D CONVERTER

(2) Analog input channel specification register (ADS)

This register specifies the analog voltage input port to be A/D converted.

ADS can be set by a 1-bit or 8-bit memory manipulation instruction.

RESET input clears this register to 00H.

Figure 10-5. Format of Analog Input Channel Specification Register (ADS)

Address: FF29H After reset: 00H R/W

Symbol

ADS

7

0

6

0

5

0

4

0

3

0

2

0

1

0

ADS1

ADS0

ADS1

ADS0

Analog input channel specification

0

1

0

1

0

1

ANI0

ANI1

ANI2

ANI3

Cautions 1. Be sure to set bits 2 to 7 of ADS to 0.

2. If data is written to ADS, a wait cycle is generated. For details, refer to CHAPTER 28

CAUTIONS FOR WAIT.

(3) A/D conversion result register (ADCR)

This register is a 16-bit register that stores the A/D conversion result. The lower six bits are fixed to 0. Each time

A/D conversion ends, the conversion result is loaded from the successive approximation register, and is stored in

ADCR in order starting from the most significant bit (MSB). FF09H indicates the higher 8 bits of the conversion

result, and FF08H indicates the lower 2 bits of the conversion result.

ADCR can be read by a 16-bit memory manipulation instruction.

RESET input makes ADCR undefined.

Figure 10-6. Format of A/D Conversion Result Register (ADCR)

Address: FF08H, FF09H After reset: Undefined

FF09H

R

FF08H

Symbol

ADCR

0

Cautions 1. When writing to the A/D converter mode register (ADM) and analog input channel

specification register (ADS), the contents of ADCR may become undefined. Read the

conversion result following conversion completion before writing to ADM and ADS. Using

timing other than the above may cause an incorrect conversion result to be read.

2. If data is read from ADCR, a wait cycle is generated. For details, see CHAPTER 28

CAUTIONS FOR WAIT.

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(4) Power-fail comparison mode register (PFM)

The power-fail comparison mode register (PFM) is used to compare the A/D conversion result (value of the

ADCR register) and the value of the power-fail comparison threshold register (PFT).

PFM can be set by a 1-bit or 8-bit memory manipulation instruction.

RESET input clears this register to 00H.

Figure 10-7. Format of Power-Fail Comparison Mode Register (PFM)

Address: FF2AH After reset: 00H R/W

Symbol

<7>

<6>

5

0

4

0

3

0

2

0

1

0

PFM PFEN

PFCM

PFEN

Power-fail comparison enable

0

1

Stops power-fail comparison (used as a normal A/D converter)

Enables power-fail comparison (used for power-fail detection)

PFCM

Power-fail comparison mode selection

0

1

Interrupt request signal (INTAD) generation

Higher 8 bits of

ADCR ≥ PFT

Higher 8 bits of

ADCR < PFT

No INTAD generation

Higher 8 bits of

ADCR ≥ PFT

Higher 8 bits of

ADCR < PFT

INTAD generation

Caution If data is written to PFM, a wait cycle is generated. For details, refer to CHAPTER 28

CAUTIONS FOR WAIT.

(5) Power-fail comparison threshold register (PFT)

The power-fail comparison threshold register (PFT) is a register that sets the threshold value when comparing the

values with the A/D conversion result.

8-bit data in PFT is compared to the higher 8 bits (FF09H) of the 10-bit A/D conversion result.

PFT can be set by an 8-bit memory manipulation instruction.

RESET input clears this register to 00H.

Figure 10-8. Format of Power-Fail Comparison Threshold Register (PFT)

Address: FF2BH After reset: 00H R/W

Symbol

7

6

5

4

3

2

1

0

PFT PFT7

PFT6

PFT5

PFT4

PFT3

PFT2

PFT1

PFT0

Caution If data is written to PFT, a wait cycle is generated. For details, refer to CHAPTER 28 CAUTIONS

FOR WAIT.

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10.4 A/D Converter Operations

10.4.1 Basic operations of A/D converter

<1> Set ADCE to 1.

<R>

<2> Select the channel and the conversion time to be used in the analog input mode by using ADS1, ADS0, and

FR2 to FR0.

<3> Set ADCS to 1 and start the conversion operation.

(<4> to <10> are operations performed by hardware.)

<4> The voltage input to the selected analog input channel is sampled by the sample & hold circuit.

<5> When sampling has been done for a certain time, the sample & hold circuit is placed in the hold state and the

input analog voltage is held until the A/D conversion operation has ended.

<6> Bit 9 of the successive approximation register (SAR) is set. The series resistor string voltage tap is set to

(1/2) AV^REFby the tap selector.

<7> The voltage difference between the series resistor string voltage tap and analog input is compared by the

voltage comparator. If the analog input is greater than (1/2) AV^REF, the MSB of SAR remains set to 1. If the

analog input is smaller than (1/2) AV^REF, the MSB is reset to 0.

<8> Next, bit 8 of SAR is automatically set to 1, and the operation proceeds to the next comparison. The series

resistor string voltage tap is selected according to the preset value of bit 9, as described below.

•

Bit 9 = 1: (3/4) AV^REF

Bit 9 = 0: (1/4) AVREF

The voltage tap and analog input voltage are compared and bit 8 of SAR is manipulated as follows.

•

Analog input voltage ≥ Voltage tap: Bit 8 = 1

Analog input voltage < Voltage tap: Bit 8 = 0

<9> Comparison is continued in this way up to bit 0 of SAR.

<10> Upon completion of the comparison of 10 bits, an effective digital result value remains in SAR, and the result

value is transferred to the A/D conversion result register (ADCR) and then latched.

At the same time, the A/D conversion end interrupt request (INTAD) can also be generated.

<11> Repeat steps <4> to <10>, until ADCS is cleared to 0.

To stop the A/D converter, clear ADCS to 0.

To restart A/D conversion from the status of ADCE = 1, start from <3>. To restart A/D conversion from the

status of ADCE = 0, however, start from <2>.

Cautions 1. Make sure the period of <1> to <3> is 14 µs or more.

2. It is no problem if the order of <1> and <2> is reversed.

<R>

3. <1> can be omitted. However, do not use the first conversion in this case.

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Figure 10-9. Basic Operation of A/D Converter

Conversion time

Sampling time

Sampling

A/D converter

operation

A/D conversion

Conversion

result

Undefined

SAR

Conversion

result

ADCR

INTAD

A/D conversion operations are performed continuously until bit 7 (ADCS) of the A/D converter mode register (ADM)

is reset (0) by software.

If a write operation is performed to one of the ADM, analog input channel specification register (ADS), power-fail

comparison mode register (PFM), or power-fail comparison threshold register (PFT) during an A/D conversion

operation, the conversion operation is initialized, and if the ADCS bit is set (1), conversion starts again from the

beginning.

RESET input makes the A/D conversion result register (ADCR) undefined.

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10.4.2 Input voltage and conversion results

The relationship between the analog input voltage input to the analog input pins (ANI0 to ANI3) and the theoretical

A/D conversion result (stored in the A/D conversion result register (ADCR)) is shown by the following expression.

V^AIN

SAR = INT (

× 1024 + 0.5)

AV^REF

ADCR = SAR × 64

or

AVREF

(ADCR − 0.5) ×

≤ V^AIN< (ADCR + 0.5) ×

1024

where, INT( ): Function which returns integer part of value in parentheses

V^AIN: Analog input voltage

AV^REF: AVREF pin voltage

ADCR: A/D conversion result register (ADCR) value

SAR:

Successive approximation register

Figure 10-10 shows the relationship between the analog input voltage and the A/D conversion result.

Figure 10-10. Relationship Between Analog Input Voltage and A/D Conversion Result

SAR

ADCR

1023

FFC0H

1022

FF80H

FF40H

00C0H

0080H

0040H

0000H

1021

A/D conversion

result

3

2

1

0

1

3

2

5

3

2043 1022 2045 1023 2047

2048 1024 2048 1024 2048

1

2048 1024 2048 1024 2048 1024

Input voltage/AV_REF

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10.4.3 A/D converter operation mode

The operation mode of the A/D converter is the select mode. One channel of analog input is selected from ANI0 to

ANI3 by the analog input channel specification register (ADS) and A/D conversion is executed.

In addition, the following two functions can be selected by setting of bit 7 (PFEN) of the power-fail comparison

mode register (PFM).

•

Normal 10-bit A/D converter (PFEN = 0)

Power-fail detection function (PFEN = 1)

(1) A/D conversion operation (when PFEN = 0)

By setting bit 7 (ADCS) of the A/D converter mode register (ADM) to 1 and bit 7 (PFEN) of the power-fail

comparison mode register (PFM) to 0, A/D conversion of the voltage applied to the analog input pin specified by

the analog input channel specification register (ADS) is started.

When A/D conversion has been completed, the result of the A/D conversion is stored in the A/D conversion result

register (ADCR), and an interrupt request signal (INTAD) is generated. Once the next A/D conversion has started

and when one A/D conversion has been completed, the A/D conversion operation after that is immediately started.

The A/D conversion operations are repeated until new data is written to ADS.

If ADM, ADS, the power-fail comparison mode register (PFM), and the power-fail comparison threshold register

(PFT) are rewritten during A/D conversion, the A/D conversion operation under execution is stopped and

restarted from the beginning.

If 0 is written to ADCS during A/D conversion, A/D conversion is immediately stopped. At this time, the

conversion result is undefined.

Figure 10-11. A/D Conversion Operation

Rewriting ADM

ADCS = 1

Rewriting ADS

ANIn

ADCS = 0

A/D conversion

ANIn

ANIm

Conversion is stopped

Conversion result is not retained

Stopped

ANIn

ANIm

ADCR

INTAD

(PFEN = 0)

Remarks 1. n = 0 to 3

2. m = 0 to 3

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(2) Power-fail detection function (when PFEN = 1)

By setting bit 7 (ADCS) of the A/D converter mode register (ADM) to 1 and bit 7 (PFEN) of the power-fail

comparison mode register (PFM) to 1, the A/D conversion operation of the voltage, which applied to the analog

input pin specified by the analog input channel specification register (ADS), is started.

When the A/D conversion has been completed, the result of the A/D conversion is stored in the A/D conversion

result register (ADCR), the values are compared with power-fail comparison threshold register (PFT), and an

interrupt request signal (INTAD) is generated under the condition specified by bit 6 (PFCM) of PFM.

<1> When PFEN = 1 and PFCM = 0

The higher 8 bits of ADCR and PFT values are compared when A/D conversion ends and INTAD is only

generated when “the higher 8 bits of ADCR ≥ PFT”.

<2> When PFEN = 1 and PFCM = 1

The higher 8 bits of ADCR and PFT values are compared when A/D conversion ends and INTAD is only

generated when “the higher 8 bits of ADCR < PFT”.

Figure 10-12. Power-Fail Detection (When PFEN = 1 and PFCM = 0)

A/D conversion

ANIn

80H

ANIn

7FH

ANIn

80H

Higher 8 bits

of ADCR

PFT

80H

INTAD

(PFEN = 1)

Note

First conversion

Condition match

Note If the conversion result is not read before the end of the next conversion after INTAD is output, the result is

replaced by the next conversion result.

Remark n = 0 to 3

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The setting methods are described below.

When used as A/D conversion operation

•

<1> Set bit 0 (ADCE) of the A/D converter mode register (ADM) to 1.

<2> Select the channel and conversion time using bits 1 and 0 (ADS1, ADS0) of the analog input channel

specification register (ADS) and bits 5 to 3 (FR2 to FR0) of ADM.

<3> Set bit 7 (ADCS) of ADM to 1 and start the A/D conversion operation.

<4> An interrupt request signal (INTAD) is generated.

<5> Transfer the A/D conversion data to the A/D conversion result register (ADCR).

<6> Change the channel using bits 1 and 0 (ADS1, ADS0) of ADS and start the A/D conversion operation.

<7> An interrupt request signal (INTAD) is generated.

<8> Transfer the A/D conversion data to the A/D conversion result register (ADCR).

<9> Clear ADCS to 0.

<10> Clear ADCE to 0.

Cautions 1. Make sure the period of <1> to <3> is 14 µs or more.

2. It is no problem if the order of <1> and <2> is reversed.

3. <1> can be omitted. However, do not use the first conversion result after <3> in this case.

4. The period from <4> to <7> differs from the conversion time set using bits 5 to 3 (FR2 to

FR0) of ADM. The period from <6> to <7> is the conversion time set using FR2 to FR0.

•

When used as power-fail function

<1> Set bit 7 (PFEN) of the power-fail comparison mode register (PFM).

<2> Set power-fail comparison condition using bit 6 (PFCM) of PFM.

<3> Set bit 0 (ADCE) of the A/D converter mode register (ADM) to 1.

<4> Select the channel and conversion time using bits 1 and 0 (ADS1, ADS0) of the analog input channel

specification register (ADS) and bits 5 to 3 (FR2 to FR0) of ADM.

<5> Set a threshold value to the power-fail comparison threshold register (PFT).

<6> Set bit 7 (ADCS) of ADM to 1.

<7> Transfer the A/D conversion data to the A/D conversion result register (ADCR).

<8> The higher 8 bits of ADCR and PFT are compared and an interrupt request signal (INTAD) is generated

if the conditions match.

<9> Change the channel using bits 1 and 0 (ADS1, ADS0) of ADS.

<10> Transfer the A/D conversion data to the A/D conversion result register (ADCR).

<11> The higher 8 bits of ADCR and the power-fail comparison threshold register (PFT) are compared and an

interrupt request signal (INTAD) is generated if the conditions match.

<12> Clear ADCS to 0.

<13> Clear ADCE to 0.

Cautions 1. Make sure the period of <3> to <6> is 14 µs or more.

2. It is no problem if order of <3>, <4>, and <5> is changed.

3. <3> must not be omitted if the power-fail function is used.

4. The period from <7> to <11> differs from the conversion time set using bits 5 to 3 (FR2 to

FR0) of ADM. The period from <9> to <11> is the conversion time set using FR2 to FR0.

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10.5 How to Read A/D Converter Characteristics Table

Here, special terms unique to the A/D converter are explained.

(1) Resolution

This is the minimum analog input voltage that can be identified. That is, the percentage of the analog input

voltage per bit of digital output is called 1LSB (Least Significant Bit). The percentage of 1LSB with respect to the

full scale is expressed by %FSR (Full Scale Range).

1LSB is as follows when the resolution is 10 bits.

1LSB = 1/2¹⁰= 1/1024

= 0.098%FSR

Accuracy has no relation to resolution, but is determined by overall error.

(2) Overall error

This shows the maximum error value between the actual measured value and the theoretical value.

Zero-scale error, full-scale error, integral linearity error, and differential linearity errors that are combinations of

these express the overall error.

Note that the quantization error is not included in the overall error in the characteristics table.

(3) Quantization error

When analog values are converted to digital values, a 1/2LSB error naturally occurs. In an A/D converter, an

analog input voltage in a range of 1/2LSB is converted to the same digital code, so a quantization error cannot

be avoided.

Note that the quantization error is not included in the overall error, zero-scale error, full-scale error, integral

linearity error, and differential linearity error in the characteristics table.

Figure 10-13. Overall Error

Figure 10-14. Quantization Error

……

1

……

1

Ideal line

Overall

error

Quantization error

1/2LSB

……

0

……

0

AV^REF

0

AVREF

Analog input

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CHAPTER 10 A/D CONVERTER

(4) Zero-scale error

This shows the difference between the actual measurement value of the analog input voltage and the theoretical

value (1/2LSB) when the digital output changes from 0......000 to 0......001.

If the actual measurement value is greater than the theoretical value, it shows the difference between the actual

measurement value of the analog input voltage and the theoretical value (3/2LSB) when the digital output

changes from 0……001 to 0……010.

(5) Full-scale error

This shows the difference between the actual measurement value of the analog input voltage and the theoretical

value (Full-scale − 3/2LSB) when the digital output changes from 1......110 to 1......111.

(6) Integral linearity error

This shows the degree to which the conversion characteristics deviate from the ideal linear relationship. It

expresses the maximum value of the difference between the actual measurement value and the ideal straight line

when the zero-scale error and full-scale error are 0.

(7) Differential linearity error

While the ideal width of code output is 1LSB, this indicates the difference between the actual measurement value

and the ideal value.

Figure 10-15. Zero-Scale Error

Figure 10-16. Full-Scale Error

111

Full-scale error

Ideal line

011

111

110

010

001

101

000

Ideal line

Zero-scale error

000

0

AVREF–3 AVREF–2 AVREF–1 AVREF

0

1

2

3

AV^REF

Analog input (LSB)

Figure 10-17. Integral Linearity Error

Figure 10-18. Differential Linearity Error

……

1

……

1

Ideal 1LSB width

Ideal line

Differential

linearity error

Integral linearity

error

……

0 0

……

0

AVREF

0

Analog input

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CHAPTER 10 A/D CONVERTER

(8) Conversion time

This expresses the time from when the analog input voltage was applied to the time when the digital output was

obtained.

The sampling time is included in the conversion time in the characteristics table.

(9) Sampling time

This is the time the analog switch is turned on for the analog voltage to be sampled by the sample & hold circuit.

Sampling

time

Conversion time

10.6 Cautions for A/D Converter

(1) Operating current in standby mode

The A/D converter stops operating in the standby mode. At this time, the operating current can be reduced by

setting bit 7 (ADCS) of the A/D converter mode register (ADM) to 0 (see Figure 10-2).

(2) Input range of ANI0 to ANI3

Observe the rated range of the ANI0 to ANI3 input voltage. If a voltage of AV^REFor higher and VSS or lower (even

in the range of absolute maximum ratings) is input to an analog input channel, the converted value of that channel

becomes undefined. In addition, the converted values of the other channels may also be affected.

(3) Conflicting operations

<1> Conflict between A/D conversion result register (ADCR) write and ADCR read by instruction upon the end

of conversion

ADCR read has priority. After the read operation, the new conversion result is written to ADCR.

<2> Conflict between ADCR write and A/D converter mode register (ADM) write or analog input channel

specification register (ADS) write upon the end of conversion

ADM or ADS write has priority. ADCR write is not performed, nor is the conversion end interrupt signal

(INTAD) generated.

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(4) Noise countermeasures

To maintain the 10-bit resolution, attention must be paid to noise input to the AV^REFpin and pins ANI0 to ANI3.

Because the effect increases in proportion to the output impedance of the analog input source, it is recommended

that a capacitor be connected externally, as shown in Figure 10-19, to reduce noise.

Figure 10-19. Analog Input Pin Connection

If there is a possibility that noise equal to or higher than AV^REFor

equal to or lower than V^SSmay enter, clamp with a diode with a

small V value (0.3 V or lower).

F

Reference

voltage

input

AV^REF

ANI0 to ANI3

C = 100 to 1,000 pF

V

SS

(5) ANI0/P20 to ANI3/P23

<1> The analog input pins (ANI0 to ANI3) are also used as input port pins (P20 to P23).

When A/D conversion is performed with any of ANI0 to ANI3 selected, do not access port 2 while

conversion is in progress; otherwise the conversion resolution may be degraded.

<2> If a digital pulse is applied to the pins adjacent to the pins currently used for A/D conversion, the expected

value of the A/D conversion may not be obtained due to coupling noise. Therefore, do not apply a pulse to

the pins adjacent to the pin undergoing A/D conversion.

(6) Input impedance of ANI0 to ANI3 pins

In this A/D converter, the internal sampling capacitor is charged and sampling is performed for approx. one sixth

of the conversion time.

Since only the leakage current flows other than during sampling and the current for charging the capacitor also

flows during sampling, the input impedance fluctuates and has no meaning.

To perform sufficient sampling, however, it is recommended to make the output impedance of the analog input

source 10 kΩ or lower, or attach a capacitor of around 100 pF to the ANI0 to ANI3 pins (see Figure 10-19).

(7) AV^REFpin input impedance

A series resistor string of several tens of 10 kΩ is connected between the AVREF and VSS pins.

Therefore, if the output impedance of the reference voltage source is high, this will result in a series connection to

the series resistor string between the AV^REFand VSS pins, resulting in a large reference voltage error.

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CHAPTER 10 A/D CONVERTER

(8) Interrupt request flag (ADIF)

The interrupt request flag (ADIF) is not cleared even if the analog input channel specification register (ADS) is

changed.

Therefore, if an analog input pin is changed during A/D conversion, the A/D conversion result and ADIF for the

pre-change analog input may be set just before the ADS rewrite. Caution is therefore required since, at this time,

when ADIF is read immediately after the ADS rewrite, ADIF is set despite the fact A/D conversion for the post-

change analog input has not ended.

When A/D conversion is stopped and then resumed, clear ADIF before the A/D conversion operation is resumed.

Figure 10-20. Timing of A/D Conversion End Interrupt Request Generation

ADS rewrite

(start of ANIn conversion)

ADS rewrite

(start of ANIm conversion)

ADIF is set but ANIm conversion

has not ended.

A/D conversion

ANIn

ANIm

ANIn

ANIm

ADCR

INTAD

ANIn

ANIm

Remarks 1. n = 0 to 3

2. m = 0 to 3

(9) Conversion results just after A/D conversion start

The first A/D conversion value immediately after A/D conversion starts may not fall within the rating range if the

ADCS bit is set to 1 within 14 µs after the ADCE bit was set to 1, or if the ADCS bit is set to 1 with the ADCE bit =

0. Take measures such as polling the A/D conversion end interrupt request (INTAD) and removing the first

conversion result.

(10) A/D conversion result register (ADCR) read operation

When a write operation is performed to the A/D converter mode register (ADM) and analog input channel

specification register (ADS), the contents of ADCR may become undefined. Read the conversion result following

conversion completion before writing to ADM and ADS. Using timing other than the above may cause an

incorrect conversion result to be read.

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CHAPTER 10 A/D CONVERTER

(11) A/D converter sampling time and A/D conversion start delay time

The A/D converter sampling time differs depending on the set value of the A/D converter mode register (ADM).

The delay time exists until actual sampling is started after A/D converter operation is enabled.

When using a set in which the A/D conversion time must be strictly observed, care is required for the contents

shown in Figure 10-21 and Table 10-3.

Figure 10-21. Timing of A/D Converter Sampling and A/D Conversion Start Delay

ADCS ← 1 or ADS rewrite

ADCS

Sampling timing

INTAD

Wait

A/D

Sampling

time

Sampling

time

period conversion

start delay

time

Conversion time

Table 10-3. A/D Converter Sampling Time and A/D Conversion Start Delay Time (ADM Set Value)

FR2

FR1

FR0

Conversion Time

Sampling Time

A/D Conversion Start Delay Time^Note

MIN.

MAX.

0

1

0

1

0

1

0

1

0

1

0

288/fX

240/fX

192/fX

144/fX

120/fX

96/fX

40/fX

32/fX

28/fX

24/fX

16/fX

14/fX

12/fX

36/fX

32/fX

28/fX

18/fX

16/fX

14/fX

32/fX

24/fX

20/fX

16/fX

12/fX

Other than above

Setting prohibited

−

Note The A/D conversion start delay time is the time after wait period. For the wait function, refer to CHAPTER 28

CAUTIONS FOR WAIT.

Remark f^X: High-speed system clock oscillation frequency

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CHAPTER 10 A/D CONVERTER

(12) Internal equivalent circuit

The equivalent circuit of the analog input block is shown below.

Figure 10-22. Internal Equivalent Circuit of ANIn Pin

R1

R2

ANIn

C1

C2

C3

Table 10-4. Resistance and Capacitance Values of Equivalent Circuit (Reference Values)

AVREF

R1

R2

C1

C2

C3

Flash Memory Version

Mask ROM Version

2.7 V

4.5 V

12 kΩ

4 kΩ

8 kΩ

8 pF

3 pF

2 pF

0.6 pF

2.7 kΩ

1.4 pF

Remarks 1. The resistance and capacitance values shown in Table 10-4 are not guaranteed values.

2. n = 0 to 3

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CHAPTER 11 SERIAL INTERFACE UART6

11.1 Functions of Serial Interface UART6

Serial interface UART6 has the following two modes.

(1) Operation stop mode

This mode is used when serial transfer is not executed and can enable a reduction in the power consumption.

For details, refer to 11.4.1 Operation stop mode.

(2) Asynchronous serial interface (UART) mode

This mode supports the LIN (Local Interconnect Network)-bus. The functions of this mode are outlined below.

For details, see 11.4.2 Asynchronous serial interface (UART) mode and 11.4.3 Dedicated baud rate

generator.

•

Two-pin configuration T^XD6: Transmit data output pin

RXD6: Receive data input pin

•

Data length of communication data can be selected from 7 or 8 bits.

Dedicated internal 8-bit baud rate generator allowing any baud rate to be set

Transmission and reception can be performed independently.

Twelve operating clock inputs selectable

MSB- or LSB-first communication selectable

Inverted transmission operation

Synchronous break field transmission is 13-bit length output.

More than 11 bits can be identified for synchronous break field reception (SBF reception flag provided).

Cautions 1. The T^XD6 output inversion function inverts only the transmission side and not the reception

side. To use this function, the reception side must be ready for reception of inverted data.

2. If clock supply to serial interface UART6 is not stopped (e.g., in the HALT mode), normal

operation continues. If clock supply to serial interface UART6 is stopped (e.g., in the STOP

mode), each register stops operating, and holds the value immediately before clock supply

was stopped. The T^XD6 pin also holds the value immediately before clock supply was

stopped and outputs it. However, the operation is not guaranteed after clock supply is

resumed. Therefore, reset the circuit so that POWER6 = 0, RXE6 = 0, and TXE6 = 0.

3. If data is continuously transmitted, the communication timing from the stop bit to the next

start bit is extended two operating clocks of the macro. However, this does not affect the

result of communication because the reception side initializes the timing when it has

detected a start bit. Do not use the continuous transmission function if UART6 is used in

the LIN communication.

206

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Remark LIN stands for Local Interconnect Network and is a low-speed (1 to 20 kbps) serial communication

protocol designed to reduce the cost of an automotive network.

LIN uses single-master communication, and up to 15 slaves can be connected to one master.

A LIN slave is used to control switches, actuators, and sensors, which are connected to the LIN master

via the LIN.

The LIN master is usually connected to a network such as CAN (Controller Area Network). The LIN bus

is a single-wire type and each node is connected to the bus via a transceiver conforming to ISO9141.

The LIN protocol defines that the master transmits frames that include baud rate information, and a

slave receives this information and corrects the baud rate error to that of the master. Therefore,

communication is enabled if the baud rate error of the slave is within 15%.

Figures 11-1 and 11-2 outline the transmission and reception operations of LIN.

Figure 11-1. LIN Transmission Operation

Wakeup

signal frame

Synchronous

break field

Synchronous

field

Identifier

field

Data field

Data field Checksum

field

Sleep

bus

13-bit^{Note 2}SBF

transmission

55H

Data

8 bits^{Note 1}

transmission transmissiontransmissiontransmissiontransmission

TX6

Note 3

INTST6

Notes 1. The wakeup signal frame is substituted by 80H transmission in the 8-bit mode.

2. The synchronous break field is output by hardware. The output width is adjusted by baud rate

generator control register 6 (BRGC6) (see 11.4.2 (2) (h) SBF transmission).

3. INTST6 is output on completion of each transmission. It is also output when SBF is transmitted.

Remark The interval between each field is controlled by software.

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CHAPTER 11 SERIAL INTERFACE UART6

Figure 11-2. LIN Reception Operation

Wakeup

signal frame

Synchronous

break field

Synchronous Identifier Data field Data field Checksum

field

Sleep

bus

SF

reception

ID

Data

reception reception reception reception^{Note 5}

13 bits^{Note 2}

SBF

reception

RX6

Disable

Enable

Note 3

Reception interrupt

(INTSR6)

Note 1

Edge detection

(INTP0)

Note 4

Enable

Capture timer

Disable

Notes 1. The wakeup signal is detected at the edge of the pin, and enables UART6 and sets the SBF reception

mode.

2. Reception continues until the STOP bit is detected. When an SBF with low-level data of 11 bits or

more has been detected, it is assumed that SBF reception has been completed correctly, and an

interrupt signal is output. If an SBF with low-level data of less than 11 bits has been detected, it is

assumed that an SBF reception error has occurred. The interrupt signal is not output and the SBF

reception mode is restored.

3. If SBF reception has been completed correctly, an interrupt signal is output. This SBF reception

completion interrupt enables the capture timer. Detection of errors OVE6, PE6, and FE6 is suppressed,

and error detection processing of UART communication and data transfer of the shift register and

RXB6 is not performed. The shift register holds the reset value FFH.

4. Calculate the baud rate error from the bit length of the synchronous field, disable UART6 after SF

reception, and then re-set baud rate generator control register 6 (BRGC6).

5. Distinguish the checksum field by software. Also perform processing by software to initialize UART6

after reception of the checksum field and to set the SBF reception mode again.

To perform a LIN receive operation, use a configuration like the one shown in Figure 11-3.

The wakeup signal transmitted from the LIN master is received by detecting the edge of the external interrupt

(INTP0). The length of the synchronous field transmitted from the LIN master can be measured using the external

event capture operation of 16-bit timer/event counter 00, and the baud rate error can be calculated.

The input signal of the reception port input (RxD6) can be input to the external interrupt (INTP0) and 16-bit

timer/event counter 00 by port input switch control (ISC0/ISC1), without connecting RxD6 and INTP0/TI000 externally.

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Figure 11-3. Port Configuration for LIN Reception Operation

Selector

P14/RxD6/<INTP0>

RXD6 input

Port mode

(PM14)

Output latch

(P14)

Selector

P00/INTP0/TI000/MCGO

INTP0 input

Port mode

(PM00)

Port input

switch control

(ISC0)

Output latch

(P00)

<ISC0>

0: Select INTP0 (P00)

1: Select RxD6 (P14)

Selector

TI000 input

Port input

switch control

(ISC1)

<ISC1>

0: Select TI000 (P00)

1: Select RxD6 (P14)

Remark ISC0, ISC1: Bits 0 and 1 of the input switch control register (ISC) (see Figure 11-11)

The peripheral functions used in the LIN communication operation are shown below.

• External interrupt (INTP0); wakeup signal detection

Use: Detects the wakeup signal edges and detects start of communication.

• 16-bit timer/event counter 00 (TI000); baud rate error detection

Use: Detects the baud rate error (measures the TI000 input edge interval in the capture mode) by detecting the

synchronous field (SF) length and divides it by the number of bits.

• Serial interface UART6

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11.2 Configuration of Serial Interface UART6

Serial interface UART6 includes the following hardware.

Table 11-1. Configuration of Serial Interface UART6

Item

Registers

Configuration

Receive buffer register 6 (RXB6)

Receive shift register 6 (RXS6)

Transmit buffer register 6 (TXB6)

Transmit shift register 6 (TXS6)

Control registers

Asynchronous serial interface operation mode register 6 (ASIM6)

Asynchronous serial interface reception error status register 6 (ASIS6)

Asynchronous serial interface transmission status register 6 (ASIF6)

Clock selection register 6 (CKSR6)

Baud rate generator control register 6 (BRGC6)

Asynchronous serial interface control register 6 (ASICL6)

Input switch control register (ISC)

Port mode register 1 (PM1)

Port register 1 (P1)

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(1) Receive buffer register 6 (RXB6)

This 8-bit register stores parallel data converted by receive shift register 6 (RXS6).

Each time 1 byte of data has been received, new receive data is transferred to this register from receive shift

register 6 (RXS6). If the data length is set to 7 bits, data is transferred as follows.

•

In LSB-first reception, the receive data is transferred to bits 0 to 6 of RXB6 and the MSB of RXB6 is always 0.

In MSB-first reception, the receive data is transferred to bits 1 to 7 of RXB6 and the LSB of RXB6 is always 0.

If an overrun error (OVE6) occurs, the receive data is not transferred to RXB6.

RXB6 can be read by an 8-bit memory manipulation instruction. No data can be written to this register.

RESET input sets this register to FFH.

(2) Receive shift register 6 (RXS6)

This register converts the serial data input to the R^XD6 pin into parallel data.

RXS6 cannot be directly manipulated by a program.

(3) Transmit buffer register 6 (TXB6)

This buffer register is used to set transmit data. Transmission is started when data is written to TXB6.

This register can be read or written by an 8-bit memory manipulation instruction.

RESET input sets this register to FFH.

Cautions 1. Do not write data to TXB6 when bit 1 (TXBF6) of asynchronous serial interface transmission

status register 6 (ASIF6) is 1.

2. Do not refresh (write the same value to) TXB6 by software during a communication

operation (when bit 7 (POWER6) and bit 6 (TXE6) of asynchronous serial interface operation

mode register 6 (ASIM6) are 1 or when bit 7 (POWER6) and bit 5 (RXE6) of ASIM6 are 1).

(4) Transmit shift register 6 (TXS6)

This register transmits the data transferred from TXB6 from the T^XD6 pin as serial data. Data is transferred from

TXB6 immediately after TXB6 is written for the first transmission, or immediately before INTST6 occurs after one

frame was transmitted for continuous transmission. Data is transferred from TXB6 and transmitted from the T^XD6

pin at the falling edge of the base clock.

TXS6 cannot be directly manipulated by a program.

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11.3 Registers Controlling Serial Interface UART6

Serial interface UART6 is controlled by the following nine registers.

•

Asynchronous serial interface operation mode register 6 (ASIM6)

Asynchronous serial interface reception error status register 6 (ASIS6)

Asynchronous serial interface transmission status register 6 (ASIF6)

Clock selection register 6 (CKSR6)

Baud rate generator control register 6 (BRGC6)

Asynchronous serial interface control register 6 (ASICL6)

Input switch control register (ISC)

Port mode register 1 (PM1)

Port register 1 (P1)

(1) Asynchronous serial interface operation mode register 6 (ASIM6)

This 8-bit register controls the serial communication operations of serial interface UART6.

This register can be set by a 1-bit or 8-bit memory manipulation instruction.

RESET input sets this register to 01H.

Remark ASIM6 can be refreshed (the same value is written) by software during a communication operation

(when bit 7 (POWER6) and bit 6 (TXE6) of ASIM6 = 1 or bit 7 (POWER6) and bit 5 (RXE6) of ASIM6

= 1).

Figure 11-5. Format of Asynchronous Serial Interface Operation Mode Register 6 (ASIM6) (1/2)

Address: FF50H After reset: 01H R/W

Symbol

ASIM6

<7>

<6>

<5>

4

3

2

1

0

POWER6

TXE6

RXE6

PS61

PS60

CL6

SL6

ISRM6

POWER6

0^{Note 1}

Enables/disables operation of internal operation clock

Disables operation of the internal operation clock (fixes the clock to low level) and asynchronously

resets the internal circuit^{Note 2}

Enables operation of the internal operation clock

.

1^{Note 3}

TXE6

Enables/disables transmission

0

1

Disables transmission (synchronously resets the transmission circuit).

Enables transmission

Notes 1. The output of the TXD6 pin goes high and the input from the RXD6 pin is fixed to the high level when

POWER6 = 0.

2. Asynchronous serial interface reception error status register 6 (ASIS6), asynchronous serial interface

transmission status register 6 (ASIF6), bit 7 (SBRF6) and bit 6 (SBRT6) of asynchronous serial

interface control register 6 (ASICL6), and receive buffer register 6 (RXB6) are reset.

3. Operation of the 8-bit counter output is enabled at the second base clock after 1 is written to the

POWER6 bit.

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Figure 11-5. Format of Asynchronous Serial Interface Operation Mode Register 6 (ASIM6) (2/2)

RXE6

Enables/disables reception

Disables reception (synchronously resets the reception circuit).

Enables reception

0

1

PS61

PS60

Transmission operation

Does not output parity bit.

Reception operation

Reception without parity

0

1

0

1

0

1

Outputs 0 parity.

Reception as 0 parity^Note

Judges as odd parity.

Judges as even parity.

Outputs odd parity.

Outputs even parity.

CL6

0

Specifies character length of transmit/receive data

Character length of data = 7 bits

Character length of data = 8 bits

1

SL6

0

Specifies number of stop bits of transmit data

Number of stop bits = 1

Number of stop bits = 2

1

ISRM6

Enables/disables occurrence of reception completion interrupt in case of error

“INTSRE6” occurs in case of error (at this time, INTSR6 does not occur).

“INTSR6” occurs in case of error (at this time, INTSRE6 does not occur).

0

1

Note If “reception as 0 parity” is selected, the parity is not judged. Therefore, bit 2 (PE6) of asynchronous serial

interface reception error status register 6 (ASIS6) is not set and the error interrupt does not occur.

Cautions 1. At startup, set POWER6 to 1 and then set TXE6 to 1. To stop the operation, clear TXE6 to 0

and then clear POWER6 to 0.

2. At startup, set POWER6 to 1 and then set RXE6 to 1. To stop the operation, clear RXE6 to 0

and then clear POWER6 to 0.

3. Set POWER6 to 1 and then set RXE6 to 1 while a high level is input to the RxD6 pin. If

POWER6 is set to 1 and RXE6 is set to 1 while a low level is input, reception is started.

4. Clear the TXE6 and RXE6 bits to 0 before rewriting the PS61, PS60, and CL6 bits.

5. Fix the PS61 and PS60 bits to 0 when UART6 is used in the LIN communication operation.

6. Make sure that TXE6 = 0 when rewriting the SL6 bit. Reception is always performed with “the

number of stop bits = 1”, and therefore, is not affected by the set value of the SL6 bit.

7. Make sure that RXE6 = 0 when rewriting the ISRM6 bit.

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(2) Asynchronous serial interface reception error status register 6 (ASIS6)

This register indicates an error status on completion of reception by serial interface UART6. It includes three

error flag bits (PE6, FE6, OVE6).

This register is read-only by an 8-bit memory manipulation instruction.

RESET input, bit 7 (POWER6) of ASIM6 = 0, or bit 5 (RXE6) of ASIM6 = 0 clears this register to 00H. 00H is

read when this register is read.

Figure 11-6. Format of Asynchronous Serial Interface Reception Error Status Register 6 (ASIS6)

Address: FF53H After reset: 00H R

Symbol

ASIS6

7

0

6

0

5

0

4

0

3

0

2

1

0

PE6

FE6

OVE6

PE6

0

Status flag indicating parity error

If POWER6 = 0 and RXE6 = 0, or if ASIS6 register is read

1

If the parity of transmit data does not match the parity bit on completion of reception

FE6

0

Status flag indicating framing error

If POWER6 = 0 and RXE6 = 0, or if ASIS6 register is read

If the stop bit is not detected on completion of reception

1

OVE6

Status flag indicating overrun error

0

1

If POWER6 = 0 and RXE6 = 0, or if ASIS6 register is read

If receive data is set to the RXB6 register and the next reception operation is completed before the

data is read.

Cautions 1. The operation of the PE6 bit differs depending on the set values of the PS61 and PS60 bits of

asynchronous serial interface mode register 6 (ASIM6).

2. The first bit of the receive data is checked as the stop bit, regardless of the number of stop

bits.

3. If an overrun error occurs, the next receive data is not written to receive buffer register 6

(RXB6) but discarded.

4. If data is read from ASIS6, a wait cycle is generated. For details, refer to CHAPTER 28

CAUTIONS FOR WAIT.

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(3) Asynchronous serial interface transmission status register 6 (ASIF6)

This register indicates the status of transmission by serial interface UART6. It includes two status flag bits

(TXBF6 and TXSF6).

Transmission can be continued without disruption even during an interrupt period, by writing the next data to the

TXB6 register after data has been transferred from the TXB6 register to the TXS6 register.

This register is read-only by an 8-bit memory manipulation instruction.

RESET input, bit 7 (POWER6) of ASIM6 = 0, or bit 5 (RXE6) of ASIM6 = 0 clears this register to 00H

Figure 11-7. Format of Asynchronous Serial Interface Transmission Status Register 6 (ASIF6)

Address: FF55H After reset: 00H R

Symbol

ASIF6

7

0

6

0

5

0

4

0

3

0

2

0

1

0

TXBF6

TXSF6

TXBF6

Transmit buffer data flag

0

1

If POWER6 = 0 or TXE6 = 0, or if data is transferred to transmit shift register 6 (TXS6)

If data is written to transmit buffer register 6 (TXB6) (if data exists in TXB6)

TXSF6

0

Transmit shift register data flag

If POWER6 = 0 or TXE6 = 0, or if the next data is not transferred from transmit buffer register 6

(TXB6) after completion of transfer

1

If data is transferred from transmit buffer register 6 (TXB6) (if data transmission is in progress)

Cautions 1. To transmit data continuously, write the first transmit data (first byte) to the TXB6 register.

Be sure to check that the TXBF6 flag is “0”. If so, write the next transmit data (second byte)

to the TXB6 register. If data is written to the TXB6 register while the TXBF6 flag is “1”, the

transmit data cannot be guaranteed.

2. To initialize the transmission unit upon completion of continuous transmission, be sure to

check that the TXSF6 flag is “0” after generation of the transmission completion interrupt,

and then execute initialization. If initialization is executed while the TXSF6 flag is “1”, the

transmit data cannot be guaranteed.

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(4) Clock selection register 6 (CKSR6)

This register selects the base clock of serial interface UART6.

CKSR6 can be set by an 8-bit memory manipulation instruction.

RESET input clears this register to 00H.

Remark CKSR6 can be refreshed (the same value is written) by software during a communication operation

(when bit 7 (POWER6) and bit 6 (TXE6) of ASIM6 = 1 or bit 7 (POWER6) and bit 5 (RXE6) of ASIM6

= 1).

Figure 11-8. Format of Clock Selection Register 6 (CKSR6)

Address: FF56H After reset: 00H R/W

Symbol

CKSR6

7

0

6

0

5

0

4

0

3

2

1

0

TPS63

TPS62

TPS61

TPS60

TPS63

TPS62

TPS61

TPS60

Base clock (fXCLK6) selection

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

fX (10 MHz)

fX/2 (5 MHz)

fX/2²(2.5 MHz)

fX/2³(1.25 MHz)

fX/2⁴(625 kHz)

fX/2⁵(312.5 kHz)

fX/2⁶(156.25 kHz)

fX/2⁷(78.13 kHz)

fX/2⁸(39.06 kHz)

fX/2⁹(19.53 kHz)

fX/2¹⁰(9.77 kHz)

TM50 output^Note

Setting prohibited

Other than above

Note When the TM50 output is selected as the base clock, observe the following.

• PWM mode (TMC506 = 1)

Set the clock so that the duty will be 50% and start the operation of 8-bit timer/event counter 50 in

advance.

• Clear & start mode entered on match of TM50 and CR50 (TMC506 = 0)

Enable the timer F/F inversion operation (TMC501 = 1) and start the operation of 8-bit timer/event counter

50 in advance.

Cautions 1. When the internal oscillation clock is selected as the clock to be supplied to the CPU, the

clock of the internal oscillator is divided and supplied as the count clock. If the base clock is

the internal oscillation clock, the operation of serial interface UART6 is not guaranteed.

2. Make sure POWER6 = 0 when rewriting TPS63 to TPS60.

Remarks 1. Figures in parentheses are for operation with f^X= 10 MHz.

2. f^X: High-speed system clock oscillation frequency

3. TMC506: Bit 6 of 8-bit timer mode control register 50 (TMC50)

TMC501: Bit 1 of TMC50

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(5) Baud rate generator control register 6 (BRGC6)

This register sets the division value of the 8-bit counter of serial interface UART6.

BRGC6 can be set by an 8-bit memory manipulation instruction.

RESET input sets this register to FFH.

Remark BRGC6 can be refreshed (the same value is written) by software during a communication operation

(when bit 7 (POWER6) and bit 6 (TXE6) of ASIM6 = 1 or bit 7 (POWER6) and bit 5 (RXE6) of ASIM6

= 1).

Figure 11-9. Format of Baud Rate Generator Control Register 6 (BRGC6)

Address: FF57H After reset: FFH R/W

Symbol

BRGC6

7

6

5

4

3

2

1

0

MDL67 MDL66 MDL65 MDL64 MDL63 MDL62 MDL61 MDL60

k

Output clock selection of

8-bit counter

0

1

×

0

×

0

1

×

0

1

0

×

8

Setting prohibited

fXCLK6/8

9

fXCLK6/9

10

fXCLK6/10

•

1

0

1

0

1

0

1

252 fXCLK6/252

253 fXCLK6/253

254 fXCLK6/254

255 fXCLK6/255

Cautions 1. Make sure that bit 6 (TXE6) and bit 5 (RXE6) of the ASIM6 register = 0 when rewriting the

MDL67 to MDL60 bits.

2. The baud rate is the output clock of the 8-bit counter divided by 2.

Remarks 1. f^XCLK6: Frequency of base clock selected by the TPS63 to TPS60 bits of CKSR6 register

2. k: Value set by MDL67 to MDL60 bits (k = 8, 9, 10, ..., 255)

3. ×: Don’t care

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CHAPTER 11 SERIAL INTERFACE UART6

(6) Asynchronous serial interface control register 6 (ASICL6)

This register controls the serial communication operations of serial interface UART6.

ASICL6 can be set by a 1-bit or 8-bit memory manipulation instruction.

RESET input sets this register to 16H.

Caution ASICL6 can be refreshed (the same value is written) by software during a communication

operation (when bit 7 (POWER6) and bit 6 (TXE6) of ASIM6 = 1 or bit 7 (POWER6) and bit 5

(RXE6) of ASIM6 = 1). However, do not set both SBRT6 and SBTT6 to 1 by a refresh operation

during SBF reception (SBRT6 = 1) or SBF transmission (until INTST6 occurs since SBTT6 has

been set (1)), because it may re-trigger SBF reception or SBF transmission.

Figure 11-10. Format of Asynchronous Serial Interface Control Register 6 (ASICL6)

Address: FF58H After reset: 16H R/W^Note

Symbol

ASICL6

<7>

<6>

5

0

4

1

3

0

2

1

0

SBRF6

SBRT6

DIR6

TXDLV6

SBRF6

SBF reception status flag

0

1

If POWER6 = 0 and RXE6 = 0 or if SBF reception has been completed correctly

SBF reception in progress

SBRT6

SBF reception trigger

0

1

−

SBF reception trigger

DIR6

First bit specification

0

1

MSB

LSB

TXDLV6

Enables/disables inverting TXD6 output

Normal output of TXD6

0

1

Inverted output of TXD6

Note Bits 2 to 5 and 7 are read-only.

<R>

Cautions 1. In the case of an SBF reception error, return the mode to the SBF reception mode. The status

of SBRF6 flag is held (1).

2. Before setting the SBRT6 bit, make sure that bit 7 (POWER6) and bit 5 (RXE6) of ASIM6 = 1.

3. The read value of the SBRT6 bit is always 0. SBRT6 is automatically cleared to 0 after SBF

reception has been correctly completed.

4. Before rewriting the DIR6 and TXDLV6 bits, clear the TXE6 and RXE6 bits to 0.

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CHAPTER 11 SERIAL INTERFACE UART6

(7) Input switch control register (ISC)

The input switch control register (ISC) is used to receive a status signal transmitted from the master during LIN

(Local Interconnect Network) reception. The input source is switched by setting ISC.

This register can be set by a 1-bit or 8-bit memory manipulation instruction.

RESET input clears this register to 00H.

Figure 11-11. Format of Input Switch Control Register (ISC)

Address: FF4FH After reset: 00H R/W

Symbol

ISC

7

0

6

0

5

0

4

0

3

0

2

0

1

0

ISC1

ISC0

ISC1

TI000 input source selection

0

1

TI000 (P00)

RxD6 (P14)

ISC0

INTP0 input source selection

0

1

INTP0 (P00)

RxD6 (P14)

(8) Port mode register 1 (PM1)

This register sets port 1 input/output in 1-bit units.

When using the P13/TxD6/INTP1/(TOH1)/(MCGO) pin for serial interface data output, clear PM13 to 0 and set

the output latch of P13 to 1.

When using the P14/RxD6/<INTP0> pin for serial interface data input, set PM14 to 1. The output latch of P14 at

this time may be 0 or 1.

PM1 can be set by a 1-bit or 8-bit memory manipulation instruction.

RESET input sets this register to FFH.

Figure 11-12. Format of Port Mode Register 1 (PM1)

Address: FF21H After reset: FFH R/W

Symbol

PM1

7

1

6

1

5

4

3

2

1

0

PM15

PM14

PM13

PM12

PM11

PM10

PM1n

P1n pin I/O mode selection (n = 0 to 5)

0

1

Output mode (output buffer on)

Input mode (output buffer off)

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11.4 Operation of Serial Interface UART6

Serial interface UART6 has the following two modes.

• Operation stop mode

• Asynchronous serial interface (UART) mode

11.4.1 Operation stop mode

In this mode, serial communication cannot be executed; therefore, the power consumption can be reduced. In

addition, the pins can be used as ordinary port pins in this mode. To set the operation stop mode, clear bits 7, 6, and

5 (POWER6, TXE6, and RXE6) of ASIM6 to 0.

(1) Register used

The operation stop mode is set by asynchronous serial interface operation mode register 6 (ASIM6).

ASIM6 can be set by a 1-bit or 8-bit memory manipulation instruction.

RESET input sets this register to 01H.

Address: FF50H After reset: 01H R/W

Symbol

ASIM6

<7>

<6>

<5>

4

3

2

1

0

POWER6

TXE6

RXE6

PS61

PS60

CL6

SL6

ISRM6

POWER6

0^{Note 1}

Enables/disables operation of internal operation clock

Disables operation of the internal operation clock (fixes the clock to low level) and asynchronously

resets the internal circuit^{Note 2}

.

TXE6

0

Enables/disables transmission

Disables transmission operation (synchronously resets the transmission circuit).

RXE6

0

Enables/disables reception

Disables reception (synchronously resets the reception circuit).

Notes 1. The output of the T^XD6 pin goes high and the input from the RXD6 pin is fixed to high level when

POWER6 = 0.

2. Asynchronous serial interface reception error status register 6 (ASIS6), asynchronous serial interface

transmission status register 6 (ASIF6), bit 7 (SBRF6) and bit 6 (SBRT6) of asynchronous serial

interface control register 6 (ASICL6), and receive buffer register 6 (RXB6) are reset.

Caution Clear POWER6 to 0 after clearing TXE6 and RXE6 to 0 to set the operation stop mode.

To start the operation, set POWER6 to 1, and then set TXE6 and RXE6 to 1.

Remark To use the RxD6/P14/<INTP0> and TxD6/P13/INTP1/(TOH1)/(MCGO) pins as general-purpose port

pins, see CHAPTER 4 PORT FUNCTIONS.

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CHAPTER 11 SERIAL INTERFACE UART6

11.4.2 Asynchronous serial interface (UART) mode

In this mode, data of 1 byte is transmitted/received following a start bit, and a full-duplex operation can be

performed.

A dedicated UART baud rate generator is incorporated, so that communication can be executed at a wide range of

baud rates.

(1) Registers used

• Asynchronous serial interface operation mode register 6 (ASIM6)

• Asynchronous serial interface reception error status register 6 (ASIS6)

• Asynchronous serial interface transmission status register 6 (ASIF6)

• Clock selection register 6 (CKSR6)

• Baud rate generator control register 6 (BRGC6)

• Asynchronous serial interface control register 6 (ASICL6)

• Input switch control register (ISC)

• Port mode register 1 (PM1)

• Port register 1 (P1)

The basic procedure of setting an operation in the UART mode is as follows.

<1> Set the CKSR6 register (see Figure 11-8).

<2> Set the BRGC6 register (see Figure 11-9).

<3> Set bits 0 to 4 (ISRM6, SL6, CL6, PS60, PS61) of the ASIM6 register (see Figure 11-5).

<4> Set bits 0 and 1 (TXDLV6, DIR6) of the ASICL6 register (see Figure 11-10).

<5> Set bit 7 (POWER6) of the ASIM6 register to 1.

<6> Set bit 6 (TXE6) of the ASIM6 register to 1. → Transmission is enabled.

Set bit 5 (RXE6) of the ASIM6 register to 1. → Reception is enabled.

<7> Write data to transmit buffer register 6 (TXB6). → Data transmission is started.

Caution Take relationship with the other party of communication when setting the port mode register

and port register.

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The relationship between the register settings and pins is shown below.

Table 11-2. Relationship Between Register Settings and Pins

POWER6 TXE6

RXE6

PM13

P13

PM14

P14

UART6

Pin Function

Operation

TxD6/P13/INTP1/ RxD6/P14/<INTP0>

(TOH1)/(MCGO)

Note

0

1

0

1

0

1

0

1

×

Stop

P13

P14

RxD6

P14

Note

×

1

×

Reception

Transmission

Note

0

1

×

TxD6

1

×

Transmission/

reception

RxD6

Note Can be set as port function.

Remark ×:

don’t care

POWER6: Bit 7 of asynchronous serial interface operation mode register 6 (ASIM6)

TXE6:

RXE6:

PM1×:

P1×:

Bit 6 of ASIM6

Bit 5 of ASIM6

Port mode register

Port output latch

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(2) Communication operation

(a) Normal transmit/receive data format

Figure 11-13 shows the format and waveform example of the normal transmit/receive data.

Figure 11-13. Format of Normal UART Transmit/Receive Data

1. LSB-first transmission/reception

1 data frame

Start

bit

Parity

bit

D0

D1

D2

D3

D4

D5

D6

D7

Stop bit

Character bits

2. MSB-first transmission/reception

1 data frame

Start

bit

Parity

bit

D7

D6

D5

D4

D3

D2

D1

D0

Stop bit

Character bits

One data frame consists of the following bits.

• Start bit ... 1 bit

• Character bits ... 7 or 8 bits

• Parity bit ... Even parity, odd parity, 0 parity, or no parity

• Stop bit ... 1 or 2 bits

The character bit length, parity, and stop bit length in one data frame are specified by asynchronous serial

interface operation mode register 6 (ASIM6).

Whether data is communicated with the LSB or MSB first is specified by bit 1 (DIR6) of asynchronous serial

interface control register 6 (ASICL6).

Whether the T^XD6 pin outputs normal or inverted data is specified by bit 0 (TXDLV6) of ASICL6.

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Figure 11-14. Example of Normal UART Transmit/Receive Data Waveform

1. Data length: 8 bits, LSB first, Parity: Even parity, Stop bit: 1 bit, Communication data: 55H

1 data frame

Start

D0

D1

D2

D3

D4

D5

D6

D7

Parity

Stop

2. Data length: 8 bits, MSB first, Parity: Even parity, Stop bit: 1 bit, Communication data: 55H

1 data frame

Start

D7

D6

D5

D4

D3

D2

D1

D0

Parity

Stop

3. Data length: 8 bits, MSB first, Parity: Even parity, Stop bit: 1 bit, Communication data: 55H, T^XD6 pin

inverted output

1 data frame

Start

D7

D6

D5

D4

D3

D2

D1

D0

Parity

Stop

4. Data length: 7 bits, LSB first, Parity: Odd parity, Stop bit: 2 bits, Communication data: 36H

1 data frame

Start

D0

D1

D2

D3

D4

D5

D6

Parity

Stop

5. Data length: 8 bits, LSB first, Parity: None, Stop bit: 1 bit, Communication data: 87H

1 data frame

Start

D0

D1

D2

D3

D4

D5

D6

D7

Stop

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CHAPTER 11 SERIAL INTERFACE UART6

(b) Parity types and operation

The parity bit is used to detect a bit error in communication data. Usually, the same type of parity bit is used

on both the transmission and reception sides. With even parity and odd parity, a 1-bit (odd number) error

can be detected. With zero parity and no parity, an error cannot be detected.

Caution Fix the PS61 and PS60 bits to 0 when the device is used in LIN communication operation.

(i) Even parity

• Transmission

Transmit data, including the parity bit, is controlled so that the number of bits that are “1” is even.

The value of the parity bit is as follows.

If transmit data has an odd number of bits that are “1”: 1

If transmit data has an even number of bits that are “1”: 0

• Reception

The number of bits that are “1” in the receive data, including the parity bit, is counted. If it is odd, a

parity error occurs.

(ii) Odd parity

• Transmission

Unlike even parity, transmit data, including the parity bit, is controlled so that the number of bits that

are “1” is odd.

If transmit data has an odd number of bits that are “1”: 0

If transmit data has an even number of bits that are “1”: 1

• Reception

The number of bits that are “1” in the receive data, including the parity bit, is counted. If it is even, a

parity error occurs.

(iii) 0 parity

The parity bit is cleared to 0 when data is transmitted, regardless of the transmit data.

The parity bit is not detected when the data is received. Therefore, a parity error does not occur

regardless of whether the parity bit is “0” or “1”.

(iv) No parity

No parity bit is appended to the transmit data.

Reception is performed assuming that there is no parity bit when data is received. Because there is no

parity bit, a parity error does not occur.

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(c) Normal transmission

The T^XD6 pin outputs a high level when bit 7 (POWER6) of asynchronous serial interface operation mode

register 6 (ASIM6) is set to 1. If bit 6 (TXE6) of ASIM6 is then set to 1, transmission is enabled.

Transmission can be started by writing transmit data to transmit buffer register 6 (TXB6). The start bit, parity

bit, and stop bit are automatically appended to the data.

When transmission is started, the data in TXB6 is transferred to transmit shift register 6 (TXS6). After that,

the data is sequentially output from TXS6 to the T^XD6 pin. When transmission is completed, the parity bit

and stop bit set by ASIM6 are appended and a transmission completion interrupt request (INTST6) is

generated.

Transmission is stopped until the data to be transmitted next is written to TXB6.

Figure 11-15 shows the timing of the transmission completion interrupt request (INTST6). This interrupt

occurs as soon as the last stop bit has been output.

Figure 11-15. Normal Transmission Completion Interrupt Request Timing

1. Stop bit length: 1

Parity

TX

D6 (output)

INTST6

Start

D0

D1

D2

D6

D7

Stop

2. Stop bit length: 2

TX

D6 (output)

INTST6

Start

D0

D1

D2

D6

D7

Parity

Stop

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(d) Continuous transmission

The next transmit data can be written to transmit buffer register 6 (TXB6) as soon as transmit shift register 6

(TXS6) has started its shift operation. Consequently, even while the INTST6 interrupt is being serviced after

transmission of one data frame, data can be continuously transmitted and an efficient communication rate

can be realized. In addition, the TXB6 register can be efficiently written twice (2 bytes) without having to wait

for the transmission time of one data frame, by reading bit 0 (TXSF6) of asynchronous serial interface

transmission status register 6 (ASIF6) when the transmission completion interrupt has occurred.

To transmit data continuously, be sure to reference the ASIF6 register to check the transmission status and

whether the TXB6 register can be written, and then write the data.

Cautions 1. The TXBF6 and TXSF6 flags of the ASIF6 register change from “10” to “11”, and to “01”

during continuous transmission. To check the status, therefore, do not use a

combination of the TXBF6 and TXSF6 flags for judgment. Read only the TXBF6 flag

when executing continuous transmission.

2. When the device is used in LIN communication, the continuous transmission function

cannot be used. Make sure that asynchronous serial interface transmission status

register 6 (ASIF6) is 00H before writing transmit data to transmit buffer register 6 (TXB6).

TXBF6

Writing to TXB6 Register

0

1

Writing enabled

Writing disabled

Caution To transmit data continuously, write the first transmit data (first byte) to the TXB6 register.

Be sure to check that the TXBF6 flag is “0”. If so, write the next transmit data (second byte)

to the TXB6 register. If data is written to the TXB6 register while the TXBF6 flag is “1”, the

transmit data cannot be guaranteed.

The communication status can be checked using the TXSF6 flag.

TXSF6

Transmission Status

0

1

Transmission is completed.

Transmission is in progress.

Cautions 1. To initialize the transmission unit upon completion of continuous transmission, be sure

to check that the TXSF6 flag is “0” after generation of the transmission completion

interrupt, and then execute initialization. If initialization is executed while the TXSF6

flag is “1”, the transmit data cannot be guaranteed.

2. During continuous transmission, an overrun error may occur, which means that the

next transmission was completed before execution of INTST6 interrupt servicing after

transmission of one data frame. An overrun error can be detected by developing a

program that can count the number of transmit data and by referencing the TXSF6 flag.

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Figure 11-16 shows an example of the continuous transmission processing flow.

Figure 11-16. Example of Continuous Transmission Processing Flow

Set registers.

Write TXB6.

Transfer

executed necessary

number of times?

Yes

No

Read ASIF6

TXBF6 = 0?

Yes

Write TXB6.

Transmission

completion interrupt

occurs?

No

Yes

Transfer

executed necessary

number of times?

Yes

No

Read ASIF6

TXSF6 = 0?

Yes

Completion of

transmission processing

Remark TXB6: Transmit buffer register 6

ASIF6: Asynchronous serial interface transmission status register 6

TXBF6: Bit 1 of ASIF6 (transmit buffer data flag)

TXSF6: Bit 0 of ASIF6 (transmit shift register data flag)

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Figure 11-17 shows the timing of starting continuous transmission, and Figure 11-18 shows the timing of

ending continuous transmission.

Figure 11-17. Timing of Starting Continuous Transmission

Start

T

X

D6

Data (1)

Parity Stop

Data (2)

Parity

Stop

INTST6

TXB6

FF

Data (1)

Data (2)

Data (3)

TXS6

Data (1)

Data (2)

Data (3)

TXBF6

TXSF6

Note

Note When ASIF6 is read, there is a period in which TXBF6 and TXSF6 = 1, 1. Therefore, judge whether

writing is enabled using only the TXBF6 bit.

Remark T^XD6:

TXD6 pin (output)

INTST6: Interrupt request signal

TXB6:

TXS6:

Transmit buffer register 6

Transmit shift register 6

ASIF6: Asynchronous serial interface transmission status register 6

TXBF6: Bit 1 of ASIF6

TXSF6: Bit 0 of ASIF6

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Figure 11-18. Timing of Ending Continuous Transmission

Start

TX

D6

Data (n)

Parity

Stop

Data (n − 1) Parity

Stop

INTST6

TXB6

Data (n − 1)

Data (n)

TXS6

FF

Data (n − 1)

Data (n)

TXBF6

TXSF6

POWER6 or TXE6

Remark T^XD6:

INTST6:

TXD6 pin (output)

Interrupt request signal

Transmit buffer register 6

Transmit shift register 6

TXB6:

TXS6:

ASIF6:

TXBF6:

TXSF6:

Asynchronous serial interface transmission status register 6

Bit 1 of ASIF6

Bit 0 of ASIF6

POWER6: Bit 7 of asynchronous serial interface operation mode register (ASIM6)

TXE6:

Bit 6 of asynchronous serial interface operation mode register (ASIM6)

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CHAPTER 11 SERIAL INTERFACE UART6

(e) Normal reception

Reception is enabled and the R^XD6 pin input is sampled when bit 7 (POWER6) of asynchronous serial

interface operation mode register 6 (ASIM6) is set to 1 and then bit 5 (RXE6) of ASIM6 is set to 1.

The 8-bit counter of the baud rate generator starts counting when the falling edge of the R^XD6 pin input is

detected. When the set value of baud rate generator control register 6 (BRGC6) has been counted, the

R^XD6 pin input is sampled again ( in Figure 11-19). If the RXD6 pin is low level at this time, it is recognized

as a start bit.

When the start bit is detected, reception is started, and serial data is sequentially stored in the receive shift

register (RXS6) at the set baud rate. When the stop bit has been received, the reception completion interrupt

(INTSR6) is generated and the data of RXS6 is written to receive buffer register 6 (RXB6). If an overrun

error (OVE6) occurs, however, the receive data is not written to RXB6.

Even if a parity error (PE6) occurs while reception is in progress, reception continues to the reception

position of the stop bit, and an error interrupt (INTSR6/INTSRE6) is generated on completion of reception.

Figure 11-19. Reception Completion Interrupt Request Timing

Start

D0

D1

D2

D3

D4

D5

D6

D7

Parity

Stop

RX

D6 (input)

INTSR6

RXB6

Cautions 1. Be sure to read receive buffer register 6 (RXB6) even if a reception error occurs.

Otherwise, an overrun error will occur when the next data is received, and the reception

error status will persist.

2. Reception is always performed with the “number of stop bits = 1”. The second stop bit

is ignored.

3. Be sure to read asynchronous serial interface reception error status register 6 (ASIS6)

before reading RXB6.

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(f) Reception error

Three types of errors may occur during reception: a parity error, framing error, or overrun error. If the error

flag of asynchronous serial interface reception error status register 6 (ASIS6) is set as a result of data

reception, a reception error interrupt request (INTSR6/INTSRE6) is generated.

Which error has occurred during reception can be identified by reading the contents of ASIS6 in the reception

error interrupt servicing (INTSR6/INTSRE6) (see Figure 11-6).

The contents of ASIS6 are reset to 0 when ASIS6 is read.

Table 11-3. Cause of Reception Error

Reception Error

Parity error

Cause

The parity specified for transmission does not match the parity of the

receive data.

Framing error

Overrun error

Stop bit is not detected.

Reception of the next data is completed before data is read from

receive buffer register 6 (RXB6).

The error interrupt can be separated into reception completion interrupt (INTSR6) and error interrupt

(INTSRE6) by clearing bit 0 (ISRM6) of asynchronous serial interface operation mode register 6 (ASIM6) to 0.

Figure 11-20. Reception Error Interrupt

1. If ISRM6 is cleared to 0 (reception completion interrupt (INTSR6) and error interrupt (INTSRE6) are

separated)

(a) No error during reception

(b) Error during reception

INTSR6

INTSRE6

2. If ISRM6 is set to 1 (error interrupt is included in INTSR6)

(a) No error during reception

(b) Error during reception

INTSR6

INTSRE6

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(g) Noise filter of receive data

The RxD6 signal is sampled with the base clock output by the prescaler block.

If two sampled values are the same, the output of the match detector changes, and the data is sampled as

input data.

Because the circuit is configured as shown in Figure 11-21, the internal processing of the reception operation

is delayed by two clocks from the external signal status.

Figure 11-21. Noise Filter Circuit

Base clock

Internal signal A

R

X

D6/P14/

Internal signal B

In

Q

In

Q

<INTP0>

LD_EN

Match detector

(h) SBF transmission

When the device is used in LIN communication operation, the SBF (Synchronous Break Field) transmission

control function is used for transmission. For the transmission operation of LIN, see Figure 11-1 LIN

Transmission Operation.

SBF transmission is used to transmit an SBF length that is a low-level width of 13 bits or more by adjusting

the baud rate value of the ordinary UART transmission function.

[Setting method]

Transmit 00H by setting the number of character bits of the data to 8 bits and the parity bit to 0 parity or even

parity. This enables a low-level transmission of a data frame consisting of 10 bits (1 bit (start bit) + 8 bits

(character bits) + 1 bit (parity bit)).

Adjust the baud rate value to adjust this 10-bit low level to the targeted SBF length.

Example If LIN is to be transmitted under the following conditions

• Base clock of UART6 = 5 MHz (set by clock selection register 6 (CKSR6))

• Target baud rate value = 19200 bps

To realize the above baud rate value, the length of a 13-bit SBF is as follows if the baud rate generator

control register 6 (BRGC6) is set to 130.

• 13-bit SBF length = 0.2 µs × 130 × 2 × 13 = 676 µs

To realize a 13-bit SBF length in 10 bits, set a value 1.3 times the targeted baud rate to BRGC6. In this

example, set 169 to BRGC6. The transmission length of a 10-bit low level in this case is as follows, and

matches the 13-bit SBF length.

• 10-bit low-level transmission length = 0.2 µs × 169 × 2 × 10 = 676 µs

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If the number of bits set by BRGC6 runs short, adjust the number of bits by setting the base clock of

UART6.

Figure 11-22. Example of Setting Procedure of SBF Transmission (Flowchart)

Start

Read BRGC6 register and save current

set value of BRGC6 register to general-

purpose register.

Clear TXE6 and RXE6 bits of ASIM6

register to 0 (to disable transmission/

reception).

Clear TXE6 and RXE6 bits of ASIM6

register to 0.

Set value to BRGC6 register to realize

desired SBF length.

Set character length of data to 8 bits

and parity to 0 or even using ASIM6

register.

Rewrite saved BRGC6 value to BRGC6

register.

Set TXE6 bit of ASIM6 register to 1 to

enable transmission.

Re-set PS61 bit, PS60 bit, and CL6 bit

of ASIM6 register to desired value.

Set TXE6 bit of ASIM6 register to 1 to

enable transmission.

Set TXB6 register to "00H" and start

transmission.

End

No

INTST6 occurred?

Yes

Figure 11-23. SBF Transmission

1

2

3

4

5

6

7

8

9

10

11

12

13 Stop

TXD6

INTST6

Remark T^XD6:

TXD6 pin (output)

INTST6: Transmission completion interrupt request

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CHAPTER 11 SERIAL INTERFACE UART6

(i) SBF reception

When the device is used in LIN communication operation, the SBF (Synchronous Break Field) reception

control function is used for reception. For the reception operation of LIN, refer to Figure 11-2 LIN Reception

Operation.

Reception is enabled when bit 7 (POWER6) of asynchronous serial interface operation mode register 6

(ASIM6) is set to 1 and then bit 5 (RXE6) of ASIM6 is set to 1. SBF reception is enabled when bit 6 (SBRT6)

of asynchronous serial interface control register 6 (ASICL6) is set to 1. In the SBF reception enabled status,

the R^XD6 pin is sampled and the start bit is detected in the same manner as the normal reception enable

status.

When the start bit has been detected, reception is started, and serial data is sequentially stored in receive

shift register 6 (RXS6) at the set baud rate. When the stop bit is received and if the width of SBF is 11 bits or

more, a reception completion interrupt request (INTSR6) is generated as normal processing. At this time, the

SBRF6 and SBRT6 bits are automatically cleared, and SBF reception ends. Detection of errors, such as

OVE6, PE6, and FE6 (bits 0 to 2 of asynchronous serial interface reception error status register 6 (ASIS6)) is

suppressed, and error detection processing of UART communication is not performed. In addition, data

transfer between receive shift register 6 (RXS6) and receive buffer register 6 (RXB6) is not performed, and

the reset value of FFH is retained. If the width of SBF is 10 bits or less, an interrupt does not occur as error

processing after the stop bit has been received, and the SBF reception mode is restored. In this case, the

SBRF6 and SBRT6 bits are not cleared.

Figure 11-24. SBF Reception

1. Normal SBF reception (stop bit is detected with a width of more than 10.5 bits)

1

2

3

4

5

6

7

8

9

10

11

RXD6

SBRT6

/SBRF6

INTSR6

2. SBF reception error (stop bit is detected with a width of 10.5 bits or less)

1

2

3

4

5

6

7

8

9

10

RXD6

SBRT6

/SBRF6

INTSR6

“0”

Remark RXD6:

RXD6 pin (input)

SBRT6: Bit 6 of asynchronous serial interface control register 6 (ASICL6)

SBRF6: Bit 7 of ASICL6

INTSR6: Reception completion interrupt request

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CHAPTER 11 SERIAL INTERFACE UART6

11.4.3 Dedicated baud rate generator

The dedicated baud rate generator consists of a source clock selector and an 8-bit programmable counter, and

generates a serial clock for transmission/reception of UART6.

Separate 8-bit counters are provided for transmission and reception.

(1) Configuration of baud rate generator

•

Base clock

The clock selected by bits 3 to 0 (TPS63 to TPS60) of clock selection register 6 (CKSR6) is supplied to

each module when bit 7 (POWER6) of the asynchronous serial interface operation mode register 6 (ASIM6)

is 1. This clock is called the base clock and its frequency is called f^XCLK6. The base clock is fixed to the low

level when POWER6 = 0.

Transmission counter

This counter stops, cleared to 0, when bit 7 (POWER6) or bit 6 (TXE6) of asynchronous serial interface

operation mode register 6 (ASIM6) is 0.

It starts counting when POWER6 = 1 and TXE6 = 1.

The counter is cleared to 0 when the first data transmitted is written to transmit buffer register 6 (TXB6).

If data are continuously transmitted, the counter is cleared to 0 again when one frame of data has been

completely transmitted. If there is no data to be transmitted next, the counter is not cleared to 0 and continues

counting until POWER6 or TXE6 is cleared to 0.

•

Reception counter

This counter stops operation, cleared to 0, when bit 7 (POWER6) or bit 5 (RXE6) of asynchronous serial

interface operation mode register 6 (ASIM6) is 0.

It starts counting when the start bit has been detected.

The counter stops operation after one frame has been received, until the next start bit is detected.

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CHAPTER 11 SERIAL INTERFACE UART6

Figure 11-25. Configuration of Baud Rate Generator

POWER6

f

X

Baud rate generator

f

X

/2

f

X

/2²

POWER6, TXE6 (or RXE6)

/2³

/2⁴

/2⁵

/2⁶

/2⁷

/2⁸

/2⁹

Selector

8-bit counter

f

XCLK6

fX

/2¹⁰

8-bit timer

50 output

Match detector

Baud rate

1/2

CKSR6: TPS63 to TPS60

BRGC6: MDL67 to MDL60

Remark POWER6: Bit 7 of asynchronous serial interface operation mode register 6 (ASIM6)

TXE6:

Bit 6 of ASIM6

RXE6:

Bit 5 of ASIM6

CKSR6:

BRGC6:

Clock selection register 6

Baud rate generator control register 6

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CHAPTER 11 SERIAL INTERFACE UART6

(2) Generation of serial clock

A serial clock can be generated by using clock selection register 6 (CKSR6) and baud rate generator control

register 6 (BRGC6).

Select the clock to be input to the 8-bit counter by using bits 3 to 0 (TPS63 to TPS60) of CKSR6.

Bits 7 to 0 (MDL67 to MDL60) of BRGC6 can be used to select the division value of the 8-bit counter.

(a) Baud rate

The baud rate can be calculated by the following expression.

f^XCLK6

• Baud rate =

[bps]

2 × k

f^XCLK6: Frequency of the base clock selected by TPS63 to TPS60 bits of CKSR6 register

k: Value set by MDL67 to MDL60 bits of BRGC6 register (k = 8, 9, 10, ..., 255)

(b) Error of baud rate

The baud rate error can be calculated by the following expression.

Actual baud rate (baud rate with error)

• Error (%) =

− 1 × 100 [%]

Desired baud rate (correct baud rate)

Cautions 1. Keep the baud rate error during transmission to within the permissible error range at

the reception destination.

2. Make sure that the baud rate error during reception satisfies the range shown in (4)

Permissible baud rate range during reception.

Example: Frequency of base clock = 10 MHz = 10,000,000 Hz

Set value of MDL67 to MDL60 bits of BRGC6 register = 00100001B (k = 33)

Target baud rate = 153600 bps

Baud rate = 10 M/(2 × 33)

= 10000000/(2 × 33) = 151515 [bps]

Error = (151515/153600 − 1) × 100

= −1.357 [%]

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CHAPTER 11 SERIAL INTERFACE UART6

(3) Example of setting baud rate

Table 11-4. Set Data of Baud Rate Generator

Baud Rate

[bps]

fX = 10.0 MHz

fX = 8.38 MHz

fX = 4.19 MHz

TPS63 to

TPS60

k

Calculated ERR[%] TPS63 to

k

Calculated ERR[%] TPS63 to

k

Calculated ERR[%]

Value

TPS60

6H

5H

4H

3H

2H

1H

0H

Value

TPS60

5H

4H

3H

2H

1H

0H

Value

600

1200

6H

5H

4H

3H

2H

1H

0H

130

120

130

80

601

1202

0.16

0.00

0.16

0.94

−1.36

109

101

109

134

109

55

601

0.11

0.28

0.11

0.06

0.11

−0.80

1.03

109

101

109

67

601

0.11

−0.28

0.11

0.06

−0.80

1.03

−2.58

1.03

1201

2400

2404

2403

4800

4808

4805

9600

9615

9610

10400

19200

31250

38400

76800

115200

153600

230400

10417

19231

31250

38462

76923

116279

151515

227272

10371

19220

31268

38440

76182

116389

155185

232778

10475

19220

31268

38090

77593

116389

149643

232778

130

65

55

27

43

36

18

33

27

14

22

18

9

Remark TPS63 to TPS60: Bits 3 to 0 of clock selection register 6 (CKSR6) (setting of base clock (f^XCLK6))

k:

Value set by MDL67 to MDL60 bits of baud rate generator control register 6

(BRGC6) (k = 8, 9, 10, ..., 255)

f^X:

High-speed system clock oscillation frequency

Baud rate error

ERR:

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(4) Permissible baud rate range during reception

The permissible error from the baud rate at the transmission destination during reception is shown below.

Caution Make sure that the baud rate error during reception is within the permissible error range, by

using the calculation expression shown below.

Figure 11-26. Permissible Baud Rate Range During Reception

Latch timing

Data frame length

Start bit

Bit 0

FL

Bit 1

Bit 7

Parity bit

Stop bit

of UART6

1 data frame (11 × FL)

Minimum permissible

data frame length

Bit 0

Bit 1

Bit 7

Parity bit

Stop bit

FLmin

Maximum permissible

data frame length

Bit 0

Bit 1

Bit 7

Parity bit

Stop bit

FLmax

As shown in Figure 11-26, the latch timing of the receive data is determined by the counter set by baud rate

generator control register 6 (BRGC6) after the start bit has been detected. If the last data (stop bit) meets this

latch timing, the data can be correctly received.

Assuming that 11-bit data is received, the theoretical values can be calculated as follows.

1

FL = (Brate)⁻

Brate: Baud rate of UART6

k:

Set value of BRGC6

1-bit data length

FL:

Margin of latch timing: 2 clocks

21k + 2

2k

k − 2

2k

Minimum permissible data frame length: FLmin = 11 × FL −

× FL =

FL

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Therefore, the maximum receivable baud rate at the transmission destination is as follows.

22k

1

BRmax = (FLmin/11)⁻

=

Brate

21k + 2

Similarly, the maximum permissible data frame length can be calculated as follows.

10

11

k + 2

21k − 2

2 × k

× FLmax = 11 × FL −

× FL =

FL

2 × k

21k − 2

20k

FLmax =

FL × 11

Therefore, the minimum receivable baud rate at the transmission destination is as follows.

20k

1

BRmin = (FLmax/11)⁻

=

Brate

21k − 2

The permissible baud rate error between UART6 and the transmission destination can be calculated from the

above minimum and maximum baud rate expressions, as follows.

Table 11-5. Maximum/Minimum Permissible Baud Rate Error

Division Ratio (k)

Maximum Permissible Baud Rate Error

Minimum Permissible Baud Rate Error

8

+3.53%

+4.26%

+4.56%

+4.66%

+4.72%

−3.61%

−4.31%

−4.58%

−4.67%

−4.73%

20

50

100

255

Remarks 1. The permissible error of reception depends on the number of bits in one frame, input clock

frequency, and division ratio (k). The higher the input clock frequency and the higher the division

ratio (k), the higher the permissible error.

2. k: Set value of BRGC6

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(5) Data frame length during continuous transmission

When data is continuously transmitted, the data frame length from a stop bit to the next start bit is extended by

two clocks of base clock from the normal value. However, the result of communication is not affected because

the timing is initialized on the reception side when the start bit is detected.

Figure 11-27. Data Frame Length During Continuous Transmission

Start bit of

1 data frame

second byte

Bit 0

FL

Bit 1

FL

Bit 7

FL

Bit 0

FL

Start bit

FL

Start bit

FL

Parity bit

FL

Stop bit

FLstp

Where the 1-bit data length is FL, the stop bit length is FLstp, and base clock frequency is fXCLK6, the following

expression is satisfied.

FLstp = FL + 2/f^XCLK6

Therefore, the data frame length during continuous transmission is:

Data frame length = 11 × FL + 2/f^XCLK6

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CHAPTER 12 SERIAL INTERFACE CSI10

12.1 Functions of Serial Interface CSI10

Serial interface CSI10 has the following two modes.

•

Operation stop mode

3-wire serial I/O mode

(1) Operation stop mode

This mode is used when serial communication is not performed and can enable a reduction in the power

consumption.

For details, see 12.4.1 Operation stop mode.

(2) 3-wire serial I/O mode (MSB/LSB-first selectable)

This mode is used to communicate 8-bit data using three lines: a serial clock line (SCK10) and two serial data

lines (SI10 and SO10).

The processing time of data communication can be shortened in the 3-wire serial I/O mode because transmission

and reception can be simultaneously executed.

In addition, whether 8-bit data is communicated with the MSB or LSB first can be specified, so this interface can

be connected to any device.

The 3-wire serial I/O mode can be used for connecting peripheral ICs and display controllers with a clocked serial

interface.

For details, see 12.4.2 3-wire serial I/O mode.

12.2 Configuration of Serial Interface CSI10

Serial interface CSI10 includes the following hardware.

Table 12-1. Configuration of Serial Interface CSI10

Item

Configuration

Registers

Transmit buffer register 10 (SOTB10)

Serial I/O shift register 10 (SIO10)

Control registers

Serial operation mode register 10 (CSIM10)

Serial clock selection register 10 (CSIC10)

Port mode register 1 (PM1)

Port register 1 (P1)

244

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CHAPTER 12 SERIAL INTERFACE CSI10

Figure 12-1. Block Diagram of Serial Interface CSI10

Internal bus

(a)

8

Serial I/O shift

register 10 (SIO10)

Transmit buffer

register 10 (SOTB10)

Output

selector

SI10/P11/INTP3

SO10/P12/

TOH1/(INTP3)

Output latch

(P12)

PM12

Transmit data

controller

Output latch

Transmit controller

f

X

/2

f

/2²

/2³

/2⁴

/2⁵

/2⁶

/2⁷

Clock start/stop controller &

clock phase controller

INTCSI10

SCK10/P10/

(INTP1)

(1) Transmit buffer register 10 (SOTB10)

This register sets the transmit data.

Transmission/reception is started by writing data to SOTB10 when bit 7 (CSIE10) and bit 6 (TRMD10) of serial

operation mode register 10 (CSIM10) are 1.

The data written to SOTB10 is converted from parallel data into serial data by serial I/O shift register 10, and

output to the serial output pin (SO10).

SOTB10 can be written or read by an 8-bit memory manipulation instruction.

RESET input makes this register undefined.

Caution Do not access SOTB10 when CSOT10 = 1 (during serial communication).

(2) Serial I/O shift register 10 (SIO10)

This is an 8-bit register that converts data from parallel data into serial data or vice versa.

This register can be read by an 8-bit memory manipulation instruction.

Reception is started by reading data from SIO10 when bit 6 (TRMD10) of serial operation mode register 10

(CSIM10) is 0.

During reception, the data is read from the serial input pin (SI10) to SIO10.

RESET input clears this register to 00H.

Caution Do not access SIO10 when CSOT10 = 1 (during serial communication).

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CHAPTER 12 SERIAL INTERFACE CSI10

12.3 Registers Controlling Serial Interface CSI10

Serial interface CSI10 is controlled by the following four registers.

•

Serial operation mode register 10 (CSIM10)

Serial clock selection register 10 (CSIC10)

Port mode register 1 (PM1)

Port register 1 (P1)

(1) Serial operation mode register 10 (CSIM10)

This register is used to select the operation mode and enable or disable operation.

This register can be set by a 1-bit or 8-bit memory manipulation instruction.

RESET input sets this register to 00H.

Figure 12-2. Format of Serial Operation Mode Register 10 (CSIM10)

Address: FF80H After reset: 00H R/W^{Note 1}

Symbol

CSIM10

<7>

6

5

0

4

3

0

2

0

1

0

CSIE10

TRMD10

DIR10

CSOT10

CSIE10

Operation control in 3-wire serial I/O mode

0

1

Disables operation^{Note 2}and asynchronously resets the internal circuit^{Note 3}

Enables operation

.

TRMD10^{Note 4}

Transmit/receive mode control

Receive mode (transmission disabled)

Transmit/receive mode

0^{Note 5}

1

DIR10^{Note 6}

First bit specification

0

1

MSB

LSB

CSOT10

Operation mode flag

Communication is stopped.

0

1

Communication is in progress.

Notes 1. Bit 0 is a read-only bit.

<R>

2. When using P10/SCK10/(INTP1), and P12/SO10/TOH1/(INTP3) as a general-purpose port, set

CSIM10 in the default status (00H).

3. Bit 0 (CSOT10) of CSIM10 and serial I/O shift register 10 (SIO10) are reset.

4. Do not rewrite TRMD10 when CSOT10 = 1 (during serial communication).

5. The SO10 output is fixed to the low level when TRMD10 is 0. Reception is started when data is read

from SIO10.

6. Do not rewrite DIR10 when CSOT10 = 1 (during serial communication).

Caution Be sure to clear bit 5 to 0.

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CHAPTER 12 SERIAL INTERFACE CSI10

(2) Serial clock selection register 10 (CSIC10)

This register is used to select the phase of the data clock and set the count clock.

This register can be set by a 1-bit or 8-bit memory manipulation instruction.

RESET input clears this register to 00H.

Figure 12-3. Format of Serial Clock Selection Register 10 (CSIC10)

Address: FF81H After reset: 00H R/W

Symbol

CSIC10

7

0

6

0

5

0

4

3

2

1

0

CKP10

DAP10

CKS102

CKS101

CKS100

CKP10

0

DAP10

0

Specification of data transmission/reception timing

SCK10

Type

1

SO10

D7 D6 D5 D4 D3 D2 D1 D0

SI10 input timing

0

1

0

1

2

3

4

SCK10

SO10

D7 D6 D5 D4 D3 D2 D1 D0

SI10 input timing

SCK10

SO10

D7 D6 D5 D4 D3 D2 D1 D0

SI10 input timing

SCK10

SO10

D7 D6 D5 D4 D3 D2 D1 D0

SI10 input timing

CKS102

CKS101

CKS100

CSI10 serial clock selection

Mode

0

1

0

1

0

1

0

1

0

1

0

1

0

1

fX/2 (5 MHz)

Master mode

Slave mode

fX/2²(2.5 MHz)

fX/2³(1.25 MHz)

fX/2⁴(625 kHz)

fX/2⁵(312.5 kHz)

fX/2⁶(156.25 kHz)

fX/2⁷(78.13 kHz)

External clock input to SCK10

Cautions 1. When the internal oscillation clock is selected as the clock supplied to the CPU, the clock of

the internal oscillator is divided and supplied as the serial clock. At this time, the operation

of serial interface CSI10 is not guaranteed.

2. Do not write to CSIC10 while CSIE10 = 1 (operation enabled).

<R>

3. When using P10/SCK10/(INTP1) and P12/SO10/TOH1/(INTP3) as general-purpose port, set

CSIC10 in the default status (00H).

4. The phase type of the data clock is type 1 after reset.

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CHAPTER 12 SERIAL INTERFACE CSI10

Remarks 1. Figures in parentheses are for operation with fx = 10 MHz.

2. f^X: High-speed system clock oscillation frequency

(3) Port mode register 1 (PM1)

This register sets port 1 input/output in 1-bit units.

When using P10/SCK10/(INTP1) as the clock output pins of the serial interface, clear PM10 to 0 and set the

output latch of P10 to 1.

When using P12/SO10/TOH1/(INTP3) as the data output pins, clear PM12 and the output latch of P12 to 0.

When using P10/SCK10/(INTP1) as the clock input pins of the serial interface, and P11/SI10/INTP3 as the data

input pins, set PM10 and PM11 to 1. At this time, the output latches of P10 and P11 may be 0 or 1.

PM1 can be set by a 1-bit or 8-bit memory manipulation instruction.

RESET input sets this register to FFH.

Figure 12-4. Format of Port Mode Register 1 (PM1)

Address: FF21H After reset: FFH R/W

Symbol

PM1

7

1

6

1

5

4

3

2

1

0

PM15

PM14

PM13

PM12

PM11

PM10

PM1n

P1n pin I/O mode selection (n = 0 to 5)

0

1

Output mode (output buffer on)

Input mode (output buffer off)

12.4 Operation of Serial Interface CSI10

Serial interface CSI10 can be used in the following two modes.

•

Operation stop mode

3-wire serial I/O mode

12.4.1 Operation stop mode

Serial communication is not executed in this mode. Therefore, the power consumption can be reduced. In

addition, the P10/SCK10/(INTP1), P11/SI10/INTP3, and P12/SO10/TOH1/(INTP3) pins can be used as ordinary I/O

port pins in this mode.

(1) Register used

The operation stop mode is set by serial operation mode register 10 (CSIM10).

To set the operation stop mode, clear bit 7 (CSIE10) of CSIM10 to 0.

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CHAPTER 12 SERIAL INTERFACE CSI10

(a) Serial operation mode register 10 (CSIM10)

CSIM10 can be set by a 1-bit or 8-bit memory manipulation instruction.

RESET input clears CSIM10 to 00H.

Address: FF80H After reset: 00H R/W

Symbol

CSIM10

<7>

6

5

0

4

3

0

2

0

1

0

CSIE10

TRMD10

DIR10

CSOT10

CSIE10

0

Operation control in 3-wire serial I/O mode

Disables operation^{Note 1}and asynchronously resets the internal circuit^{Note 2}

.

<R>

Notes 1. When using P10/SCK10/(INTP1), and P12/SO10/TOH1/(INTP3) as a general-purpose port, set

CSIM10 in the default status (00H).

2. Bit 0 (CSOT10) of CSIM10 and serial I/O shift register 10 (SIO10) are reset.

12.4.2 3-wire serial I/O mode

The 3-wire serial I/O mode can be used for connecting peripheral ICs and display controllers that have a clocked

serial interface.

In this mode, communication is executed by using three lines: the serial clock (SCK10), serial output (SO10), and

serial input (SI10) lines.

(1) Registers used

• Serial operation mode register 10 (CSIM10)

• Serial clock selection register 10 (CSIC10)

• Port mode register 1 (PM1)

• Port register 1 (P1)

The basic procedure of setting an operation in the 3-wire serial I/O mode is as follows.

<1> Set the CSIC10 register (see Figure 12-3).

<2> Set bits 0, 4, and 6 (CSOT10, DIR10, and TRMD10) of the CSIM10 register (see Figure 12-2).

<3> Set bit 7 (CSIE10) of the CSIM10 register to 1. → Transmission/reception is enabled.

<4> Write data to transmit buffer register 10 (SOTB10). → Data transmission/reception is started.

Read data from serial I/O shift register 10 (SIO10). → Data reception is started.

Caution Take relationship with the other party of communication when setting the port mode

register and port register.

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CHAPTER 12 SERIAL INTERFACE CSI10

The relationship between the register settings and pins is shown below.

Table 12-2. Relationship Between Register Settings and Pins

CSIE10

PM11

P11

PM12

P12

PM10

P10

CSI10

Pin Function

TRMD10

Operation

P11/SI10

/INTP3

P12/SO10 P10/SCK10

/TOH1

/(INTP1)

/(INTP3)

Note 1

0

1

×

0

×

Stop

P11

P12

P10

/INTP3

/TOH1

/(INTP3)

/(INTP1)^Note2

Note 1

1

×

1

×

Slave

reception^{Note 3}

SI10

P12

SCK10

(input)^{Note 3}

/TOH1

/(INTP3)

Note 1

1

×

0

1

×

Slave

P11

SO10

SCK10

transmission^{Note 3}

/INTP3

(input)^{Note 3}

1

×

Slave

SI10

SO10

SCK10

(input)^{Note 3}

transmission/

reception^{Note 3}

Note 1

1

0

×

0

1

Master

SI10

P12

SCK10

(output)

reception

/TOH1

/(INTP3)

Note 1

1

×

0

1

Master

P11

SO10

SCK10

(output)

transmission

/INTP3

1

×

Master

transmission/

reception

SI10

SO10

SCK10

(output)

Notes 1. Can be set as port function.

2. To use P10/SCK10/(INTP1) as port pins, clear CKP10 to 0.

3. To use the slave mode, set CKS102, CKS101, and CKS100 to 1, 1, 1.

Remark ×:

don’t care

CSIE10:

TRMD10:

CKP10:

Bit 7 of serial operation mode register 10 (CSIM10)

Bit 6 of CSIM10

Bit 4 of serial clock selection register 10 (CSIC10)

CKS102, CKS101, CKS100: Bits 2 to 0 of CSIC10

PM1×:

P1×:

Port mode register

Port output latch

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CHAPTER 12 SERIAL INTERFACE CSI10

(2) Communication operation

In the 3-wire serial I/O mode, data is transmitted or received in 8-bit units. Each bit of the data is transmitted or

received in synchronization with the serial clock.

Data can be transmitted or received if bit 6 (TRMD10) of serial operation mode register 10 (CSIM10) is 1.

Transmission/reception is started when a value is written to transmit buffer register 10 (SOTB10). In addition,

data can be received when bit 6 (TRMD10) of serial operation mode register 10 (CSIM10) is 0.

Reception is started when data is read from serial I/O shift register 10 (SIO10).

After communication has been started, bit 0 (CSOT10) of CSIM10 is set to 1. When communication of 8-bit data

has been completed, a communication completion interrupt request flag (CSIIF10) is set, and CSOT10 is cleared

to 0. Then the next communication is enabled.

Caution Do not access the control register and data register when CSOT10 = 1 (during serial

communication).

Figure 12-5. Timing in 3-Wire Serial I/O Mode (1/2)

(1) Transmission/reception timing (Type 1; TRMD10 = 1, DIR10 = 0, CKP10 = 0, DAP10 = 0)

SCK10

Read/write trigger

SOTB10

SIO10

55H (communication data)

ABH

56H

ADH

5AH

B5H

6AH

D5H AAH

CSOT10

INTCSI10

CSIIF10

SI10 (receive AAH)

SO10

55H is written to SOTB10.

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CHAPTER 12 SERIAL INTERFACE CSI10

Figure 12-5. Timing in 3-Wire Serial I/O Mode (2/2)

(2) Transmission/reception timing (Type 2; TRMD10 = 1, DIR10 = 0, CKP10 = 0, DAP10 = 1)

SCK10

Read/write trigger

SOTB10

SIO10

55H (communication data)

ABH

56H

ADH

5AH

B5H

6AH

D5H

AAH

CSOT10

INTCSI10

CSIIF10

SI10 (input AAH)

SO10

55H is written to SOTB10.

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CHAPTER 12 SERIAL INTERFACE CSI10

Figure 12-6. Timing of Clock/Data Phase

(a) Type 1; CKP10 = 0, DAP10 = 0

SCK10

SI10 capture

SO10

Writing to SOTB10 or

reading from SIO10

CSIIF10

D7

D6

D5

D4

D3

D2

D1

D0

CSOT10

(b) Type 2; CKP10 = 0, DAP10 = 1

SCK10

<R>

SI10 capture

SO10

Writing to SOTB10 or

reading from SIO10

CSIIF10

D7

D6

D5

D4

D3

D2

D1

D0

CSOT10

(c) Type 3; CKP10 = 1, DAP10 = 0

SCK10

SI10 capture

SO10

Writing to SOTB10 or

reading from SIO10

CSIIF10

D7

D6

D5

D4

D3

D2

D1

D0

CSOT10

(d) Type 4; CKP10 = 1, DAP10 = 1

SCK10

<R>

SI10 capture

SO10

Writing to SOTB10 or

reading from SIO10

CSIIF10

D7

D6

D5

D4

D3

D2

D1

D0

CSOT10

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CHAPTER 12 SERIAL INTERFACE CSI10

(3) Timing of output to SO10 pin (first bit)

When communication is started, the value of transmit buffer register 10 (SOTB10) is output from the SO10 pin.

The output operation of the first bit at this time is described below.

Figure 12-7. Output Operation of First Bit

(1) When CKP10 = 0, DAP10 = 0 (or CKP10 = 1, DAP10 = 0)

SCK10

Writing to SOTB10 or

reading from SIO10

SOTB10

SIO10

Output latch

First bit

2nd bit

SO10

The first bit is directly latched by the SOTB10 register to the output latch at the falling (or rising) edge of the

SCK10, and output from the SO10 pin via an output selector. Then, the value of the SOTB10 register is

transferred to the SIO10 register at the next rising (or falling) edge of SCK10, and shifted one bit. At the same

time, the first bit of the receive data is stored in the SIO10 register via the SI10 pin.

The second and subsequent bits are latched by the SIO10 register to the output latch at the next falling (or rising)

edge of SCK10, and the data is output from the SO10 pin.

(2) When CKP10 = 0, DAP10 = 1 (or CKP10 = 1, DAP10 = 1)

SCK10

Writing to SOTB10 or

reading from SIO10

SOTB10

SIO10

Output latch

First bit

2nd bit

3rd bit

SO10

The first bit is directly latched by the SOTB10 register at the falling edge of the write signal of the SOTB10

register or the read signal of the SIO10 register, and output from the SO10 pin via an output selector. Then, the

value of the SOTB10 register is transferred to the SIO10 register at the next falling (or rising) edge of SCK10, and

shifted one bit. At the same time, the first bit of the receive data is stored in the SIO10 register via the SI10 pin.

The second and subsequent bits are latched by the SIO10 register to the output latch at the next rising (or falling)

edge of SCK10, and the data is output from the SO10 pin.

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CHAPTER 12 SERIAL INTERFACE CSI10

(4) Output value of SO10 pin (last bit)

After communication has been completed, the SO10 pin holds the output value of the last bit.

Figure 12-8. Output Value of SO10 Pin (Last Bit)

(1) Type 1; when CKP10 = 0 and DAP10 = 0 (or CKP10 = 1, DAP10 = 0)

SCK10

Writing to SOTB10 or

reading from SIO10

( ← Next request is issued.)

SOTB10

SIO10

Output latch

Last bit

SO10

(2) Type 2; when CKP10 = 0 and DAP10 = 1 (or CKP10 = 1, DAP10 = 1)

SCK10

Writing to SOTB10 or

reading from SIO10

( ← Next request is issued.)

SOTB10

SIO10

Output latch

SO10

Last bit

(5) SO10 output (see (a) in Figure 12-1)

The status of the SO10 output is as follows if bit 7 (CSIE10) of serial operation mode register 10 (CSIM10) is

cleared to 0.

Table 12-3. SO10 Output Status

TRMD10

TRMD10 = 0^{Note 2}

TRMD10 = 1

DAP10

DIR10

SO10 Output^{Note 1}

Outputs low level^{Note 2}

−

.

DAP10 = 0

Value of SO10 latch

(low-level output)

DAP10 = 1

DIR10 = 0

DIR10 = 1

Value of bit 7 of SOTB10

Value of bit 0 of SOTB10

Notes 1. The actual output of the SO10/P12/TOH1/(INTP3) pin is determined by PM12 and P12 as well

as SO10 output.

2. Status after reset

Caution If a value is written to TRMD10, DAP10, and DIR10, the output value of SO10 changes.

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CHAPTER 13 MANCHESTER CODE GENERATOR

13.1 Functions of Manchester Code Generator

The following three types of modes are available for the Manchester code generator.

(1) Operation stop mode

This mode is used when output by the Manchester code generator/bit sequential buffer is not performed. This

mode reduces the power consumption.

For details, refer to 13.4.1 Operation stop mode.

(2) Manchester code generator mode

This mode is used to transmit Manchester code from the MCGO pin.

The transfer bit length can be set and transfers of various bit lengths are enabled. Also, the output level of the

data transfer and LSB- or MSB-first can be set for 8-bit transfer data.

(3) Bit sequential buffer mode

This mode is used to transmit bit sequential data from the MCGO pin.

The transfer bit length can be set and transfers of various bit lengths are enabled. Also, the output level of the

data transfer and LSB- or MSB-first can be set for 8-bit transfer data.

13.2 Configuration of Manchester Code Generator

The Manchester code generator includes the following hardware.

Table 13-1. Configuration of Manchester Code Generator

Item

Configuration

Registers

MCG transmit buffer register (MC0TX)

MCG transmit bit count specification register (MC0BIT)

Control registers

MCG control register 0 (MC0CTL0)

MCG control register 1 (MC0CTL1)

MCG control register 2 (MC0CTL2)

MCG status register (MC0STR)

Port mode registers 0, 1 (PM0, PM1)

Port registers 0, 1 (P0, P1)

256

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CHAPTER 13 MANCHESTER CODE GENERATOR

Figure 13-1. Block Diagram of Manchester Code Generator

Internal bus

MC0CTL1 MC0CTL2

MC0BIT

MC0TX

MC0STR MC0CTL0

Control

INTMCG

3-bit

counter

P00 PM00

f

X

to f

/2⁵

X

P00/TI000/INTP0/

MCGO

BRG

Selector

Output

control

Selector

8-bit shift register

P13/TxD6/INTP1/

(TOH1)/(MCGO)

P13 PM13

PSEL: MCGSL

Remark BRG:

Baud rate generator

f^X:

High-speed system clock oscillation frequency

MCG transmit bit count specification register

MC0BIT:

MC0CTL2 to MC0CTL0: MCG control registers 2 to 0

MC0STR:

MC0TX:

MCGSL:

PSEL:

MCG status register

MCG transmit buffer register

Bit 0 of PSEL register

Alternate-function pin switch register

Figure 13-2. Block Diagram of Baud Rate Generator

fX

to fX

/2⁵

Selector

5-bit counter

1/2

Baud rate

MC0CTL1:

MC0CKS2-

MC0CKS0

MC0CTL2:

MC0BRS4-

MC0BRS0

Remark f^X:

High-speed system clock oscillation frequency

MC0CTL2, MC0CTL 1: MCG control registers 2, 1

MC0CKS2 to MC0CKS0: Bits 2 to 0 of MC0CTL1 register

MC0BRS4 to MC0BRS0: Bits 4 to 0 of MC0CTL2 register

(1) MCG transmit buffer register (MC0TX)

This register is used to set the transmit data. A transmit operation starts when data is written to MC0TX while bit

7 (MC0PWR) of MCG control register 0 (MC0CTL0) is 1.

The data written to MC0TX is converted into serial data by the 8-bit shift register, and output to the MCGO pin.

Manchester code or bit sequential data can be set as the output code using bit 1 (MC0OSL) of MCG control

register 0 (MC0CTL0).

This register can be set by an 8-bit memory manipulation instruction.

RESET input sets this register to FFH.

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(2) MCG transmit bit count specification register (MC0BIT)

This register is used to set the number of transmit bits.

Set the transmit bit count to this register before setting the transmit data to MC0TX.

In continuous transmission, the number of transmit bits to be transmitted next needs to be written after the

occurrence of a transmission start interrupt (INTMCG). However, if the next transmit count is the same number

as the previous transmit count, this register does not need to be written.

This register can be set by an 8-bit memory manipulation instruction.

RESET input sets this register to 07H.

Figure 13-3. Format of MCG Transmit Bit Count Specification Register (MC0BIT)

Address: FF65H After reset: 07H R/W

Symbol

MC0BIT

7

0

6

0

5

0

4

0

3

0

<2>

<1>

<0>

MC0BIT2

MC0BIT1

MC0BIT0

MC0BIT2

MC0BIT1

MC0BIT0

Transmit bit count setting

0

1

0

1

0

1

0

1

0

1

0

1

0

1

1 bit

2 bits

3 bits

4 bits

5 bits

6 bits

7 bits

8 bits

<R>

Remark When the number of transmit bits is set as 7 bits or smaller, the lower bits are always

transmitted regardless of MSB/LSB settings as the transmission start bit.

ex. When the number of transmit bits is set as 3 bits, and D7 to D0 are written to MCG transmit

buffer register (MC0TX)

7

6

5

4

3

2

1

0

MC0TX

D7

D6

D5

D4

D3

D2

D1

D0

Transmit data

→

Start bit: LSB

Transmission order

D0

D2

D1

D2

D0

Start bit: MSB

Transmission order

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13.3 Registers Controlling Manchester Code Generator

The following six types of registers are used to control the Manchester code generator.

• MCG control register 0 (MC0CTL0)

• MCG control register 1 (MC0CTL1)

• MCG control register 2 (MC0CTL2)

• MCG status register (MC0STR)

• Port mode registers 0, 1 (PM0, PM1)

• Port registers 0, 1 (P0, P1)

(1) MCG control register 0 (MC0CTL0)

This register is used to set the operation mode and to enable/disable the operation.

This register can be set by a 1-bit or 8-bit memory manipulation instruction.

RESET input sets this register to 10H.

Figure 13-4. Format of MCG Control Register 0 (MC0CTL0)

Address: FF60H After reset: 10H R/W

Symbol

<7>

6

0

5

0

<4>

3

0

2

0

<1>

<0>

MC0CTL0

MC0PWR

MC0DIR

MC0OSL

MC0OLV

MC0PWR

Operation control

First bit specification

Data format

0

1

Operation stopped

Operation enabled

MC0DIR

0

1

MSB

LSB

MC0OSL

0

1

Manchester code

Bit sequential data

MC0OLV

Output level when transmission suspended

0

1

Low level

High level

Caution Clear (0) the MC0PWR bit before rewriting the MC0DIR, MC0OSL, and MC0OLV bits (it is

possible to rewrite these bits by an 8-bit memory manipulation instruction at the same

time when the MC0PWR bit is set (1)).

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(2) MCG control register 1 (MC0CTL1)

This register is used to set the base clock of the Manchester code generator.

This register can be set by an 8-bit memory manipulation instruction.

RESET input clears this register to 00H.

Figure 13-5. Format of MCG Control Register 1 (MC0CTL1)

Address: FF61H After reset: 00H R/W

Symbol

7

0

6

0

5

0

4

0

3

0

2

1

0

MC0CTL1

MC0CKS2

MC0CKS1

MC0CKS0

MC0CKS2

MC0CKS1

MC0CKS0

Base clock (fXCLK) selection

0

1

0

1

0

1

0

1

0

1

0

1

0

1

fX (10 MHz)

fX/2 (5 MHz)

fX/2²(2.5 MHz)

fX/2³(1.25 MHz)

fX/2⁴(625 kHz)

f^X/2⁵(312.5 kHz)

Caution Clear bit 7 (MC0PWR) of the MC0CTL0 register to 0 before rewriting the MC0CKS2 to

MC0CKS0 bits.

Remarks 1. f^X: High-speed system clock oscillation frequency

2. Figures in parentheses are for operation with fX = 10 MHz.

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(3) MCG control register 2 (MC0CTL2)

This register is used to set the transmit baud rate.

This register can be set by an 8-bit memory manipulation instruction.

RESET input sets this register to 1FH.

Figure 13-6. Format of MCG Control Register 2 (MC0CTL2)

Address: FF62H After reset: 1FH R/W

Symbol

7

0

6

0

5

0

4

3

2

1

0

MC0CTL2

MC0BRS4

MC0BRS3

MC0BRS2

MC0BRS1

MC0BRS0

MC0BRS4

MC0BRS3

MC0BRS2

MC0BRS1

MC0BRS0

k

Output clock selection of 5-bit

counter

0

1

×

0

1

×

0

1

0

1

4

5

6

7

fXCLK/4

fXCLK/5

fXCLK/6

fXCLK/7

•

1

0

1

0

1

0

1

28

29

30

31

fXCLK/28

fXCLK/29

fXCLK/30

fXCLK/31

Cautions 1. Clear bit 7 (MC0PWR) of the MC0CTL0 register to 0 before rewriting the MC0BRS4 to

MC0BRS0 bits.

2. The value from further dividing the output clock of the 5-bit counter by 2 is the baud

rate value.

Remarks 1. f^XCLK: Frequency of the base clock selected by the MC0CKS2 to MC0CKS0 bits of the

MC0CTL1 register

2. k: Value set by the MC0BRS4 to MC0BRS0 bits (k = 4, 5, 6, 7, …., 31)

3. ×: Don’t care

(4) MCG status register (MC0STR)

This register is used to indicate the operation status of the Manchester code generator.

This register can be read by a 1-bit or 8-bit memory manipulation instruction. Writing to this register is not

possible.

RESET input or setting MC0PWR = 0 clears this register to 00H.

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Figure 13-7. Format of MCG Status Register (MC0STR)

Address: FF63H After reset: 00H

R

Symbol

<7>

6

0

5

0

4

0

3

0

2

0

1

0

MC0STR

MC0TSF

0

Data transmission status

• RESET input

• MC0PWR = 0

• If the next transfer data is not written to MC0TX when a transmission is completed

1

Transmission operation in progress

Caution This flag always indicates 1 during continuous transmission. Do not initialize a

transmission operation without confirming that this flag has been cleared.

13.4 Operation of Manchester Code Generator

The Manchester code generator has the three modes described below.

• Operation stop mode

• Manchester code generator mode

• Bit sequential buffer mode

13.4.1 Operation stop mode

Transmissions are not performed in the operation stop mode. Therefore, the power consumption can be reduced.

In addition, the P00/TI00/INTP0/MCGO and P13/TxD6/INTP1/(TOH1)/(MCGO) pins are used as an ordinary I/O port

in this mode.

(1) Register description

MCG control register 0 (MC0CTL0) is used to set the operation stop mode.

To set the operation stop mode, clear bit 7 (MC0PWR) of MC0CTL0 to 0.

(a) MCG control register 0 (MC0CTL0)

This register can be set by a 1-bit or 8-bit memory manipulation instruction.

RESET input sets this register to 10H.

Address: FF60H After reset: 10H R/W

Symbol

<7>

6

0

5

0

<4>

3

0

2

0

<1>

<0>

MC0CTL0

MC0PWR

MC0DIR

MC0OSL

MC0OLV

MC0PWR

Operation control

0

1

Operation stopped

Operation enabled

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13.4.2 Manchester code generator mode

This mode is used to transmit data in Manchester code format using the MCGO pin.

(1) Register description

MCG control register 0 (MC0CTL0), MCG control register 1 (MC0CTL1), and MCG control register 2 (MC0CTL2)

are used to set the Manchester code generator mode.

(a) MCG control register 0 (MC0CTL0)

This register can be set by a 1-bit or 8-bit memory manipulation instruction.

RESET input sets this register to 10H.

Address: FF60H After reset: 10H R/W

Symbol

<7>

6

0

5

0

<4>

3

0

2

0

<1>

<0>

MC0CTL0

MC0PWR

MC0DIR

MC0OSL

MC0OLV

MC0PWR

Operation control

First bit specification

Data format

0

1

Operation stopped

Operation enabled

MC0DIR

0

1

MSB

LSB

MC0OSL

0

1

Manchester code

Bit sequential data

MC0OLV

Output level when transmission suspended

0

1

Low level

High level

Caution Clear (0) the MC0PWR bit before rewriting the MC0DIR, MC0OSL, and MC0OLV bits (it is

possible to rewrite these bits by an 8-bit memory manipulation instruction at the same

time when the MC0PWR bit is set (1)).

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(b) MCG control register 1 (MC0CTL1)

This register is used to set the base clock of the Manchester code generator.

This register can be set by an 8-bit memory manipulation instruction.

RESET input clears this register to 00H.

Address: FF61H After reset: 00H R/W

Symbol

7

0

6

0

5

0

4

0

3

0

2

1

0

MC0CTL1

MC0CKS2

MC0CKS1

MC0CKS0

MC0CKS2

MC0CKS1

MC0CKS0

Base clock (fXCLK) selection

0

1

0

1

0

1

0

1

0

1

0

1

0

1

fX (10 MHz)

fX/2 (5 MHz)

fX/2²(2.5 MHz)

fX/2³(1.25 MHz)

fX/2⁴(625 kHz)

fX/2⁵(312.5 kHz)

Caution Clear bit 7 (MC0PWR) of the MC0CTL0 register to 0 before rewriting the MC0CKS2 to

MC0CKS0 bits.

Remarks 1. f^X: High-speed system clock oscillation frequency

2. Figures in parentheses are for operation with f^X= 10 MHz.

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(c) MCG control register 2 (MC0CTL2)

This register is used to set the transmit baud rate.

This register can be set by an 8-bit memory manipulation instruction.

RESET input sets this register to 1FH.

Address: FF62H After reset: 1FH R/W

Symbol

7

0

6

0

5

0

4

3

2

1

0

MC0CTL2

MC0BRS4

MC0BRS3

MC0BRS2

MC0BRS1

MC0BRS0

MC0BRS4

MC0BRS3

MC0BRS2

MC0BRS1

MC0BRS0

k

Output clock selection of 5-bit

counter

0

1

×

0

1

×

0

1

0

1

4

5

6

7

fXCLK/4

fXCLK/5

fXCLK/6

fXCLK/7

•

1

0

1

0

1

0

1

28

29

30

31

fXCLK/28

fXCLK/29

fXCLK/30

fXCLK/31

Cautions 1. Clear bit 7 (MC0PWR) of the MC0CTL0 register to 0 before rewriting the MC0BRS4 to

MC0BRS0 bits.

2. The value from further dividing the output clock of the 5-bit counter by 2 is the baud

rate value.

Remarks 1. f^XCLK: Frequency of the base clock selected by the MC0CKS2 to MC0CKS0 bits of the

MC0CTL1 register

2. k: Value set by the MC0BRS4 to MC0BRS0 bits (k = 4, 5, 6, 7, …., 31)

3. ×: Don’t care

<1> Baud rate

The baud rate can be calculated by the following expression.

fXCLK

• Baud rate =

[bps]

2 × k

f^XCLK: Frequency of base clock selected by the MC0CKS2 to MC0CKS0 bits of the MC0CTL1 register

k:

Value set by the MC0BRS4 to MC0BRS0 bits of the MC0CTL2 register (k = 4, 5, 6, ..., 31)

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<2> Error of baud rate

The baud rate error can be calculated by the following expression.

Actual baud rate (baud rate with error)

• Error (%) =

− 1 × 100 [%]

Desired baud rate (correct baud rate)

Caution Keep the baud rate error during transmission to within the permissible error range at the

reception destination.

Example: Frequency of base clock = 2.5 MHz = 2,500,000 Hz

Set value of MC0BRS4 to MC0BRS0 bits of MC0CTL2 register = 10000B (k = 16)

Target baud rate = 76,800 bps

Baud rate = 2.5 M/(2 × 16)

= 2,500,000/(2 × 16) = 78125 [bps]

Error = (78,125/76,800 − 1) × 100

= 1.725 [%]

<3> Example of setting baud rate

Baud

Rate

[bps]

f

X

= 10.0 MHz

f

X

= 8.38 MHz

Calculated ERR MC0CKS2

f

X

= 8.0 MHz

Calculated ERR MC0CKS2

f

X

= 6.0 MHz

Calculated ERR

MC0CKS2

k

Calculated ERR MC0CKS2

k

to

Value

[%]

to

MC0CKS0

Value

[%]

to

Value

[%]

to

Value

[%]

MC0CKS0

4800

9600

–

5, 6, or 7 27

4850

9699

1.03 5, 6, or 7 26

1.03 5, 6, or 7 13

4808

9615

0.16 5, 6, or 7 20

4688

9375

–2.34

5, 6, or 7 16

9766

1.73

0

4

3

2

1

2

1

2

1

0

27

17

27

19

17

27

9

0.16

0

4

2

1

2

1

20

10

24

20

27

12

10

13

12

10

6

19200

31250

38400

56000

62500

76800

115200

125000

153600

250000

5

4

3

2

1

8

19531

31250

39063

56818

62500

78125

19398

1.03

4

3

2

1

13

8

19231

31250

38462

55556

62500

76923

18750 –2.34

31250

10

8

30809 –1.41

38796 1.03

0

1.73

1.46

0

13

9

0.16

–0.79

0

37500 –2.34

55556 –0.79

11

20

16

22

20

16

10

55132 –1.55

61618 –1.41

8

62500

0

1.73

77592

1.03

13

17

16

13

8

0.16

75000 –2.34

115385 0.16

113636 –1.36

125000

156250 1.73

250000

116389 1.03

123235 –1.41

149643 –2.58

261875 4.75

246471 –1.41

117647 2.12

125000

153846 0.16

250000

0

17

7

0

125000

150000 –2.34

250000

0

8

0

17

Remark MC0CKS2 to MC0CKS0: Bits 2 to 0 of MCG control register 1 (MC0CTL1) (setting of base clock (f^XCLK))

k:

Value set by bits 4 to 0 (MC0BRS4 to MC0BRS0) of MCG control register 2

(MC0CTL2) (k = 4, 5, 6, …, 31)

f^X:

High-speed system clock oscillation frequency

Baud rate error

ERR:

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(d) Alternate-function pin switch register (PSEL)

This register is used to select the MCGO pin.

This register can be set by a 1-bit or 8-bit memory manipulation instruction.

RESET input clears this register to 00H.

Address: FF70H After reset: 00H R/W

Symbol

PSEL

7

0

6

0

<5>

<4>

3

0

2

0

<1>

<0>

TOH1SL

MCGSL

INTP1SL

INTP3SL

MCGSL

MCGO pin selection

0

1

P00/TI000/INTP0/MCGO

P13/TxD6/INTP1/(TOH1)/(MCGO)

Caution Clear bit 7 (MC0PWR) of MCG control register 0 (MC0CTL0) to 0 before rewriting the

MCGSL bit.

(e) Port mode registers 0, 1 (PM0, PM1)

This register sets ports 0 and 1 input/output in 1-bit units.

When using the P00/TI000/INTP0/MCGO and P13/TxD6/INTP1/(TOH1)/(MCGO) pins for Manchester code

output, clear PM00 and PM13 to 0 and clear the output latches of P00 and P13 to 0.

PM0 and PM1 can be set by a 1-bit or 8-bit memory manipulation instruction.

RESET input sets these registers to FFH.

Address: FF20H After reset: FFH R/W

Symbol

PM0

7

1

6

1

5

1

4

1

3

1

2

1

0

PM01

PM00

PM0n

P0n pin I/O mode selection (n = 0, 1)

0

1

Output mode (output buffer on)

Input mode (output buffer off)

Address: FF21H After reset: FFH R/W

Symbol

PM1

7

1

6

1

5

4

3

2

1

0

PM15

PM14

PM13

PM12

PM11

PM10

PM1n

P1n pin I/O mode selection (n = 0 to 5)

0

1

Output mode (output buffer on)

Input mode (output buffer off)

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(2) Port settings

(a) When P00/TI000/INTP0/MCGO is set as Manchester code output

Bit 0 of port mode register 0 (PM00): Cleared to 0

Bit 0 of port 0 (P00):

Cleared to 0

(b) When P13/TxD6/INTP1/(TOH1)/(MCGO) is set as Manchester code output

Bit 3 (PM13) of port mode register 1: Cleared to 0

Bit 3 (P13) of port 1:

Cleared to 0

<R>

(3) Format of "0" and "1" of Manchester code output

The format of "0" and "1" of Manchester code output in µPD780862 Subseries is as follows.

"0"

"1"

MCG0 pin

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(3) Transmit operation

In Manchester code generator mode, data is transmitted in 1- to 8-bit units. Data bits are transmitted in

Manchester code format. Transmission is enabled if bit 7 (MC0PWR) of MCG control register 0 (MC0CTL0) is

set to 1.

The output value while a transmission is suspended can be set by using bit 0 (MC0OLV) of the MC0CTL0

register.

A transmission starts by writing a value to the MCG transmit buffer register (MC0TX) after setting the transmit

data bit length to the MCG transmit bit count specification register (MC0BIT). At the transmission start timing, the

MC0BIT value is transferred to the 3-bit counter and the data of MC0TX is transferred to the 8-bit shift register.

An interrupt request signal (INTMCG) occurs at the timing that the MC0TX value is transferred to the 8-bit shift

register. The 8-bit shift register is continuously shifted by the baud rate clock, and signal that is XORed with the

baud rate clock is output from the MCGO pin.

When continuous transmission is executed, the next data is set to MC0BIT and MC0TX during data transmission

after INTMCG occurs.

To transmit continuously, writing the next transfer data to MC0TX must be complete within the period (3) and (4)

in Figure 13-8. Rewrite the MC0BIT before writing to MC0TX during continuous transmission.

Figure 13-8. Timing of Manchester Code Generator Mode (LSB First) (1/4)

(1) Transmit timing (MC0OLV = 1, total transmit bit length = 8 bits)

MC0PWR

MC0OLV

MC0OSL

“L”

MC0BIT

3-bit counter

“111”

“110”

“101”

“100”

“011”

“010”

“001”

“000”

MC0TX

“10010110” (8-bit data)

8-bit shift register

Baud rate clock

“10010110” “x1001011” “xx100101” “xxx10010”

“xxxx1001”

“xxxxx100”

“xxxxxx10”

“xxxxxxx1”

MCGO pin

MC0TSF

INTMCG

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Figure 13-8. Timing of Manchester Code Generator Mode (LSB First) (2/4)

(2) Transmit timing (MC0OLV = 0, total transmit bit length = 8 bits)

MC0PWR

MC0OLV

MC0OSL

“L”

MC0BIT

“111”

3-bit counter

“111”

“110”

“101”

“100”

“011”

“010”

“001”

“000”

MC0TX

“10010110” (8-bit data)

8-bit shift register

“10010110” “x1001011” “xx100101” “xxx10010”

“xxxx1001”

“xxxxx100”

“xxxxxx10”

“xxxxxxx1”

Baud rate clock

MCGO pin

MC0TSF

INTMCG

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Figure 13-8. Timing of Manchester Code Generator Mode (LSB First) (3/4)

(3) Transmit timing (MC0OLV = 1, total transmit bit length = 13 bits)

MC0PWR

MC0OLV

MC0OSL

"L"

Write

MC0BIT

"

111

"

"100"

3-bit counter

"

111

"

110

"

101

"

100

"

011

"

010

"

001

"

000

"

100

"

011

"

010

"

001

"

"000"

Write

10100101

^"(8-bit data)^"

<R>

MC0TX

"xxx10100" (5-bit data)

"1010

0101"

"x101

0010"

"xx10

1001"

"xxx1

0100"

"xxxx

1010"

"xxxx

x101"

"xxxx

xx10"

"xxxx

xxx1"

"xxx1

0100"

"xxxx

1010"

"xxxx

x101"

"xxxx

xx10"

"xxxx

xxx1"

8-bit shift register

Baud rate clock

MCGO pin

MC0TSF

INTMCG

(a)

(b)

(a):

(b):

“8-bit transfer period” – (b)

“1/2 cycle of baud rate” + 1 clock (f^XCLK) before the last bit of transmit data

fXCLK:

Frequency of the operation base clock selected by using the MC0CKS2 to MC0CKS0 bits of

the MC0CTL1 register

Last bit: Transfer bit when 3-bit counter = 000

Caution Writing the next transmit data to MC0TX must be complete within the period (a) during

continuous transmission. If writing the next transmit data to MC0TX is executed in the period

(b), the next data transmission starts 2 clocks (f^XCLK) after the last bit has been transmitted.

Rewrite the MC0BIT before writing to MC0TX during continuous transmission.

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Figure 13-8. Timing of Manchester Code Generator Mode (LSB First) (4/4)

(4) Transmit timing (MC0OLV = 0, total transmit bit length = 13 bits)

MC0PWR

MC0OLV

MC0OSL

"

L

"

L

Write

MC0BIT

"

111

"

"100"

3-bit counter

"

111

"

110

"

101

"

100

"

011

"

010

"

001

"

000

"

100

"

011

"

010

"

001

"

"000"

Write

^"(8-bit data)^"

10100101

<R>

MC0TX

"xxx10100" (5-bit data)

"1010

0101"

"x101

0010"

"xx10

1001"

"xxx1

0100"

"xxxx

1010"

"xxxx

x101"

"xxxx

xx10"

"xxxx

xxx1"

"xxx1

0100"

"xxxx

1010"

"xxxx

x101"

"xxxx

xx10"

"xxxx

xxx1"

8-bit shift register

Baud rate clock

MCGO pin

MC0TSF

INTMCG

(a)

(b)

(a):

(b):

“8-bit transfer period” – (b)

“1/2 cycle of baud rate” + 1 clock (f^XCLK) before the last bit of transmit data

fXCLK:

Frequency of the operation base clock selected by using the MC0CKS2 to MC0CKS0 bits of

the MC0CTL1 register

Last bit: Transfer bit when 3-bit counter = 000

Caution Writing the next transmit data to MC0TX must be complete within the period (a) during

continuous transmission. If writing the next transmit data to MC0TX is executed in the period

(b), the next data transmission starts 2 clocks (f^XCLK) after the last bit has been transmitted.

Rewrite the MC0BIT before writing to MC0TX during continuous transmission.

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CHAPTER 13 MANCHESTER CODE GENERATOR

13.4.3 Bit sequential buffer mode

The bit sequential buffer mode is used to output sequential signals using the MCGO pin.

(1) Register description

The MCG control register 0 (MC0CTL0), MCG control register 1 (MC0CTL1), and MCG control register 2

(MC0CTL2) are used to set the bit sequential buffer mode.

(a) MCG control register 0 (MC0CTL0)

This register can be set by a 1-bit or 8-bit memory manipulation instruction.

RESET input sets this register to 10H.

Address: FF60H After reset: 10H R/W

Symbol

<7>

6

0

5

0

<4>

3

0

2

0

<1>

<0>

MC0CTL0

MC0PWR

MC0DIR

MC0OSL

MC0OLV

MC0PWR

Operation control

First bit specification

Data format

0

1

Operation stopped

Operation enabled

MC0DIR

0

1

MSB

LSB

MC0OSL

0

1

Manchester code

Bit sequential data

MC0OLV

Output level when transmission suspended

0

1

Low level

High level

Caution Clear (0) the MC0PWR bit before rewriting the MC0DIR, MC0OSL, and MC0OLV bits (it is

possible to rewrite these bits by an 8-bit memory manipulation instruction at the same

time when the MC0PWR bit is set (1)).

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CHAPTER 13 MANCHESTER CODE GENERATOR

(b) MCG control register 1 (MC0CTL1)

This register is used to set the base clock of the Manchester code generator.

This register can be set by an 8-bit memory manipulation instruction.

RESET input clears this register to 00H.

Address: FF61H After reset: 00H R/W

Symbol

7

0

6

0

5

0

4

0

3

0

2

1

0

MC0CTL1

MC0CKS2

MC0CKS1

MC0CKS0

MC0CKS2

MC0CKS1

MC0CKS0

Base clock (fXCLK) selection

0

1

0

1

0

1

0

1

0

1

0

1

0

1

fX (10 MHz)

fX/2 (5 MHz)

fX/2²(2.5 MHz)

fX/2³(1.25 MHz)

fX/2⁴(625 kHz)

fX/2⁵(312.5 kHz)

Caution Clear bit 7 (MC0PWR) of the MC0CTL0 register to 0 before rewriting the MC0CKS2 to

MC0CKS0 bits.

Remarks 1. f^X: High-speed system clock oscillation frequency

2. Figures in parentheses are for operation with f^X= 10 MHz.

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CHAPTER 13 MANCHESTER CODE GENERATOR

(c) MCG control register 2 (MC0CTL2)

This register is used to set the transmit baud rate.

This register can be set by an 8-bit memory manipulation instruction.

RESET input sets this register to 1FH.

Address: FF62H After reset: 1FH R/W

Symbol

7

0

6

0

5

0

4

3

2

1

0

MC0CTL2

MC0BRS4

MC0BRS3

MC0BRS2

MC0BRS1

MC0BRS0

MC0BRS4

MC0BRS3

MC0BRS2

MC0BRS1

MC0BRS0

k

Output clock selection of 5-bit

counter

0

1

×

0

1

×

0

1

0

1

4

5

6

7

fXCLK/4

fXCLK/5

fXCLK/6

fXCLK/7

•

1

0

1

0

1

0

1

28

29

30

31

fXCLK/28

fXCLK/29

fXCLK/30

fXCLK/31

Cautions 1. Clear bit 7 (MC0PWR) of the MC0CTL0 register to 0 before rewriting the MC0BRS4 to

MC0BRS0 bits.

2. The value from further dividing the output clock of the 5-bit counter by 2 is the baud

rate value.

Remarks 1. f^XCLK: Frequency of the base clock selected by the MC0CKS2 to MC0CKS0 bits of the

MC0CTL1 register

2. k: Value set by the MC0BRS4 to MC0BRS0 bits (k = 4, 5, 6, 7, …., 31)

3. ×: Don’t care

<1> Baud rate

The baud rate can be calculated by the following expression.

fXCLK

• Baud rate =

[bps]

2 × k

f^XCLK: Frequency of base clock selected by the MC0CKS2 to MC0CKS0 bits of the MC0CTL1 register

k:

Value set by the MC0BRS4 to MC0BRS0 bits of the MC0CTL2 register (k = 4, 5, 6, ..., 31)

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CHAPTER 13 MANCHESTER CODE GENERATOR

<2> Error of baud rate

The baud rate error can be calculated by the following expression.

Actual baud rate (baud rate with error)

• Error (%) =

− 1 × 100 [%]

Desired baud rate (correct baud rate)

Caution Keep the baud rate error during transmission to within the permissible error range at the

reception destination.

Example: Frequency of base clock = 2.5 MHz = 2,500,000 Hz

Set value of MC0BRS4 to MC0BRS0 bits of MC0CTL2 register = 10000B (k = 16)

Target baud rate = 76,800 bps

Baud rate = 2.5 M/(2 × 16)

= 2,500,000/(2 × 16) = 78125 [bps]

Error = (78,125/76,800 − 1) × 100

= 1.725 [%]

<3> Example of setting baud rate

Baud

Rate

[bps]

f

X

= 10.0 MHz

f

X

= 8.38 MHz

Calculated ERR MC0CKS2

f

X

= 8.0 MHz

Calculated ERR MC0CKS2

f

X

= 6.0 MHz

Calculated ERR

MC0CKS2

k

Calculated ERR MC0CKS2

k

to

Value

[%]

to

MC0CKS0

Value

[%]

to

Value

[%]

to

Value

[%]

MC0CKS0

4800

9600

–

5, 6, or 7 27

4850

9699

1.03 5, 6, or 7 26

1.03 5, 6, or 7 13

4808

9615

0.16 5, 6, or 7 20

4688

9375

–2.34

5, 6, or 7 16

9766

1.73

0

4

3

2

1

2

1

2

1

0

27

17

27

19

17

27

9

0.16

0

4

2

1

2

1

20

10

24

20

27

12

10

13

12

10

6

19200

31250

38400

56000

62500

76800

115200

125000

153600

250000

5

4

3

2

1

8

19531

31250

39063

56818

62500

78125

19398

1.03

4

3

2

1

13

8

19231

31250

38462

55556

62500

76923

18750 –2.34

31250

10

8

30809 –1.41

38796 1.03

0

1.73

1.46

0

13

9

0.16

–0.79

0

37500 –2.34

55556 –0.79

11

20

16

22

20

16

10

55132 –1.55

61618 –1.41

8

62500

0

1.73

77592

1.03

13

17

16

13

8

0.16

75000 –2.34

115385 0.16

113636 –1.36

125000

156250 1.73

250000

116389 1.03

123235 –1.41

149643 –2.58

261875 4.75

246471 –1.41

117647 2.12

125000

153846 0.16

250000

0

17

7

0

125000

150000 –2.34

250000

0

8

0

17

Remark MC0CKS2 to MC0CKS0: Bits 2 to 0 of MCG control register 1 (MC0CTL1) (setting of base clock (f^XCLK))

k:

Value set by bits 4 to 0 (MC0BRS4 to MC0BRS0) of MCG control register 2

(MC0CTL2) (k = 4, 5, 6, …, 31)

f^X:

High-speed system clock oscillation frequency

Baud rate error

ERR:

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CHAPTER 13 MANCHESTER CODE GENERATOR

(d) Alternate-function pin switch register (PSEL)

This register is used to select the MCGO pin.

This register can be set by a 1-bit or 8-bit memory manipulation instruction.

RESET input clears this register to 00H.

Address: FF70H After reset: 00H R/W

<Symbol

PSEL

7

0

6

0

<5>

<4>

3

0

2

0

<1>

<0>

TOH1SL

MCGSL

INTP1SL

INTP3SL

MCGSL

MCGO pin selection

0

1

P00/TI000/INTP0/MCGO

P13/TxD6/INTP1/(TOH1)/(MCGO)

Caution Clear bit 7 (MC0PWR) of MCG control register 0 (MC0CTL0) to 0 before rewriting the

MCGSL bit.

(e) Port mode registers 0, 1 (PM0, PM1)

This register sets ports 0 and 1 input/output in 1-bit units.

When using the P00/TI000/INTP0/MCGO and P13/TxD6/INTP1/(TOH1)/(MCGO) pins for bit sequential data

output, clear PM00 and PM13 to 0 and clear the output latches of P00 and P13 to 0.

PM0 and PM1 can be set by a 1-bit or 8-bit memory manipulation instruction.

RESET input sets these registers to FFH.

Address: FF20H After reset: FFH R/W

Symbol

PM0

7

1

6

1

5

1

4

1

3

1

2

1

0

PM01

PM00

PM0n

P0n pin I/O mode selection (n = 0, 1)

0

1

Output mode (output buffer on)

Input mode (output buffer off)

Address: FF21H After reset: FFH R/W

Symbol

PM1

7

1

6

1

5

4

3

2

1

0

PM15

PM14

PM13

PM12

PM11

PM10

PM1n

P1n pin I/O mode selection (n = 0 to 5)

0

1

Output mode (output buffer on)

Input mode (output buffer off)

(2) Port settings

(a) When P00/TI000/INTP0/MCGO is set as bit sequential data output

Bit 0 of port mode register 0 (PM00): Cleared to 0

Bit 0 of port 0 (P00):

Cleared to 0

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CHAPTER 13 MANCHESTER CODE GENERATOR

(b) When P13/TxD6/INTP1/(TOH1)/(MCGO) is set as bit sequential data output

Bit 3 (PM13) of port mode register 1: Cleared to 0

Bit 3 (P13) of port 1:

Cleared to 0

(3) Transmit operation

In bit sequential buffer mode, data is transmitted in 1- to 8-bit units. Transmission is enabled if bit 7 (MC0PWR)

of MCG control register 0 (MC0CTL0) is set to 1.

The output value while transmission is suspended can be set by using bit 0 (MC0OLV) of the MC0CTL0 register.

A transmission starts by writing a value to the MCG transmit buffer register (MC0TX) after setting the transmit

data bit length to the MCG transmit bit count specification register (MC0BIT). At the transmission start timing, the

MC0BIT value is transferred to the 3-bit counter and data of MC0TX is transferred to the 8-bit shift register. An

interrupt request signal (INTMCG) occurs at the timing that the MC0TX value is transferred to the 8-bit shift

register. The 8-bit shift register is continuously shifted by the baud rate clock and is output from the MCGO pin.

When continuous transmission is executed, the next data is set to MC0BIT and MC0TX during data transmission

after INTMCG occurs.

To transmit continuously, writing the next transfer data to MC0TX must be complete within the period (3) and (4)

in Figure 13-9. Rewrite MC0BIT before writing to MC0TX during continuous transmission.

Figure 13-9. Timing of Bit Sequential Buffer Mode (LSB First) (1/4)

(1) Transmit timing (MC0OLV = 1, total transmit bit length = 8 bits)

MC0PWR

MC0OLV

MC0OSL

MC0BIT

“111”

3-bit counter

“111”

“110”

“101”

“100”

“011”

“010”

“001”

“000”

MC0TX

“10010110” (8-bit data)

8-bit shift register

“10010110” “x1001011” “xx100101” “xxx10010”

“xxxx1001”

“xxxxx100”

“xxxxxx10”

“xxxxxxx1”

Baud rate clock

MCGO pin

MC0TSF

INTMCG

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CHAPTER 13 MANCHESTER CODE GENERATOR

Figure 13-9. Timing of Bit Sequential Buffer Mode (LSB First) (2/4)

(2) Transmit timing (MC0OLV = 0, total transmit bit length = 8 bits)

MC0PWR

MC0OLV

MC0OSL

“L”

MC0BIT

“111”

3-bit counter

“111”

“110”

“101”

“100”

“011”

“010”

“001”

“000”

MC0TX

“10010110” (8-bit data)

8-bit shift register

“10010110” “x1001011” “xx100101” “xxx10010”

“xxxx1001”

“xxxxx100”

“xxxxxx10”

“xxxxxxx1”

Baud rate clock

MCGO pin

MC0TSF

INTMCG

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CHAPTER 13 MANCHESTER CODE GENERATOR

Figure 13-9. Timing of Bit Sequential Buffer Mode (LSB First) (3/4)

(3) Transmit timing (MC0OLV = 1, total transmit bit length = 13 bits)

MC0PWR

MC0OLV

MC0OSL

Write

MC0BIT

"

111

"

"100"

3-bit counter

"

111

"

110

"

101

"

100

"

011

"

010

"

001

"

000

"

100

"

011

"

010

"

001

"

"000"

Write

10100101

^"(8-bit data)^"

<R>

"xxx10100"(5-bit data)

MC0TX

"1010

0101"

"x101

0010"

"xx10

1001"

"xxx1

0100"

"xxxx

1010"

"xxxx

x101"

"xxxx

xx10"

"xxxx

xxx1"

"xxx1

0100"

"xxxx

1010"

"xxxx

x101"

"xxxx

xx10"

"xxxx

xxx1"

8-bit shift register

Baud rate clock

MCGO pin

MC0TSF

INTMCG

(a)

(b)

(a):

“8-bit transfer period” – (b)

“1/2 cycle of baud rate” + 1 clock (f^XCLK) before the last bit of transmit data

(b):

fXCLK:

Frequency of operation base clock selected by using the MC0CKS2 to MC0CKS0 bits of the

MC0CTL1 register

Last bit: Transfer bit when 3-bit counter = 000

Caution Writing the next transmit data to MC0TX must be complete within the period (a) during

continuous transmission. If writing the next transmit data to MC0TX is executed in the period

(b), the next data transmission starts 2 clocks (f^XCLK) after the last bit has been transmitted.

Rewrite the MC0BIT before writing to MC0TX during continuous transmission.

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CHAPTER 13 MANCHESTER CODE GENERATOR

Figure 13-9. Timing of Bit Sequential Buffer Mode (LSB First) (4/4)

(4) Transmit timing (MC0OLV = 0, total transmit bit length = 13 bits)

MC0PWR

MC0OLV

MC0OSL

"L"

Write

MC0BIT

"

111

"

"100"

3-bit counter

"

111

"

110

"

101

"

100

"

011

"

010

"

001

"

000

"

100

"

011

"

010

"

001

"

"000"

Write

10100101

^"(8-bit data)^"

<R>

"

xxx10100" (5-bit data)

MC0TX

"1010

0101"

"x101

0010"

"xx10

1001"

"xxx1

0100"

"xxxx

1010"

"xxxx

x101"

"xxxx

xx10"

"xxxx

xxx1"

"xxx1

0100"

"xxxx

1010"

"xxxx

x101"

"xxxx

xx10"

"xxxx

xxx1"

8-bit shift register

Baud rate clock

MCGO pin

MC0TSF

INTMCG

(a)

(b)

(a):

(b):

“8-bit transfer period” – (b)

“1/2 cycle of baud rate” + 1 clock (f^XCLK) before the last bit of transmit data

fXCLK:

Frequency of operation base clock selected by using the MC0CKS2 to MC0CKS0 bits of the

MC0CTL1 register

Last bit: Transfer bit when 3-bit counter = 000

Caution Writing the next transmit data to MC0TX must be complete within the period (a) during

continuous transmission. If writing the next transmit data to MC0TX is executed in the period

(b), the next data transmission starts 2 clocks (f^XCLK) after the last bit has been transmitted.

Rewrite the MC0BIT before writing to MC0TX during continuous transmission.

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CHAPTER 14 INTERRUPT FUNCTIONS

14.1 Interrupt Function Types

The following two types of interrupt functions are used.

(1) Maskable interrupts

These interrupts undergo mask control. Maskable interrupts can be divided into a high interrupt priority group

and a low interrupt priority group by setting the priority specification flag registers (PR0L, PR0H, PR1L).

Multiple interrupt servicing of high-priority interrupts can be applied to low priority interrupts. If two or more

interrupts with the same priority are simultaneously generated, each interrupt is serviced according to its

predetermined priority (see Table 14-1).

A standby release signal is generated and the STOP and HALT modes are released.

Four external interrupt requests and 12 internal interrupt requests are provided as maskable interrupts.

(2) Software interrupt

This is a vectored interrupt generated by executing the BRK instruction. It is acknowledged even when interrupts

are disabled. The software interrupt does not undergo interrupt priority control.

14.2 Interrupt Sources and Configuration

A total of 17 interrupt sources exist for maskable and software interrupts. In addition, maximum total of 5 reset

sources are also provided (see Table 14-1).

282

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CHAPTER 14 INTERRUPT FUNCTIONS

Table 14-1. Interrupt Source List

Interrupt

Type

Default

Interrupt Source

Trigger

Internal/

External

Vector

Table

Basic

Priority^{Note 1}

Configuration

Type^{Note 2}

Name

INTLVI

Address

Maskable

0

1

Low-voltage detection^{Note 3}

Pin input edge detection

Internal

0004H

0006H

0008H

000AH

000CH

000EH

0012H

0014H

0016H

0018H

001AH

(A)

(B)

INTP0

External

2

INTP1

3

INTP2

4

INTP3

5

INTMCG

INTSRE6

INTSR6

INTST6

INTCSI10

INTTMH1

End of Manchester code transmission

UART6 reception error generation

End of UART6 reception

Internal

(A)

6

7

8

End of UART6 transmission

9

End of CSI10 communication

10

Match between TMH1 and CMP01

(when compare register is specified)

11

12

13

INTTMH0

INTTM50

Match between TMH0 and CMP00

(when compare register is specified)

001CH

001EH

0020H

Match between TM50 and CR50

(when compare register is specified)

<R>

INTTM000 Match between TM00 and CR000

(when compare register is specified),

TI010 pin valid edge detection

(when capture register is specified)

14

INTTM010 Match between TM00 and CR010

(when compare register is specified),

TI000 pin valid edge detection

0022H

(when capture register is specified)

15

−

INTAD

BRK

End of A/D conversion

BRK instruction execution

Reset input

0024H

003EH

0000H

Software

Reset

−

(C)

−

RESET

POC

−

Power-on-clear

LVI

Low-voltage detection^{Note 4}

Clock

High-speed system clock stop detection

monitor

WDT

WDT overflow

Notes 1. The default priority is the priority applicable when two or more maskable interrupts are generated

simultaneously. 0 is the highest priority, and 15 is the lowest.

2. Basic configuration types (A) to (C) correspond to (A) to (C) in Figure 14-1.

3. When bit 1 (LVIMD) = 0 is selected for the low-voltage detection register (LVIM).

4. When LVIMD = 1 is selected.

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CHAPTER 14 INTERRUPT FUNCTIONS

Figure 14-1. Basic Configuration of Interrupt Function

(A) Internal maskable interrupt

Internal bus

IE

MK

PR

ISP

Vector table

address generator

Priority controller

Interrupt

request

IF

Standby release signal

(B) External maskable interrupt (INTP0 to INTP3)

Internal bus

External interrupt edge

enable register

(EGP, EGN)

MK

IE

PR

ISP

Vector table

address generator

Priority controller

Interrupt

request

Edge

detector

IF

Standby release signal

(C) Software interrupt

Internal bus

Interrupt

request

Vector table

address generator

Priority controller

IF:

IE:

Interrupt request flag

Interrupt enable flag

ISP: In-service priority flag

MK:

PR:

Interrupt mask flag

Priority specification flag

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CHAPTER 14 INTERRUPT FUNCTIONS

14.3 Registers Controlling Interrupt Function

The following 8 types of registers are used to control the interrupt functions.

•

Interrupt request flag register (IF0L, IF0H, IF1L)

Interrupt mask flag register (MK0L, MK0H, MK1L)

Priority specification flag register (PR0L, PR0H, PR1L)

External interrupt rising edge enable register (EGP)

External interrupt falling edge enable register (EGN)

Program status word (PSW)

Input switch control register (ISC)

Alternate-function pin switch register (PSEL)

The following registers are used to select the INTP0, INTP1, and INTP3 pins, which are used for external interrupt

requests.

•

Input switch control register (ISC): INTP0

Alternate-function pin switch register (PSEL): INTP1, INTP3

•

Table 14-2 shows a list of interrupt request flags, interrupt mask flags, and priority specification flags corresponding

to interrupt request sources.

Table 14-2. Flags Corresponding to Interrupt Request Sources

Interrupt

Source

Interrupt Request Flag

Register

IF0L

Interrupt Mask Flag

Register

MK0L

Priority Specification Flag

Register

INTLVI

LVIIF

LVIMK

LVIPR

PR0L

INTP0

PIF0

PMK0

PPR0

INTP1

PIF1

PMK1

PPR1

INTP2

PIF2

PMK2

PPR2

INTP3

PIF3

PMK3

PPR3

INTMCG

INTSRE6

INTSR6

INTST6

INTCSI10

INTTMH1

INTTMH0

INTTM50

INTTM000

INTTM010

INTAD

MCGIF

SREIF6

SRIF6

STIF6

CSIIF10

TMIFH1

TMIFH0

TMIF50

TMIF000

TMIF010

ADIF

MCGMK

SREMK6

SRMK6

STMK6

CSIMK10

TMMKH1

TMMKH0

TMMK50

TMMK000

TMMK010

ADMK

MCGPR

SREPR6

SRPR6

STPR6

CSIPR10

TMPRH1

TMPRH0

TMPR50

TMPR000

TMPR010

ADPR

IF0H

MK0H

PR0H

1F1L

MK1L

PR1L

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CHAPTER 14 INTERRUPT FUNCTIONS

(1) Interrupt request flag registers (IF0L, IF0H, IF1L)

The interrupt request flags are set to 1 when the corresponding interrupt request is generated or an instruction is

executed. They are cleared to 0 when an instruction is executed upon acknowledgment of an interrupt request or

upon RESET input.

When an interrupt is acknowledged, the interrupt request flag is automatically cleared and then the interrupt

routine is entered.

IF0L, IF0H, and IF1L are set by a 1-bit or 8-bit memory manipulation instruction. When IF0L and IF0H are

combined to form 16-bit register IF0, they are set by a 16-bit memory manipulation instruction.

RESET input sets these registers to 00H.

Figure 14-2. Format of Interrupt Request Flag Register (IF0L, IF0H, IF1L)

Address: FFE0H After reset: 00H R/W

Symbol

IF0L

<7>

6

0

<5>

<4>

<3>

<2>

<1>

<0>

SREIF6

MCGIF

PIF3

PIF2

PIF1

PIF0

LVIIF

Address: FFE1H After reset: 00H R/W

Symbol

IF0H

<7>

<6>

<5>

<4>

<3>

<2>

<1>

<0>

TMIF010

TMIF000

TMIF50

TMIFH0

TMIFH1

CSIIF10

STIF6

SRIF6

Address: FFE2H After reset: 00H R/W

Symbol

IF1L

7

0

6

0

5

0

4

0

3

0

2

0

1

0

<0>

ADIF

XXIFX

Interrupt request flag

0

1

No interrupt request signal is generated

Interrupt request is generated, interrupt request status

Cautions 1. Be sure to set bit 6 of IF0L and bits 1 to 7 of IF1L to 0.

2. When operating a timer, serial interface, or A/D converter after standby release, operate it

once after clearing the interrupt request flag. An interrupt request flag may be set by noise.

3. When manipulating a flag of the interrupt request flag register, use a 1-bit memory

manipulation instruction (CLR1). When describing in C language, use a bit manipulation

instruction such as “IF0L.0 = 0;” or “_asm(“clr1 IF0L, 0”);” because the compiled assembler

must be a 1-bit memory manipulation instruction (CLR1).

If a program is described in C language using an 8-bit memory manipulation instruction

such as “IF0L &= 0xfe;” and compiled, it becomes the assembler of three instructions.

mov

and

a, IF0L

a, #0FEH

IF0L, a

mov

In this case, even if the request flag of another bit of the same interrupt request flag register

(IF0L) is set to 1 at the timing between “mov a, IF0L” and “mov IF0L, a”, the flag is cleared

to 0 at “mov IF0L, a”. Therefore, care must be exercised when using an 8-bit memory

manipulation instruction in C language.

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(2) Interrupt mask flag registers (MK0L, MK0H, MK1L)

The interrupt mask flags are used to enable/disable the corresponding maskable interrupt servicing.

MK0L, MK0H, and MK1L are set by a 1-bit or 8-bit memory manipulation instruction. When MK0L and MK0H are

combined to form 16-bit register MK0, they are set by a 16-bit memory manipulation instruction.

RESET input sets these registers to FFH.

Figure 14-3. Format of Interrupt Mask Flag Register (MK0L, MK0H, MK1L)

Address: FFE4H After reset: FFH R/W

Symbol

MK0L

<7>

6

1

<5>

<4>

<3>

<2>

<1>

<0>

SREMK6

MCGMK

PMK3

PMK2

PMK1

PMK0

LVIMK

Address: FFE5H After reset: FFH R/W

Symbol

MK0H

<7>

<6>

<5>

<4>

<3>

<2>

<1>

<0>

TMMK010 TMMK000

TMMK50

TMMKH0

TMMKH1

CSIMK10

STMK6

SRMK6

Address: FFE6H After reset: FFH R/W

Symbol

MK1L

7

1

6

1

5

1

4

1

3

1

2

1

<0>

ADMK

XXMKX

Interrupt servicing control

0

1

Interrupt servicing enabled

Interrupt servicing disabled

Caution Be sure to set bit 6 of MK0L and bits 1 to 7 of MK1L to 1.

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(3) Priority specification flag registers (PR0L, PR0H, PR1L)

The priority specification flag registers are used to set the corresponding maskable interrupt priority order.

PR0L, PR0H, and PR1L are set by a 1-bit or 8-bit memory manipulation instruction. If PR0L and PR0H are

combined to form 16-bit register PR0, they are set by a 16-bit memory manipulation instruction.

RESET input sets these registers to FFH.

Figure 14-4. Format of Priority Specification Flag Register (PR0L, PR0H, PR1L)

Address: FFE8H After reset: FFH R/W

Symbol

PR0L

<7>

6

1

<5>

<4>

<3>

<2>

<1>

<0>

SREPR6

MCGPR

PPR3

PPR2

PPR1

PPR0

LVIPR

Address: FFE9H After reset: FFH R/W

Symbol

PR0H

<7>

<6>

<5>

<4>

<3>

<2>

<1>

<0>

TMPR010 TMPR000

TMPR50

TMPRH0

TMPRH1

CSIPR10

STPR6

SRPR6

Address: FFEAH After reset: FFH R/W

Symbol

PR1L

7

1

6

1

5

1

4

1

3

1

2

1

<0>

ADPR

XXPRX

Priority level selection

0

1

High priority level

Low priority level

Caution Be sure to set bit 6 of PR0L and bits 1 to 7 of PR1L to 1.

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(4) External interrupt rising edge enable register (EGP), external interrupt falling edge enable register (EGN)

These registers specify the valid edge for INTP0 to INTP3.

EGP and EGN are set by a 1-bit or 8-bit memory manipulation instruction.

RESET input sets these registers to 00H.

Figure 14-5. Format of External Interrupt Rising Edge Enable Register (EGP)

and External Interrupt Falling Edge Enable Register (EGN)

Address: FF48H After reset: 00H R/W

Symbol

EGP

7

0

6

0

5

0

4

0

3

2

1

0

EGP3

EGP2

EGP1

EGP0

Address: FF49H After reset: 00H R/W

Symbol

EGN

7

0

6

0

5

0

4

0

3

2

1

0

EGN3

EGN2

EGN1

EGN0

EGPn

EGNn

INTPn pin valid edge selection (n = 0 to 3)

0

1

0

1

0

1

Edge detection disabled

Falling edge

Rising edge

Both rising and falling edges

Table 14-3 shows the ports corresponding to EGPn and EGNn.

Table 14-3. Ports Corresponding to EGPn and EGNn

Detection Enable Register

Edge Detection Port

Interrupt Request Signal

EGP0

EGP1

EGP2

EGP3

EGN0

EGN1

EGN2

EGN3

P00 (ISC0 = 0)

P14 (ISC0 = 1)

INTP0

INTP1

INTP2

INTP3

P13 (INTP1SL = 0)

P01

P10 (INTP1SL = 1)

P11 (INTP3SL = 0)

P12 (INTP3SL = 1)

Caution Select the port mode by clearing EGPn and EGNn to 0 because an edge may be detected when

the external interrupt function is switched to the port function.

Remark n = 0 to 3

ISC0:

Bit 0 of input switch control register (ISC)

INTP1SL: Bit 1 of alternate-function pin switch register (PSEL)

INTP3SL: Bit 0 of alternate-function pin switch register (PSEL)

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(5) Program status word (PSW)

The program status word is a register used to hold the instruction execution result and the current status for an

interrupt request. The IE flag that sets maskable interrupt enable/disable and the ISP flag that controls multiple

interrupt servicing are mapped to the PSW.

Besides 8-bit read/write, this register can carry out operations using bit manipulation instructions and dedicated

instructions (EI and DI). When a vectored interrupt request is acknowledged, if the BRK instruction is executed,

the contents of the PSW are automatically saved into a stack and the IE flag is reset to 0. If a maskable interrupt

request is acknowledged, the contents of the priority specification flag of the acknowledged interrupt are

transferred to the ISP flag. The PSW contents are also saved into the stack with the PUSH PSW instruction.

They are restored from the stack with the RETI, RETB, and POP PSW instructions.

RESET input sets PSW to 02H.

Figure 14-6. Format of Program Status Word

After reset

02H

<7> <6> <5> <4> <3>

PSW IE RBS1 AC RBS0

2

0

<1>

ISP

0

Z

CY

Used when normal instruction is executed

ISP

Priority of interrupt currently being serviced

0

High-priority interrupt servicing (low-priority

interrupt disabled)

Interrupt request not acknowledged, or low-

priority interrupt servicing (all maskable

interrupts enabled)

1

IE

0

Interrupt request acknowledgment enable/disable

Disable

Enable

1

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CHAPTER 14 INTERRUPT FUNCTIONS

(6) Input switch control register (ISC)

The input source is switched by setting ISC.

• When P00/INTP0/TI000/MCGO is used as an external interrupt input pin

ISC0 = 0

• When P14/<INTP0>/RxD6 is used as an external interrupt input pin

ISC0 = 1

This register can be set by a 1-bit or 8-bit memory manipulation instruction.

RESET input clears this register to 00H.

Figure 14-7. Format of Input Switch Control Register (ISC)

Address: FF4FH After reset: 00H R/W

Symbol

ISC

7

0

6

0

5

0

4

0

3

0

2

0

1

0

ISC1

ISC0

INTP0 input source selection

0

1

INTP0 (P00)

RxD6 (P14)

Remark When using the P00/INTP0/TI000/MCGO and P14/<INTP0>/RxD6 pins as external

interrupt request inputs, set PM00 and PM14 to 1.

(7) Alternate-function pin switch register (PSEL)

This register is used to select the INTP1 and INTP3 pins.

This register can be set by a 1-bit or 8-bit memory manipulation instruction.

RESET input clears this register to 00H.

Figure 14-8. Format of Alternate-Function Pin Switch Register (PSEL)

Address: FF70H After reset: 00H R/W

Symbol

PSEL

7

0

6

0

<5>

<4>

3

0

2

0

<1>

<0>

TOH1SL

MCGSL

INTP1SL

INTP3SL

INTP1SL

INTP1 pin selection

0

1

P13/TxD6/INTP1/(TOH1)/(MCGO)

P10/SCK10/(INTP1)

INTP3SL

INTP3 pin selection

0

1

P11/SI10/INTP3

P12/SO10/TOH1/(INTP3)

Remark When using the P10/SCK10/(INTP1), P11/SI10/INTP3, P12/TOH1/SO10/(INTP3), and

P13/(TOH1)/TxD6/INTP1/(MCGO) pins as external interrupt request inputs, set PM10 to

PM13 to 1.

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14.4 Interrupt Servicing Operations

14.4.1 Maskable interrupt request acknowledgment

A maskable interrupt request becomes acknowledgeable when the interrupt request flag is set to 1 and the mask

(MK) flag corresponding to that interrupt request is cleared to 0. A vectored interrupt request is acknowledged if

interrupts are in the interrupt enabled state (when the IE flag is set to 1). However, a low-priority interrupt request is

not acknowledged during servicing of a higher priority interrupt request (when the ISP flag is reset to 0). The times

from generation of a maskable interrupt request until interrupt servicing is performed are listed in Table 14-4 below.

For the interrupt request acknowledgment timing, see Figures 14-10 and 14-11.

Table 14-4. Time from Generation of Maskable Interrupt Request Until Servicing

Minimum Time

7 clocks

8 clocks

Maximum Time^Note

32 clocks

33 clocks

When ××PR = 0

When ××PR = 1

Note If an interrupt request is generated just before a divide instruction, the wait time becomes longer.

Remark 1 clock: 1/f^CPU(fCPU: CPU clock)

If two or more maskable interrupt requests are generated simultaneously, the request with a higher priority level

specified in the priority specification flag is acknowledged first. If two or more interrupts requests have the same

priority level, the request with the highest default priority is acknowledged first.

An interrupt request that is held pending is acknowledged when it becomes acknowledgeable.

Figure 14-9 shows the interrupt request acknowledgment algorithm.

If a maskable interrupt request is acknowledged, the contents are saved into the stacks in the order of PSW, then

PC, the IE flag is reset (0), and the contents of the priority specification flag corresponding to the acknowledged

interrupt are transferred to the ISP flag. The vector table data determined for each interrupt request is loaded into the

PC and branched.

Restoring from an interrupt is possible by using the RETI instruction.

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CHAPTER 14 INTERRUPT FUNCTIONS

Figure 14-9. Interrupt Request Acknowledgment Processing Algorithm

Start

No

××IF = 1?

Yes (interrupt request generation)

No

××MK = 0?

Yes

Interrupt request held pending

Yes (High priority)

××PR = 0?

No (Low priority)

Any high-priority

Yes

Any high-priority

interrupt request among those

simultaneously generated

with ××PR = 0?

Yes

interrupt request among

those simultaneously generated

with ××PR = 0?

Interrupt request held pending

No

Interrupt request held pending

Yes

No

IE = 1?

Yes

Any high-priority

interrupt request among

those simultaneously

generated?

Interrupt request held pending

No

IE = 1?

Yes

Vectored interrupt servicing

Interrupt request held pending

No

ISP = 1?

Yes

Interrupt request held pending

Vectored interrupt servicing

××IF: Interrupt request flag

××MK: Interrupt mask flag

××PR: Priority specification flag

IE:

Flag that controls acknowledgment of maskable interrupt request (1 = Enable, 0 = Disable)

ISP: Flag that indicates the priority level of the interrupt currently being serviced (0 = High-priority interrupt

servicing, 1 = No interrupt request acknowledged, or low-priority interrupt servicing)

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CHAPTER 14 INTERRUPT FUNCTIONS

Figure 14-10. Interrupt Request Acknowledgment Timing (Minimum Time)

6 clocks

PSW and PC saved,

jump to interrupt

servicing

Interrupt servicing

program

CPU processing

Instruction

××IF

(××PR = 1)

8 clocks

××IF

(××PR = 0)

7 clocks

Remark 1 clock: 1/fCPU (fCPU: CPU clock)

Figure 14-11. Interrupt Request Acknowledgment Timing (Maximum Time)

25 clocks

6 clocks

PSW and PC saved,

jump to interrupt

servicing

Interrupt servicing

program

CPU processing

Instruction

Divide instruction

××IF

(××PR = 1)

33 clocks

××IF

(××PR = 0)

32 clocks

Remark 1 clock: 1/fCPU (fCPU: CPU clock)

14.4.2 Software interrupt request acknowledgment

A software interrupt request is acknowledged by BRK instruction execution. Software interrupts cannot be

disabled.

If a software interrupt request is acknowledged, the contents are saved into the stacks in the order of the program

status word (PSW), then program counter (PC), the IE flag is reset (0), and the contents of the vector table (003EH,

003FH) are loaded into the PC and branched.

Restoring from a software interrupt is possible by using the RETB instruction.

Caution Do not use the RETI instruction for restoring from the software interrupt.

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CHAPTER 14 INTERRUPT FUNCTIONS

14.4.3 Multiple interrupt servicing

Multiple interrupt servicing occurs when another interrupt request is acknowledged during execution of an interrupt.

Multiple interrupt servicing does not occur unless the interrupt request acknowledgment enabled state is selected

(IE = 1). When an interrupt request is acknowledged, interrupt request acknowledgment becomes disabled (IE = 0).

Therefore, to enable multiple interrupt servicing, it is necessary to set (1) the IE flag with the EI instruction during

interrupt servicing to enable interrupt acknowledgment.

Moreover, even if interrupts are enabled, multiple interrupt servicing may not be enabled, this being subject to

interrupt priority control. Two types of priority control are available: default priority control and programmable priority

control. Programmable priority control is used for multiple interrupt servicing.

In the interrupt enabled state, if an interrupt request with a priority equal to or higher than that of the interrupt

currently being serviced is generated, it is acknowledged for multiple interrupt servicing. If an interrupt with a priority

lower than that of the interrupt currently being serviced is generated during interrupt servicing, it is not acknowledged

for multiple interrupt servicing.

Interrupt requests that are not enabled because interrupts are in the interrupt disabled state or because they have

a lower priority are held pending. When servicing of the current interrupt ends, the pending interrupt request is

acknowledged following execution of at least one main processing instruction execution.

Table 14-5 shows relationship between interrupt requests enabled for multiple interrupt servicing and Figure 14-12

shows multiple interrupt servicing examples.

Table 14-5. Relationship Between Interrupt Requests Enabled for Multiple Interrupt Servicing

During Interrupt Servicing

Multiple Interrupt Request

Maskable Interrupt Request

PR = 0 PR = 1

Software

Interrupt

Request

Interrupt Being Serviced

IE = 1

IE = 0

IE = 1

IE = 0

Maskable interrupt

ISP = 0

ISP = 1

×

Software interrupt

Remarks 1. : Multiple interrupt servicing enabled

2. ×: Multiple interrupt servicing disabled

3. The ISP and IE are flags contained in the PSW.

ISP = 0: An interrupt with higher priority is being serviced.

ISP = 1: No interrupt request has been acknowledged, or an interrupt with a lower

priority is being serviced.

IE = 0: Interrupt request acknowledgment is disabled.

IE = 1: Interrupt request acknowledgment is enabled.

4. PR is a flag contained in PR0L, PR0H, and PR1L.

PR = 0: Higher priority level

PR = 1: Lower priority level

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Figure 14-12. Examples of Multiple Interrupt Servicing (1/2)

Example 1. Multiple interrupt servicing occurs twice

Main processing

INTxx servicing

INTyy servicing

INTzz servicing

IE = 0

EI

INTxx

(PR = 1)

INTyy

(PR = 0)

INTzz

(PR = 0)

RETI

IE = 1

During servicing of interrupt INTxx, two interrupt requests, INTyy and INTzz, are acknowledged, and multiple

interrupt servicing takes place. Before each interrupt request is acknowledged, the EI instruction must always be

issued to enable interrupt request acknowledgment.

Example 2. Multiple interrupt servicing does not occur due to priority control

Main processing

INTxx servicing

INTyy servicing

EI

IE = 0

INTyy

EI

INTxx

(PR = 0)

(PR = 1)

RETI

IE = 1

1 instruction execution

IE = 0

RETI

IE = 1

Interrupt request INTyy issued during servicing of interrupt INTxx is not acknowledged because its priority is lower

than that of INTxx, and multiple interrupt servicing does not take place. The INTyy interrupt request is held pending,

and is acknowledged following execution of one main processing instruction.

PR = 0: Higher priority level

PR = 1: Lower priority level

IE = 0: Interrupt request acknowledgment disabled

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Figure 14-12. Examples of Multiple Interrupt Servicing (2/2)

Example 3. Multiple interrupt servicing does not occur because interrupts are not enabled

Main processing

INTxx servicing INTyy servicing

IE = 0

EI

INTyy

(PR = 0)

INTxx

RETI

(PR = 0)

IE = 1

IE = 0

1 instruction execution

RETI

IE = 1

Interrupts are not enabled during servicing of interrupt INTxx (EI instruction is not issued), therefore, interrupt

request INTyy is not acknowledged and multiple interrupt servicing does not take place. The INTyy interrupt request

is held pending, and is acknowledged following execution of one main processing instruction.

PR = 0: Higher priority level

IE = 0: Interrupt request acknowledgment disabled

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14.4.4 Interrupt request hold

There are instructions where, even if an interrupt request is issued for them while another instruction is being

executed, request acknowledgment is held pending until the end of execution of the next instruction. These

instructions (interrupt request hold instructions) are listed below.

•

MOV PSW, #byte

MOV A, PSW

MOV PSW, A

MOV1 PSW. bit, CY

MOV1 CY, PSW. bit

AND1 CY, PSW. bit

OR1 CY, PSW. bit

XOR1 CY, PSW. bit

SET1 PSW. bit

CLR1 PSW. bit

RETB

RETI

PUSH PSW

POP PSW

BT PSW. bit, $addr16

BF PSW. bit, $addr16

BTCLR PSW. bit, $addr16

EI

DI

Manipulation instructions for the IF0L, IF0H, IF1L, MK0L, MK0H, MK1L, PR0L, PR0H, and PR1L registers

Caution The BRK instruction is not one of the above-listed interrupt request hold instructions. However,

the software interrupt activated by executing the BRK instruction causes the IE flag to be cleared

to 0. Therefore, even if a maskable interrupt request is generated during execution of the BRK

instruction, the interrupt request is not acknowledged.

Figure 14-13 shows the timing at which interrupt requests are held pending.

Figure 14-13. Interrupt Request Hold

PSW and PC saved, jump Interrupt servicing

CPU processing

Instruction N

Instruction M

to interrupt servicing

program

××IF

Remarks 1. Instruction N: Interrupt request hold instruction

2. Instruction M: Instruction other than interrupt request hold instruction

3. The ××PR (priority level) values do not affect the operation of ××IF (interrupt request).

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CHAPTER 15 STANDBY FUNCTION

15.1 Standby Function and Configuration

15.1.1 Standby function

Table 15-1. Relationship Between Operation Clocks in Each Operation Status

Status

High-Speed System

Clock Oscillator

Internal Low-Speed Oscillator

Note 1 Note 2

CPU Clock After

Release

Prescaler Clock

oscillation

Supplied to Peripherals

<R>

MSTOP = MSTOP =

RSTOP =

1

MCM0 = 0 MCM0 = 1

Stopped

Operation

Mode

0

1

0

Reset

Stopped

Internal Low-

speed Oscillation

clock

STOP

HALT

Oscillating

Oscillating Stopped

Note 3

Note 4

Stopped

Oscillating

Internal

Low-

High-

speed

system

speed

Oscillation clock

clock

Notes 1. When “Cannot be stopped” is selected for the internal low-speed oscillator by a mask option (option byte

when using a flash memory version).

2. When “Can be stopped by software” is selected for the internal low-speed oscillator by a mask option

(option byte when using a flash memory version).

3. Operates using the CPU clock at STOP instruction execution.

4. Operates using the CPU clock at HALT instruction execution.

Caution The RSTOP setting is valid only when “Can be stopped by software” is set for the internal low-

speed oscillator by a mask option (option byte when using a flash memory version).

Remark MSTOP: Bit 7 of the main OSC control register (MOC)

RSTOP: Bit 0 of the internal low-speed oscillation mode register (RCM)

MCM0: Bit 0 of the main clock mode register (MCM)

The standby function is designed to reduce the operating current of the system. The following two modes are

available.

299

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(1) HALT mode

HALT instruction execution sets the HALT mode. The HALT mode is intended to stop the CPU operation clock. If

the high-speed system clock oscillator and internal low-speed oscillator are operating before the HALT mode is

set, oscillation of the high-speed system clock and internal low-speed oscillation clock continues. In this mode,

operating current is not decreased as much as in the STOP mode. However, the HALT mode is effective for

restarting operation immediately upon interrupt request generation and carrying out intermittent operations.

(2) STOP mode

STOP instruction execution sets the STOP mode. In the STOP mode, the high-speed system clock oscillator

stops, stopping the whole system, thereby considerably reducing the CPU operating current.

Because this mode can be cleared by an interrupt request, it enables intermittent operations to be carried out.

However, because a wait time is required to secure the oscillation stabilization time after the STOP mode is

released, select the HALT mode if it is necessary to start processing immediately upon interrupt request

generation.

In either of these two modes, all the contents of registers, flags, and data memory just before the standby mode is

set are held. The I/O port output latches and output buffer statuses are also held.

Cautions 1. When shifting to the STOP mode, be sure to stop the peripheral hardware operation before

executing STOP instruction.

2. The following sequence is recommended for operating current reduction of the A/D converter

when the standby function is used: First clear bit 7 (ADCS) of the A/D converter mode

register (ADM) to 0 to stop the A/D conversion operation, and then execute the HALT or STOP

instruction.

3. If the internal low-speed oscillator is operating before the STOP mode is set, oscillation of the

internal low-speed oscillation clock cannot be stopped in the STOP mode. However, when

the internal low-speed oscillation clock is used as the CPU clock, operation is stopped for

17/f^R(s) after STOP mode is released.

15.1.2 Registers controlling standby function

The standby function is controlled by the following two registers.

•

Oscillation stabilization time counter status register (OSTC)

Oscillation stabilization time select register (OSTS)

Remark For the registers that start, stop, or select the clock, see CHAPTER 5 CLOCK GENERATOR.

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(1) Oscillation stabilization time counter status register (OSTC)

This is the status register of the high-speed system clock oscillation stabilization time counter. If the internal low-

speed oscillation clock is used as the CPU clock, the high-speed system clock oscillation stabilization time can be

checked.

OSTC can be read by a 1-bit or 8-bit memory manipulation instruction.

Reset release (reset by RESET input, POC, LVI, clock monitor, or WDT), the STOP instruction or MSTOP (bit 7

of MOC register) = 1 clear OSTC to 00H.

Caution Waiting for the oscillation stabilization time is not required when the external RC oscillation

clock or internal high-speed oscillation clock is selected as the high-speed system clock by a

mask option (option byte when using a flash memory version). Therefore, the CPU clock can

be switched without reading the OSTC value.

Figure 15-1. Format of Oscillation Stabilization Time Counter Status Register (OSTC)

Address: FFA3H After reset: 00H

R

Symbol

OSTC

7

0

6

0

5

0

4

3

2

1

0

MOST11

MOST13

MOST14

MOST15

MOST16

MOST11

MOST13

MOST14

MOST15

MOST16

Oscillation stabilization time status

2¹¹/fXH min. (204.8 µs min.)

2¹³/fXH min. (819.2 µs min.)

2¹⁴/fXH min. (1.64 ms min.)

2¹⁵/fXH min. (3.28 ms min.)

2¹⁶/fXH min. (6.55 ms min.)

1

0

1

0

1

0

1

0

1

Cautions 1. After the above time has elapsed, the bits are set to 1 in order from MOST11 and

remain 1.

2. If the STOP mode is entered and then released while the internal low-speed

oscillation clock is being used as the CPU clock, set the oscillation stabilization

time as follows.

•

Desired OSTC oscillation stabilization time ≤ Oscillation stabilization time

set by OSTS

The high-speed system clock oscillation stabilization time counter counts only

during the oscillation stabilization time set by OSTS. Therefore, note that only

the statuses during the oscillation stabilization time set by OSTS are set to

OSTC after STOP mode has been released.

3. The wait time when STOP mode is released does not include the time after

STOP mode release until clock oscillation starts (“a” below) regardless of

whether STOP mode is released by RESET input or interrupt generation.

STOP mode release

X1 pin voltage

waveform

a

Remarks 1. Values in parentheses are reference values for operation with fXH = 10 MHz.

2. f^XH: High-speed system clock oscillation frequency

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(2) Oscillation stabilization time select register (OSTS)

This register is used to select the oscillation stabilization wait time of the high-speed system clock when STOP

mode is released. The wait time set by OSTS is valid only after the STOP mode is released while the high-speed

system clock is selected as the CPU clock. Check the oscillation stabilization time by OSTC after the STOP

mode is released when the internal low-speed oscillation clock is selected as the CPU clock.

OSTS can be set by an 8-bit memory manipulation instruction.

RESET input sets OSTS to 05H.

Figure 15-2. Format of Oscillation Stabilization Time Select Register (OSTS)

Address: FFA4H After reset: 05H R/W

Symbol

OSTS

7

0

6

0

5

0

4

0

3

0

2

1

0

OSTS2

OSTS1

OSTS0

OSTS2

OSTS1

OSTS0

Oscillation stabilization time selection

0

1

0

1

0

1

0

1

2¹¹/fXH (204.8 µs)

2¹³/fXH (819.2 µs)

2¹⁴/fXH (1.64 ms)

2¹⁵/fXH (3.28 ms)

2¹⁶/fXH (6.55 ms)

Setting prohibited

1

0

Other than above

<R>

Cautions 1. To set the STOP mode when the high-speed system clock is used as the CPU

clock , set OSTS before executing a STOP instruction.

2. Before setting OSTS, confirm with OSTC that the desired oscillation

stabilization time has elapsed.

3. If the STOP mode is entered and then released while the internal low-speed

oscillation clock is being used as the CPU clock, set the oscillation stabilization

time as follows.

•

Desired OSTC oscillation stabilization time ≤ Oscillation stabilization time

set by OSTS

The high-speed system clock oscillation stabilization time counter counts up to

the oscillation stabilization time set by OSTS. Therefore, note with caution that

only the status up to the oscillation stabilization time set by OSTS is set to

OSTC after the STOP mode is released.

4. The wait time when STOP mode is released does not include the time after

STOP mode release until clock oscillation starts (“a” below) regardless of

whether STOP mode is released by RESET input or interrupt generation.

STOP mode release

X1 pin voltage

waveform

a

Remarks 1. Values in parentheses are reference values for operation with f^XH= 10 MHz.

2. f^XH: High-speed system clock oscillation frequency

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CHAPTER 15 STANDBY FUNCTION

15.2 Standby Function Operation

15.2.1 HALT mode

(1) HALT mode

The HALT mode is set by executing the HALT instruction. The HALT mode can be set regardless of whether the

CPU clock before the setting was the high-speed system clock or internal low-speed oscillation clock.

The operating statuses in the HALT mode are shown below.

Table 15-2. Operating Statuses in HALT Mode

When HALT Instruction Is Executed While CPU When HALT Instruction Is Executed While CPU

HALT Mode Setting

Is Operating Using High-Speed System Clock

Is Operating Using Internal Low-Speed

Oscillation Clock

When Internal Low-

Speed Oscillation

Clock Continues

When Internal Low-

Speed Oscillation

Stopped^{Note 1}

When High-Speed

System Clock

When High-Speed

System Clock

Item

Oscillation Continues Oscillation Stopped

System clock

CPU

Clock supply to CPU stops.

Operation stopped

Port (output latch)

16-bit timer/event counter 00

8-bit timer 50

Holds the status before HALT mode is set

Operable

Operation not guaranteed

8-bit timer H0

8-bit timer H1

Operation not guaranteed when count clock

other than f^R/2⁷is selected

Watchdog Internal Low-speed

Operable

−

Operable

timer

oscillator cannot be

stopped^{Note 2}

Internal Low-speed

oscillator can be

stopped^{Note 2}

Operation stopped

A/D converter

Serial interface

Operable

Operation not guaranteed

UART6

CSI10

Operation not guaranteed when serial clock

other than external SCK10 is selected

Manchester code generator

Clock monitor

Operable

Operation not guaranteed

Operation stopped

Operable

Operation stopped

Power-on-clear function

Low-voltage detection function

External interrupt

Notes 1. When “Can be stopped by software” is selected for the internal low-speed oscillator by a mask option

(option byte if a flash memory version is used) and the internal low-speed oscillator is stopped by software

(for mask options and option bytes, see CHAPTER 20 MASK OPTIONS/OPTION BYTE).

2. For the internal low-speed oscillator, “Cannot be stopped” or “Can be stopped by software” can be

selected by a mask option (option byte if a flash memory version is used).

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CHAPTER 15 STANDBY FUNCTION

(2) HALT mode release

The HALT mode can be released by the following two sources.

(a) Release by unmasked interrupt request

When an unmasked interrupt request is generated, the HALT mode is released. If interrupt acknowledgment

is enabled, vectored interrupt servicing is carried out. If interrupt acknowledgment is disabled, the next

address instruction is executed.

Figure 15-3. HALT Mode Release by Interrupt Request Generation

Interrupt

request

HALT

instruction

Wait

Standby

release signal

Operating mode

HALT mode

Operating mode

Status of CPU

Oscillates

High-speed system clock or

Internal low-speed oscillation clock

Remarks 1. The broken lines indicate the case when the interrupt request which has released the standby

mode is acknowledged.

2. The wait time is as follows:

• When vectored interrupt servicing is carried out: 8 or 9 clocks

• When vectored interrupt servicing is not carried out: 2 or 3 clocks

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CHAPTER 15 STANDBY FUNCTION

(b) Release by reset signal (reset by RESET input, POC, LVI, clock monitor, or WDT )

When the reset signal is generated, HALT mode is released, and then, as in the case with a normal reset

operation, the program is executed after branching to the reset vector address.

<R>

Figure 15-4. HALT Mode Release by Reset Signal

(1) When high-speed system clock is used as CPU clock

HALT

instruction

Reset signal

Operation

stopped

Reset

period

Status of CPU

Operating mode

HALT mode

Oscillates

Operating mode

(17/f )

R

(High-speed

(Internal low-speed oscillation clock)

Oscillation

stopped

system clock)

Oscillates

High-speed

system clock

Oscillation stabilization time

(2¹¹/fXH to 2¹⁶/fXH

)

Note

Note Waiting for the oscillation stabilization time is not required when the external RC oscillation clock or

Internal high-speed oscillation clock is selected as the high-speed system clock by a mask option

(option byte when using a flash memory version). Therefore, the CPU clock can be switched without

reading the OSTC value.

(2) When Internal low-speed oscillation clock is used as CPU clock

HALT

instruction

Reset signal

Reset Operation

Operating mode

Status of CPU

HALT mode

Oscillates

Operating mode

period

stopped

(Internal low-speed

oscillation clock)

(17/f

R

)

(Internal low-speed oscillation clock)

Oscillation

stopped

Oscillates

Internal low-speed

oscillation clock

Remarks 1. f^XH: High-speed system clock oscillation frequency

2. f^R: Internal low-speed oscillation clock frequency

Table 15-3. Operation in Response to Interrupt Request in HALT Mode

Release Source

MK××

PR××

IE

0

1

0

×

1

×

ISP

×

Operation

Maskable interrupt

request

0

1

−

0

1

×

−

Next address instruction execution

Interrupt servicing execution

Next address instruction execution

×

1

0

1

Interrupt servicing execution

HALT mode held

×

Reset signal

×

Reset processing

×: Don’t care

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CHAPTER 15 STANDBY FUNCTION

15.2.2 STOP mode

(1) STOP mode setting and operating statuses

The STOP mode is set by executing the STOP instruction. It can be set regardless of whether the CPU clock

before the setting was the high-speed system clock or internal low-speed oscillation clock.

Caution Because the interrupt request signal is used to clear the standby mode, if there is an interrupt

source with the interrupt request flag set and the interrupt mask flag reset, the standby mode is

immediately cleared if set. Thus, the STOP mode is reset to the HALT mode immediately after

execution of the STOP instruction and the system returns to the operating mode as soon as the

wait time set using the oscillation stabilization time select register (OSTS) has elapsed.

The operating statuses in the STOP mode are shown below.

Table 15-4. Operating Statuses in STOP Mode

When STOP Instruction Is Executed While CPU

Is Operating Using High-Speed System Clock

When STOP Instruction Is Executed While

CPU Is Operating Using Internal Low-Speed

oscillation Clock

HALT Mode Setting

When Internal Low-

Speed Oscillation

clock Continues

When Internal Low-

Speed Oscillation

Clock Stopped^{Note 1}

Item

System clock

CPU

Only high-speed system clock oscillator oscillation stops. Clock supply to CPU stops.

Operation stopped

Port (output latch)

16-bit timer/event counter 00

8-bit timer 50

Holds the status before STOP mode is set

Operation stopped

8-bit timer H0

Operation stopped

8-bit timer H1

Operable^{Note 2}

Operation stopped

Operable^{Note 2}

Operable

Watch- Internal low-speed oscillator Operable

−

dog

cannot be stopped^{Note 3}

timer

Internal low-speed oscillator Operation stopped

can be stopped^{Note 3}

A/D converter

Serial interface

Operation stopped

UART6 Operation stopped

CSI10

Operable only when external SCK10 is selected as serial clock

Manchester code generator

Clock monitor

Operation stopped

Operable

Power-on-clear function

Low-voltage detection function

External interrupt

Operable

Notes 1. When “Can be stopped by software” is selected for the internal low-speed oscillator by a mask option

(option byte if a flash memory version is used) and the internal low-speed oscillator is stopped by software

(for mask options and option bytes, see CHAPTER 20 MASK OPTIONS/OPTION BYTE).

2. Operable only when f^R/2⁷is selected as count clock.

3. For the internal low-speed oscillator, “Cannot be stopped” or “Can be stopped by software” can be

selected by a mask option (option byte if a flash memory version is used).

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CHAPTER 15 STANDBY FUNCTION

(2) STOP mode release

Figure 15-5. Operation Timing When STOP Mode Is Released

STOP mode release

STOP mode

High-speed system

clock

Internal low-speed

oscillation clock

High-speed system

clock is used as CPU

clock when STOP

HALT status

(oscillation stabilization time set by OSTS)

High-speed system clock

instruction is executed

Internal low-speed

oscillation clock is

used as CPU clock

Internal low-speed

oscillation clock

when STOP instruction

is executed

Operation stopped

Clock switched

by software

(17/f )

R

The STOP mode can be released by the following two sources.

(a) Release by unmasked interrupt request

When an unmasked interrupt request is generated, the STOP mode is released. After the oscillation

stabilization time has elapsed, if interrupt acknowledgment is enabled, vectored interrupt servicing is carried

out. If interrupt acknowledgment is disabled, the next address instruction is executed.

Figure 15-6. STOP Mode Release by Interrupt Request Generation (1/2)

(1) When high-speed system clock is used as CPU clock

Wait

(set by OSTS)

STOP

instruction

Standby release signal

Oscillation stabilization

Status of CPU

Operating mode

wait status

STOP mode

(High-speed

system clock)

Oscillates

(High-speed

system clock)

(HALT mode status)

Oscillates

Oscillation stopped

High-speed system clock

Oscillation stabilization time (set by OSTS)

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CHAPTER 15 STANDBY FUNCTION

Figure 15-6. STOP Mode Release by Interrupt Request Generation (2/2)

(2) When internal low-speed oscillation clock is used as CPU clock

STOP

instruction

Standby release signal

Operation

stopped

Operating mode

STOP mode

Status of CPU

(Internal low-speed

oscillation clock)

(Internal low-speed oscillation clock)

(17/f )

R

Oscillates

Internal low-speed

oscillation clock

Remarks 1. The broken lines indicate the case when the interrupt request that has released the standby

mode is acknowledged.

2. f^R: Internal low-speed oscillation clock frequency

(b) Release by reset signal (reset by RESET input, POC, LVI, clock monitor, or WDT )

When the reset signal is generated, STOP mode is released and a reset operation is performed after the

oscillation stabilization time has elapsed.

<R>

Figure 15-7. STOP Mode Release by Reset Signal (1/2)

(1) When high-speed system clock is used as CPU clock

STOP

instruction

Reset signal

Reset

period

Operation

stopped

Status of CPU

Operating mode

STOP mode

Operating mode

(High-speed

(17/f

R

)

(Internal low-speed oscillation clock)

Oscillation

stopped

system clock)

Oscillation stopped

Oscillates

High-speed

system clock

Note

Oscillation stabilization time (2¹¹/fXH to 2¹⁶/fXH

)

Note Waiting for the oscillation stabilization time is not required when the external RC oscillation clock or

internal high-speed oscillation clock is selected as the high-speed system clock by a mask option

(option byte when using a flash memory version). Therefore, the CPU clock can be switched without

reading the OSTC value.

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CHAPTER 15 STANDBY FUNCTION

Figure 15-7. STOP Mode Release by Reset Signal (2/2)

(2) When internal low-speed oscillation clock is used as CPU clock

STOP

instruction

Reset signal

Reset

period

Operation

stopped

Status of CPU

Operating mode

(Internal low-speed

oscillation clock)

STOP mode

Oscillates

Operating mode

(17/f

R

)

(Intenal low-speed oscillation clock)

Oscillation

stopped

Oscillates

Internal low-speed

oscillation clock

Remarks 1. f^XH: High-speed system clock oscillation frequency

2. f^R: Internal low-speed oscillation clock frequency

Table 15-5. Operation in Response to Interrupt Request in STOP Mode

Release Source

MK××

PR××

IE

0

1

0

×

1

×

ISP

×

Operation

Maskable interrupt

request

0

1

−

0

1

×

−

Next address instruction execution

Interrupt servicing execution

Next address instruction execution

×

1

0

1

Interrupt servicing execution

STOP mode held

×

Reset signal

×

Reset processing

×: Don’t care

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CHAPTER 16 RESET FUNCTION

The following five operations are available to generate a reset signal.

(1) External reset input via RESET pin

(2) Internal reset by watchdog timer program loop detection

(3) Internal reset by clock monitor high-speed system clock oscillation stop detection

(4) Internal reset by comparison of supply voltage and detection voltage of power-on-clear (POC) circuit

(5) Internal reset by comparison of supply voltage and detection voltage of low-power-supply detector (LVI)

External and internal resets have no functional differences. In both cases, program execution starts at the address

at 0000H and 0001H when the reset signal is input.

A reset is applied when a low level is input to the RESET pin, the watchdog timer overflows, high-speed system

clock oscillation stop is detected by the clock monitor, or by POC and LVI circuit voltage detection, and each hardware

is set to the status shown in Table 16-1. Each pin is high impedance during reset input or during the oscillation

stabilization time just after reset release, except for P130, which is low-level output.

When a high level is input to the RESET pin, the reset is released and program execution starts using the internal

low-speed oscillation clock after the CPU clock operation has stopped for 17/f^R(s). Reset by the watchdog timer or

clock monitor source is automatically released after the reset, and program execution starts using the internal low-

speed oscillation clock after the CPU clock operation has stopped for 17/f^R(s) (see Figures 16-2 to 16-4). Reset by

POC and LVI circuit power supply detection is automatically released when V^DD> VPOC or VDD > VLVI after the reset,

and program execution starts using the internal low-speed oscillation clock after the CPU clock operation has stopped

for 17/f^R(s) (see CHAPTER 18 POWER-ON-CLEAR CIRCUIT and CHAPTER 19 LOW-VOLTAGE DETECTOR).

Cautions 1. For an external reset, input a low level for 10 µs or more to the RESET pin.

2. During reset input, the high-speed system clock and internal low-speed oscillation clock stop

oscillating.

3. When the STOP mode is released by a reset, the STOP mode contents are held during reset

input. However, the port pins become high-impedance, except for P130, which is set to low-

level output.

310

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CHAPTER 16 RESET FUNCTION

Figure 16-2. Timing of Reset by RESET Input

Internal low-speed

oscillation clock

High-speed

system clock

Operation stop

Normal operation

(Reset processing, internal low-speed oscillation clock)

Reset period

(Oscillation stop)

CPU clock

RESET

Normal operation

(17/f )

R

Internal

reset signal

Delay

Port pin

Hi-Z

(except P130)

Note

Port pin (P130)

Note Set P130 to high-level output by software.

Remark When reset is effected, P130 outputs a low level. If P130 is set to output a high level before reset is

effected, the output signal of P130 can be dummy-output as the reset signal to the CPU.

Figure 16-3. Timing of Reset Due to Watchdog Timer Overflow

Internal low-speed

oscillation clock

High-speed

system clock

Operation stop

Reset period

(Oscillation stop)

Normal operation

(Reset processing, internal low-speed oscillation clock)

CPU clock

Normal operation

(17/f )

R

Watchdog timer

overflow

Internal

reset signal

Hi-Z

Port pin

(except P130)

Note

Port pin (P130)

Note Set P130 to high-level output by software.

Caution A watchdog timer internal reset resets the watchdog timer.

Remark When reset is effected, P130 outputs a low level. If P130 is set to output a high level before reset is

effected, the output signal of P130 can be dummy-output as the reset signal to the CPU.

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CHAPTER 16 RESET FUNCTION

Figure 16-4. Timing of Reset in STOP Mode by RESET Input

Internal low-speed

oscillation clock

High-speed

system clock

STOP instruction execution

Operation stop

(17/fR)

Normal

operation

Normal operation

(Reset processing, internal low-speed oscillation clock)

Reset period

(Oscillation stop)

Stop status

CPU clock

RESET

(Oscillation stop)

Internal

reset signal

Delay

Hi-Z

Port pin

(except P130)

Port pin (P130)

Note

Note Set P130 to high-level output by software.

Remarks 1. When reset is effected, P130 outputs a low level. If P130 is set to output a high level before reset is

effected, the output signal of P130 can be dummy-output as the reset signal to the CPU.

2. For the reset timing of the power-on-clear circuit and low-voltage detector, see CHAPTER 18

POWER-ON-CLEAR CIRCUIT and CHAPTER 19 LOW-VOLTAGE DETECTOR.

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CHAPTER 16 RESET FUNCTION

Table 16-1. Hardware Statuses After Reset (1/2)

Hardware

Status After Reset

Program counter (PC)^{Note 1}

The contents of the

reset vector table

(0000H, 0001H) are

set.

Stack pointer (SP)

Program status word (PSW)

RAM

Undefined

02H

Data memory

Undefined^{Note 2}

General-purpose registers

Port registers (P0 to P2, P13) (output latches)

00H

(undefined only for P2)

Port mode registers (PM0, PM1)

FFH

00H

CFH

00H

05H

00H

0000H

00H

Pull-up resistor option registers (PU0, PU1)

Alternate-function pin switch register (PSEL)

Input switch control register (ISC)

Internal memory size switching register (IMS)

Processor clock control register (PCC)

Internal low-speed oscillation mode register (RCM)

Main clock mode register (MCM)

Main OSC control register (MOC)

Oscillation stabilization time select register (OSTS)

Oscillation stabilization time counter status register (OSTC)

16-bit timer/event counter 00

Timer counter 00 (TM00)

Capture/compare registers 000, 010 (CR000, CR010)

Mode control register 00 (TMC00)

Prescaler mode register 00 (PRM00)

Capture/compare control register 00 (CRC00)

Timer output control register 00 (TOC00)

Timer counter 50 (TM50)

8-bit timer 50

Compare register 50 (CR50)

Timer clock selection register 50 (TCL50)

Timer clock switch register (CSEL)

Mode control register 50 (TMC50)

8-bit timer/event counters H0, H1 Compare registers 00, 10, 01, 11 (CMP00, CMP10, CMP01, CMP11) 00H

Mode registers (TMHMD0, TMHMD1)

Timer clock switch register (CSEL)

Carrier control register 1 (TMCYC1)^{Note 3}

Mode register (WDTM)

00H

67H

9AH

Watchdog timer

Enable register (WDTE)

Notes 1. During reset input or oscillation stabilization time wait, only the PC contents among the hardware statuses

become undefined. All other hardware statuses remain unchanged after reset.

2. When a reset is executed in the standby mode, the pre-reset status is held even after reset.

3. 8-bit timer H1 only.

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CHAPTER 16 RESET FUNCTION

Table 16-1. Hardware Statuses After Reset (2/2)

Hardware

Status After Reset

A/D converter

Conversion result register (ADCR)

Undefined

00H

Mode register (ADM)

Analog input channel specification register (ADS)

Power-fail comparison mode register (PFM)

Power-fail comparison threshold register (PFT)

Receive buffer register 6 (RXB6)

00H

Serial interface UART6

FFH

Transmit buffer register 6 (TXB6)

FFH

Asynchronous serial interface operation mode register 6 (ASIM6)

01H

Asynchronous serial interface reception error status register 6 (ASIS6) 00H

Asynchronous serial interface transmission status register 6 (ASIF6)

Clock selection register 6 (CKSR6)

00H

Baud rate generator control register 6 (BRGC6)

Asynchronous serial interface control register 6 (ASICL6)

Transmit buffer register 10 (SOTB10)

Serial I/O shift register 10 (SIO10)

FFH

16H

Serial interface CSI10

Undefined

00H

Serial operation mode register 10 (CSIM10)

Serial clock selection register 10 (CSIC10)

Transmit buffer register (MC0TX)

00H

Manchester code generator

FFH

Transmit bit count specification register (MC0BIT)

Control register 0 (MC0CTL0)

07H

10H

Control register 1 (MC0CTL1)

00H

Control register 2 (MC0CTL2)

1FH

Status register (MC0STR)

00H

Clock monitor

Mode register (CLM)

00H

Reset function

Reset control flag register (RESF)

00H^Note

00H

Low-voltage detector

Low-voltage detection register (LVIM)

Low-voltage detection level selection register (LVIS)

Request flag registers 0L, 0H, 1L (IF0L, IF0H, IF1L)

Mask flag registers 0L, 0H, 1L (MK0L, MK0H, MK1L)

Interrupt

FFH

Priority specification flag registers 0L, 0H, 1L (PR0L, PR0H, PR1L) FFH

External interrupt rising edge enable register (EGP)

External interrupt falling edge enable register (EGN)

00H

Note These values vary depending on the reset source.

Reset Source

RESET Input

Cleared (00H)

Reset by POC

Cleared (00H)

Reset by WDT

Reset by CLM

Reset by LVI

Register

<R>

RESF WDTRF

CLMRF

LVIRF

Set (1)

Held

Set (1)

Held

Set (1)

Held

LVIM

Cleared (00H)

LVIS

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CHAPTER 16 RESET FUNCTION

16.1 Register for Confirming Reset Source

Many internal reset generation sources exist in the µPD780862 Subseries. The reset control flag register (RESF)

is used to store which source has generated the reset request.

RESF can be read by an 8-bit memory manipulation instruction.

RESET input, reset input by power-on-clear (POC) circuit, and reading RESF clear RESF to 00H.

Figure 16-5. Format of Reset Control Flag Register (RESF)

Address: FFACH After reset: 00H^Note

R

Symbol

RESF

7

0

6

0

5

0

4

3

0

2

0

1

0

WDTRF

CLMRF

LVIRF

WDTRF

Internal reset request by watchdog timer (WDT)

0

1

Internal reset request is not generated, or RESF is cleared.

Internal reset request is generated.

CLMRF

Internal reset request by clock monitor (CLM)

Internal reset request is not generated, or RESF is cleared.

Internal reset request is generated.

0

1

LVIRF

Internal reset request by low-voltage detector (LVI)

Internal reset request is not generated, or RESF is cleared.

Internal reset request is generated.

0

1

Note The value after reset varies depending on the reset source.

Caution Do not read data by a 1-bit memory manipulation instruction.

The status of RESF when a reset request is generated is shown in Table 16-2.

Table 16-2. RESF Status When Reset Request Is Generated

Reset Source

RESET Input

Cleared (0)

Reset by POC

Cleared (0)

Reset by WDT

Reset by CLM

Reset by LVI

Flag

WDTRF

CLMRF

LVIRF

Set (1)

Held

Set (1)

Held

Set (1)

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CHAPTER 17 CLOCK MONITOR

17.1 Functions of Clock Monitor

The clock monitor samples the high-speed system clock using the internal low-speed oscillation clock, and

generates an internal reset signal when the high-speed system clock is stopped.

When a reset signal is generated by the clock monitor, bit 1 (CLMRF) of the reset control flag register (RESF) is set

to 1. For details of RESF, refer to CHAPTER 16 RESET FUNCTION.

The clock monitor automatically stops under the following conditions.

•

Reset is released and during the oscillation stabilization time

In STOP mode and during the oscillation stabilization time

When the high-speed system clock is stopped by software (MSTOP = 1) and during the oscillation stabilization

time

•

When the internal low-speed oscillation clock is stopped

Remark MSTOP: Bit 7 of the main OSC control register (MOC)

17.2 Configuration of Clock Monitor

The clock monitor includes the following hardware.

Table 17-1. Configuration of Clock Monitor

Item

Configuration

Control register

Clock monitor mode register (CLM)

Figure 17-1. Block Diagram of Clock Monitor

Internal bus

Clock monitor

mode register (CLM)

CLME

High-speed system clock control signal

(MSTOP)

High-speed system clock stabilization status

(OSTC overflow)

Operation mode

controller

High-speed system

clock monitor circuit

Internal reset

signal

High-speed system clock

Internal low-speed oscillation clock

Remark MSTOP: Bit 7 of the main OSC control register (MOC)

OSTC: Oscillation stabilization time counter status register (OSTC)

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17.3 Registers Controlling Clock Monitor

The clock monitor is controlled by the clock monitor mode register (CLM).

(1) Clock monitor mode register (CLM)

This register sets the operation mode of the clock monitor.

This register can be set by a 1-bit or 8-bit memory manipulation instruction.

RESET input clears this register to 00H.

Figure 17-2. Format of Clock Monitor Mode Register (CLM)

Address: FFA9H After reset: 00H R/W

Symbol

CLM

7

0

6

0

5

0

4

0

3

0

2

0

1

0

<0>

CLME

Enables/disables clock monitor operation

CLME

0

1

Disables clock monitor operation

Enables clock monitor operation

Cautions 1. Once bit 0 (CLME) is set to 1, it cannot be cleared to 0 except by RESET input or the internal

reset signal.

2. If the reset signal is generated by the clock monitor, CLME is cleared to 0 and bit 1 (CLMRF)

of the reset control flag register (RESF) is set to 1.

3. The clock monitor stops operating during the oscillation stabilization time set by the

oscillation stabilization time select register (OSTS).

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CHAPTER 17 CLOCK MONITOR

17.4 Operation of Clock Monitor

This section explains the functions of the clock monitor. The monitor start and stop conditions are as follows.

Set bit 0 (CLME) of the clock monitor mode register (CLM) to operation enabled (1).

•

Reset is released and during the oscillation stabilization time

In STOP mode and during the oscillation stabilization time

When the high-speed system clock is stopped by software (MSTOP = 1) and during the oscillation

stabilization time

•

When the internal low-speed oscillation clock is stopped

Remark MSTOP: Bit 7 of the main OSC control register (MOC)

Table 17-2. Operation Status of Clock Monitor (When CLME = 1)

CPU Operation Clock Operation Mode High-Speed System Clock

Status

Internal Low-Speed

Clock Monitor Status

Stopped

Oscillation Clock Status

High-speed system

clock

STOP mode

Stopped

Oscillating

Stopped^Note

Oscillating

Stopped^Note

Oscillating

Stopped^Note

RESET input

Normal operation Oscillating

Operating

Stopped

mode

HALT mode

Internal low-speed

oscillation clock

STOP mode

RESET input

Stopped

Oscillating

Stopped

Normal operation Oscillating

Operating

Stopped

mode

Stopped

HALT mode

Note The internal low-speed oscillation clock is stopped only when the “Internal low-speed oscillator can be

stopped by software” is selected by a mask option (option byte if a flash memory version is used). If

“Internal low-speed oscillator cannot be stopped” is selected, the internal low-speed oscillation clock cannot

be stopped.

The clock monitor timing is as shown in Figure 17-3.

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CHAPTER 17 CLOCK MONITOR

Figure 17-3. Timing of Clock Monitor (1/4)

(1) When internal reset is executed by oscillation stop of high-speed system clock

4 clocks of internal low-speed oscillation clock

High-speed

system clock

Internal low-speed

oscillation clock

Internal reset signal

CLME

CLMRF

(2) Clock monitor status after RESET input

(CLME = 1 is set after RESET input and during high-speed system clock oscillation stabilization time)

Clock supply

stopped

Normal

operation

Normal operation (internal low-speed oscillation clock)

CPU operation

Reset

High-speed

system clock

Oscillation

stopped

Oscillation stabilization time

Internal low-speed

oscillation clock

Oscillation

stopped

17 clocks

RESET

Set to 1 by software

CLME

Clock monitor status

Monitoring

Monitoring stopped

Monitoring

Waiting for end

of oscillation

stabilization time

RESET input clears bit 0 (CLME) of the clock monitor mode register (CLM) to 0 and stops the clock monitor

operation. Even if CLME is set to 1 by software during the oscillation stabilization time (OSTS register reset value =

05H (2¹⁶/fXH)) of the high-speed system clock, monitoring is not performed until the oscillation stabilization time of the

high-speed system clock ends. Monitoring is automatically started at the end of the oscillation stabilization time.

Caution Waiting for the oscillation stabilization time is not required when the external RC oscillation

clock or internal high-speed oscillation clock is selected as the high-speed system clock by a

mask option (option byte when using a flash memory version). Therefore, the CPU clock can be

switched without reading the OSTC value. However, the clock monitor starts operation after the

oscillation stabilization time (OSTS register reset value = 05H (2¹⁶/fXH)) has elapsed.

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CHAPTER 17 CLOCK MONITOR

Figure 17-3. Timing of Clock Monitor (2/4)

(3) Clock monitor status after RESET input

(CLME = 1 is set after RESET input and at the end of high-speed system clock oscillation stabilization time)

Normal

operation

Clock supply

stopped

CPU operation

Reset

Normal operation (internal low-speed oscillation clock)

Oscillation stabilization time

High-speed

system clock

Internal low-speed

oscillation clock

17 clocks

RESET

Set to 1 by software

CLME

Clock monitor status

Monitoring

Monitoring stopped

Monitoring

RESET input clears bit 0 (CLME) of the clock monitor mode register (CLM) to 0 and stops the clock monitor

operation. When CLME is set to 1 by software at the end of the oscillation stabilization time (OSTS register reset

value = 05H (2¹⁶/fXH)) of the high-speed system clock, monitoring is started.

Caution Waiting for the oscillation stabilization time is not required when the external RC oscillation

clock or internal high-speed oscillation clock is selected as the high-speed system clock by a

mask option (option byte when using a flash memory version). Therefore, the CPU clock can be

switched without reading the OSTC value. However, the clock monitor starts operation after the

oscillation stabilization time (OSTS register reset value = 05H (2¹⁶/fXH)) has elapsed.

(4) Clock monitor status after STOP mode is released

(CLME = 1 is set when CPU clock operates on high-speed system clock and before entering STOP mode)

Normal

operation

Normal operation

Oscillation stabilization time

CPU operation

STOP

High-speed

system clock

(CPU clock)

Oscillation

stopped

Oscillation stabilization time

(set by OSTS register)

Internal low-speed

oscillation clock

CLME

Clock monitor status

Monitoring

Monitoring stopped

Monitoring

When bit 0 (CLME) of the clock monitor mode register (CLM) is set to 1 before entering STOP mode, monitoring

automatically starts at the end of the high-speed system clock oscillation stabilization time. Monitoring is stopped in

STOP mode and during the oscillation stabilization time.

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CHAPTER 17 CLOCK MONITOR

Figure 17-3. Timing of Clock Monitor (3/4)

(5) Clock monitor status after STOP mode is released

(CLME = 1 is set when CPU clock operates on internal low-speed oscillation clock and before entering

STOP mode)

Clock supply

stopped

Normal

operation

Normal operation

STOP

CPU operation

High-speed

system clock

Oscillation

stopped

Oscillation stabilization time

(set by OSTS register)

Internal low-speed

oscillation clock

(CPU clock)

17 clocks

CLME

Clock monitor status

Monitoring

stopped

Monitoring stopped

Monitoring

When bit 0 (CLME) of the clock monitor mode register (CLM) is set to 1 before entering STOP mode, monitoring

automatically starts at the end of the high-speed system clock oscillation stabilization time. Monitoring is stopped in

STOP mode and during the oscillation stabilization time.

(6) Clock monitor status after high-speed system clock oscillation is stopped by software

CPU operation

Normal operation (internal low-speed oscillation clock)

High-speed

system clock

Oscillation

stopped

Oscillation stabilization time

(time set by OSTS register)

Internal low-speed

oscillation clock

MSTOP

CLME

Clock monitor status

Monitoring

stopped

Monitoring stopped

Monitoring

When bit 0 (CLME) of the clock monitor mode register (CLM) is set to 1 before or while oscillation of the high-

speed system clock is stopped, monitoring automatically starts at the end of the high-speed system clock oscillation

stabilization time. Monitoring is stopped when oscillation of the high-speed system clock is stopped and during the

oscillation stabilization time.

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CHAPTER 17 CLOCK MONITOR

Figure 17-3. Timing of Clock Monitor (4/4)

(7) Clock monitor status after internal low-speed oscillation clock oscillation is stopped by software

Normal operation (high-speed system clock)

CPU operation

High-speed

system clock

Internal low-speed

oscillation clock

Oscillation stopped

RSTOP^Note

CLME

Clock monitor status

Monitoring

stopped

Monitoring

When bit 0 (CLME) of the clock monitor mode register (CLM) is set to 1 before or while oscillation of the internal

low-speed oscillation clock is stopped, monitoring automatically starts after the internal low-speed oscillation clock is

stopped. Monitoring is stopped when oscillation of the internal low-speed oscillation clock is stopped.

Note If it is specified by a mask option (option byte when using a flash memory version) that the internal low-

speed oscillator cannot be stopped, the setting of bit 0 (RSTOP) of the internal low-speed oscillation mode

register (RCM) is invalid. To set RSTOP, be sure to confirm that bit 1 (MCS) of the main clock mode

register (MCM) is 1.

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CHAPTER 18 POWER-ON-CLEAR CIRCUIT

18.1 Functions of Power-on-Clear Circuit

The power-on-clear circuit (POC) has the following functions.

•

Generates internal reset signal at power on.

Compares supply voltage (V^DD) and detection voltage (VPOC = 2.85 V 0.15 V), and generates internal reset

signal when V^DD< VPOC.

Cautions 1. If an internal reset signal is generated in the POC circuit, the reset control flag register

(RESF) is cleared to 00H.

2. Although the supply voltage is V^DD= 2.7 to 5.5 V, use the product in a voltage range of 3.0 to

5.5 V because the detection voltage (VPOC) of the POC circuit is 2.85 V 0.15 V.

Remark This product incorporates multiple hardware functions that generate an internal reset signal. A flag that

indicates the reset source is located in the reset control flag register (RESF) for when an internal reset

signal is generated by the watchdog timer (WDT), low-voltage-detector (LVI), or clock monitor. RESF is

not cleared to 00H and the flag is set to 1 when an internal reset signal is generated by WDT, LVI, or the

clock monitor. For details of RESF, refer to CHAPTER 16 RESET FUNCTION.

324

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CHAPTER 18 POWER-ON-CLEAR CIRCUIT

18.2 Configuration of Power-on-Clear Circuit

The block diagram of the power-on-clear circuit is shown in Figure 18-1.

Figure 18-1. Block Diagram of Power-on-Clear Circuit

V

DD

V

DD

+

Internal reset signal

−

Detection

voltage source

(V^POC

)

18.3 Operation of Power-on-Clear Circuit

In the power-on-clear circuit, the supply voltage (V^DD) and detection voltage (VPOC = 2.85 V 0.15 V) are compared,

and when VDD < VPOC, an internal reset signal is generated.

Figure 18-2. Timing of Internal Reset Signal Generation in Power-on-Clear Circuit

Supply voltage (V^DD

)

POC detection voltage

(V^POC

)

Time

Internal reset signal

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CHAPTER 18 POWER-ON-CLEAR CIRCUIT

18.4 Cautions for Power-on-Clear Circuit

In a system where the supply voltage (VDD) fluctuates for a certain period in the vicinity of the POC detection

voltage (V^POC= 2.85 V 0.15 V), the system may be repeatedly reset and released from the reset status. In this case,

the time from release of reset to the start of the operation of the microcontroller can be arbitrarily set by taking the

following action.

After releasing the reset signal, wait for the supply voltage fluctuation period of each system by means of a

software counter that uses a timer, and then initialize the ports.

Figure 18-3. Example of Software Processing After Release of Reset (1/2)

• If supply voltage fluctuation is 50 ms or less in vicinity of POC detection voltage

; The Internal low-speed oscillation clock is set as the CPU clock

when the reset signal is generated

Reset

Checking cause

of reset^{Note 2}

; The cause of reset (power-on-clear, WDT, LVI, or clock monitor)

can be identified by the RESF register.

Power-on-clear

; 8-bit timer H1 can operate with the internal low-speed oscillation clock.

Source: f^R(480 kHz (MAX.))/2⁷× compare value 200 = 53 ms

(f^R: Internal low-speed oscillation clock frequency)

Start timer

(set to 50 ms)

Check stabilization

of oscillation

; Check the stabilization of oscillation of the high-speed system clock

by using the OSTC register^{Note 3}

.

Note 1

; Change the CPU clock from the internal low-speed oscillation clock to

the high-speed system clock.

Change CPU clock

No

50 ms has passed?

(TMIFH1 = 1?)

; TMIFH1 = 1: Interrupt request is generated.

Yes

Initialization

processing

; Initialization of ports

Notes 1. If reset is generated again during this period, initialization processing is not started.

2. A flowchart is shown on the next page.

3. Waiting for the oscillation stabilization time is not required when the external RC oscillation clock or

internal high-speed oscillation clock is selected as the high-speed system clock by a mask option

(option byte when using a flash memory version). Therefore, the CPU clock can be switched without

reading the OSTC value.

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CHAPTER 18 POWER-ON-CLEAR CIRCUIT

Figure 18-3. Example of Software Processing After Release of Reset (2/2)

• Checking reset source

Check reset source

Yes

WDTRF of RESF

register = 1?

No

Reset processing by

watchdog timer

CLMRF of RESF

register = 1?

No

Reset processing by

clock monitor

LVIRF of RESF

register = 1?

No

Reset processing by

low-voltage detector

Power-on-clear/external

reset generated

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CHAPTER 19 LOW-VOLTAGE DETECTOR

19.1 Functions of Low-Voltage Detector

The low-voltage detector (LVI) has the following functions.

•

Compares supply voltage (V^DD) and detection voltage (VLVI), and generates an internal interrupt signal or

internal reset signal when VDD < VLVI.

•

Detection levels (seven levels) of supply voltage can be changed by software.

Interrupt or reset function can be selected by software.

Operable in STOP mode.

When the low-voltage detector is used to reset, bit 0 (LVIRF) of the reset control flag register (RESF) is set to 1 if

reset occurs. For details of RESF, refer to CHAPTER 16 RESET FUNCTION.

19.2 Configuration of Low-Voltage Detector

The block diagram of the low-voltage detector is shown below.

Figure 19-1. Block Diagram of Low-Voltage Detector

VDD

N-ch

Internal reset signal

+

−

INTLVI

Detection

voltage source

(V^LVI

)

3

LVIF

LVIMD

LVION

LVIS1 LVIS0

LVIS2

Low-voltage detection level

selection register (LVIS)

Low-voltage detection register

(LVIM)

Internal bus

328

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CHAPTER 19 LOW-VOLTAGE DETECTOR

19.3 Registers Controlling Low-Voltage Detector

The low-voltage detector is controlled by the following registers.

•

Low-voltage detection register (LVIM)

Low-voltage detection level selection register (LVIS)

(1) Low-voltage detection register (LVIM)

This register sets low-voltage detection and the operation mode.

This register can be set by a 1-bit or 8-bit memory manipulation instruction.

RESET input clears this register to 00H.

Figure 19-2. Format of Low-Voltage Detection Register (LVIM)

Address: FFBEH After reset: 00H R/W^{Note 1}

<7>

6

0

5

0

4

0

3

0

2

0

<1>

<0>

Symbol

LVIM

LVION

LVIMD

LVIF

LVION^{Notes 2, 3}

Enables low-voltage detection operation

0

1

Disables operation

Operation starts

LVIMD^{Note 2}

Low-voltage detection operation mode selection

Generates interrupt signal when supply voltage (VDD) < detection voltage (VLVI)

0

1

Generates internal reset signal when supply voltage (VDD) < detection voltage (VLVI)

LVIF^{Note 4}

Low-voltage detection flag

Supply voltage (VDD) > detection voltage (VLVI), or when operation is disabled

Supply voltage (VDD) < detection voltage (VLVI)

0

1

Notes 1. Bit 0 is a read-only bit.

2. LVION and LVIMD are cleared to 0 at a reset other than an LVI reset. These are not cleared

to 0 at an LVI reset.

3. When LVION is set to 1, operation of the comparator in the LVI circuit is started. Use

software to instigate a wait of at least 0.2 ms from when LVION is set to 1 until the voltage is

confirmed at LVIF.

4. The value of LVIF is output as the interrupt request signal INTLVI when LVION = 1 and

LVIMD = 0.

Cautions 1. To stop LVI, follow either of the procedures below.

• When using 8-bit memory manipulation instruction: Write 00H to LVIM.

• When using 1-bit memory manipulation instruction: Clear LVION to 0.

2. Be sure to clear bits 2 to 6 to 0.

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CHAPTER 19 LOW-VOLTAGE DETECTOR

(2) Low-voltage detection level selection register (LVIS)

This register selects the low-voltage detection level.

This register can be set by an 8-bit memory manipulation instruction.

RESET input clears this register to 00H.

Figure 19-3. Format of Low-Voltage Detection Level Selection Register (LVIS)

Address: FFBFH After reset: 00H R/W

7

0

6

0

5

0

4

0

3

0

2

1

0

Symbol

LVIS

LVIS2

LVIS1

LVIS0

LVIS2

LVIS1

LVIS0

Detection level

0

1

0

1

0

1

0

1

0

1

0

1

0

1

VLVI0 (4.3 V 0.2 V)

VLVI1 (4.1 V 0.2 V)

VLVI2 (3.9 V 0.2 V)

VLVI3 (3.7 V 0.2 V)

VLVI4 (3.5 V 0.2 V)

VLVI5 (3.3 V 0.15 V)

VLVI6 (3.1 V 0.15 V)

Setting prohibited

Caution Be sure to clear bits 3 to 7 to 0.

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CHAPTER 19 LOW-VOLTAGE DETECTOR

19.4 Operation of Low-Voltage Detector

The low-voltage detector can be used in the following two modes.

•

Used as reset

Compares the supply voltage (V^DD) and detection voltage (VLVI), and generates an internal reset signal when

V^DD< VLVI.

Used as interrupt

Compares the supply voltage (V^DD) and detection voltage (VLVI), and generates an interrupt signal (INTLVI)

when V^DD< VLVI.

The operation is set as follows.

(1) When used as reset

•

When starting operation

<1> Mask the LVI interrupt (LVIMK = 1).

<2> Set the detection voltage using bits 2 to 0 (LVIS2 to LVIS0) of the low-voltage detection level selection

register (LVIS).

<3> Set bit 7 (LVION) of LVIM to 1 (enables LVI operation).

<4> Use software to instigate a wait of at least 0.2 ms.

<5> Wait until it is checked that “supply voltage (V^DD) ≥ detection voltage (VLVI)” by bit 0 (LVIF) of LVIM.

<6> Set bit 1 (LVIMD) of LVIM to 1 (generates internal reset signal when supply voltage (V^DD) < detection

voltage (V^LVI)).

Figure 19-4 shows the timing of the internal reset signal generated by the low-voltage detector. The numbers in

this timing chart correspond to <1> to <6> above.

Cautions 1. <1> must always be executed. When LVIMK = 0, an interrupt may occur immediately

after the processing in <3>.

2. If supply voltage (V^DD) ≥ detection voltage (VLVI) when LVIM is set to 1, an internal reset

signal is not generated.

•

When stopping operation

Either of the following procedures must be executed.

•

When using 8-bit memory manipulation instruction: Write 00H to LVIM.

•

When using 1-bit memory manipulation instruction: Clear LVIMD to 0 and LVION to 0 in that order.

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CHAPTER 19 LOW-VOLTAGE DETECTOR

Figure 19-4. Timing of Low-Voltage Detector Internal Reset Signal Generation

Supply voltage (VDD

)

LVI detection voltage

(VLVI

)

POC detection voltage

(V^POC

)

Time

<2>

H

LVIMK flag

(set by software)

<1>^{Note 1}

LVION flag

(set by software)

Not cleared

<3>

Clear

<4> 0.2 ms or longer

LVIF flag

Clear

<5>

Note 2

LVIMD flag

(set by software)

Not cleared

<6>

LVIRF flag^{Note 3}

LVI reset signal

POC reset signal

Cleared by

software

Cleared by

software

Internal reset signal

Notes 1. The LVIMK flag is set to “1” by RESET input.

2. The LVIF flag may be set (1).

3. LVIRF is bit 0 of the reset control flag register (RESF). For details of RESF, see CHAPTER 16

RESET FUNCTION.

Remark <1> to <6> in Figure 19-4 above correspond to <1> to <6> in the description of “when starting operation”

in 19.4 (1) When used as reset.

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CHAPTER 19 LOW-VOLTAGE DETECTOR

(2) When used as interrupt

When starting operation

•

<1> Mask the LVI interrupt (LVIMK = 1).

<2> Set the detection voltage using bits 2 to 0 (LVIS2 to LVIS0) of the low-voltage detection level selection

register (LVIS).

<3> Set bit 7 (LVION) of LVIM to 1 (enables LVI operation).

<4> Use software to instigate a wait of at least 0.2 ms.

<5> Wait until it is checked that “supply voltage (V^DD) ≥ detection voltage (VLVI)” by bit 0 (LVIF) of LVIM.

<6> Clear the interrupt request flag of LVI (LVIIF) to 0.

<7> Release the interrupt mask flag of LVI (LVIMK).

<8> Execute the EI instruction (when vector interrupts are used).

Figure 19-5 shows the timing of the interrupt signal generated by the low-voltage detector. The numbers in this

timing chart correspond to <1> to <7> above.

•

When stopping operation

Either of the following procedures must be executed.

• When using 8-bit memory manipulation instruction: Write 00H to LVIM.

• When using 1-bit memory manipulation instruction: Clear LVION to 0.

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CHAPTER 19 LOW-VOLTAGE DETECTOR

Figure 19-5. Timing of Low-Voltage Detector Interrupt Signal Generation

Supply voltage (VDD

)

LVI detection voltage

(VLVI

)

POC detection voltage

(V^POC

)

Time

<2>

LVIMK flag

(set by software)

<1>^{Note 1}

<7> Cleared by software

LVION flag

(set by software)

<3>

<4> 0.2 ms or longer

<5>

LVIF flag

INTLVI

Note 2

LVIIF flag

<6>

Cleared by software

Note 2

Internal reset signal

Notes 1. The LVIMK flag is set to “1” by RESET input.

2. The LVIF and LVIIF flags may be set (1).

Remark <1> to <7> in Figure 19-5 above correspond to <1> to <7> in the description of “when starting operation”

in 19.4 (2) When used as interrupt.

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CHAPTER 19 LOW-VOLTAGE DETECTOR

19.5 Cautions for Low-Voltage Detector

In a system where the supply voltage (VDD) fluctuates for a certain period in the vicinity of the LVI detection voltage

(V^LVI), the operation is as follows depending on how the low-voltage detector is used.

(1) When used as reset

The system may be repeatedly reset and released from the reset status.

In this case, the time from release of reset to the start of the operation of the microcontroller can be arbitrarily set

by taking action (a) below.

(2) When used as interrupt

Interrupt requests may be frequently generated. Take action (b) below.

In this system, take the following actions.

(a) When used as reset

After releasing the reset signal, wait for the supply voltage fluctuation period of each system by means of a

software counter that uses a timer, and then initialize the ports.

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CHAPTER 19 LOW-VOLTAGE DETECTOR

Figure 19-6. Example of Software Processing After Release of Reset (1/2)

• If supply voltage fluctuation is 50 ms or less in vicinity of LVI detection voltage

; The internal low-speed osillation clock is set as the CPU clock when the

reset signal is generated

Reset

Checking cause

of reset^{Note 2}

; The cause of reset (power-on-clear, WDT, LVI, or clock monitor)

can be identified by the RESF register.

LVI

; 8-bit timer H1 can operate with the internal low-speed oscillation clock.

Start timer

(set to 50 ms)

Source: f

R

(480 kHz (MAX.))/2⁷× compare value 200 = 53 ms

(fR: Internal low-speed oscillation clock frequency)

Check stabilization

of oscillation

; Check the stabilization of oscillation of the high-speed system clock

by using the OSTC register^{Note 3}

Note 1

.

; Change the CPU clock from the the internal low-speed oscillation clock

to the high-speed system clock.

Change CPU clock

No

50 ms has passed?

(TMIFH1 = 1?)

; TMIFH1 = 1: Interrupt request is generated.

Yes

Initialization

processing

; Initialization of ports

Notes 1. If reset is generated again during this period, initialization processing is not started.

2. A flowchart is shown on the next page.

3. Waiting for the oscillation stabilization time is not required when the external RC oscillation clock or

internal high-speed oscillation clock is selected as the high-speed system clock by a mask option

(option byte when using a flash memory version). Therefore, the CPU clock can be switched without

reading the OSTC value.

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CHAPTER 19 LOW-VOLTAGE DETECTOR

Figure 19-6. Example of Software Processing After Release of Reset (2/2)

• Checking reset source

Check reset source

Yes

No

WDTRF of RESF

register = 1?

No

Reset processing by

watchdog timer

CLMRF of RESF

register = 1?

No

Reset processing by

clock monitor

LVIRF of RESF

register = 1?

Yes

Power-on-clear/external

reset generated

Reset processing by

low-voltage detector

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CHAPTER 19 LOW-VOLTAGE DETECTOR

(b) When used as interrupt

Check that “supply voltage (V^DD) ≥ detection voltage (VLVI)” in the servicing routine of the LVI interrupt by using bit

0 (LVIF) of the low-voltage detection register (LVIM). Clear bit 0 (LVIIF) of interrupt request flag register 0L (IF0L)

to 0 and enable interrupts (EI).

In a system where the supply voltage fluctuation period is long in the vicinity of the LVI detection voltage, wait for

the supply voltage fluctuation period, check that “supply voltage (V^DD) ≥ detection voltage (VLVI)” with the LVIF flag,

and then enable interrupts (EI).

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CHAPTER 20 MASK OPTIONS/OPTION BYTE

20.1 Mask Options (Mask ROM Versions)

Mask ROM versions have the following mask options.

1. High-speed system clock oscillation selection

• Crystal/ceramic oscillation

• External RC oscillation

• Internal high-speed oscillation

2. Internal low-speed oscillator oscillation

• Cannot be stopped^Note

• Can be stopped by software

Note If “Internal low-speed oscillator cannot be stopped” is selected, the source clock of the watchdog timer is

fixed to the internal low-speed oscillator clock, and it cannot be changed.

Caution Select crystal/ceramic oscillation or external RC oscillation when using an external clock.

339

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CHAPTER 20 MASK OPTIONS/OPTION BYTE

20.2 Option Bytes (Flash Memory Versions)

In the flash memory versions, the functions equivalent to the mask options of the mask ROM versions can be

realized by setting using option bytes.

Option bytes are prepared at address 0080H in the flash memory.

When using flash memory version products, be sure to set the mask option information to the option bytes.

Figure 20-1. Allocation of Option Bytes (Flash Memory Versions)

3FFFH

Flash memory

(16384 × 8 bits)

0080H

Option bytes

–

OSCSEL1 OSCSEL0 LSROSC

0000H

Figure 20-2. Format of Option Bytes (Flash Memory Versions)

Address: 0080H

7

0

6

0

5

0

4

0

3

0

2

1

0

OSCSEL1

OSCSEL0

LSROSC

OSCSEL1

OSCSEL0

High-speed system clock oscillation selection

0

1

0

1

×

Crystal/ceramic oscillation

External RC oscillation

Internal high-speed oscillation

LSROSC

Internal low-speed oscillator oscillation

0

1

Can be stopped by software

Cannot be stopped

Caution Select crystal/ceramic oscillation or external RC oscillation when using an external clock.

Remark An example of software coding for setting the option bytes is shown below.

OPT

CSEG

AT 0080H

03H

OPTION: DB

; Set to option byte (external RC oscillation used/internal low-speed

oscillator cannot be stopped)

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CHAPTER 21 FLASH MEMORY

The µPD78F0862 and 78F0862A are provided as the flash memory version of the µPD780862 Subseries.

The µPD78F0862 and 78F0862A replace the internal mask ROM of the µPD780862 with flash memory to which a

program can be written, erased, and overwritten while mounted on the board. Table 21-1 lists the differences

between the µPD78F0862, 78F0862A and the mask ROM versions.

Table 21-1. Differences Between µPD78F0862, 78F0862A and Mask ROM Versions

Item

µPD78F0862, 78F0862A

Flash memory

Mask ROM Versions

Mask ROM

Internal ROM configuration

Internal ROM capacity

16 KB^Note

µPD780861: 8 KB

µPD780862: 16 KB

Internal high-speed RAM capacity

768 bytes^Note

µPD780861: 512 bytes

µPD780862: 768 bytes

IC pin

None

Available

None

FLMD0, FLMD1 pins

Electrical specifications

Available

Refer to the description of electrical specifications.

Note The same capacity as the mask ROM versions can be specified by means of the internal memory size

switching register (IMS).

Cautions 1. There are differences in noise immunity and noise radiation between the flash memory and

mask ROM versions. When pre-producing an application set with the flash memory version

and then mass-producing it with the mask ROM version, be sure to conduct sufficient

evaluations for the commercial samples (not engineering samples) of the mask ROM

versions.

<R>

2. µPD78F0862 and 78F0862A differ only in the flash memory characteristics. For details,

refer to “Flash Memory Programming Characteristics” in the chapter of the electrical

specifications.

341

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CHAPTER 21 FLASH MEMORY

21.1 Internal Memory Size Switching Register

The µPD78F0862 and 78F0862A allow users to select the internal memory capacity using the internal memory

size switching register (IMS) so that the same memory map as that of the mask ROM versions with a different internal

memory capacity can be achieved.

IMS is set by an 8-bit memory manipulation instruction.

RESET input sets IMS to CFH.

Caution The initial value of IMS is “setting prohibited (CFH)”. Be sure to set the value of the relevant

mask ROM version at initialization.

Figure 21-1. Format of Internal Memory Size Switching Register (IMS)

Address: FFF0H After reset: CFH R/W

Symbol

IMS

7

6

5

4

0

3

2

1

0

RAM2

RAM1

RAM0

ROM3

ROM2

ROM1

ROM0

RAM2

RAM1

RAM0

Internal high-speed RAM capacity selection

0

768 bytes

512 bytes

1

Other than above

Setting prohibited

ROM3

ROM2

ROM1

ROM0

Internal ROM capacity selection

0

1

0

8 KB

16 KB

Other than above

Setting prohibited

The IMS settings required to obtain the same memory map as mask ROM versions are shown in Table 21-2.

Table 21-2. Internal Memory Size Switching Register Settings

Target Mask ROM Versions

µPD780861

IMS Setting

42H

µPD780862

04H

Caution When using a mask ROM version, be sure to set the value indicated in Table 21-2 to IMS.

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CHAPTER 21 FLASH MEMORY

21.2 Writing with Flash Programmer

Data can be written to the flash memory on-board or off-board, by using a dedicated flash programmer (FlashPro

4).

(1) On-board programming

The contents of the flash memory can be rewritten after the µPD78F0862 and 78F0862A have been mounted on

the target system. The connectors that connect the dedicated flash programmer must be mounted on the target

system.

(2) Off-board programming

Data can be written to the flash memory with a dedicated program adapter (FA series) before the µPD78F0862

and 78F0862A are mounted on the target system.

Remark The FA series is a product of Naito Densei Machida Mfg. Co., Ltd.

Table 21-3. Wiring Between µPD78F0862, 78F0862A and Dedicated Flash Programmer

Pin Configuration of Dedicated Flash Programmer

With CSI10 + HS

With CSI10

Pin Name

With UART6

Pin Name

Signal Name

SI/RxD

I/O

Input

Pin Function

Receive signal

Pin Name

Pin No.

11

Pin No.

12

SO10/P12/TOH1/

(INTP3)

11

SO10/P12/TOH1/

(INTP3)

TxD6/P13/INTP1/

(TOH1)/(MCGO)

SO/TxD

SCK

Output

Transmit signal

Transfer clock

SI10/P11/INTP3

10

SI10/P11/INTP3

10

RxD6/P14/<INTP0> 13

SCK10/P10/(INTP1) 9

Not required

Not

required

CLK

Output

Clock to µPD78F0862,

X1[CL1]

2

X1[CL1]

2

X1[CL1]

2

X2[CL2]/P02^Note

3

X2[CL2]/P02^Note

3

X2[CL2]/P02^Note

3

78F0862A

/RESET

FLMD0

FLMD1

Output

Reset signal

Mode signal

RESET

6

RESET

6

RESET

6

FLMD0

4

FLMD0

4

FLMD0

4

HS/P15/TOH0/

FLMD1

14

HS/P15/TOH0/

FLMD1

14

HS/P15/TOH0/

FLMD1

14

H/S

Input

I/O

Handshake signal for CSI10 HS/P15/TOH0/

+ HS signal FLMD1

DD voltage generation

14

Not required

Not

Not required

Not

required

VDD

V

VDD

5

V

DD

5

V

DD

5

AV^REF

20

1

AVREF

20

1

AVREF

20

1

GND

−

Ground

VSS

Note When using the clock out of the flash programmer, connect CLK of the programmer to X1, and connect its

inverse signal to X2.

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CHAPTER 21 FLASH MEMORY

Examples of the recommended connection when using the adapter for flash memory writing are shown below.

Figure 21-2. Example of Wiring Adapter for Flash Memory Writing in 3-Wire Serial I/O (CSI10) Mode

VDD (3.0 to 5.5 V)

GND

1

2

3

4

5

6

7

8

9

10

20

19

18

17

16

15

14

13

12

11

GND

VDD

VDD2

FRASHWRITER

INTERFACE

SI SO SCK CLKOUT RESET FLMD0

FLMD1 HS

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CHAPTER 21 FLASH MEMORY

Figure 21-3. Example of Wiring Adapter for Flash Memory Writing in 3-Wire Serial I/O (CSI10 + HS) Mode

VDD (3.0 to 5.5 V)

GND

1

20

19

18

17

16

15

14

13

12

11

2

3

4

5

6

7

8

9

10

GND

VDD

VDD2

FRASHWRITER

INTERFACE

SI SO SCK CLKOUT RESET FLMD0

FLMD1 HS

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CHAPTER 21 FLASH MEMORY

Figure 21-4. Example of Wiring Adapter for Flash Memory Writing in UART (UART6) Mode

VDD (3.0 to 5.5 V)

GND

1

2

3

4

5

6

7

8

9

10

20

19

18

17

16

15

14

13

12

11

GND

VDD

VDD2

FRASHWRITER

INTERFACE

SI SO SCK CLKOUT RESET FLMD0

FLMD1 HS

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CHAPTER 21 FLASH MEMORY

21.3 Programming Environment

The environment required for writing a program to the flash memory of the µPD78F0862 and 78F0862A illustrated

below.

Figure 21-5. Environment for Writing Program to Flash Memory

FLMD0

FLMD1

Axxxx

RS-232C

Bxxxxx

VDD

Cxxxxxx

A

TVE

(F^Sl^Tash Pro4)

PG-FP4

VSS

USB

RESET

PD78F0862,

78F0862A

µ

Dedicated flash

programmer

CSI10/UART6

Host machine

A host machine that controls the dedicated flash programmer is necessary.

CSI10 or UART6 is used for manipulation such as writing and erasing to interface between the dedicated flash

programmer and the µPD78F0862, 78F0862A. To write the flash memory off-board, a dedicated program adapter (FA

series) is necessary.

21.4 Communication Mode

Communication between the dedicated flash programmer and the µPD78F0862, 78F0862A are established by

serial communication via CSI10 or UART6 of the µPD78F0862 and 78F0862A.

(1) CSI10

<R>

Transfer rate: 2.4 kHz to 2.5 MHz

Figure 21-6. Communication with Dedicated Flash Programmer (CSI10)

FLMD0

FLMD1

V^DD

FLMD0

FLMD1

V^DD/AVREF

Axxxx

GND

/RESET

SI/RxD

SO/TxD

SCK

VSS

Bxxxxx

Cxxxxxx

A

TVE

(F^Sl^Tash Pro4)

PG-FP4

RESET

SO10

SI10

PD78F0862,

78F0862A

Dedicated flash

programmer

µ

SCK10

X1

CLK

X2

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CHAPTER 21 FLASH MEMORY

(2) CSI communication mode supporting handshake

<R>

Transfer rate: 2.4 kHz to 2.5 MHz

Figure 21-7. Communication with Dedicated Flash Programmer (CSI10 + HS)

FLMD0

FLMD1

H/S

FLMD0

FLMD1/HS

Axxxx

V

DD

V

DD/AVREF

SS

Bxxxxx

Cxxxxxx

A

TVE

(F^Sl^Tash Pro4)

PG-FP4

GND

/RESET

SI/RxD

SO/TxD

SCK

V

RESET

SO10

SI10

SCK10

X1

PD78F0862,

78F0862A

Dedicated flash

programmer

µ

CLK

X2

(3) UART6

Transfer rate: 9600, 19200, 31250, 38400, 76800 and 153600^Notebps

<R>

Figure 21-8. Communication with Dedicated Flash Programmer (UART6)

FLMD0

FLMD1

FLMD0

FLMD1

V

DD

V

DD/AVREF

SS

Axxxx

Bxxxxx

Cxxxxxx

A

TVE

GND

/RESET

SI/RxD

SO/TxD

CLK

V

(F^Sl^Tash Pro4)

PG-FP4

RESET

TxD6

µ

PD78F0862,

78F0862A

Dedicated flash

programmer

RxD6

X1

X2

Note When peripheral hardware clock frequency is 2.5 MHz or less, 153600 bps cannot be selected.

<R>

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CHAPTER 21 FLASH MEMORY

If FlashPro4 is used as the dedicated flash programmer, FlashPro4 generates the following signal for the

µPD78F0862 and 78F0862A. For details, refer to the FlashPro4 Manual.

Table 21-4. Pin Connection

FlashPro4

µPD78F0862,

Connection

78F0862A

Signal Name

FLMD0

FLMD1

VDD

I/O

Output

Pin Function

Pin Name

CSI10 UART6

Mode signal

FLMD0

Output

I/O

FLMD1

VDD, AVREF

VSS

VDD voltage generation

Ground

GND

−

CLK

Output

Input

Clock output to µPD78F0862

Reset signal

X1, X2^Note

RESET

SO10/TxD6

SI10/RxD6

SCK10

{

/RESET

SI/RxD

SO/TxD

SCK

Receive signal

Output

Input

Transmit signal

Transfer clock

×

H/S

Handshake signal

HS

Note When using the clock out of the flash programmer, connect CLK of the programmer to X1, and connect its

inverse signal to X2.

Remark

: Be sure to connect the pin.

{: The pin does not have to be connected if the signal is generated on the target board.

×: The pin does not have to be connected.

: In handshake mode

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CHAPTER 21 FLASH MEMORY

21.5 Handling of Pins on Board

To write the flash memory on-board, connectors that connect the dedicated flash programmer must be provided on

the target system. First provide a function that selects the normal operation mode or flash memory programming

mode on the board.

When the flash memory programming mode is set, all the pins not used for programming the flash memory are in

the same status as immediately after reset. Therefore, if the external device does not recognize the state immediately

after reset, the pins must be handled as described below.

21.5.1 FLMD0 pin

In the normal operation mode, 0 V is input to the FLMD0 pin. In the flash memory programming mode, the V^DD

write voltage is supplied to the FLMD0 pin. The following shows an example of the connection of the FLMD0 pin.

Figure 21-9. FLMD0 Pin Connection Example

µ

PD78F0862,

78F0862A

Dedicated flash programmer connection pin

FLMD0

21.5.2 FLMD1 pin

When 0 V is input to the FLMD0 pin, the FLMD1 pin does not function. When V^DDis supplied to the FLMD0 pin,

the flash memory programming mode is entered, so the FLMD1 pin must be the same voltage as VSS. An FLMD1 pin

connection example is shown below.

Figure 21-10. FLMD1 Pin Connection Example

µ

PD78F0862,

78F0862A

Dedicated flash programmer

connection pin

Signal collision

FLMD1

Other device

Output pin

If the VDD signal is input to the FLMD1 pin from another device during

on-board writing and immediately after reset, isolate this signal.

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CHAPTER 21 FLASH MEMORY

21.5.3 Serial interface pins

The pins used by each serial interface are listed below.

Table 21-5. Pins Used by Each Serial Interface

Serial Interface

Pins Used

SO10, SI10, SCK10

SO10, SI10, SCK10, HS

TxD6, RxD6

CSI10

CSI10 + HS

UART6

To connect the dedicated flash programmer to the pins of a serial interface that is connected to another device on

the board, care must be exercised so that signals do not collide or that the other device does not malfunction.

(1) Signal collision

If the dedicated flash programmer (output) is connected to a pin (input) of a serial interface connected to another

device (output), signal collision takes place. To avoid this collision, either isolate the connection with the other

device, or make the other device go into an output high-impedance state.

Figure 21-11. Signal Collision (Input Pin of Serial Interface)

µ

PD78F0862,

78F0862A

Dedicated flash programmer

connection pin

Signal collision

Input pin

Other device

Output pin

In the flash memory programming mode, the signal output by the device

collides with the signal sent from the dedicated flash programmer.

Therefore, isolate the signal of the other device.

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CHAPTER 21 FLASH MEMORY

(2) Malfunction of other device

If the dedicated flash programmer (output or input) is connected to a pin (input or output) of a serial interface

connected to another device (input), a signal may be output to the other device, causing the device to

malfunction. To avoid this malfunction, isolate the connection with the other device.

Figure 21-12. Malfunction of Other Device

PD78F0862,

78F0862A

µ

Dedicated flash programmer

connection pin

Other device

Input pin

µ

If the signal output by the PD78F0862 and 78F0862A in the flash memory

programming mode affects the other device, isolate the signal of the other

device.

PD78F0862,

µ

78F0862A

Dedicated flash programmer

connection pin

Other device

Input pin

If the signal output by the dedicated flash programmer in the flash memory

programming mode affects the other device, isolate the signal of the other

device.

21.5.4 RESET pin

If the reset signal of the dedicated flash programmer is connected to the RESET pin that is connected to the reset

signal generator on the board, signal collision takes place. To prevent this collision, isolate the connection with the

reset signal generator.

If the reset signal is input from the user system while the flash memory programming mode is set, the flash

memory will not be correctly programmed. Do not input any signal other than the reset signal of the dedicated flash

programmer.

Figure 21-13. Signal Collision (RESET Pin)

PD78F0862,

78F0862A

µ

Dedicated flash programmer

connection pin

Signal collision

RESET

Reset signal generator

Output pin

In the flash memory programming mode, the signal output by the reset

signal generator collides with the signal output by the dedicated flash

programmer. Therefore, isolate the signal of the reset signal generator.

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CHAPTER 21 FLASH MEMORY

21.5.5 Port pins

When the flash memory programming mode is set, all the pins not used for flash memory programming enter the

same status as that immediately after reset. If external devices connected to the ports do not recognize the port

status immediately after reset, the port pin must be connected to V^DDor VSS via a resistor.

21.5.6 Other signal pins

Connect X1 and X2 in the same status as in the normal operation mode when using the on-board clock.

To input the operating clock from the programmer, however, connect the clock out of the programmer to X1, and its

inverse signal to X2.

21.5.7 Power supply

To use the power supply output of the flash programmer, connect the V^DDpin to VDD of the flash programmer, and

the V^SSpin to VSS of the flash programmer.

To use the on-board power supply, connect in compliance with the normal operation mode.

Supply the same other power supply (AV^REF) as those in the normal operation mode.

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CHAPTER 21 FLASH MEMORY

21.6 Programming Method

21.6.1 Controlling flash memory

The following figure illustrates the procedure to manipulate the flash memory.

Figure 21-14. Flash Memory Manipulation Procedure

Start

Flash memory programming

FLMD0 pulse supply

mode is set

Selecting communication mode

Manipulate flash memory

No

End?

Yes

End

21.6.2 Flash memory programming mode

To rewrite the contents of the flash memory by using the dedicated flash programmer, set the µPD78F0862 and

78F0862A in the flash memory programming mode. To set the mode, set the FLMD0 pin to VDD and clear the reset

signal.

Change the mode by using a jumper when writing the flash memory on-board.

Figure 21-15. Flash Memory Programming Mode

VDD

RESET

0 V

FLMD0 pulse

V

DD

FLMD0

FLMD1

0 V

V

DD

Hi-Z

Flash memory programming mode

0 V

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CHAPTER 21 FLASH MEMORY

Table 21-6. Relationship of Operation Mode of FLMD0 and FLMD1 Pins

FLMD0

0

FLMD1

Operation Mode

Normal operation mode

×

0

VDD

Flash memory programming mode

Setting prohibited

VDD

21.6.3 Selecting communication mode

In the µPD78F0862 and 78F0862A, a communication mode is selected by inputting pulses (up to 11 pulses) to the

FLMD0 pin after the flash memory programming mode is entered. These FLMD0 pulses are generated by the

dedicated flash programmer.

The following table shows the relationship between the number of pulses and communication modes.

Table 21-7. Communication Modes

<R>

Standard Setting^{Note 1}

Communication Mode

Pins Used

Number of

FLMD0

Port

Speed

On Target

Frequency

Multiply Rate

Pulses

UART

UART-ch0

9600, 19200, 31250,

38400, 76800, and

153600 bps^{Notes 3, 4}

Optional

2 M to 10 MHz

Note 2

1.0

TxD6, RxD6

0

(UART6)

3-wire serial I/O

(CSI10)

SIO-ch0

SIO-H/S

2.4 kHz to 2.5 MHz

SO10, SI10,

SCK10

8

3-wire serial I/O with

handshake supported

(CSI10 + HS)

2.4 kHz to 2.5 MHz

SO10, SI10,

SCK10,

11

HS/P15

Notes 1. Selection items for Standard settings on FlashPro4.

2. The possible setting range differs depending on the voltage. For details, refer to the chapters of electrical

specifications.

3. When peripheral hardware clock frequency is 2.5 MHz or less, 153600 bps cannot be selected.

4. Because factors other than the baud rate error, such as the signal waveform slew, also affect UART

communication, thoroughly evaluate the slew as well as the baud rate error.

Caution When UART6 is selected, the receive clock is calculated based on the reset command sent from the

dedicated flash programmer after the FLMD0 pulse has been received.

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CHAPTER 21 FLASH MEMORY

21.6.4 Communication commands

The µPD78F0862 and 78F0862A communicate with the dedicated flash programmer by using commands. The

signals sent from the flash programmer to the µPD78F0862 and 78F0862A are called commands, and the commands

sent from the µPD78F0862 and 78F0862A to the dedicated flash programmer are called response commands.

Figure 21-16. Communication Commands

Command

Axxxx

Bxxxxx

Cxxxxxx

(F^Sl^Tash Pro4)

A

TVE

PG-FP4

Response command

PD78F0862,

78F0862A

µ

Dedicated flash

programmer

The flash memory control commands of the µPD78F0862 and 78F0862 are listed in the table below. All these

commands are issued from the programmer and the µPD78F0862 and 78F0862A perform processing corresponding

to the respective commands.

Table 21-8. Flash Memory Control Commands

Classification

Command Name

Batch verify command

Function

Verify

Erase

Compares the contents of the entire memory

with the input data.

Batch erase command

Erases the contents of the entire memory.

Blank check

Data write

Batch blank check command

High-speed write command

Checks the erasure status of the entire memory.

Writes data by specifying the write address and

number of bytes to be written, and executes a

verify check.

Successive write command

Writes data from the address following that of

the high-speed write command executed

immediately before, and executes a verify

check.

System setting, control

Status read command

Obtains the operation status.

Oscillation frequency setting command

Erase time setting command

Write time setting command

Baud rate setting command

Silicon signature command

Reset command

Sets the oscillation frequency.

Sets the erase time for batch erase.

Sets the write time for writing data.

Sets the baud rate when UART is used.

Reads the silicon signature information.

Escapes from each status.

The µPD78F0862 and 78F0862A return a response command for the command issued by the dedicated flash

programmer. The response commands sent from the µPD78F0862 and 78F0862A are listed below.

Table 21-9. Response Commands

Command Name

Function

ACK

NAK

Acknowledges command/data.

Acknowledges illegal command/data.

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CHAPTER 22 INSTRUCTION SET

This chapter lists each instruction set of the µPD780862 Subseries in table form. For details of each operation and

operation code, refer to the separate document 78K/0 Series Instructions User’s Manual (U12326E).

22.1 Conventions Used in Operation List

22.1.1 Operand identifiers and specification methods

Operands are written in the “Operand” column of each instruction in accordance with the specification method of

the instruction operand identifier (refer to the assembler specifications for details). When there are two or more

methods, select one of them. Uppercase letters and the symbols #, !, $ and [ ] are keywords and must be written as

they are. Each symbol has the following meaning.

•

#: Immediate data specification

!: Absolute address specification

$: Relative address specification

[ ]: Indirect address specification

In the case of immediate data, describe an appropriate numeric value or a label. When using a label, be sure to

write the #, !, $, and [ ] symbols.

For operand register identifiers r and rp, either function names (X, A, C, etc.) or absolute names (names in

parentheses in the table below, R0, R1, R2, etc.) can be used for specification.

Table 22-1. Operand Identifiers and Specification Methods

Identifier

Specification Method

r

X (R0), A (R1), C (R2), B (R3), E (R4), D (R5), L (R6), H (R7)

AX (RP0), BC (RP1), DE (RP2), HL (RP3)

rp

sfr

sfrp

Special function register symbol^Note

Special function register symbol (16-bit manipulatable register even addresses only)^Note

saddr

FE20H to FF1FH Immediate data or labels

saddrp

FE20H to FF1FH Immediate data or labels (even address only)

addr16

0000H to FFFFH Immediate data or labels

(Only even addresses for 16-bit data transfer instructions)

0800H to 0FFFH Immediate data or labels

addr11

addr5

0040H to 007FH Immediate data or labels (even address only)

word

byte

bit

16-bit immediate data or label

8-bit immediate data or label

3-bit immediate data or label

RBn

RB0 to RB3

Note Addresses from FFD0H to FFDFH cannot be accessed with these operands.

Remark For special function register symbols, refer to Table 3-5 Special Function Register List.

357

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CHAPTER 22 INSTRUCTION SET

22.1.2 Description of operation column

A:

A register; 8-bit accumulator

X register

X:

B:

B register

C:

C register

D:

D register

E:

E register

H:

H register

L:

L register

AX:

BC:

DE:

HL:

PC:

SP:

AX register pair; 16-bit accumulator

BC register pair

DE register pair

HL register pair

Program counter

Stack pointer

PSW: Program status word

CY:

AC:

Z:

Carry flag

Auxiliary carry flag

Zero flag

RBS:

IE:

Register bank select flag

Interrupt request enable flag

( ):

Memory contents indicated by address or register contents in parentheses

X^H, XL: Higher 8 bits and lower 8 bits of 16-bit register

∧:

∨:

Logical product (AND)

Logical sum (OR)

∨:



Exclusive logical sum (exclusive OR)

Inverted data

:

addr16: 16-bit immediate data or label

jdisp8: Signed 8-bit data (displacement value)

22.1.3 Description of flag operation column

(Blank): Not affected

0:

1:

×:

R:

Cleared to 0

Set to 1

Set/cleared according to the result

Previously saved value is restored

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CHAPTER 22 INSTRUCTION SET

22.2 Operation List

Clock

Byte

Flag

Instruction

Mnemonic

Group

Operands

r, #byte

Operation

Z AC CY

Note 1 Note 2

8-bit data

transfer

MOV

2

3

1

2

3

2

1

2

1

2

3

1

2

4

6

−

2

4

−

8

−

4

8

6

2

4

−

8

4

8

−

7

r ← byte

saddr, #byte

sfr, #byte

A, r

(saddr) ← byte

sfr ← byte

A ← r

7

Note 3

−

r, A

−

r ← A

A, saddr

saddr, A

A, sfr

5

A ← (saddr)

(saddr) ← A

A ← sfr

5

sfr, A

5

sfr ← A

A, !addr16

!addr16, A

PSW, #byte

A, PSW

9

A ← (addr16)

(addr16) ← A

PSW ← byte

A ← PSW

9

7

×

5

PSW, A

5

PSW ← A

A, [DE]

5

A ← (DE)

[DE], A

5

(DE) ← A

A, [HL]

5

A ← (HL)

[HL], A

5

(HL) ← A

A, [HL + byte]

[HL + byte], A

A, [HL + B]

[HL + B], A

A, [HL + C]

[HL + C], A

A, r

9

A ← (HL + byte)

(HL + byte) ← A

A ← (HL + B)

(HL + B) ← A

A ← (HL + C)

(HL + C) ← A

A ↔ r

9

7

Note 3

XCH

−

A, saddr

A, sfr

6

A ↔ (saddr)

A ↔ sfr

6

A, !addr16

A, [DE]

10

6

A ↔ (addr16)

A ↔ (DE)

A, [HL]

6

A ↔ (HL)

A, [HL + byte]

A, [HL + B]

A, [HL + C]

10

A ↔ (HL + byte)

A ↔ (HL + B)

A ↔ (HL + C)

Notes 1. When the internal high-speed RAM area is accessed or for an instruction with no data access

2. When an area except the internal high-speed RAM area is accessed

3. Except “r = A”

Remarks 1. One instruction clock cycle is one cycle of the CPU clock (f^CPU) selected by the processor clock

control register (PCC).

2. This clock cycle applies to the internal ROM program.

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CHAPTER 22 INSTRUCTION SET

Clock

Byte

Flag

Instruction

Group

Mnemonic

Operands

rp, #word

Operation

Z AC CY

Note 1 Note 2

16-bit data MOVW

3

4

2

1

3

1

2

3

2

3

1

2

3

2

3

1

2

6

8

−

6

−

4

10

4

6

4

8

4

8

4

6

4

8

4

8

−

10

8

rp ← word

transfer

saddrp, #word

sfrp, #word

AX, saddrp

saddrp, AX

AX, sfrp

(saddrp) ← word

sfrp ← word

AX ← (saddrp)

(saddrp) ← AX

AX ← sfrp

8

sfrp, AX

8

sfrp ← AX

Note 3

AX, rp

−

AX ← rp

rp, AX

−

rp ← AX

AX, !addr16

!addr16, AX

AX, rp

12

−

AX ← (addr16)

(addr16) ← AX

AX ↔ rp

Note 3

XCHW

8-bit

ADD

A, #byte

−

A, CY ← A + byte

×

operation

saddr, #byte

A, r

8

(saddr), CY ← (saddr) + byte

A, CY ← A + r

Note 4

−

r, A

−

r, CY ← r + A

A, saddr

A, !addr16

A, [HL]

5

A, CY ← A + (saddr)

9

A, CY ← A + (addr16)

A, CY ← A + (HL)

5

A, [HL + byte]

A, [HL + B]

A, [HL + C]

A, #byte

9

A, CY ← A + (HL + byte)

A, CY ← A + (HL + B)

A, CY ← A + (HL + C)

A, CY ← A + byte + CY

(saddr), CY ← (saddr) + byte + CY

A, CY ← A + r + CY

9

ADDC

−

saddr, #byte

A, r

8

Note 4

−

r, A

−

r, CY ← r + A + CY

A, saddr

A, !addr16

A, [HL]

5

A, CY ← A + (saddr) + CY

A, CY ← A + (addr16) + CY

A, CY ← A + (HL) + CY

A, CY ← A + (HL + byte) + CY

A, CY ← A + (HL + B) + CY

A, CY ← A + (HL + C) + CY

9

5

A, [HL + byte]

A, [HL + B]

A, [HL + C]

9

Notes 1. When the internal high-speed RAM area is accessed or for an instruction with no data access

2. When an area except the internal high-speed RAM area is accessed

3. Only when rp = BC, DE or HL

4. Except “r = A”

Remarks 1. One instruction clock cycle is one cycle of the CPU clock (f^CPU) selected by the processor clock

control register (PCC).

2. This clock cycle applies to the internal ROM program.

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CHAPTER 22 INSTRUCTION SET

Clock

Byte

Flag

Instruction

Group

Mnemonic

Operands

A, #byte

Operation

A, CY ← A − byte

Z AC CY

Note 1 Note 2

8-bit

SUB

2

3

2

3

1

2

3

2

3

1

2

3

2

3

1

2

4

6

4

8

4

8

4

6

4

8

4

8

4

6

4

8

4

8

−

8

−

5

9

5

9

−

8

−

5

9

5

9

−

8

−

5

9

5

9

×

operation

saddr, #byte

A, r

(saddr), CY ← (saddr) − byte

A, CY ← A − r

Note 3

r, A

r, CY ← r − A

A, saddr

A, !addr16

A, [HL]

A, CY ← A − (saddr)

A, CY ← A − (addr16)

A, CY ← A − (HL)

A, [HL + byte]

A, [HL + B]

A, [HL + C]

A, #byte

saddr, #byte

A, r

A, CY ← A − (HL + byte)

A, CY ← A − (HL + B)

A, CY ← A − (HL + C)

A, CY ← A − byte − CY

(saddr), CY ← (saddr) − byte − CY

A, CY ← A − r − CY

r, CY ← r − A − CY

A, CY ← A − (saddr) − CY

A, CY ← A − (addr16) − CY

A, CY ← A − (HL) − CY

A, CY ← A − (HL + byte) − CY

A, CY ← A − (HL + B) − CY

A, CY ← A − (HL + C) − CY

A ← A ∧ byte

SUBC

r, A

A, saddr

A, !addr16

A, [HL]

A, [HL + byte]

A, [HL + B]

A, [HL + C]

A, #byte

saddr, #byte

A, r

AND

(saddr) ← (saddr) ∧ byte

A ← A ∧ r

r, A

r ← r ∧ A

A, saddr

A, !addr16

A, [HL]

A ← A ∧ (saddr)

A ← A ∧ (addr16)

A ← A ∧ (HL)

A, [HL + byte]

A, [HL + B]

A, [HL + C]

A ← A ∧ (HL + byte)

A ← A ∧ (HL + B)

A ← A ∧ (HL + C)

Notes 1. When the internal high-speed RAM area is accessed or for an instruction with no data access

2. When an area except the internal high-speed RAM area is accessed

3. Except “r = A”

Remarks 1. One instruction clock cycle is one cycle of the CPU clock (f^CPU) selected by the processor clock

control register (PCC).

2. This clock cycle applies to the internal ROM program.

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CHAPTER 22 INSTRUCTION SET

Clock

Byte

Flag

Instruction

Group

Mnemonic

Operands

A, #byte

Operation

Z AC CY

Note 1 Note 2

8-bit

OR

2

3

2

3

1

2

3

2

3

1

2

3

2

3

1

2

4

6

4

8

4

8

4

6

4

8

4

8

4

6

4

8

4

8

−

8

−

5

9

5

9

−

8

−

5

9

5

9

−

8

−

5

9

5

9

A ← A ∨ byte

×

operation

saddr, #byte

A, r

(saddr) ← (saddr) ∨ byte

A ← A ∨ r

Note 3

r, A

r ← r ∨ A

A, saddr

A, !addr16

A, [HL]

A ← A ∨ (saddr)

A ← A ∨ (addr16)

A ← A ∨ (HL)

A ← A ∨ (HL + byte)

A ← A ∨ (HL + B)

A ← A ∨ (HL + C)

A ← A ∨ byte

(saddr) ← (saddr) ∨ byte

A ← A ∨ r

A, [HL + byte]

A, [HL + B]

A, [HL + C]

A, #byte

saddr, #byte

A, r

XOR

r, A

r ← r ∨ A

A, saddr

A, !addr16

A, [HL]

A ← A ∨ (saddr)

A ← A ∨ (addr16)

A ← A ∨ (HL)

A ← A ∨ (HL + byte)

A ← A ∨ (HL + B)

A ← A ∨ (HL + C)

A − byte

A, [HL + byte]

A, [HL + B]

A, [HL + C]

A, #byte

saddr, #byte

A, r

CMP

×

(saddr) − byte

A − r

r, A

r − A

A, saddr

A, !addr16

A, [HL]

A − (saddr)

A − (addr16)

A − (HL)

A, [HL + byte]

A, [HL + B]

A, [HL + C]

A − (HL + byte)

A − (HL + B)

A − (HL + C)

Notes 1. When the internal high-speed RAM area is accessed or for an instruction with no data access

2. When an area except the internal high-speed RAM area is accessed

3. Except “r = A”

Remarks 1. One instruction clock cycle is one cycle of the CPU clock (f^CPU) selected by the processor clock

control register (PCC).

2. This clock cycle applies to the internal ROM program.

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CHAPTER 22 INSTRUCTION SET

Clock

Byte

Flag

Instruction

Group

Mnemonic

Operands

AX, #word

Operation

AX, CY ← AX + word

Z AC CY

Note 1 Note 2

16-bit

ADDW

SUBW

CMPW

MULU

DIVUW

3

2

1

2

1

2

1

2

6

−

6

−

6

−

12

×

operation

AX, #word

AX, CY ← AX − word

AX − word

AX, #word

6

Multiply/

divide

X

16

25

2

AX ← A × X

C

AX (Quotient), C (Remainder) ← AX ÷ C

r ← r + 1

Increment/ INC

r

×

decrement

saddr

r

4

(saddr) ← (saddr) + 1

r ← r − 1

DEC

2

saddr

rp

4

(saddr) ← (saddr) − 1

rp ← rp + 1

INCW

4

DECW

rp

4

rp ← rp − 1

Rotate

ROR

A, 1

[HL]

2

(CY, A7 ← A0, Am − 1 ← Am) × 1 time

(CY, A0 ← A7, Am + 1 ← Am) × 1 time

(CY ← A0, A7 ← CY, Am − 1 ← Am) × 1 time

(CY ← A7, A0 ← CY, Am + 1 ← Am) × 1 time

×

ROL

2

RORC

ROLC

ROR4

2

10

A3 − 0 ← (HL)3 − 0, (HL)7 − 4 ← A3 − 0,

(HL)^{3 − 0}← (HL)7 − 4

ROL4

[HL]

2

10

12

A^{3 − 0}← (HL)7 − 4, (HL)3 − 0 ← A3 − 0,

(HL)^{7 − 4}← (HL)3 − 0

BCD

ADJBA

ADJBS

MOV1

2

3

2

3

2

3

2

3

2

4

6

−

4

−

6

−

4

−

6

−

7

−

7

8

−

8

Decimal Adjust Accumulator after Addition

Decimal Adjust Accumulator after Subtract

CY ← (saddr.bit)

×

adjustment

Bit

CY, saddr.bit

CY, sfr.bit

manipulate

CY ← sfr.bit

CY, A.bit

CY ← A.bit

CY, PSW.bit

CY, [HL].bit

saddr.bit, CY

sfr.bit, CY

CY ← PSW.bit

CY ← (HL).bit

(saddr.bit) ← CY

sfr.bit ← CY

A.bit, CY

A.bit ← CY

PSW.bit, CY

[HL].bit, CY

PSW.bit ← CY

×

(HL).bit ← CY

Notes 1. When the internal high-speed RAM area is accessed or for an instruction with no data access

2. When an area except the internal high-speed RAM area is accessed

Remarks 1. One instruction clock cycle is one cycle of the CPU clock (f^CPU) selected by the processor clock

control register (PCC).

2. This clock cycle applies to the internal ROM program.

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CHAPTER 22 INSTRUCTION SET

Clock

Byte

Flag

Instruction

Group

Mnemonic

Operands

CY, saddr.bit

Operation

CY ← CY ∧ (saddr.bit)

Z AC CY

Note 1 Note 2

Bit

manipulate

AND1

3

2

3

2

3

2

3

2

3

2

3

2

3

2

3

2

1

6

−

4

−

6

−

4

−

6

−

4

−

6

4

−

4

−

6

4

−

4

−

6

2

7

−

7

−

7

−

7

6

8

−

6

8

6

8

−

6

8

−

×

CY, sfr.bit

CY, A.bit

CY, PSW.bit

CY, [HL].bit

CY, saddr.bit

CY, sfr.bit

CY, A.bit

CY, PSW.bit

CY, [HL].bit

CY, saddr.bit

CY, sfr.bit

CY, A.bit

CY, PSW.bit

CY, [HL].bit

saddr.bit

sfr.bit

CY ← CY ∧ sfr.bit

CY ← CY ∧ A.bit

CY ← CY ∧ PSW.bit

CY ← CY ∧ (HL).bit

CY ← CY ∨ (saddr.bit)

CY ← CY ∨ sfr.bit

CY ← CY ∨ A.bit

CY ← CY ∨ PSW.bit

CY ← CY ∨ (HL).bit

CY ← CY ∨ (saddr.bit)

CY ← CY ∨ sfr.bit

CY ← CY ∨ A.bit

CY ← CY ∨ PSW.bit

CY ← CY ∨ (HL).bit

(saddr.bit) ← 1

sfr.bit ← 1

OR1

XOR1

SET1

CLR1

A.bit

A.bit ← 1

PSW.bit

[HL].bit

PSW.bit ← 1

×

(HL).bit ← 1

saddr.bit

sfr.bit

(saddr.bit) ← 0

sfr.bit ← 0

A.bit

A.bit ← 0

PSW.bit

[HL].bit

PSW.bit ← 0

×

(HL).bit ← 0

SET1

CLR1

NOT1

CY

CY ← 1

1

0

×

CY

CY ← 0

CY

CY ← CY

Notes 1. When the internal high-speed RAM area is accessed or for an instruction with no data access

2. When an area except the internal high-speed RAM area is accessed

Remarks 1. One instruction clock cycle is one cycle of the CPU clock (f^CPU) selected by the processor clock

control register (PCC).

2. This clock cycle applies to the internal ROM program.

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CHAPTER 22 INSTRUCTION SET

Clock

Byte

Flag

Instruction

Group

Mnemonic

Operands

!addr16

Operation

Z AC CY

Note 1 Note 2

Call/return CALL

3

2

7

5

−

(SP − 1) ← (PC + 3)H, (SP − 2) ← (PC + 3)L,

PC ← addr16, SP ← SP − 2

CALLF

!addr11

[addr5]

−

(SP − 1) ← (PC + 2)H, (SP − 2) ← (PC + 2)L,

PC^{15 − 11}← 00001, PC10 − 0 ← addr11,

SP ← SP − 2

CALLT

BRK

1

6

−

(SP − 1) ← (PC + 1)H, (SP − 2) ← (PC + 1)L,

PC^H← (00000000, addr5 + 1),

PC^L← (00000000, addr5),

SP ← SP − 2

(SP − 1) ← PSW, (SP − 2) ← (PC + 1)H,

(SP − 3) ← (PC + 1)^L, PCH ← (003FH),

PC^L← (003EH), SP ← SP − 3, IE ← 0

RET

1

6

−

PCH ← (SP + 1), PCL ← (SP),

SP ← SP + 2

RETI

RETB

PCH ← (SP + 1), PCL ← (SP),

PSW ← (SP + 2), SP ← SP + 3,

R

PC^H← (SP + 1), PCL ← (SP),

PSW ← (SP + 2), SP ← SP + 3

−

Stack

PUSH

POP

PSW

rp

1

2

4

(SP − 1) ← PSW, SP ← SP − 1

manipulate

(SP − 1) ← rp^H, (SP − 2) ← rpL,

SP ← SP − 2

−

PSW

rp

1

2

4

PSW ← (SP), SP ← SP + 1

R

rp^H← (SP + 1), rpL ← (SP),

SP ← SP + 2

−

6

8

6

MOVW

SP, #word

SP, AX

AX, SP

!addr16

$addr16

AX

4

2

3

2

10

8

−

SP ← word

SP ← AX

AX ← SP

Unconditional BR

PC ← addr16

branch

−

PC ← PC + 2 + jdisp8

PC^H← A, PCL ← X

PC ← PC + 2 + jdisp8 if CY = 1

PC ← PC + 2 + jdisp8 if CY = 0

PC ← PC + 2 + jdisp8 if Z = 1

PC ← PC + 2 + jdisp8 if Z = 0

−

Conditional BC

$addr16

branch

−

BNC

−

BZ

−

BNZ

Notes 1. When the internal high-speed RAM area is accessed or for an instruction with no data access

2. When an area except the internal high-speed RAM area is accessed

Remarks 1. One instruction clock cycle is one cycle of the CPU clock (f^CPU) selected by the processor clock

control register (PCC).

2. This clock cycle applies to the internal ROM program.

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CHAPTER 22 INSTRUCTION SET

Clock

Byte

Flag

Instruction

Group

Mnemonic

Operands

Operation

Z AC CY

Note 1 Note 2

Conditional BT

saddr.bit, $addr16

sfr.bit, $addr16

A.bit, $addr16

3

4

3

4

3

4

3

4

8

−

9

PC ← PC + 3 + jdisp8 if (saddr.bit) = 1

PC ← PC + 4 + jdisp8 if sfr.bit = 1

PC ← PC + 3 + jdisp8 if A.bit = 1

PC ← PC + 3 + jdisp8 if PSW.bit = 1

PC ← PC + 3 + jdisp8 if (HL).bit = 1

PC ← PC + 4 + jdisp8 if (saddr.bit) = 0

PC ← PC + 4 + jdisp8 if sfr.bit = 0

PC ← PC + 3 + jdisp8 if A.bit = 0

PC ← PC + 4 + jdisp8 if PSW. bit = 0

PC ← PC + 3 + jdisp8 if (HL).bit = 0

branch

11

−

8

PSW.bit, $addr16

[HL].bit, $addr16

saddr.bit, $addr16

sfr.bit, $addr16

A.bit, $addr16

−

9

10

−

11

−

BF

8

PSW.bit, $addr16

[HL].bit, $addr16

saddr.bit, $addr16

−

11

12

10

BTCLR

PC ← PC + 4 + jdisp8 if (saddr.bit) = 1

then reset (saddr.bit)

sfr.bit, $addr16

A.bit, $addr16

PSW.bit, $addr16

[HL].bit, $addr16

B, $addr16

4

3

4

3

2

3

−

8

12

−

PC ← PC + 4 + jdisp8 if sfr.bit = 1

then reset sfr.bit

PC ← PC + 3 + jdisp8 if A.bit = 1

then reset A.bit

−

12

−

PC ← PC + 4 + jdisp8 if PSW.bit = 1

then reset PSW.bit

×

10

6

PC ← PC + 3 + jdisp8 if (HL).bit = 1

then reset (HL).bit

DBNZ

B ← B − 1, then

PC ← PC + 2 + jdisp8 if B ≠ 0

C, $addr16

6

−

C ← C −1, then

PC ← PC + 2 + jdisp8 if C ≠ 0

saddr, $addr16

RBn

8

10

(saddr) ← (saddr) − 1, then

PC ← PC + 3 + jdisp8 if (saddr) ≠ 0

CPU

SEL

NOP

EI

2

1

2

4

2

−

6

−

6

−

RBS1, 0 ← n

control

No Operation

IE ← 1 (Enable Interrupt)

IE ← 0 (Disable Interrupt)

Set HALT Mode

DI

HALT

STOP

Set STOP Mode

Notes 1. When the internal high-speed RAM area is accessed or for an instruction with no data access

2. When an area except the internal high-speed RAM area is accessed

Remarks 1. One instruction clock cycle is one cycle of the CPU clock (f^CPU) selected by the processor clock

control register (PCC).

2. This clock cycle applies to the internal ROM program.

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CHAPTER 22 INSTRUCTION SET

22.3 Instructions Listed by Addressing Type

(1) 8-bit instructions

MOV, XCH, ADD, ADDC, SUB, SUBC, AND, OR, XOR, CMP, MULU, DIVUW, INC, DEC, ROR, ROL, RORC,

ROLC, ROR4, ROL4, PUSH, POP, DBNZ

Second Operand

#byte

A

r^Note

sfr

saddr !addr16 PSW

[DE]

[HL] [HL + byte] $addr16

[HL + B]

1

None

First Operand

A

[HL + C]

ADD

ADDC

SUB

SUBC

AND

OR

MOV MOV MOV MOV MOV MOV MOV MOV

ROR

XCH

ADD

ADDC

SUB

SUBC

AND

OR

XCH

ADD

XCH

ADD

XCH

ADD

XCH

ADD

ROL

RORC

ROLC

ADDC ADDC

SUB SUB

SUBC SUBC

ADDC ADDC

SUB SUB

SUBC SUBC

XOR

CMP

AND

OR

AND

OR

AND

OR

AND

OR

XOR

CMP

XOR

CMP

XOR

CMP

XOR

CMP

XOR

CMP

r

MOV MOV

ADD

INC

DEC

ADDC

SUB

SUBC

AND

OR

XOR

CMP

B, C

sfr

DBNZ

MOV MOV

saddr

MOV MOV

ADD

INC

DEC

ADDC

SUB

SUBC

AND

OR

XOR

CMP

!addr16

PSW

MOV

MOV MOV

PUSH

POP

[DE]

[HL]

MOV

ROR4

ROL4

[HL + byte]

[HL + B]

MOV

[HL + C]

X

C

MULU

DIVUW

Note Except r = A

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CHAPTER 22 INSTRUCTION SET

(2) 16-bit instructions

MOVW, XCHW, ADDW, SUBW, CMPW, PUSH, POP, INCW, DECW

Second Operand

First Operand

#word

AX

rp^Note

sfrp

saddrp

!addr16

SP

None

AX

ADDW

MOVW

XCHW

MOVW

SUBW

CMPW

rp

MOVW

MOVW^Note

INCW

DECW

PUSH

POP

sfrp

MOVW

saddrp

!addr16

SP

MOVW

Note Only when rp = BC, DE, HL

(3) Bit manipulation instructions

MOV1, AND1, OR1, XOR1, SET1, CLR1, NOT1, BT, BF, BTCLR

Second Operand

First Operand

A.bit

sfr.bit

saddr.bit

PSW.bit

[HL].bit

CY

$addr16

None

A.bit

MOV1

BT

SET1

CLR1

BF

BTCLR

sfr.bit

MOV1

BT

SET1

CLR1

BF

BTCLR

saddr.bit

PSW.bit

[HL].bit

CY

BT

SET1

CLR1

BF

BTCLR

BT

SET1

CLR1

BF

BTCLR

BT

SET1

CLR1

BF

BTCLR

MOV1

AND1

OR1

MOV1

SET1

CLR1

NOT1

AND1

OR1

AND1

OR1

AND1

OR1

AND1

OR1

XOR1

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CHAPTER 22 INSTRUCTION SET

(4) Call instructions/branch instructions

CALL, CALLF, CALLT, BR, BC, BNC, BZ, BNZ, BT, BF, BTCLR, DBNZ

Second Operand

First Operand

AX

!addr16

!addr11

[addr5]

$addr16

Basic instruction

BR

CALL

BR

CALLF

CALLT

BR

BC

BNC

BZ

BNZ

Compound

instruction

BT

BF

BTCLR

DBNZ

(5) Other instructions

ADJBA, ADJBS, BRK, RET, RETI, RETB, SEL, NOP, EI, DI, HALT, STOP

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CHAPTER 23 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS, (A) GRADE PRODUCTS)

<R>

Target products: µPD780861, 780862, 78F0862, 78F0862A, 780861(A), 780862(A), 78F0862(A), 78F0862A(A)

Parameter

Supply voltage

Symbol

Conditions

Ratings

Unit

V

VDD

−0.3 to +6.5

VSS

−0.3 to +0.3

V

AV^REF

VI1

−0.3 to VDD + 0.3^Note

V

Input voltage

P00, P01, P10 to P15, P20 to P23, X1,

X2, RESET

V

Output voltage

VO

−0.3 to VDD + 0.3^Note

V

Analog input voltage

VAN

VSS − 0.3 to AVREF + 0.3^Note

and −0.3 to V^DD+ 0.3^Note

Output current, high

Output current, low

IOH

IOL

T^A

Per pin

−10

−30

mA

°C

Total of P00, P01, P10 to P15, P130 pins

Per pin

20

Total of P00, P01, P10 to P15, P130 pins

In normal operation mode

In flash memory programming

Mask ROM versions

35

Operating ambient

temperature

−40 to +85

−65 to +150

−40 to +150

Storage temperature

Tstg

°C

Flash memory versions

Note Must be 6.5 V or lower.

Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any

parameter. That is, the absolute maximum ratings are rated values at which the product is on the

verge of suffering physical damage, and therefore the product must be used under conditions that

ensure that the absolute maximum ratings are not exceeded.

Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins.

370

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CHAPTER 23 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS, (A) GRADE PRODUCTS)

Crystal/Ceramic Oscillator Characteristics (When Selecting Crystal/Ceramic Oscillation)

(T^A= −40 to +85°C, 2.7 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ AVREF ≤ VDD, VSS = 0 V)

Resonator

Recommended Circuit

Parameter

Conditions

MIN.

2.0

TYP. MAX.

Unit

Crystal resonator

Oscillation frequency

(f^XH)^Note

4.0 V ≤ VDD ≤ 5.5 V

3.3 V ≤ VDD < 4.0 V

2.7 V ≤ V^DD< 3.3 V

10

8.38

5.0

MHz

V

SS

X1

X2

2.0

C2

C1

Ceramic resonator

Oscillation frequency

(f^XH)^Note

4.0 V ≤ VDD ≤ 5.5 V

3.3 V ≤ VDD < 4.0 V

2.7 V ≤ V^DD< 3.3 V

2.0

10

8.38

5.0

MHz

V

^SSX1

X2

C2

C1

X1

External clock

X1 input frequency

(f^XH)^Note

4.0 V ≤ VDD ≤ 5.5 V

3.3 V ≤ VDD < 4.0 V

2.7 V ≤ V^DD< 3.3 V

4.0 V ≤ VDD ≤ 5.5 V

3.3 V ≤ VDD < 4.0 V

2.7 V ≤ V^DD< 3.3 V

2.0

46

10

8.38

5.0

MHz

ns

X2

X1 input high-/low-

level width (t^XH, tXL)

250

<R>

56

96

Note Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time.

Caution When using the crystal/ceramic oscillator, wire as follows in the area enclosed by the broken lines

in the above figures to avoid an adverse effect from wiring capacitance.

• Keep the wiring length as short as possible.

• Do not cross the wiring with the other signal lines.

• Do not route the wiring near a signal line through which a high fluctuating current flows.

• Always make the ground point of the oscillator capacitor the same potential as V^SS.

• Do not ground the capacitor to a ground pattern through which a high current flows.

• Do not fetch signals from the oscillator.

Remark For the resonator selection and oscillator constant, users are required to either evaluate the oscillation

themselves or apply to the resonator manufacturer for evaluation.

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CHAPTER 23 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS, (A) GRADE PRODUCTS)

External RC Oscillator Characteristics (When Selecting External RC Oscillation)

(T^A= −40 to +85°C, 2.7 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ AVREF ≤ VDD, VSS = 0 V)

Resonator

RC oscillation

Recommended Circuit

Parameter

Conditions

MIN.

3.0

TYP. MAX.

4.0

Unit

Oscillation frequency

(f^XH)^Note

MHz

V^SSCL1

CL2

R

C

External clock

X1 input frequency

(f^XH)^Note

4.0 V ≤ VDD ≤ 5.5 V

3.3 V ≤ VDD < 4.0 V

2.7 V ≤ V^DD< 3.3 V

4.0 V ≤ VDD ≤ 5.5 V

3.3 V ≤ VDD < 4.0 V

2.7 V ≤ V^DD< 3.3 V

2.0

46

10

8.38

5.0

MHz

ns

X1

X2

X1 input high-/low-

level width (t^XH, tXL)

250

<R>

56

96

Note Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time.

Caution When using the RC oscillator, wire as follows in the area enclosed by the broken lines in the above

figure to avoid an adverse effect from wiring capacitance.

• Keep the wiring length as short as possible.

• Do not cross the wiring with the other signal lines.

• Do not route the wiring near a signal line through which a high fluctuating current flows.

• Always make the ground point of the oscillator capacitor the same potential as V^SS.

• Do not ground the capacitor to a ground pattern through which a high current flows.

• Do not fetch signals from the oscillator.

External RC Oscillation Frequency Characteristics (When Selecting External RC Oscillation)

(T^A= −40 to +85°C, 2.7 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ AVREF ≤ VDD, VSS = 0 V)

Parameter

Conditions

MIN.

2.5

TYP. MAX.

Unit

Oscillation frequency

(f^XH)^Note

R = 6.8 kΩ, C = 22 pF

Target value: 3 MHz

3.0

3.5

MHz

R = 4.7 kΩ, C = 22 pF

3.5

4.0

4.7

MHz

Target value: 4 MHz

Note Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time.

Caution Set one of the above values to R and C.

Internal High-Speed Oscillator Characteristics (When Selecting Internal High-Speed Oscillation)

(T^A= −40 to +85°C, 4.0 V ≤ VDD ≤ 5.5 V, 4.0 V ≤ AVREF ≤ VDD, VSS = 0 V)

Resonator

Parameter

Conditions

MIN.

6.80

TYP. MAX.

8.00 9.20

Unit

Internal high-speed oscillator

Oscillation frequency (fXH)^Note

MHz

Note Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time.

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Internal Low-Speed Oscillator Characteristics (TA = −40 to +85°C, 2.7 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ AVREF ≤ VDD, VSS = 0 V)

Resonator

Parameter

Conditions

MIN.

120

TYP. MAX.

240 480

Unit

kHz

Internal low-speed oscillator

Oscillation frequency (fR)^Note

Note Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time.

DC Characteristics (T^A= −40 to +85°C, 2.7 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ AVREF ≤ VDD, VSS = 0 V) (1/3)

Parameter

Symbol

Conditions

MIN.

TYP. MAX.

−5

Unit

mA

V

Output current, high

IOH

Per pin

4.0 V ≤ VDD ≤ 5.5 V

2.7 V ≤ V^DD< 4.0 V

4.0 V ≤ VDD ≤ 5.5 V

2.7 V ≤ V^DD< 4.0 V

Total of P00, P01, P10 to P15, P130

−25

−10

Output current, low

Input voltage, high

IOL

Per pin

10

Total of P00, P01, P10 to P15, P130

30

10

VIH1

VIH2

VIH3

V^IH4

VIL1

VIL2

VIL3

V^IL4

VOH

P02^{Note 1}, P12, P13, P15

P00, P01, P10, P11, P14, RESET

P20 to P23^{Note 2}

0.7VDD

VDD

0.8VDD

VDD

V

0.7AVREF

AVREF

VDD

V

X1, X2

VDD − 0.5

V

Input voltage, low

P02^{Note 1}, P12, P13, P15

P00, P01, P10, P11, P14, RESET

P20 to P23^{Note 2}

0

0.3VDD

0.2VDD

0.3AVREF

0.4

V

X1, X2

V

Output voltage, high

Output voltage, low

Total of P00, P01, P10 to P15,

4.0 V ≤ V^DD≤ 5.5 V, V^DD− 1.0

I^OH= −5 mA

V

P130 pins

I^OH= −25 mA

I^OH= −100 µA

2.7 V ≤ VDD < 4.0 V VDD − 0.5

V

VOL

ILIH1

Total of P00, P01, P10 to P15,

4.0 V ≤ V^DD≤ 5.5 V,

I^OL= 10 mA

1.3

P130 pins

I^OL= 400 µA

VI = VDD

I^OL= 30 mA

2.7 V ≤ VDD < 4.0 V

0.4

3

V

Input leakage current, high

P00, P01, P10 to P15, RESET

µA

V^I= AVREF

VI = VDD

P20 to P23

3

I^LIH2

X1, X2^{Note 3}

20

−3

Input leakage current, low

ILIL1

V^I= 0 V

P00, P01, P10 to P15, P20 to P23,

RESET

I^LIL2

X1, X2^{Note 3}

−20

3

µA

kΩ

V

Output leakage current, high ILOH

Output leakage current, low ILOL

VO = VDD

VO = 0 V

VI = 0 V

−3

Pull-up resistance value

R

10

0

30

100

FLMD0 supply voltage

(Flash memory versions

only)

Flmd

In normal operation mode

0.2V^DD

Notes 1. When the internal high-speed oscillation clock is selected as the high-speed system clock, P02 can be

used as a port input pin.

<R>

2. When used as a digital input port, set AV^REF= VDD.

3. When the inverse input level of X1 is input to X2.

Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins.

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DC Characteristics (2/3): Flash Memory Versions

(T^A= −40 to +85°C, 2.7 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ AVREF ≤ VDD, VSS = 0 V)

Parameter

Symbol

Conditions

MIN. TYP. MAX. Unit

7.8 15.4 mA

Crystal/

Supply

current^{Note 1}

IDD1

fXH = 10 MHz,

V^DD= 5.0 V 10%^{Note 3}

When A/D converter is stopped

ceramic oscillation

operating mode^{Notes 2, 6}

When A/D converter is

operating^{Note 4}

8.8 17.4 mA

f^XH= 5 MHz,

V^DD= 3.0 V 10%^{Note 3}

When A/D converter is stopped

2.4

3.0

5.1

6.3

mA

When A/D converter is

operating^{Note 4}

Crystal/

IDD2

fXH = 10 MHz,

When peripheral functions are

stopped

1.7

3.8

6.7

mA

ceramic oscillation

HALT mode^{Note 6}

V^DD= 5.0 V 10%

When peripheral functions are

operating

f^XH= 5 MHz,

When peripheral functions are

stopped

0.48 1.0

2.1

V^DD= 3.0 V 10%

When peripheral functions are

operating

IDD3

External RC

fX = 4 MHz,

When A/D converter is stopped

4.5

9.5

oscillation operating V^DD= 5.0 V 10%

mode^{Notes 2, 7}

When A/D converter is

operating^{Note 4}

5.5 11.5 mA

f^X= 4 MHz,

When A/D converter is stopped

2.4

3.0

5.1

6.3

mA

V^DD= 3.0 V 10%

When A/D converter is

operating^{Note 4}

IDD4

External RC

oscillation HALT

mode^{Note 7}

fX = 4 MHz,

When peripheral functions are

stopped

1.6

3.5

5.3

mA

V^DD= 5.0 V 10%

When peripheral functions are

operating

fX = 4 MHz,

When peripheral functions are

stopped

0.87 2.0

3.0

V^DD= 3.0 V 10%

When peripheral functions are

operating

IDD5

IDD6

Internal high-speed

f^XH= 8 MHz,

When A/D converter is stopped

6.9 14.4 mA

7.9 16.4 mA

oscillation operating V^DD= 5.0 V 10%

mode^{Notes 2, 8}

When A/D converter is

operating^{Note 4}

Internal high-speed

oscillation HALT

mode^{Note 8}

f^XH= 8 MHz,

When peripheral functions are

stopped

1.4

3.2

5.9

7.2

mA

V^DD= 5.0 V 10%

When peripheral functions are

operating

IDD7

IDD8

IDD9

Internal low-speed

oscillation operating

mode^{Note 5}

VDD = 5.0 V 10%

V^DD= 3.0 V 10%

1.8

mA

0.88 3.5

Internal low-speed

oscillation HALT

mode^{Note 5}

VDD = 5.0 V 10%

V^DD= 3.0 V 10%

0.08 0.32 mA

0.06 0.24 mA

STOP mode

VDD = 5.0 V 10% Internal low-speed oscillation: OFF

Internal low-speed oscillation: ON

3.5 35.5 µA

17.5 63.5 µA

3.5 15.5 µA

11.0 30.5 µA

VDD = 3.0 V 10% Internal low-speed oscillation OFF

Internal low-speed oscillation: ON

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Notes 1. Total current flowing through the internal power supply (VDD). Peripheral operation current is included

(however, the current that flows through the pull-up resistors of ports is not included).

2. Peripheral operation current is included.

3. When PCC = 00H.

4. Total of the current that flows through the V^DDpin and AVREF pin.

5. When high-speed system clock is stopped.

6. When crystal/ceramic oscillation is selected as the high-speed system clock using an option byte.

7. When an external RC is selected as the high-speed system clock using an option byte.

8. When an internal high-speed oscillation is selected as the high-speed system clock using an option byte.

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DC Characteristics (3/3): Mask ROM Versions

(T^A= −40 to +85°C, 2.7 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ AVREF ≤ VDD, VSS = 0 V)

Parameter

Symbol

Conditions

MIN. TYP. MAX. Unit

6.1 11.9 mA

Crystal/

Supply

current^{Note 1}

IDD1

fXH = 10 MHz,

V^DD= 5.0 V 10%^{Note 3}

When A/D converter is stopped

ceramic oscillation

operating mode^{Notes 2, 6}

When A/D converter is

operating^{Note 4}

7.1 13.9 mA

f^XH= 5 MHz,

V^DD= 3.0 V 10%^{Note 3}

When A/D converter is stopped

1.7

2.3

3.6

4.8

mA

When A/D converter is

operating^{Note 4}

Crystal/

IDD2

fXH = 10 MHz,

When peripheral functions are

stopped

1.6

3.6

6.5

mA

ceramic oscillation

HALT mode^{Note 6}

V^DD= 5.0 V 10%

When peripheral functions are

operating

f^XH= 5 MHz,

When peripheral functions are

stopped

0.41 0.96 mA

V^DD= 3.0 V 10%

When peripheral functions are

operating

2.1

mA

IDD3

External RC

fX = 4 MHz,

When A/D converter is stopped

3.2

4.2

6.4

8.4

mA

oscillation operating V^DD= 5.0 V 10%

mode^{Notes 2, 7}

When A/D converter is

operating^{Note 4}

f^X= 4 MHz,

When A/D converter is stopped

1.7

2.3

3.6

4.8

mA

V^DD= 3.0 V 10%

When A/D converter is

operating^{Note 4}

IDD4

External RC

oscillation HALT

mode^{Note 7}

fX = 4 MHz,

When peripheral functions are

stopped

1.6

3.5

5.3

mA

V^DD= 5.0 V 10%

When peripheral functions are

operating

fX = 4 MHz,

When peripheral functions are

stopped

0.87 2.0

3.0

V^DD= 3.0 V 10%

When peripheral functions are

operating

IDD5

IDD6

Internal high-speed

f^XH= 8 MHz,

When A/D converter is stopped

4.98 10.1 mA

5.98 12.1 mA

oscillation operating V^DD= 5.0 V 10%

mode^{Notes 2, 8}

When A/D converter is

operating^{Note 4}

Internal high-speed

oscillation HALT

mode^{Note 8}

f^XH= 8 MHz,

When peripheral functions are

stopped

1.24 2.8

5.5

mA

V^DD= 5.0 V 10%

When peripheral functions are

operating

IDD7

IDD8

IDD9

Internal low-speed

oscillation operating

mode^{Note 5}

VDD = 5.0 V 10%

V^DD= 3.0 V 10%

0.17 0.68 mA

0.11 0.44 mA

Internal low-speed

oscillation HALT

mode^{Note 5}

VDD = 5.0 V 10%

V^DD= 3.0 V 10%

0.04 0.16 mA

0.03 0.12 mA

STOP mode

VDD = 5.0 V 10% Internal low-speed oscillator: OFF

Internal low-speed oscillator : ON

3.5 35.5 µA

17.5 63.5 µA

3.5 15.5 µA

11.0 30.5 µA

VDD = 3.0 V 10% Internal low-speed oscillator: OFF

Internal low-speed oscillator: ON

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Notes 1. Total current flowing through the internal power supply (VDD). Peripheral operation current is included

(however, the current that flows through the pull-up resistors of ports is not included).

2. Peripheral operation current is included.

3. When PCC = 00H.

4. Total of the current that flows through the V^DDpin and AVREF pin.

5. When high-speed system clock is stopped.

6. When crystal/ceramic oscillation is selected as the high-speed system clock using mask option.

7. When an external RC is selected as the high-speed system clock using mask option.

8. When an internal high-speed oscillation is selected as the high-speed system clock using mask option.

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AC Characteristics

(1) Basic operation (T^A= −40 to +85°C, 2.7 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ AVREF ≤ VDD, VSS = 0 V)

Parameter

Symbol

T^CY

Conditions

MIN.

0.2

TYP.

MAX.

16

Unit

µs

Instruction cycle

(minimum instruction

execution time)

Main

High- Crystal/ceramic 4.0 V ≤ VDD ≤ 5.5 V

speed oscillation clock

system

clock

3.3 V ≤ VDD < 4.0 V 0.238

2.7 V ≤ VDD < 3.3 V 0.4

16

µs

system

16

µs

operation clock

External RC

2.7 V ≤ V^DD≤ 5.5 V 0.426

12.8

µs

oscillation clock

Internal high-

speed

4.0 V ≤ V^DD≤ 5.5 V 0.217

0.25

8.33

4.7

µs

oscillation clock

Internal low-speed

oscillation clock

4.0 V ≤ VDD ≤ 5.5 V

2.7 V ≤ V^DD≤ 5.5 V 4.17

33.33

µs

TI00 input high-level

width, low-level width

tTIH0,

2/f^sam+

0.1^Note

t^TIL0

2.7 V ≤ V^DD< 4.0 V

2/f^sam+

0.2^Note

Interrupt input high-level tINTH,

1

width, low-level width

t^INTL

RESET low-level width

tRSL

10

Note Selection of fsam = fXH, fXH/4, or fXH/256 is possible using bits 0 and 1 (PRM000, PRM001) of prescaler mode

register 00 (PRM00). Note that when selecting the TI000 valid edge as the count clock, f^sam= fXH.

T^CYvs. VDD (Main System Clock Operation)

33.33

20.0

10.0

µ

5.0

Guaranteed

operation range

2.0

1.0

0.4

0.238

0.2

0.1

5.5

0

1.0

2.0

3.0

4.0

5.0

6.0

2.7 3.3

Supply voltage V^DD[V]

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(2) Serial interface (TA = −40 to +85°C, 2.7 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ AVREF ≤ VDD, VSS = 0 V)

(a) UART mode (UART6, dedicated baud rate generator output)

Parameter

Transfer rate

Symbol

Conditions

MIN.

TYP.

MAX.

312.5

Unit

kbps

(b) 3-wire serial I/O mode (SCK10... internal clock output)

Parameter

SCK10 cycle time

Symbol

Conditions

4.0 V ≤ VDD ≤ 5.5 V

3.3 V ≤ VDD < 4.0 V

2.7 V ≤ V^DD< 3.3 V

MIN.

200

MAX.

Unit

ns

tKCY1

240

ns

400

ns

SCK10 high-/low-level width

t^KH1,

t^KL1

t^KCY1/2 − 10

ns

SI10 setup time (to SCK10↑)

SI10 hold time (from SCK10↑)

tSIK1

tKSI1

t^KSO1

30

ns

Delay time from SCK10↓ to

C = 100 pF^Note

30

SO10 output

Note C is the load capacitance of the SCK10 and SO10 output lines.

(c) 3-wire serial I/O mode (SCK10... external clock input)

Parameter

SCK10 cycle time

Symbol

Conditions

MIN.

400

TYP.

MAX.

Unit

ns

tKCY2

SCK10 high-/low-level width

t^KH2,

t^KL2

t^KCY2/2

ns

SI10 setup time (to SCK10↑)

SI10 hold time (from SCK10↑)

tSIK2

tKSI2

t^KSO2

80

50

ns

Delay time from SCK10↓ to

C = 100 pF^Note

120

SO10 output

Note C is the load capacitance of the SO10 output line.

(3) Manchester code generator (T^A= −40 to +85°C, 2.7 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ AVREF ≤ VDD, VSS = 0 V)

(a) Dedicated baud rate generator output

Parameter

Transfer rate

Symbol

Conditions

MIN.

TYP.

MAX.

250.0

Unit

kbps

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AC Timing Test Points (Excluding X1)

0.8VDD

0.2VDD

0.8VDD

0.2VDD

Test points

Clock Timing

1/f^XP

tXL

tXH

V

IH4 (MIN.)

IL4 (MAX.)

X1

V

TI Timing

t

TIL0

tTIH0

TI00

Interrupt Request Input Timing

t^INTL

tINTH

INTP0 to INTP3

RESET Input Timing

tRSL

RESET

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Serial Transfer Timing

3-wire serial I/O mode:

tKCYm

t

KLm

t

KHm

SCK10

t

SIKm

t

KSIm

SI10

Input data

t

KSOm

SO10

Output data

Remark m = 1, 2

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CHAPTER 23 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS, (A) GRADE PRODUCTS)

A/D Converter Characteristics (TA = −40 to +85°C, 2.7 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ AVREF ≤ VDD, VSS = 0 V^{Note 1}

)

Parameter

Symbol

Conditions

MIN.

10

TYP.

10

MAX.

10

Unit

bit

Resolution

Overall error^{Notes 2, 3}

4.0 V ≤ AVREF ≤ 5.5 V

0.2

0.3

0.4

%FSR

µs

2.7 V ≤ AV^REF< 4.0 V

4.0 V ≤ AVREF ≤ 5.5 V

2.7 V ≤ AV^REF< 4.0 V

4.0 V ≤ AVREF ≤ 5.5 V

2.7 V ≤ AV^REF< 4.0 V

4.0 V ≤ AVREF ≤ 5.5 V

2.7 V ≤ AV^REF< 4.0 V

4.0 V ≤ AVREF ≤ 5.5 V

2.7 V ≤ AV^REF< 4.0 V

4.0 V ≤ AVREF ≤ 5.5 V

2.7 V ≤ AV^REF< 4.0 V

0.6

Conversion time

tCONV

14

17

100

0.4

µs

Zero-scale error^{Notes 2, 3}

Full-scale error^{Notes 2, 3}

Integral linearity error^{Note 2}

Differential linearity error^{Note 2}

Analog input voltage

%FSR

LSB

V

0.6

0.4

0.6

2.5

4.5

1.5

2.0

Note 1

VSS

VAIN

AVREF

Notes 1. VSS and AVSS are internally connected in the µPD780862 Subseries. The above specifications are for

when only the A/D converter is operating.

2. Excludes quantization error ( 1/2 LSB).

3. This value is indicated as a ratio (%FSR) to the full-scale value.

POC Circuit Characteristics (T^A= −40 to +85°C)

Parameter

Detection voltage

Symbol

VPOC

Conditions

MIN.

2.7

TYP.

2.85

MAX.

3.0

Unit

V

Power supply rise time

tPTH

VDD: 0 V → 2.7 V

0.0015

ms

Response delay time 1^{Note 1}

tPTHD

When power supply rises, after reaching

detection voltage (MAX.)

3.0

1.0

Response delay time 2^{Note 2}

Minimum pulse width

tPD

When VDD falls

ms

tPW

0.2

Notes 1. Time required from voltage detection to reset release.

2. Time required from voltage detection to internal reset output.

POC Circuit Timing

Supply voltage

(VDD

)

Detection voltage (MAX.)

Detection voltage (TYP.)

Detection voltage (MIN.)

t

PW

tPTH

tPTHD

t

PD

Time

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CHAPTER 23 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS, (A) GRADE PRODUCTS)

LVI Circuit Characteristics (TA = −40 to +85°C)

Parameter

Detection voltage

Symbol

Conditions

MIN.

4.1

TYP.

4.3

4.1

3.9

3.7

3.5

3.3

3.1

0.2

MAX.

4.5

Unit

V

VLVI0

VLVI1

VLVI2

VLVI3

VLVI4

VLVI5

VLVI6

tLD

3.9

4.3

V

3.7

4.1

V

3.5

3.9

V

3.3

3.7

V

3.15

2.95

3.45

3.25

2.0

V

Response time^{Note 1}

ms

Minimum pulse width

tLW

0.2

Operation stabilization wait time^{Note 2}tLWAIT

0.1

0.2

Notes 1. Time required from voltage detection to interrupt output or reset output.

2. Time required from setting LVION to 1 to operation stabilization.

Remarks 1. V^LVI0> VLVI1 > VLVI2 > VLVI3 > VLVI4 > VLVI5 > VLVI6

2. VPOC < VLVIm (m = 0 to 6)

LVI Circuit Timing

Supply voltage

(V^DD

)

Detection voltage (MAX.)

Detection voltage (TYP.)

Detection voltage (MIN.)

tLW

t

WAIT

t

LD

LVION ← 1

Time

Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics (T^A= −40 to +85°C)

Parameter

Symbol

VDDDR

tSREL

Conditions

MIN.

2.7

0

TYP.

MAX.

5.5

Unit

V

<R>

Data retention supply voltage

Release signal set time

µs

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CHAPTER 23 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS, (A) GRADE PRODUCTS)

Flash Memory Programming Characteristics: Flash Memory Versions

(T^A= 10 to 65°C, 3.0 V ≤ VDD ≤ 5.5 V, 3.0 V ≤ AVREF ≤ VDD, VSS = 0 V)

(1) µPD78F0862, 78F0862 (A)

Parameter

Symbol

IDD

Conditions

MIN.

TYP.

20

MAX.

45

Unit

mA

ms

s

VDD supply current

fX = 10 MHz, VDD = 5.5 V

<R>

Step erase time

Erase time^{Note 1}

Chip unit

Terac

100

Sector unit

Chip unit

T^eras

Teraca

T^erasa

Twrw

25.5

Sector unit

s

Step write time

Write time

50

µs

Twrwa

Cerwr

500

Number of rewrites per chip

1 erase + 1 write after erase = 1 rewrite^{Note 2}

100^{Note 3}Times

Notes 1. The prewrite time before erasure and the erase verify time (writeback time) are not included.

2. When a product is first written after shipment, “erase → write” and “write only” are both taken as one

rewrite.

<R>

3. µPD78F0862(A): 10 times (MAX.)

(2) µPD78F0862A, 78F0862A (A)

Parameter

Symbol

IDD

Conditions

MIN.

TYP.

MAX.

30.5

Unit

mA

ms

s

VDD supply current

fX = 10 MHz, VDD = 5.5 V

Step erase time

Erase time^{Note 1}

Chip unit

Terac

10

Sector unit

Chip unit

T^eras

Teraca

T^erasa

Twrw

2.55

500

100

Sector unit

s

Step write time

Write time

µs

Twrwa

Cerwr

µs

Number of rewrites per chip

1 erase + 1 write after erase = 1 rewrite^{Note 2}

Times

Notes 1. The prewrite time before erasure and the erase verify time (writeback time) are not included.

2. When a product is first written after shipment, “erase → write” and “write only” are both taken as one

rewrite.

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<R>

Target products: µPD780861(A1), 780862(A1), 78F0862A(A1)

Absolute Maximum Ratings (T^A= 25°C)

Parameter

Supply voltage

Symbol

Conditions

Ratings

Unit

V

VDD

−0.3 to +6.5

VSS

−0.3 to +0.3

V

AV^REF

VI1

−0.3 to VDD + 0.3^Note

−0.3 to V^DD+ 0.3^Note

V

Input voltage

P00, P01, P10 to P15, P20 to P23, X1,

X2, RESET

V

Output voltage

VO

−0.3 to VDD + 0.3^Note

V

Analog input voltage

VAN

V^SS− 0.3 to AVREF + 0.3^Note

and −0.3 to V^DD+ 0.3^Note

Output current, high

Output current, low

IOH

IOL

T^A

Per pin

−8

−24

mA

°C

Total of P00, P01, P10 to P15, P130 pins

Per pin

16

Total of P00, P01, P10 to P15, P130 pins

In normal operation mode

In flash memory programming mode

Mask ROM versions

28

Operating ambient

temperature

−40 to +110

−40 to +85

−65 to +150

−40 to +150

<R>

Storage temperature

Tstg

°C

Flash memory version

Note Must be 6.5 V or lower.

Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any

parameter. That is, the absolute maximum ratings are rated values at which the product is on the

verge of suffering physical damage, and therefore the product must be used under conditions that

ensure that the absolute maximum ratings are not exceeded.

Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins.

385

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Crystal/Ceramic Oscillator Characteristics (When Selecting Crystal/Ceramic Oscillation)

(T^A= −40 to +110°C, 2.7 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ AVREF ≤ VDD, VSS = 0 V)

Resonator

Recommended Circuit

Parameter

Conditions

MIN.

2.0

TYP. MAX.

Unit

Crystal resonator

Oscillation frequency

(f^XH)^Note

4.0 V ≤ VDD ≤ 5.5 V

2.7 V ≤ V^DD< 4.0 V

10

MHz

VSS

X1

X2

2.0

5.0

C2

C1

Ceramic resonator

Oscillation frequency

(f^XH)^Note

4.0 V ≤ VDD ≤ 5.5 V

2.7 V ≤ VDD < 4.0 V

2.0

10

MHz

V

^SSX1

X2

5.0

C2

C1

X1

External clock

X1 input frequency

(f^XH)^Note

4.0 V ≤ VDD ≤ 5.5 V

2.7 V ≤ V^DD< 4.0 V

2.0

10

MHz

ns

5.0

X2

X1 input high-/low-

level width (t^XH, tXL)

4.0 V ≤ VDD ≤ 5.5 V

2.7 V ≤ V^DD< 4.0 V

46

96

250

<R>

Note Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time.

Caution When using the crystal/ceramic oscillator, wire as follows in the area enclosed by the broken lines

in the above figures to avoid an adverse effect from wiring capacitance.

• Keep the wiring length as short as possible.

• Do not cross the wiring with the other signal lines.

• Do not route the wiring near a signal line through which a high fluctuating current flows.

• Always make the ground point of the oscillator capacitor the same potential as V^SS.

• Do not ground the capacitor to a ground pattern through which a high current flows.

• Do not fetch signals from the oscillator.

Remark For the resonator selection and oscillator constant, users are required to either evaluate the oscillation

themselves or apply to the resonator manufacturer for evaluation.

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CHAPTER 24 ELECTRICAL SPECIFICATIONS ((A1) GRADE PRODUCTS)

External RC Oscillator Characteristics (When Selecting External RC Oscillation)

(T^A= −40 to +110°C, 2.7 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ AVREF ≤ VDD, VSS = 0 V)

Resonator

RC oscillation

Recommended Circuit

Parameter

Conditions

MIN.

3.0

TYP. MAX.

4.0

Unit

Oscillation frequency

(f^XH)^Note

MHz

V

^SSCL1 CL2

R

C

External clock

X1 input frequency

(f^XH)^Note

4.0 V ≤ VDD ≤ 5.5 V

2.7 V ≤ VDD < 4.0 V

2.0

10

MHz

ns

5.0

X1

X2

X1 input high-/low-

level width (t^XH, tXL)

4.0 V ≤ VDD ≤ 5.5 V

2.7 V ≤ VDD < 4.0 V

46

96

250

<R>

Note Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time.

Caution When using the RC oscillator, wire as follows in the area enclosed by the broken lines in the above

figure to avoid an adverse effect from wiring capacitance.

• Keep the wiring length as short as possible.

• Do not cross the wiring with the other signal lines.

• Do not route the wiring near a signal line through which a high fluctuating current flows.

• Always make the ground point of the oscillator capacitor the same potential as V^SS.

• Do not ground the capacitor to a ground pattern through which a high current flows.

• Do not fetch signals from the oscillator.

External RC Oscillation Frequency Characteristics (When Selecting External RC Oscillation)

(T^A= −40 to +110°C, 2.7 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ AVREF ≤ VDD, VSS = 0 V)

Parameter

Conditions

MIN.

2.5

TYP. MAX.

Unit

Oscillation frequency

(f^XH)^Note

R = 6.8 kΩ, C = 22 pF

Target value: 3 MHz

3.0

3.5

MHz

R = 4.7 kΩ, C = 22 pF

3.5

4.0

4.7

MHz

Target value: 4 MHz

Note Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time.

Caution Set one of the above values to R and C.

Internal High-Speed Oscillator Characteristics (When Selecting Internal High-Speed Oscillation)

(T^A= −40 to +110°C, 4.0 V ≤ VDD ≤ 5.5 V, 4.0 V ≤ AVREF ≤ VDD, VSS = 0 V)

Resonator

Parameter

Conditions

MIN.

6.80

TYP. MAX.

8.00 9.20

Unit

Internal high-speed oscillator

Oscillation frequency (fXH)^Note

MHz

Note Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time.

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CHAPTER 24 ELECTRICAL SPECIFICATIONS ((A1) GRADE PRODUCTS)

Internal Low-Speed Oscillator Characteristics (TA = −40 to +110°C, 2.7 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ AVREF ≤ VDD, VSS = 0 V)

Resonator

Parameter

Conditions

MIN.

120

TYP. MAX.

240 490

Unit

kHz

Internal low-speed oscillator

Oscillation frequency (fR)^Note

Note Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time.

DC Characteristics (T^A= −40 to +110°C, 2.7 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ AVREF ≤ VDD, VSS = 0 V) (1/3)

Parameter

Symbol

Conditions

MIN.

TYP. MAX.

Unit

mA

V

Output current, high

IOH

Per pin

4.0 V ≤ VDD ≤ 5.5 V

2.7 V ≤ V^DD< 4.0 V

4.0 V ≤ VDD ≤ 5.5 V

2.7 V ≤ V^DD< 4.0 V

−4

−20

Total of P00, P01, P10 to P15, P130

−8

Output current, low

Input voltage, high

IOL

Per pin

8

Total of P00, P01, P10 to P15, P130

24

8

VIH1

VIH2

VIH3

V^IH4

VIL1

VIL2

VIL3

V^IL4

VOH

P02^{Note 1}, P12, P13, P15

P00, P01, P10, P11, P14, RESET

P20 to P23^{Note 2}

0.7VDD

VDD

0.8VDD

VDD

V

0.7AVREF

AVREF

VDD

V

X1, X2

VDD − 0.5

V

Input voltage, low

P02^{Note 1}, P12, P13, P15

P00, P01, P10, P11, P14, RESET

P20 to P23^{Note 2}

0

0.3VDD

0.2VDD

0.3AVREF

0.4

V

X1, X2

V

Output voltage, high

Output voltage, low

Total of P00, P01, P10 to P15,

4.0 V ≤ V^DD≤ 5.5 V, V^DD− 1.0

I^OH= −4 mA

V

P130 pins

I^OH= −20 mA

I^OH= −100 µA

2.7 V ≤ VDD < 4.0 V VDD − 0.5

V

VOL

ILIH1

Total of P00, P01, P10 to P15,

4.0 V ≤ V^DD≤ 5.5 V,

I^OL= 8 mA

1.3

P130 pins

I^OL= 400 µA

VI = VDD

I^OL= 24 mA

2.7 V ≤ VDD < 4.0 V

0.4

10

V

Input leakage current, high

P00, P01, P10 to P15, RESET

µA

V^I= AVREF

VI = VDD

P20 to P23

10

I^LIH2

X1, X2^{Note 3}

20

Input leakage current, low

ILIL1

V^I= 0 V

P00, P01, P10 to P15, P20 to P23,

RESET

−10

I^LIL2

X1, X2^{Note 3}

−20

10

µA

kΩ

V

Output leakage current, high ILOH

Output leakage current, low ILOL

VO = VDD

VO = 0 V

VI = 0 V

−10

Pull-up resistance value

R

10

0

30

120

<R>

FLMD0 supply voltage

Flmd

In normal operation mode

0.2V^DD

(Flash memory version only)

Notes 1. When the internal high-speed oscillation clock is selected as the high-speed system clock, P02 can be

used as a port input pin.

2. When used as a digital input port, set AV^REF= VDD.

3. When the inverse input level of X1 is input to X2.

Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins.

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<R>

DC Characteristics (2/3): Flash Memory Version

(T^A= −40 to +110°C, 2.7 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ AVREF ≤ VDD, VSS = 0 V)

Parameter

Symbol

Conditions

MIN. TYP. MAX. Unit

7.8 16.2 mA

Crystal/

Supply

current^{Note 1}

IDD1

fXH = 10 MHz,

V^DD= 5.0 V 10%^{Note 3}

When A/D converter is stopped

ceramic oscillation

operating mode^{Notes 2, 6}

When A/D converter is

operating^{Note 4}

8.8 18.2 mA

fXH = 5 MHz,

V^DD= 3.0 V 10%^{Note 3}

When A/D converter is stopped

2.4

3.0

5.5

6.7

mA

When A/D converter is

operating^{Note 4}

Crystal/

IDD2

fXH = 10 MHz,

When peripheral functions are

stopped

1.7

4.6

7.5

mA

ceramic oscillation

HALT mode^{Note 6}

V^DD= 5.0 V 10%

When peripheral functions are

operating

f^XH= 5 MHz,

When peripheral functions are

stopped

0.48 1.4

2.5

V^DD= 3.0 V 10%

When peripheral functions are

operating

IDD3

External RC

fX = 4 MHz,

When A/D converter is stopped

4.5 10.3 mA

5.5 12.3 mA

oscillation operating V^DD= 5.0 V 10%

mode^{Notes 2, 7}

When A/D converter is

operating^{Note 4}

f^X= 4 MHz,

When A/D converter is stopped

2.4

3.0

5.5

6.7

mA

V^DD= 3.0 V 10%

When A/D converter is

operating^{Note 4}

IDD4

External RC

oscillation HALT

mode^{Note 7}

fX = 4 MHz,

When peripheral functions are

stopped

1.6

4.3

6.1

mA

V^DD= 5.0 V 10%

When peripheral functions are

operating

fX = 4 MHz,

When peripheral functions are

stopped

0.87 2.4

3.4

V^DD= 3.0 V 10%

When peripheral functions are

operating

IDD5

IDD6

Internal high-speed

f^XH= 8 MHz,

When A/D converter is stopped

6.9 15.2 mA

7.9 17.2 mA

oscillation operating V^DD= 5.0 V 10%

mode^{Notes 2, 8}

When A/D converter is

operating^{Note 4}

Internal high-speed

oscillation HALT

mode^{Note 8}

f^XH= 8 MHz,

When peripheral functions are

stopped

1.4

4.0

6.7

8.0

mA

V^DD= 5.0 V 10%

When peripheral functions are

operating

IDD7

IDD8

IDD9

Internal low-speed

oscillation operating

mode^{Note 5}

VDD = 5.0 V 10%

V^DD= 3.0 V 10%

1.8

mA

0.88 3.9

Internal low-speed

oscillation HALT

mode^{Note 5}

VDD = 5.0 V 10%

V^DD= 3.0 V 10%

0.08 1.12 mA

0.06 0.64 mA

STOP mode

VDD = 5.0 V 10% Internal low-speed oscillation: OFF

Internal low-speed oscillation: ON

3.5 800

17.5 900

3.5 400

11.0 500

µA

VDD = 3.0 V 10% Internal low-speed oscillation OFF

Internal low-speed oscillation: ON

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CHAPTER 24 ELECTRICAL SPECIFICATIONS ((A1) GRADE PRODUCTS)

Notes 1. Total current flowing through the internal power supply (VDD). Peripheral operation current is included

(however, the current that flows through the pull-up resistors of ports is not included).

2. Peripheral operation current is included.

3. When PCC = 00H.

4. Total of the current that flows through the V^DDpin and AVREF pin.

5. When high-speed system clock is stopped.

6. When crystal/ceramic oscillation is selected as the high-speed system clock using an option byte.

7. When an external RC is selected as the high-speed system clock using an option byte.

8. When an internal high-speed oscillation is selected as the high-speed system clock using an option byte.

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CHAPTER 24 ELECTRICAL SPECIFICATIONS ((A1) GRADE PRODUCTS)

DC Characteristics (3/3): Mask ROM Versions

(T^A= −40 to +110°C, 2.7 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ AVREF ≤ VDD, VSS = 0 V)

Parameter

Symbol

Conditions

MIN. TYP. MAX. Unit

6.1 12.7 mA

Crystal/

Supply

current^{Note 1}

IDD1

fXH = 10 MHz,

V^DD= 5.0 V 10%^{Note 3}

When A/D converter is stopped

ceramic oscillation

operating mode^{Notes 2, 6}

When A/D converter is

operating^{Note 4}

7.1 14.7 mA

fXH = 5 MHz,

V^DD= 3.0 V 10%^{Note 3}

When A/D converter is stopped

1.7

2.3

4.0

5.2

mA

When A/D converter is

operating^{Note 4}

Crystal/

IDD2

fXH = 10 MHz,

When peripheral functions are

stopped

1.6

4.4

7.3

mA

ceramic oscillation

HALT mode^{Note 6}

V^DD= 5.0 V 10%

When peripheral functions are

operating

f^XH= 5 MHz,

When peripheral functions are

stopped

0.41 1.36 mA

V^DD= 3.0 V 10%

When peripheral functions are

operating

2.5

mA

IDD3

External RC

fX = 4 MHz,

When A/D converter is stopped

3.2

4.2

7.2

9.2

mA

oscillation operating V^DD= 5.0 V 10%

mode^{Notes 2, 7}

When A/D converter is

operating^{Note 4}

f^X= 4 MHz,

When A/D converter is stopped

1.7

2.3

4.0

5.2

mA

V^DD= 3.0 V 10%

When A/D converter is

operating^{Note 4}

IDD4

External RC

oscillation HALT

mode^{Note 7}

fX = 4 MHz,

When peripheral functions are

stopped

1.6

4.3

6.1

mA

V^DD= 5.0 V 10%

When peripheral functions are

operating

fX = 4 MHz,

When peripheral functions are

stopped

0.87 2.4

3.4

V^DD= 3.0 V 10%

When peripheral functions are

operating

IDD5

IDD6

Internal high-speed

f^XH= 8 MHz,

When A/D converter is stopped

4.98 10.9 mA

5.98 12.9 mA

oscillation operating V^DD= 5.0 V 10%

mode^{Notes 2, 8}

When A/D converter is

operating^{Note 4}

Internal high-speed

oscillation HALT

mode^{Note 8}

f^XH= 8 MHz,

When peripheral functions are

stopped

1.24 3.6

6.3

mA

V^DD= 5.0 V 10%

When peripheral functions are

operating

IDD7

IDD8

IDD9

Internal low-speed

oscillation operating

mode^{Note 5}

VDD = 5.0 V 10%

V^DD= 3.0 V 10%

0.17 1.48 mA

0.11 0.84 mA

Internal low-speed

oscillation HALT

mode^{Note 5}

VDD = 5.0 V 10%

V^DD= 3.0 V 10%

0.04 0.96 mA

0.03 0.52 mA

STOP mode

VDD = 5.0 V 10% Internal low-speed oscillation: OFF

Internal low-speed oscillation: ON

3.5 800

17.5 900

3.5 400

11.0 500

µA

VDD = 3.0 V 10% Internal low-speed oscillation OFF

Internal low-speed oscillation: ON

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CHAPTER 24 ELECTRICAL SPECIFICATIONS ((A1) GRADE PRODUCTS)

Notes 1. Total current flowing through the internal power supply (VDD). Peripheral operation current is included

(however, the current that flows through the pull-up resistors of ports is not included).

2. Peripheral operation current is included.

3. When PCC = 00H.

4. Total of the current that flows through the V^DDpin and AVREF pin.

5. When high-speed system clock is stopped.

6. When crystal/ceramic oscillation is selected as the high-speed system clock using mask option.

7. When an external RC is selected as the high-speed system clock using mask option.

8. When an internal high-speed oscillation is selected as the high-speed system clock using mask option.

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AC Characteristics

(1) Basic operation (T^A= −40 to +110°C, 2.7 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ AVREF ≤ VDD, VSS = 0 V)

Parameter

Symbol

T^CY

Conditions

MIN.

0.2

TYP.

MAX.

16

Unit

µs

Instruction cycle

(minimum instruction

execution time)

Main

High- Crystal/ceramic 4.0 V ≤ VDD ≤ 5.5 V

speed oscillation clock

system

2.7 V ≤ V^DD< 4.0 V

0.4

16

µs

clock

system

External RC

2.7 V ≤ V^DD≤ 5.5 V 0.426

12.8

µs

operation clock

oscillation clock

Internal high-

speed

4.0 V ≤ V^DD≤ 5.5 V 0.217

0.25

8.33

4.7

µs

oscillation clock

<R>

Internal low-speed

oscillation clock

4.0 V ≤ VDD ≤ 5.5 V

2.7 V ≤ VDD ≤ 5.5 V 4.09

16.67

µs

TI00 input high-level

width, low-level width

tTIH0,

2/f^sam+

0.1^Note

t^TIL0

2.7 V ≤ V^DD< 4.0 V

2/f^sam+

0.2^Note

Interrupt input high-level tINTH,

1

width, low-level width

t^INTL

RESET low-level width

tRSL

10

Note Selection of fsam = fXH, fXH/4, or fXH/256 is possible using bits 0 and 1 (PRM000, PRM001) of prescaler mode

register 00 (PRM00). Note that when selecting the TI000 valid edge as the count clock, f^sam= fXH.

TCY vs. VDD (Main System Clock Operation)

20.0

16.67

10.0

µ

5.0

Guaranteed

operation range

2.0

1.0

0.4

0.2

0.1

5.5

0

1.0

2.0

3.0

4.0

5.0

6.0

2.7

Supply voltage V^DD[V]

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CHAPTER 24 ELECTRICAL SPECIFICATIONS ((A1) GRADE PRODUCTS)

(2) Serial interface (TA = −40 to +110°C, 2.7 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ AVREF ≤ VDD, VSS = 0 V)

(a) UART mode (UART6, dedicated baud rate generator output)

Parameter

Transfer rate

Symbol

Conditions

MIN.

TYP.

MAX.

312.5

Unit

kbps

(b) 3-wire serial I/O mode (SCK10... internal clock output)

Parameter

SCK10 cycle time

Symbol

Conditions

4.0 V ≤ VDD ≤ 5.5 V

2.7 V ≤ V^DD< 4.0 V

MIN.

200

MAX.

Unit

ns

tKCY1

400

ns

SCK10 high-/low-level width

tKH1,

t^KCY1/2 − 10

ns

t^KL1

SI10 setup time (to SCK10↑)

SI10 hold time (from SCK10↑)

tSIK1

tKSI1

t^KSO1

30

ns

Delay time from SCK10↓ to

C = 100 pF^Note

30

SO10 output

Note C is the load capacitance of the SCK10 and SO10 output lines.

(c) 3-wire serial I/O mode (SCK10... external clock input)

Parameter

SCK10 cycle time

Symbol

Conditions

MIN.

400

TYP.

MAX.

Unit

ns

tKCY2

SCK10 high-/low-level width

t^KH2,

t^KL2

t^KCY2/2

ns

SI10 setup time (to SCK10↑)

SI10 hold time (from SCK10↑)

tSIK2

tKSI2

t^KSO2

80

50

ns

Delay time from SCK10↓ to

C = 100 pF^Note

120

SO10 output

Note C is the load capacitance of the SO10 output line.

(3) Manchester code generator (T^A= −40 to +110°C, 2.7 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ AVREF ≤ VDD, VSS = 0 V)

(a) Dedicated baud rate generator output

Parameter

Transfer rate

Symbol

Conditions

MIN.

TYP.

MAX.

250.0

Unit

kbps

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CHAPTER 24 ELECTRICAL SPECIFICATIONS ((A1) GRADE PRODUCTS)

AC Timing Test Points (Excluding X1)

0.8VDD

0.2VDD

0.8VDD

0.2VDD

Test points

Clock Timing

1/f^XP

tXL

t

XH

V

IH4 (MIN.)

IL4 (MAX.)

X1

V

TI Timing

t

TIL0

tTIH0

TI00

Interrupt Request Input Timing

t^INTL

tINTH

INTP0 to INTP3

RESET Input Timing

tRSL

RESET

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CHAPTER 24 ELECTRICAL SPECIFICATIONS ((A1) GRADE PRODUCTS)

Serial Transfer Timing

3-wire serial I/O mode:

tKCYm

t

KLm

t

KHm

SCK10

t

SIKm

t

KSIm

SI10

Input data

t

KSOm

SO10

Output data

Remark m = 1, 2

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CHAPTER 24 ELECTRICAL SPECIFICATIONS ((A1) GRADE PRODUCTS)

A/D Converter Characteristics (TA = −40 to +110°C, 2.7 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ AVREF ≤ VDD, VSS = 0 V^{Note 1}

)

Parameter

Symbol

Conditions

MIN.

10

TYP.

10

MAX.

10

Unit

bit

Resolution

Overall error^{Notes 2, 3}

4.0 V ≤ AVREF ≤ 5.5 V

0.2

0.3

0.6

0.8

60

%FSR

µs

2.7 V ≤ AV^REF< 4.0 V

4.0 V ≤ AVREF ≤ 5.5 V

2.7 V ≤ AV^REF< 4.0 V

4.0 V ≤ AVREF ≤ 5.5 V

2.7 V ≤ AV^REF< 4.0 V

4.0 V ≤ AVREF ≤ 5.5 V

2.7 V ≤ AV^REF< 4.0 V

4.0 V ≤ AVREF ≤ 5.5 V

2.7 V ≤ AV^REF< 4.0 V

4.0 V ≤ AVREF ≤ 5.5 V

2.7 V ≤ AV^REF< 4.0 V

Conversion time

tCONV

14

19

60

µs

Zero-scale error^{Notes 2, 3}

Full-scale error^{Notes 2, 3}

Integral linearity error^{Note 2}

Differential linearity error^{Note 2}

Analog input voltage

0.6

0.8

0.6

0.8

4.5

6.5

2.0

2.5

AVREF

%FSR

LSB

V

Note 1

VSS

VAIN

Notes 1. VSS and AVSS are internally connected in the µPD780862 Subseries. The above specifications are for

when only the A/D converter is operating.

2. Excludes quantization error ( 1/2 LSB).

3. This value is indicated as a ratio (%FSR) to the full-scale value.

POC Circuit Characteristics (T^A= −40 to +110°C)

Parameter

Detection voltage

Symbol

VPOC

Conditions

MIN.

2.7

TYP.

2.85

MAX.

3.02

Unit

V

Power supply rise time

tPTH

VDD: 0 V → 2.7 V

0.0015

ms

Response delay time 1^{Note 1}

tPTHD

When power supply rises, after reaching

detection voltage (MAX.)

3.0

1.0

Response delay time 2^{Note 2}

Minimum pulse width

tPD

When VDD falls

ms

tPW

0.2

Notes 1. Time required from voltage detection to reset release.

2. Time required from voltage detection to internal reset output.

POC Circuit Timing

Supply voltage

(VDD

)

Detection voltage (MAX.)

Detection voltage (TYP.)

Detection voltage (MIN.)

t

PW

t

PTH

t

PTHD

tPD

Time

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CHAPTER 24 ELECTRICAL SPECIFICATIONS ((A1) GRADE PRODUCTS)

LVI Circuit Characteristics (TA = −40 to +110°C)

Parameter

Detection voltage

Symbol

VLVI0

VLVI1

VLVI2

VLVI3

VLVI4

VLVI5

VLVI6

tLD

Conditions

MIN.

4.1

TYP.

4.3

4.1

3.9

3.7

3.5

3.3

3.1

0.2

MAX.

4.52

4.32

4.12

3.92

3.72

3.47

3.27

2.0

Unit

V

3.9

V

3.7

V

3.5

V

3.3

V

3.15

2.95

V

Response time^{Note 1}

ms

Minimum pulse width

tLW

0.2

Operation stabilization wait time^{Note 2}tLWAIT

0.1

0.2

Notes 1. Time required from voltage detection to interrupt output or reset output.

2. Time required from setting LVION to 1 to operation stabilization.

Remarks 1. V^LVI0> VLVI1 > VLVI2 > VLVI3 > VLVI4 > VLVI5 > VLVI6

2. VPOC < VLVIm (m = 0 to 6)

LVI Circuit Timing

Supply voltage

(V^DD

)

Detection voltage (MAX.)

Detection voltage (TYP.)

Detection voltage (MIN.)

tLW

tWAIT

tLD

LVION ← 1

Time

Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics (T^A= −40 to +110°C)

Parameter

Symbol

VDDDR

tSREL

Conditions

MIN.

2.7

0

TYP.

MAX.

5.5

Unit

V

<R>

Data retention supply voltage

Release signal set time

µs

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CHAPTER 24 ELECTRICAL SPECIFICATIONS ((A1) GRADE PRODUCTS)

Flash Memory Programming Characteristics: Flash Memory Version

(T^A= 10 to 65°C, 3.0 V ≤ VDD ≤ 5.5 V, 3.0 V ≤ AVREF ≤ VDD, VSS = 0 V)

<R>

Parameter

VDD supply current

Symbol

IDD

Conditions

MIN.

TYP.

MAX.

30.5

Unit

mA

ms

s

fX = 10 MHz, VDD = 5.5 V

Step erase time

Chip unit

Terac

10

Sector unit

Chip unit

T^eras

Erase time^{Note 1}

Teraca

T^erasa

Twrw

2.55

500

100

Sector unit

s

Step write time

Write time

µs

Twrwa

Cerwr

µs

Number of rewrites per chip

1 erase + 1 write after erase = 1 rewrite^{Note 2}

Times

Notes 1. The prewrite time before erasure and the erase verify time (writeback time) are not included.

2. When a product is first written after shipment, “erase → write” and “write only” are both taken as one

rewrite.

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CHAPTER 25 ELECTRICAL SPECIFICATIONS ((A2) GRADE PRODUCTS)

<R>

Target products: µPD780861(A2), 780862(A2), 78F0862A(A2)

Absolute Maximum Ratings (T^A= 25°C)

Parameter

Supply voltage

Symbol

Conditions

Ratings

Unit

V

VDD

−0.3 to +6.5

VSS

−0.3 to +0.3

V

AV^REF

VI1

−0.3 to VDD + 0.3^Note

−0.3 to V^DD+ 0.3^Note

V

Input voltage

P00, P01, P10 to P15, P20 to P23, X1,

X2, RESET

V

Output voltage

VO

−0.3 to VDD + 0.3^Note

V

Analog input voltage

VAN

V^SS− 0.3 to AVREF + 0.3^Note

and −0.3 to V^DD+ 0.3^Note

Output current, high

Output current, low

IOH

IOL

T^A

Per pin

−7

mA

°C

Total of P00, P01, P10 to P15, P130 pins

Per pin

−21

14

Total of P00, P01, P10 to P15, P130 pins

In normal operation mode

In flash memory programming mode

Mask ROM versions

24.5

Operating ambient

temperature

−40 to +125

−40 to +85

−65 to +150

−40 to +150

<R>

Storage temperature

Tstg

°C

Flash memory version

Note Must be 6.5 V or lower.

Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any

parameter. That is, the absolute maximum ratings are rated values at which the product is on the

verge of suffering physical damage, and therefore the product must be used under conditions that

ensure that the absolute maximum ratings are not exceeded.

Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins.

400

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CHAPTER 25 ELECTRICAL SPECIFICATIONS ((A2) GRADE PRODUCTS)

Crystal/Ceramic Oscillator Characteristics (When Selecting Crystal/Ceramic Oscillation)

(T^A= −40 to +125°C, 2.7 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ AVREF ≤ VDD, VSS = 0 V)

Resonator

Recommended Circuit

Parameter

Conditions

MIN.

2.0

TYP. MAX.

Unit

Crystal resonator

Oscillation frequency

(f^XH)^Note

4.0 V ≤ VDD ≤ 5.5 V

2.7 V ≤ V^DD< 4.0 V

9.2

5.0

MHz

V

SS

X1

X2

2.0

C2

C1

Ceramic resonator

Oscillation frequency

(f^XH)^Note

4.0 V ≤ VDD ≤ 5.5 V

2.7 V ≤ VDD < 4.0 V

2.0

9.2

5.0

MHz

V

^SSX1

X2

C2

C1

X1

External clock

X1 input frequency

(f^XH)^Note

4.0 V ≤ VDD ≤ 5.5 V

2.7 V ≤ V^DD< 4.0 V

2.0

9.2

5.0

MHz

ns

X2

X1 input high-/low-

level width (t^XH, tXL)

4.0 V ≤ VDD ≤ 5.5 V

2.7 V ≤ V^DD< 4.0 V

51

96

250

<R>

Note Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time.

Caution When using the crystal/ceramic oscillator, wire as follows in the area enclosed by the broken lines

in the above figures to avoid an adverse effect from wiring capacitance.

• Keep the wiring length as short as possible.

• Do not cross the wiring with the other signal lines.

• Do not route the wiring near a signal line through which a high fluctuating current flows.

• Always make the ground point of the oscillator capacitor the same potential as V^SS.

• Do not ground the capacitor to a ground pattern through which a high current flows.

• Do not fetch signals from the oscillator.

Remark For the resonator selection and oscillator constant, users are required to either evaluate the oscillation

themselves or apply to the resonator manufacturer for evaluation.

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CHAPTER 25 ELECTRICAL SPECIFICATIONS ((A2) GRADE PRODUCTS)

External RC Oscillator Characteristics (When Selecting External RC Oscillation)

(T^A= −40 to +125°C, 2.7 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ AVREF ≤ VDD, VSS = 0 V)

Resonator

RC oscillation

Recommended Circuit

Parameter

Conditions

MIN.

3.0

TYP. MAX.

4.0

Unit

Oscillation frequency

(f^XH)^Note

MHz

V^SSCL1

CL2

R

C

External clock

X1 input frequency

(f^XH)^Note

4.0 V ≤ VDD ≤ 5.5 V

2.7 V ≤ VDD < 4.0 V

2.0

9.2

5.0

MHz

ns

X1

X2

X1 input high-/low-

level width (t^XH, tXL)

4.0 V ≤ VDD ≤ 5.5 V

2.7 V ≤ VDD < 4.0 V

51

96

250

<R>

Note Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time.

Caution When using the RC oscillator, wire as follows in the area enclosed by the broken lines in the above

figure to avoid an adverse effect from wiring capacitance.

• Keep the wiring length as short as possible.

• Do not cross the wiring with the other signal lines.

• Do not route the wiring near a signal line through which a high fluctuating current flows.

• Always make the ground point of the oscillator capacitor the same potential as V^SS.

• Do not ground the capacitor to a ground pattern through which a high current flows.

• Do not fetch signals from the oscillator.

External RC Oscillation Frequency Characteristics (When Selecting External RC Oscillation)

(T^A= −40 to +125°C, 2.7 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ AVREF ≤ VDD, VSS = 0 V)

Parameter

Conditions

MIN.

2.5

TYP. MAX.

Unit

Oscillation frequency

(f^XH)^Note

R = 6.8 kΩ, C = 22 pF

Target value: 3 MHz

3.0

3.5

MHz

R = 4.7 kΩ, C = 22 pF

3.5

4.0

4.7

MHz

Target value: 4 MHz

Note Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time.

Caution Set one of the above values to R and C.

Internal High-Speed Oscillator Characteristics (When Selecting Internal High-Speed Oscillation)

(T^A= −40 to +125°C, 4.0 V ≤ VDD ≤ 5.5 V, 4.0 V ≤ AVREF ≤ VDD, VSS = 0 V)

Resonator

Parameter

Conditions

MIN.

6.80

TYP. MAX.

8.00 9.20

Unit

Internal high-speed oscillator

Oscillation frequency (fXH)^Note

MHz

Note Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time.

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CHAPTER 25 ELECTRICAL SPECIFICATIONS ((A2) GRADE PRODUCTS)

Internal Low-Speed Oscillator Characteristics (TA = −40 to +125°C, 2.7 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ AVREF ≤ VDD, VSS = 0 V)

Resonator

Parameter

Conditions

MIN.

120

TYP. MAX.

240 495

Unit

kHz

Internal low-speed oscillator

Oscillation frequency (fR)^Note

Note Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time.

DC Characteristics (T^A= −40 to +125°C, 2.7 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ AVREF ≤ VDD, VSS = 0 V) (1/3)

Parameter

Symbol

Conditions

MIN.

TYP. MAX.

−3.5

Unit

mA

V

Output current, high

IOH

Per pin

4.0 V ≤ VDD ≤ 5.5 V

2.7 V ≤ V^DD< 4.0 V

4.0 V ≤ VDD ≤ 5.5 V

2.7 V ≤ V^DD< 4.0 V

Total of P00, P01, P10 to P15, P130

−17.5

−7

Output current, low

Input voltage, high

IOL

Per pin

7

Total of P00, P01, P10 to P15, P130

21

7

VIH1

VIH2

VIH3

V^IH4

VIL1

VIL2

VIL3

V^IL4

VOH

P02^{Note 1}, P12, P13, P15

P00, P01, P10, P11, P14, RESET

P20 to P23^{Note 2}

0.7VDD

VDD

0.8VDD

VDD

V

0.7AVREF

AVREF

VDD

V

X1, X2

VDD − 0.5

V

Input voltage, low

P02^{Note 1}, P12, P13, P15

P00, P01, P10, P11, P14, RESET

P20 to P23^{Note 2}

0

0.3VDD

0.2VDD

0.3AVREF

0.4

V

X1, X2

V

Output voltage, high

Output voltage, low

Total of P00, P01, P10 to P15,

4.0 V ≤ V^DD≤ 5.5 V, V^DD− 1.0

I^OH= −3.5 mA

V

P130 pins

I^OH= −17.5 mA

I^OH= −100 µA

2.7 V ≤ VDD < 4.0 V VDD − 0.5

V

VOL

ILIH1

Total of P00, P01, P10 to P15,

4.0 V ≤ V^DD≤ 5.5 V,

I^OL= 7 mA

1.3

P130 pins

I^OL= 400 µA

VI = VDD

I^OL= 21 mA

2.7 V ≤ VDD < 4.0 V

0.4

10

V

Input leakage current, high

P00, P01, P10 to P15, RESET

µA

V^I= AVREF

VI = VDD

P20 to P23

10

I^LIH2

X1, X2^{Note 3}

20

Input leakage current, low

ILIL1

V^I= 0 V

P00, P01, P10 to P15, P20 to P23,

RESET

−10

I^LIL2

X1, X2^{Note 3}

−20

10

µA

kΩ

V

Output leakage current, high ILOH

Output leakage current, low ILOL

VO = VDD

VO = 0 V

VI = 0 V

−10

Pull-up resistance value

R

10

0

30

120

<R>

FLMD0 supply voltage

Flmd

In normal operation mode

0.2V^DD

(Flash memory version only)

Notes 1. When the internal high-speed oscillation clock is selected as the high-speed system clock, P02 can be

used as a port input pin.

2. When used as a digital input port, set AV^REF= VDD.

3. When the inverse input level of X1 is input to X2.

Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins.

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CHAPTER 25 ELECTRICAL SPECIFICATIONS ((A2) GRADE PRODUCTS)

<R>

DC Characteristics (2/3) : Flash Memory Version

(T^A= −40 to +125°C, 2.7 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ AVREF ≤ VDD, VSS = 0 V)

Parameter

Symbol

Conditions

MIN. TYP. MAX. Unit

7.2 15.9 mA

Crystal/

Supply

current^{Note 1}

IDD1

fXH = 9.2 MHz,

V^DD= 5.0 V 10%^{Note 3}

When A/D converter is stopped

ceramic oscillation

operating mode^{Notes 2, 6}

When A/D converter is

operating^{Note 4}

8.2 17.9 mA

f^XH= 5 MHz,

V^DD= 3.0 V 10%^{Note 3}

When A/D converter is stopped

2.4

3.0

5.7

6.9

mA

When A/D converter is

operating^{Note 4}

Crystal/

IDD2

fXH = 9.2 MHz,

When peripheral functions are

stopped

1.7

4.7

7.4

mA

ceramic oscillation

HALT mode^{Note 6}

V^DD= 5.0 V 10%

When peripheral functions are

operating

f^XH= 5 MHz,

When peripheral functions are

stopped

0.48 1.6

2.7

V^DD= 3.0 V 10%

When peripheral functions are

operating

IDD3

External RC

fX = 4 MHz,

When A/D converter is stopped

4.5 10.7 mA

5.5 12.7 mA

oscillation operating V^DD= 5.0 V 10%

mode^{Notes 2, 7}

When A/D converter is

operating^{Note 4}

f^X= 4 MHz,

When A/D converter is stopped

2.4

3.0

5.7

6.9

mA

V^DD= 3.0 V 10%

When A/D converter is

operating^{Note 4}

IDD4

External RC

oscillation HALT

mode^{Note 7}

fX = 4 MHz,

When peripheral functions are

stopped

1.6

4.7

6.5

mA

V^DD= 5.0 V 10%

When peripheral functions are

operating

fX = 4 MHz,

When peripheral functions are

stopped

0.87 2.6

3.6

V^DD= 3.0 V 10%

When peripheral functions are

operating

IDD5

IDD6

Internal high-speed

f^XH= 8 MHz,

When A/D converter is stopped

6.9 15.6 mA

7.9 17.6 mA

oscillation operating V^DD= 5.0 V 10%

mode^{Notes 2, 8}

When A/D converter is

operating^{Note 4}

Internal high-speed

oscillation HALT

mode^{Note 8}

f^XH= 8 MHz,

When peripheral functions are

stopped

1.4

4.4

7.1

8.4

mA

V^DD= 5.0 V 10%

When peripheral functions are

operating

IDD7

IDD8

IDD9

Internal low-speed

oscillation operating

mode^{Note 5}

VDD = 5.0 V 10%

V^DD= 3.0 V 10%

1.8

mA

0.88 4.1

Internal low-speed

oscillation HALT

mode^{Note 5}

VDD = 5.0 V 10%

V^DD= 3.0 V 10%

0.08 1.52 mA

0.06 0.84 mA

STOP mode

VDD = 5.0 V 10% Internal low-speed oscillation: OFF

Internal low-speed oscillation: ON

3.5 1200 µA

17.5 1300 µA

VDD = 3.0 V 10% Internal low-speed oscillation OFF

Internal low-speed oscillation: ON

3.5 600

11.0 700

µA

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CHAPTER 25 ELECTRICAL SPECIFICATIONS ((A2) GRADE PRODUCTS)

Notes 1. Total current flowing through the internal power supply (VDD). Peripheral operation current is included

(however, the current that flows through the pull-up resistors of ports is not included).

2. Peripheral operation current is included.

3. When PCC = 00H.

4. Total of the current that flows through the V^DDpin and AVREF pin.

5. When high-speed system clock is stopped.

6. When crystal/ceramic oscillation is selected as the high-speed system clock using an option byte.

7. When an external RC is selected as the high-speed system clock using an option byte.

8. When an internal high-speed oscillation is selected as the high-speed system clock using an option byte.

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CHAPTER 25 ELECTRICAL SPECIFICATIONS ((A2) GRADE PRODUCTS)

DC Characteristics (3/3): Mask ROM Versions

(T^A= −40 to +125°C, 2.7 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ AVREF ≤ VDD, VSS = 0 V)

Parameter

Symbol

Conditions

MIN. TYP. MAX. Unit

5.3 11.6 mA

Crystal/

Supply

current^{Note 1}

IDD1

fXH = 9.2 MHz,

V^DD= 5.0 V 10%^{Note 3}

When A/D converter is stopped

<R>

ceramic oscillation

operating mode^{Notes 2, 6}

When A/D converter is

operating^{Note 4}

6.3 13.6 mA

f^XH= 5 MHz,

V^DD= 3.0 V 10%^{Note 3}

When A/D converter is stopped

1.7

2.3

4.2

5.4

mA

When A/D converter is

operating^{Note 4}

<R>

Crystal/

IDD2

fXH = 9.2 MHz,

When peripheral functions are

stopped

1.5

4.3

7.0

mA

ceramic oscillation

HALT mode^{Note 6}

V^DD= 5.0 V 10%

When peripheral functions are

operating

f^XH= 5 MHz,

When peripheral functions are

stopped

0.41 1.56 mA

V^DD= 3.0 V 10%

When peripheral functions are

operating

2.7

mA

IDD3

External RC

fX = 4 MHz,

When A/D converter is stopped

3.2

4.2

7.6

9.6

mA

oscillation operating V^DD= 5.0 V 10%

mode^{Notes 2, 7}

When A/D converter is

operating^{Note 4}

f^X= 4 MHz,

When A/D converter is stopped

1.7

2.3

4.2

5.4

mA

V^DD= 3.0 V 10%

When A/D converter is

operating^{Note 4}

IDD4

External RC

oscillation HALT

mode^{Note 7}

fX = 4 MHz,

When peripheral functions are

stopped

1.6

4.7

6.5

mA

V^DD= 5.0 V 10%

When peripheral functions are

operating

fX = 4 MHz,

When peripheral functions are

stopped

0.87 2.6

3.6

V^DD= 3.0 V 10%

When peripheral functions are

operating

IDD5

IDD6

Internal high-speed

f^XH= 8 MHz,

When A/D converter is stopped

4.98 11.3 mA

5.98 13.3 mA

oscillation operating V^DD= 5.0 V 10%

mode^{Notes 2, 8}

When A/D converter is

operating^{Note 4}

Internal high-speed

oscillation HALT

mode^{Note 8}

f^XH= 8 MHz,

When peripheral functions are

stopped

1.24 4.0

6.7

mA

V^DD= 5.0 V 10%

When peripheral functions are

operating

IDD7

IDD8

IDD9

Internal low-speed

oscillation operating

mode^{Note 5}

VDD = 5.0 V 10%

V^DD= 3.0 V 10%

0.17 1.88 mA

0.11 1.04 mA

Internal low-speed

oscillation HALT

mode^{Note 5}

VDD = 5.0 V 10%

V^DD= 3.0 V 10%

0.04 1.36 mA

0.03 0.72 mA

STOP mode

VDD = 5.0 V 10% Internal low-speed oscillation: OFF

Internal low-speed oscillation: ON

3.5 1200 µA

17.5 1300 µA

VDD = 3.0 V 10% Internal low-speed oscillation OFF

Internal low-speed oscillation: ON

3.5 600

11.0 700

µA

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CHAPTER 25 ELECTRICAL SPECIFICATIONS ((A2) GRADE PRODUCTS)

Notes 1. Total current flowing through the internal power supply (VDD). Peripheral operation current is included

(however, the current that flows through the pull-up resistors of ports is not included).

2. Peripheral operation current is included.

3. When PCC = 00H.

4. Total of the current that flows through the V^DDpin and AVREF pin.

5. When high-speed system clock is stopped.

6. When crystal/ceramic oscillation is selected as the high-speed system clock using mask option.

7. When an external RC is selected as the high-speed system clock using mask option.

8. When an internal high-speed oscillation is selected as the high-speed system clock using mask option.

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CHAPTER 25 ELECTRICAL SPECIFICATIONS ((A2) GRADE PRODUCTS)

AC Characteristics

(1) Basic operation (T^A= −40 to +125°C, 2.7 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ AVREF ≤ VDD, VSS = 0 V)

Parameter

Symbol

T^CY

Conditions

MIN.

TYP.

MAX.

16

Unit

µs

Instruction cycle

(minimum instruction

execution time)

Main

High- Crystal/ceramic 4.0 V ≤ VDD ≤ 5.5 V 0.217

speed oscillation clock

system

clock

2.7 V ≤ V^DD< 4.0 V

0.4

16

µs

system

External RC

2.7 V ≤ V^DD≤ 5.5 V 0.426

12.8

µs

operation clock

oscillation clock

Internal high-

speed

4.0 V ≤ V^DD≤ 5.5 V 0.217

0.25

8.33

4.7

µs

oscillation clock

<R>

Internal low-speed

oscillation clock

4.0 V ≤ VDD ≤ 5.5 V

2.7 V ≤ VDD ≤ 5.5 V 4.04

16.67

µs

TI00 input high-level

width, low-level width

tTIH0,

2/f^sam+

0.1^Note

t^TIL0

2.7 V ≤ V^DD< 4.0 V

2/f^sam+

0.2^Note

Interrupt input high-level tINTH,

1

width, low-level width

t^INTL

RESET low-level width

tRSL

10

Note Selection of fsam = fXH, fXH/4, or fXH/256 is possible using bits 0 and 1 (PRM000, PRM001) of prescaler mode

register 00 (PRM00). Note that when selecting the TI000 valid edge as the count clock, f^sam= fXH.

TCY vs. VDD (Main System Clock Operation)

20.0

16.67

10.0

µ

5.0

Guaranteed

operation range

2.0

1.0

0.4

0.217

0.2

0.1

5.5

0

1.0

2.0

3.0

4.0

5.0

6.0

2.7

Supply voltage V^DD[V]

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CHAPTER 25 ELECTRICAL SPECIFICATIONS ((A2) GRADE PRODUCTS)

(2) Serial interface (TA = −40 to +125°C, 2.7 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ AVREF ≤ VDD, VSS = 0 V)

(a) UART mode (UART6, dedicated baud rate generator output)

Parameter

Transfer rate

Symbol

Conditions

MIN.

TYP.

MAX.

312.5

Unit

kbps

(b) 3-wire serial I/O mode (SCK10... internal clock output)

Parameter

SCK10 cycle time

Symbol

Conditions

4.0 V ≤ VDD ≤ 5.5 V

2.7 V ≤ V^DD< 4.0 V

MIN.

200

MAX.

Unit

ns

tKCY1

400

ns

SCK10 high-/low-level width

tKH1,

t^KCY1/2 − 10

ns

t^KL1

SI10 setup time (to SCK10↑)

SI10 hold time (from SCK10↑)

tSIK1

tKSI1

t^KSO1

30

ns

Delay time from SCK10↓ to

C = 100 pF^Note

30

SO10 output

Note C is the load capacitance of the SCK10 and SO10 output lines.

(c) 3-wire serial I/O mode (SCK10... external clock input)

Parameter

SCK10 cycle time

Symbol

Conditions

MIN.

400

TYP.

MAX.

Unit

ns

tKCY2

SCK10 high-/low-level width

t^KH2,

t^KL2

t^KCY2/2

ns

SI10 setup time (to SCK10↑)

SI10 hold time (from SCK10↑)

tSIK2

tKSI2

t^KSO2

80

50

ns

Delay time from SCK10↓ to

C = 100 pF^Note

120

SO10 output

Note C is the load capacitance of the SO10 output line.

(3) Manchester code generator (T^A= −40 to +125°C, 2.7 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ AVREF ≤ VDD, VSS = 0 V)

(a) Dedicated baud rate generator output

Parameter

Transfer rate

Symbol

Conditions

MIN.

TYP.

MAX.

250.0

Unit

kbps

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CHAPTER 25 ELECTRICAL SPECIFICATIONS ((A2) GRADE PRODUCTS)

AC Timing Test Points (Excluding X1)

0.8VDD

0.2VDD

0.8VDD

0.2VDD

Test points

Clock Timing

1/f^XP

tXL

tXH

V

IH4 (MIN.)

IL4 (MAX.)

X1

V

TI Timing

t

TIL0

tTIH0

TI00

Interrupt Request Input Timing

t^INTL

tINTH

INTP0 to INTP3

RESET Input Timing

tRSL

RESET

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CHAPTER 25 ELECTRICAL SPECIFICATIONS ((A2) GRADE PRODUCTS)

Serial Transfer Timing

3-wire serial I/O mode:

tKCYm

t

KLm

t

KHm

SCK10

t

SIKm

t

KSIm

SI10

Input data

t

KSOm

SO10

Output data

Remark m = 1, 2

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CHAPTER 25 ELECTRICAL SPECIFICATIONS ((A2) GRADE PRODUCTS)

A/D Converter Characteristics (TA = −40 to +125°C, 2.7 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ AVREF ≤ VDD, VSS = 0 V^{Note 1}

)

Parameter

Symbol

Conditions

MIN.

10

TYP.

10

MAX.

10

Unit

bit

Resolution

Overall error^{Notes 2, 3}

4.0 V ≤ AVREF ≤ 5.5 V

0.2

0.3

0.7

0.9

48

%FSR

µs

2.7 V ≤ AV^REF< 4.0 V

4.0 V ≤ AVREF ≤ 5.5 V

2.7 V ≤ AV^REF< 4.0 V

4.0 V ≤ AVREF ≤ 5.5 V

2.7 V ≤ AV^REF< 4.0 V

4.0 V ≤ AVREF ≤ 5.5 V

2.7 V ≤ AV^REF< 4.0 V

4.0 V ≤ AVREF ≤ 5.5 V

2.7 V ≤ AV^REF< 4.0 V

4.0 V ≤ AVREF ≤ 5.5 V

2.7 V ≤ AV^REF< 4.0 V

Conversion time

tCONV

16

19

48

µs

Zero-scale error^{Notes 2, 3}

Full-scale error^{Notes 2, 3}

Integral linearity error^{Note 2}

Differential linearity error^{Note 2}

Analog input voltage

0.7

0.9

0.7

0.9

5.5

7.5

2.5

3.0

AVREF

%FSR

LSB

V

Note 1

VSS

VAIN

Notes 1. VSS and AVSS are internally connected in the µPD780862 Subseries. The above specifications are for

when only the A/D converter is operating.

2. Excludes quantization error ( 1/2 LSB).

3. This value is indicated as a ratio (%FSR) to the full-scale value.

POC Circuit Characteristics (T^A= −40 to +125°C)

Parameter

Detection voltage

Symbol

VPOC

Conditions

MIN.

2.7

TYP.

2.85

MAX.

3.06

Unit

V

Power supply rise time

tPTH

VDD: 0 V → 2.7 V

0.0015

ms

Response delay time 1^{Note 1}

tPTHD

When power supply rises, after reaching

detection voltage (MAX.)

3.0

1.0

Response delay time 2^{Note 2}

Minimum pulse width

tPD

When VDD falls

ms

tPW

0.2

Notes 1. Time required from voltage detection to reset release.

2. Time required from voltage detection to internal reset output.

POC Circuit Timing

Supply voltage

(V^DD

)

Detection voltage (MAX.)

Detection voltage (TYP.)

Detection voltage (MIN.)

tPW

tPTH

tPTHD

t

PD

Time

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CHAPTER 25 ELECTRICAL SPECIFICATIONS ((A2) GRADE PRODUCTS)

LVI Circuit Characteristics (TA = −40 to +125°C)

Parameter

Detection voltage

Symbol

VLVI0

VLVI1

VLVI2

VLVI3

VLVI4

VLVI5

VLVI6

tLD

Conditions

MIN.

4.1

TYP.

4.3

4.1

3.9

3.7

3.5

3.3

3.1

0.2

MAX.

4.56

4.36

4.16

3.96

3.76

3.51

3.31

2.0

Unit

V

3.9

V

3.7

V

3.5

V

3.3

V

3.15

2.95

V

Response time^{Note 1}

ms

Minimum pulse width

tLW

0.2

Operation stabilization wait time^{Note 2}tLWAIT

0.1

0.2

Notes 1. Time required from voltage detection to interrupt output or reset output.

2. Time required from setting LVION to 1 to operation stabilization.

Remarks 1. V^LVI0> VLVI1 > VLVI2 > VLVI3 > VLVI4 > VLVI5 > VLVI6

2. VPOC < VLVIm (m = 0 to 6)

LVI Circuit Timing

Supply voltage

(V^DD

)

Detection voltage (MAX.)

Detection voltage (TYP.)

Detection voltage (MIN.)

tLW

t

WAIT

t

LD

LVION ← 1

Time

Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics (T^A= −40 to +125°C)

Parameter

Symbol

VDDDR

tSREL

Conditions

MIN.

2.7

0

TYP.

MAX.

5.5

Unit

V

<R>

Data retention supply voltage

Release signal set time

µs

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CHAPTER 25 ELECTRICAL SPECIFICATIONS ((A2) GRADE PRODUCTS)

Flash Memory Programming Characteristics: Flash Memory Version

<R>

(T^A= 10 to 65°C, 3.0 V ≤ VDD ≤ 5.5 V, 3.0 V ≤ AVREF ≤ VDD, VSS = 0 V)

Parameter

VDD supply current

Symbol

IDD

Conditions

MIN.

TYP.

MAX.

30.5

Unit

mA

ms

s

fX = 10 MHz, VDD = 5.5 V

Step erase time

Chip unit

Terac

10

Sector unit

Chip unit

T^eras

Erase time^{Note 1}

Teraca

T^erasa

Twrw

2.55

500

100

Sector unit

s

Step write time

Write time

µs

Twrwa

Cerwr

µs

Number of rewrites per chip

1 erase + 1 write after erase = 1 rewrite^{Note 2}

Times

Notes 1. The prewrite time before erasure and the erase verify time (writeback time) are not included.

2. When a product is first written after shipment, “erase → write” and “write only” are both taken as one

rewrite.

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CHAPTER 26 PACKAGE DRAWING

20-PIN PLASTIC SSOP (7.62 mm (300))

20

11

detail of lead end

F

G

T

P

L

U

E

1

10

A

H

I

J

S

N

S

K

C

B

M

D

M

NOTE

ITEM MILLIMETERS

Each lead centerline is located within 0.13 mm of

its true position (T.P.) at maximum material condition.

A

B

C

6.65 0.15

0.475 MAX.

0.65 (T.P.)

+0.08

0.24

D

−0.07

E

F

G

H

I

0.1 0.05

1.3 0.1

1.2

8.1 0.2

6.1 0.2

1.0 0.2

0.17 0.03

0.5

J

K

L

M

N

0.13

0.10

+5°

3°

P

−3°

T

0.25

U

0.6 0.15

S20MC-65-5A4-2

415

User’s Manual U16418EJ3V0UD

CHAPTER 27 RECOMMENDED SOLDERING CONDITIONS

These products should be soldered and mounted under the following recommended conditions.

For soldering methods and conditions other than those recommended below, please contact an NEC Electronics

sales representative.

For technical information, see the following website.

Semiconductor Device Mount Manual (http://www.necel.com/pkg/en/mount/index.html)

Table 27-1. Surface Mounting Type Soldering Conditions (1/2)

(1) 20-pin plastic SSOP (7.62 mm (300))

µPD780861MC-×××-5A4, 780862MC-×××-5A4

µPD780861MC(A)-×××-5A4, 780862MC(A)-×××-5A4,

µPD780861MC(A1)-×××-5A4, 780862MC(A1)-×××-5A4,

µPD780861MC(A2)-×××-5A4, 780862MC(A2)-×××-5A4,

µPD78F0862MC-5A4, 78F0862AMC-5A4, 78F0862MC(A)-5A4, 78F0862AMC(A)-5A4,

µPD78F0862AMC(A1)-5A4, 78F0862AMC(A2)-5A4

<R>

Soldering Method

Infrared reflow

Soldering Conditions

Recommended

Condition Symbol

Package peak temperature: 235°C, Time: 30 seconds max. (at 210°C or higher),

Count: 3 times or less, Exposure limit: 7 days^Note(after that, prebake at 125°C for

20 to 72 hours)

IR35-207-3

VP15-207-3

WS60-207-1

Package peak temperature: 215°C, Time: 40 seconds max. (at 200°C or higher),

Count: 3 times or less, Exposure limit: 7 days^Note(after that, prebake at 125°C for

20 to 72 hours)

VPS

Wave soldering

Solder bath temperature: 260°C max., Time: 10 seconds max., Count: Once,

Preheating temperature: 120°C max. (package surface temperature), Exposure

limit: 7 days^{Note 2}(after that, prebake at 125°C for 20 to 72 hours)

Partial heating

Pin temperature: 350°C max., Time: 3 seconds max. (per pin row)

−

Note After opening the dry pack, store it at 25°C or less and 65% RH or less for the allowable storage period.

Caution Do not use different soldering methods together (except for partial heating).

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CHAPTER 27 RECOMMENDED SOLDERING CONDITIONS

Table 27-1. Surface Mounting Type Soldering Conditions (2/2)

(2) 20-pin plastic SSOP (7.62 mm (300))

<R>

µPD780861MC-×××-5A4-A, 780862MC-×××-5A4-A

µPD780861MC(A)-×××-5A4-A, 780862MC(A)-×××-5A4-A,

µPD780861MC(A1)-×××-5A4-A, 780862MC(A1)-×××-5A4-A,

µPD780861MC(A2)-×××-5A4-A, 780862MC(A2)-×××-5A4-A,

µPD78F0862MC-5A4-A, 78F0862AMC-5A4-A, 78F0862MC(A)-5A4-A, 78F0862AMC(A)-5A4-A,

µPD78F0862AMC(A1)-5A4-A, 78F0862AMC(A2)-5A4-A

Soldering Method

Infrared reflow

Soldering Conditions

Recommended

Condition Symbol

Package peak temperature: 260°C, Time: 30 seconds max. (at 220°C or higher),

Count: 3 times or less, Exposure limit: 7 days^Note(after that, prebake at 125°C for

20 to 72 hours)

IR60-207-3

Wave soldering

Partial heating

For details, contact an NEC Electronics sales representative.

−

Pin temperature: 350°C max., Time: 3 seconds max. (per pin row)

Note After opening the dry pack, store it at 25°C or less and 65% RH or less for the allowable storage period.

Caution Do not use different soldering methods together (except for partial heating).

Remark Products with -A at the end of the part number are lead-free products.

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CHAPTER 28 CAUTIONS FOR WAIT

28.1 Cautions for Wait

This product has two internal system buses.

One is a CPU bus and the other is a peripheral bus that interfaces with the low-speed peripheral hardware.

Because the clock of the CPU bus and the clock of the peripheral bus are asynchronous, unexpected illegal data

may be passed if an access to the CPU conflicts with an access to the peripheral hardware.

When accessing the peripheral hardware that may cause a conflict, therefore, the CPU repeatedly executes

processing until the correct data is passed.

As a result, the CPU does not start the next instruction processing but waits. If this happens, the number of

execution clocks of an instruction increases by the number of wait clocks (for the number of wait clocks, refer to Table

28-1). This must be noted when real-time processing is performed.

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CHAPTER 28 CAUTIONS FOR WAIT

28.2 Peripheral Hardware That Generates Wait

Table 28-1 lists the registers that issue a wait request when accessed by the CPU, and the number of CPU wait

clocks.

Table 28-1. Registers That Generate Wait and Number of CPU Wait Clocks

Peripheral Hardware

Watchdog timer

Register

Access

Number of Wait Clocks

3 clocks (fixed)

WDTM

ASIS6

ADM

ADS

Write

Read

Write

Read

Serial interface UART6

A/D converter

1 clock (fixed)

2 to 5 clocks^Note

(when ADM.5 flag = “1”)

2 to 9 clocks^Note

PFM

(when ADM.5 flag = “0”)

PFT

ADCR

1 to 5 clocks

(when ADM.5 flag = “1”)

1 to 9 clocks

(when ADM.5 flag = “0”)

2 f^CPU

・

＋1

fMACRO

*The result after the decimal point is truncated if it is less than t^CPULafter it has been multiplied by

(1/f^CPU), and is rounded up if it exceeds tCPUL.

f^MACRO:

Macro operating frequency

(When bit 5 (FR2) of ADM = “1”: f^X/2, when bit 5 (FR2) of ADM = “0”: fX/2²)

f^CPU:

CPU clock frequency

t^CPUL:

Low-level width of CPU clock

Note No wait cycle is generated for the CPU if the number of wait clocks calculated by the above expression is 1.

Remark The clock is the CPU clock (f^CPU).

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CHAPTER 28 CAUTIONS FOR WAIT

28.3 Example of Wait Occurrence

<1> Watchdog timer

Number of execution clocks: 8

(5 clocks when data is written to a register that does not issue a wait (MOV sfr, A).)

Number of execution clocks: 10

(7 clocks when data is written to a register that does not issue a wait (MOV sfr, #byte).)

<2> Serial interface UART6

Number of execution clocks: 6

(5 clocks when data is read from a register that does not issue a wait (MOV A, sfr).)

<3> A/D converter

Table 28-2. Number of Wait Clocks and Number of Execution Clocks on Occurrence of Wait (A/D Converter)

• When f^X= 10 MHz, tCPUL = 50 ns

Value of Bit 5 (FR2)

f^CPU

Number of Wait Clocks

9 clocks

Number of Execution Clocks

14 clocks

of ADM Register

0

1

fX

fX/2

fX/2²

fX/2³

fX/2⁴

fX

5 clocks

10 clocks

3 clocks

8 clocks

2 clocks

7 clocks

0 clocks (1 clock^Note

5 clocks

)

5 clocks (6 clocks^Note

10 clocks

)

fX/2

fX/2²

fX/2³

f^X/2⁴

3 clocks

8 clocks

2 clocks

7 clocks

0 clocks (1 clock^Note

)

5 clocks (6 clocks^Note

)

Note On execution of MOV A, ADCR

Remark The clock is the CPU clock (f^CPU).

f^X: High-speed system clock oscillation frequency

t^CPUL: Low-level width of CPU clock

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APPENDIX A DEVELOPMENT TOOLS

The following development tools are available for the development of systems that employ the µPD780862

Subseries.

Figure A-1 shows the development tool configuration.

•

Support for PC98-NX series

Unless otherwise specified, products supported by IBM PC/AT^TMcompatibles are compatible with PC98-NX

series computers. When using PC98-NX series computers, refer to the explanation for IBM PC/AT compatibles.

Windows

Unless otherwise specified, “Windows” means the following OSs.

•

Windows 3.1

Windows 95

Windows 98

Windows NT^TM

Windows 2000

Windows XP

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APPENDIX A DEVELOPMENT TOOLS

Figure A-1. Development Tool Configuration

Software package

• Software package

Debugging software

Language processing software

• Assembler package

• C compiler package

• Device file

• Integrated debugger

• System simulator

• C library source file^{Note 1}

Control software

• Project manager

(Windows only)^{Note 2}

Host machine (PC or EWS)

Interface adapter,

PC card interface, etc.

Power supply unit

In-circuit emulator^{Note 3}

Flash memory

write environment

Emulation board

Flash programmer

Flash memory

write adapter

Performance board

Flash memory

Emulation probe

Conversion socket or

conversion adapter

Target system

Notes 1. The C library source file is not included in the software package.

2. The project manage PM plus is included in the assembler package.

PM plus is only used for Windows.

3. Products other than in-circuit emulators IE-78K0-NS and IE-78K0-NS-A are all sold separately.

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APPENDIX A DEVELOPMENT TOOLS

A.1 Software Package

SP78K0

Development tools (software) common to the 78K/0 Series are combined in this package.

78K/0 Series software package

Part number: µS××××SP78K0

Remark ×××× in the part number differs depending on the host machine and OS used.

µS××××SP78K0

××××

AB17

BB17

Host Machine

PC-9800 series,

IBM PC/AT compatibles

OS

Supply Medium

Windows (Japanese version) CD-ROM

Windows (English version)

A.2 Language Processing Software

RA78K0

This assembler converts programs written in mnemonics into object codes executable

with a microcontroller.

Assembler package

This assembler is also provided with functions capable of automatically creating symbol

tables and branch instruction optimization.

This assembler should be used in combination with a device file (DF780862) (sold

separately).

This assembler package is a DOS-based application. It can also be used in Windows,

however, by using the Project Manager (included in assembler package) on Windows.

Part number: µS××××RA78K0

CC78K0

This compiler converts programs written in C language into object codes executable with

a microcontroller.

C compiler package

This compiler should be used in combination with an assembler package and device file

(both sold separately).

This C compiler package is a DOS-based application. It can also be used in Windows,

however, by using the Project Manager (included in assembler package) on Windows.

Part number: µS××××CC78K0

DF780862^{Note 1}

Device file

This file contains information peculiar to the device.

This device file should be used in combination with a tool (RA78K0, CC78K0, SM78K0,

ID78K0-NS, and ID78K0) (all sold separately).

The corresponding OS and host machine differ depending on the tool to be used.

Part number: µS××××DF780862

CC78K0-L^{Note 2}

This is a source file of the functions that configure the object library included in the C

compiler package.

C library source file

This file is required to match the object library included in the C compiler package to the

user’s specifications.

Since this is a source file, its operation environment does not depend on any particular

operating system.

Part number: µS××××CC78K0-L

Notes 1. The DF780862 can be used in common with the RA78K0, CC78K0, SM78K0, ID78K0-NS, and

ID78K0.

2. The CC78K0-L is not included in the software package (SP78K0).

User’s Manual U16418EJ3V0UD

423

APPENDIX A DEVELOPMENT TOOLS

Remark ×××× in the part number differs depending on the host machine and OS used.

µS××××RA78K0

µS××××CC78K0

××××

AB13

Host Machine

PC-9800 series,

OS

Supply Medium

Windows (Japanese version) 3.5-inch 2HD FD

Windows (English version)

IBM PC/AT compatibles

BB13

AB17

BB17

3P17

3K17

Windows (Japanese version) CD-ROM

Windows (English version)

HP9000 series 700^TM

SPARCstation^TM

HP-UX^TM(Rel. 10.10)

SunOS^TM(Rel. 4.1.4)

Solaris^TM(Rel. 2.5.1)

µS××××DF780862

µS××××CC78K0-L

××××

Host Machine

OS

Supply Medium

AB13

BB13

3P16

3K13

3K15

PC-9800 series,

Windows (Japanese version) 3.5-inch 2HD FD

Windows (English version)

IBM PC/AT compatibles

HP9000 series 700

SPARCstation

HP-UX (Rel. 10.10)

DAT

SunOS (Rel. 4.1.4)

Solaris (Rel. 2.5.1)

3.5-inch 2HD FD

1/4-inch CGMT

A.3 Control Software

PM plus

This is control software designed to enable efficient user program development in the

Windows environment. All operations used in development of a user program, such as

starting the editor, building, and starting the debugger, can be performed from PM plus.

<R>

Project manager

The project manager is included in the assembler package (RA78K0).

It can only be used in Windows.

A.4 Flash Memory Writing Tools

FlashPro4

Flash memory programmer dedicated to microcontrollers with on-chip flash memory.

(part number: FL-PR4, PG-FP4)

Flash memory programmer

FA-20MC-5A4-A

Flash memory writing adapter used connected to the FlashPro4.

20-pin plastic SSOP (MC-5A4 type)

<R>

Flash memory writing adapter

Remark FL-PR4 and FA-20MC-5A4-A are products of Naito Densei Machida Mfg. Co., Ltd.

TEL: +81-45-475-4191 Naito Densei Machida Mfg. Co., Ltd.

User’s Manual U16418EJ3V0UD

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APPENDIX A DEVELOPMENT TOOLS

A.5 Debugging Tools (Hardware)

IE-78K0-NS

The in-circuit emulator serves to debug hardware and software when developing

application systems using a 78K/0 Series product. It corresponds to the integrated

debugger (ID78K0-NS). This emulator should be used in combination with a power

supply unit, emulation probe, and the interface adapter required to connect this emulator

to the host machine.

In-circuit emulator

IE-78K0-NS-PA

This board is connected to the IE-78K0-NS to expand its functions. Adding this board

adds a coverage function and enhances debugging functions such as tracer and timer

functions.

Performance board

IE-78K0-NS-A

Product that combines the IE-78K0-NS and IE-78K0-NS-PA

In-circuit emulator

IE-70000-MC-PS-B

Power supply unit

This adapter is used for supplying power from a 100 V to 240 V AC outlet.

IE-70000-98-IF-C

Interface adapter

This adapter is required when using a PC-9800 series computer (except notebook type)

as the IE-78K0-NS(-A) host machine (C bus compatible).

IE-70000-CD-IF-A

PC card interface

This is PC card and interface cable required when using a notebook-type computer as

the IE-78K0-NS(-A) host machine (PCMCIA socket compatible).

IE-70000-PC-IF-C

Interface adapter

This adapter is required when using an IBM PC/AT compatible computer as the IE-78K0-

NS(-A) host machine (ISA bus compatible).

IE-70000-PCI-IF-A

Interface adapter

This adapter is required when using a computer with a PCI bus as the IE-78K0-NS(-A)

host machine.

IE-780862-NS-EM1

Emulation board

This board emulates the operations of the peripheral hardware peculiar to a device. It

should be used in combination with an in-circuit emulator.

NP-30MC

This probe is used to connect the in-circuit emulator to the target system and is designed

for use with a 30-pin plastic SSOP (MC-5A4 type).

Emulation probe

NSPACK20BK

This conversion socket connects the NP-30MC to a target system board designed to

mount a 20-pin plastic SSOP (MC-5A4 type).

YSPACK30BK

HSPACK30BK

YQ-Guide

• NSPACK20BK: Socket for connecting target

• YSPACK30BK: Socket for connecting emulator

• HSPACK30BK: Cover for mounting device

Conversion socket

• YQ-Guide:

Guide pin

Remarks 1. NP-30MC is a product of Naito Densei Machida Mfg. Co., Ltd.

TEL: +81-45-475-4191 Naito Densei Machida Mfg. Co., Ltd.

2. NSPACK20BK, YSPACK30BK, HSPACK30BK, and YQ-Guide are products of TOKYO ELETECH

CORPORATION.

For further information, contact Daimaru Kogyo Co., Ltd.

Tokyo Electronics Department (TEL: +81-3-3820-7112)

Osaka Electronics Department (TEL: +81-6-6244-6672)

User’s Manual U16418EJ3V0UD

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APPENDIX A DEVELOPMENT TOOLS

A.6 Debugging Tools (Software)

SM78K0

This system simulator is used to perform debugging at C source level or assembler level

while simulating the operation of the target system on a host machine.

This simulator runs on Windows.

System simulator

Use of the SM78K0 allows the execution of application logical testing and performance

testing on an independent basis from hardware development without having to use an in-

circuit emulator, thereby providing higher development efficiency and software quality.

The SM78K0 should be used in combination with a device file (DF780862) (sold

separately).

Part number: µS××××SM78K0

ID78K0-NS

This debugger is a control program used to debug 78K/0 Series microcontrollers. The

ID78K0-NS is Windows-based software.

Integrated debugger

(supporting in-circuit emulator

IE-78K0-NS, IE-78K0-NS-A)

It has an enhanced debugging function for C language programs, and thus trace results

can be displayed on screen at C-language level by using the windows integration

function which links a trace result with its source program, disassembled display, and

memory display.

It should be used in combination with a device file (sold separately).

Part number: µS××××ID78K0-NS

Remark ×××× in the part number differs depending on the host machine and OS used.

µS××××SM78K0

µS××××ID78K0-NS

××××

AB17

BB17

Host Machine

PC-9800 series,

IBM PC/AT compatibles

OS

Supply Medium

Windows (Japanese version) CD-ROM

Windows (English version)

User’s Manual U16418EJ3V0UD

426

APPENDIX B NOTES ON TARGET SYSTEM DESIGN

The following shows the conditions when connecting the emulation probe to the conversion adapter. Follow the

configuration below and consider the shape of parts to be mounted on the target system when designing a system.

Among the products described in this appendix, NP-30MC is a product of Naito Densei Machida Mfg. Co., Ltd., and

YSPACK30BK, NSPACK20BK, and YQ-Guide are products of TOKYO ELETECH CORPORATION.

Table B-1. Distance Between IE System and Conversion Adapter

Emulation Probe

NP-30MC

Conversion Adapter

YSPACK30BK

Distance Between IE System and Conversion Adapter

150 mm

NSPACK20BK

YQ-Guide

Figure B-1. Distance Between In-Circuit Emulator and Conversion Adapter

In-circuit emulator

IE-78K0-NS or IE-78K0-NS-A

Target system

Emulation board

150 mm

NP-30MC head PWB

CN1

Emulation probe NP-30MC

Conversion board

Conversion adapter

YSPACK30BK,

NSPACK20BK

IE-780862-NS-EM1 PROBE Board (20MC)

427

User’s Manual U16418EJ3V0UD

APPENDIX B NOTES ON TARGET SYSTEM DESIGN

Figure B-2. Connection Conditions of Target System

Emulation board

Emulation probe

NP-30MC

NP-30MC head PWB

Guide pin

YQ-Guide

13 mm

Conversion adapter

YSPACK30BK,

NSPACK20BK

5 mm

15 mm

31 mm

20 mm

37 mm

Target system

428

User’s Manual U16418EJ3V0UD

APPENDIX C REGISTER INDEX

C.1 Register Index (In Alphabetical Order with Respect to Register Names)

[A]

A/D conversion result register (ADCR) … 191

A/D converter mode register (ADM) … 189

Alternate-function pin switch register (PSEL) … 75, 157, 267, 277, 291

Analog input channel specification register (ADS) … 191

Asynchronous serial interface control register 6 (ASICL6) … 219

Asynchronous serial interface operation mode register 6 (ASIM6) … 213

Asynchronous serial interface reception error status register 6 (ASIS6) … 215

Asynchronous serial interface transmission status register 6 (ASIF6) … 216

[B]

Baud rate generator control register 6 (BRGC6) … 218

[C]

Capture/compare control register 00 (CRC00) … 107

Clock monitor mode register (CLM) … 318

Clock selection register 6 (CKSR6) … 217

[E]

8-bit timer compare register 50 (CR50) … 139

8-bit timer counter 50 (TM50) … 139

8-bit timer H carrier control register 1 (TMCYC1) … 157

8-bit timer H compare register 00 (CMP00) … 151

8-bit timer H compare register 01 (CMP01) … 151

8-bit timer H compare register 10 (CMP10) … 151

8-bit timer H compare register 11 (CMP11) … 151

8-bit timer H mode register 0 (TMHMD0) … 152

8-bit timer H mode register 1 (TMHMD1) … 152

8-bit timer mode control register 50 (TMC50) … 142

External interrupt falling edge enable register (EGN) … 289

External interrupt rising edge enable register (EGP) … 289

[I]

Input switch control register (ISC) … 220, 291

Internal low-speed oscillation mode register (RCM) … 81

Internal memory size switching register (IMS) … 342

Interrupt mask flag register 0H (MK0H) … 287

Interrupt mask flag register 0L (MK0L) … 287

Interrupt mask flag register 1L (MK1L) … 287

Interrupt request flag register 0H (IF0H) … 286

Interrupt request flag register 0L (IF0L) … 286

Interrupt request flag register 1L (IF1L) … 286

429

User’s Manual U16418EJ3V0UD

APPENDIX C REGISTER INDEX

[L]

Low-voltage detection level selection register (LVIS) … 330

Low-voltage detection register (LVIM) … 329

[M]

Main clock mode register (MCM) … 82

Main OSC control register (MOC) … 83

MCG control register 0 (MC0CTL0) … 259, 262, 263, 273

MCG control register 1 (MC0CTL1) … 260, 264, 274

MCG control register 2 (MC0CTL2) … 261, 265, 275

MCG status register (MC0STR) … 261

MCG transmit bit count specification register (MC0BIT) … 258

MCG transmit buffer register (MC0TX) … 257

[O]

Oscillation stabilization time counter status register (OSTC) … 84, 301

Oscillation stabilization time select register (OSTS) … 85, 302

[P]

Port mode register 0 (PM0) … 71, 110, 267, 277

Port mode register 1 (PM1) … 71, 158, 220, 248, 267, 277

Port register 0 (P0) … 73

Port register 1 (P1) … 73

Port register 13 (P13) … 73

Port register 2 (P2) … 73

Power-fail comparison mode register (PFM) … 192

Power-fail comparison threshold register (PFT) … 192

Prescaler mode register 00 (PRM00) … 109

Priority specification flag register 0H (PR0H) … 288

Priority specification flag register 0L (PR0L) … 288

Priority specification flag register 1L (PR1L) … 288

Processor clock control register (PCC) … 80

Pull-up resistor option register 0 (PU0) … 74

Pull-up resistor option register 1 (PU1) … 74

[R]

Receive buffer register 6 (RXB6) … 212

Reset control flag register (RESF) … 316

[S]

Serial clock selection register 10 (CSIC10) … 247

Serial I/O shift register 10 (SIO10) … 245

Serial operation mode register 10 (CSIM10) … 246, 249

16-bit timer capture/compare register 000 (CR000) … 102

16-bit timer capture/compare register 010 (CR010) … 104

16-bit timer counter 00 (TM00) … 102

User’s Manual U16418EJ3V0UD

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APPENDIX C REGISTER INDEX

16-bit timer mode control register 00 (TMC00) … 105

16-bit timer output control register 00 (TOC00) … 107

[T]

Timer clock selection register 50 (TCL50) … 140

Timer clock switch control register (CSEL) … 141, 156

Transmit buffer register 10 (SOTB10) … 245

Transmit buffer register 6 (TXB6) … 212

[W]

Watchdog timer enable register (WDTE) … 179

Watchdog timer mode register (WDTM) … 177

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431

APPENDIX C REGISTER INDEX

C.2 Register Index (In Alphabetical Order with Respect to Register Symbol)

[A]

ADCR:

ADM:

A/D conversion result register … 191

A/D converter mode register … 189

ADS:

Analog input channel specification register … 191

Asynchronous serial interface control register 6 … 219

Asynchronous serial interface transmission status register 6 … 216

Asynchronous serial interface operation mode register 6 … 213

Asynchronous serial interface reception error status register 6 … 215

ASICL6:

ASIF6:

ASIM6:

ASIS6:

[B]

BRGC6:

Baud rate generator control register 6 … 218

[C]

CKSR6:

CLM:

Clock selection register 6 … 217

Clock monitor mode register … 318

CMP00:

CMP01:

CMP10:

CMP11:

CR000:

CR010:

CR50:

8-bit timer H compare register 00 … 151

8-bit timer H compare register 01 … 151

8-bit timer H compare register 10 … 151

8-bit timer H compare register 11 … 151

16-bit timer capture/compare register 000 … 102

16-bit timer capture/compare register 010 … 104

8-bit timer compare register 50 … 139

Capture/compare control register 00 … 107

Timer clock switch control register … 141, 156

Serial clock selection register 10 … 247

Serial operation mode register 10 … 246, 249

CRC00:

CSEL:

CSIC10:

CSIM10:

[E]

EGN:

EGP:

External interrupt falling edge enable register … 289

External interrupt rising edge enable register … 289

[I]

IF0H:

IF0L:

IF1L:

IMS:

ISC:

Interrupt request flag register 0H … 286

Interrupt request flag register 0L … 286

Interrupt request flag register 1L … 286

Internal memory size switching register … 342

Input switch control register … 220, 291

[L]

LVIM:

LVIS:

Low-voltage detection register … 329

Low-voltage detection level selection register … 330

[M]

MC0BIT:

MC0CTL0:

MC0CTL1:

MCG transmit bit count specification register … 258

MCG control register 0 … 259, 262, 263, 273

MCG control register 1 … 260, 264, 274

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APPENDIX C REGISTER INDEX

MC0CTL2:

MC0STR:

MC0TX:

MCM:

MCG control register 2 … 261, 265, 275

MCG status register … 261

MCG transmit buffer register … 257

Main clock mode register … 82

Interrupt mask flag register 0H … 287

Interrupt mask flag register 0L … 287

Interrupt mask flag register 1L … 287

Main OSC control register … 83

MK0H:

MK0L:

MK1L:

MOC:

[O]

OSTC:

OSTS:

Oscillation stabilization time counter status register … 84, 301

Oscillation stabilization time select register … 85, 302

[P]

P0:

Port register 0 … 73

P1:

Port register 1 … 73

P13:

Port register 13 … 73

P2:

Port register 2 … 73

PCC:

PFM:

PFT:

PM0:

PM1:

PR0H:

PR0L:

PR1L:

PRM00:

PSEL:

PU0:

PU1:

Processor clock control register … 80

Power-fail comparison mode register … 192

Power-fail comparison threshold register … 192

Port mode register 0 … 71, 110, 267, 277

Port mode register 1 … 71, 158, 220, 248, 267, 277

Priority specification flag register 0H … 288

Priority specification flag register 0L … 288

Priority specification flag register 1L … 288

Prescaler mode register 00 … 109

Alternate-function pin switch register … 75, 157, 267, 277, 291

Pull-up resistor option register 0 … 74

Pull-up resistor option register 1 … 74

[R]

RCM:

RESF:

RXB6:

Internal low-speed oscillation mode register … 81

Reset control flag register … 316

Receive buffer register 6 … 212

[S]

SIO10:

SOTB10:

Serial I/O shift register 10 … 245

Transmit buffer register 10 … 245

[T]

TCL50:

TM00:

Timer clock selection register 50 … 140

16-bit timer counter 00 … 102

TM50:

8-bit timer counter 50 … 139

TMC00:

TMC50:

TMCYC1:

TMHMD0:

16-bit timer mode control register 00 … 105

8-bit timer mode control register 50 … 142

8-bit timer H carrier control register 1 … 157

8-bit timer H mode register 0 … 152

User’s Manual U16418EJ3V0UD

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APPENDIX C REGISTER INDEX

TMHMD1:

TOC00:

TXB6:

8-bit timer H mode register 1 … 152

16-bit timer output control register 00 … 107

Transmit buffer register 6 … 212

[W]

WDTE:

WDTM:

Watchdog timer enable register … 179

Watchdog timer mode register … 177

User’s Manual U16418EJ3V0UD

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APPENDIX D REVISION HISTORY

D.1 Major Revisions in This Edition

(1/3)

Page

Description

Throughout

Addition of the following part numbers

µPD780861MC-×××-5A4-A, 780862MC-×××-5A4-A, 780861MC(A)-×××-5A4-A, 780862MC(A)-×××-5A4,

780861MC(A1)-×××-5A4-A, 780862MC(A1)-×××-5A4-A, 780861MC(A2)-×××-5A4-A, 780862MC(A2)-×××-

5A4-A, 78F0862MC-5A4-A, 78F0862AMC-5A4, 78F0862AMC-5A4-A, 78F0862MC(A)-5A4-A,

78F0862AMC(A)-5A4, 78F0862AMC(A)-5A4-A, 78F0862AMC(A1)-5A4, 78F0862AMC(A1)-5A4-A,

78F0862AMC(A2)-5A4, 78F0862AMC(A2)-5A4-A

p.15

p.21

Addition of Note to 1.1 Features

Addition of description of (A1) grade products and (2) grade products, and Note 2 to High-speed system

clock (oscillation frequency) in 1.6 Outline of Functions

p.45

p.65

p.76

p.85

Modification of description on Symbol in 3.2.3 Special function registers (SFRs)

Modification of Caution in 4.2.2 Port 1

Addition of 4.3 (5) Input switch control register (ISC)

Addition of Cautions 1 and 2 to Figure 5-7 Format of Oscillation Stabilization Time Select Register

(OSTS)

p.106

Addition of description of <When used as capture register> to Interrupt request generation in Figure 6-5

Format of 16-Bit Timer Mode Control Register 00 (TMC00).

p.109

Modification of Caution 4 in Figure 6-8 Format of Prescaler Mode Register 00 (PRM00)

6.4.6 One-shot pulse output operation

pp.130, 132

• Modification of Caution 1 in (1) One-shot pulse output with software trigger

• Modification of Caution in (2) One-shot pulse output with external trigger

p.135

p.137

Modification of (a) One-shot pulse output by software and (b) One-shot pulse output with external

trigger in (5) Re-triggering one-shot pulse in 6.5 Cautions for 16-Bit Timer/Event Counter 00

Modification of description on <1> in (11) Edge detection in 6.5 Cautions for 16-Bit Timer/Event Counter

00

p.141

p.156

p.157

Addition of Remark 2 to Figure 7-5 Format of Timer Clock Switch Control Register (CSEL)

Addition of Remark 3 to Figure 8-7 Format of Timer Clock Switch Control Register (CSEL)

Modification of description on RMC1 bit and NRZB bit in Figure 8-8 Format of 8-Bit Timer H Carrier

Control Register 1 (TMCYC1)

p.161

Modification of (c) Operation when CMP0n = 00H in Figure 8-12 Timing of Interval Timer/Square-Wave

Output Operation

p.168

p.175

p.178

Modification of description on RMC1 bit and NRZB bit in 8.4.3 (2) Carrier output control

Modification of Table 9-1 Loop Detection Time of Watchdog Timer

Modification of description on the overflow time setting in Figure 9-2 Format of Watchdog Timer Mode

Register (WDTM)

p.193

p.219

Modification of 10.4.1 Basic operations of A/D converter

Modification of Caution 1 in Figure 11-10 Format of Asynchronous Serial Interface Control Register 6

(ASICL6)

p.246

p.247

p.249

p.253

Modification of Note 2 in Figure 12-2 Format of Serial Operation Mode Register 10 (CSIM10)

Modification of Caution 3 in Figure 12-3 Format of Serial Clock Selection Register 10 (CSIC10)

Modification of Note 1 in 12.4.1 (1) (a) Serial operation mode register 10 (CSIM10)

Modification of (b) Type 2 and (d) Type 4 in Figure 12-6 Timing of Clock/Data Phase

435

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APPENDIX D REVISION HISTORY

(2/3)

Page

Description

p.258

p.268

Addition of Remark to 13.2 (2) MCG transmit bit count specification register (MC0BIT)

Addition of 14.4.2 (3) Format of “0” and “1” of Manchester code output

p.271, 272

Modification of (3) Transmit timing (MC0OLV = 1, total transmit bit length = 13 bits) and (4) Transmit

timing (MC0OLV = 0, total transmit bit length = 13 bits) in Figure 13-8 Timing of Manchester Code

Generator Mode (LSB First)

p.280, 281

Modification of (3) Transmit timing (MC0OLV = 1, total transmit bit length = 13 bits) and (4) Transmit

timing (MC0OLV = 0, total transmit bit length = 13 bits) in Figure 13-9 Timing of Bit Sequential Buffer

Mode (LSB First)

p.283

p.299

p.302

Modification of description on INTTM00 and INTTM01 in Table 14-1 Interrupt Source List

Modification of Table 15-1 Relationship Between Operation Clocks in Each Operation Status

Addition of Cautions 1 and 2 to Figure 15-2 Format of Oscillation Stabilization Time Select Register

(OSTS)

p.305

Modification of (2) (b) Release by reset signal (reset by RESET input, POC, LVI, clock monitor, or WDT )

in 15.2.1 HALT mode

p.308

Modification of (2) (b) Release by reset signal (reset by RESET input, POC, LVI, clock monitor, or WDT )

in 15.2.2 STOP mode

p.315

Addition of description of WDTRF, CLMRF, and LVIRF to the table of Note in Table 16-1 Hardware

Statuses After Reset

p.341

Modification of Caution 2 to Table 21-1 Differences Between µPD78F0862, 78F0862A and Mask ROM

Versions

pp.347, 348

Modification of Transfer rate in 21.4 (1) CSI10, (2) CSI communication mode supporting handshake, and

(3) UART6 Figure, and addition of Note to 21.4 (3) UART6

p.355

Modification of Table 21-7 Communication Modes

pp.370 to 373,

383, 384

Modification or addition of the following contents in or to CHAPTER 23 ELECTRICAL SPECIFICATIONS

(STANDARD PRODUCTS, (A) GRADE PRODUCTS)

• Addition of µPD78F0862A and 78F0862A(A) in Target products

• Modification of Max. value of X1 input high-/low-level width (tXH, tXL) of the external clock

• Addition of Note 1 to DC Characteristics (1/3)

• Modification of Min. value of Data retention supply voltage

• Flash Memory Programming Characteristics

Modification of VDD supply current (IDD) in, and addition of Note 3 to (1) µPD78F0862, 78F0862(A)

Addition of (2) µPD78F0862A, 78F0862A(A)

pp.385 to 389,

393, 398, 399

Modification or addition of the following contents in or to CHAPTER 24 ELECTRICAL SPECIFICATIONS

((A1) GRADE PRODUCTS)

• Addition of µPD78F0862A(A1) in Target products, and the item of Flash memory version

• Modification of Max. value of X1 input high-/low-level width (tXH, tXL) of the external clock

• Addition of FLMD0 supply voltage and Note 1 to DC Characteristics (1/3)

• Modification of Instruction cycle when Internal low-speed oscillation clock is operating as Main system clock

in AC Characteristics

• Modification of Min. value of Data retention supply voltage

• Addition of Flash Memory Programming

436

User’s Manual U16418EJ3V0UD

APPENDIX D REVISION HISTORY

(3/3)

Page

Description

pp.400 to 404,

406, 408, 413,

414

Modification or addition of the following contents in or to CHAPTER 25 ELECTRICAL SPECIFICATIONS

((A2) GRADE PRODUCTS)

• Addition of µPD78F0862A(A2) in Target products, and the item of Flash memory version

• Modification of Max. value of X1 input high-/low-level width (tXH, tXL) of the external clock

• Addition of FLMD0 supply voltage and Note 1 to DC Characteristics (1/3)

• Addition of the value of IDD1 and IDD2 to DC Characteristics (3/3)

• Modification of Instruction cycle when Internal low-speed oscillation clock is operating as Main system clock

in AC Characteristics

• Modification of Min. value of Data retention supply voltage

• Addition of Flash Memory Programming

pp.416, 417

p.424

Modification of Table 27-1 Surface Mounting Type Soldering Conditions

Addition of “PM plus” to A.3 Control Software, and modification of the part number of the flash memory

writing adapter in A.4 Flash Memory Writing Tools

p.438

Addition of D.2 Revision History of Preceding Editions

437

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APPENDIX D REVISION HISTORY

<R>

D.2 Revision History of Preceding Editions

Here is the revision history of the preceding editions. Chapter indicates the chapter of each edition.

(1/7)

Edition

Description

Chapter

Throughout

2nd edition The following packages have been changed from under development to in mass-

production.

µPD780861MC(A)-×××-5A4, 780862MC(A)-×××-5A4, 780861MC(A1)-×××-5A4,

µPD780862MC(A1)-×××-5A4, 780861MC(A2)-×××-5A4, 780862MC(A2)-×××-5A4

Addition of µPD78F0862MC-5A4

Addition of Note and description on operating ambient temperature to 1.1 Features

Addition of Note 3 to 1.4 Pin Configuration (Top View)

Addition of Note 3 to 1.5 Block Diagram

CHAPTER 1 OUTLINE

Addition of Note to 1.6 Outline of Functions

Addition of Table 2-1 Pin I/O Buffer Power Supplies

Addition of Note 1 to 2.1 (1) Port pins

CHAPTER 2 PIN

FUNCTIONS

Modification of description on AVREF in 2.1 (2) Non-port pins

Addition of Caution to 2.2.1 P00 to P02 (port 0)

Addition of description to 2.2.11 FLMD0 and FLMD1 (flash memory version only)

Addition of Note 1 to Table 2-2 Pin I/O Circuit Types

Modification of figure in Figure 3-3 Memory Map (µPD78F0862)

CHAPTER 3 CPU

ARCHITECTURE

Addition of (3) Option byte area (flash memory version only) to 3.1.1 Internal

program memory space

Modification of figure in Figure 3-10 Data to Be Saved to Stack Memory

Modification of figure in Figure 3-11 Data to Be Restored from Stack Memory

Modification of [Description example] in 3.4.4 Short direct addressing

Addition of [Illustration] to 3.4.7 Based addressing

Addition of [Illustration] to 3.4.8 Based indexed addressing

Addition of [Illustration] to 3.4.9 Stack addressing

Addition of Table 4-1 Pin I/O Buffer Power Supplies

Addition of Note 1 to Table 4-2 Port Functions

CHAPTER 4 PORT

FUNCTIONS

Addition of Caution to 4.2.1 Port 0

Modification of Figure 4-6 Block Diagram of P12

Modification of Figure 4-7 Block Diagram of P13

Modification of Cautions 2 and 3 in 4.3 (1) Port mode registers (PM0 and PM1)

Addition of 4.3 (2) Port registers (P0 to P2, P13)

Addition of description to 4.4.1 (1) Output mode

Addition of description to 4.4.3 (1) Output mode and modification of description in

(2) Input mode

Modification of Figure 5-2 Format of Processor Clock Control Register (PCC)

CHAPTER 5 CLOCK

GENERATOR

Modification of Table 5-2 Relationship Between CPU Clock and Minimum

Instruction Execution Time

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User’s Manual U16418EJ3V0UD

APPENDIX D REVISION HISTORY

(2/7)

Edition

Description

Chapter

2nd edition Addition of Cautions 2 and 3 to Figure 5-6 Format of Oscillation Stabilization

CHAPTER 5 CLOCK

GENERATOR

Time Counter Status Register (OSTC)

Modification of Table 5-5 Maximum Time Required to Switch Between Internal

Low-Speed Oscillation Clock and High-Speed System Clock

Addition of 5.7 Time Required for CPU Clock Switchover

Modification of Table 6-1 Configuration of 16-Bit Timer/Event Counter 00

Modification of Figure 6-1 Block Diagram of 16-Bit Timer/Event Counter 00

Addition of Figure 6-2 Format of 16-Bit Timer Counter 00 (TM00)

CHAPTER 6 16-BIT

TIMER/EVENT COUNTER

00

Modification of description in 6.2 (2) 16-bit timer capture/compare register 000

(CR000)

Addition of Figure 6-3 Format of 16-Bit Timer Capture/Compare Register 000

(CR000)

Modification of Table 6-2 CR000 Capture Trigger and Valid Edges of TI000 and

TI010 Pins

Modification of description in 6.2 (3) 16-bit timer capture/compare register 010

(CR010)

Modification of Table 6-3 CR010 Capture Trigger and Valid Edge of TI000 Pin

(CRC002 = 1)

Addition of Caution 3 to Figure 6-6 Format of Capture/Compare Control Register

00 (CRC00)

Modification of Caution 5 and addition of Cautions 6 and 7 in Figure 6-7 Format of

16-Bit Timer Output Control Register 00 (TOC00)

Addition of Caution 1 to Figure 6-8 Format of Prescaler Mode Register 00

(PRM00)

Addition of description to 6.3 (5) Port mode register 0 (PM0)

Modification of description in 6.4.1 Interval timer operation

Addition of Figure 6-10 (c) Prescaler mode register 00 (PRM00)

Modification of Figure 6-12 Timing of Interval Timer Operation

Modification of description in 6.4.2 PPG output operation

Addition of Figure 6-13 (d) Prescaler mode register 00 (PRM00)

Modification of Figure 6-15 PPG Output Operation Timing

Modification of description in 6.4.3 Pulse width measurement operation

Modification of description in 6.4.3 (1) Pulse width measurement with free-running

counter and one capture register

Addition of Figure 6-17 (c) Prescaler mode register 00 (PRM00)

Addition of Note to Figure 6-19 Timing of Pulse Width Measurement Operation

with Free-Running Counter and One Capture Register (with Both Edges

Specified)

Modification of description in 6.4.3 (2) Measurement of two pulse widths with free-

running counter

Addition of Figure 6-20 (c) Prescaler mode register 00 (PRM00)

Addition of Note to Figure 6-21 Timing of Pulse Width Measurement Operation

with Free-Running Counter (with Both Edges Specified)

Addition of Figure 6-22 (c) Prescaler mode register 00 (PRM00)

439

User’s Manual U16418EJ3V0UD

APPENDIX D REVISION HISTORY

(3/7)

Edition

Description

Chapter

2nd edition Addition of Note to Figure 6-23 Timing of Pulse Width Measurement Operation

with Free-Running Counter and Two Capture Registers (with Rising Edge

Specified)

CHAPTER 6 16-BIT

TIMER/EVENT COUNTER

00

Addition of Figure 6-24 (c) Prescaler mode register 00 (PRM00)

Modification of description in 6.4.4 External event counter operation

Addition of Figure 6-26 (c) Prescaler mode register 00 (PRM00)

Modification of Figure 6-27 Configuration Diagram of External Event Counter

Modification of description in 6.4.5 Square-wave output operation

Addition of Figure 6-29 (d) Prescaler mode register 00 (PRM00)

Modification of description in 6.4.6 One-shot pulse output operation

Modification of Note in 6.4.6 (1) One-shot pulse output with software trigger

Addition of Figure 6-31 (d) Prescaler mode register 00 (PRM00)

Modification of Note in 6.4.6 (2) One-shot pulse output with external trigger

Addition of Figure 6-33 (d) Prescaler mode register 00 (PRM00)

Modification of Figure 6-34 Timing of One-Shot Pulse Output Operation with

External Trigger (with Rising Edge Specified)

Modification of Figure 7-1 Block Diagram of 8-Bit Timer 50

CHAPTER 7 8-BIT TIMER

50

Addition of Figure 7-2 Format of 8-Bit Timer Counter 50 (TM50)

Addition of Figure 7-3 Format of 8-Bit Timer Compare Register 50 (CR50)

Modification of Figure 7-6 Format of 8-Bit Timer Mode Control Register 50

(TMC50)

Modification of Figure 7-7 (a) Basic operation

Addition of 7.4.2 Operation as operating clock of TMH0 and UART6

Modification of Figure 8-2 Block Diagram of 8-Bit Timer H1

CHAPTER 8 8-BIT

TIMERS H0 AND H1

Addition of Note 1 and Caution 1 to Figure 8-5 Format of 8-Bit Timer H Mode

Register 0 (TMHMD0)

Addition of Caution 1 to Figure 8-6 Format of 8-Bit Timer H Mode Register 1

(TMHMD1)

Addition of description to 8.4.1 Operation as interval timer

Modification of Figure 8-12 Timing of Interval Timer/Square-Wave Output

Operation

Modification of description on duty in 8.4.2 (1) Usage

Modification of Figure 8-14 Operation Timing in PWM Output Mode

Modification of description on carrier clock output cycle and duty in 8.4.3 (3) Usage

Modification of figures (a) and (b) in Figure 8-17 Carrier Generator Mode

Operation Timing

Modification of Caution 3 and addition of Caution 5 in Figure 9-2 Format of

CHAPTER 9 WATCHDOG

TIMER

Watchdog Timer Mode Register (WDTM)

Modification of Cautions 1 and 2 in Figure 9-3 Format of Watchdog Timer Enable

Register (WDTE)

Addition of Table 9-4 Relationship Between Watchdog Timer Operation and

Internal Reset Signal Generated by Watchdog Timer

Modification of Caution in 9.4.1 Watchdog timer operation when “internal low-

speed oscillation clock cannot be stopped” is selected by mask option

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User’s Manual U16418EJ3V0UD

APPENDIX D REVISION HISTORY

(4/7)

Edition

Description

Chapter

2nd edition Modification of Figure 10-1 Block Diagram of A/D Converter

Modification of 10.2 Configuration of A/D Converter

CHAPTER 10 A/D

CONVERTER

Modification of Note 1 in Figure 10-3 Format of A/D Converter Mode Register

(ADM)

Modification of Note in Figure 10-4 Timing Chart When Boost Reference Voltage

Generator Is Used

Addition of 10.3 (3) A/D conversion result register (ADCR)

Modification of description in 10.3 (4) Power-fail comparison mode register (PFM)

Modification of description in 10.4.1 Basic operations of A/D converter

Addition of description to 10.4.2 Input voltage and conversion results

Modification of Figure 10-10 Relationship Between Analog Input Voltage and A/D

Conversion Result

Modification of description in 10.4.3 (1) A/D conversion operation (when PFEN =

0)

Modification of description in 10.4.3 (2) Power-fail detection function (when PFEN

= 1)

Modification of Caution 3 in 10.4.3 • When used as power-fail function

Modification of description in 10.6 (6) Input impedance of ANI0 to ANI3 pins

Modification of description in 10.6 (9) Conversion results just after A/D

conversion start

Modification of Figure 10-21 Timing of A/D Converter Sampling and A/D

Conversion Start Delay

Addition of 10.6 (12) Internal equivalent circuit

Modification of Cautions 1 and 3 in 11.1 (2) Asynchronous serial interface

CHAPTER 11 SERIAL

INTERFACE UART6

(UART) mode

Modification of Figure 11-1 LIN Transmission Operation

Modification of Figure 11-2 LIN Reception Operation

Modification of Figure 11-3 Port Configuration for LIN Reception Operation

Modification of Caution 2 in 11.2 (3) Transmit buffer register 6 (TXB6)

Addition of Note 2 and modification of Note 3 in Figure 11-5 Format of

Asynchronous Serial Interface Operation Mode Register 6 (ASIM6) (1/2)

Addition of Cautions 1 and 3 and modification of Caution 2 in Figure 11-5 Format

of Asynchronous Serial Interface Operation Mode Register 6 (ASIM6) (2/2)

Addition of Note and Caution 1 in Figure 11-8 Format of Clock Selection Register

6 (CKSR6)

Modification of Figure 11-10 Format of Asynchronous Serial Interface Control

Register 6 (ASICL6)

Addition of 11.3 (7) Input switch control register (ISC)

Addition of 11.3 (8) Port mode register 1 (PM1)

Modification of Note 2 in 11.4.1 (1) Register used

Modification of description in 11.4.2 (1) Registers used

Modification of description in 11.4.2 (2) (c) Normal transmission

Modification of description in 11.4.2 (2) (d) Continuous transmission

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User’s Manual U16418EJ3V0UD

APPENDIX D REVISION HISTORY

(5/7)

Edition

Description

Chapter

2nd edition Modification of Figure 11-16 Example of Continuous Transmission Processing

CHAPTER 11 SERIAL

INTERFACE UART6

Flow

Modification of description in 11.4.2 (2) (e) Normal reception

Modification of description in 11.4.2 (2) (h) SBF transmission

Modification of example in 11.4.3 (2) (b) Error of baud rate

Modification of Figure 12-2 Format of Serial Operation Mode Register 10

CHAPTER 12 SERRAL

INTERFACE CSI10

(CSIM10)

Modification of Figure 12-3 Format of Serial Clock Selection Register 10

(CSIC10)

Modification of 12.3 (3) Port mode register 1 (PM1)

Modification of description in 12.4.1 (1) Register used

Modification of description in 12.4.2 (1) Registers used

Addition of Table 12-2 Relationship Between Register Settings and Pins

Addition of 12.4.2 (5) SO10 output

Addition of 13.4.2 (1) (c) <1> Baud rate, <2> Error of baud rate, and <3> Example CHAPTER 13

of setting baud rate

MENCHESTER CODE

GENERATOR

Addition of 13.4.2 (1) (e) Port mode registers 0, 1 (PM0, PM1)

Modification of description in 13.4.2 (2) (b) When P13/TxD6/INTP1/(TOH1)/(MCGO)

is set as Manchester code output

Addition of 13.4.3 (1) (c) <1> Baud rate, <2> Error of baud rate, and <3> Example

of setting baud rate

Addition of 13.4.3 (1) (e) Port mode registers 0, 1 (PM0, PM1)

Modification of Figure 14-1 Basic Configuration of Interrupt Function

CHAPTER 14

INTERRUPT FUNCTIONS

Addition of Caution 3 in Figure 14-2 Format of Interrupt Request Flag Register

(IF0L, IF0H, IF1L)

Modification of Figure 14-5 Format of External Interrupt Rising Edge Enable

Register (EGP) and External Interrupt Falling Edge Enable Register (EGN)

Addition of Table 14-3 Ports Corresponding to EGPn and EGNn

Modification of Table 14-5 Relationship Between Interrupt Requests Enabled for

Multiple Interrupt Servicing During Interrupt Servicing

Modification of Table 15-1 Relationship Between Operation Clocks in Each

CHAPTER 15 STANDBY

FUNCTION

Operation Status

Addition of Cautions 2 and 3 to Figure 15-1 Format of Oscillation Stabilization

Time Counter Status Register (OSTC)

Modification of Table 15-2 Operating Statuses in HALT Mode

Modification of UART6 in Table 15-4 Operating Statuses in STOP Mode

Modification of Figure 16-1 Block Diagram of Reset Function

Modification of Figure 16-2 Timing of Reset by RESET Input

Modification of Figure 16-3 Timing of Reset Due to Watchdog Timer Overflow

Modification of Figure 16-4 Timing of Reset in STOP Mode by RESET Input

Modification of description in 17.1 Functions of Clock Monitor

Modification of Figure 17-1 Block Diagram of Clock Monitor

CHAPTER 16 RESET

FUNCTION

CHAPTER 17 CLOCK

MONITOR

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User’s Manual U16418EJ3V0UD

APPENDIX D REVISION HISTORY

(6/7)

Edition

Description

Chapter

2nd edition Addition of Caution 3 to Figure 17-2 Format of Clock Monitor Mode Register

CHAPTER 17 CLOCK

MONITOR

(CLM)

Addition of Figure 17-3 (6) Clock monitor status after high-speed system clock

oscillation is stopped by software

Addition of Figure 17-3 (7) Clock monitor status after internal low-speed

oscillation clock oscillation is stopped by software

Addition of Caution 2 to 18.1 Functions of Power-on-Clear Circuit

Modification of Figure 18-1 Block Diagram of Power-on-Clear Circuit

CHAPTER 18 POWER-

ON-CLEAR CIRCUIT

Modification of Figure 18-3 Example of Software Processing After Release of

Reset

Modification of Figure 19-1 Block Diagram of Low-Voltage Detector

CHAPTER 19 LOW-

VOLTAGE DETECTOR

Addition of Caution to Figure 19-3 Format of Low-Voltage Detection Level

Selection Register (LVIS)

Modification of Figure 19-4 Timing of Low-Voltage Detector Internal Reset Signal

Generation

Modification of Figure 19-5 Timing of Low-Voltage Detector Interrupt Signal

Generation

Modification of Figure 19-6 Example of Software Processing After Release of

Reset

Modification of description in 19.5 Cautions for Low-Voltage Detector <Action> (2)

When used as interrupt

Modification of Figure 20-2 Format of Option Bytes (Flash Memory Version)

CHAPTER 20 MASK

OPTIONS / OPTION BYTE

Modification of Table 21-3 Wiring Between µPD78F0862 and Dedicated Flash

Programmer

CHAPTER 21 FLASH

MEMORY

Modification of Figure 21-2 Example of Wiring Adapter for Flash Memory Writing

in 3-Wire Serial I/O (CSI10) Mode

Modification of Figure 21-3 Example of Wiring Adapter for Flash Memory Writing

in 3-Wire Serial I/O (CSI10 + HS) Mode

Modification of Figure 21-4 Example of Wiring Adapter for Flash Memory Writing

in UART (UART6) Mode

Addition of 21.3 Programming Environment

Addition of 21.4 Communication Mode

Addition of 21.5 Handling of Pins on Board

Addition of 21.6 Programming Method

Modification of CHAPTER 23 ELECTRICAL SPECIFICATIONS (STANDARD

CHAPTER 23

PRODUCTS, (A) GRADE PRODUCTS)

ELECTRICAL

SPECIFICATIONS

(STANDARD PRODUCTS,

(A) GRADE PRODUCTS

Addition of CHAPTER 24 ELECTRICAL SPECIFICATIONS ((A1) GRADE

CHAPTER 24

PRODUCTS)

ELECTRICAL

SPECIFICATIONS ((A1)

GRADE PRODUCTS

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User’s Manual U16418EJ3V0UD

APPENDIX D REVISION HISTORY

(7/7)

Edition

Description

Chapter

CHAPTER 25

ELECTRICAL

2nd edition Addition of CHAPTER 25 ELECTRICAL SPECIFICATIONS ((A2) GRADE

PRODUCTS)

SPECIFICATIONS ((A2)

GRADE PRODUCTS)

Addition of CHAPTER 27 RECOMMENDED SOLDERING CONDITIONS

CHAPTER 27

RECOMMENDED

SOLDERING

CONDITIONS

Modification of Figure A-1 Development Tool Configuration

Addition of A.3 Control Software

APPENDIX A

DEVELOPMENT TOOLS

Modification of A.5 Debugging Tools (Hardware)

Addition of APPENDIX B NOTES ON TARGET SYSTEM DESIGN

APPENDIX B NOTES ON

TARGET SYSTEM

DESIGN

Addition of APPENDIX D REVISION HISTORY

APPENDIX D REVISION

HISTORY

444

User’s Manual U16418EJ3V0UD

[MEMO]

For further information,

please contact:

NEC Electronics Corporation

1753, Shimonumabe, Nakahara-ku,

Kawasaki, Kanagawa 211-8668,

Japan

Tel: 044-435-5111

http://www.necel.com/

[Asia & Oceania]

[America]

[Europe]

NEC Electronics (China) Co., Ltd

7th Floor, Quantum Plaza, No. 27 ZhiChunLu Haidian

District, Beijing 100083, P.R.China

TEL: 010-8235-1155

NEC Electronics America, Inc.

2880 Scott Blvd.

Santa Clara, CA 95050-2554, U.S.A.

Tel: 408-588-6000

NEC Electronics (Europe) GmbH

Arcadiastrasse 10

40472 Düsseldorf, Germany

Tel: 0211-65030

http://www.cn.necel.com/

800-366-9782

http://www.eu.necel.com/

http://www.am.necel.com/

NEC Electronics Shanghai Ltd.

Room 2509-2510, Bank of China Tower,

200 Yincheng Road Central,

Hanover Office

Podbielski Strasse 166 B

30177 Hanover

Pudong New Area, Shanghai P.R. China P.C:200120

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Tel: 0 511 33 40 2-0

http://www.cn.necel.com/

Munich Office

Werner-Eckert-Strasse 9

81829 München

Tel: 0 89 92 10 03-0

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12/F., Cityplaza 4,

12 Taikoo Wan Road, Hong Kong

Tel: 2886-9318

http://www.hk.necel.com/

Stuttgart Office

Industriestrasse 3

70565 Stuttgart

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Tel: 0 711 99 01 0-0

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Yeoksam-Dong, Kangnam-Ku,

Seoul, 135-080, Korea

Tel: 02-558-3737

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Cygnus House, Sunrise Parkway

Linford Wood, Milton Keynes

MK14 6NP, U.K.

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7F, No. 363 Fu Shing North Road

Taipei, Taiwan, R. O. C.

Tel: 02-2719-2377

Tel: 01908-691-133

Succursale Française

9, rue Paul Dautier, B.P. 52180

78142 Velizy-Villacoublay Cédex

France

NEC Electronics Singapore Pte. Ltd.

238A Thomson Road,

#12-08 Novena Square,

Singapore 307684

Tel: 6253-8311

http://www.sg.necel.com/

Tel: 01-3067-5800

Sucursal en España

Juan Esplandiu, 15

28007 Madrid, Spain

Tel: 091-504-2787

Tyskland Filial

Täby Centrum

Entrance S (7th floor)

18322 Täby, Sweden

Tel: 08 638 72 00

Filiale Italiana

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20124 Milano, Italy

Tel: 02-667541

Branch The Netherlands

Limburglaan 5

5616 HR Eindhoven

The Netherlands

Tel: 040 265 40 10

G05.12A


型号：	UPD78F0862MC(A)-5A4-A
厂家：	RENESAS TECHNOLOGY CORP
描述：	8-bit Microcontrollers for General Purpose Applications (Non Promotion), , / 时钟微控制器 ISM频段光电二极管外围集成电路
文件：	总448页 (文件大小：2656K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

UPD78F0862MC(A)-5A4-A [RENESAS]

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