UPD78F9234MC(A2)-5A4-A

User’s Manual

78K0S/KB1+

8-bit Single-Chip Microcontrollers

μPD78F9232

μPD78F9234

μPD78F9232(A)

μPD78F9232(A2)

μPD78F9234(A)

μPD78F9234(A2)

Document No. U17446EJ5V0UD00 (5th edition)

Date Published November 2009 NS

2005

Printed in Japan

[MEMO]

2

User’s Manual U17446EJ5V0UD

NOTES FOR CMOS DEVICES

(1) VOLTAGE APPLICATION WAVEFORM AT INPUT PIN: Waveform distortion due to input noise or a reflected

wave may cause malfunction. If the input of the CMOS device stays in the area between VIL (MAX) and VIH

(MIN) due to noise, etc., the device may malfunction. Take care to prevent chattering noise from entering the

device when the input level is fixed, and also in the transition period when the input level passes through the

area between VIL (MAX) and VIH (MIN).

(2) HANDLING OF UNUSED INPUT PINS: Unconnected CMOS device inputs can be cause of malfunction. If

an input pin is unconnected, it is possible that an internal input level may be generated due to noise, etc.,

causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS

devices must be fixed high or low by using pull-up or pull-down circuitry. Each unused pin should be

connected to VDD or GND via a resistor if there is a possibility that it will be an output pin. All handling related

to unused pins must be judged separately for each device and according to related specifications governing

the device.

(3) PRECAUTION AGAINST ESD: A strong electric field, when exposed to a MOS device, can cause destruction

of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of

static electricity as much as possible, and quickly dissipate it when it has occurred. Environmental control

must be adequate. When it is dry, a humidifier should be used. It is recommended to avoid using insulators

that easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static

container, static shielding bag or conductive material. All test and measurement tools including work benches

and floors should be grounded. The operator should be grounded using a wrist strap. Semiconductor devices

must not be touched with bare hands. Similar precautions need to be taken for PW boards with mounted

semiconductor devices.

(4) STATUS BEFORE INITIALIZATION: Power-on does not necessarily define the initial status of a MOS device.

Immediately after the power source is turned ON, devices with reset functions have not yet been initialized.

Hence, power-on does not guarantee output pin levels, I/O settings or contents of registers. A device is not

initialized until the reset signal is received. A reset operation must be executed immediately after power-on

for devices with reset functions.

(5) POWER ON/OFF SEQUENCE: In the case of a device that uses different power supplies for the internal

operation and external interface, as a rule, switch on the external power supply after switching on the internal

power supply. When switching the power supply off, as a rule, switch off the external power supply and then

the internal power supply. Use of the reverse power on/off sequences may result in the application of an

overvoltage to the internal elements of the device, causing malfunction and degradation of internal elements

due to the passage of an abnormal current. The correct power on/off sequence must be judged separately for

each device and according to related specifications governing the device.

(6) INPUT OF SIGNAL DURING POWER OFF STATE : Do not input signals or an I/O pull-up power supply while

the device is not powered. The current injection that results from input of such a signal or I/O pull-up power

supply may cause malfunction and the abnormal current that passes in the device at this time may cause

degradation of internal elements. Input of signals during the power off state must be judged separately for

each device and according to related specifications governing the device.

3

User’s Manual U17446EJ5V0UD

Windows is a registered trademark or a trademark of Microsoft Corporation in the United States and/or other

countries.

PC/AT is a trademark of International Business Machines Corporation.

HP9000 series 700 and HP-UX are trademarks of Hewlett-Packard Company.

SPARCstation is a trademark of SPARC International, Inc.

Solaris and SunOS are trademarks of Sun Microsystems, Inc.

SuperFlash is a registered trademark of Silicon Storage Technology, Inc. in several countries including the

United States and Japan.

Caution: This product uses SuperFlash^®technology licensed from Silicon Storage Technology, Inc.

• The information in this document is current as of November, 2009. The information is subject to change without notice. For

actual design-in, refer to the latest publications of NEC Electronics data sheets or data books, etc., for the most up-to-date

specifications of NEC Electronics products. Not all products and/or types are available in every country. Please check with an

NEC Electronics sales representative for availability and additional information.

• No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC

Electronics. NEC Electronics assumes no responsibility for any errors that may appear in this document.

• NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of

third parties by or arising from the use of NEC Electronics products listed in this document or any other liability arising from the

use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual

property rights of NEC Electronics or others.

• Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in

semiconductor product operation and application examples. The incorporation of these circuits, software and information in

the design of a customer's equipment shall be done under the full responsibility of the customer. NEC Electronics assumes no

responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and

information.

• While NEC Electronics endeavors to enhance the quality, reliability and safety of NEC Electronics products, customers agree

and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize risks of damage to property

or injury (including death) to persons arising from defects in NEC Electronics products, customers must incorporate sufficient

safety measures in their design, such as redundancy, fire-containment and anti-failure features.

• NEC Electronics products are classified into the following three quality grades: "Standard", "Special" and "Specific". The

"Specific" quality grade applies only to NEC Electronics products developed based on a customer-designated "quality

assurance program" for a specific application. The recommended applications of an NEC Electronics product depend on its

quality grade, as indicated below. Customers must check the quality grade of each NEC Electronics product before using it in

a particular application.

"Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio and visual

equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots.

"Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-

crime systems, safety equipment and medical equipment (not specifically designed for life support).

"Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and

medical equipment for life support, etc.

The quality grade of NEC Electronics products is "Standard" unless otherwise expressly specified in NEC Electronics data

sheets or data books, etc. If customers wish to use NEC Electronics products in applications not intended by NEC Electronics,

they must contact an NEC Electronics sales representative in advance to determine NEC Electronics' willingness to support a

given application.

(Note 1) "NEC Electronics" as used in this statement means NEC Electronics Corporation and also includes its majority-owned

subsidiaries.

(Note 2) "NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as defined

above).

(M8E0909)

4

User’s Manual U17446EJ5V0UD

INTRODUCTION

Target Readers

This manual is intended for user engineers who wish to understand the functions of

the 78K0S/KB1+ in order to design and develop its application systems and

programs.

The target devices are the following subseries products.

• 78K0S/KB1+: μPD78F9232, 78F9234, 78F9232(A), 78F9234(A), 78F9232(A2),

78F9234(A2)

Purpose

This manual is intended to give users on understanding of the functions described in

the Organization below.

Organization

Two manuals are available for the 78K0S/KB1+: this manual and the Instruction

Manual (common to the 78K/0S Series).

78K/0S Series

78K0S/KB1+

Instructions

User’s Manual

• Pin functions

• CPU function

• Internal block functions

• Interrupts

• Instruction set

• Instruction description

• Other internal peripheral functions

• Electrical specifications

How to Use This Manual

It is assumed that the readers of this manual have general knowledge of electrical

engineering, logic circuits, and microcontrollers.

◊ To understand the overall functions of 78K0S/KB1+

→ Read this manual in the order of the CONTENTS. The mark <R> shows major

revised points. The revised points can be easily searched by copying an “<R>”

in the PDF file and specifying it in the “Find what:” field.

◊ How to read register formats

→ For a bit number enclosed in a square, the bit name is defined as a reserved

word in the RA78K0S, and is defined as an sfr variable using the #pragma sfr

directive in the CC78K0S.

◊ To learn the detailed functions of a register whose register name is known

→ See APPENDIX C REGISTER INDEX.

◊ To learn the details of the instruction functions of the 78K/0S Series

→ Refer to 78K/0S Series Instructions User’s Manual (U11047E) separately

available.

◊ To learn the electrical specifications of the 78K0S/KB1+

→ See CHAPTER 22 and CHAPTER 23 ELECTRICAL SPECIFICATIONS.

5

User’s Manual U17446EJ5V0UD

Conventions

Data significance:

Higher digits on the left and lower digits on the right

Active low representation: ××× (overscore over pin or signal name)

Note:

Footnote for item marked with Note in the text

Information requiring particular attention

Supplementary information

Caution:

Remark:

Numerical representation: Binary ... ×××× or ××××B

Decimal ... ××××

Hexadecimal ... ××××H

Other Related Documents

Document Name

Document No.

X13769X

Note

SEMICONDUCTOR SELECTION GUIDE - Products and Packages -

Semiconductor Device Mount Manual

Quality Grades on NEC Semiconductor Devices

C11531E

C10983E

C11892E

NEC Semiconductor Device Reliability/Quality Control System

Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD)

Note See the “Semiconductor Device Mount Manual” website (http://www.necel.com/pkg/en/mount/index.html).

Caution The related documents listed above are subject to change without notice. Be sure to use the latest

version of each document for designing.

7

User’s Manual U17446EJ5V0UD

CONTENTS

CHAPTER 1 OVERVIEW.........................................................................................................................14

1.1 Features.........................................................................................................................................14

1.2 Ordering Information....................................................................................................................15

1.3 Pin Configuration (Top View) ......................................................................................................16

1.4 78K0S/Kx1+ Product Lineup........................................................................................................18

1.5 Block Diagram...............................................................................................................................19

1.6 Functional Outline ........................................................................................................................20

CHAPTER 2 PIN FUNCTIONS ...............................................................................................................21

2.1 Pin Function List...........................................................................................................................21

2.2 Pin Functions ................................................................................................................................23

2.2.1 P00 to P03 (Port 0)............................................................................................................................23

2.2.2 P20 to P23 (Port 2)............................................................................................................................23

2.2.3 P30 to P34 (Port 3)............................................................................................................................23

2.2.4 P40 to P47 (Port 4)............................................................................................................................24

2.2.5 P120 to P123 (Port 12)......................................................................................................................24

2.2.6 P130 (Port 13)...................................................................................................................................24

2.2.7 RESET ..............................................................................................................................................24

2.2.8 X1 and X2..........................................................................................................................................25

2.2.9 AVREF.................................................................................................................................................25

2.2.10 AVSS ................................................................................................................................................25

2.2.11 VDD ..................................................................................................................................................25

2.2.12 VSS...................................................................................................................................................25

2.3 Pin I/O Circuits and Connection of Unused Pins ......................................................................26

CHAPTER 3 CPU ARCHITECTURE......................................................................................................28

3.1 Memory Space ..............................................................................................................................28

3.1.1 Internal program memory space........................................................................................................30

3.1.2 Internal data memory space..............................................................................................................30

3.1.3 Special function register (SFR) area..................................................................................................31

3.1.4 Data memory addressing ..................................................................................................................31

3.2 Processor Registers.....................................................................................................................33

3.2.1 Control registers................................................................................................................................33

3.2.2 General-purpose registers.................................................................................................................36

3.2.3 Special function registers (SFRs)......................................................................................................37

3.3 Instruction Address Addressing.................................................................................................42

3.3.1 Relative addressing...........................................................................................................................42

3.3.2 Immediate addressing .......................................................................................................................43

3.3.3 Table indirect addressing ..................................................................................................................43

3.3.4 Register addressing...........................................................................................................................44

3.4 Operand Address Addressing.....................................................................................................45

3.4.1 Direct addressing ..............................................................................................................................45

3.4.2 Short direct addressing......................................................................................................................46

3.4.3 Special function register (SFR) addressing .......................................................................................47

3.4.4 Register addressing...........................................................................................................................48

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User’s Manual U17446EJ5V0UD

3.4.5 Register indirect addressing.............................................................................................................. 49

3.4.6 Based addressing ............................................................................................................................. 50

3.4.7 Stack addressing............................................................................................................................... 51

CHAPTER 4 PORT FUNCTIONS...........................................................................................................52

4.1 Functions of Ports........................................................................................................................52

4.2 Port Configuration........................................................................................................................54

4.2.1 Port 0................................................................................................................................................ 55

4.2.2 Port 2 ................................................................................................................................................ 56

4.2.3 Port 3 ................................................................................................................................................ 57

4.2.4 Port 4 ................................................................................................................................................ 60

4.2.5 Port 12 .............................................................................................................................................. 63

4.2.6 Port 13 .............................................................................................................................................. 65

4.3 Registers Controlling Port Functions ........................................................................................66

4.4 Operation of Port Function .........................................................................................................71

4.4.1 Writing to I/O port.............................................................................................................................. 71

4.4.2 Reading from I/O port........................................................................................................................ 71

4.4.3 Operations on I/O port....................................................................................................................... 71

CHAPTER 5 CLOCK GENERATORS...................................................................................................72

5.1 Functions of Clock Generators...................................................................................................72

5.1.1 System clock oscillators.................................................................................................................... 72

5.1.2 Clock oscillator for interval time generation....................................................................................... 72

5.2 Configuration of Clock Generators ............................................................................................73

5.3 Registers Controlling Clock Generators....................................................................................75

5.4 System Clock Oscillators ............................................................................................................78

5.4.1 High-speed internal oscillator............................................................................................................ 78

5.4.2 Crystal/ceramic oscillator .................................................................................................................. 78

5.4.3 External clock input circuit................................................................................................................. 80

5.4.4 Prescaler........................................................................................................................................... 80

5.5 Operation of CPU Clock Generator ............................................................................................81

5.6 Operation of Clock Generator Supplying Clock to Peripheral Hardware...............................86

CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00.............................................................................88

6.1 Functions of 16-bit Timer/Event Counter 00..............................................................................88

6.2 Configuration of 16-bit Timer/Event Counter 00 .......................................................................89

6.3 Registers to Control 16-bit Timer/Event Counter 00 ................................................................93

6.4 Operation of 16-bit Timer/Event Counter 00..............................................................................99

6.4.1 Interval timer operation ..................................................................................................................... 99

6.4.2 External event counter operation .................................................................................................... 101

6.4.3 Pulse width measurement operations ............................................................................................. 104

6.4.4 Square-wave output operation ........................................................................................................ 112

6.4.5 PPG output operations.................................................................................................................... 114

6.4.6 One-shot pulse output operation..................................................................................................... 117

6.5 Cautions Related to 16-bit Timer/Event Counter 00 ...............................................................122

CHAPTER 7 8-BIT TIMER 80..............................................................................................................129

7.1 Function of 8-bit Timer 80 .........................................................................................................129

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User’s Manual U17446EJ5V0UD

7.2 Configuration of 8-bit Timer 80 .................................................................................................130

7.3 Register Controlling 8-bit Timer 80...........................................................................................132

7.4 Operation of 8-bit Timer 80........................................................................................................133

7.4.1 Operation as interval timer ..............................................................................................................133

7.5 Notes on 8-bit Timer 80..............................................................................................................135

CHAPTER 8 8-BIT TIMER H1 .............................................................................................................136

8.1 Functions of 8-bit Timer H1.......................................................................................................136

8.2 Configuration of 8-bit Timer H1.................................................................................................136

8.3 Registers Controlling 8-bit Timer H1........................................................................................139

8.4 Operation of 8-bit Timer H1 .......................................................................................................142

8.4.1 Operation as interval timer/square-wave output..............................................................................142

8.4.2 Operation as PWM output mode .....................................................................................................145

CHAPTER 9 WATCHDOG TIMER .......................................................................................................151

9.1 Functions of Watchdog Timer...................................................................................................151

9.2 Configuration of Watchdog Timer ............................................................................................153

9.3 Registers Controlling Watchdog Timer....................................................................................154

9.4 Operation of Watchdog Timer...................................................................................................156

9.4.1 Watchdog timer operation when “low-speed internal oscillator cannot be stopped” is selected by

option byte.......................................................................................................................................156

9.4.2 Watchdog timer operation when “low-speed internal oscillator can be stopped by software” is

selected by option byte....................................................................................................................158

9.4.3 Watchdog timer operation in STOP mode (when “low-speed internal oscillator can be stopped by

software” is selected by option byte) ...............................................................................................160

9.4.4 Watchdog timer operation in HALT mode (when “low-speed internal oscillator can be stopped by

software” is selected by option byte) ...............................................................................................162

CHAPTER 10 A/D CONVERTER .........................................................................................................163

10.1 Functions of A/D Converter.....................................................................................................163

10.2 Configuration of A/D Converter ..............................................................................................165

10.3 Registers Used by A/D Converter...........................................................................................167

10.4 A/D Converter Operations .......................................................................................................172

10.4.1 Basic operations of A/D converter.................................................................................................172

10.4.2 Input voltage and conversion results .............................................................................................174

10.4.3 A/D converter operation mode.......................................................................................................175

10.5 How to Read A/D Converter Characteristics Table...............................................................177

10.6 Cautions for A/D Converter.....................................................................................................179

CHAPTER 11 SERIAL INTERFACE UART6 ......................................................................................182

11.1 Functions of Serial Interface UART6......................................................................................182

11.2 Configuration of Serial Interface UART6................................................................................186

11.3 Registers Controlling Serial Interface UART6.......................................................................189

11.4 Operation of Serial Interface UART6 ......................................................................................198

11.4.1 Operation stop mode.....................................................................................................................198

11.4.2 Asynchronous serial interface (UART) mode ................................................................................199

11.4.3 Dedicated baud rate generator......................................................................................................213

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CHAPTER 12 MULTIPLIER ..................................................................................................................220

12.1 Multiplier Function ...................................................................................................................220

12.2 Multiplier Configuration...........................................................................................................220

12.3 Multiplier Control Register......................................................................................................222

12.4 Multiplier Operation .................................................................................................................223

CHAPTER 13 INTERRUPT FUNCTIONS............................................................................................225

13.1 Interrupt Function Types.........................................................................................................225

13.2 Interrupt Sources and Configuration.....................................................................................226

13.3 Interrupt Function Control Registers.....................................................................................228

13.4 Interrupt Servicing Operation .................................................................................................233

13.4.1 Maskable interrupt request acknowledgment operation ................................................................ 233

13.4.2 Multiple interrupt servicing............................................................................................................. 235

13.4.3 Interrupt request pending .............................................................................................................. 237

CHAPTER 14 STANDBY FUNCTION..................................................................................................238

14.1 Standby Function and Configuration.....................................................................................238

14.1.1 Standby function ........................................................................................................................... 238

14.1.2 Registers used during standby...................................................................................................... 240

14.2 Standby Function Operation...................................................................................................241

14.2.1 HALT mode................................................................................................................................... 241

14.2.2 STOP mode .................................................................................................................................. 244

CHAPTER 15 RESET FUNCTION .......................................................................................................248

15.1 Register for Confirming Reset Source...................................................................................255

CHAPTER 16 POWER-ON-CLEAR CIRCUIT .....................................................................................256

16.1 Functions of Power-on-Clear Circuit .....................................................................................256

16.2 Configuration of Power-on-Clear Circuit...............................................................................257

16.3 Operation of Power-on-Clear Circuit......................................................................................257

16.4 Cautions for Power-on-Clear Circuit......................................................................................258

CHAPTER 17 LOW-VOLTAGE DETECTOR.......................................................................................260

17.1 Functions of Low-Voltage Detector........................................................................................260

17.2 Configuration of Low-Voltage Detector .................................................................................260

17.3 Registers Controlling Low-Voltage Detector.........................................................................261

17.4 Operation of Low-Voltage Detector........................................................................................263

17.5 Cautions for Low-Voltage Detector........................................................................................266

CHAPTER 18 OPTION BYTE ...............................................................................................................269

18.1 Functions of Option Byte ........................................................................................................269

18.2 Format of Option Byte .............................................................................................................270

18.3 Caution When the RESET Pin Is Used as an Input-Only Port Pin (P34).............................271

CHAPTER 19 FLASH MEMORY..........................................................................................................272

19.1 Features.....................................................................................................................................272

19.2 Memory Configuration.............................................................................................................273

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User’s Manual U17446EJ5V0UD

19.3 Functional Outline ....................................................................................................................273

19.4 Writing with Flash Memory Programmer ...............................................................................274

19.5 Programming Environment .....................................................................................................275

19.6 Pin Connection on Board.........................................................................................................277

19.6.1 X1 and X2 pins..............................................................................................................................277

19.6.2 RESET pin.....................................................................................................................................278

19.6.3 Port pins ........................................................................................................................................279

19.6.4 Power supply.................................................................................................................................279

19.7 On-Board and Off-Board Flash Memory Programming........................................................280

19.7.1 Flash memory programming mode................................................................................................280

19.7.2 Communication commands...........................................................................................................280

19.7.3 Security settings............................................................................................................................281

19.8 Flash Memory Programming by Self Programming..............................................................282

19.8.1 Outline of self programming ..........................................................................................................282

19.8.2 Cautions on self programming function .........................................................................................285

19.8.3 Registers used for self programming function ...............................................................................285

19.8.4 Example of shifting normal mode to self programming mode........................................................293

19.8.5 Example of shifting self programming mode to normal mode........................................................296

19.8.6 Example of block erase operation in self programming mode .......................................................299

19.8.7 Example of block blank check operation in self programming mode .............................................302

19.8.8 Example of byte write operation in self programming mode..........................................................305

19.8.9 Examples of internal verify operation in self programming mode ..................................................308

19.8.10 Examples of operation when command execution time should be minimized in self programming

mode ...........................................................................................................................................312

19.8.11 Examples of operation when interrupt-disabled time should be minimized in self programming

mode ...........................................................................................................................................319

CHAPTER 20 ON-CHIP DEBUG FUNCTION.......................................................................................330

20.1 Connecting QB-MINI2 to 78K0S/KB1+....................................................................................330

20.1.1 Connection of INTP3 pin ...............................................................................................................331

20.1.2 Connection of X1 and X2 pins.......................................................................................................332

20.2 Securing of user resources.....................................................................................................333

CHAPTER 21 INSTRUCTION SET OVERVIEW.................................................................................334

21.1 Operation...................................................................................................................................334

21.1.1 Operand identifiers and description methods ................................................................................334

21.1.2 Description of “Operation” column.................................................................................................335

21.1.3 Description of “Flag” column..........................................................................................................335

21.2 Operation List ...........................................................................................................................336

21.3 Instructions Listed by Addressing Type................................................................................341

CHAPTER 22 ELECTRICAL SPECIFICATIONS (Standard product, (A) grade product) ................344

CHAPTER 23 ELECTRICAL SPECIFICATIONS ((A2) grade product)..............................................356

CHAPTER 24 PACKAGE DRAWING ..................................................................................................370

CHAPTER 25 RECOMMENDED SOLDERING CONDITIONS...........................................................373

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APPENDIX A DEVELOPMENT TOOLS ..............................................................................................375

A.1 Software Package ......................................................................................................................378

A.2 Language Processing Software ...............................................................................................378

A.3 Flash Memory Writing Tools.....................................................................................................379

A.3.1 When using flash memory programmer PG-FP5 and FL-PR5........................................................ 379

A.3.2 When using on-chip debug emulator with programming function QB-MINI2................................... 379

A.4 Debugging Tools (Hardware)....................................................................................................379

A.4.1 When using in-circuit emulator QB-78K0SKX1............................................................................... 379

A.4.2 When using on-chip debug emulator with programming function QB-MINI2................................... 380

A.5 Debugging Tools (Software).....................................................................................................381

APPENDIX B NOTES ON DESIGNING TARGET SYSTEM ................................................................382

APPENDIX C REGISTER INDEX.........................................................................................................384

C.1 Register Index (Register Name) ...............................................................................................384

C.2 Register Index (Symbol)............................................................................................................387

APPENDIX D LIST OF CAUTIONS.....................................................................................................390

APPENDIX E REVISION HISTORY .....................................................................................................410

E.1 Major Revisions in This Edition................................................................................................410

E.2 Revision History up to Previous Editions ...............................................................................411

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User’s Manual U17446EJ5V0UD

CHAPTER 1 OVERVIEW

1.1 Features

O 78K0S CPU core

O ROM and RAM capacities

Item

Program Memory (Flash Memory)

Memory (Internal High-Speed RAM)

Part number

μPD78F9232

μPD78F9234

4 KB

8 KB

256 bytes

O Minimum instruction execution time: 0.2 μs (with 10 MHz@4.0 to 5.5 V operation)

O Clock

• High-speed system clock … Selected from the following three sources

- Ceramic/crystal resonator:

2 to 10 MHz (Standard product, (A) grade product)

2 to 8 MHz ((A2) grade product)

- External clock:

2 to 10 MHz (Standard product, (A) grade product)

2 to 8 MHz ((A2) grade product)

- High-speed internal oscillator: 8 MHz ±3% (−10 to +80°C),

8 MHz ±5% (Standard product, (A) grade product: −40 to +85°C,

(A2) grade product: −40 to +125°C)

• Low-speed internal oscillator 240 kHz (TYP.) … Watchdog timer, timer clock in intermittent operation

O I/O ports: 26 (CMOS I/O: 24, CMOS input: 1, CMOS output: 1)

O Timer: 4 channels

• 16-bit timer/event counter: 1 channel … Timer output × 1, capture input × 2

• 8-bit timer:

2 channels … PWM output × 1

• Watchdog timer:

1 channel … Operable with low-speed internal oscillation clock

O Serial interface: UART (LIN (Local Interconnect Network) bus supported) 1 channel

O On-chip multiplier: 8 bits × 8 bits = 16 bits

O 10-bit resolution A/D converter: 4 channels

O On-chip power-on-clear (POC) circuit (A reset is automatically generated when the voltage drops to 2.1 V (TYP.)

or below.)

O On-chip low voltage detector (LVI) circuit (An interrupt/reset (selectable) is generated when the detection voltage

is reached.)

• Detection voltage: Selectable from ten levels between 2.35 and 4.3 V

O Single-power-supply flash memory

• Flash self programming enabled

• Software protection function: Protected from outside party copying (no flash reading command)

• Time required for writing by dedicated flash memory programmer: Approximately 3 seconds (4 KB)

∗ Flash programming on mass production lines supported

O Safety function

• Watchdog timer operated by clock independent from CPU

… A hang-up can be detected even if the system clock stops

• Supply voltage drop detectable by LVI

… Appropriate processing can be executed before the supply voltage drops below the operation voltage

• Equipped with option byte function

… Important system operation settings set in hardware

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User’s Manual U17446EJ5V0UD

CHAPTER 1 OVERVIEW

O Assembler and C language supported

O Enhanced development environment

• Support for full-function emulator (IECUBE), simplified emulator (MINICUBE2), and simulator

O Supply voltage: V^DD= 2.0 to 5.5 V

∗ Use these products in the following voltage range because the detection voltage (V^POC) of the POC circuit is

the supply voltage range.

Standard product, (A) grade product: 2.2 to 5.5 V, (A2) grade product: 2.26 to 5.5 V

O Operating temperature range

• Standard product, (A) grade product: T^A= −40 to +85°C

• (A2) grade product: T^A= −40 to +125°C

<R>

1.2 Ordering Information

Part Number

μPD78F9 ××× - ×× (×) - ××× - ××

Semiconductor component

-A

Lead-free

Product contains no lead in any area

(Terminal finish is Sn/Bi plating)

Product contains no lead in any area

(Terminal finish is Ni/Pd/Au plating)

-AX

Quality grades

Blank

(A)

Standard (for ordinary electronic systems)

Special (for high-reliability electronic systems)

(A2)

Package type

30-pin Plastic SSOP

MC-5A4

MC-CAB

CS-CAA

32-pin Plastic SDIP

High-speed RAM

256 bytes

Flash memory

4 K bytes

8 K bytes

232

234

256 bytes

Product type

F

Flash memory versions

Please refer to "Quality Grades on NEC Semiconductor Devices" (Document No. C11531E) published by

NEC Electronics Corporation to know the specification of the quality grade on the device and its

recommended applications.

[Part number list]

μ PD78F9232MC-5A4-A

μ PD78F9234MC-5A4-A

μ PD78F9232MC(A)-5A4-A

μ PD78F9232MC(A2)-5A4-A

μ PD78F9232MC(A)-CAB-AX

μ PD78F9232MC(A2)-CAB-AX

μ PD78F9232CS-CAA-A

μ PD78F9234MC(A)-5A4-A

μ PD78F9234MC(A2)-5A4-A

μ PD78F9234MC(A)-CAB-AX

μ PD78F9234MC(A2)-CAB-AX

μ PD78F9234CS-CAA-A

15

User’s Manual U17446EJ5V0UD

CHAPTER 1 OVERVIEW

1.3 Pin Configuration (Top View)

• 30-pin plastic SSOP

P03

1

P120

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

P02

P01

2

AVSS

3

AVREF

P00

4

P20/ANI0

P21/ANI1

P22/ANI2

P23/ANI3

P130

P123

5

VSS

6

VDD

7

P121/X1

8

P122/X2

9

P47

P34/RESET

10

11

12

13

14

15

P46

P33

P32

P45

P44/RxD6

P43/TxD6/INTP1

P42/TOH1

P41/INTP3

P31/TI010/TO00/INTP2

P30/TI000/INTP0

P40

Caution Connect the AV^SSpin to VSS.

• 32-pin plastic SDIP

P23/ANI3

P22/ANI2

P21/ANI1

P20/ANI0

AVREF

AVSS

1

P130

P47

P46

P45

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

2

3

4

5

P44/RxD6

6

P43/TxD6/INTP1

P42/TOH1

P41/INTP3

P40

AVSS

7

P120

8

P03

9

P02

10

11

12

13

14

15

16

P30/TI00/INTP0

P01

P31/TI010/TO00/INTP2

P00

P32

P123

P33

V

SS

P34/RESET

P122/X2

P121/X1

SS

V

DD

Caution Connect the AV^SSpin to VSS.

16

User’s Manual U17446EJ5V0UD

CHAPTER 1 OVERVIEW

Pin Name

ANI0 to ANI3:

AV^REF:

Analog input

P130:

Port 13

Analog Power Supply,

RESET:

Reset

Analog Reference Voltage,

RxD6:

Receive data

Timer input

Power Supply for P20 to P23

TI000, TI010:

TO00, TOH1:

TxD6:

AV^SS:

Analog ground

External interrupt input

Port 0

Timer output

Transmit data

Power supply

Ground

INTP0 to INTP3:

P00 to P03:

P20 to P23:

P30 to P34:

P40 to P47:

P120 to P123:

V^DD:

Port 2

V^SS:

Port 3

X1, X2:

Crystal oscillator (X1 input clock)

Port 4

Port 12

17

User’s Manual U17446EJ5V0UD

CHAPTER 1 OVERVIEW

1.4 78K0S/Kx1+ Product Lineup

The following table shows the product lineup of the 78K0S/Kx1+.

Part Number

78K0S/KU1+

78K0S/KY1+

78K0S/KA1+

20 pins

78K0S/KB1+

Item

Number of pins

10 pins

16 pins

30/32 pins

4 KB, 8 KB

Internal

memory

Flash memory

1 KB, 2 KB, 4 KB

2 KB

4 KB,

<R>

8 KB

RAM

128 bytes

128

256

256 bytes

bytes

V^DD= 2.0 to 5.5 V^{Note 1}

Supply voltage

Minimum instruction

execution time

0.20 μs (10 MHz, VDD = 4.0 to 5.5 V)

0.33 μs (6 MHz, VDD = 3.0 to 5.5 V)

0.40 μs (5 MHz, VDD = 2.7 to 5.5 V)

1.0 μs (2 MHz, VDD = 2.0 to 5.5 V)

High-speed internal oscillation (8 MHz (TYP.))

Crystal/ceramic oscillation (2 to 10 MHz)^{Note 2}

System clock

(oscillation frequency)

External clock input oscillation (2 to 10 MHz)

Low-speed internal oscillation (240 kHz (TYP.))

Clock for TMH1 and WDT

(oscillation frequency)

Port

CMOS I/O

CMOS input

CMOS output

16-bit (TM0)

8-bit (TMH)

8-bit (TM8)

WDT

7

1

−

13

1

15

1

24

1

−

1

1 ch^{Note 3}

1 ch

Timer

−

1 ch

Serial interface

LIN-Bus-supporting UART: 1 ch

A/D converter^{Note 4}

Multiplier (8 bits × 8 bits)

Interrupts Internal

External

10 bits: 4 ch (2.7 to 5.5 V)^{Note 4}

−

Provided

5^{Note 5}

2

9

4

Reset

RESET pin

POC

Provided

2.1 V (TYP.)

LVI

Provided (selectable by software)

Provided

WDT

Standard product:

−40 to +85°C

Standard product, (A) grade product: −40 to +85°C

(A2) grade product: −40 to +125°C

Operating temperature range

Notes 1. Use these products in the following voltage range because the detection voltage (VPOC) of the power-on-

clear (POC) circuit is the supply voltage range.

Standard product, (A) grade product: 2.2 to 5.5 V, (A2) grade product: 2.26 to 5.5 V

2. μ PD78F950x does not support the crystal/ceramic oscillation.

<R>

3. The product without A/D converter (μ PD78F950x) in the 78K0S/KU1+ is not supported.

4. The product without A/D converter (μ PD78F95xx) is provided for the 78K0S/KU1+ and 78K0S/KY1+

respectively. This product has A/D converter.

5. There are 2 and 4 factors for the products without A/D converter in the 78K0S/KU1+ and 78K0S/KY1+,

respectively.

18

User’s Manual U17446EJ5V0UD

CHAPTER 1 OVERVIEW

1.5 Block Diagram

TO00/TI010/P31

TI000/P30

4

Port 0

Port 2

Port 3

Port 4

P00 to P03

P20 to P23

16-bit timer/

event counter 00

4

8-bit timer 80

8-bit timer H1

P30 to P33

P34

TOH1/P42

78K0S

Flash

CPU

8

4

P40 to P47

P120 to P123

P130

Low-speed

internal oscillator

memory

core

Port 12

Port 13

Watchdog timer

RxD6/P44

TxD6/P43

Serial interface

UART6

Internal

high-speed

RAM

Power-on-clear/

low-voltage

indicator

ANI0/P20 to

4

POC/LVI control

ANI3/P23

A/D converter

AVREF

AVSS

Reset control

INTP0/P30

INTP1/P43

INTP2/P31

INTP3/P41

Interrupt control

RESET/P34

X1/P121

System control

X2/P122

High-speed

internal oscillator

Multiplier

VDD

VSS

19

User’s Manual U17446EJ5V0UD

CHAPTER 1 OVERVIEW

1.6 Functional Outline

Item

μPD78F9232

μPD78F9234

Internal

memory

Flash memory

4 KB

8 KB

High-speed RAM

256 bytes

64 KB

Memory space

X1 input clock (oscillation frequency)

Crystal/ceramic/external clock input:

10 MHz (V^DD= 2.0 to 5.5 V)

Internal

High speed (oscillation

Internal oscillation: 8 MHz (TYP.)

Internal oscillation: 240 kHz (TYP.)

8 bits × 8 registers

oscillation frequency)

clock

Low speed (for TMH1

and WDT)

General-purpose registers

Instruction execution time

Multiplier

0.2 μs/0.4 μs/0.8 μs/1.6 μs/3.2 μs (X1 input clock: fX = 10 MHz)

8 bits × 8 bits = 16 bits

I/O port

Total:

26 pins

24 pins

1 pin

CMOS I/O:

CMOS input:

CMOS output:

1 pin

Timer

• 16-bit timer/event counter: 1 channel

• 8-bit timer (timer H1):

• 8-bit timer (timer 80):

• Watchdog timer:

1 channel

Timer output

2 pins (PWM: 1 pin)

A/D converter

Serial interface

10-bit resolution × 4 channels

LIN-bus-supporting UART mode: 1 channel

Vectored

External

Internal

4

9

interrupt sources

• Reset by RESET pin

Reset

• Internal reset by watchdog timer

• Internal reset by power-on-clear

• Internal reset by low-voltage detector

Supply voltage

VDD = 2.0 to 5.5 V^Note

Operating temperature range

Standard product, (A) grade product: −40 to +85°C

(A2) grade product: −40 to +125°C

Package

• 30-pin plastic SSOP

• 32-pin plastic SDIP

Note Use these products in the following voltage range because the detection voltage (VPOC) of the power-on-

clear (POC) circuit is the supply voltage range.

Standard product, (A) grade product: 2.2 to 5.5 V, (A2) grade product: 2.26 to 5.5 V

20

User’s Manual U17446EJ5V0UD

CHAPTER 2 PIN FUNCTIONS

2.1 Pin Function List

(1) Port pins

Pin Name

I/O

Function

After Reset

Input

Alternate-

Function Pin

P00 to P03

I/O

Port 0.

−

4-bit I/O port.

Can be set to input or output mode in 1-bit units.

An on-chip pull-up resistor can be connected by setting software.

P20 to P23

Port 2.

Input

ANI0 to ANI3

4-bit I/O port.

Can be set to input or output mode in 1-bit units.

An on-chip pull-up resistor can be connected by setting software.

P30

P31

Port 3

Can be set to input or output mode in 1- Input

TI000/INTP0

bit units.

TI010/TO00/

INTP2

An on-chip pull-up resistor can be

connected by setting software.

P32

−

P33

−

P34^Note

Input

I/O

Input only

Input

RESET ^Note

P40

Port 4.

−

8-bit I/O port.

P41

INTP3

Can be set to input or output mode in 1-bit units.

P42

TOH1

An on-chip pull-up resistor can be connected by setting software.

P43

TxD6/INTP1

P44

RxD6

P45

−

P46

−

P47

−

P120

P121^Note

P122^Note

P123

P130

I/O

Port 12.

Input

−

4-bit I/O port.

X1^Note

X2^Note

−

Can be set to input or output mode in 1-bit units.

An on-chip pull-up resistor can be connected only to P120 and

P123 by setting software.

Output

Port 13.

Output

−

1-bit output-only port

Note For settings of alternate function, refer to CHAPTER 18 OPTION BYTE.

Caution The P121/X1 and P122/X2 pins are pulled down during reset.

21

User’s Manual U17446EJ5V0UD

CHAPTER 2 PIN FUNCTIONS

(2) Non-port pins

Pin Name

I/O

Function

After Reset

Input

Alternate-

Function Pin

INTP0

Input

External interrupt input for which the valid edge (rising edge,

falling edge, or both rising and falling edges) can be specified

P30/TI000

P43/TxD6

P31/TI010/TO00

P41

INTP1

INTP2

INTP3

RxD6

TxD6

Input

Serial data input for asynchronous serial interface

Serial data output for asynchronous serial interface

Input

P44

Output

Input

P43/INTP1

P30/INTP0

TI000

External count clock input to 16-bit timer/event counter 00.

Capture trigger input to capture registers (CR000 and CR010) of

16-bit timer/event counter 00

TI010

Capture trigger input to capture register (CR000) of 16-bit

timer/event counter 00

P31/TO00/INTP2

TO00

Output

Input

−

16-bit timer/event counter 00 output

8-bit timer H1 output

Input

−

P31/TI010/INTP2

TOH1

P42

ANI0 to ANI3

AVREF

Analog input of A/D converter

P20 to P23

A/D converter reference voltage input and positive power supply

for P20 to P23 and A/D converter

−

AVSS

−

A/D converter ground potential. Make the same potential as

V^SS.

−

RESET ^Note

X1^Note

Input

System reset input

−

P34^Note

Connection of crystal/ceramic resonator for system clock

Input

P121^Note

oscillation.

External clock input

X2^Note

−

Connection of crystal/ceramic resonator for system clock

oscillation.

Input

P122^Note

VDD

VSS

−

Positive power supply

Ground potential

−

Note For settings of alternate function, refer to CHAPTER 18 OPTION BYTE.

Caution The P121/X1 and P122/X2 pins are pulled down during reset.

22

User’s Manual U17446EJ5V0UD

CHAPTER 2 PIN FUNCTIONS

2.2 Pin Functions

2.2.1 P00 to P03 (Port 0)

P00 to P03 function as a 4-bit I/O port. P00 to P03 can be set to input or output in 1-bit units using port mode

register 0 (PM0). Use of an on-chip pull-up resistor can be specified by pull-up resistor option register 0 (PU0).

2.2.2 P20 to P23 (Port 2)

P20 to P23 constitute a 4-bit I/O port, port 2. In addition to I/O port pins, these pins also have a function to input

analog signals to the A/D converter. These pins can be set to the following operation modes in 1-bit units.

(1) Port mode

P20 to P23 function as a 4-bit I/O port. Each bit of this port can be set to the input or output mode by using

port mode register 2 (PM2). In addition, an on-chip pull-up resistor can be connected to the port by using pull-

up resistor option register 2 (PU2).

(2) Control mode

P20 to P23 function as the analog input pins (ANI0 to ANI3) of the A/D converter. When using these pins as

analog input pins, refer to 10.6 Cautions for A/D converter (5) ANI0/P20 to ANI3/P23.

2.2.3 P30 to P34 (Port 3)

P30 to P33 constitute a 4-bit I/O port, port 3. In addition to I/O port pins, P30 and p31 also have functions to

input/output a timer signal, and input an external interrupt request signal.

P34 is a 1-bit input-only port. This pin is also used as a RESET pin, and when the power is turned on, this is the

reset function.

For settings of alternate function, refer to CHAPTER 18 OPTION BYTE. When using P34 as input port, pull up the

P34 pin by using external resistor.

P30 to P34 can be set to the following operation modes in 1-bit units.

(1) Port mode

P30 to P33 function as a 4-bit I/O port. Each bit of this port can be set to the input or output mode by using

port mode register 3 (PM3). In addition, an on-chip pull-up resistor can be connected to the port by using pull-

up resistor option register 3 (PU3).

P34 functions as a 1-bit input-only port.

(2) Control mode

P30 and P31 function to input/output signals to/from internal timers, and to input an external interrupt request

signal.

(a) INTP0 and INTP2

These are external interrupt request input pins for which the valid edge (rising edge, falling edge, or both

rising and falling edges) can be specified.

(b) TI000

This pin inputs an external count clock to 16-bit timer/event counter 00, or a capture trigger signal to the

capture registers (CR000 and CR010) of 16-bit timer/event counter 00.

(c) TI010

This pin inputs a capture trigger signal to the capture register (CR000) of 16-bit timer/event counter 00.

23

User’s Manual U17446EJ5V0UD

CHAPTER 2 PIN FUNCTIONS

(d) TO00

This pin outputs a signal from 16-bit timer/event counter 00.

2.2.4 P40 to P47 (Port 4)

P40 to P47 constitute an 8-bit I/O port, port 4. In addition to I/O port pins, P41 to P44 also have functions to output

a timer signal, input external interrupt request signals, and input/output the data of the serial interface.

These pins can be set to the following operation modes in 1-bit units.

(1) Port mode

P40 to P47 function as an 8-bit I/O port. Each bit of this port can be set to the input or output mode by using

port mode register 4 (PM4). In addition, an on-chip pull-up resistor can be connected to the port by using pull-

up resistor option register 4 (PU4).

(2) Control mode

P41 to 44 function to output a signal from an internal timer, input external interrupt request signals, and

input/output data of the serial interface.

(a) INTP1 and INTP3

These are external interrupt request input pins for which the valid edge (rising edge, falling edge, or both

rising and falling edges) can be specified.

(b) TOH1

This is the output pin of 8-bit timer H1.

(c) TxD6

This pin outputs serial data from the asynchronous serial interface.

(d) RxD6

This pin inputs serial data to the asynchronous serial interface.

2.2.5 P120 to P123 (Port 12)

P120 to P123 constitute a 4-bit I/O port, port 12.

Each bit of this port can be set to the input or output mode by using port mode register 12 (PM12). An on-chip pull-

up resistor can be connected to P120 and P123 by using pull-up resistor option register 12 (PU12).

P121 and P122 also function as the X1 and X2, respectively. For settings of alternate function, refer to CHAPTER

18 OPTION BYTE.

Caution The P121/X1 and P122/X2 pins are pulled down during reset.

2.2.6 P130 (Port 13)

This is a 1-bit output-only port.

2.2.7 RESET

This pin inputs an active-low system reset signal. When the power is turned on, this is the reset function,

regardless of the option byte setting.

24

User’s Manual U17446EJ5V0UD

CHAPTER 2 PIN FUNCTIONS

2.2.8 X1 and X2

These pins connect an oscillator to oscillate the X1 input clock.

X1 and X2 also function as the P121 and P122 pins, respectively. For settings of alternate function, refer to

CHAPTER 18 OPTION BYTE.

Supply an external clock to X1.

Caution The P121/X1 and P122/X2 pins are pulled down during reset.

2.2.9 AV^REF

This is the A/D converter reference voltage input pin and the positive power supply pin of P20 to P23 and A/D

converter. When the A/D converter is not used, connect this pin to V^DD.

2.2.10 AV^SS

This is the A/D converter ground potential pin. Even when the A/D converter is not used, always use this pin with

the same potential as the V^SSpin.

2.2.11 V^DD

This is the positive power supply pin.

2.2.12 V^SS

This is the ground pin.

25

User’s Manual U17446EJ5V0UD

CHAPTER 2 PIN FUNCTIONS

2.3 Pin I/O Circuits and Connection of Unused Pins

Table 2-1 shows I/O circuit type of each pin and the connections of unused pins.

For the configuration of the I/O circuit of each type, refer to Figure 2-1.

Table 2-1. Types of Pin I/O Circuits and Connection of Unused Pins

Pin Name

P00 to P03

I/O Circuit Type

8-A

I/O

Recommended Connection of Unused Pin

I/O

Input: Independently connect to VDD or VSS via a resistor.

Output: Leave open.

P20/ANI0 to P23/ANI3

11

Input: Independently connect to AVREF or VSS via a resistor.

Output: Leave open.

P30/TI000/INTP0

P31/TI010/TO00/INTP2

P32 and P33

P34/RESET

P40

8-A

Input: Independently connect to V^DDor VSS via a resistor.

Output: Leave open.

2

Input

I/O

Connect to VDD via a resistor.

8-A

Input: Independently connect to V^DDor VSS via a resistor.

Output: Leave open.

P41/INTP3

P42/TOH1

P43/TxD6/INTP1

P44/RxD6

P45 to P47

P120

P121/X1

16-B

8-A

Input: Independently connect to V^SSvia a resistor.

Output: Leave open.

P122/X2

P123

Input:

Independently connect to VDD or VSS via a resistor.

Output: Leave open.

P130

AVREF

AVSS

3-C

Output

Input

−

Leave open.

−

Connect directly to VDD.

Connect directly to VSS.

−

26

User’s Manual U17446EJ5V0UD

CHAPTER 2 PIN FUNCTIONS

Figure 2-1. Pin I/O Circuits

V

DD

Type 2

Type 11

Pull up

enable

P-ch

AV^REF

P-ch

Data

IN

IN/OUT

Output

disable

N-ch

V

SS

Schmitt-triggered input with hysteresis characteristics

Comparator

P-ch

N-ch

+

-

AVSS

AVREF

(Threshold voltage)

Input

enable

Type 3-C

Type 16-B

Feedback

cut-off

P-ch

V

DD

P-ch

OSC

enable

Data

OUT

X1,

IN/OUT

X2,

IN/OUT

N-ch

V

SS

V

DD

Data

P-ch

Type 8-A

Output

disable

N-ch

V

DD

V

SS

Pull up

enable

P-ch

V

DD

Data

P-ch

N-ch

Data

P-ch

N-ch

IN/OUT

Output

Disable

Output

disable

V

SS

V

SS

27

User’s Manual U17446EJ5V0UD

CHAPTER 3 CPU ARCHITECTURE

3.1 Memory Space

The 78K0S/KB1+ can access up to 64 KB of memory space. Figures 3-1 and 3-2 show the memory maps.

Figure 3-1. Memory Map (μPD78F9232)

F F F F H

Special function registers

(SFR)

256 × 8 bits

F F 0 0 H

F E F F H

Internal high-speed RAM

256 × 8 bits

F E 0 0 H

F D F F H

Use prohibited

Data memory

space

0 F F F H

1 0 0 0 H

0 F F F H

Program area

0 0 8 2 H

Protect byte area

Option byte area

0 0 8 1 H

0 0 8 0 H

0 0 7 F H

Program memory

space

Flash memory

4,096 × 8 bits

CALLT table area

Program area

0 0 4 0 H

0 0 3 F H

0 0 2 2 H

0 0 2 1 H

Vector table area

0 0 0 0 H

Remark The option byte and protect byte are 1 byte each.

28

User’s Manual U17446EJ5V0UD

CHAPTER 3 CPU ARCHITECTURE

Figure 3-2. Memory Map (μPD78F9234)

F F F F H

Special function registers

(SFR)

256 × 8 bits

F F 0 0 H

F E F F H

Internal high-speed RAM

256 × 8 bits

F E 0 0 H

F D F F H

Use prohibited

Data memory

space

1 F F F H

2 0 0 0 H

1 F F F H

Program area

0 0 8 2 H

0 0 8 1 H

0 0 8 0 H

0 0 7 F H

Protect byte area

Option byte area

Flash memory

8,192 × 8 bits

Program memory

space

CALLT table area

Program area

0 0 4 0 H

0 0 3 F H

0 0 2 2 H

0 0 2 1 H

Vector table area

0 0 0 0 H

Remark The option byte and protect byte are 1 byte each.

29

User’s Manual U17446EJ5V0UD

CHAPTER 3 CPU ARCHITECTURE

3.1.1 Internal program memory space

The internal program memory space stores programs and table data. This space is usually addressed by the

program counter (PC).

The 78K0S/KB1+ provides the following internal ROMs (or flash memory) containing the following capacities.

Table 3-1. Internal ROM Capacity

Part Number

Internal ROM

Structure

Flash memory

Capacity

4,096 × 8 bits

8,192 × 8 bits

μPD78F9232

μPD78F9234

The following areas are allocated to the internal program memory space.

(1) Vector table area

The 34-byte area of addresses 0000H to 0021H is reserved as a vector table area. This area stores program

start addresses to be used when branching by RESET input or interrupt request generation. Of a

16-bit address, the lower 8 bits are stored in an even address, and the higher 8 bits are stored in an odd

address.

Table 3-2. Vector Table

Vector Table Address

0000H

Interrupt Request

Reset input

Vector Table Address

0012H

Interrupt Request

INTAD

0006H

0008H

000AH

000CH

000EH

0010H

INTLVI

0016H

0018H

001AH

001CH

001EH

0020H

INTP2

INTP0

INTP3

INP1

INTTM80

INTSRE6

INTSR6

INTST6

INTTMH1

INTTM000

INTTM010

Caution No interrupt sources correspond to the vector table address 0014H.

(2) CALLT instruction table area

The subroutine entry address of a 1-byte call instruction (CALLT) can be stored in the 64-byte area of

addresses 0040H to 007FH.

(3) Option byte area

The option byte area is the 1-byte area of address 0080H. For details, refer to CHAPTER 18 OPTION

BYTE.

(4) Protect byte area

The protect byte area is the 1-byte area of address 0081H. For details, refer to CHAPTER 19 FLASH

MEMORY.

3.1.2 Internal data memory space

μPD78F9232 and μPD78F9234 provide 256-byte internal high-speed RAM.

The internal high-speed RAM can also be used as a stack memory.

30

User’s Manual U17446EJ5V0UD

CHAPTER 3 CPU ARCHITECTURE

3.1.3 Special function register (SFR) area

Special function registers (SFRs) of on-chip peripheral hardware are allocated to the area of FF00H to FFFFH (see

Table 3-3).

3.1.4 Data memory addressing

The 78K0S/KB1+ is provided with a wide range of addressing modes to make memory manipulation as efficient as

possible. The area (FE00H to FEFFH) which contains a data memory and the special function register area (SFR)

can be accessed using a unique addressing mode in accordance with each function. Figures 3-3 and 3-4 illustrate the

data memory addressing.

Figure 3-3. Data Memory Addressing (μPD78F9232)

F F F F H

Special function registers (SFR)

SFR addressing

256 × 8 bits

F F 2 0 H

F F 1 F H

F F 0 0 H

F E F F H

Short direct addressing

Internal high-speed RAM

256 × 8 bits

F E 2 0 H

F E 1 F H

F E 0 0 H

F D F F H

Direct addressing

Register indirect addressing

Based addressing

Use prohibited

1 0 0 0 H

0 F F F H

Flash memory

4,096 × 8 bits

0 0 0 0 H

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CHAPTER 3 CPU ARCHITECTURE

Figure 3-4. Data Memory Addressing (μPD78F9234)

F F F F H

Special function registers (SFR)

SFR addressing

256 × 8 bits

F F 2 0 H

F F 1 F H

F F 0 0 H

F E F F H

Short direct addressing

Internal high-speed RAM

256 × 8 bits

F E 2 0 H

F E 1 F H

F E 0 0 H

F D F F H

Direct addressing

Register indirect addressing

Based addressing

Use prohibited

2 0 0 0 H

1 F F F H

Flash memory

8,192 × 8 bits

0 0 0 0 H

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CHAPTER 3 CPU ARCHITECTURE

3.2 Processor Registers

The 78K0S/KB1+ provides the following on-chip processor registers.

3.2.1 Control registers

The control registers have special functions to control the program sequence statuses and stack memory. The

control registers include a program counter, a program status word, and a stack pointer.

(1) Program counter (PC)

The program counter is a 16-bit register which holds the address information of the next program to be

executed.

In normal operation, the PC is automatically incremented according to the number of bytes of the instruction to

be fetched. When a branch instruction is executed, immediate data or register contents are set.

Reset signal generation sets the reset vector table values at addresses 0000H and 0001H to the program

counter.

Figure 3-5. Program Counter Configuration

15

0

PC PC15 PC14 PC13 PC12 PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0

(2) Program status word (PSW)

The program status word is an 8-bit register consisting of various flags to be set/reset by instruction execution.

Program status word contents are stored in stack area upon interrupt request generation or PUSH PSW

instruction execution and are restored upon execution of the RETI and POP PSW instructions.

Reset signal generation sets PSW to 02H.

Figure 3-6. Program Status Word Configuration

7

0

IE

Z

0

AC

0

1

CY

PSW

(a) Interrupt enable flag (IE)

This flag controls interrupt request acknowledge operations of the CPU.

When IE = 0, the interrupt disabled (DI) status is set. All interrupt requests are disabled.

When IE = 1, the interrupt enabled (EI) status is set. Interrupt request acknowledgment is controlled with

an interrupt mask flag for various interrupt sources.

This flag is reset to 0 upon DI instruction execution or interrupt acknowledgment and is set to 1 upon EI

instruction execution.

(b) Zero flag (Z)

When the operation result is zero, this flag is set to 1. It is reset to 0 in all other cases.

(c) Auxiliary carry flag (AC)

If the operation result has a carry from bit 3 or a borrow at bit 3, this flag is set to 1. It is reset to 0 in all

other cases.

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CHAPTER 3 CPU ARCHITECTURE

(d) Carry flag (CY)

This flag stores overflow and underflow that have occurred upon add/subtract instruction execution. It

stores the shift-out value upon rotate instruction execution and functions as a bit accumulator during bit

operation instruction execution.

(3) Stack pointer (SP)

This is a 16-bit register to hold the start address of the memory stack area. Only the internal high-speed RAM

area can be set as the stack area (the stack area cannot be set except internal high-speed RAM area).

Figure 3-7. Stack Pointer Configuration

15

0

SP SP15 SP14 SP13 SP12 SP11 SP10 SP9 SP8 SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0

The SP is decremented before writing (saving) to the stack memory and is incremented after reading

(restoring) from the stack memory.

Each stack operation saves/restores data as shown in Figures 3-8 and 3-9.

Cautions 1. Since generation of reset signal makes the SP contents undefined, be sure to initialize

the SP before using the stack memory.

2. Stack pointers can be set only to the high-speed RAM area, and only the lower 10 bits

can be actually set.

Thus, if the stack pointer is specified to 0FF00H, it is converted to 0FB00H in the high-

speed RAM area, since 0FF00H is in the SFR area and not in the high-speed RAM area.

When the value is actually pushed onto the stack, 1 is subtracted from 0FB00H to

become 0FAFFH, but since that value is not in the high-speed RAM area, it is converted

to 0FEFFH, which is the same value as when 0FF00H is set to the stack pointer.

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CHAPTER 3 CPU ARCHITECTURE

Figure 3-8. Data to Be Saved to Stack Memory

Interrupt

PUSH rp

CALL, CALLT

instruction

instructions

_

SP

3

2

1

_

SP

2

1

SP

2

1

PC7 to PC0

PC15 to PC8

PSW

Lower half

register pairs

PC7 to PC0

Upper half

register pairs

PC15 to PC8

SP

Figure 3-9. Data to Be Restored from Stack Memory

POP rp

RET instruction

RETI instruction

instruction

Lower half

register pairs

SP

PC7 to PC0

SP

PC7 to PC0

PC15 to PC8

PSW

Upper half

register pairs

PC15 to PC8

SP + 1

SP + 2

SP + 1

SP + 2

SP + 1

SP + 2

SP + 3

SP

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CHAPTER 3 CPU ARCHITECTURE

3.2.2 General-purpose registers

A general-purpose register consists of eight 8-bit registers (X, A, C, B, E, D, L, and H).

In addition each register being used as an 8-bit register, two 8-bit registers in pairs can be used as a 16-bit register

(AX, BC, DE, and HL).

Registers can be described in terms of function names (X, A, C, B, E, D, L, H, AX, BC, DE, and HL) and absolute

names (R0 to R7 and RP0 to RP3).

Figure 3-10. General-Purpose Register Configuration

(a) Function names

16-bit processing

HL

8-bit processing

H

L

D

E

DE

BC

AX

B

C

A

X

15

0

7

0

(b) Absolute names

16-bit processing

RP3

8-bit processing

R7

R6

R5

R4

RP2

RP1

RP0

R3

R2

R1

R0

15

0

7

0

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CHAPTER 3 CPU ARCHITECTURE

3.2.3 Special function registers (SFRs)

Unlike the general-purpose registers, each special function register has a special function.

The special function registers are allocated to the 256-byte area FF00H to FFFFH.

The special function registers can be manipulated, like the general-purpose registers, with operation, transfer, and

bit manipulation instructions. Manipulatable bit units (1, 8, and 16) differ depending on the special function register

type.

Each manipulation bit unit can be specified as follows.

• 1-bit manipulation

Describes a symbol reserved by the assembler for the 1-bit manipulation instruction operand (sfr.bit). This

manipulation can also be specified with an address and bit.

• 8-bit manipulation

Describes a symbol reserved by the assembler for the 8-bit manipulation instruction operand (sfr). This

manipulation can also be specified with an address.

• 16-bit manipulation

Describes a symbol reserved by the assembler for the 16-bit manipulation instruction operand. When specifying

an address, describe an even address.

Table 3-3 lists the special function registers. The meanings of the symbols in this table are as follows:

• Symbol

Indicates the addresses of the implemented special function registers. It is defined as a reserved word in the

RA78K0S, and is defined as an sfr variable using the #pragma sfr directive in the CC78K0S. Therefore, these

symbols can be used as instruction operands if an assembler or integrated debugger is used.

• R/W

Indicates whether the special function register can be read or written.

R/W: Read/write

R: Read only

W: Write only

• Number of bits manipulated simultaneously

Indicates the bit units (1, 8, and 16) in which the special function register can be manipulated.

• After reset

Indicates the status of the special function register when a reset signal is generated.

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Table 3-3. Special Function Registers (1/4)

<R>

Address

Symbol

Bit No.

R/W

Number of Bits

Manipulated

After

Reset

Simultaneously

7

0

6

0

5

0

4

0

3

2

1

0

1

8

16

FF00H P0

P03

P02

P01

P00

R/W

√

−

00H

68

Note 1

FF01H

−

0

−

0

−

0

−

0

−

√

−

√

−

00H

−

FF02H P2

FF03H P3

FF04H P4

P23

P33

P43

−

P22

P32

P42

−

P21

P31

P41

−

P20

P30

P40

−

R/W

68

−

Note 1

0

P34

P44

−

P47

−

P46

−

P45

−

FF05H to

FF0BH

−

FF0CH P12

FF0DH P13

0

−

0

−

0

−

0

−

P123

P122

P121

P120

R/W

√

−

√

−

√

00H

68

Note 1

0

−

0

−

0

−

P130

00H

FF0EH CMP01

FF0FH CMP11

FF10H MUL MU

−

R/W

R

00H

138

220

00H

Undefined

0L

L0

FF11H MUL

0H

−

√

220

90

Note 2

√

FF12H TM00

FF13H

−

0

−

0

−

0

−

0

−

0

−

0

−

0000H

Undefined

FF14H CR000

FF15H

R/W

−

90

92

FF16H CR010

FF17H

FF18H ADCR

FF19H

R

170

FF1AH ADCRH

−

√

−

171

FF1BH

−

to FF21H

FF20H PM0

FF21H

1

−

1

−

1

−

1

−

1

PM03 PM02 PM01 PM00

R/W

−

√

−

√

−

√

−

FFH

−

67

−

FF22H PM2

FF23H PM3

FF24H PM4

PM23 PM22 PM21 PM20

PM33 PM32 PM31 PM30

R/W

FFH

67, 171

67, 98

PM47 PM46 PM45 PM44 PM43 PM42 PM41 PM40

67, 141,

197

FF25H to

FF2BH

−

FF2CH PM12

1

PM123 PM122 PM121 PM120 R/W

√

−

√

−

FFH

67

FF2DH

−

to FF2FH

FF30H PU0

FF31H

0

−

0

−

0

−

0

−

0

PU03 PU02 PU01 PU00

R/W

−

√

−

√

−

√

−

00H

−

70

−

FF32H PU2

FF33H PU3

PU23 PU22 PU21 PU20

PU33 PU32 PU31 PU30

R/W

00H

70

Notes 1. Only P34 is an input-only port.

2. A 16-bit access is possible only by the short direction addressing.

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CHAPTER 3 CPU ARCHITECTURE

<R>

Table 3-3. Special Function Registers (2/4)

Address Symbol

Bit No.

R/W

Number of Bits

Manipulated

After

Reset

Simultaneously

7

PU47

−

6

PU46

−

5

PU45

−

4

3

PU43

−

2

PU42

−

1

PU41

−

0

PU40

−

1

√

−

8

√

−

16

FF34H PU4

PU44

R/W

−

00H

70

FF35H to

FF3BH

−

FF3CH PU12

0

PU123

0

PU120 R/W

√

−

√

−

00H

70

FF3DH

−

to FF47H

FF48H WDTM

0

1

WDCS WDCS WDCS WDCS WDCS R/W

−

√

−

67H

9AH

154

4

−

0

3

−

0

2

−

0

1

0

FF49H WDTE

FF50H LVIM

−

√

−

155

261

<LVI

ON>

0

<LVI

MD>

<LVI

F>

00H

Note 1

FF51H LVIS

0

−

0

−

0

−

0

−

0

−

0

−

0

−

0

−

0

−

0

LVIS3 LVIS2 LVIS1 LVIS0

−

√

−

√

−

√

−

√

−

√

−

√

−

√

−

√

−

00H

262

−

Note 1

FF52H,

FF53H

−

0

−

0

−

0

−

0

−

0

−

0

−

LVIRF

−

R

−

FF54H RESF

WDT

RF

00H

255

−

Note 2

FF55H to

FF57H

−

0

−

0

−

00H

−

FF58H LSRCM

<LSR

R/W

−

76

−

STOP>

FF59H to

FF5FH

−

FF60H TMC00

FF61H PRM00

FF62H CRC00

FF63H TOC00

TMC

003

TMC

002

TMC

001

<OVF

00>

R/W

00H

−

93

97

95

96

−

ES110 ES100 ES010 ES000

0

PRM

001

PRM

000

0

−

0

CRC

002

CRC

001

CRC

000

<OSPT <OSPE TOC

<LVS

00>

<LVR

00>

TOC

001

<TOE

00>

004

FF64H to

FF6FH

−

FF70H TMHMD <TMH CKS12 CKS11 CKS10 TMMD TMMD <TOLE <TOEN R/W

00H

−

139

−

1

E1>

11

10

V1>

1>

FF71H to

FF7FH

−

FF80H ADM

FF81H ADS

<ADCS>

0

−

FR2

0

FR1

0

FR0

0

−

0

ADS1

−

<ADCE> R/W

ADS0

√

−

√

−

00H

−

168

170

−

0

FF82H,

FF83H

−

Notes 1. Retained only after a reset by LVI.

2. Varies depending on the reset cause.

Remark For a bit name enclosed in angle brackets (<>), the bit name is defined as a reserved word in the RA78K0S,

and is defined as an sfr variable using the #pragma sfr directive in the CC78K0S.

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CHAPTER 3 CPU ARCHITECTURE

<R>

Table 3-3. Special Function Registers (3/4)

Address Symbol

FF84H PMC2

Bit No.

R/W

Number of Bits

Manipulated

After

Reset

Simultaneously

7

0

−

6

0

−

5

0

−

4

0

−

3

2

1

0

1

√

−

8

√

−

16

PMC23 PMC22 PMC21 PMC20 R/W

−

00H

69, 171

FF85H to

FF8BH

−

FF8CH ISC

0

ISC1

ISC0

R/W

√

−

√

−

00H

197

FF8DH

−

to FF8FH

FF90H ASIM6

<POW <TXE6> <RXE6> PS61

ER6>

PS60

CL6

SL6

ISRM6 R/W

√

−

01H

189

FF91H

−

0

−

0

−

0

−

0

−

0

−

0

−

0

−

0

−

0

−

0

−

√

−

√

−

FFH

00H

FFH

00H

FFH

16H

−

FF92H RXB6

FF93H ASIS6

FF94H TXB6

FF95H ASIF6

FF96H CKSR6

−

OVE6

−

R

188

191

188

192

193

194

195

PE6

−

FE6

−

R/W

R

0

TXBF6 TXSF6

TPS63 TPS62 TPS61 TPS60 R/W

FF97H BRGC6 MLD67 MLD66 MLD65 MLD64 MLD63 MLD62 MLD61 MLD60

FF98H ASICL6 <SBRF <SBRT SBTT6 SBL62 SBL61 SBL60

DIR6 TXDLV

6

6>

FF99H to

FF9FH

−

FFA0H PFCMD REG7 REG6 REG5 REG4 REG3

REG2

REG1 REG0

W

−

√

−

Undefined

287

FFA1H PFS

0

WEPR

ERR

VCE

RR

FPR

ERR

R/W

00H

FFA2H FLPMC

FFA3H FLCMD

PRSEL PRSEL PRSEL PRSEL PRSEL

0

FLSPM

−

√

−

Undefined

00H

286

289

F4

F3

F2

F1

F0

FLCMD FLCMD FLCM

D0

FLAP7 FLAP6 FLAP5 FLAP4 FLAP3 FLAP2 FLAP1 FLAP0

0

2

1

FFA4H FLAPL

FFA5H FLAPH

√

−

Undefined

290

0

FLA

P12

FLA

P11

FLA

P10

FLA

P9

FLA

P8

FFA6H FLAPHC

0

FLAP

C12

FLAP

C11

FLAP

C10

FLAP

C9

FLAP

C8

√

−

00H

290

FFA7H FLAPLC FLAP

C7

FLAP

C6

FLAP

C5

FLAP

C4

FLAP

C3

FLAP

C2

FLAP

C1

FLAP

C0

FFA8H FLW

FLW7

FLW6

FLW5

FLW4

FLW3

FLW2

FLW1

FLW0

−

√

−

291

FFA9H to

FFCBH

−

FFCCH TMC80

<TCE

80>

0

TCL

801

TCL

800

0

R/W

√

−

00H

132

FFCDH CR80

FFCEH TM80

−

W

R

−

√

−

Undefined

00H

−

131

−

FFCFH

−

Remark For a bit name enclosed in angle brackets (<>), the bit name is defined as a reserved word in the RA78K0S,

and is defined as an sfr variable using the #pragma sfr directive in the CC78K0S.

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CHAPTER 3 CPU ARCHITECTURE

<R>

Table 3-3. Special Function Registers (4/4)

Address Symbol

Bit No.

R/W

Number of Bits

Manipulated

After

Reset

Simultaneously

7

−

0

6

−

0

5

−

0

4

−

0

3

−

0

2

−

0

1

−

0

−

1

−

√

8

√

16

FFD0H MRA0

FFD1H MRB0

FFD2H MULC0

W

−

Undefined

220

222

<MULS R/W

T0>

00H

−

FFD3H to

FFDFH

−

0

−

1

−

√

−

√

−

√

−

√

−

FFE0H IF0

010> 000> H1>

R/W

00H

−

229

−

FFE1H IF1

0

6>

IF6>

80>

FFE2H,

FFE3H

−

FFE4H MK0

<ADM <TMM <TMM <TMM <PMK <PMK

<LVI

MK>

R/W

FFH

−

230

−

K>

1

K010> K000> KH1>

1>

0>

FFE5H MK1

<STMK <SRM <SRE <TMM <PMK <PMK

6>

K6>

MK6>

K80>

3>

2>

FFE6H to

FFEBH

−

FFECH INTM0

FFEDH INTM1

ES21

ES20

ES11

ES10

ES01

ES00

0

ES31

−

0

ES30

−

R/W

−

√

−

00H

−

231

232

−

0

FFEEH

−

to FFF2H

FFF3H PPCC

FFF4H OSTS

0

PPCC1 PPCC0 R/W

OSTS1 OSTS0

√

−

√

−

02H

75

Undefined 77, 240

Note

FFF5H to

FFFAH

−

FFFBH PCC

0

PCC1

0

R/W

√

−

√

−

02H

75

FFFCH

−

to FFFFH

Note The oscillation stabilization time that elapses after release of reset is selected by the option byte. For details,

refer to CHAPTER 18 OPTION BYTE.

Remark For a bit name enclosed in angle brackets (<>), the bit name is defined as a reserved word in the RA78K0S,

and is defined as an sfr variable using the #pragma sfr directive in the CC78K0S.

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CHAPTER 3 CPU ARCHITECTURE

3.3 Instruction Address Addressing

An instruction address is determined by the program counter (PC) contents. The PC contents are normally

incremented (+1 for each byte) automatically according to the number of bytes of an instruction to be fetched each

time another instruction is executed. When a branch instruction is executed, the branch destination address

information is set to the PC to branch by the following addressing (for details of each instruction, refer to 78K/0S

Series Instructions User’s Manual (U11047E)).

3.3.1 Relative addressing

[Function]

The value obtained by adding 8-bit immediate data (displacement value: jdisp8) of an instruction code to the start

address of the following instruction is transferred to the program counter (PC) to branch. The displacement

value is treated as signed two’s complement data (–128 to +127) and bit 7 becomes the sign bit. In other words,

the range of branch in relative addressing is between –128 and +127 of the start address of the following

instruction.

This function is carried out when the BR $addr16 instruction or a conditional branch instruction is executed.

[Illustration]

15

0

...

PC is the start address of

the next instruction of

a BR instruction.

PC

+

8

7

6

α

S

jdisp8

15

0

PC

When S = 0, α indicates that all bits are “0”.

When S = 1, α indicates that all bits are “1”.

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CHAPTER 3 CPU ARCHITECTURE

3.3.2 Immediate addressing

[Function]

Immediate data in the instruction word is transferred to the program counter (PC) to branch.

This function is carried out when the CALL !addr16 and BR !addr16 instructions are executed.

CALL !addr16 and BR !addr16 instructions can be used to branch to all the memory spaces.

[Illustration]

In case of CALL !addr16 and BR !addr16 instructions

7

0

PC

PC+1

PC+2

CALL or BR

Low Addr.

High Addr.

15

8

7

0

PC

3.3.3 Table indirect addressing

[Function]

The table contents (branch destination address) of the particular location to be addressed by the immediate data

of an instruction code from bit 1 to bit 5 are transferred to the program counter (PC) to branch.

Table indirect addressing is carried out when the CALLT [addr5] instruction is executed. This instruction can be

used to branch to all the memory spaces according to the address stored in the memory table 40H to 7FH.

[Illustration]

7

0

6

1

5

1

0

Instruction code

Effective address

ta4–0

15

0

8

0

7

0

6

1

5

1

0

7

Memory (Table)

Low addr.

0

High addr.

Effective address + 1

15

8

7

0

PC

43

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CHAPTER 3 CPU ARCHITECTURE

3.3.4 Register addressing

[Function]

The register pair (AX) contents to be specified with an instruction word are transferred to the program counter

(PC) to branch.

This function is carried out when the BR AX instruction is executed.

[Illustration]

7

0

8

7

0

rp

A

X

15

PC

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CHAPTER 3 CPU ARCHITECTURE

3.4 Operand Address Addressing

The following methods (addressing) are available to specify the register and memory to undergo manipulation

during instruction execution.

3.4.1 Direct addressing

[Function]

The memory indicated by immediate data in an instruction word is directly addressed.

[Operand format]

Identifier

addr16

Description

Label or 16-bit immediate data

[Description example]

MOV A, !0FE80H; When setting !addr16 to FE80H

Instruction code

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

OP code

80H

FEH

[Illustration]

7

0

OP code

addr16 (low)

addr16 (high)

Memory

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3.4.2 Short direct addressing

[Function]

The memory to be manipulated in the fixed space is directly addressed with the 8-bit data in an instruction word.

The fixed space where this addressing is applied is the 256-byte space FE20H to FF1FH (FE20H to FEFFH

(internal high-speed RAM) + FF00H to FF1FH (special function registers)).

The SFR area where short direct addressing is applied (FF00H to FF1FH) is a part of the total SFR area. In this

area, ports which are frequently accessed in a program and a compare register of the timer counter are mapped,

and these SFRs can be manipulated with a small number of bytes and clocks.

When 8-bit immediate data is at 20H to FFH, bit 8 of an effective address is cleared to 0. When it is at 00H to

1FH, bit 8 is set to 1. See [Illustration] below.

[Operand format]

Identifier

saddr

Description

Label or FE20H to FF1FH immediate data

saddrp

Label or FE20H to FF1FH immediate data (even address only)

[Description example]

EQU DATA1 0FE90H; DATA1 indicates FE90H in saddr area

MOV DATA1, #50H; When the immediate data to 50H

Instruction code

1

0

1

0

1

0

1

0

1

0

1

0

OP code

90H (saddr-offset)

50H (immediate data)

[Illustration]

7

0

OP code

saddr-offset

Short direct memory

15

1

8

0

Effective

address

1

α

When 8-bit immediate data is 20H to FFH, = 0.

α

When 8-bit immediate data is 00H to 1FH, = 1.

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3.4.3 Special function register (SFR) addressing

[Function]

A memory-mapped special function register (SFR) is addressed with the 8-bit immediate data in an instruction

word.

This addressing is applied to the 256-byte space FF00H to FFFFH. However, SFRs mapped at FF00H to

FF1FH are accessed with short direct addressing.

[Operand format]

Identifier

sfr

Description

Special function register name

[Description example]

MOV PM0, A; When selecting PM0 for sfr

Instruction code

1

0

1

0

1

0

1

0

1

0

1

0

[Illustration]

7

0

OP code

sfr-offset

SFR

15

1

8 7

0

Effective

address

1

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3.4.4 Register addressing

[Function]

A general-purpose register is accessed as an operand.

The general-purpose register to be accessed is specified with the register specify code and functional name in

the instruction code.

Register addressing is carried out when an instruction with the following operand format is executed. When an

8-bit register is specified, one of the eight registers is specified with 3 bits in the instruction code.

[Operand format]

Identifier

Description

r

X, A, C, B, E, D, L, H

AX, BC, DE, HL

rp

‘r’ and ‘rp’ can be described with absolute names (R0 to R7 and RP0 to RP3) as well as function names (X, A, C,

B, E, D, L, H, AX, BC, DE, and HL).

[Description example]

MOV A, C; When selecting the C register for r

Instruction code

0

1

0

1

0

1

0

1

Register specify code

INCW DE; When selecting the DE register pair for rp

Instruction code

1

0

1

0

Register specify code

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3.4.5 Register indirect addressing

[Function]

The memory is addressed with the contents of the register pair specified as an operand. The register pair to be

accessed is specified with the register pair specify code in the instruction code. This addressing can be carried

out for all the memory spaces.

[Operand format]

Identifier

Description

−

[DE], [HL]

[Description example]

MOV A, [DE]; When selecting register pair [DE]

Instruction code

0

1

0

1

0

1

[Illustration]

15

8

7

0

DE

D

E

Memory address specified

by register pair DE

The contents of addressed

memory are transferred

7

0

A

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3.4.6 Based addressing

[Function]

8-bit immediate data is added to the contents of the base register, that is, the HL register pair, and the sum is

used to address the memory. Addition is performed by expanding the offset data as a positive number to 16 bits.

A carry from the 16th bit is ignored. This addressing can be carried out for all the memory spaces.

[Operand format]

Identifier

Description

−

[HL+byte]

[Description example]

MOV A, [HL+10H]; When setting byte to 10H

Instruction code

0

1

0

1

0

1

0

1

0

[Illustration]

16

8

7

0

HL

H

L

+10

7

Memory

0

The contents of the memory

addressed are transferred.

7

0

A

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3.4.7 Stack addressing

[Function]

The stack area is indirectly addressed with the stack pointer (SP) contents.

This addressing method is automatically employed when the PUSH, POP, subroutine call, and return instructions

are executed or the register is saved/restored upon interrupt request generation.

Stack addressing can be used to access the internal high-speed RAM area only.

[Description example]

In the case of PUSH DE

Instruction code

1

0

1

0

1

0

1

0

[Illustration]

7

Memory

0

FEE0H

FEDEH

FEE0H

FEDFH

FEDEH

SP

D

E

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4.1 Functions of Ports

The 78K0S/KB1+ has the ports shown in Figure 4-1, which can be used for various control operations. Table 4-1

shows the functions of each port.

In addition to digital I/O port functions, each of these ports has an alternate function. For details, refer to

CHAPTER 2 PIN FUNCTIONS.

Figure 4-1. Port Functions

P00

P40

Port 0

Port 2

P03

P20

Port 4

P47

P23

P30

P120

Port 12

Port 13

Port 3

P123

P130

P33

P34

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Table 4-1. Port Functions

Pin Name

I/O

Function

After Reset

Input

Alternate-

Function Pin

P00 to P03

I/O

Port 0.

−

4-bit I/O port.

Can be set to input or output mode in 1-bit units.

On-chip pull-up resistor can be connected by setting software.

P20 to P23

Port 2.

Input

ANI0 to ANI3

4-bit I/O port.

Can be set to input or output mode in 1-bit units.

On-chip pull-up resistor can be connected by setting software.

P30

P31

Port 3

Can be set to input or output mode in 1- Input

TI000/INTP0

bit units.

TI010/TO00/

INTP2

On-chip pull-up resistor can be

connected by setting software.

P32

−

P33

−

P34^Note

Input

I/O

Input only

Input

RESET^Note

P40

Port 4.

−

8-bit I/O port.

P41

INTP3

Can be set to input or output mode in 1-bit units.

P42

TOH1

On-chip pull-up resistor can be connected by setting software.

P43

TxD6/INTP1

P44

RxD6

P45

−

P46

−

P47

−

P120

P121^Note

P122^Note

P123

P130

I/O

Port 12.

Input

−

4-bit I/O port.

X1^Note

X2^Note

−

Can be set to input or output mode in 1-bit units.

On-chip pull-up resistor can be connected only to P120 and

P123 by setting software.

Output

Port 13.

Output

−

1-bit output-only port.

Note For settings of alternate function, refer to CHAPTER 18 OPTION BYTE.

Caution The P121/X1 and P122/X2 pins are pulled down during reset.

Remarks 1. P121 and P122 can be allocated when the high-speed internal oscillation is selected as the system

clock.

2. P122 can be allocated when an external clock is selected as the system clock.

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4.2 Port Configuration

Ports consist of the following hardware units.

Table 4-2. Configuration of Ports

Item

Configuration

Port mode registers (PM0, PM2, PM3, PM4, PM12)

Control registers

Port registers (P0, P2, P3, P4, P12, P13)

Port mode control register 2 (PMC2)

Pull-up resistor option registers (PU0, PU2, PU3, PU4, PU12)

Ports

Total: 26 (CMOS I/O: 24, CMOS input: 1, CMOS output: 1)

Total: 22

Pull-up resistor

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4.2.1 Port 0

Port 0 is a 4-bit I/O port with an output latch. Each bit of this port can be set to the input or output mode by using

port mode register 0 (PM0). When the P00 to P03 pins are used as an input port, an on-chip pull-up resistor can be

connected in 1-bit units by using pull-up resistor option register 0 (PU0).

This port is also used as the analog input pins of the internal A/D converter.

Generation of reset signal sets port 0 to the input mode.

Figure 4-2 shows the block diagram of port 0.

Figure 4-2. Block Diagram of P00 to P03

VDD

WR^PU

PU0

PU00 to PU03

P-ch

RD

WR^PORT

P0

Output latch

(P00 to P03)

P00 to P03

WRPM

PM0

PM00 to PM03

PU0:

P0:

Pull-up resistor option register 0

Port register 0

PM0:

RD:

Port mode register 0

Read signal

WR××: Write signal

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4.2.2 Port 2

Port 2 is a 4-bit I/O port with an output latch. Each bit of this port can be set to the input or output mode by using

port mode register 2 (PM2). When the P20 to P23 pins are used as an input port, an on-chip pull-up resistor can be

connected in 1-bit units by using pull-up resistor option register 2 (PU2).

This port is also used as the analog input pins of the internal A/D converter.

Generation of reset signal sets port 2 to the input mode.

Figure 4-2 shows the block diagram of port 2.

Figure 4-3. Block Diagram of P20 to P23

V

DD

WR^PU

PU2

PU20 to PU23

P-ch

WRPMC

PMC2

PMC20 to PMC23

RD

WRPORT

WRPM

P2

Output latch

(P20 to P23)

P20/ANI0 to P23/ANI3

PM2

PM20 to PM23

A/D converter

PU2:

Pull-up resistor option register 2

Port register 2

P2:

PM2:

Port mode register 2

PMC2: Port mode control register 2

RD: Read signal

WR××: Write signal

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4.2.3 Port 3

Pins P30 to P33 constitute a 4-bit I/O port with an output latch. Each bit of this port can be set to the input or

output mode by using port mode register 3 (PM3). When the P30 to P33 pins are used as an input port, an on-chip

pull-up resistor can be connected in 1-bit units by using pull-up resistor option register 3 (PU3).

The P30 and P31 pins are also used for both timer I/O and external interrupt request input pin functions.

Generation of reset signal sets port 3 to the input mode.

P34 is a 1-bit input-only port. This pin is also used as a RESET pin, and when the power is turned on, this is the

reset function.

For settings of alternate function, refer to CHAPTER 18 OPTION BYTE. When using P34 as input port, pull up the

P34 pin by using external resistor.

Figures 4-4 to 4-7 show the block diagrams of port 3.

Figure 4-4. Block Diagram of P30

V

DD

WRPU

PU3

PU30

P-ch

Alternate

function

RD

WR^PORT

P3

Output latch

(P30)

P30/TI000/INTP0

WRPM

PM3

PM30

PU3:

P3:

Pull-up resistor option register 3

Port register 3

PM3:

RD:

Port mode register 3

Read signal

WR××: Write signal

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Figure 4-5. Block Diagram of P31

VDD

WRPU

PU3

PU31

P-ch

Alternate

function

RD

WR^PORT

P3

Output latch

(P31)

P31/TI010/TO00/INTP2

WRPM

PM3

PM31

Alternate

function

PU3:

P3:

Pull-up resistor option register 3

Port register 3

PM3:

RD:

Port mode register 3

Read signal

WR××: Write signal

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Figure 4-6. Block Diagram of P32 and P33

V

DD

WR^PU

PU3

PU32, PU33

P-ch

RD

WR^PORT

P3

Output latch

(P32, P33)

P32, P33

WRPM

PM3

PM32, PM33

PU3:

P3:

Pull-up resistor option register 3

Port register 3

PM3:

RD:

Port mode register 3

Read signal

WR××: Write signal

Figure 4-7. Block Diagram of P34

RD

P34/RESET

Reset

Option

byte

RD:

Read signal

Caution Because the P34 pin functions alternately as the RESET pin, if it is used as an input port pin, the

function to input an external reset signal to the RESET pin cannot be used. The function of the

port is selected by the option byte. For details, refer to CHAPTER 18 OPTION BYTE.

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CHAPTER 4 PORT FUNCTIONS

Also, since the option byte is referenced after the reset release, if low level is input to the RESET

pin before the referencing, then the reset state is not released. When it is used as an input port

pin, connect the pull-up resistor.

4.2.4 Port 4

Port 4 is an 8-bit I/O port with an output latch. Each bit of this port can be set to the input or output mode by using

port mode register 4 (PM4). When the P40 to P47 pins are used as an input port, an on-chip pull-up resistor can be

connected in 1-bit units by using pull-up resistor option register 4 (PU4).

The P41 to P44 pins can also be used for external interrupt request input, serial interface data I/O, and timer

output.

Generation of reset signal sets port 4 to the input mode.

Figures 4-8 to 4-11 show the block diagrams of port 4.

Figure 4-8. Block Diagram of P40, P45 to P47

VDD

WR^PU

PU4

PU40,

PU45 to PU47

P-ch

RD

WR^PORT

P4

Output latch

(P40, P45 to P47)

P40, P45 to P47

WRPM

PM4

PM40,

PM45 to PM47

PU4:

P4:

Pull-up resistor option register 4

Port register 4

PM4:

RD:

Port mode register 4

Read signal

WR××: Write signal

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Figure 4-9. Block Diagram of P41 and P44

VDD

WR^PU

PU4

PU41, PU44

P-ch

Alternate

function

RD

WR^PORT

P4

Output latch

(P41, P44)

P41/INTP3,

P44/RxD6

WRPM

PM4

PM41, PM44

PU4:

Pull-up resistor option register 4

Port register 4

P4:

PM4:

RD:

Port mode register 4

Read signal

WR××: Write signal

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Figure 4-10. Block Diagram of P42

V

DD

WR^PU

PU4

PU42

P-ch

RD

WR^PORT

P4

Output latch

(P42)

P42/TOH1

WRPM

PM4

PM42

Alternate

function

PU4:

P4:

Pull-up resistor option register 4

Port register 4

PM4:

RD:

Port mode register 4

Read signal

WR××: Write signal

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Figure 4-11. Block Diagram of P43

V

DD

WR^PU

PU4

PU43

P-ch

Alternate

function

RD

WR^PORT

P4

Output latch

(P43)

P43/TxD6/INTP1

WRPM

PM4

PM43

Alternate

function

PU4:

P4:

Pull-up resistor option register 4

Port register 4

PM4:

RD:

Port mode register 4

Read signal

WR××: Write signal

4.2.5 Port 12

Port 12 is a 4-bit I/O port with an output latch. Each bit of this port can be set to the input or output mode by using

port mode register 12 (PM12). When the P120 and P123 pins are used as an input port, an on-chip pull-up resistor

can be connected by using pull-up resistor option register 12 (PU12).

The P121 and P122 pins are also used as the X1 and X2 pins of the system clock oscillator. The functions of the

P121 and P122 pins differ, therefore, depending on the selected system clock oscillator. The following three system

clock oscillators can be used.

(1) High-speed internal oscillator

The P121 and P122 pins can be used as I/O port pins.

(2) Crystal/ceramic oscillator

The P121 and P122 pins cannot be used as I/O port pins because they are used as the X1 and X2 pins.

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(3) External clock input

The P121 pin is used as the X1 pin to input an external clock, and therefore it cannot be used as an I/O port pin.

The P122 pin can be used as an I/O port pin.

The system clock oscillation is selected by the option byte. For details, refer to CHAPTER 18 OPTION BYTE.

Generation of reset signal sets port 12 to the input mode.

Figures 4-12 and 4-13 show the block diagrams of port 12.

Figure 4-12. Block Diagram of P120 and P123

V

DD

WR^PU

PU12

PU120, PU123

P-ch

RD

WR^PORT

P12

Output latch

(P120, P123)

P120, P123

WRPM

PM12

PM120, PM123

PU12: Pull-up resistor option register 12

P12: Port register 12

PM12: Port mode register 12

RD: Read signal

WR××: Write signal

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Figure 4-13. Block Diagram of P121 and P122

RD

WR^PORT

P12

Output latch

(P121, P122)

P121/X1,

P122/X2

WRPM

PM12

PM121, PM122

PM12: Port mode register 12

P12:

RD:

Port register 12

Read signal

WR××: Write signal

4.2.6 Port 13

This is a 1-bit output-only port.

Figure 4-14 shows the block diagram of port 13.

Figure 4-14. Block Diagram of P130

RD

WR^PORT

P13

Output latch

(P130)

P130

P13:

RD:

Port register 13

Read signal

WR××: Write signal

Remark When a reset is input, P130 outputs a low level. If P130 outputs a high level immediately after

reset is released, the output signal of P130 can be used as a dummy CPU reset signal.

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4.3 Registers Controlling Port Functions

The ports are controlled by the following four types of registers.

• Port mode registers (PM0, PM2, PM3, PM4, PM12)

• Port registers (P0, P2, P3, P4, P12, P13)

• Port mode control register 2 (PMC2)

• Pull-up resistor option registers (PU0, PU2, PU3, PU4, PU12)

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(1) Port mode registers (PM0, PM2, PM3, PM4, PM12)

These registers are used to set the corresponding port to the input or output mode in 1-bit units.

Each port mode register can be set by a 1-bit or 8-bit memory manipulation instruction.

Generation of reset signal sets these registers to FFH.

When a port pin is used as an alternate-function pin, set its port mode register and output latch as shown in

Table 4-3.

Caution Because P30, P31, and P43 are also used as external interrupt pins, the corresponding

interrupt request flag is set if each of these pins is set to the output mode and its output level

is changed. To use the port pin in the output mode, therefore, set the corresponding

interrupt mask flag to 1 in advance.

Figure 4-15. Format of Port Mode Register

Address: FF20H After reset: FFH R/W

Symbol

PM0

7

1

6

1

5

1

4

1

3

2

1

0

PM03

PM02

PM01

PM00

Address: FF22H After reset: FFH R/W

Symbol

PM2

7

1

6

1

5

1

4

1

3

2

1

0

PM23

PM22

PM21

PM20

Address: FF23H After reset: FFH R/W

Symbol

PM3

7

1

6

1

5

1

4

1

3

2

1

0

PM33

PM32

PM31

PM30

Address: FF24H After reset: FFH R/W

Symbol

PM4

7

6

5

4

3

2

1

0

PM47

PM46

PM45

PM44

PM43

PM42

PM41

PM40

Address: FF2CH After reset: FFH R/W

Symbol

PM12

7

1

6

1

5

1

4

1

3

2

1

0

PM123

PM122

PM121

PM120

PMmn

Selection of I/O mode of Pmn pin (m = 0, 2, 3, 4, or 12; n = 0 to 7)

0

1

Output mode (output buffer ON)

Input mode (output buffer OFF)

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(2) Port registers (P0, P2, P3, P4, P12, P13)

These registers are used to write data to be output from the corresponding port pin to an external device

connected to the chip.

When a port register is read, the pin level is read in the input mode, and the value of the output latch of the

port is read in the output mode.

P00 to P03, P20 to P23, P30 to P34, P40 to P47, P120 to P123, and P130 are set by using a 1-bit or 8-bit

memory manipulation instruction.

Generation of reset signal sets these registers to 00H.

Figure 4-16. Format of Port Register

Address: FF00H After reset: 00H (Output latch) R/W

Symbol

P0

7

0

6

0

5

0

4

0

3

2

1

0

P03

P02

P01

P00

Address: FF02H After reset: 00H (Output latch) R/W

Symbol

P2

7

0

6

0

5

0

4

0

3

2

1

0

P23

P22

P21

P20

Address: FF03H After reset: 00H^Note(Output latch) R/W^Note

Symbol

P3

7

0

6

0

5

0

4

3

2

1

0

P34

P33

P32

P31

P30

Address: FF04H After reset: 00H (Output latch) R/W

Symbol

P4

7

6

5

4

3

2

1

0

P47

P46

P45

P44

P43

P42

P41

P40

Address: FF0CH After reset: 00H (Output latch) R/W

Symbol

P12

7

0

6

0

5

0

4

0

3

2

1

0

P123

P122

P121

P120

Address: FF0DH After reset: 00H (Output latch) R/W

Symbol

P13

7

0

6

0

5

0

4

0

3

0

2

0

1

0

P130

Pmn

m = 0, 2, 3, 4, 12, or 13; n = 0-7

Controls of output data (in output mode) Input data read (in input mode)

Output 0 Input low level

Output 1 Input high level

0

1

Note Because P34 is read-only, its reset value is undefined.

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(3) Port mode control register 2 (PMC2)

This register specifies the port mode or A/D converter mode.

Each bit of the PMC2 register corresponds to each pin of port 2 and can be specified in 1-bit units.

PMC2 is set by using a 1-bit or 8-bit memory manipulation instruction.

Generation of reset signal sets PMC2 to 00H.

Figure 4-17. Format of Port Mode Control Register 2

Address: FF84H After reset: 00H R/W

Symbol

PMC2

7

0

6

0

5

0

4

0

3

2

1

0

PMC23

PMC22

PMC21

PMC20

PMC2n

Specification of operation mode (n = 0 to 3)

0

1

Port mode

A/D converter mode

Caution When PMC20 to PMC23 are set to 1, the P20/ANI0 to P23/ANI3 pins cannot be used as port

pins. Moreover, be sure to set the pull-up resistor option registers (PU20 to PU23) to 0 for

the pins set to A/D converter mode.

Table 4-3. Setting of Port Mode Register, Port Register (Output Latch), and Port Mode Control Register

When Alternate Function Is Used

Port Name

Alternate-Function Pin

Name

PM××

P××

PMC2n

(n = 0 to 3)

I/O

P20 to P23

ANI0 to ANI3

TI000

Input

1

0

1

0

1

×

0

×

0

1

×

1

−

P30

INTP0

TO00

P31

Output

Input

TI010

INTP2

INTP3

TOH1

Input

P41

P42

P43

Input

Output

Input

TxD6

INTP1

RxD6

P44

Input

Remark ×:

don’t care

PM××: Port mode register, P××: Port register (output latch of port)

PMC2×: Port mode control register

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(4) Pull-up resistor option registers (PU0, PU2, PU3, PU4, and PU12)

These registers are used to specify whether an on-chip pull-up resistor is connected to P00 to P03, P20 to

P23, P30 to P33, P40 to P47, P120, and P123. By setting PU0, PU2, PU3, PU4, or PU12, an on-chip pull-up

resistor can be connected to the port pin corresponding to the bit of PU0, PU2, PU3, PU4, or PU12.

PU0, PU2, PU3, PU4, and PU12 are set by using a 1-bit or 8-bit memory manipulation instruction.

Generation of reset signal set these registers to 00H.

Figure 4-18. Format of Pull-up Resistor Option Register

Address: FF30H After reset: 00H R/W

Symbol

PU0

7

0

6

0

5

0

4

0

3

2

1

0

PU03

PU02

PU01

PU00

Address: FF32H After reset: 00H R/W

Symbol

PU2

7

0

6

0

5

0

4

0

3

2

1

0

PU23

PU22

PU21

PU20

Address: FF33H After reset: 00H R/W

Symbol

PU3

7

0

6

0

5

0

4

0

3

2

1

0

PU33

P32

PU31

PU30

Address: FF34H After reset: 00H R/W

Symbol

PU4

7

6

5

4

3

2

1

0

PU47

PU46

PU45

PU44

PU43

PU42

PU41

PU40

Address: FF3CH After reset: 00H R/W

Symbol

PU12

7

0

6

0

5

0

4

0

3

2

0

1

0

PU123

PU120

PUmn

Selection of connection of on-chip pull-up resistor of Pmn (m = 0, 2, 3, 4, or 12; n = 0 to 7)

Does not connect on-chip pull-up resistor

0

1

Connects on-chip pull-up resistor

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4.4 Operation of Port Function

The operation of a port differs, as follows, depending on the setting of the I/O mode.

Caution Although a 1-bit memory manipulation instruction manipulates 1 bit, it accesses a port in 8-bit

units. Therefore, the contents of the output latch of a pin in the input mode, even if it is not

subject to manipulation by the instruction, are undefined in a port with a mixture of inputs and

outputs.

4.4.1 Writing to I/O port

(1) In output mode

A value can be written to the output latch by a transfer instruction. In addition, the data of the output latch is

output from the pin. Once data is written to the output latch, it is retained until new data is written to the output

latch.

Reset signal generation clears the data in the output latch.

(2) In input mode

A value can be written to the output latch by a transfer instruction. Because the output buffer is off, however, the

pin status remains unchanged.

Once data is written to the output latch, it is retained until new data is written to the output latch.

Reset signal generation clears the data in the output latch.

4.4.2 Reading from I/O port

(1) In output mode

The data of the output latch can be read by a transfer instruction. The contents of the output latch remain

unchanged.

(2) In input mode

The pin status can be read by a transfer instruction. The data of the output latch remains unchanged.

4.4.3 Operations on I/O port

(1) In output mode

An operation is performed on the contents of the output latch and the result is written to the output latch. The

data of the output latch is output from the pin.

Once data is written to the output latch, it is retained until new data is written to the output latch.

Reset signal generation clears the data in the output latch.

(2) In input mode

The pin level is read and an operation is performed on its data. The operation result is written to the output latch.

However, the pin status remains unchanged because the output buffer is off.

Reset signal generation clears the data in the output latch.

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5.1 Functions of Clock Generators

The clock generators include a circuit that generates a clock (system clock) to be supplied to the CPU and

peripheral hardware, and a circuit that generates a clock (interval time generation clock) to be supplied to the

watchdog timer and 8-bit timer H1 (TMH1).

5.1.1 System clock oscillators

The following three types of system clock oscillators are used.

• High-speed internal oscillator

This circuit internally oscillates a clock of 8 MHz (TYP.). Its oscillation can be stopped by execution of the STOP

instruction.

If the high-speed internal oscillator is selected to supply the system clock, the X1 and X2 pins can be used as I/O

port pins.

• Crystal/ceramic oscillator

This circuit oscillates a clock with a crystal/ceramic oscillator connected across the X1 and X2 pins. It can

oscillate a clock of 2 to 10 MHz. Oscillation of this circuit can be stopped by execution of the STOP instruction.

• External clock input circuit

This circuit supplies a clock from an external IC to the X1 pin. A clock of 2 to 10 MHz can be supplied. Internal

clock supply can be stopped by execution of the STOP instruction.

If the external clock input is selected as the system clock, the X2 pin can be used as an I/O port pin.

The system clock source is selected by using the option byte. For details, refer to CHAPTER 18 OPTION BYTE.

When using the X1 and X2 pins as I/O port pins, refer to CHAPTER 4 PORT FUNCTIONS for details.

5.1.2 Clock oscillator for interval time generation

The following circuit is used as a clock oscillator for interval time generation.

• Low-speed internal oscillator

This circuit oscillates a clock of 240 kHz (TYP.). Its oscillation can be stopped by using the low-speed internal

oscillation mode register (LSRCM) when it is specified by the option byte that its oscillation can be stopped by

software.

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5.2 Configuration of Clock Generators

The clock generators consist of the following hardware.

Table 5-1. Configuration of Clock Generators

Item

Configuration

Control registers

Processor clock control register (PCC)

Preprocessor clock control register (PPCC)

Low-speed internal oscillation mode register (LSRCM)

Oscillation stabilization time select register (OSTS)

Oscillators

Crystal/ceramic oscillator

High-speed internal oscillator

External clock input circuit

Low-speed internal oscillator

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Figure 5-1. Block Diagram of Clock Generators

Internal bus

Oscillation stabilization

time select register (OSTS)

Processor clock

control register (PCC)

Preprocessor clock

control register (PPCC)

OSTS1 OSTS0

PPCC1 PPCC0

PCC1

System clock oscillation

stabilization time counter

Controller

C

P

U

CPU clock

(f^CPU

)

STOP

Watchdog timer

Prescaler

System clock

oscillator^Note

X1/P121

X2/P122

Crystal/ceramic

oscillation

f

X

f

X

fX

2

2²

External clock

input

High-speed

internal

oscillation

f

XP

2²

f

XP

Prescaler

Clock to peripheral

hardware (f^XP

)

Low-speed

internal

oscillator

f

RL

8-bit timer H1,

watchdog timer

Option byte

1: Cannot be stopped.

0: Can be stopped.

LSRSTOP

Low-speed internal oscillation

mode register (LSRCM)

Internal bus

Note Select the high-speed internal oscillator, crystal/ceramic oscillator, or external clock input as the system

clock source by using the option byte.

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5.3 Registers Controlling Clock Generators

The clock generators are controlled by the following four registers.

• Processor clock control register (PCC)

• Preprocessor clock control register (PPCC)

• Low-speed internal oscillation mode register (LSRCM)

• Oscillation stabilization time select register (OSTS)

(1) Processor clock control register (PCC) and preprocessor clock control register (PPCC)

These registers are used to specify the division ratio of the system clock.

PCC and PPCC are set by using a 1-bit or 8-bit memory manipulation instruction.

Generation of reset signal sets PCC and PPCC to 02H.

Figure 5-2. Format of Processor Clock Control Register (PCC)

Address: FFFBH After reset: 02H R/W

Symbol

PCC

7

0

6

0

5

0

4

0

3

0

2

0

1

0

PCC1

Figure 5-3. Format of Preprocessor Clock Control Register (PPCC)

Address: FFF3H After reset: 02H R/W

Symbol

PPCC

7

0

6

0

5

0

4

0

3

0

2

0

1

0

PPCC1

PPCC0

PPCC1

PPCC0

PCC1

Selection of CPU clock (fCPU)

0

1

0

1

0

1

0

1

fX

1

fX/2 ^{Note 1}

fX/2²

0

Note 2

0

fX/2²

Note 1

1

fX/2³

Note 2

0

fX/2⁴

Other than above

Setting prohibited

Notes 1. If PPCC = 01H, the clock (f^XP) supplied to the peripheral hardware is fX/2.

2. If PPCC = 02H, the clock (f^XP) supplied to the peripheral hardware is fX/2².

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The fastest instruction of the 78K0S/KB1+ is executed in two CPU clocks. Therefore, the relationship between the

CPU clock (f^CPU) and the minimum instruction execution time is as shown in Table 5-2.

Table 5-2. Relationship Between CPU Clock and Minimum Instruction Execution Time

CPU Clock (fCPU) ^Note

Minimum Instruction Execution Time: 2/fCPU

High-speed internal oscillation clock

(at 8.0 MHz (TYP.))

Crystal/ceramic oscillation clock

or external clock input (at 10.0 MHz)

fX

0.25 μs

0.5 μs

1.0 μs

2.0 μs

4.0 μs

0.2 μs

fX/2

fX/2²

fX/2³

fX/2⁴

0.4 μs

0.8 μs

1.6 μs

3.2 μs

Note The CPU clock (high-speed internal oscillation clock, crystal/ceramic oscillation clock, or external clock

input) is selected by the option byte.

(2) Low-speed internal oscillation mode register (LSRCM)

This register is used to select the operation mode of the low-speed internal oscillator (240 kHz (TYP.)).

This register is valid when it is specified by the option byte that the low-speed internal oscillator can be stopped

by software. If it is specified by the option byte that the low-speed internal oscillator cannot be stopped by

software, setting of this register is invalid, and the low-speed internal oscillator continues oscillating. In addition,

the source clock of WDT is fixed to the low-speed internal oscillator. For details, refer to CHAPTER 9

WATCHDOG TIMER.

LSRCM can be set by using a 1-bit or 8-bit memory manipulation instruction.

Generation of reset signal sets LSRCM to 00H.

Figure 5-4. Format of Low-Speed Internal Oscillation Mode Register (LSRCM)

Address: FF58H After reset: 00H R/W

Symbol

LSRCM

7

0

6

0

5

0

4

0

3

0

2

0

1

0

<0>

LSRSTOP

Oscillation/stop of low-speed internal oscillator

0

1

Low-speed internal oscillates

Low-speed internal oscillator stops

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(3) Oscillation stabilization time select register (OSTS)

This register is used to select oscillation stabilization time of the clock supplied from the oscillator when the STOP

mode is released. The wait time set by OSTS is valid only when the crystal/ceramic oscillation clock is selected

as the system clock and after the STOP mode is released. If the high-speed internal oscillator or external clock

input is selected as the system clock source, no wait time elapses.

The system clock oscillator and the oscillation stabilization time that elapses after power application or release of

reset are selected by the option byte. For details, refer to CHAPTER 18 OPTION BYTE.

OSTS is set by using an 8-bit memory manipulation instruction.

Figure 5-5. Format of Oscillation Stabilization Time Select Register (OSTS)

Address: FFF4H After reset: Undefined R/W

Symbol

OSTS

7

0

6

0

5

0

4

0

3

0

2

0

1

0

OSTS1

OSTS0

OSTS1

OSTS0

Selection of oscillation stabilization time

0

1

0

1

0

1

2¹⁰/fX (102.4 μs)

2¹²/fX (409.6 μs)

2¹⁵/fX (3.27 ms)

2¹⁷/fX (13.1 ms)

Cautions 1. To set and then release the STOP mode, set the oscillation stabilization time as follows.

Expected oscillation stabilization time of resonator ≤ Oscillation stabilization time set by

OSTS

2. The wait time after the STOP mode is released does not include the time from the release of

the STOP mode to the start of clock oscillation (“a” in the figure below), regardless of

whether STOP mode was released by reset signal generation or interrupt generation.

STOP mode is released

Voltage

waveform

of X1 pin

a

3. The oscillation stabilization time that elapses on power application or after release of reset is

selected by the option byte. For details, refer to CHAPTER 18 OPTION BYTE.

Remarks 1. ( ): f^X= 10 MHz

2. Determine the oscillation stabilization time of the resonator by checking the characteristics of the

resonator to be used.

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5.4 System Clock Oscillators

The following three types of system clock oscillators are available.

• High-speed internal oscillator:

• Crystal/ceramic oscillator:

• External clock input circuit:

Internally oscillates a clock of 8 MHz (TYP.).

Oscillates a clock of 2 to 10 MHz.

Supplies a clock of 2 to 10 MHz to the X1 pin.

5.4.1 High-speed internal oscillator

The 78K0S/KB1+ includes a high-speed internal oscillator (8 MHz (TYP.)).

If the high-speed internal oscillation is selected by the option byte as the clock source, the X1 and X2 pins can be

used as I/O port pins.

For details of the option byte, refer to CHAPTER 18 OPTION BYTE. For details of I/O ports, refer to CHAPTER 4

PORT FUNCTIONS.

5.4.2 Crystal/ceramic oscillator

The crystal/ceramic oscillator oscillates using a crystal or ceramic resonator connected between the X1 and X2

pins.

If the crystal/ceramic oscillator is selected by the option byte as the system clock source, the X1 and X2 pins are

used as crystal or ceramic resonator connection pins.

For details of the option byte, refer to CHAPTER 18 OPTION BYTE. For details of I/O ports, refer to CHAPTER 4

PORT FUNCTIONS.

Figure 5-6 shows the external circuit of the crystal/ceramic oscillator.

Figure 5-6. External Circuit of Crystal/Ceramic Oscillator

V

SS

X1

X2

Crystal resonator

or ceramic resonator

Caution When using the crystal/ceramic oscillator, wire as follows in the area enclosed by the broken

lines in Figure 5-6 to avoid an adverse effect from wiring capacitance.

• Keep the wiring length as short as possible.

• Do not cross the wiring with the other signal lines. Do not route the wiring near a signal line

through which a high fluctuating current flows.

• Always make the ground point of the oscillator capacitor the same potential as V^SS. Do not

ground the capacitor to a ground pattern through which a high current flows.

• Do not fetch signals from the oscillator.

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Figure 5-7 shows examples of incorrect resonator connection.

Figure 5-7. Examples of Incorrect Resonator Connection (1/2)

(a) Too long wiring of connected circuit (b) Crossed signal lines

PORT

X2

VSS

X1

X2

VSS

X1

(d) Current flowing through ground line of oscillator

(Potential at points A, B, and C fluctuates.)

(c) Wiring near high fluctuating current

VDD

PORT

X2

VSS

X1

X2

X1

VSS

A

B

C

High current

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Figure 5-7. Examples of Incorrect Resonator Connection (2/2)

(e) Signals are fetched

VSS

X1

X2

5.4.3 External clock input circuit

This circuit supplies a clock from an external IC to the X1 pin.

If external clock input is selected by the option byte as the system clock source, the X2 pin can be used as an I/O

port pin.

For details of the option byte, refer to CHAPTER 18 OPTION BYTE. For details of I/O ports, refer to CHAPTER 4

PORT FUNCTIONS.

5.4.4 Prescaler

The prescaler divides the clock (f^X) output by the system clock oscillator to generate a clock (fXP) to be supplied to

the peripheral hardware. It also divides the clock to peripheral hardware (f^XP) to generate a clock to be supplied to the

CPU.

Remark The clock output by the oscillator selected by the option byte (high-speed internal oscillator,

crystal/ceramic oscillator, or external clock input circuit) is divided. For details of the option byte, refer to

CHAPTER 18 OPTION BYTE.

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5.5 Operation of CPU Clock Generator

A clock (fCPU) is supplied to the CPU from the system clock (fX) oscillated by one of the following three types of

oscillators.

• High-speed internal oscillator:

• Crystal/ceramic oscillator:

• External clock input circuit:

Internally oscillates a clock of 8 MHz (TYP.).

Oscillates a clock of 2 to 10 MHz.

Supplies a clock of 2 to 10 MHz to X1 pin.

The system clock oscillator is selected by the option byte. For details of the option byte, refer to CHAPTER 18

OPTION BYTE.

(1) High-speed internal oscillator

When the high-speed internal oscillation is selected by the option byte, the following is possible.

• Shortening of start time

If the high-speed internal oscillator is selected as the oscillator, the CPU can be started without having to wait

for the oscillation stabilization time of the system clock. Therefore, the start time can be shortened.

• Improvement of expandability

If the high-speed internal oscillator is selected as the oscillator, the X1 and X2 pins can be used as I/O port

pins. For details, refer to CHAPTER 4 PORT FUNCTIONS.

Figures 5-8 and 5-9 show the timing chart and status transition diagram of the default start by the high-speed

internal oscillation.

Remark When the high-speed internal oscillation is used, the clock accuracy is 5%.

Figure 5-8. Timing Chart of Default Start by High-Speed Internal Oscillation

(a)

VDD

RESET

H

Internal reset

(b)

System clock

CPU clock

High-speed internal oscillation clock

PCC = 02H, PPCC = 02H

Option byte is read.

System clock is selected.

(Operation stops^Note

)

Note Operation stop time is 277 μs (MIN.), 544 μs (TYP.), and 1.075 ms (MAX.).

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(a) The internal reset signal is generated by the power-on-clear function on power application, the option byte is

referenced after reset, and the system clock is selected.

(b) The option byte is referenced and the system clock is selected. Then the high-speed internal oscillation

clock operates as the system clock.

Figure 5-9. Status Transition of Default Start by High-Speed internal oscillation

Power

application

VDD > 2.1 V (TYP.)

Reset by

power-on-clear

Reset signal

High-speed internal

oscillator selected

by option byte

Start with PCC = 02H,

PPCC = 02H

Clock division ratio

variable during

CPU operation

Interrupt

HALT

instruction

STOP

instruction

HALT

STOP

Remark PCC: Processor clock control register

PPCC: Preprocessor clock control register

(2) Crystal/ceramic oscillator

If crystal/ceramic oscillation is selected by the option byte, a clock frequency of 2 to 10 MHz can be selected and

the accuracy of processing is improved because the frequency deviation is small, as compared with high-speed

internal oscillation (8 MHz (TYP.)).

Figures 5-10 and 5-11 show the timing chart and status transition diagram of default start by the crystal/ceramic

oscillator.

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Figure 5-10. Timing Chart of Default Start by Crystal/Ceramic Oscillator

(a)

VDD

RESET

H

Internal reset

(b)

System clock

CPU clock

(c)

Crystal/ceramic

oscillator clock

PCC = 02H, PPCC = 02H

Option byte is read.

Clock oscillation

stabilization

time^{Note 2}

System clock is selected.

(Operation stops^{Note 1}

)

Notes 1. Operation stop time is 276 μs (MIN.), 544 μs (TYP.), and 1.074 ms (MAX.).

2. The clock oscillation stabilization time for default start is selected by the option byte. For details, refer

to CHAPTER 18 OPTION BYTE. The oscillation stabilization time that elapses after the STOP mode

is released is selected by the oscillation stabilization time select register (OSTS).

(a) The internal reset signal is generated by the power-on-clear function on power application, the option byte is

referenced after reset, and the system clock is selected.

(b) After the high-speed internal oscillation clock is generated, the option byte is referenced and the system

clock is selected. In this case, the crystal/ceramic oscillator clock is selected as the system clock.

(c) If the system clock is the crystal/ceramic oscillator clock, it starts operating as the CPU clock after clock

oscillation is stabilized. The wait time is selected by the option byte. For details, refer to CHAPTER 18

OPTION BYTE.

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Figure 5-11. Status Transition of Default Start by Crystal/Ceramic Oscillation

Power

application

VDD > 2.1 V (TYP.)

Reset by

power-on-clear

Reset signal

Crystal/ceramic

oscillation selected

by option byte

Wait for clock

oscillation stabilization

Start with PCC = 02H,

PPCC = 02H

Clock division ratio

variable during

CPU operation

Interrupt

HALT

instruction

STOP

instruction

HALT

STOP

Remark PCC: Processor clock control register

PPCC: Preprocessor clock control register

(3) External clock input circuit

If external clock input is selected by the option byte, the following is possible.

• High-speed operation

The accuracy of processing is improved as compared with high-speed internal oscillation (8 MHz (TYP.))

because an oscillation frequency of 2 to 10 MHz can be selected and an external clock with a small frequency

deviation can be supplied.

• Improvement of expandability

If the external clock input circuit is selected as the oscillator, the X2 pin can be used as an I/O port pin. For

details, refer to CHAPTER 4 PORT FUNCTIONS.

Figures 5-12 and 5-13 show the timing chart and status transition diagram of default start by external clock input.

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Figure 5-12. Timing of Default Start by External Clock Input

(a)

VDD

RESET

H

Internal reset

(b)

System clock

CPU clock

External clock input

PCC = 02H, PPCC = 02H

Option byte is read.

System clock is selected.

(Operation stops^Note

)

Note Operation stop time is 277 μs (MIN.), 544 μs (TYP.), and 1.075 ms (MAX.).

(a) The internal reset signal is generated by the power-on-clear function on power application, the option byte is

referenced after reset, and the system clock is selected.

(b) The option byte is referenced and the system clock is selected. Then the external clock operates as the

system clock.

Figure 5-13. Status Transition of Default Start by External Clock Input

Power

application

VDD > 2.1 V (TYP.)

Reset by

power-on-clear

Reset signal

External clock input

selected by option byte

Start with PCC = 02H,

PPCC = 02H

Clock division ratio

variable during

CPU operation

Interrupt

HALT

instruction

STOP

instruction

HALT

STOP

Remark PCC: Processor clock control register

PPCC: Preprocessor clock control register

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5.6 Operation of Clock Generator Supplying Clock to Peripheral Hardware

The following two types of clocks are supplied to the peripheral hardware.

• Clock to peripheral hardware (f^XP)

• Low-speed internal oscillation clock (fRL)

(1) Clock to peripheral hardware

The clock to the peripheral hardware is supplied by dividing the system clock (f^X). The division ratio is selected

by the pre-processor clock control register (PPCC).

Three types of frequencies are selectable: “f^X”, “fX/2”, and “fX/2²”. Table 5-3 lists the clocks supplied to the

peripheral hardware.

Table 5-3. Clocks to Peripheral Hardware

PPCC1

PPCC0

Selection of clock to peripheral hardware (fXP)

0

1

0

1

0

1

fX

fX/2

fX/2²

Setting prohibited

(2) Low-speed internal oscillation clock

The low-speed internal oscillator of the clock oscillator for interval time generation is always started after release

of reset, and oscillates at 240 kHz (TYP.).

It can be specified by the option byte whether the low-speed internal oscillator can or cannot be stopped by

software. If it is specified that the low-speed internal oscillator can be stopped by software, oscillation can be

started or stopped by using the low-speed internal oscillation mode register (LSRCM). If it is specified that it

cannot be stopped by software, the clock source of WDT is fixed to the low-speed internal oscillation clock (f^RL).

The low-speed internal oscillator is independent of the CPU clock. If it is used as the source clock of WDT,

therefore, a hang-up can be detected even if the CPU clock is stopped. If the low-speed internal oscillator is used

as a count clock source of 8-bit timer H1, 8-bit timer H1 can operate even in the standby status.

Table 5-4 shows the operation status of the low-speed internal oscillator when it is selected as the source clock of

WDT and the count clock of 8-bit timer H1. Figure 5-14 shows the status transition of the low-speed internal

oscillator.

Table 5-4. Operation Status of Low-Speed Internal Oscillator

Option Byte Setting

CPU Status

WDT Status

Stopped

TMH1 Status

Stopped

Can be stopped by

LSRSTOP = 1

LSRSTOP = 0

LSRSTOP = 1

LSRSTOP = 0

Operation mode

software

Operates

Stopped

Operates

Stopped

Operates

Standby

Cannot be stopped

Operation mode

Standby

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Figure 5-14. Status Transition of Low-Speed Internal Oscillation

Power

application

VDD > 2.1 V (TYP.)

Reset by

power-on-clear

Reset signal

Select by option byte

if low-speed internal oscillator

can be stopped or not

Can be stopped

Cannot be stopped

Clock source of

WDT is selected

by software^Note

Clock source of

WDT is fixed to f^RL

Low-speed internal

oscillator cannot be stopped

Low-speed internal

oscillator can be stopped

LSRSTOP = 1

LSRSTOP = 0

Low-speed internal

oscillator stops

Note The clock source of the watchdog timer (WDT) is selected from f^Xor fRL, or it may be stopped. For details,

refer to CHAPTER 9 WATCHDOG TIMER.

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CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00

6.1 Functions of 16-bit Timer/Event Counter 00

16-bit timer/event counter 00 has the following functions.

(1) Interval timer

16-bit timer/event counter 00 generates interrupt requests at the preset time interval.

• Number of counts: 2 to 65536

(2) External event counter

16-bit timer/event counter 00 can measure the number of pulses with a high-/low-level width of valid level

pulse width or more of a signal input externally.

• Valid level pulse width: 2/f^XPor more

(3) Pulse width measurement

16-bit timer/event counter 00 can measure the pulse width of an externally input signal.

• Valid level pulse width: 2/f^XPor more

(4) Square-wave output

16-bit timer/event counter 00 can output a square wave with any selected frequency.

• Cycle: (2 to 65536) × 2 × count clock cycle

(5) PPG output

16-bit timer/event counter 00 can output a square wave that have arbitrary cycle and pulse width.

• 1 < Pulse width < Cycle ≤ 65536

(6) One-shot pulse output

16-bit timer/event counter 00 can output a one-shot pulse for which output pulse width can be set to any

desired value.

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6.2 Configuration of 16-bit Timer/Event Counter 00

16-bit timer/event counter 00 consists of the following hardware.

Table 6-1. Configuration of 16-bit Timer/Event Counter 00

Item

Timer counter

Register

Configuration

16-bit timer counter 00 (TM00)

16-bit timer capture/compare registers 000, 010 (CR000, CR010)

Timer input

Timer output

Control registers

TI000, TI010

TO00, output controller

16-bit timer mode control register 00 (TMC00)

Capture/compare control register 00 (CRC00)

16-bit timer output control register 00 (TOC00)

Prescaler mode register 00 (PRM00)

Port mode register 3 (PM3)

Port register 3 (P3)

Figure 6-1 shows a block diagram of these counters.

Figure 6-1. Block Diagram of 16-bit Timer/Event Counter 00

Internal bus

Capture/compare control

register 00 (CRC00)

CRC002CRC001 CRC000

CR010

INTTM000

16-bit timer capture/compare

register 000 (CR000)

Noise

elimi-

nator

TI010/TO00/

INTP2/P31

Match

f

XP

f

XP/2²

XP/2⁸

16-bit timer counter 00

(TM00)

Clear

Output

TO00/TI010/

INTP2/P31

controller

Match

Noise

elimi-

nator

2

fX

Output latch

(P31)

PM31

Noise

elimi-

nator

16-bit timer capture/compare

register 010 (CR010)

TI000/INTP0/P30

INTTM010

CRC002

PRM001

TMC003 TMC002 TMC001OVF00 OSPT00 OSPE00 TOC004 LVS00 LVR00 TOC001 TOE00

PRM000

16-bit timer output

control register 00

(TOC00)

16-bit timer mode

control register 00

(TMC00)

Prescaler mode

register 00 (PRM00)

Internal bus

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(1) 16-bit timer counter 00 (TM00)

TM00 is a 16-bit read-only register that counts count pulses.

The counter is incremented in synchronization with the rising edge of the count clock. If the count value is read

during operation, input of the count clock is temporarily stopped, and the count value at that point is read.

Figure 6-2. Format of 16-bit Timer Counter 00 (TM00)

Address: FF12H, FF13H After reset: 0000H

R

Symbol

FF13H

FF12H

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

TM00

The count value is reset to 0000H in the following cases.

<1> At reset signal generation

<2> If TMC003 and TMC002 are cleared

<3> If the valid edge of TI000 is input in the clear & start mode entered by inputting the valid edge of TI000

<4> If TM00 and CR000 match in the clear & start mode entered on a match between TM00 and CR000

<5> If OSPT00 is set to 1 in the one-shot pulse output mode

Cautions 1. Even if TM00 is read, the value is not captured by CR010.

2. When TM00 is read, count misses do not occur, since the input of the count clock is

temporarily stopped and then resumed after the read.

(2) 16-bit timer capture/compare register 000 (CR000)

CR000 is a 16-bit register which has the functions of both a capture register and a compare register. Whether

it is used as a capture register or as a compare register is set by bit 0 (CRC000) of capture/compare control

register 00 (CRC00).

CR000 is set by 16-bit memory manipulation instruction.

Reset signal generation clears this register to 0000H.

Figure 6-3. Format of 16-bit Timer Capture/Compare Register 000 (CR000)

Address: FF14H, FF15H After reset: 0000H R/W

Symbol

FF15H

FF14H

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

CR000

•

When CR000 is used as a compare register

The value set in CR000 is constantly compared with the 16-bit timer/counter 00 (TM00) count value, and an

interrupt request (INTTM000) is generated if they match. It can also be used as the register that holds the

interval time then TM00 is set to interval timer operation.

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•

When CR000 is used as a capture register

It is possible to select the valid edge of the TI000 pin or the TI010 pin as the capture trigger. Setting of the

TI000 or TI010 valid edge is performed by means of prescaler mode register 00 (PRM00) (refer to Table 6-

2).

Table 6-2. CR000 Capture Trigger and Valid Edges of TI000 and TI010 Pins

(1) TI000 pin valid edge selected as capture trigger (CRC001 = 1, CRC000 = 1)

CR000 Capture Trigger

TI000 Pin Valid Edge

ES010

ES000

Falling edge

Rising edge

Falling edge

0

1

0

1

Rising edge

No capture operation

Both rising and falling edges

(2) TI010 pin valid edge selected as capture trigger (CRC001 = 0, CRC000 = 1)

CR000 Capture Trigger

TI010 Pin Valid Edge

ES110

ES100

Falling edge

Rising edge

0

1

0

1

Rising edge

Both rising and falling edges

Remarks 1. Setting ES010, ES000 = 1, 0 and ES110, ES100 = 1, 0 is prohibited.

2. ES010, ES000:

Bits 5 and 4 of prescaler mode register 00 (PRM00)

Bits 7 and 6 of prescaler mode register 00 (PRM00)

ES110, ES100:

CRC001, CRC000: Bits 1 and 0 of capture/compare control register 00 (CRC00)

Cautions 1. Set CR000 to other than 0000H in the clear & start mode entered on match between TM00

and CR000. This means a 1-pulse count operation cannot be performed when this

register is used as an external event counter. However, in the free-running mode and in

the clear & start mode using the valid edge of TI000 pin, if CR000 is set to 0000H, an

interrupt request (INTTM000) is generated when CR000 changes from 0000H to 0001H

following overflow (FFFFH).

2. If the new value of CR000 is less than the value of 16-bit timer counter 0 (TM00), TM00

continues counting, overflows, and then starts counting from 0 again. If the new value of

CR000 is less than the old value, therefore, the timer must be reset to be restarted after

the value of CR000 is changed.

3. The value of CR000 after 16-bit timer/event counter 00 has stopped is not guaranteed.

4. The capture operation may not be performed for CR000 set in compare mode even if a

capture trigger is input.

5. When using P31 as the input pin (TI010) of the valid edge, it cannot be used as a timer

output pin (TO00). When using P31 as the timer output pin (TO00), it cannot be used as

the input pin (TI010) of the valid edge.

6. If the register read period and the input of the capture trigger conflict when CR000 is

used as a capture register, the capture trigger input takes precedence and the read data

is undefined. Also, if the count stop of the timer and the input of the capture trigger

conflict, the capture trigger is undefined.

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Caution 7. Changing the CR000 setting during TM00 operation may cause a malfunction. To change

the setting, refer to 6.5 Cautions Related to 16-bit Timer/Event Counter 00 (17) Changing

compare register during timer operation.

(3) 16-bit timer capture/compare register 010 (CR010)

CR010 is a 16-bit register which has the functions of both a capture register and a compare register. Whether

it is used as a capture register or a compare register is set by bit 2 (CRC002) of capture/compare control

register 00 (CRC00).

CR010 is set by 16-bit memory manipulation instruction.

Reset signal generation clears CR010 to 0000H.

Figure 6-4. Format of 16-bit Timer Capture/Compare Register 010 (CR010)

Address: FF16H, FF17H After reset: 0000H R/W

Symbol

FF17H

FF16H

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

CR010

•

When CR010 is used as a compare register

The value set in CR010 is constantly compared with the 16-bit timer counter 00 (TM00) count value, and an

interrupt request (INTTM010) is generated if they match.

When CR010 is used as a capture register

It is possible to select the valid edge of the TI000 pin as the capture trigger. The TI000 valid edge is set by

means of prescaler mode register 00 (PRM00) (refer to Table 6-3).

Table 6-3. CR010 Capture Trigger and Valid Edge of TI000 Pin (CRC002 = 1)

CR010 Capture Trigger

TI000 Pin Valid Edge

ES010

ES000

Falling edge

Rising edge

0

1

0

1

Rising edge

Both rising and falling edges

Remarks 1. Setting ES010, ES000 = 1, 0 is prohibited.

2. ES010, ES000: Bits 5 and 4 of prescaler mode register 00 (PRM00)

CRC002: Bit 2 of capture/compare control register 00 (CRC00)

Cautions 1. In the free-running mode and in the clear & start mode using the valid edge of the TI000

pin, if CR010 is set to 0000H, an interrupt request (INTTM010) is generated when CR010

changes from 0000H to 0001H following overflow (FFFFH).

2. If the new value of CR010 is less than the value of 16-bit timer counter 0 (TM00), TM00

continues counting, overflows, and then starts counting from 0 again. If the new value of

CR010 is less than the old value, therefore, the timer must be reset to be restarted after

the value of CR010 is changed.

3. The value of CR010 after 16-bit timer/event counter 00 has stopped is not guaranteed.

4. The capture operation may not be performed for CR010 set in compare mode even if a

capture trigger is input.

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Cautions 5. If the register read period and the input of the capture trigger conflict when CR010 is

used as a capture register, the capture trigger input takes precedence and the read data

is undefined. Also, if the timer count stop and the input of the capture trigger conflict,

the capture data is undefined.

6. Changing the CR010 setting during TM00 operation may cause a malfunction. To change

the setting, refer to 6.5 Cautions Related to 16-bit Timer/Event Counter 00 (17) Changing

compare register during timer operation.

6.3 Registers to Control 16-bit Timer/Event Counter 00

The following six types of registers are used to control 16-bit timer/event counter 00.

• 16-bit timer mode control register 00 (TMC00)

• Capture/compare control register 00 (CRC00)

• 16-bit timer output control register 00 (TOC00)

• Prescaler mode register 00 (PRM00)

• Port mode register 3 (PM3)

• Port register 3 (P3)

(1) 16-bit timer mode control register 00 (TMC00)

This register sets the 16-bit timer operating mode, the 16-bit timer counter 00 (TM00) clear mode, and output

timing, and detects an overflow.

TMC00 is set by a 1-bit or 8-bit memory manipulation instruction.

Generation of reset signal sets the value of TMC00 to 00H.

Caution 16-bit timer counter 00 (TM00) starts operation at the moment TMC002 and TMC003

(operation stop mode) are set to a value other than 0, 0, respectively. Set TMC002 and

TMC003 to 0, 0 to stop the operation.

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Figure 6-5. Format of 16-bit Timer Mode Control Register 00 (TMC00)

Address: FF60H After reset: 00H R/W

Symbol

TMC00

7

0

6

0

5

0

4

0

3

2

1

<0>

TMC003TMC002TMC001 OVF00

TMC003 TMC002 TMC001

Operating mode and clear

mode selection

TO00 inversion timing selection

No change

Interrupt request generation

Not generated

0

1

0

1

0

Operation stop

(TM00 cleared to 0)

Free-running mode

Match between TM00 and

CR000 or match between

TM00 and CR010

<When operating as compare

register>

Generated on match between

TM00 and CR000, or match

between TM00 and CR010

<When operating as capture

register>

0

1

Match between TM00 and

CR000, match between TM00

and CR010 or TI000 pin valid

edge

Generated on TI000 pin and

TI010 pin valid edge

1

0

1

0

1

0

Clear & start occurs on valid

edge of TI000 pin

−

Clear & start occurs on match

between TM00 and CR000

Match between TM00 and

CR000 or match between

TM00 and CR010

1

Match between TM00 and

CR000, match between TM00

and CR010 or TI000 pin valid

edge

OVF00

Overflow detection of 16-bit timer counter 00 (TM00)

0

1

Overflow not detected

Overflow detected

Cautions 1. The timer operation must be stopped before writing to bits other than the OVF00 flag.

2. If the timer is stopped, timer counts and timer interrupts do not occur, even if a signal is

input to the TI000/TI010 pins.

3. Except when the valid edge of the TI000 pin is selected as the count clock, stop the timer

operation before setting STOP mode or system clock stop mode; otherwise the timer may

malfunction when the system clock starts.

4. Set the valid edge of the TI000 pin with bits 4 and 5 of prescaler mode register 00 (PRM00)

after stopping the timer operation.

5. If the clear & start mode entered on a match between TM00 and CR000, clear & start mode at

the valid edge of the TI000 pin, or free-running mode is selected, when the set value of CR000

is FFFFH and the TM00 value changes from FFFFH to 0000H, the OVF00 flag is set to 1.

6. Even if the OVF00 flag is cleared before the next count clock is counted (before TM00

becomes 0001H) after the occurrence of a TM00 overflow, the OVF00 flag is re-set newly and

clear is disabled.

7. The capture operation is performed at the fall of the count clock. An interrupt request input

(INTTM0n0), however, occurs at the rise of the next count clock.

Remark TM00: 16-bit timer counter 00

CR000: 16-bit timer capture/compare register 000

CR010: 16-bit timer capture/compare register 010

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(2) Capture/compare control register 00 (CRC00)

This register controls the operation of the 16-bit capture/compare registers (CR000, CR010).

CRC00 is set by a 1-bit or 8-bit memory manipulation instruction.

Generation of reset signal sets the value of CRC00 to 00H.

Figure 6-6. Format of Capture/Compare Control Register 00 (CRC00)

Address: FF62H After reset: 00H R/W

Symbol

CRC00

7

0

6

0

5

0

4

0

3

0

2

1

0

CRC002

CRC001

CRC000

CRC002

CR010 operating mode selection

0

1

Operate as compare register

Operate as capture register

CRC001

CR000 capture trigger selection

0

1

Capture on valid edge of TI010 pin

Capture on valid edge of TI000 pin by reverse phase^Note

CRC000

CR000 operating mode selection

0

1

Operate as compare register

Operate as capture register

Note When the CRC001 bit value is 1, capture is not performed if both the rising and falling edges have been

selected as the valid edges of the TI000 pin.

Cautions 1. The timer operation must be stopped before setting CRC00.

2. When the clear & start mode entered on a match between TM00 and CR000 is selected by

16-bit timer mode control register 00 (TMC00), CR000 should not be specified as a

capture register.

3. To ensure the reliability of the capture operation, the capture trigger requires a pulse

longer than two cycles of the count clock selected by prescaler mode register 00

(PRM00) (refer to Figure 6-17).

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(3) 16-bit timer output control register 00 (TOC00)

This register controls the operation of the 16-bit timer/event counter output controller. It sets timer output F/F

set/reset, output inversion enable/disable, 16-bit timer/event counter 00 timer output enable/disable, one-shot

pulse output operation enable/disable, and output trigger of one-shot pulse by software.

TOC00 is set by a 1-bit or 8-bit memory manipulation instruction.

Generation of reset signal sets the value of TOC00 to 00H.

Figure 6-7. Format of 16-bit Timer Output Control Register 00 (TOC00)

Address: FF63H After reset: 00H R/W

Symbol

TOC00

7

0

<6>

<5>

4

<3>

<2>

1

<0>

OSPT00

OSPE00

TOC004

LVS00

LVR00

TOC001

TOE00

OSPT00

One-shot pulse output trigger control via software

0

1

No one-shot pulse output trigger

One-shot pulse output trigger

OSPE00

One-shot pulse output operation control

0

1

Successive pulse output mode

One-shot pulse output mode^Note

TOC004

Timer output F/F control using match of CR010 and TM00

0

1

Disables inversion operation

Enables inversion operation

LVS00

LVR00

Timer output F/F status setting

0

1

0

1

0

1

No change

Timer output F/F reset (0)

Timer output F/F set (1)

Setting prohibited

TOC001

Timer output F/F control using match of CR000 and TM00

0

1

Disables inversion operation

Enables inversion operation

TOE00

Timer output control

0

1

Disables output (output fixed to level 0)

Enables output

Note The one-shot pulse output mode operates correctly only in the free-running mode and the mode in which

clear & start occurs at the TI000 pin valid edge. In the mode in which clear & start occurs on a match

between TM00 and CR000, one-shot pulse output is not possible because an overflow does not occur.

Cautions 1. The timer operation must be stopped before setting other than OSPT00.

2. If LVS00 and LVR00 are read, 0 is read.

3. OSPT00 is automatically cleared after data is set, so 0 is read.

4. Do not set OSPT00 to 1 other than in one-shot pulse output mode.

5. A write interval of two cycles or more of the count clock selected by prescaler mode register

00 (PRM00) is required, when OSPT00 is set to 1 successively.

6. When TOE00 is 0, set TOE00, LVS00, and LVR00 at the same time with the 8-bit memory

manipulation instruction. When TOE00 is 1, LVS00 and LVR00 can be set with the 1-bit

memory manipulation instruction.

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(4) Prescaler mode register 00 (PRM00)

This register is used to set the 16-bit timer counter 00 (TM00) count clock and the TI000, TI010 pin input valid

edges.

PRM00 is set by a 1-bit or 8-bit memory manipulation instruction.

Generation of reset signal sets the value of PRM00 to 00H.

Figure 6-8. Format of Prescaler Mode Register 00 (PRM00)

Address: FF61H After reset: 00H R/W

Symbol

PRM00

7

6

5

4

3

0

2

0

1

0

ES110

ES100

ES010

ES000

PRM001

PRM000

ES110

ES100

TI010 pin valid edge selection

0

1

0

1

0

1

Falling edge

Rising edge

Setting prohibited

Both falling and rising edges

ES010

ES000

TI000 pin valid edge selection

0

1

0

1

0

1

Falling edge

Rising edge

Setting prohibited

Both falling and rising edges

PRM001

PRM000

Count clock selection

0

1

0

1

0

1

fXP (10 MHz)

fXP/2²(2.5 MHz)

fXP/2⁸(39.06 kHz)

TI000 pin valid edge^Note

Remarks 1. f^XP: Oscillation frequency of clock supplied to peripheral hardware

2. ( ): fXP = 10 MHz

Note The external clock requires a pulse longer than two cycles of the internal count clock (f^XP).

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Cautions 1. Always set data to PRM00 after stopping the timer operation.

2. If the valid edge of the TI000 pin is to be set as the count clock, do not set the clear/start

mode and the capture trigger at the valid edge of the TI000 pin.

3. In the following cases, note with caution that the valid edge of the TI0n0 pin is detected.

<1> Immediately after a system reset, if a high level is input to the TI0n0 pin, the

operation of the 16-bit timer counter 00 (TM00) is enabled

→ If the rising edge or both rising and falling edges are specified as the valid edge

of the TI0n0 pin, a rising edge is detected immediately after the TM00 operation is

enabled.

<2> If the TM00 operation is stopped while the TI0n0 pin is high level, TM00 operation is

then enabled after a low level is input to the TI0n0 pin

→ If the falling edge or both rising and falling edges are specified as the valid edge

of the TI0n0 pin, a falling edge is detected immediately after the TM00 operation is

enabled.

<3> If the TM00 operation is stopped while the TI0n0 pin is low level, TM00 operation is

then enabled after a high level is input to the TI0n0 pin

→ If the rising edge or both rising and falling edges are specified as the valid edge

of the TI0n0 pin, a rising edge is detected immediately after the TM00 operation is

enabled.

4. The sampling clock used to eliminate noise differs when a TI000 valid edge is used as the

count clock and when it is used as a capture trigger. In the former case, the count clock

is f^XP, and in the latter case the count clock is selected by prescaler mode register 00

(PRM00). The capture operation is not performed until the valid edge is sampled and the

valid level is detected twice, thus eliminating noise with a short pulse width.

5. When using P31 as the input pin (TI010) of the valid edge, it cannot be used as a timer

output pin (TO00). When using P31 as the timer output pin (TO00), it cannot be used as

the input pin (TI010) of the valid edge.

Remark n = 0, 1

(5) Port mode register 3 (PM3)

This register sets port 3 input/output in 1-bit units.

When using the P31/TO00/TI010/INTP2 pin for timer output, set PM31 and the output latch of P31 to 0.

When using the P30/TI000/INTP0 and P31/TO00/TI010/INTP2 pins as a timer input, set PM30 and PM31 to 1.

At this time, the output latches of P30 and P31 can be either 0 or 1.

PM3 is set by a 1-bit or 8-bit memory manipulation instruction.

Generation of reset signal sets the value of PM3 to FFH.

Figure 6-9. Format of Port Mode Register 3 (PM3)

Address: FF23H After reset: FFH R/W

Symbol

PM3

7

1

6

1

5

1

4

1

3

2

1

0

PM33 PM32 PM31 PM30

PM3n P3n pin I/O mode selection (n = 0 to 3)

0

1

Output mode (output buffer on)

Input mode (output buffer off)

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6.4 Operation of 16-bit Timer/Event Counter 00

6.4.1 Interval timer operation

Setting 16-bit timer mode control register 00 (TMC00) and capture/compare control register 00 (CRC00) as shown

in Figure 6-10 allows operation as an interval timer.

Setting

The basic operation setting procedure is as follows.

<1> Set the CRC00 register (see Figure 6-10 for the set value).

<2> Set any value to the CR000 register.

<3> Set the count clock by using the PRM00 register.

<4> Set the TMC00 register to start the operation (see Figure 6-10 for the set value).

Caution Changing the CR000 setting during TM00 operation may cause a malfunction. To change the

setting, refer to 6.5 Cautions Related to 16-bit Timer/Event Counter 00 (17) Changing compare

register during timer operation.

Remark For how to enable the INTTM000 interrupt, see CHAPTER 13 INTERRUPT FUNCTIONS.

Interrupt requests are generated repeatedly using the count value set in 16-bit timer capture/compare register 000

(CR000) beforehand as the interval.

When the count value of 16-bit timer counter 00 (TM00) matches the value set to CR000, counting continues with

the TM00 value cleared to 0 and the interrupt request signal (INTTM000) is generated.

The count clock of the 16-bit timer/event counter can be selected using bits 0 and 1 (PRM000, PRM001) of

prescaler mode register 00 (PRM00).

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Figure 6-10. Control Register Settings for Interval Timer Operation

(a) Capture/compare control register 00 (CRC00)

7

0

6

0

5

0

4

0

3

0

CRC002 CRC001 CRC000

CRC00

0/1

0

CR000 used as compare register

(b) Prescaler mode register 00 (PRM00)

ES110 ES100 ES010 ES000

3

0

2

0

PRM001 PRM000

PRM00 0/1

0/1

Selects count clock.

Setting invalid (setting “10” is prohibited.)

(c) 16-bit timer mode control register 00 (TMC00)

7

6

0

5

0

4

0

TMC003 TMC002 TMC001 OVF00

TMC00

0

1

0/1

0

Clears and starts on match between TM00 and CR000.

Remark 0/1: Setting 0 or 1 allows another function to be used simultaneously with the interval timer. See the

description of the respective control registers for details.

Figure 6-11. Interval Timer Configuration Diagram

16-bit timer capture/compare

register 000 (CR000)

INTTM000

f

XP

f

XP/2²

XP/2⁸

Note

16-bit timer counter 00

(TM00)

OVF00

Noise

eliminator

TI000/INTP0/P30

Clear

circuit

fXP

Note OVF00 is set to 1 only when 16-bit timer capture/compare register 000 (CR000) is set to FFFFH.

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Figure 6-12. Timing of Interval Timer Operation

t

Count clock

TM00 count value

0000H

0001H

N

0000H 0001H

N

0000H 0001H

N

Timer operation enabled

N

Clear

N

CR000

INTTM000

Interrupt request generated

Remark Interval time = (N + 1) × t

N = 0001H to FFFFH (settable range)

When the compare register is changed during timer count operation, if the value after 16-bit timer capture/compare

register 000 (CR000) is changed is smaller than that of 16-bit timer counter 00 (TM00), TM00 continues counting,

overflows and then restarts counting from 0. Thus, if the value (M) after the CR000 change is smaller than that (N)

before the change, it is necessary to restart the timer after changing CR000.

Figure 6-13. Timing After Change of Compare Register During Timer Count Operation (N → M: N > M)

Count clock

N

M

CR000

X – 1

X

FFFFH

0000H

0001H

0002H

TM00 count value

Remark N > X > M

6.4.2 External event counter operation

Setting

The basic operation setting procedure is as follows.

<1> Set the CRC00 register (see Figure 6-14 for the set value).

<2> Set the count clock by using the PRM00 register.

<3> Set any value to the CR000 register (0000H cannot be set).

<4> Set the TMC00 register to start the operation (see Figure 6-14 for the set value).

Remarks 1. For the setting of the TI000 pin, see 6.3 (5) Port mode register 3 (PM3).

2. For how to enable the INTTM000 interrupt, see CHAPTER 13 INTERRUPT FUNCTIONS.

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The external event counter counts the number of external clock pulses to be input to the TI000 pin with using 16-bit

timer counter 00 (TM00).

TM00 is incremented each time the valid edge specified by prescaler mode register 00 (PRM00) is input.

When the TM00 count value matches the 16-bit timer capture/compare register 000 (CR000) value, TM00 is

cleared to 0 and the interrupt request signal (INTTM000) is generated.

Input a value other than 0000H to CR000. (A count operation with a pulse cannot be carried out.)

The rising edge, the falling edge, or both edges can be selected using bits 4 and 5 (ES000 and ES010) of

prescaler mode register 00 (PRM00).

Because an operation is carried out only when the valid edge of the TI000 pin is detected twice after sampling with

the internal clock (f^XP), noise with a short pulse width can be removed.

Figure 6-14. Control Register Settings in External Event Counter Mode (with Rising Edge Specified)

(a) Capture/compare control register 00 (CRC00)

7

0

6

0

5

0

4

0

3

0

CRC002 CRC001 CRC000

CRC00

0/1

0

CR000 used as compare register

(b) Prescaler mode register 00 (PRM00)

ES110 ES100 ES010 ES000

3

0

2

0

PRM001 PRM000

PRM00 0/1

0/1

0

1

Selects external clock.

Specifies rising edge for pulse width detection.

Setting invalid (setting “10” is prohibited.)

(c) 16-bit timer mode control register 00 (TMC00)

7

6

0

5

0

4

0

TMC003 TMC002 TMC001 OVF00

TMC00

0

1

0/1

0

Clears and starts on match between TM00 and CR000.

Remark 0/1: Setting 0 or 1 allows another function to be used simultaneously with the external event counter.

See the description of the respective control registers for details.

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Figure 6-15. External Event Counter Configuration Diagram

Internal bus

16-bit timer capture/compare

register 000 (CR000)

Match

Clear

INTTM000

OVF00^Note

f

XP

16-bit timer counter 00 (TM00)

Noise eliminator

Valid edge of TI000

Note OVF00 is 1 only when 16-bit timer capture/compare register 000 (CR000) is set to FFFFH.

Figure 6-16. External Event Counter Operation Timing (with Rising Edge Specified)

(1) INTTM000 generation timing immediately after operation starts

Counting is started after a valid edge is detected twice.

Timer operation starts

Count starts

TI000 pin input

2

3

1

TM00 count value

CR000

0000H 0001H 0002H 0003H

N

N-2

N-1

N

0000H 0001H 0002H

INTTM000

(2) INTTM000 generation timing after INTTM000 has been generated twice

TI000 pin input

TM00 count value

CR000

N

0000H 0001H 0002H 0003H 0004H

N

N-1

N

0000H 0001H 0002H 0003H

INTTM000

Caution When reading the external event counter count value, TM00 should be read.

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6.4.3 Pulse width measurement operations

It is possible to measure the pulse width of the signals input to the TI000 pin and TI010 pin using 16-bit timer

counter 00 (TM00).

There are two measurement methods: measuring with TM00 used in free-running mode, and measuring by

restarting the timer in synchronization with the edge of the signal input to the TI000 pin.

When an interrupt occurs, read the valid value of the capture register, check the overflow flag, and then calculate

the necessary pulse width. Clear the overflow flag after checking it.

The capture operation is not performed until the signal pulse width is sampled in the count clock cycle selected by

prescaler mode register 00 (PRM00) and the valid level of the TI000 or TI010 pin is detected twice, thus eliminating

noise with a short pulse width.

Figure 6-17. CR010 Capture Operation with Rising Edge Specified

Count clock

TM00

N − 3

N − 2

N − 1

N

N + 1

TI000

Rising edge detection

N

CR010

INTTM010

Setting

The basic operation setting procedure is as follows.

<1> Set the CRC00 register (see Figures 6-18, 6-21, 6-23, and 6-25 for the set value).

<2> Set the count clock by using the PRM00 register.

<3> Set the TMC00 register to start the operation (see Figures 6-18, 6-21, 6-23, and 6-25 for the set value).

Caution To use two capture registers, set the TI000 and TI010 pins.

Remarks 1. For the setting of the TI000 (or TI010) pin, see 6.3 (5) Port mode register 3 (PM3).

2. For how to enable the INTTM000 (or INTTM010) interrupt, see CHAPTER 13 INTERRUPT

FUNCTIONS.

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(1) Pulse width measurement with free-running counter and one capture register

Specify both the rising and falling edges as the valid edges of the TI000 pin, by using bits 4 and 5 (ES000 and

ES010) of PRM00.

When 16-bit timer counter 00 (TM00) is operated in free-running mode, and the valid edge specified by

PRM00 is input, the value of TM00 is taken into 16-bit timer capture/compare register 010 (CR010) and an

external interrupt request signal (INTTM010) is set.

Sampling is performed using the count clock selected by PRM00, and a capture operation is only performed

when a valid level of the TI000 pin is detected twice, thus eliminating noise with a short pulse width.

Caution The measurable pulse width in this operation example is up to 1 cycle of the timer counter.

Figure 6-18. Control Register Settings for Pulse Width Measurement with Free-Running Counter

and One Capture Register (When TI000 and CR010 Are Used)

(a) Capture/compare control register 00 (CRC00)

7

0

6

0

5

0

4

0

3

0

CRC002 CRC001 CRC000

CRC00

1

0/1

0

CR000 used as compare register

CR010 used as capture register

(b) Prescaler mode register 00 (PRM00)

ES101 ES100 ES010 ES000

PRM00 0/1 0/1

3

0

2

0

PRM001 PRM000

1

0/1

Selects count clock (setting “11” is prohibited).

Specifies both edges for pulse width detection.

Setting invalid (setting “10” is prohibited.)

(c) 16-bit timer mode control register 00 (TMC00)

7

0

6

0

5

0

4

0

TMC003 TMC002 TMC001 OVF00

TMC00

0

1

0/1

0

Free-running mode

Remark 0/1: Setting 0 or 1 allows another function to be used simultaneously with pulse width measurement.

See the description of the respective control registers for details.

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Figure 6-19. Configuration Diagram for Pulse Width Measurement by Free-Running Counter

f

XP

XP/2²

XP/2⁶

16-bit timer/counter 00

(TM00)

f

16-bit timer capture/compare

register 010 (CR010)

TI000/INTP0/P30

INTTM010

Internal bus

Figure 6-20. Timing of Pulse Width Measurement Operation by Free-Running Counter

and One Capture Register (with Both Edges Specified)

t

Count clock

0000H 0001H

D0 D0 + 1

D1 D1 + 1

FFFFH 0000H

D2

D3

TM00 count value

TI000 pin input

CR010 capture value

INTTM010

D0

D1

D2

D3

(D1 − D0) × t

(D2 − D1) × t^Note

(D3 − D2) × t

Note The carry flag is set to 1. Ignore this setting.

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(2) Measurement of two pulse widths with free-running counter

When 16-bit timer counter 00 (TM00) is operated in free-running mode, it is possible to simultaneously

measure the pulse widths of the two signals input to the TI000 pin and the TI010 pin.

Specify both the rising and falling edges as the valid edges of the TI000 and TI010 pins, by using bits 4 and 5

(ES000 and ES010) and bits 6 and 7 (ES100 and ES110) of PRM00.

When the valid edge specified by bits 4 and 5 (ES000 and ES010) of PRM00 is input to the TI000 pin, the

value of TM00 is taken into 16-bit timer capture/compare register 000 (CR010) and an interrupt request signal

(INTTM010) is set.

Also, when the valid edge specified by bits 6 and 7 (ES100 and ES110) of PRM00 is input to the TI010 pin, the

value of TM00 is taken into 16-bit timer capture/compare register 000 (CR000) and an interrupt request signal

(INTTM000) is set.

Sampling is performed using the count clock cycle selected by prescaler mode register 00 (PRM00), and a

capture operation is only performed when a valid level of the TI000 or TI010 pin is detected twice, thus

eliminating noise with a short pulse width.

Caution The measurable pulse width in this operation example is up to 1 cycle of the timer counter.

Figure 6-21. Control Register Settings for Measurement of Two Pulse Widths with Free-Running Counter

(a) Capture/compare control register 00 (CRC00)

7

0

6

0

5

0

4

0

3

0

CRC002 CRC001 CRC000

CRC00

1

0

1

CR000 used as capture register

Captures valid edge of TI010 pin to CR000.

CR010 used as capture register

(b) Prescaler mode register 00 (PRM00)

ES110 ES100 ES010 ES000

3

0

2

0

PRM001 PRM000

PRM00

1

0/1

Selects count clock (setting “11” is prohibited).

Specifies both edges for pulse width detection.

(c) 16-bit timer mode control register 00 (TMC00)

7

0

6

0

5

0

4

0

TMC003 TMC002 TMC001 OVF00

TMC00

0

1

0/1

0

Free-running mode

Remark 0/1: Setting 0 or 1 allows another function to be used simultaneously with pulse width measurement.

See the description of the respective control registers for details.

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Figure 6-22. Timing of Pulse Width Measurement Operation with Free-Running Counter

(with Both Edges Specified)

t

Count clock

0000H 0001H

D0 D0 + 1

D1 D1 + 1

FFFFH 0000H

D2 D2 + 1 D2 + 2

D3

TM00 count value

TI000 pin input

CR010 capture value

INTTM010

D0

D1

D2

TI010 pin input

CR000 capture value

INTTM000

D1

D2 + 1

(D1 − D0) × t

(D2 − D1) × t^Note

(D3 − D2) × t

((D2 + 1) − D1) × t^Note

Note The carry flag is set to 1. Ignore this setting.

(3) Pulse width measurement with free-running counter and two capture registers

When 16-bit timer counter 00 (TM00) is operated in free-running mode, it is possible to measure the pulse

width of the signal input to the TI000 pin.

When the rising or falling edge specified by bits 4 and 5 (ES000 and ES010) of prescaler mode register 00

(PRM00) is input to the TI000 pin, the value of TM00 is taken into 16-bit timer capture/compare register 010

(CR010) and an interrupt request signal (INTTM010) is set.

Also, when the inverse edge to that of the capture operation is input into CR010, the value of TM00 is taken

into 16-bit timer capture/compare register 000 (CR000).

Sampling is performed using the count clock cycle selected by prescaler mode register 00 (PRM00), and a

capture operation is only performed when a valid level of the TI000 pin is detected twice, thus eliminating

noise with a short pulse width.

Caution The measurable pulse width in this operation example is up to 1 cycle of the timer counter.

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Figure 6-23. Control Register Settings for Pulse Width Measurement with Free-Running Counter and

Two Capture Registers (with Rising Edge Specified)

(a) Capture/compare control register 00 (CRC00)

7

0

6

0

5

0

4

0

3

0

CRC002 CRC001 CRC000

CRC00

1

CR000 used as capture register

Captures to CR000 at inverse edge

to valid edge of TI000^Note

.

CR010 used as capture register

(b) Prescaler mode register 00 (PRM00)

ES110 ES100 ES010 ES000

3

0

2

0

PRM001 PRM000

PRM00 0/1

0/1

0

1

0/1

Selects count clock (setting “11” is prohibited).

Specifies rising edge for pulse width detection.

Setting invalid (setting “10” is prohibited.)

(c) 16-bit timer mode control register 00 (TMC00)

7

6

0

5

0

4

0

TMC003 TMC002 TMC001 OVF00

TMC00

0

1

0/1

0

Free-running mode

Note If the valid edge of the TI000 pin is specified to be both the rising and falling edges, 16-bit timer

capture/compare register 000 (CR000) cannot perform the capture operation. When the CRC001 bit value is

1, the TM00 count value is not captured in the CR000 register when a valid edge of the TI010 pin is

detected, but the input from the TI010 pin can be used as an external interrupt source because INTTM000 is

generated at that timing.

Remark 0/1: Setting 0 or 1 allows another function to be used simultaneously with pulse width measurement.

See the description of the respective control registers for details.

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Figure 6-24. Timing of Pulse Width Measurement Operation by Free-Running Counter

and Two Capture Registers (with Rising Edge Specified)

t

Count clock

TM00 count value

TI000 pin input

0000H 0001H

D0 D0 + 1

D1 D1 + 1

FFFFH 0000H

D2 D2 + 1

D3

CR010 capture value

CR000 capture value

INTTM010

D0

D2

D1

D3

(D1 − D0) × t

(D2 − D1) × t^Note

(D3 − D2) × t

Note The carry flag is set to 1. Ignore this setting.

(4) Pulse width measurement by means of restart

Specify both the rising and falling edges as the valid edges of the TI000 pin, by using bits 4 and 5 (ES000 and

ES010) of PRM00.

When a valid edge of the TI000 pin is detected, the count value of 16-bit timer/counter 00 (TM00) is taken into

16-bit timer capture/compare register 010 (CR010), and then the pulse width of the signal input to the TI000

pin is measured by clearing TM00 and restarting the count.

Sampling is performed at the interval selected by prescaler mode register 00 (PRM00) and a capture operation

is only performed when a valid level of the TI000 pin is detected twice, thus eliminating noise with a short

pulse width.

Caution The measurable pulse width in this operation example is up to 1 cycle of the timer counter.

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Figure 6-25. Control Register Settings for Pulse Width Measurement by Means of Restart

(with Rising Edge Specified)

(a) Capture/compare control register 00 (CRC00)

7

0

6

0

5

0

4

0

3

0

CRC002 CRC001 CRC000

CRC00

1

CR000 used as capture register

Captures to CR000 at inverse edge to valid edge of TI000^Note

.

CR010 used as capture register

(b) Prescaler mode register 00 (PRM00)

ES110 ES100 ES010 ES000

3

0

2

0

PRM001 PRM000

PRM00 0/1

0/1

0

1

0/1

Selects count clock (setting “11” is prohibited).

Specifies rising edge for pulse width detection.

Setting invalid (setting “10” is prohibited.)

(c) 16-bit timer mode control register 00 (TMC00)

7

6

0

5

0

4

0

TMC003 TMC002 TMC001 OVF00

TMC00

0

1

0

0/1

0

Clears and starts at valid edge of TI000 pin.

Note If the valid edge of the TI000 pin is specified to be both the rising and falling edges, 16-bit timer

capture/compare register 000 (CR000) cannot perform the capture operation.

Figure 6-26. Timing of Pulse Width Measurement Operation by Means of Restart

(with Rising Edge Specified)

t

Count clock

0000H 0001H

D0 0000H 0001H D1

D2 0000H 0001H

TM00 count value

TI000 pin input

CR010 capture value

D0

D2

D1

CR000 capture value

INTTM010

(D1 + 1) × t

(D2 + 1) × t

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6.4.4 Square-wave output operation

Setting

The basic operation setting procedure is as follows.

<1> Set the count clock by using the PRM00 register.

<2> Set the CRC00 register (see Figure 6-27 for the set value).

<3> Set the TOC00 register (see Figure 6-27 for the set value).

<4> Set any value to the CR000 register (0000H cannot be set).

<5> Set the TMC00 register to start the operation (see Figure 6-27 for the set value).

Caution Changing the CR000 setting during TM00 operation may cause a malfunction. To change the

setting, refer to 6.5 Cautions Related to 16-bit Timer/Event Counter 00 (17) Changing compare

register during timer operation.

Remarks 1. For the setting of the TO00 pin, see 6.3 (5) Port mode register 3 (PM3).

2. For how to enable the INTTM000 interrupt, see CHAPTER 13 INTERRUPT FUNCTIONS.

A square wave with any selected frequency can be output at intervals determined by the count value preset to 16-

bit timer capture/compare register 000 (CR000).

The TO00 pin output status is reversed at intervals determined by the count value preset to CR000 + 1 by setting

bit 0 (TOE00) and bit 1 (TOC001) of 16-bit timer output control register 00 (TOC00) to 1. This enables a square wave

with any selected frequency to be output.

Figure 6-27. Control Register Settings in Square-Wave Output Mode (1/2)

(a) Prescaler mode register 00 (PRM00)

ES110 ES100 ES010 ES000

3

0

2

0

PRM001 PRM000

PRM00 0/1

0/1

Selects count clock.

Setting invalid (setting “10” is prohibited.)

(b) Capture/compare control register 00 (CRC00)

7

6

0

5

0

4

0

3

0

CRC002 CRC001 CRC000

CRC00

0

0/1

0

CR000 used as compare register

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Figure 6-27. Control Register Settings in Square-Wave Output Mode (2/2)

(c) 16-bit timer output control register 00 (TOC00)

7

0

OSPT00 OSPE00 TOC004 LVS00 LVR00 TOC001 TOE00

TOC00

0

0/1

1

Enables TO00 output.

Inverts output on match between TM00 and CR000.

Specifies initial value of TO00 output F/F (setting “11” is prohibited).

Does not invert output on match between TM00 and CR010.

Disables one-shot pulse output.

(d) 16-bit timer mode control register 00 (TMC00)

7

0

6

5

4

TMC003 TMC002 TMC001 OVF00

TMC00

0

1

0

Clears and starts on match between TM00 and CR000.

Remark 0/1: Setting 0 or 1 allows another function to be used simultaneously with square-wave output. See the

description of the respective control registers for details.

Figure 6-28. Square-Wave Output Operation Timing

Count clock

TM00 count value

CR000

0000H 0001H 0002H

N − 1

N

0000H 0001H 0002H

N − 1

N

0000H

N

INTTM000

TO00 pin output

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6.4.5 PPG output operations

Setting 16-bit timer mode control register 00 (TMC00) and capture/compare control register 00 (CRC00) as shown

in Figure 6-29 allows operation as PPG (Programmable Pulse Generator) output.

Setting

The basic operation setting procedure is as follows.

<1> Set the CRC00 register (see Figure 6-29 for the set value).

<2> Set any value to the CR000 register as the cycle.

<3> Set any value to the CR010 register as the duty factor.

<4> Set the TOC00 register (see Figure 6-29 for the set value).

<5> Set the count clock by using the PRM00 register.

<6> Set the TMC00 register to start the operation (see Figure 6-29 for the set value).

Caution Changing the CRC0n0 setting during TM00 operation may cause a malfunction. To change the

setting, refer to 6.5 Cautions Related to 16-bit Timer/Event Counter 00 (17) Changing compare

register during timer operation.

Remarks 1. For the setting of the TO00 pin, see 6.3 (5) Port mode register 3 (PM3).

2. For how to enable the INTTM000 interrupt, see CHAPTER 13 INTERRUPT FUNCTIONS.

3. n = 0 or 1

In the PPG output operation, rectangular waves are output from the TO00 pin with the pulse width and the cycle

that correspond to the count values preset in 16-bit timer capture/compare register 010 (CR010) and in 16-bit timer

capture/compare register 000 (CR000), respectively.

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Figure 6-29. Control Register Settings for PPG Output Operation

(a) Capture/compare control register 00 (CRC00)

7

0

6

0

5

0

4

0

3

0

CRC002 CRC001 CRC000

CRC00

0

×

0

CR000 used as compare register

CR010 used as compare register

(b) 16-bit timer output control register 00 (TOC00)

7

OSPT00 OSPE00 TOC004 LVS00 LVR00 TOC001 TOE00

TOC00

0

1

0/1

1

Enables TO00 output.

Inverts output on match between TM00 and CR000.

Specifies initial value of TO00 output F/F (setting "11" is prohibited).

Inverts output on match between TM00 and CR010.

Disables one-shot pulse output.

(c) Prescaler mode register 00 (PRM00)

ES110 ES100 ES010 ES000

3

0

2

PRM001 PRM000

PRM00 0/1

0/1

0

0/1

Selects count clock.

Setting invalid (setting “10” is prohibited.)

(d) 16-bit timer mode control register 00 (TMC00)

7

6

0

5

0

4

0

TMC003 TMC002 TMC001 OVF00

TMC00

0

1

0

Clears and starts on match between TM00 and CR000.

Cautions 1. Values in the following range should be set in CR000 and CR010.

0000H < CR010 < CR000 ≤ FFFFH

2. The cycle of the pulse generated through PPG output (CR000 setting value + 1) has a duty of

(CR010 setting value + 1)/(CR000 setting value + 1).

Remark ×: Don’t care

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Figure 6-30. Configuration Diagram of PPG Output

16-bit timer capture/compare

register 000 (CR000)

fXP

f

XP/2²

XP/2⁸

Clear

circuit

16-bit timer counter 00

(TM00)

Noise

eliminator

TI000/INTP0/P30

TO00/TI010/

INTP2/P31

f

XP

16-bit timer capture/compare

register 010 (CR010)

Figure 6-31. PPG Output Operation Timing

t

Count clock

TM00 count value

0000H 0001H

M − 1

M

0000H 0001H

N

N − 1

N

Clear

CR000 capture value

CR010 capture value

TO00

N

M

Pulse width: (M + 1) × t

1 cycle: (N + 1) × t

Remark 0000H < M < N ≤ FFFFH

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6.4.6 One-shot pulse output operation

16-bit timer/event counter 00 can output a one-shot pulse in synchronization with a software trigger or an external

trigger (TI000 pin input).

Setting

The basic operation setting procedure is as follows.

<1> Set the count clock by using the PRM00 register.

<2> Set the CRC00 register (see Figures 6-32 and 6-34 for the set value).

<3> Set the TOC00 register (see Figures 6-32 and 6-34 for the set value).

<4> Set any value to the CR000 and CR010 registers (0000H cannot be set).

<5> Set the TMC00 register to start the operation (see Figures 6-32 and 6-34 for the set value).

Remarks 1. For the setting of the TO00 pin, see 6.3 (5) Port mode register 3 (PM3).

2. For how to enable the INTTM000 (if necessary, INTTM010) interrupt, see CHAPTER 13

INTERRUPT FUNCTIONS.

(1) One-shot pulse output with software trigger

A one-shot pulse can be output from the TO00 pin by setting 16-bit timer mode control register 00 (TMC00),

capture/compare control register 00 (CRC00), and 16-bit timer output control register 00 (TOC00) as shown in

Figure 6-32, and by setting bit 6 (OSPT00) of the TOC00 register to 1 by software.

By setting the OSPT00 bit to 1, 16-bit timer/event counter 00 is cleared and started, and its output becomes

active at the count value (N) set in advance to 16-bit timer capture/compare register 010 (CR010). After that,

the output becomes inactive at the count value (M) set in advance to 16-bit timer capture/compare register 000

(CR000)^Note

.

Even after the one-shot pulse has been output, the TM00 register continues its operation. To stop the TM00

register, the TMC003 and TMC002 bits of the TMC00 register must be cleared to 00.

Note The case where N < M is described here. When N > M, the output becomes active with the CR000

register and inactive with the CR010 register. Do not set N to M.

Cautions 1. Do not set the OSPT00 bit to 1 again while the one-shot pulse is being output. To output the

one-shot pulse again, wait until the current one-shot pulse output is completed.

2. When using the one-shot pulse output of 16-bit timer/event counter 00 with a software

trigger, do not change the level of the TI000 pin or its alternate-function port pin.

Because the external trigger is valid even in this case, the timer is cleared and started even

at the level of the TI000 pin or its alternate-function port pin, resulting in the output of a

pulse at an undesired timing.

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Figure 6-32. Control Register Settings for One-Shot Pulse Output with Software Trigger

(a) Prescaler mode register 00 (PRM00)

ES110

0/1

ES100

0/1

ES010

0/1

ES000

0/1

3

0

2

0

PRM001 PRM000

0/1 0/1

PRM00

Selects count clock.

Setting invalid

(setting “10” is prohibited.)

Setting invalid

(setting “10” is prohibited.)

(b) Capture/compare control register 00 (CRC00)

7

0

6

0

5

0

4

0

3

0

CRC002 CRC001 CRC000

0/1

CRC00

0

CR000 as compare register

CR010 as compare register

(c) 16-bit timer output control register 00 (TOC00)

7

0

OSPT00 OSPE00 TOC004 LVS00

0/1

LVR00 TOC001 TOE00

0/1

TOC00

0

1

Enables TO00 output.

Inverts output upon match

between TM00 and CR000.

Specifies initial value of

TO00 output F/F (setting “11” is prohibited.)

Inverts output upon match

between TM00 and CR010.

Sets one-shot pulse output mode.

Set to 1 for output.

(d) 16-bit timer mode control register 00 (TMC00)

7

0

6

0

5

0

4

0

TMC003 TMC002 TMC001 OVF00

TMC00

0

1

0

Free-running mode

Caution Do not set 0000H to the CR000 and CR010 registers.

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CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00

Figure 6-33. Timing of One-Shot Pulse Output Operation with Software Trigger

Set TMC00 to 04H

(TM00 count starts)

Count clock

TM00 count

CR010 set value

CR000 set value

0000H 0001H

N

N + 1 0000H

N − 1

N

M − 1

M

M + 1 M + 2

N

M

OSPT00

INTTM010

INTTM000

TO00 pin output

Caution 16-bit timer counter 00 starts operating as soon as a value other than 00 (operation stop

mode) is set to the TMC003 and TMC002 bits.

Remark N < M

(2) One-shot pulse output with external trigger

A one-shot pulse can be output from the TO00 pin by setting 16-bit timer mode control register 00 (TMC00),

capture/compare control register 00 (CRC00), and 16-bit timer output control register 00 (TOC00) as shown in

Figure 6-34, and by using the valid edge of the TI000 pin as an external trigger.

The valid edge of the TI000 pin is specified by bits 4 and 5 (ES000, ES010) of prescaler mode register 00

(PRM00). The rising, falling, or both the rising and falling edges can be specified.

When the valid edge of the TI000 pin is detected, the 16-bit timer/event counter is cleared and started, and the

output becomes active at the count value set in advance to 16-bit timer capture/compare register 010

(CR010). After that, the output becomes inactive at the count value set in advance to 16-bit timer

capture/compare register 000 (CR000)^Note

.

Note The case where N < M is described here. When N > M, the output becomes active with the CR000

register and inactive with the CR010 register. Do not set N to M.

Caution Do not input the external trigger again while the one-shot pulse is being output. To output

the one-shot pulse again, wait until the current one-shot pulse output is completed.

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CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00

Figure 6-34. Control Register Settings for One-Shot Pulse Output with External Trigger

(with Rising Edge Specified)

(a) Prescaler mode register 00 (PRM00)

ES110

0/1

ES100

0/1

ES010

0

ES000

1

3

0

2

0

PRM001 PRM000

0/1 0/1

PRM00

Selects count clock

(setting “11” is prohibited).

Specifies the rising edge

for pulse width detection.

Setting invalid

(setting “10” is prohibited.)

(b) Capture/compare control register 00 (CRC00)

7

0

6

0

5

0

4

0

3

0

CRC002 CRC001 CRC000

0/1

CRC00

0

CR000 used as compare register

CR010 used as compare register

(c) 16-bit timer output control register 00 (TOC00)

7

0

OSPT00 OSPE00 TOC004 LVS00

0/1

LVR00 TOC001 TOE00

0/1

TOC00

0

1

Enables TO00 output.

Inverts output upon match

between TM00 and CR000.

Specifies initial value of

TO00 output F/F (setting “11” is prohibited.)

Inverts output upon match

between TM00 and CR010.

Sets one-shot pulse output mode.

(d) 16-bit timer mode control register 00 (TMC00)

7

0

6

0

5

0

4

0

TMC003 TMC002 TMC001 OVF00

TMC00

1

0

Clears and starts at

valid edge of TI000 pin.

Caution Do not set 0000H to the CR000 and CR010 registers.

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Figure 6-35. Timing of One-Shot Pulse Output Operation with External Trigger (with Rising Edge Specified)

When TMC00 is set to 08H

(TM00 count starts)

t

Count clock

TM00 count value

CR010 set value

CR000 set value

0000H 0001H

0000H

N

N + 1 N + 2

M − 2 M − 1

M

M + 1 M + 2

N

M

TI000 pin input

INTTM010

INTTM000

TO00 pin output

Caution 16-bit timer counter 00 starts operating as soon as a value other than 0, 0 (operation stop mode)

is set to the TMC003 and TMC002 bits.

Remark N < M

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CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00

6.5 Cautions Related to 16-bit Timer/Event Counter 00

(1) Timer start errors

An error of up to one clock may occur in the time required for a match signal to be generated after timer start.

This is because 16-bit timer counter 00 (TM00) is started asynchronously to the count clock.

Figure 6-36. Start Timing of 16-bit Timer Counter 00 (TM00)

Count clock

0000H

0001H

0002H

0003H

0004H

TM00 count value

Timer start

(2) 16-bit timer counter 00 (TM00) operation

<1> 16-bit timer counter 00 (TM00) starts operation at the moment TMC002 and TMC003 (operation stop

mode) are set to a value other than 0, 0, respectively. Set TMC002 and TMC003 to 0, 0 to stop the

operation.

<2> Even if TM00 is read, the value is not captured by 16-bit timer capture/compare register 010 (CR010).

<3> When TM00 is read, count misses do not occur, since the input of the count clock is temporarily stopped

and then resumed after the read.

<4> If the timer is stopped, timer counts and timer interrupts do not occur, even if a signal is input to the

TI000/TI010 pins.

(3) Setting of 16-bit timer capture/compare registers 000, 010 (CR000, CR010)

<1> Set 16-bit timer capture/compare register 000 (CR000) to other than 0000H in the clear & start mode

entered on match between TM00 and CR000. This means a 1-pulse count operation cannot be

performed when this register is used as an external event counter.

<2> When the clear & start mode entered on a match between TM00 and CR000 is selected, CR000 should

not be specified as a capture register.

<3> In the free-running mode and in the clear & start mode using the valid edge of the TI000 pin, if CR0n0 is

set to 0000H, an interrupt request (INTTM0n0) is generated when CR0n0 changes from 0000H to

0001H following overflow (FFFFH).

<4> If the new value of CR0n0 is less than the value of TM00, TM00 continues counting, overflows, and then

starts counting from 0 again. If the new value of CR0n0 is less than the old value, therefore, the timer

must be reset to be restarted after the value of CR0n0 is changed.

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(4) Capture register data retention

The value of 16-bit timer capture/compare register 0n0 (CR0n0) after 16-bit timer/event counter 00 has

stopped is not guaranteed.

Remark n = 0, 1

(5) Setting of 16-bit timer mode control register 00 (TMC00)

The timer operation must be stopped before writing to bits other than the OVF00 flag.

(6) Setting of capture/compare control register 00 (CRC00)

The timer operation must be stopped before setting CRC00.

(7) Setting of 16-bit timer output control register 00 (TOC00)

<1> Timer operation must be stopped before setting other than OSPT00.

<2> If LVS00 and LVR00 are read, 0 is read.

<3> OSPT00 is automatically cleared after data is set, so 0 is read.

<4> Do not set OSPT00 to 1 other than in one-shot pulse output mode.

<5> A write interval of two cycles or more of the count clock selected by prescaler mode register 00 (PRM00)

is required, when OSPT00 is set to 1 successively.

(8) Setting of prescaler mode register 00 (PRM00)

Always set data to PRM00 after stopping the timer operation.

(9) Valid edge setting

Set the valid edge of the TI000 pin with bits 4 and 5 (ES000 and ES010) of prescaler mode register 00

(PRM00) after stopping the timer operation.

(10) One-shot pulse output

One-shot pulse output normally operates only in the free-running mode or in the clear & start mode at the valid

edge of the TI000 pin. Because an overflow does not occur in the clear & start mode on a match between

TM00 and CR000, one-shot pulse output is not possible.

(11) One-shot pulse output by software

<1> Do not set the OSPT00 bit to 1 again while the one-shot pulse is being output. To output the one-shot

pulse again, wait until the current one-shot pulse output is completed.

<2> When using the one-shot pulse output of 16-bit timer/event counter 00 with a software trigger, do not

change the level of the TI000 pin or its alternate function port pin. Because the external trigger is valid

even in this case, the timer is cleared and started even at the level of the TI000 pin or its alternate

function port pin, resulting in the output of a pulse at an undesired timing.

<3> Do not set the 16-bit timer capture/compare registers 000 and 010 (CR000 and CR010) to 0000H.

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CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00

(12) One-shot pulse output with external trigger

<1> Do not input the external trigger again while the one-shot pulse is being output. To output the one-shot

pulse again, wait until the current one-shot pulse output is completed.

<2> Do not set the 16-bit timer capture/compare registers 000 and 010 (CR000 and CR010) to 0000H.

(13) Operation of OVF00 flag

<1> The OVF00 flag is also set to 1 in the following case.

Either of the clear & start mode entered on a match between TM00 and CR000, clear & start at the valid

edge of the TI000 pin, or free-running mode is selected.

↓

CR000 is set to FFFFH.

↓

When TM00 is counted up from FFFFH to 0000H.

Figure 6-37. Operation Timing of OVF00 Flag

Count clock

CR000

TM00

FFFFH

FFFEH

FFFFH

0000H

0001H

OVF00

INTTM000

<2> Even if the OVF00 flag is cleared before the next count clock is counted (before TM00 becomes 0001H)

after the occurrence of a TM00 overflow, the OVF00 flag is re-set newly and clear is disabled.

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CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00

(14) Conflicting operations

If the register read period and the input of the capture trigger conflict when CR000/CR010 is used as a capture

register, the capture trigger input takes precedence and the read data is undefined. Also, if the count stop of

the timer and the input of the capture trigger conflict, the captured data is undefined.

Figure 6-38. Capture Register Data Retention Timing

Count clock

N

N + 1

N + 2

M

M + 1

M + 2

TM00 count value

Edge input

INTTM010

Capture read signal

CR010 capture value

X

N + 2

M + 1

Capture

Capture, but

read value is

not guaranteed

(15) Capture operation

<1> If the valid edge of the TI000 pin is to be set as the count clock, do not set the clear/start mode and the

capture trigger at the valid edge of the TI000 pin.

<2> If both the rising and falling edges are selected as the valid edges of the TI000 pin, capture is not

performed.

<3> When the CRC001 bit value is 1, the TM00 count value is not captured in the CR000 register when a

valid edge of the TI010 pin is detected, but the input from the TI010 pin can be used as an external

interrupt source because INTTM000 is generated at that timing.

<4> To ensure the reliability of the capture operation, the capture trigger requires a pulse longer than two

cycles of the count clock selected by prescaler mode register 00 (PRM00).

<5> The capture operation is performed at the fall of the count clock. An interrupt request input (INTTM0n0),

however, occurs at the rise of the next count clock.

<6> To use two capture registers, set the TI000 and TI010 pins.

Remark n = 0, 1

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(16) Compare operation

The capture operation may not be performed for CR0n0 set in compare mode even if a capture trigger is input.

Remark n = 0, 1

(17) Changing compare register during timer operation

<1> With the 16-bit timer capture/compare register 0n0 (CR0n0) used as a compare register, when changing

CR0n0 around the timing of a match between 16-bit timer counter 00 (TM00) and 16-bit timer

capture/compare register 0n0 (CR0n0) during timer counting, the change timing may conflict with the

timing of the match, so the operation is not guaranteed in such cases. To change CR0n0 during timer

counting, follow the procedure below using an INTTM000 interrupt.

1. Disable the timer output inversion operation at the match between TM00 and CR000 (TOC001 = 0).

2. Disable the INTTM000 interrupt (TMMK000 = 1).

3. Rewrite CR000.

4. Wait for 1 cycle of the TM00 count clock.

5. Enable the timer output inversion operation at the match between TM00 and CR000 (TOC001 = 1).

6. Clear the interrupt request flag of INTTM000 (TMIF000 = 0).

7. Enable the INTTM000 interrupt (TMMK000 = 0).

1. Disable the timer output inversion operation at the match between TM00 and CR010 (TOC004 = 0).

2. Disable the INTTM000 interrupt (TMMK000 = 1).

3. Rewrite CR010.

4. Wait for 1 cycle of the TM00 count clock.

5. Enable the timer output inversion operation at the match between TM00 and CR010 (TOC004 = 1).

6. Clear the interrupt request flag of INTTM000 (TMIF000 = 0).

7. Enable the INTTM000 interrupt (TMMK000 = 0).

While interrupts and timer output inversion are disabled (1 to 4 above), timer counting is continued. If

the value to be set in CR0n0 is small, the value of TM00 may exceed CR0n0. Therefore, set the value,

considering the time lapse of the timer clock and CPU clock after an INTTM000 interrupt has been

generated.

Remark n = 0, 1

<2> If CR010 is changed during timer counting without performing processing <1> above, the value in

CR010 may be rewritten twice or more, causing an inversion of the output level of the TO00 pin at each

rewrite.

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CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00

(18) Edge detection

<1> In the following cases, note with caution that the valid edge of the TI0n0 pin is detected.

(a) Immediately after a system reset, if a high level is input to the TI0n0 pin, the operation of the 16-bit

timer counter 00 (TM00) is enabled

→ If the rising edge or both rising and falling edges are specified as the valid edge of the TI0n0 pin,

a rising edge is detected immediately after the TM00 operation is enabled.

(b) If the TM00 operation is stopped while the TI0n0 pin is high level, TM00 operation is then enabled

after a low level is input to the TI0n0 pin

→ If the falling edge or both rising and falling edges are specified as the valid edge of the TI0n0 pin,

a falling edge is detected immediately after the TM00 operation is enabled.

(c) If the TM00 operation is stopped while the TI0n0 pin is low level, TM00 operation is then enabled

after a high level is input to the TI0n0 pin

→ If the rising edge or both rising and falling edges are specified as the valid edge, of the TI0n0 pin,

a rising edge is detected immediately after the TM00 operation is enabled.

Remark n = 0, 1

<2> The sampling clock used to remove noise differs when a TI000 valid edge is used as the count clock and

when it is used as a capture trigger. In the former case, the count clock is f^XP, and in the latter case the

count clock is selected by prescaler mode register 00 (PRM00). The capture operation is not performed

until the valid edge is sampled and the valid level is detected twice, thus eliminating, noise with a short

pulse width.

(19) External event counter

<1> The timing of the count start is after two valid edge detections.

<2> When reading the external event counter count value, TM00 should be read.

(20) PPG output

<1> Values in the following range should be set in CR000 and CR010:

0000H < CR010 < CR000 ≤ FFFFH

<2> The cycle of the pulse generated through PPG output (CR000 setting value + 1) has a duty of (CR010

setting value + 1)/(CR000 setting value + 1).

(21) STOP mode or system clock stop mode setting

Except when the valid edge of the TI000 pin is selected as the count clock, stop the timer operation before

setting STOP mode or system clock stop mode; otherwise the timer may malfunction when the system clock

starts.

(22) P31/TI010/TO00 pin

When using P31 as the input pin (TI010) of the valid edge, it cannot be used as a timer output pin (TO00).

When using P31 as the timer output pin (TO00), it cannot be used as the input pin (TI010) of the valid edge.

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(23) External clock limitation

<1> When using an input pulse of the TI000 pin as a count clock (external trigger), be sure to input the pulse

width which satisfies the AC characteristics. For the AC characteristics, refer to CHAPTER 22 and

CHAPTER 23 ELECTRICAL SPECIFICATIONS.

<2> When an external waveform is input to 16-bit timer/event counter 00, it is sampled by the noise limiter

circuit and thus an error occurs on the timing to become valid inside the device.

Count clock (fsam

)

TI000

Sampling time on filter

Input pulse through

noise limiter circuit

Remark The count clock (f^sam) can be selected using bits 0 and 1 (PRM000, PRM001) of prescaler

mode register 00 (PRM00).

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CHAPTER 7 8-BIT TIMER 80

7.1 Function of 8-bit Timer 80

8-bit timer 80 has an 8-bit interval timer function and generates an interrupt at intervals specified in advance.

Table 7-1. Interval Time of 8-bit Timer 80

Minimum Interval Time

2⁶/fXP (8 μs)

2⁸/fXP (32 μs)

2¹⁰/fXP (128 μs)

2¹⁶/fXP (8.19 ms)

2⁶/fXP (6.4 μs)

2⁸/fXP (25.6 μs)

2¹⁰/fXP (102 μs)

2¹⁶/fXP (6.55 ms)

Maximum Interval Time

2¹⁴/fXP (2.05 ms)

2¹⁶/fXP (8.19 ms)

2¹⁸/fXP (32.7 ms)

2²⁴/fXP (2.01 s)

Resolution

2⁶/fXP (8 μs)

2⁸/fXP (32 μs)

2¹⁰/fXP (128 μs)

2¹⁶/fXP (8.19 ms)

2⁶/fXP (6.4 μs)

2⁸/fXP (25.6 μs)

2¹⁰/fXP (102 μs)

2¹⁶/fXP (6.55 ms)

fXP = 8.0 MHz

fXP = 10.0 MHz

2¹⁴/fXP (1.64 ms)

2¹⁶/fXP (6.55 ms)

2¹⁸/fXP (26.2 ms)

2²⁴/fXP (1.68 s)

Remark fXP: Oscillation frequency of clock to peripheral hardware

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CHAPTER 7 8-BIT TIMER 80

7.2 Configuration of 8-bit Timer 80

8-bit timer 80 consists of the following hardware.

Table 7-2. Configuration of 8-bit Timer 80

Item

Timer counter

Configuration

8-bit timer counter 80 (TM80)

Register

8-bit compare register 80 (CR80)

Control register

8-bit timer mode control register 80 (TMC80)

Figure 7-1. Block Diagram of 8-bit Timer 80

Internal bus

8-bit compare register 80

(CR80)

Match

INTTM80

f

XP/2⁶

XP/2⁸

Clear

8-bit timer/counter 80

(TM80)

f

XP/2¹⁰

XP/2¹⁶

f

TCE80 TCL801 TCL800

8-bit timer mode control

register 80 (TMC80)

Internal bus

Remark f^XP: Oscillation frequency of clock to peripheral hardware

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CHAPTER 7 8-BIT TIMER 80

(1) 8-bit compare register 80 (CR80)

This 8-bit register always compares its set value with the count value of 8-bit timer/counter 80 (TM80). It

generates an interrupt request signal (INTTM80) if the two values match.

CR80 is set by using an 8-bit memory manipulation instruction. A value of 00H to FFH can be set to this

register.

Reset signal generation makes the contents of this register undefined.

Figure 7-2. Format of 8-bit Compare Register 80 (CR80)

Address: FFCDH

After reset: Undefined

W

Symbol

CR80

7

6

5

4

3

2

1

0

Caution When changing the value of CR80, be sure to stop the timer operation. If the value of CR80

is changed with the timer operation enabled, a match interrupt request signal is generated

immediately and the timer may be cleared.

(2) 8-bit timer counter 80 (TM80)

This 8-bit register counts the count pulses.

The value of TM80 can be read by using an 8-bit memory manipulation instruction.

Reset signal generation clears TM80 to 00H.

Figure 7-3. Format of 8-bit Timer Counter 80 (TM80)

Address: FFCEH

After reset: 00H

R

Symbol

TM80

7

6

5

4

3

2

1

0

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CHAPTER 7 8-BIT TIMER 80

7.3 Register Controlling 8-bit Timer 80

8-bit timer 80 is controlled by 8-bit timer mode control register 80 (TMC80).

(1) 8-bit timer mode control register 80 (TMC80)

This register is used to enable or stop the operation of 8-bit timer/counter 80 (TM80), and to set the count

clock of TM80.

This register is set by using a 1-bit or 8-bit memory manipulation instruction.

Reset signal generation clears TMC80 to 00H.

Figure 7-4. Format of 8-bit Timer Mode Control Register 80 (TMC80)

Address: FFCCH

After reset: 00H

R/W

Symbol

TMC80

<7>

6

0

5

4

0

3

0

2

1

0

TCE80

0

TCL801

TCL800

TCE80

Control of operation of TM80

0

1

Stop operation (clear TM80 to 00H).

Enable operation.

TCL801

TCL800

Selection of count clock of 8-bit timer 80

f^XP= 8.0 MHz

156.3 kHz

39.06 kHz

9.77 kHz

fXP = 10.0 MHz

0

1

0

1

0

1

fXP/2⁶

fXP/2⁸

fXP/2¹⁰

fXP/2¹⁶

125 kHz

31.25 kHz

7.81 kHz

0.12 kHz

0.15 kHz

Cautions 1. Be sure to set TMC80 after stopping the timer operation.

2. Be sure to clear bits 0 and 6 to 0.

Remark f^XP: Oscillation frequency of clock to peripheral hardware

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CHAPTER 7 8-BIT TIMER 80

7.4 Operation of 8-bit Timer 80

7.4.1 Operation as interval timer

When 8-bit timer 80 operates as an interval timer, it can repeatedly generate an interrupt at intervals specified by

the count value set in advance to 8-bit compare register 80 (CR80).

To use 8-bit timer 80 as an interval timer, make the following setting.

<1> Disable the operation of 8-bit timer counter 80 (clear TCE80 (bit 7 of 8-bit timer mode control register 80

(TMC80)) to 0).

<2> Set the count clock of 8-bit timer 80 (refer to Tables 7-3 and 7-4).

<3> Set the count value to CR80.

<4> Enable the operation of TM80 (set TCE80 to 1).

When the count value of 8-bit timer counter 80 (TM80) matches the set value of CR80, the value of TM80 is

cleared to 00H and counting is continued. At the same time, an interrupt request signal (INTTM80) is generated.

Tables 7-3 and 7-4 show the interval time, and Figure 7-5 shows the timing of the interval timer operation.

Cautions 1. When changing the value of CR80, be sure to stop the timer operation. If the value of CR80 is

changed with the timer operation enabled, a match interrupt request signal may be generated

immediately.

2. If the count clock of TMC80 is set and the operation of TM80 is enabled at the same time by

using an 8-bit memory manipulation instruction, the error of one cycle after the timer is

started may be 1 clock or more (refer to 7.5 (1) Error when timer starts). Therefore, be sure to

follow the above sequence when using TM80 as an interval timer.

Table 7-3. Interval Time of 8-bit Timer 80 (f^XP= 8.0 MHz)

TCL801

TCL800

Minimum Interval Time

2⁶/fXP (8 μs)

2⁸/fXP (32 μs)

2¹⁰/fXP (128 μs)

2¹⁶/fXP (8.19 ms)

Maximum Interval Time

2¹⁴/fXP (2.05 ms)

Resolution

2⁶/fXP (8 μs)

2⁸/fXP (32 μs)

2¹⁰/fXP (128 μs)

2¹⁶/fXP (8.19 ms)

0

1

0

1

0

1

2¹⁶/fXP (8.19 ms)

2¹⁸/fXP (32.7 ms)

2²⁴/fXP (2.01 s)

Remark fXP: Oscillation frequency of clock to peripheral hardware

Table 7-4. Interval Time of 8-bit Timer 80 (f^XP= 10.0 MHz)

TCL801

TCL800

Minimum Interval Time

2⁶/fXP (6.4 μs)

2⁸/fXP (25.6 μs)

2¹⁰/fXP (102 μs)

2¹⁶/fXP (6.55 ms)

Maximum Interval Time

2¹⁴/fXP (1.64 ms)

Resolution

2⁶/fXP (6.4 μs)

2⁸/fXP (25.6 μs)

2¹⁰/fXP (102 μs)

2¹⁶/fXP (6.55 ms)

0

1

0

1

0

1

2¹⁶/fXP (6.55 ms)

2¹⁸/fXP (26.2 ms)

2²⁴/fXP (1.68 s)

Remark fXP: Oscillation frequency of clock to peripheral hardware

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CHAPTER 7 8-BIT TIMER 80

Figure 7-5. Timing of Interval Timer Operation

t

Count clock

TM80 count value

00H

01H

N

00H 01H

Clear

N

00H 01H

Clear

N

CR80

N

TCE80

Count start

INTTM80

Interrupt request generated

Interval time

Interrupt request generated

Interval time

Remark Interval time = (N + 1) × t

N = 00H to FFH

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CHAPTER 7 8-BIT TIMER 80

7.5 Notes on 8-bit Timer 80

(1) Error when timer starts

The time from starting the timer to generation of the match signal includes an error of up to 1.5 clocks. This is

because, if the timer is started while the count clock is high, the rising edge may be immediately detected and

the counter may be incremented (refer to Figure 7-6).

Figure 7-6. Case Where Error of 1.5 Clocks (Max.) Occurs

Delay A

Count pulse

8-bit timer counter 80

(TM80)

Selected clock

TCE80

Clear signal

Delay B

Selected clock

TCE80

Clear signal

Count pulse

...

TM80 count value

00H

01H

Delay A

02H

03H

Delay B

If the timer is started when the selected clock is high

and if delay A > delay B, an error of up to 1.5 clocks occurs.

(2) Setting of 8-bit compare register 80

8-bit compare register 80 (CR80) can be set to 00H.

(3) Note on setting STOP mode

Before executing the STOP instruction, be sure to stop the timer operation (TCE80 = 0).

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CHAPTER 8 8-BIT TIMER H1

8.1 Functions of 8-bit Timer H1

8-bit timer H1 has the following functions.

• Interval timer

• PWM output mode

• Square-wave output

8.2 Configuration of 8-bit Timer H1

8-bit timer H1 consists of the following hardware.

Table 8-1. Configuration of 8-bit Timer H1

Item

Timer register

Registers

Configuration

8-bit timer counter H1

8-bit timer H compare register 01 (CMP01)

8-bit timer H compare register 11 (CMP11)

Timer output

TOH1

Control registers

8-bit timer H mode register 1 (TMHMD1)

Port mode register 4 (PM4)

Port register 4 (P4)

Figure 8-1 shows a block diagram.

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(1) 8-bit timer H compare register 01 (CMP01)

This register can be read or written by an 8-bit memory manipulation instruction.

Reset signal generation clears this register to 00H.

Figure 8-2. Format of 8-bit Timer H Compare Register 01 (CMP01)

Address: FF0EH After reset: 00H R/W

Symbol

CMP01

7

5

3

2

1

0

6

4

Caution CMP01 cannot be rewritten during timer count operation.

(2) 8-bit timer H compare register 11 (CMP11)

This register can be read or written by an 8-bit memory manipulation instruction.

Reset signal generation clears this register to 00H.

Figure 8-3. Format of 8-bit Timer H Compare Register 11 (CMP11)

Address: FF0FH After reset: 00H R/W

Symbol

CMP11

7

5

3

2

1

0

6

4

CMP11 can be rewritten during timer count operation.

If the CMP11 value is rewritten during timer operation, the compare value after the rewrite takes effect at the timing

at which the count value and the compare value before the rewrite match. If the timing at which the count value and

compare value match conflicts with the timing of the writing from the CPU to CMP11, the compare value after the

rewrite takes effect at the timing at which the next count value and the compare value before the rewrite match.

Caution In the PWM output mode, be sure to set CMP11 when starting the timer count operation (TMHE1

= 1) after the timer count operation was stopped (TMHE1 = 0) (be sure to set again even if setting

the same value to CMP11).

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8.3 Registers Controlling 8-bit Timer H1

The following three registers are used to control 8-bit timer H1.

• 8-bit timer H mode register 1 (TMHMD1)

• Port mode register 4 (PM4)

• Port register 4 (P4)

(1) 8-bit timer H mode register 1 (TMHMD1)

This register controls the mode of timer H.

This register can be set by a 1-bit or 8-bit memory manipulation instruction.

Reset signal generation clears this register to 00H.

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Figure 8-4. Format of 8-bit Timer H Mode Register 1 (TMHMD1)

Address: FF70H After reset: 00H R/W

<7>

5

3

2

<1>

<0>

6

4

Symbol

TMHMD1

TMHE1 CKS12

CKS11 CKS10 TMMD11 TMMD10 TOLEV1 TOEN1

TMHE1

Timer operation enable

0

1

Stop timer count operation (counter is cleared to 0)

Enable timer count operation (count operation started by inputting clock)

CKS12

CKS11

CKS10

Count clock (fCNT) selection

(10 MHz)

0

1

0

1

0

1

0

1

0

1

f

XP

XP/2²(2.5 MHz)

XP/2⁴(625 kHz)

XP/2⁶(156.25 kHz)

XP/2¹²(2.44 kHz)

RL/2⁷(1.88 kHz (TYP.))

Other than above

Setting prohibited

TMMD11 TMMD10

Timer operation mode

0

1

0

Interval timer mode

PWM output mode

Other than above Setting prohibited

TOLEV1

Timer output level control (in default mode)

0

1

Low level

High level

TOEN1

Timer output control

0

1

Disable output

Enable output

Cautions 1. When TMHE1 = 1, setting the other bits of the TMHMD1 register is prohibited.

2. In the PWM output mode, be sure to set 8-bit timer H compare register 11 (CMP11) when

starting the timer count operation (TMHE1 = 1) after the timer count operation was stopped

(TMHE1 = 0) (be sure to set again even if setting the same value to the CMP11 register).

Remarks 1. f^XP: Oscillation frequency of clock to peripheral hardware

2. f^RL: Low-speed internal oscillation clock frequency

3. Figures in parentheses apply to operation at fXP = 10 MHz, fRL = 240 kHz (TYP.).

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(2) Port mode register 4 (PM4)

This register sets port 4 input/output in 1-bit units.

When using the P42/TOH1 pin for timer output, clear PM42 and the output latch of P42 to 0.

PM4 can be set by a 1-bit or 8-bit memory manipulation instruction.

Generation of reset signal sets this register to FFH.

Figure 8-5. Format of Port Mode Register 4 (PM4)

Address: FF24H After reset: FFH R/W

Symbol

PM4

7

6

5

4

3

2

1

0

PM47

PM46

PM45

PM44

PM43

PM42

PM41

PM40

PM4n

P4n pin I/O mode selection (n = 0 to 7)

0

1

Output mode (output buffer on)

Input mode (output buffer off)

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8.4 Operation of 8-bit Timer H1

8.4.1 Operation as interval timer/square-wave output

When 8-bit timer counter H1 and compare register 01 (CMP01) match, an interrupt request signal (INTTMH1) is

generated and 8-bit timer counter H1 is cleared to 00H.

Compare register 11 (CMP11) is not used in interval timer mode. Since a match of 8-bit timer counter H1 and the

CMP11 register is not detected even if the CMP11 register is set, timer output is not affected.

By setting bit 0 (TOEN1) of timer H mode register 1 (TMHMD1) to 1, a square wave of any frequency (duty = 50%)

is output from TOH1.

(1) Usage

Generates the INTTMH1 signal repeatedly at the same interval.

<1> Set each register.

Figure 8-6. Register Setting During Interval Timer/Square-Wave Output Operation

(i) Setting timer H mode register 1 (TMHMD1)

TMHE1

0

CKS12 CKS11

0/1 0/1

CKS10 TMMD11 TMMD10 TOLEV1 TOEN1

0/1 0/1 0/1

TMHMD1

0

Timer output setting

Timer output level inversion setting

Interval timer mode setting

Count clock (f^CNT) selection

Count operation stopped

(ii) CMP01 register setting

• Compare value (N)

<2> Count operation starts when TMHE1 = 1.

<3> When the values of 8-bit timer counter H1 and the CMP01 register match, the INTTMH1 signal is generated

and 8-bit timer counter H1 is cleared to 00H.

Interval time = (N +1)/f^CNT

<4> Subsequently, the INTTMH1 signal is generated at the same interval. To stop the count operation, clear

TMHE1 to 0.

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(2) Timing chart

The timing of the interval timer/square-wave output operation is shown below.

Figure 8-7. Timing of Interval Timer/Square-Wave Output Operation (1/2)

(a) Basic operation (01H ≤ CMP01 ≤ FEH)

Count clock

Count start

00H

01H

N

00H

Clear

01H

N

00H 01H 00H

Clear

8-bit timer counter H1

CMP01

TMHE1

INTTMH1

TOH1

Interval time

<1>

<2>

Level inversion,

<3>

<2>

Level inversion,

match interrupt occurrence,

8-bit timer counter H1 clear

match interrupt occurrence,

8-bit timer counter H1 clear

<1> The count operation is enabled by setting the TMHE1 bit to 1. The count clock starts counting no more than

1 clock after the operation is enabled.

<2> When the values of 8-bit timer counter H1 and the CMP01 register match, the value of 8-bit timer counter H1

is cleared, the TOH1 output level is inverted, and the INTTMH1 signal is output.

<3> The INTTMH1 signal and TOH1 output become inactive by clearing the TMHE1 bit to 0 during timer H1

operation. If these are inactive from the first, the level is retained.

Remark 01H ≤ N ≤ FEH

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Figure 8-7. Timing of Interval Timer/Square-Wave Output Operation (2/2)

(b) Operation when CMP01 = FFH

Count clock

Count start

00H

01H

FEH

FFH

00H

FEH

FFH

8-bit timer counter H1

Clear

FFH

CMP01

TMHE1

INTTMH1

TOH1

Interval time

(c) Operation when CMP01 = 00H

Count clock

Count start

00H

8-bit timer counter H1

CMP01

TMHE1

INTTMH1

TOH1

Interval time

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8.4.2 Operation as PWM output mode

In PWM output mode, a pulse with an arbitrary duty and arbitrary cycle can be output.

8-bit timer compare register 01 (CMP01) controls the cycle of timer output (TOH1). Rewriting the CMP01 register

during timer operation is prohibited.

8-bit timer compare register 11 (CMP11) controls the duty of timer output (TOH1). Rewriting the CMP11 register

during timer operation is possible.

The operation in PWM output mode is as follows.

TOH1 output becomes active and 8-bit timer counter H1 is cleared to 0 when 8-bit timer counter H1 and the

CMP01 register match after the timer count is started. TOH1 output becomes inactive when 8-bit timer counter H1

and the CMP11 register match.

(1) Usage

In PWM output mode, a pulse for which an arbitrary duty and arbitrary cycle can be set is output.

<1> Set each register.

Figure 8-8. Register Setting in PWM Output Mode

(i) Setting timer H mode register 1 (TMHMD1)

TMHE1

0

CKS12 CKS11

0/1 0/1

CKS10 TMMD11 TMMD10 TOLEV1 TOEN1

0/1 0/1

TMHMD1

1

0

1

Timer output enabled

Timer output level inversion setting

PWM output mode selection

Count clock (f^CNT) selection

Count operation stopped

(ii) Setting CMP01 register

• Compare value (N): Cycle setting

(iii) Setting CMP11 register

• Compare value (M): Duty setting

Remark 00H ≤ CMP11 (M) < CMP01 (N) ≤ FFH

<2> The count operation starts when TMHE1 = 1.

<3> The CMP01 register is the compare register that is to be compared first after count operation is enabled.

When the values of 8-bit timer counter H1 and the CMP01 register match, 8-bit timer counter H1 is cleared,

an interrupt request signal (INTTMH1) is generated, and TOH1 output becomes active. At the same time,

the compare register to be compared with 8-bit timer counter H1 is changed from the CMP01 register to the

CMP11 register.

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<4> When 8-bit timer counter H1 and the CMP11 register match, TOH1 output becomes inactive and the

compare register to be compared with 8-bit timer counter H1 is changed from the CMP11 register to the

CMP01 register. At this time, 8-bit timer counter H1 is not cleared and the INTTMH1 signal is not

generated.

<5> By performing procedures <3> and <4> repeatedly, a pulse with an arbitrary duty can be obtained.

<6> To stop the count operation, set TMHE1 = 0.

If the setting value of the CMP01 register is N, the setting value of the CMP11 register is M, and the count clock

frequency is f^CNT, the PWM pulse output cycle and duty are as follows.

PWM pulse output cycle = (N+1)/f^CNT

Duty = Active width : Total width of PWM = (M + 1) : (N + 1)

Cautions 1. In PWM output mode, the setting value for the CMP11 register can be changed during timer

count operation. However, three operation clocks (signal selected using the CKS12 to

CKS10 bits of the TMHMD1 register) or more are required to transfer the register value after

rewriting the CMP11 register value.

2. Be sure to set the CMP11 register when starting the timer count operation (TMHE1 = 1) after

the timer count operation was stopped (TMHE1 = 0) (be sure to set again even if setting the

same value to the CMP11 register).

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(2) Timing chart

The operation timing in PWM output mode is shown below.

Caution Make sure that the CMP11 register setting value (M) and CMP01 register setting value (N) are

within the following range.

00H ≤ CMP11 (M) < CMP01 (N) ≤ FFH

Figure 8-9. Operation Timing in PWM Output Mode (1/4)

(a) Basic operation (00H < CMP11 < CMP01 < FFH)

Count clock

00H 01H

A5H 00H 01H 02H

A5H 00H

8-bit timer counter H1

A5H

01H

CMP01

CMP11

TMHE1

INTTMH1

TOH1

(TOLEV1 = 0)

<4>

<2>

<3>

<1>

TOH1

(TOLEV1 = 1)

<1> The count operation is enabled by setting the TMHE1 bit to 1. Start 8-bit timer counter H1 by masking one

count clock to count up. At this time, TOH1 output remains inactive (when TOLEV1 = 0).

<2> When the values of 8-bit timer counter H1 and the CMP01 register match, the TOH1 output level is inverted,

the value of 8-bit timer counter H1 is cleared, and the INTTMH1 signal is output.

<3> When the values of 8-bit timer counter H1 and the CMP11 register match, the level of the TOH1 output is

returned. At this time, the 8-bit timer counter value is not cleared and the INTTMH1 signal is not output.

<4> Clearing the TMHE1 bit to 0 during timer H1 operation makes the INTTMH1 signal and TOH1 output inactive.

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Figure 8-9. Operation Timing in PWM Output Mode (2/4)

(b) Operation when CMP01 = FFH, CMP11 = 00H

Count clock

8-bit timer counter H1

00H 01H

FFH 00H 01H 02H

FFH 00H

FFH

00H

CMP01

CMP11

TMHE1

INTTMH1

TOH1

(TOLEV1 = 0)

(c) Operation when CMP01 = FFH, CMP11 = FEH

Count clock

00H 01H

FEH FFH 00H 01H

FEH FFH 00H

8-bit timer counter H1

FFH

FEH

CMP01

CMP11

TMHE1

INTTMH1

TOH1

(TOLEV1 = 0)

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Figure 8-9. Operation Timing in PWM Output Mode (3/4)

(d) Operation when CMP01 = 01H, CMP11 = 00H

Count clock

00H 01H 00H 01H 00H

00H 01H 00H 01H

8-bit timer counter H1

CMP01

01H

00H

CMP11

TMHE1

INTTMH1

TOH1

(TOLEV1 = 0)

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Figure 8-9. Operation Timing in PWM Output Mode (4/4)

(e) Operation by changing CMP11 (CMP11 = 02H → 03H, CMP01 = A5H)

Count clock

8-bit timer counter H1

00H 01H 02H

80H

A5H 00H 01H 02H 03H

A5H 00H

A5H

03H

CMP01

CMP11

02H

02H (03H)

<2>'

<2>

TMHE1

INTTMH1

TOH1

(TOLEV1 = 0)

<4>

<3>

<6>

<5>

<1>

<1> The count operation is enabled by setting TMHE1 = 1. Start 8-bit timer counter H1 by masking one count

clock to count up. At this time, the TOH1 output remains inactive (when TOLEV1 = 0).

<2> The CMP11 register value can be changed during timer counter operation. This operation is asynchronous

to the count clock.

<3> When the values of 8-bit timer counter H1 and the CMP01 register match, the value of 8-bit timer counter H1

is cleared, the TOH1 output becomes active, and the INTTMH1 signal is output.

<4> If the CMP11 register value is changed, the value is latched and not transferred to the register. When the

values of 8-bit timer counter H1 and the CMP11 register before the change match, the value is transferred to

the CMP11 register and the CMP11 register value is changed (<2>’).

However, three count clocks or more are required from when the CMP11 register value is changed to when

the value is transferred to the register. If a match signal is generated within three count clocks, the changed

value cannot be transferred to the register.

<5> When the values of 8-bit timer counter H1 and the CMP11 register after the change match, the TOH1 output

becomes inactive. 8-bit timer counter H1 is not cleared and the INTTMH1 signal is not generated.

<6> Clearing the TMHE1 bit to 0 during timer H1 operation makes the INTTMH1 signal and TOH1 output inactive.

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CHAPTER 9 WATCHDOG TIMER

9.1 Functions of Watchdog Timer

The watchdog timer is used to detect an inadvertent program loop. If a program loop is detected, an internal reset

signal is generated.

When a reset occurs due to the watchdog timer, bit 4 (WDTRF) of the reset control flag register (RESF) is set to 1.

For details of RESF, see CHAPTER 15 RESET FUNCTION.

Table 9-1. Loop Detection Time of Watchdog Timer

Loop Detection Time

During Low-Speed Internal Oscillation Clock

Operation

During System Clock Operation

2¹¹/fRL (4.27 ms)

2¹³/fX (819.2 μs)

2¹²/fRL (8.53 ms)

2¹⁴/fX (1.64 ms)

2¹⁵/fX (3.28 ms)

2¹⁶/fX (6.55 ms)

2¹⁷/fX (13.11 ms)

2¹⁸/fX (26.21 ms)

2¹⁹/fX (52.43 ms)

2²⁰/fX (104.86 ms)

2¹³/fRL (17.07 ms)

2¹⁴/fRL (34.13 ms)

2¹⁵/fRL (68.27 ms)

2¹⁶/fRL (136.53 ms)

2¹⁷/fRL (273.07 ms)

2¹⁸/fRL (546.13 ms)

Remarks 1. fRL: Low-speed internal oscillation clock frequency

2. f^X: System clock oscillation frequency

3. Figures in parentheses apply to operation at fRL = 480 kHz (MAX.), fX = 10 MHz.

The operation mode of the watchdog timer (WDT) is switched according to the option byte setting of the on-chip

low-speed internal oscillator as shown in Table 9-2.

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Table 9-2. Option Byte Setting and Watchdog Timer Operation Mode

Option Byte Setting

Low-Speed Internal Oscillator Cannot Be Stopped

Low-Speed Internal Oscillator Can Be Stopped

by Software

Note 1

Watchdog timer clock

source

Fixed to f^RL

.

• Selectable by software (f^X, fRL or stopped)

• When reset is released: f^RL

Operation after reset

Operation starts with the maximum interval (2¹⁸/fRL). Operation starts with the maximum interval

(2¹⁸/fRL).

Operation mode

selection

The interval can be changed only once.

The clock selection/interval can be changed only

once.

Features

The watchdog timer cannot be stopped.

The watchdog timer can be stopped^{Note 2}

.

Notes 1. As long as power is being supplied, low-speed internal oscillator cannot be stopped (except in the reset

period).

2. The conditions under which clock supply to the watchdog timer is stopped differ depending on the

clock source of the watchdog timer.

<1> If the clock source is f^X, clock supply to the watchdog timer is stopped under the following

conditions.

• When f^Xis stopped

• In HALT/STOP mode

• During oscillation stabilization time

<2> If the clock source is f^RL, clock supply to the watchdog timer is stopped under the following

conditions.

• If the CPU clock is f^Xand if fRL is stopped by software before execution of the STOP instruction

• In HALT/STOP mode

Remarks 1. f^RL: Low-speed internal oscillation clock frequency

2. f^X: System clock oscillation frequency

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9.2 Configuration of Watchdog Timer

The watchdog timer consists of the following hardware.

Table 9-3. Configuration of Watchdog Timer

Item

Configuration

Control registers

Watchdog timer mode register (WDTM)

Watchdog timer enable register (WDTE)

Figure 9-1. Block Diagram of Watchdog Timer

2¹¹/fRL to

2¹⁸/fRL

Clock

input

controller

f

RL/2²

Output

controller

16-bit

counter

Internal reset signal

Selector

f

/2⁴

X

or

2¹³/f

2²⁰/f

X

to

2

3

Clear

Option byte

(to set “low-speed

internal oscillator cannot be

stopped” or “low-speed

internal oscillator can be

stopped by software”)

0

1

WDCS4 WDCS3 WDCS2 WDCS1 WDCS0

Watchdog timer enable

register (WDTE)

Watchdog timer mode

register (WDTM)

Internal bus

Remarks 1. f^RL: Low-speed internal oscillation clock frequency

2. f^X: System clock oscillation frequency

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9.3 Registers Controlling Watchdog Timer

The watchdog timer is controlled by the following two registers.

•

Watchdog timer mode register (WDTM)

Watchdog timer enable register (WDTE)

(1) Watchdog timer mode register (WDTM)

This register sets the overflow time and operation clock of the watchdog timer.

This register can be set by an 8-bit memory manipulation instruction and can be read many times, but can be

written only once after reset is released.

Generation of reset signal sets this register to 67H.

Figure 9-2. Format of Watchdog Timer Mode Register (WDTM)

Address: FF48H After reset: 67H R/W

7

0

6

1

5

1

4

3

2

1

0

Symbol

WDTM

WDCS4

WDCS3

WDCS2

WDCS1

WDCS0

WDCS4^{Note 1}WDCS3^{Note 1}

Operation clock selection

0

1

0

1

×

Low-speed internal oscillation clock (fRL)

System Clock (fX)

Watchdog timer operation stopped

WDCS2^{Note 2}WDCS1^{Note 2}WDCS0^{Note 2}

Overflow time setting

During low-speed internal

oscillation clock operation

During system clock operation

0

1

0

1

0

1

0

1

0

1

0

1

0

1

2¹¹/fRL (4.27 ms)

2¹²/fRL (8.53 ms)

2¹³/fRL (17.07 ms)

2¹⁴/fRL (34.13 ms)

2¹⁵/fRL (68.27 ms)

2¹⁶/fRL (136.53 ms)

2¹⁷/fRL (273.07 ms)

2¹⁸/fRL (546.13 ms)

2¹³/fX (819.2 μs)

2¹⁴/fX (1.64 ms)

2¹⁵/fX (3.28 ms)

2¹⁶/fX (6.55 ms)

2¹⁷/fX (13.11 ms)

2¹⁸/fX (26.21 ms)

2¹⁹/fX (52.43 ms)

2²⁰/fX (104.86 ms)

Notes 1. If “low-speed internal oscillator cannot be stopped” is specified by the option byte, this cannot

be set. The low-speed internal oscillation clock will be selected no matter what value is

written.

2. Reset is released at the maximum cycle (WDCS2, 1, 0 = 1, 1, 1).

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Cautions 1. Set bits 7, 6, and 5 to 0, 1, and 1, respectively. Do not set the other values.

2. After reset is released, WDTM can be written only once by an 8-bit memory

manipulation instruction. If writing is attempted a second time, an internal reset

signal is generated. However, at the first write, if “1” and “x” are set for WDCS4 and

WDCS3 respectively and the watchdog timer is stopped, then the internal reset

signal does not occur even if the following are executed.

• Second write to WDTM

• 1-bit memory manipulation instruction to WDTE

• Writing of a value other than “ACH” to WDTE

3. WDTM cannot be set by a 1-bit memory manipulation instruction.

4. When using the flash memory programming by self programming, set the overflow

time for the watchdog timer so that enough overflow time is secured (Example 1-

byte writing: 200 μs MIN., 1-block deletion: 10 ms MIN.).

Remarks 1. f^RL: Low-speed internal oscillation clock frequency

2. f^X: System clock oscillation frequency

3. ×: Don’t care

4. Figures in parentheses apply to operation at f^RL= 480 kHz (MAX.), fX = 10 MHz.

(2) Watchdog timer enable register (WDTE)

Writing ACH to WDTE clears the watchdog timer counter and starts counting again.

This register can be set by an 8-bit memory manipulation instruction.

Generation of reset signal sets this register to 9AH.

Figure 9-3. Format of Watchdog Timer Enable Register (WDTE)

Address: FF49H After reset: 9AH R/W

7

6

5

4

3

2

1

0

Symbol

WDTE

Cautions 1. If a value other than ACH is written to WDTE, an internal reset signal is generated.

2. If a 1-bit memory manipulation instruction is executed for WDTE, an internal reset

signal is generated.

3. The value read from WDTE is 9AH (this differs from the written value (ACH)).

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9.4 Operation of Watchdog Timer

9.4.1 Watchdog timer operation when “low-speed internal oscillator cannot be stopped” is selected by

option byte

The operation clock of watchdog timer is fixed to low-speed internal oscillation clock.

After reset is released, operation is started at the maximum cycle (bits 2, 1, and 0 (WDCS2, WDCS1, WDCS0) of

the watchdog timer mode register (WDTM) = 1, 1, 1). The watchdog timer operation cannot be stopped.

The following shows the watchdog timer operation after reset release.

1. The status after reset release is as follows.

•

Operation clock: Low-speed internal oscillation clock

Cycle: 2¹⁸/fRL (546.13 ms: operation with fRL = 480 kHz (MAX.))

Counting starts

2. The following should be set in the watchdog timer mode register (WDTM) by an 8-bit memory manipulation

instruction^{Notes 1, 2}

Cycle: Set using bits 2 to 0 (WDCS2 to WDCS0)

.

•

3. After the above procedures are executed, writing ACH to WDTE clears the count to 0, enabling recounting.

Notes 1. The operation clock (low-speed internal oscillation clock) cannot be changed. If any value is written to

bits 3 and 4 (WDCS3, WDCS4) of WDTM, it is ignored.

2. As soon as WDTM is written, the counter of the watchdog timer is cleared.

Caution In this mode, operation of the watchdog timer cannot be stopped even during STOP instruction

execution. For 8-bit timer H1 (TMH1), a division of the low-speed internal oscillation clock can be

selected as the count source, so clear the watchdog timer using the interrupt request of TMH1

before the watchdog timer overflows after STOP instruction execution. If this processing is not

performed, an internal reset signal is generated when the watchdog timer overflows after STOP

instruction execution.

A status transition diagram is shown below

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Figure 9-4. Status Transition Diagram When “Low-Speed Internal Oscillator Cannot Be Stopped”

Is Selected by Option Byte

Reset

WDT clock: f^RL

Overflow time: 546.13 ms (MAX.)

WDTE = “ACH”

Clear WDT counter.

WDT clock is fixed to f^RL

.

Select overflow time (settable only once).

WDT clock: fRL

Overflow time: 4.27 ms to 546.13 ms (MAX.)

WDT count continues.

HALT instruction

STOP instruction

Interrupt

HALT

WDT count continues.

STOP

WDT count continues.

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9.4.2 Watchdog timer operation when “low-speed internal oscillator can be stopped by software” is

selected by option byte

The operation clock of the watchdog timer can be selected as either the low-speed internal oscillation clock or the

system clock.

After reset is released, operation is started at the maximum cycle of the low-speed internal oscillation clock (bits 2,

1, and 0 (WDCS2, WDCS1, WDCS0) of the watchdog timer mode register (WDTM) = 1, 1, 1).

The following shows the watchdog timer operation after reset release.

1. The status after reset release is as follows.

•

Operation clock: Low-speed internal oscillation clock

Cycle: 2¹⁸/fRL (546.13 ms: operation with fRL = 480 kHz (MAX.))

Counting starts

2. The following should be set in the watchdog timer mode register (WDTM) by an 8-bit memory manipulation

instruction^{Notes 1, 2, 3}

.

•

Operation clock: Any of the following can be selected using bits 3 and 4 (WDCS3 and WDCS4).

Low-speed internal oscillation clock (f^RL)

System clock (fX)

Watchdog timer operation stopped

Cycle: Set using bits 2 to 0 (WDCS2 to WDCS0)

•

3. After the above procedures are executed, writing ACH to WDTE clears the count to 0, enabling recounting.

Notes 1. As soon as WDTM is written, the counter of the watchdog timer is cleared.

2. Set bits 7, 6, and 5 to 0, 1, 1, respectively. Do not set the other values.

3. At the first write, if the watchdog timer is stopped by setting WDCS4 and WDCS3 to 1 and ×,

respectively, an internal reset signal is not generated even if the following processing is performed.

•

WDTM is written a second time.

A 1-bit memory manipulation instruction is executed to WDTE.

A value other than ACH is written to WDTE.

Caution In this mode, watchdog timer operation is stopped during HALT/STOP instruction execution.

After HALT/STOP mode is released, counting is started again using the operation clock of the

watchdog timer set before HALT/STOP instruction execution by WDTM. At this time, the counter

is not cleared to 0 but holds its value.

For the watchdog timer operation during STOP mode and HALT mode in each status, see 9.4.3 Watchdog timer

operation in STOP mode (when “low-speed internal oscillator can be stopped by software” is selected by

option byte) and 9.4.4 Watchdog timer operation in HALT mode (when “low-speed internal oscillator can be

stopped by software” is selected by option byte).

A status transition diagram is shown below.

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Figure 9-5. Status Transition Diagram When “Low-Speed Internal Oscillator Can Be Stopped by

Software” Is Selected by Option Byte

Reset

WDT clock: f^RL

Overflow time: 546.13 ms (MAX.)

WDCS4 = 1

WDT clock = f

X

Select overflow time

(settable only once).

WDT clock = fRL

Select overflow time

(settable only once).

WDT operation stops.

WDTE = “ACH”

Clear WDT counter.

WDTE = “ACH”

Clear WDT counter.

WDTE = “ACH”

Clear WDT counter.

LSRSTOP = 1

LSRSTOP = 0

WDT clock: f

Overflow time: 2¹³/f

WDT count continues.

X

WDT clock: fRL

Overflow time: 4.27 ms to 546.13 ms (MAX.)

WDT count continues.

to 2²⁰/f

X

WDT clock: fRL

WDT count stops.

X

HALT instruction

HALT

instruction

Interrupt

STOP

instruction

STOP

instruction

HALT

instruction

Interrupt

HALT

WDT count stops.

STOP

WDT count stops.

HALT

WDT count stops.

STOP

WDT count stops.

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9.4.3

Watchdog timer operation in STOP mode (when “low-speed internal oscillator can be stopped by

software” is selected by option byte)

The watchdog timer stops counting during STOP instruction execution regardless of whether the system clock or

low-speed internal oscillation clock is being used.

(1) When the watchdog timer operation clock is the clock to peripheral hardware (f^X) when the STOP

instruction is executed

When STOP instruction is executed, operation of the watchdog timer is stopped. After STOP mode is released,

operation stops for 34 μs (TYP.) (after waiting for the oscillation stabilization time set by the oscillation

stabilization time select register (OSTS) after operation stops in the case of crystal/ceramic oscillation) and then

counting is started again using the operation clock before the operation was stopped. At this time, the counter is

not cleared to 0 but holds its value.

Figure 9-6. Operation in STOP Mode (WDT Operation Clock: Clock to Peripheral Hardware)

<1> CPU clock: Crystal/ceramic oscillation clock

Operation

Normal

operation

stopped^NoteOscillation stabilization time

Normal operation

STOP

CPU operation

f

CPU

Oscillation stabilization time

(set by OSTS register)

Oscillation stopped

Watchdog timer

Operating

Operation stopped

Operating

<2> CPU clock: High-speed internal oscillation clock or external clock input

Normal

operation

Operation

stopped^Note

Normal operation

STOP

CPU operation

fCPU

Oscillation stopped

Operation stopped

Watchdog timer

Operating

Note The operation stop time is 17 μs (MIN.), 34 μs (TYP.), and 67 μs (MAX.).

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(2) When the watchdog timer operation clock is the low-speed internal oscillation clock (fRL) when the STOP

instruction is executed

When the STOP instruction is executed, operation of the watchdog timer is stopped. After STOP mode is

released, operation stops for 34 μs (TYP.) and then counting is started again using the operation clock before the

operation was stopped. At this time, the counter is not cleared to 0 but holds its value.

Figure 9-7. Operation in STOP Mode (WDT Operation Clock: Low-Speed Internal Oscillation Clock)

<1> CPU clock: Crystal/ceramic oscillation clock

Operation

Normal

operation

stopped^Note

STOP

Oscillation stabilization time

Normal operation

CPU operation

fCPU

Oscillation stabilization time

(set by OSTS register)

Oscillation stopped

f

RL

Watchdog timer

Operating

Operation stopped

Operating

<2> CPU clock: High-speed internal oscillation clock or external clock input

Operation

Normal

operation

stopped^Note

CPU operation

STOP

Normal operation

fCPU

Oscillation stopped

fRL

Watchdog timer

Operating

Operation stopped

Operating

Note The operation stop time is 17 μs (MIN.), 34 μs (TYP.), and 67 μs (MAX.).

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9.4.4

Watchdog timer operation in HALT mode (when “low-speed internal oscillator can be stopped by

software” is selected by option byte)

The watchdog timer stops counting during HALT instruction execution regardless of whether the operation clock of

the watchdog timer is the system clock (f^X) or low-speed internal oscillation clock (fRL). After HALT mode is released,

counting is started again using the operation clock before the operation was stopped. At this time, the counter is not

cleared to 0 but holds its value.

Figure 9-8. Operation in HALT Mode

Normal operation

HALT

Normal operation

CPU operation

fCPU

fX or fRL

Watchdog timer

Operating Operation stopped

Operating

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CHAPTER 10 A/D CONVERTER

10.1 Functions of A/D Converter

The A/D converter converts an analog input signal into a digital value, and consists of up to four channels (ANI0 to

ANI3) with a resolution of 10 bits.

The A/D converter has the following function.

•

10-bit resolution A/D conversion

10-bit resolution A/D conversion is carried out repeatedly for one channel selected from analog inputs ANI0 to

ANI3. Each time an A/D conversion operation ends, an interrupt request (INTAD) is generated.

Figure 10-1 shows the timing of sampling and A/D conversion, and Table 10-1 shows the sampling time and A/D

conversion time.

Figure 10-1. Timing of A/D Converter Sampling and A/D Conversion

ADCS ← 1 or ADS rewrite

ADCS

Sampling

timing

INTAD

Note Sampling

Sampling

time

Conversion time

Note 2 or 3 clocks are required from the ADCS rising to sampling start.

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Table 10-1. Sampling Time and A/D Conversion Time

Reference

Voltage

Range^{Note 1}

Sampling

Time^{Note 2}

Conversion

Time^{Note 3}

fXP = 8 MHz

fXP = 10 MHz

FR2

FR1

FR0

Sampling

Time^{Note 2}

Conversion

Time^{Note 3}

4.5 μs

Sampling

Time^{Note 2}

1.2 μs

Conversion

Time^{Note 3}

3.6 μs

AVREF ≥ 4.5 V

AVREF ≥ 4.0 V

AVREF ≥ 2.85 V

12/fXP

24/fXP

96/fXP

48/fXP

24/f^XP

36/fXP

72/fXP

144/fXP

96/fXP

72/fXP

48/fXP

1.5 μs

0

1

0

1

0

1

0

1

0

1

3.0 μs

9.0 μs

2.4 μs

9.6 μs

4.8 μs

Setting

7.2 μs

12.0 μs

6.0 μs

18.0 μs

12.0 μs

9.0 μs

14.4 μs

9.6 μs

6.0 μs

7.2 μs

3.0 μs

6.0 μs

Setting

prohibited

Note 4

(2.4 μs)

17.6 μs

Setting

(4.8 μs)

22.4 μs

Setting

AVREF ≥ 2.7 V

176/fXP

88/f^XP

224/fXP

112/fXP

22.0 μs

11.0 μs

28.0 μs

14.0 μs

1

0

1

prohibited

Note 4

(8.8 μs)

(11.2 μs)

Notes 1. Be sure to set the FR2, FR1, and FR0, in accordance with the reference voltage so that Notes 2 and 3

below are satisfied.

Example When AV^REF≥ 2.7 V, fXP = 8 MHz

• The sampling time is 11.0 μs or more and the A/D conversion time is 14.0 μs or more and 100 μs or

less.

• Set FR2, FR1, and FR0 = 0, 1, 1 or 1, 1, 1.

2. Set the sampling time as follows.

• AV^REF≥ 4.5 V: 1.0 μs or more

• AVREF ≥ 4.0 V: 2.4 μs or more

• AV^REF≥ 2.85 V: 3.0 μs or more

• AV^REF≥ 2.7 V: 11.0 μs or more

3. Set the A/D conversion time as follows.

• AV^REF≥ 4.5 V: 3.0 μs or more and less than 100 μs

• AV^REF≥ 4.0 V: 4.8 μs or more and less than 100 μs

• AVREF ≥ 2.85 V: 6.0 μs or more and less than 100 μs

• AV^REF≥ 2.7 V: 14.0 μs or more and less than 100 μs

4. Setting is prohibited because the values do not satisfy the condition of Notes 2 or 3.

Caution The above sampling time and conversion time do not include the clock frequency error. Select the

sampling time and conversion time such that Notes 2 and 3 above are satisfied, while taking the

clock frequency error into consideration (an error margin maximum of 5% when using the high-

speed internal oscillator).

Remarks 1. f^XP: Oscillation frequency of clock to peripheral hardware

2. The conversion time refers to the total of the sampling time and the time from successively comparing

with the sampling value until the conversion result is output.

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Figure 10-2 shows the block diagram of A/D converter.

Figure 10-2. Block Diagram of A/D Converter

ANI0/P20

ANI1/P21

ANI2/P22

Sample & hold circuit

Voltage comparator

AVREF

AVSS

D/A converter

AVSS

ANI3/P23

Successive

approximation

register (SAR)

INTAD

Controller

A/D conversion result register

(ADCR, ADCRH)

2

3

ADS1 ADS0

ADCS

FR2

FR1

FR0

ADCE

Analog input

channel specification

register (ADS)

A/D converter mode

register (ADM)

Internal bus

10.2 Configuration of A/D Converter

The A/D converter consists of the following hardware.

(1) ANI0 to ANI3 pins

These are the analog input pins of the 4-channel A/D converter. They input analog signals to be converted into

digital signals. Pins other than the one selected as the analog input pin by the analog input channel specification

register (ADS) can be used as I/O port pins.

(2) Sample & hold circuit

The sample & hold circuit samples the input signal of the analog input pin selected by the selector when A/D

conversion is started, and holds the sampled analog input voltage value during A/D conversion.

(3) D/A converter

The D/A converter is connected between AV^REFand AVSS, and generates a voltage to be compared with the

analog input signal.

(4) Voltage comparator

The voltage comparator compares the sampled analog input voltage and the output voltage of the D/A converter.

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(5) Successive approximation register (SAR)

This register compares the sampled analog voltage and the voltage of the D/A converter, and converts the result,

starting from the most significant bit (MSB).

When the voltage value is converted into a digital value down to the least significant bit (LSB) (end of A/D

conversion), the contents of the SAR register are transferred to the A/D conversion result register (ADCR).

(6) 10-bit A/D conversion result register (ADCR)

The result of A/D conversion is loaded from the successive approximation register to this register each time A/D

conversion is completed, and the ADCR register holds the result of A/D conversion in its lower 10 bits (the higher

6 bits are fixed to 0).

(7) 8-bit A/D conversion result register (ADCRH)

The result of A/D conversion is loaded from the successive approximation register to this register each time A/D

conversion is completed, and the ADCRH register holds the result of A/D conversion in its higher 8 bits.

(8) Controller

When A/D conversion has been completed, INTAD is generated.

(9) AV^REFpin

This pin inputs an analog power/reference voltage to the A/D converter. When the A/D converter is not used,

connect this pin to V^DD.

The signal input to ANI0 to ANI3 is converted into a digital signal, based on the voltage applied across AV^REFand

AV^SS.

(10) AV^SSpin

This is the ground potential pin of the A/D converter. Always use this pin at the same potential as that of the V^SS

pin even when the A/D converter is not used.

(11) A/D converter mode register (ADM)

This register is used to set the conversion time of the analog input signal to be converted, and to start or stop the

conversion operation.

(12) Analog input channel specification register (ADS)

This register is used to specify the port that inputs the analog voltage to be converted into a digital signal.

(13) Port mode control register 2 (PMC2)

This register is used when the P20/ANI0 to P23/ANI3 pins are used as the analog input pins of the A/D converter.

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10.3 Registers Used by A/D Converter

The A/D converter uses the following six registers.

•

A/D converter mode register (ADM)

Analog input channel specification register (ADS)

10-bit A/D conversion result register (ADCR)

8-bit A/D conversion result register (ADCRH)

Port mode control register 2 (PMC2)

Port mode register 2 (PM2)

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(1) A/D converter mode register (ADM)

This register sets the conversion time for analog input to be A/D converted, and starts/stops conversion.

ADM can be set by a 1-bit or 8-bit memory manipulation instruction.

Reset signal generation clears this register to 00H.

Figure 10-3. Format of A/D Converter Mode Register (ADM)

Address: FF80H After reset: 00H R/W

Symbol

ADM

<7>

6

0

5

4

3

2

0

1

0

<0>

ADCS

FR2

FR1

FR0

ADCE

ADCS

0

1^{Note 1}

A/D conversion operation control

Stops conversion operation

Starts conversion operation

FR2

FR1

FR0

Reference Sampling Conversion

fXP = 8 MHz

fXP = 10 MHz

Voltage

Time^{Note 3}Time^{Note 4}

Sampling Conversion Sampling Conversion

Time^{Note 3}Time^{Note 4}Time^{Note 3}Time^{Note 4}

Range^{Note 2}

0

1

0

AVREF ≥ 12/fXP

4.5 V

36/fXP

72/fXP

1.5 μs

4.5 μs

1.2 μs

3.6 μs

AVREF ≥ 24/fXP

3.0 μs

9.0 μs

2.4 μs

7.2 μs

4.0 V

1

0

1

0

1

0

1

0

1

AVREF ≥ 96/fXP

144/fXP

96/fXP

72/fXP

48/fXP

12.0 μs

6.0 μs

3.0 μs

18.0 μs

12.0 μs

9.0 μs

9.6 μs

4.8 μs

Setting

14.4 μs

9.6 μs

7.2 μs

Setting

2.85 V

48/fXP

24/f^XP

6.0 μs

prohibited prohibited

Note 5

(2.4 μs) (4.8 μs)

1

0

1

AVREF ≥ 176/fXP

224/fXP

112/fXP

22.0 μs

11.0 μs

28.0 μs

14.0 μs

17.6 μs

22.4 μs

2.7 V

88/fXP

Setting

prohibited prohibited

Note 5

(8.8 μs) (11.2 μs)

ADCE

0^{Note 1}

1

Comparator operation control^{Note 6}

Stops operation of comparator

Enables operation of comparator

Remarks 1. fXP: Oscillation frequency of clock to peripheral hardware

2. The conversion time refers to the total of the sampling time and the time from successively

comparing with the sampling value until the conversion result is output.

Note 1. Even when the ADCE = 0 (comparator operation stopped), the A/D conversion operation starts if

the ADCS is set to 1. However, the first conversion data is out of the guaranteed-value range, so

ignore it.

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Notes 2. Be sure to set the FR2, FR1, and FR0, in accordance with the reference voltage so that Notes 3

and 4 below are satisfied.

Example When AV^REF≥ 2.7 V, fXP = 8 MHz

• The sampling time is 11.0 μs or more and the A/D conversion time is 14.0 μs or

more and 100 μs or less.

• Set FR2, FR1, and FR0 = 0, 1, 1 or 1, 1, 1.

3. Set the sampling time as follows.

• AV^REF≥ 4.5 V: 1.0 μs or more

• AVREF ≥ 4.0 V: 2.4 μs or more

• AV^REF≥ 2.85 V: 3.0 μs or more

• AV^REF≥ 2.7 V: 11.0 μs or more

4. Set the A/D conversion time as follows.

• AV^REF≥ 4.5 V: 3.0 μs or more and less than 100 μs

• AV^REF≥ 4.0 V: 4.8 μs or more and less than 100 μs

• AVREF ≥ 2.85 V: 6.0 μs or more and less than 100 μs

• AV^REF≥ 2.7 V: 14.0 μs or more and less than 100 μs

5. Setting is prohibited because the values do not satisfy the condition of Notes 3 or 4.

6. The operation of the comparator is controlled by ADCS and ADCE, and it takes 1 μs from

operation start to operation stabilization. Therefore, when ADCS is set to 1 after 1 μs or more

has elapsed from the time ADCE is set to 1, the conversion result at that time has priority over

the first conversion result. If the ADCS is set to 1 without waiting for 1 μs or longer, ignore the

first conversion data.

Table 10-2. Settings of ADCS and ADCE

ADCS

ADCE

A/D Conversion Operation

Stop status (DC power consumption path does not exist)

Conversion waiting mode (only comparator consumes power)

Conversion mode

0

1

0

1

×

Figure 10-4. Timing Chart When Comparator Is Used

Comparator operating

ADCE

Comparator

ADCS

Conversion

operation

Conversion

waiting

Conversion

operation

Conversion stopped

Note

Note The time from the rising of the ADCE bit to the rising of the ADCS bit must be 1 μs or

longer to stabilize the internal circuit.

Caution 1. The above sampling time and conversion time do not include the clock frequency error.

Select the sampling time and conversion time such that Notes 3 and 4 above are satisfied,

while taking the clock frequency error into consideration (an error margin maximum of 5%

when using the high-speed internal oscillator).

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Cautions 2. If a bit other than ADCS of ADM is manipulated while A/D conversion is stopped (ADCS = 0)

and then A/D conversion is started, execute two NOP instructions or an instruction

equivalent to two machine cycles, and set ADCS to 1.

3. A/D conversion must be stopped (ADCS = 0) before rewriting bits FR0 to FR2.

4. Be sure to clear bits 6, 2, and 1 to 0.

(2) Analog input channel specification register (ADS)

This register specifies the input port of the analog voltage to be A/D converted.

ADS can be set by a 1-bit or 8-bit memory manipulation instruction.

Reset signal generation clears this register to 00H.

Figure 10-5. Format of Analog Input Channel Specification Register (ADS)

Address: FF81H After reset: 00H R/W

Symbol

ADS

7

0

6

0

5

0

4

0

3

0

2

0

1

0

ADS1

ADS0

ADS1 ADS0

Analog input channel specification

0

1

0

1

0

1

ANI0

ANI1

ANI2

ANI3

Caution Be sure to clear bits 2 to 7 of ADS to 0.

(3) 10-bit A/D conversion result register (ADCR)

This register is a 16-bit register that stores the A/D conversion result. The higher six bits are fixed to 0. Each

time A/D conversion ends, the conversion result is loaded from the successive approximation register, and is

stored in ADCR in order starting from bit 1 of FF19H. FF19H indicates the higher 2 bits of the conversion result,

and FF18H indicates the lower 8 bits of the conversion result.

ADCR can be read by a 16-bit memory manipulation instruction.

Reset signal generation makes ADCR undefined.

Figure 10-6. Format of 10-bit A/D Conversion Result Register (ADCR)

Address: FF18H, FF19H After reset: Undefined

FF19H

R

FF18H

Symbol

ADCR

0

Caution When writing to the A/D converter mode register (ADM) and analog input channel specification

register (ADS), the contents of ADCR may become undefined. Read the conversion result

following conversion completion before writing to ADM and ADS. Using timing other than the

above may cause an incorrect conversion result to be read.

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(4) 8-bit A/D conversion result register (ADCRH)

This register is an 8-bit register that stores the A/D conversion result. It stores the higher 8 bits of a 10-bit

resolution result.

ADCRH can be read by an 8-bit memory manipulation instruction.

Reset signal generation makes ADCRH undefined.

Figure 10-7. Format of 8-bit A/D Conversion Result Register (ADCRH)

Address: FF1AH After reset: Undefined

R

Symbol

ADCRH

7

6

5

4

3

2

1

0

(5) Port mode control register 2 (PMC2) and port mode register 2 (PM2)

When using the P20/ANI0 to P23/ANI3 pins for analog input, set PMC20 to PMC23 and PM20 to PM23 to 1. At

this time, the output latches of P20 to P23 may be 0 or 1.

PMC2 and PM2 are set by a 1-bit or 8-bit memory manipulation instruction.

Reset signal generation clears PMC2 to 00H and sets PM2 to FFH.

Figure 10-8. Format of Port Mode Control Register 2 (PMC2)

Address: FF84H After reset: 00H R/W

Symbol

PMC2

7

0

6

0

5

0

4

0

3

2

1

0

PMC23

PMC22

PMC21

PMC20

PMC2n

Operation mode specification (n = 0 to 3)

0

1

Port mode

A/D converter mode

Caution When PMC20 to PMC23 are set to 1, the P20/ANI0 to P23/ANI3 pins cannot be used as port

pins. Be sure to set the pull-up resistor option registers (PU20 to PU23) to 0 for the pins

set to A/D converter mode.

Figure 10-9. Format of Port Mode Register 2 (PM2)

Address: FF22H After reset: FFH R/W

Symbol

PM2

7

1

6

1

5

1

4

1

3

2

1

0

PM23

PM22

PM21

PM20

PM2n

Pmn pin I/O mode selection (n = 0 to 3)

0

1

Output mode (output buffer on)

Input mode (output buffer off)

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10.4 A/D Converter Operations

10.4.1 Basic operations of A/D converter

<1> Set ADCE to 1.

<2> Select one channel for A/D conversion using the analog input channel specification register (ADS), and

select the conversion time using FR2 to FR0.

<3> Execute two NOP instructions or an instruction equivalent to two machine cycles.

<4> Set ADCS to 1 and start the conversion operation.

(<5> to <11> are operations performed by hardware.)

<5> The voltage input to the selected analog input channel is sampled by the sample & hold circuit.

<6> When sampling has been done for a certain time, the sample & hold circuit is placed in the hold state and the

input analog voltage is held until the A/D conversion operation has ended.

<7> Bit 9 of the successive approximation register (SAR) is set. The D/A converter voltage tap is set to (1/2)

AV^REFby the tap selector.

<8> The voltage difference between the D/A converter voltage tap and analog input is compared by the voltage

comparator. If the analog input is greater than (1/2) AV^REF, the MSB of SAR remains set to 1. If the analog

input is smaller than (1/2) AVREF, the MSB is reset to 0.

<9> Next, bit 8 of SAR is automatically set to 1, and the operation proceeds to the next comparison. The D/A

converter voltage tap is selected according to the preset value of bit 9, as described below.

•

Bit 9 = 1: (3/4) AV^REF

Bit 9 = 0: (1/4) AV^REF

The voltage tap and analog input voltage are compared and bit 8 of SAR is manipulated as follows.

•

Analog input voltage ≥ Voltage tap: Bit 8 = 1

Analog input voltage < Voltage tap: Bit 8 = 0

<10> Comparison is continued in this way up to bit 0 of SAR.

<11> Upon completion of the comparison of 10 bits, an effective digital result value remains in SAR, and the result

value is transferred to the A/D conversion result register (ADCR, ADCRH) and then latched.

At the same time, the A/D conversion end interrupt request (INTAD) can also be generated.

<12> Repeat steps <5> to <11>, until ADCS is cleared to 0.

To stop the A/D converter, clear ADCS to 0.

To restart A/D conversion from the status of ADCE = 1, start from <3>. To restart A/D conversion from the

status of ADCE = 0, however, start from <1> (when not changing the channel and conversion time, skip step

<2>).

Cautions 1. Make sure the period of <1> to <4> is 1 μs or more.

2. It is no problem if the order of <1> and <2> is reversed.

Remark The following two types of A/D conversion result registers can be used.

• ADCR (16 bits):

• ADCRH (8 bits):

Stores a 10-bit A/D conversion value.

Stores an 8-bit A/D conversion value.

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Figure 10-10. Basic Operation of A/D Converter

Conversion time

Sampling time

Sampling

A/D converter

operation

A/D conversion

Conversion

result

Undefined

SAR

ADCR,

ADCRH

Conversion

result

INTAD

A/D conversion operations are performed continuously until bit 7 (ADCS) of the A/D converter mode register (ADM)

is reset (0) by software.

If a write operation is performed to ADM or the analog input channel specification register (ADS) during an A/D

conversion operation, the conversion operation is initialized, and if the ADCS bit is set (1), conversion starts again

from the beginning.

Reset input makes the A/D conversion result register (ADCR, ADCRH) undefined.

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10.4.2 Input voltage and conversion results

The relationship between the analog input voltage input to the analog input pins (ANI0 to ANI3) and the theoretical

A/D conversion result (stored in the 10-bit A/D conversion result register (ADCR)) is shown by the following

expression.

V^AIN

ADCR = INT (

× 1024 + 0.5)

AV^REF

or

AVREF

(ADCR − 0.5) ×

≤ V^AIN< (ADCR + 0.5) ×

1024

where, INT( ): Function which returns integer part of value in parentheses

V^AIN: Analog input voltage

AVREF: AVREF pin voltage

ADCR: 10-bit A/D conversion result register (ADCR) value

Figure 10-11 shows the relationship between the analog input voltage and the A/D conversion result.

Figure 10-11. Relationship Between Analog Input Voltage and A/D Conversion Result

SAR

ADCR

1023

03FFH

1022

03FEH

03FDH

0003H

0002H

0001H

0000H

1021

A/D conversion result

3

2

1

0

1

3

2

5

3

2043 1022 2045 1023 2047

2048 1024 2048 1024 2048

1

2048 1024 2048 1024 2048 1024

Input voltage/AV_REF

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10.4.3 A/D converter operation mode

The operation mode of the A/D converter is the select mode. One channel of analog input is selected from ANI0 to

ANI3 by the analog input channel specification register (ADS) and A/D conversion is executed.

(1) A/D conversion operation

By setting bit 7 (ADCS) of the A/D converter mode register (ADM) to 1, the A/D conversion operation of the

voltage, which is applied to the analog input pin specified by the analog input channel specification register

(ADS), is started.

When A/D conversion has been completed, the result of the A/D conversion is stored in the A/D conversion result

register (ADCR, ADCRH), and an interrupt request signal (INTAD) is generated. Once the A/D conversion has

started and when one A/D conversion has been completed, the next A/D conversion operation is immediately

started. The A/D conversion operations are repeated until new data is written to ADS.

If ADM or ADS is written during A/D conversion, the A/D conversion operation under execution is stopped and

restarted from the beginning.

If 0 is written to ADCS during A/D conversion, A/D conversion is immediately stopped. At this time, the

conversion result is undefined.

Figure 10-12. A/D Conversion Operation

Rewriting ADM

ADCS = 1

Rewriting ADS

ANIn

ADCS = 0

A/D conversion

ANIn

ANIm

Conversion is stopped

Conversion result is not retained

Stopped

ADCR,

ADCRH

ANIn

ANIm

INTAD

Remarks 1. n = 0 to 3

2. m = 0 to 3

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The setting method is described below.

<1> Set bit 0 (ADCE) of the A/D converter mode register (ADM) to 1.

<2> Select the channel and conversion time using bits 1 and 0 (ADS1, ADS0) of the analog input channel

specification register (ADS) and bits 5 to 3 (FR2 to FR0) of ADM.

<3> Execute two NOP instructions or an instruction equivalent to two machine cycles.

<4> Set bit 7 (ADCS) of ADM to 1 to start A/D conversion.

<5> An interrupt request signal (INTAD) is generated.

<6> Transfer the A/D conversion data to the A/D conversion result register (ADCR, ADCRH).

<7> Change the channel using bits 1 and 0 (ADS1, ADS0) of ADS.

<8> An interrupt request signal (INTAD) is generated.

<9> Transfer the A/D conversion data to the A/D conversion result register (ADCR, ADCRH).

<10> Clear ADCS to 0.

<11> Clear ADCE to 0.

Cautions 1. Make sure the period of <1> to <4> is 1 μs or more.

2. It is no problem if the order of <1> and <2> is reversed.

3. <1> can be omitted. However, ignore the data resulting from the first conversion after

<4> in this case.

4. The period from <5> to <8> differs from the conversion time set using bits 5 to 3 (FR2 to

FR0) of ADM. The period from <7> to <8> is the conversion time set using FR2 to FR0.

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10.5 How to Read A/D Converter Characteristics Table

Here, special terms unique to the A/D converter are explained.

(1) Resolution

This is the minimum analog input voltage that can be identified. That is, the percentage of the analog input

voltage per bit of digital output is called 1LSB (Least Significant Bit). The percentage of 1LSB with respect to the

full scale is expressed by %FSR (Full Scale Range).

1LSB is as follows when the resolution is 10 bits.

1LSB = 1/2¹⁰= 1/1024

= 0.098%FSR

Accuracy has no relation to resolution, but is determined by overall error.

(2) Overall error

This shows the maximum error value between the actual measured value and the theoretical value.

Zero-scale error, full-scale error, integral linearity error, and differential linearity errors that are combinations of

these express the overall error.

Note that the quantization error is not included in the overall error in the characteristics table.

(3) Quantization error

When analog values are converted to digital values, a 1/2LSB error naturally occurs. In an A/D converter, an

analog input voltage in a range of 1/2LSB is converted to the same digital code, so a quantization error cannot

be avoided.

Note that the quantization error is not included in the overall error, zero-scale error, full-scale error, integral

linearity error, and differential linearity error in the characteristics table.

Figure 10-13. Overall Error

Figure 10-14. Quantization Error

……

1

……

1

Ideal line

Overall

error

Quantization error

1/2LSB

……

0

……

0

AV^REF

0

AVREF

Analog input

(4) Zero-scale error

This shows the difference between the actual measurement value of the analog input voltage and the theoretical

value (1/2LSB) when the digital output changes from 0......000 to 0......001.

If the actual measurement value is greater than the theoretical value, it shows the difference between the actual

measurement value of the analog input voltage and the theoretical value (3/2LSB) when the digital output

changes from 0……001 to 0……010.

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(5) Full-scale error

This shows the difference between the actual measurement value of the analog input voltage and the theoretical

value (Full-scale − 3/2LSB) when the digital output changes from 1......110 to 1......111.

(6) Integral linearity error

This shows the degree to which the conversion characteristics deviate from the ideal linear relationship. It

expresses the maximum value of the difference between the actual measurement value and the ideal straight line

when the zero-scale error and full-scale error are 0.

(7) Differential linearity error

While the ideal width of code output is 1LSB, this indicates the difference between the actual measurement value

and the ideal value.

Figure 10-15. Zero-Scale Error

Figure 10-16. Full-Scale Error

111

Full-scale error

Ideal line

011

111

110

010

101

000

001

Ideal line

Zero-scale error

000

0

1

2

3

AV^REF

0

AVREF−3 AVREF−2 AVREF−1 AVREF

Analog input (LSB)

Figure 10-17. Integral Linearity Error

Figure 10-18. Differential Linearity Error

……

1

……

1

Ideal 1LSB width

Ideal line

Differential

linearity error

Integral linearity

error

……

0 0

……

0

AVREF

0

Analog input

(8) Conversion time

This expresses the time from the start of sampling to when the digital output is obtained.

The sampling time is included in the conversion time in the characteristics table.

(9) Sampling time

This is the time the analog switch is turned on for the analog voltage to be sampled by the sample & hold circuit.

Sampling

time

Conversion time

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10.6 Cautions for A/D Converter

(1) Operating current in STOP mode

To satisfy the DC characteristics of the supply current in the STOP mode, clear bit 7 (ADCS) and bit 0 (ADCE) of

the A/D converter mode register (ADM) to 0 before executing the STOP instruction.

(2) Input range of ANI0 to ANI3

Observe the rated range of the ANI0 to ANI3 input voltage. If a voltage of AV^REFor higher and AVSS or lower

(even in the range of absolute maximum ratings) is input to an analog input channel, the converted value of that

channel becomes undefined. In addition, the converted values of the other channels may also be affected.

(3) Conflicting operations

<1> Conflict between A/D conversion result register (ADCR, ADCRH) write and ADCR, ADCRH read by

instruction upon the end of conversion

ADCR, ADCRH read has priority. After the read operation, the new conversion result is written to ADCR,

ADCRH.

<2> Conflict between ADCR, ADCRH write and A/D converter mode register (ADM) write or analog input

channel specification register (ADS) write upon the end of conversion

ADM or ADS write has priority. ADCR, ADCRH write is not performed, nor is the conversion end interrupt

signal (INTAD) generated.

(4) Noise countermeasures

To maintain the 10-bit resolution, attention must be paid to noise input to the AV^REFpin and pins ANI0 to ANI3.

<1> Connect a capacitor with a low equivalent resistance and a high frequency response to the power supply.

<2> Because the effect increases in proportion to the output impedance of the analog input source, it is

recommended that a capacitor be connected externally, as shown in Figure 10-19, to reduce noise.

<3> Do not switch the A/D conversion function of the ANI0 to ANI3 pins to their alternate functions during

conversion.

<4> The conversion accuracy can be improved by setting HALT mode immediately after the conversion starts.

Figure 10-19. Analog Input Pin Connection

If there is a possibility that noise equal to or higher than AV^REFor

equal to or lower than AV^SSmay enter, clamp with a diode with a

small V value (0.3 V or lower).

F

Reference

voltage

input

AV^REF

ANI0 to ANI3

μ

C = 0.01 to 0.1 F

AVSS

VSS

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(5) ANI0/P20 to ANI3/P23

<1> The analog input pins (ANI0 to ANI3) are also used as I/O port pins (P20 to P23).

When A/D conversion is performed with any of ANI0 to ANI3 selected, do not access port 2 (P20 to P23)

while conversion is in progress; otherwise the conversion resolution may be degraded.

<2> If a digital pulse is applied to the pins adjacent to the pins currently used for A/D conversion, the expected

value of the A/D conversion may not be obtained due to coupling noise. Therefore, do not apply a pulse to

the pins adjacent to the pin undergoing A/D conversion.

(6) Input impedance of ANI0 to ANI3 pins

In this A/D converter, the internal sampling capacitor is charged and sampling is performed during sampling time.

Since only the leakage current flows other than during sampling and the current for charging the capacitor also

flows during sampling, the input impedance fluctuates both during sampling and otherwise.

If the shortest conversion time of the reference voltage is used, to perform sufficient sampling, it is recommended

to make the output impedance of the analog input source 1 kΩ or lower, or attach a capacitor of around 0.01 μF

to 0.1 μF to the ANI0 to ANI3 pins (see Figure 10-19).

(7) Interrupt request flag (ADIF)

The interrupt request flag (ADIF) is not cleared even if the analog input channel specification register (ADS) is

changed.

Therefore, if an analog input pin is changed during A/D conversion, the A/D conversion result and ADIF for the

pre-change analog input may be set just before the ADS rewrite. Caution is therefore required since, at this time,

when ADIF is read immediately after the ADS rewrite, ADIF is set despite the fact A/D conversion for the post-

change analog input has not ended.

When A/D conversion is stopped and then resumed, clear ADIF before the A/D conversion operation is resumed.

Figure 10-20. Timing of A/D Conversion End Interrupt Request Generation

ADS rewrite

(start of ANIn conversion)

ADS rewrite

(start of ANIm conversion)

ADIF is set but ANIm conversion

has not ended.

A/D conversion

ANIn

ANIm

ANIn

ANIm

ADCR,

ADCRH

ANIn

ANIm

ADIF

Remarks 1. n = 0 to 3

2. m = 0 to 3

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(8) Conversion results just after A/D conversion start

The first A/D conversion value immediately after A/D conversion starts may not fall within the rating range if the

ADCS bit is set to 1 within 1 μs after the ADCE bit was set to 1, or if the ADCS bit is set to 1 with the ADCE bit =

0. Take measures such as polling the A/D conversion end interrupt request (INTAD) and removing the first

conversion result.

(9) A/D conversion result register (ADCR, ADCRH) read operation

When a write operation is performed to the A/D converter mode register (ADM) and analog input channel

specification register (ADS), the contents of ADCR and ADCRH may become undefined. Read the conversion

result following conversion completion before writing to ADM and ADS. Using a timing other than the above may

cause an incorrect conversion result to be read.

(10) Operating current at conversion waiting mode

The DC characteristic of the operating current during the STOP mode is not satisfied due to the conversion

waiting mode (only the comparator consumes power), when bit 7 (ADCS) and bit 0 (ADCE) of the A/D converter

mode register (ADM) are set to 0 and 1 respectively.

(11) Internal equivalent circuit

The equivalent circuit of the analog input block is shown below.

Figure 10-21. Internal Equivalent Circuit of ANIn Pin

R

OUT

R

IN

ANIn

C

OUT

C

IN

LSI internal

Table 10-3. Resistance and Capacitance Values (Reference Values) of Equivalent Circuit

AVREF

ROUT

1 kΩ

RIN

COUT

8 pF

CIN

4.5 V ≤ AVREF ≤ 5.5 V

2.7 V ≤ AVREF < 4.5 V

3 kΩ

60 kΩ

15 pF

Remarks 1. The resistance and capacitance values shown in Table 10-3 are not guaranteed values.

2. n = 0 to 3

3. R^OUT: Allowable signal source impedance

R^IN: Analog input equivalent resistance

C^IN: Analog input equivalent capacitance

C^OUT: Internal pin capacitance

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CHAPTER 11 SERIAL INTERFACE UART6

11.1 Functions of Serial Interface UART6

Serial interface UART6 has the following two modes.

(1) Operation stop mode

This mode is used when serial communication is not executed and can enable a reduction in the power

consumption.

For details, see 11.4.1 Operation stop mode.

(2) Asynchronous serial interface (UART) mode

This mode supports the LIN (Local Interconnect Network)-bus. The functions of this mode are outlined below.

For details, see 11.4.2 Asynchronous serial interface (UART) mode and 11.4.3 Dedicated baud rate

generator.

•

Two-pin configuration T^XD6: Transmit data output pin

R^XD6: Receive data input pin

•

Data length of communication data can be selected from 7 or 8 bits.

Dedicated internal 8-bit baud rate generator allowing any baud rate to be set

Transmission and reception can be performed independently.

MSB- or LSB-first communication selectable

Inverted transmission operation

Synchronous break field transmission from 13 to 20 bits

More than 11 bits can be identified for synchronous break field reception (SBF reception flag provided).

Cautions 1. The T^XD6 output inversion function inverts only the transmission side and not the reception

side. To use this function, the reception side must be ready for reception of inverted data.

2. If clock supply to serial interface UART6 is not stopped (e.g., in the HALT mode), normal

operation continues. If clock supply to serial interface UART6 is stopped (e.g., in the STOP

mode), each register stops operating, and holds the value immediately before clock supply

was stopped. The T^XD6 pin also holds the value immediately before clock supply was

stopped and outputs it. However, the operation is not guaranteed after clock supply is

resumed. Therefore, reset the circuit so that POWER6 = 0, RXE6 = 0, and TXE6 = 0.

3. If data is continuously transmitted, the communication timing from the stop bit to the next

start bit is extended two operating clocks of the macro. However, this does not affect the

result of communication because the reception side initializes the timing when it has

detected a start bit. Do not use the continuous transmission function if the interface is

used in LIN communication operation.

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Remark LIN stands for Local Interconnect Network and is a low-speed (1 to 20 kbps) serial communication

protocol intended to aid the cost reduction of an automotive network.

LIN communication is single-master communication, and up to 15 slaves can be connected to one

master.

The LIN slaves are used to control the switches, actuators, and sensors, and these are connected to the

LIN master via the LIN network.

Normally, the LIN master is connected to a network such as CAN (Controller Area Network).

In addition, the LIN bus uses a single-wire method and is connected to the nodes via a transceiver that

complies with ISO9141.

In the LIN protocol, the master transmits a frame with baud rate information and the slave receives it and

corrects the baud rate error. Therefore, communication is possible when the baud rate error in the slave

is 15% or less.

Figures 11-1 and 11-2 outline the transmission and reception operations of LIN.

Figure 11-1. LIN Transmission Operation

Wakeup

signal frame

Synchronous

break field

Synchronous

field

Identifier

field

Data field

Data field Checksum

field

LIN bus

13-bit^{Note 2}SBF

transmission

55H

Data

8 bits^{Note 1}

transmission transmissiontransmissiontransmissiontransmission

TxD6

(output)

INTST6^{Note 3}

Notes 1. The wakeup signal frame is substituted by 80H transmission in the 8-bit mode.

2. The synchronous break field is output by hardware. The output width is equal to the bit length set by

bits 4 to 2 (SBL62 to SBL60) of asynchronous serial interface control register 6 (ASICL6) (see 11.4.2

(2) (h) SBF transmission).

3. INTST6 is output on completion of each transmission. It is also output when SBF is transmitted.

Remark The interval between each field is controlled by software.

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Figure 11-2. LIN Reception Operation

Wakeup

signal frame

Synchronous

break field

Synchronous Identifier Data field Data field Checksum

field

LIN bus

13 bits

SF

ID

Data

reception

reception reception reception reception

SBF reception

<5>

<2>

RxD6

(input)

Disable

Enable

<3>

Reception interrupt

(INTSR6)

<1>

Edge detection

(INTP0)

<4>

Capture timer

Disable

Enable

<1> The wakeup signal is detected at the edge of the pin, and enables UART6 and sets the SBF reception mode.

<2> Reception continues until the STOP bit is detected. When an SBF with low-level data of 11 bits or more has

been detected, it is assumed that SBF reception has been completed correctly, and an interrupt request signal

is output. If an SBF with low-level data of less than 11 bits has been detected, it is assumed that an SBF

reception error has occurred. The interrupt request signal is not output and the SBF reception mode is

restored.

<3> If SBF reception has been completed correctly, an interrupt request signal is output. Start the 16-bit

timer/event counter 00 during SBF reception completion interrupt processing, and measure the bit width

(pulse width) of the sync field (refer to 6.4.3 Pulse width measurement operations). Detection of errors

OVE6, PE6, and FE6 is suppressed, and error detection processing of UART communication and data

transfer of the shift register and RXB6 is not performed. The shift register holds the reset value FFH.

<4> Calculate the baud rate error from the bit interval of the synchronous field, disable UART6 after SF reception,

and then re-set baud rate generator control register 6 (BRGC6).

<5> Distinguish the checksum field by software. Also perform processing by software to initialize UART6 after

reception of the checksum field and to set the SBF reception mode again.

Figure 11-3 illustrates the port configuration for LIN reception operation.

The wakeup signal transmitted from the LIN master is received by detecting the edge of the external interrupt

(INTP0). The length of the synchronous field transmitted from the LIN master can be measured using the external

event capture operation of 16-bit timer/event counter 00, and the baud rate error can be calculated.

The input signal of the reception port input (RxD6) can be input to the external interrupt (INTP0) and 16-bit

timer/event counter 00 by port input switch control (ISC0/ISC1), without connecting RxD6 and INTP0/TI000 externally.

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Figure 11-3. Port Configuration for LIN Reception Operation

Selector

P44/R D6

X

RXD6 input

Port mode

(PM44)

Output latch

(P44)

Selector

P30/INTP0/TI000

INTP0 input

Port mode

(PM30)

Port input

selection control

(ISC0)

Output latch

(P30)

<ISC0>

0: Selects INTP0 (P30).

1: Selects RxD6 (P44).

Selector

TI000 input

Port input

selection control

(ISC1)

<ISC1>

0: Selects TI000 (P30).

1: Selects RxD6 (P44).

Remark ISC0, ISC1: Bits 0 and 1 of the input switch control register (ISC) (see Figure 11-11)

The peripheral functions used in the LIN communication operation are shown below.

• External interrupt (INTP0); wakeup signal detection

Use: Detects the wakeup signal edges and detects start of communication.

• 16-bit timer/event counter 00 (TI000); baud rate error detection

Use: Detects the baud rate error (measures the TI000 input edge interval in the capture mode) by detecting the

synchronous field (SF) length and divides it by the number of bits.

• Serial interface UART6

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11.2 Configuration of Serial Interface UART6

Serial interface UART6 consists of the following hardware.

Table 11-1. Configuration of Serial Interface UART6

Item

Registers

Configuration

Receive buffer register 6 (RXB6)

Receive shift register 6 (RXS6)

Transmit buffer register 6 (TXB6)

Transmit shift register 6 (TXS6)

Control registers

Asynchronous serial interface operation mode register 6 (ASIM6)

Asynchronous serial interface reception error status register 6 (ASIS6)

Asynchronous serial interface transmission status register 6 (ASIF6)

Clock selection register 6 (CKSR6)

Baud rate generator control register 6 (BRGC6)

Asynchronous serial interface control register 6 (ASICL6)

Input switch control register (ISC)

Port mode register 4 (PM4)

Port register 4 (P4)

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(1) Receive buffer register 6 (RXB6)

This 8-bit register stores parallel data converted by receive shift register 6 (RXS6).

Each time 1 byte of data has been received, new receive data is transferred to this register from receive shift

register 6 (RXS6). If the data length is set to 7 bits, data is transferred as follows.

•

In LSB-first reception, the receive data is transferred to bits 0 to 6 of RXB6 and the MSB of RXB6 is always 0.

In MSB-first reception, the receive data is transferred to bits 7 to 1 of RXB6 and the LSB of RXB6 is always 0.

If an overrun error (OVE6) occurs, the receive data is not transferred to RXB6.

RXB6 can be read by an 8-bit memory manipulation instruction. No data can be written to this register.

Generation of reset signal sets this register to FFH.

Caution Reception enable status is entered, after having set RXE6 to 1 and one clock of the base clock

(f^XCLK6) has elapsed.

(2) Receive shift register 6 (RXS6)

This register converts the serial data input to the R^XD6 pin into parallel data.

RXS6 cannot be directly manipulated by a program.

(3) Transmit buffer register 6 (TXB6)

This buffer register is used to set transmit data. Transmission is started when data is written to TXB6.

If the data length is set to 7 bits:

•

In LSB-fast transmission, data is transferred to bits 0 to 6 of TXB6, and the MSB of TXB6 is not transmitted.

In MSB-fast transmission, data is transferred to bits 7 to 1 of TXB6, and the LSB of TXB6 is not transmitted.

This register can be read or written by an 8-bit memory manipulation instruction.

Generation of reset signal sets this register to FFH.

Cautions 1. When starting transmission, write transmit data to TXB6, after having set TXE6 to 1 and a

wait of one clock or more of the base clock (f^XCLK6) has been performed.

2. Do not write data to TXB6 when bit 1 (TXBF6) of asynchronous serial interface transmission

status register 6 (ASIF6) is 1.

3. Do not refresh (write the same value to) TXB6 by software during a communication

operation (when bit 7 (POWER6) and bit 6 (TXE6) of asynchronous serial interface operation

mode register 6 (ASIM6) are 1 or when bit 7 (POWER6) and bit 5 (RXE6) of ASIM6 are 1).

When outputting same values in continuous transmission, be sure to confirm that TXBF6 is

0 before writing the same values to TXB6.

(4) Transmit shift register 6 (TXS6)

This register transmits the data transferred from TXB6 from the T^XD6 pin as serial data. Data is transferred from

TXB6 immediately after TXB6 is written for the first transmission, or immediately before INTST6 occurs after one

frame was transmitted for continuous transmission. Data is transferred from TXB6 and transmitted from the T^XD6

pin at the falling edge of the base clock.

TXS6 cannot be directly manipulated by a program.

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CHAPTER 11 SERIAL INTERFACE UART6

11.3 Registers Controlling Serial Interface UART6

Serial interface UART6 is controlled by the following nine registers.

•

Asynchronous serial interface operation mode register 6 (ASIM6)

Asynchronous serial interface reception error status register 6 (ASIS6)

Asynchronous serial interface transmission status register 6 (ASIF6)

Clock selection register 6 (CKSR6)

Baud rate generator control register 6 (BRGC6)

Asynchronous serial interface control register 6 (ASICL6)

Input switch control register (ISC)

Port mode register 4 (PM4)

Port register 4 (P4)

(1) Asynchronous serial interface operation mode register 6 (ASIM6)

This 8-bit register controls the serial communication operations of serial interface UART6.

This register can be set by a 1-bit or 8-bit memory manipulation instruction.

Generation of reset signal sets this register to 01H.

Remark ASIM6 can be refreshed (the same value is written) by software during a communication operation

(when bit 7 (POWER6) and bit 6 (TXE6) of ASIM6 = 1 or bit 7 (POWER6) and bit 5 (RXE6) of ASIM6

= 1).

Figure 11-5. Format of Asynchronous Serial Interface Operation Mode Register 6 (ASIM6) (1/2)

Address: FF90H After reset: 01H R/W

Symbol

ASIM6

<7>

<6>

<5>

4

3

2

1

0

POWER6

TXE6

RXE6

PS61

PS60

CL6

SL6

ISRM6

POWER6

0^{Note 1}

Enabling/disabling operation of internal operation clock

Disable operation of the internal operation clock (fixes the clock to low level) and asynchronously

resets the internal circuit^{Note 2}

Enable operation of the internal operation clock

.

1^{Note 3}

Notes 1. The output of the T^XD6 pin goes high and the input from the RXD6 pin is fixed to the high level when

POWER6 is cleared to 0 during a transmission 0.

2. Asynchronous serial interface reception error status register 6 (ASIS6), asynchronous serial interface

transmission status register 6 (ASIF6), bit 7 (SBRF6) and bit 6 (SBRT6) of asynchronous serial

interface control register 6 (ASICL6), and receive buffer register 6 (RXB6) are reset.

3. A base clock (f^XCLK6) is supplied as the internal operation clock when the POWER6 bit is set to 1 and

one clock of the base clock (f^XCLK6) has elapsed.

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Figure 11-5. Format of Asynchronous Serial Interface Operation Mode Register 6 (ASIM6) (2/2)

TXE6^{Note 1}

Enabling/disabling transmission

Disable transmission (synchronously reset the transmission circuit).

Enable transmission

0

1

RXE6^{Note 2}

Enabling/disabling reception

Disable reception (synchronously reset the reception circuit).

Enable reception

0

1

PS61

PS60

Transmission operation

Parity bit not output.

Reception operation

Reception without parity

0

1

0

1

0

1

Output 0 parity.

Reception as 0 parity^{Note 3}

Judge as odd parity.

Judge as even parity.

Output odd parity.

Output even parity.

CL6

0

Specification of character length of transmit/receive data

Character length of data = 7 bits

Character length of data = 8 bits

1

SL6

0

Specification of number of stop bits of transmit data

Number of stop bits = 1

Number of stop bits = 2

1

ISRM6

Enabling/disabling occurrence of reception completion interrupt in case of error

0

1

“INTSRE6” occurs in case of error (at this time, INTSR6 does not occur).

“INTSR6” occurs in case of error (at this time, INTSRE6 does not occur).

Notes 1. TXE6 is synchronized by the base clock (fXCLK6) set by CKSR6. When re-enabling transmission

operation, set TXE6 to 1 after having set TXE6 to 0 and one clock of the base clock (f^XCLK6) has

elapsed. If TXE6 is set to 1 before one clock of the base clock (f^XCLK6) has elapsed, the transmission

circuit may not able to be initialized.

2. RXE6 is synchronized by the base clock (f^XCLK6) set by CKSR6. When re-enabling reception operation,

set RXE6 to 1 after having set RXE6 to 0 and one clock of the base clock (f^XCLK6) has elapsed. If

RXE6 is set to 1 before one clock of the base clock (fXCLK6) has elapsed, the reception circuit may not

be able to be initialized.

3. If “reception as 0 parity” is selected, the parity is not judged. Therefore, bit 2 (PE6) of asynchronous

serial interface reception error status register 6 (ASIS6) is not set and the error interrupt does not

occur.

Caution 1. At startup, transmission operation is started by setting TXE6 to 1 after having set POWER6 to

1, then setting the transmit data to TXB6 after having waited for one clock or more of the

base clock (f^XCLK6). When stopping transmission operation, set POWER6 to 0 after having set

TXE6 to 0.

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Cautions 2. At startup, reception enable status is entered after having set POWER6 to 1, then setting

RXE6 to 1, and one clock of the base clock (f^XCLK6) has elapsed. When stopping reception

operation, set POWER6 to 0 after having set RXE6 to 0.

3. Set POWER6 = 1 → RXE6 = 1 in a state where a high level has been input to the RxD6 pin. If

POWER6 = 1 → RXE6 = 1 is set during low-level input, reception is started and correct data

will not be received.

4. Clear the TXE6 and RXE6 bits to 0 before rewriting the PS61, PS60, and CL6 bits.

5. Fix the PS61 and PS60 bits to 0 when the interface is used in LIN communication operation.

6. Make sure that TXE6 = 0 when rewriting the SL6 bit. Reception is always performed with “the

number of stop bits = 1”, and therefore, is not affected by the set value of the SL6 bit.

7. Make sure that RXE6 = 0 when rewriting the ISRM6 bit.

(2) Asynchronous serial interface reception error status register 6 (ASIS6)

This register indicates an error status on completion of reception by serial interface UART6. It includes three

error flag bits (PE6, FE6, OVE6).

This register is read-only by an 8-bit memory manipulation instruction.

Reset signal generation clears this register to 00H if bit 7 (POWER6) and bit 5 (RXE6) of ASIM6 = 0. 00H is read

when this register is read.

Figure 11-6. Format of Asynchronous Serial Interface Reception Error Status Register 6 (ASIS6)

Address: FF93H After reset: 00H R

Symbol

ASIS6

7

0

6

0

5

0

4

0

3

0

2

1

0

PE6

FE6

OVE6

PE6

0

Status flag indicating parity error

If POWER6 = 0 and RXE6 = 0, or if ASIS6 register is read

1

If the parity of transmit data does not match the parity bit on completion of reception

FE6

0

Status flag indicating framing error

If POWER6 = 0 and RXE6 = 0, or if ASIS6 register is read

If the stop bit is not detected on completion of reception

1

OVE6

Status flag indicating overrun error

0

1

If POWER6 = 0 and RXE6 = 0, or if ASIS6 register is read

If receive data is set to the RXB register and the next reception operation is completed before the

data is read.

Cautions 1. The operation of the PE6 bit differs depending on the set values of the PS61 and PS60 bits of

asynchronous serial interface operation mode register 6 (ASIM6).

2. The first bit of the receive data is checked as the stop bit, regardless of the number of stop

bits.

3. If an overrun error occurs, the next receive data is not written to receive buffer register 6

(RXB6) but discarded.

4. Be sure to read ASIS6 before reading receive buffer register 6 (RXB6).

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(3) Asynchronous serial interface transmission status register 6 (ASIF6)

This register indicates the status of transmission by serial interface UART6. It includes two status flag bits

(TXBF6 and TXSF6).

Transmission can be continued without disruption even during an interrupt period, by writing the next data to the

TXB6 register after data has been transferred from the TXB6 register to the TXS6 register.

This register is read-only by an 8-bit memory manipulation instruction.

Reset signal generation clears this register to 00H if bit 7 (POWER6) and bit 6 (TXE6) of ASIM6 = 0.

Figure 11-7. Format of Asynchronous Serial Interface Transmission Status Register 6 (ASIF6)

Address: FF95H After reset: 00H R

Symbol

ASIF6

7

0

6

0

5

0

4

0

3

0

2

0

1

0

TXBF6

TXSF6

TXBF6

Transmit buffer data flag

0

1

If POWER6 = 0 or TXE6 = 0, or if data is transferred to transmit shift register 6 (TXS6)

If data is written to transmit buffer register 6 (TXB6) (if data exists in TXB6)

TXSF6

0

Transmit shift register data flag

If POWER6 = 0 or TXE6 = 0, or if the next data is not transferred from transmit buffer register 6

(TXB6) after completion of transfer

1

If data is transferred from transmit buffer register 6 (TXB6) (if data transmission is in progress)

Cautions 1. To transmit data continuously, write the first transmit data (first byte) to the TXB6 register.

Be sure to check that the TXBF6 flag is “0”. If so, write the next transmit data (second byte)

to the TXB6 register. If data is written to the TXB6 register while the TXBF6 flag is “1”, the

transmit data cannot be guaranteed.

2. To initialize the transmission unit upon completion of continuous transmission, be sure to

check that the TXSF6 flag is “0” after generation of the transmission completion interrupt,

and then execute initialization. If initialization is executed while the TXSF6 flag is “1”, the

transmit data cannot be guaranteed.

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(4) Clock selection register 6 (CKSR6)

This register selects the base clock of serial interface UART6.

CKSR6 can be set by an 8-bit memory manipulation instruction.

Reset signal generation clears this register to 00H.

Remark CKSR6 can be refreshed (the same value is written) by software during a communication operation

(when bit 7 (POWER6) and bit 6 (TXE6) of ASIM6 = 1 or bit 7 (POWER6) and bit 5 (RXE6) of ASIM6

= 1).

Figure 11-8. Format of Clock Selection Register 6 (CKSR6)

Address: FF96H After reset: 00H R/W

Symbol

CKSR6

7

0

6

0

5

0

4

0

3

2

1

0

TPS63

TPS62

TPS61

TPS60

TPS63

TPS62

TPS61

TPS60

Base clock (fXCLK6) selection

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

fXP (10 MHz)

fXP/2 (5 MHz)

fXP/2²(2.5 MHz)

fXP/2³(1.25 MHz)

fXP/2⁴(625 kHz)

fXP/2⁵(312.5 kHz)

fXP/2⁶(156.25 kHz)

fXP/2⁷(78.13 kHz)

fXP/2⁸(39.06 kHz)

fXP/2⁹(19.53 kHz)

fXP/2¹⁰(9.77 kHz)

fXP/2¹¹(4.89 kHz)

Setting prohibited

Other than above

Caution Make sure POWER6 = 0 when rewriting TPS63 to TPS60.

Remarks 1. Figures in parentheses are for operation with f^XP= 10 MHz

2. f^XP: Oscillation frequency of clock to peripheral hardware

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(5) Baud rate generator control register 6 (BRGC6)

This register sets the division value of the 8-bit counter of serial interface UART6.

BRGC6 can be set by an 8-bit memory manipulation instruction.

Generation of reset signal sets this register to FFH.

Remark BRGC6 can be refreshed (the same value is written) by software during a communication operation

(when bit 7 (POWER6) and bit 6 (TXE6) of ASIM6 = 1 or bit 7 (POWER6) and bit 5 (RXE6) of ASIM6

= 1).

Figure 11-9. Format of Baud Rate Generator Control Register 6 (BRGC6)

Address: FF97H After reset: FFH R/W

Symbol

BRGC6

7

6

5

4

3

2

1

0

MDL67 MDL66 MDL65 MDL64 MDL63 MDL62 MDL61 MDL60

k

Output clock selection of

8-bit counter

0

1

×

0

×

0

1

×

0

1

0

×

8

Setting prohibited

fXCLK6/8

9

fXCLK6/9

10

fXCLK6/10

•

1

0

1

0

1

0

1

252 fXCLK6/252

253 fXCLK6/253

254 fXCLK6/254

255 fXCLK6/255

Cautions 1. Make sure that bit 6 (TXE6) and bit 5 (RXE6) of the ASIM6 register = 0 when rewriting the

MDL67 to MDL60 bits.

2. The baud rate is the output clock of the 8-bit counter divided by 2.

Remarks 1. f^XCLK6: Frequency of base clock selected by the TPS63 to TPS60 bits of CKSR6 register

2. k: Value set by MDL67 to MDL60 bits (k = 8, 9, 10, ..., 255)

3. ×: Don’t care

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(6) Asynchronous serial interface control register 6 (ASICL6)

This register controls the serial communication operations of serial interface UART6.

ASICL6 can be set by a 1-bit or 8-bit memory manipulation instruction.

Generation of reset signal sets this register to 16H.

Caution ASICL6 can be refreshed (the same value is written) by software during a communication

operation (when bit 7 (POWER6) and bit 6 (TXE6) of ASIM6 are 1 or when bit 7 (POWER6) and

bit 5 (RXE6) of ASIM6 are 1), if 0 data has been written to ASICL6 by SBRT6 and SBTT6.

Figure 11-10. Format of Asynchronous Serial Interface Control Register 6 (ASICL6) (1/2)

Address: FF98H After reset: 16H R/W^Note

Symbol

ASICL6

<7>

<6>

5

4

3

2

1

0

SBRF6

SBRT6

SBTT6

SBL62

SBL61

SBL60

DIR6

TXDLV6

SBRF6

SBF reception status flag

0

1

If POWER6 = 0 and RXE6 = 0 or if SBF reception has been completed correctly

SBF reception in progress

SBRT6

SBF reception trigger

0

1

−

SBF reception trigger

SBTT6

SBF transmission trigger

0

1

−

SBF transmission trigger

Note Bit 7 is read-only.

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Figure 11-10. Format of Asynchronous Serial Interface Control Register 6 (ASICL6) (2/2)

SBL62

SBL61

SBL60

SBF transmission output width control

SBF is output with 13-bit length.

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

SBF is output with 14-bit length.

SBF is output with 15-bit length.

SBF is output with 16-bit length.

SBF is output with 17-bit length.

SBF is output with 18-bit length.

SBF is output with 19-bit length.

SBF is output with 20-bit length.

DIR6

Specification of first bit

0

1

MSB

LSB

TXDLV6

Enabling/disabling inverting TXD6 output

0

1

Normal output of TXD6

Inverted output of TXD6

Cautions 1. In the case of an SBF reception error, return to SBF reception mode again. The status of the

SBRF6 flag will be held (1). For details on SBF reception refer to (2) – (i) SBF reception in

11.4.2 Asynchronous serial interface (UART) mode described later.

2. Before setting the SBRT6 bit to 1, make sure that bit 7 (POWER6) and bit 5 (RXE6) of ASIM6 =

1. Moreover, after setting the SBRT6 bit to 1, do not clear the SBRT6 bit to 0 before the SBF

reception ends (an interrupt request signal is generated).

3. The read value of the SBRT6 bit is always 0. SBRT6 is automatically cleared to 0 after SBF

reception has been correctly completed.

4. Before setting the SBTT6 bit to 1, make sure that bit 7 (POWER6) and bit 6 (TXE6) of ASIM6 =

1. Moreover, after setting the SBTT6 bit to 1, do not clear the SBTT6 bit to 0 before the SBF

transmission ends (an interrupt request signal is generated).

5. The read value of the SBTT6 bit is always 0. SBTT6 is automatically cleared to 0 at the end of

SBF transmission.

6. Before rewriting the DIR6 and TXDLV6 bits, clear the TXE6 and RXE6 bits to 0.

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(7) Input switch control register (ISC)

The input switch control register (ISC) is used to receive a status signal transmitted from the master during LIN

(Local Interconnect Network) reception.

By setting 1 to ISC0 and ISC1, the input source to INTP0 and TI000 switches to the input signal from the

P44/RxD6 pin.

This register can be set by a 1-bit or 8-bit memory manipulation instruction.

Reset signal generation clears this register to 00H.

Figure 11-11. Format of Input Switch Control Register (ISC)

Address: FF8CH After reset: 00H R/W

Symbol

ISC

7

0

6

0

5

0

4

0

3

0

2

0

1

0

ISC1

ISC0

ISC1

TI000 input source selection

0

1

TI000 (P30)

RxD6 (P44)

ISC0

INTP0 input source selection

0

1

INTP0 (P30)

RxD6 (P44)

(8) Port mode register 4 (PM4)

This register sets port 4 input/output in 1-bit units.

When using the P43/TxD6/INTP1 pin for serial interface data output, clear PM43 to 0 and set the output latch of

P43 to 1.

When using the P44/RxD6 pin for serial interface data input, set PM44 to 1. The output latch of P44 at this time

may be 0 or 1.

PM4 can be set by a 1-bit or 8-bit memory manipulation instruction.

Reset signal generation sets this register to FFH.

Figure 11-12. Format of Port Mode Register 4 (PM4)

Address: FF24H After reset: FFH R/W

Symbol

PM4

7

6

5

4

3

2

1

0

PM47

PM46

PM45

PM44

PM43

PM42

PM41

PM40

PM4n

P4n pin I/O mode selection (n = 0 to 7)

0

1

Output mode (output buffer on)

Input mode (output buffer off)

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11.4 Operation of Serial Interface UART6

Serial interface UART6 has the following two modes.

• Operation stop mode

• Asynchronous serial interface (UART) mode

11.4.1 Operation stop mode

In this mode, serial communication cannot be executed; therefore, the power consumption can be reduced. In

addition, the pins can be used as ordinary port pins in this mode. To set the operation stop mode, clear bits 7, 6, and

5 (POWER6, TXE6, and RXE6) of ASIM6 to 0.

(1) Register used

The operation stop mode is set by asynchronous serial interface operation mode register 6 (ASIM6).

ASIM6 can be set by a 1-bit or 8-bit memory manipulation instruction.

Reset signal generation sets this register to 01H.

Address: FF90H After reset: 01H R/W

Symbol

ASIM6

<7>

<6>

<5>

4

3

2

1

0

POWER6

TXE6

RXE6

PS61

PS60

CL6

SL6

ISRM6

POWER6

0^{Note 1}

Enabling/disabling operation of internal operation clock

Disable operation of the internal operation clock (fix the clock to low level) and asynchronously

reset the internal circuit^{Note 2}

.

TXE6

0

Enabling/disabling transmission

Disable transmission operation (synchronously reset the transmission circuit).

RXE6

0

Enabling/disabling reception

Disable reception (synchronously reset the reception circuit).

Notes 1. The output of the T^XD6 pin goes high and the input from the RXD6 pin is fixed to high level when

POWER6 = 0 during a transmission.

2. Asynchronous serial interface reception error status register 6 (ASIS6), asynchronous serial interface

transmission status register 6 (ASIF6), bit 7 (SBRF6) and bit 6 (SBRT6) of asynchronous serial

interface control register 6 (ASICL6), and receive buffer register 6 (RXB6) are reset.

Caution Clear POWER6 to 0 after clearing TXE6 and RXE6 to 0 to set the operation stop mode.

To start the operation, set POWER6 to 1, and then set TXE6 and RXE6 to 1.

Remark To use the RxD6/P44 and TxD6/INTP1/P43 pins as general-purpose port pins, see CHAPTER 4 PORT

FUNCTIONS.

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11.4.2 Asynchronous serial interface (UART) mode

In this mode, data of 1 byte is transmitted/received following a start bit, and a full-duplex operation can be

performed.

A dedicated UART baud rate generator is incorporated, so that communication can be executed at a wide range of

baud rates.

(1) Registers used

• Asynchronous serial interface operation mode register 6 (ASIM6)

• Asynchronous serial interface reception error status register 6 (ASIS6)

• Asynchronous serial interface transmission status register 6 (ASIF6)

• Clock selection register 6 (CKSR6)

• Baud rate generator control register 6 (BRGC6)

• Asynchronous serial interface control register 6 (ASICL6)

• Input switch control register (ISC)

• Port mode register 4 (PM4)

• Port register 4 (P4)

The basic procedure of setting an operation in the UART mode is as follows.

<1> Set the CKSR6 register (see Figure 11-8).

<2> Set the BRGC6 register (see Figure 11-9).

<3> Set bits 0 to 4 (ISRM6, SL6, CL6, PS60, PS61) of the ASIM6 register (see Figure 11-5).

<4> Set bits 0 and 1 (TXDLV6, DIR6) of the ASICL6 register (see Figure 11-10).

<5> Set bit 7 (POWER6) of the ASIM6 register to 1.

<6> Set bit 6 (TXE6) of the ASIM6 register to 1. → Transmission is enabled.

Set bit 5 (RXE6) of the ASIM6 register to 1. → Reception is enabled.

<7> Write data to transmit buffer register 6 (TXB6). → Data transmission is started.

Caution Take the relationship with the other party of communication into consideration when setting the

port mode register and port register. In order to avoid the generation of unintended start bits

(falling signals), set PM43 to 0 (output) after having set P43 to 1.

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The relationship between the register settings and pins is shown below.

Table 11-2. Relationship Between Register Settings and Pins

POWER6 TXE6

RXE6

PM43

P43

PM44

P44

UART6

Pin Function

TxD6/INTP1/P43

Operation

RxD6/P44

P44

Note

0

1

0

1

0

1

0

1

×

Stop

P43

Note

×

1

×

Reception

Transmission

RxD6

P44

Note

0

1

×

TxD6

1

×

Transmission/

reception

RxD6

Note Can be set as port function.

Remark ×:

don’t care

POWER6: Bit 7 of asynchronous serial interface operation mode register 6 (ASIM6)

TXE6:

RXE6:

PM4×:

P4×:

Bit 6 of ASIM6

Bit 5 of ASIM6

Port mode register

Port output latch

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(2) Communication operation

(a) Format and waveform example of normal transmit/receive data

Figures 11-13 and 11-14 show the format and waveform example of the normal transmit/receive data.

Figure 11-13. Format of Normal UART Transmit/Receive Data

1. LSB-first transmission/reception

1 data frame

Start

bit

Parity

bit

D0

D1

D2

D3

D4

D5

D6

D7

Stop bit

Character bits

2. MSB-first transmission/reception

1 data frame

Start

bit

Parity

bit

D7

D6

D5

D4

D3

D2

D1

D0

Stop bit

Character bits

One data frame consists of the following bits.

• Start bit ... 1 bit

• Character bits ... 7 or 8 bits

• Parity bit ... Even parity, odd parity, 0 parity, or no parity

• Stop bit ... 1 or 2 bits

The character bit length, parity, and stop bit length in one data frame are specified by asynchronous serial

interface operation mode register 6 (ASIM6).

Whether data is communicated with the LSB or MSB first is specified by bit 1 (DIR6) of asynchronous serial

interface control register 6 (ASICL6).

Whether the T^XD6 pin outputs normal or inverted data is specified by bit 0 (TXDLV6) of ASICL6.

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Figure 11-14. Example of Normal UART Transmit/Receive Data Waveform

1. Data length: 8 bits, LSB first, Parity: Even parity, Stop bit: 1 bit, Communication data: 55H

1 data frame

Start

D0

D1

D2

D3

D4

D5

D6

D7

Parity

Stop

2. Data length: 8 bits, MSB first, Parity: Even parity, Stop bit: 1 bit, Communication data: 55H

1 data frame

Start

D7

D6

D5

D4

D3

D2

D1

D0

Parity

Stop

3. Data length: 8 bits, MSB first, Parity: Even parity, Stop bit: 1 bit, Communication data: 55H, T^XD6 pin

inverted output

1 data frame

Start

D7

D6

D5

D4

D3

D2

D1

D0

Parity

Stop

4. Data length: 7 bits, LSB first, Parity: Odd parity, Stop bit: 2 bits, Communication data: 36H

1 data frame

Start

D0

D1

D2

D3

D4

D5

D6

Parity

Stop

5. Data length: 8 bits, LSB first, Parity: None, Stop bit: 1 bit, Communication data: 87H

1 data frame

Start

D0

D1

D2

D3

D4

D5

D6

D7

Stop

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(b) Parity types and operation

The parity bit is used to detect a bit error in communication data. Usually, the same type of parity bit is used

on both the transmission and reception sides. With even parity and odd parity, a 1-bit (odd number) error

can be detected. With zero parity and no parity, an error cannot be detected.

Caution Fix the PS61 and PS60 bits to 0 when the interface is used in LIN communication operation.

(i) Even parity

• Transmission

Transmit data, including the parity bit, is controlled so that the number of bits that are “1” is even.

The value of the parity bit is as follows.

If transmit data has an odd number of bits that are “1”:

1

If transmit data has an even number of bits that are “1”: 0

• Reception

The number of bits that are “1” in the receive data, including the parity bit, is counted. If it is odd, a

parity error occurs.

(ii) Odd parity

• Transmission

Unlike even parity, transmit data, including the parity bit, is controlled so that the number of bits that

are “1” is odd.

If transmit data has an odd number of bits that are “1”:

0

If transmit data has an even number of bits that are “1”: 1

• Reception

The number of bits that are “1” in the receive data, including the parity bit, is counted. If it is even, a

parity error occurs.

(iii) 0 parity

The parity bit is cleared to 0 when data is transmitted, regardless of the transmit data.

The parity bit is not detected when the data is received. Therefore, a parity error does not occur

regardless of whether the parity bit is “0” or “1”.

(iv) No parity

No parity bit is appended to the transmit data.

Reception is performed assuming that there is no parity bit when data is received. Because there is no

parity bit, a parity error does not occur.

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(c) Normal transmission

When bit 7 (POWER6) of asynchronous serial interface operation mode register 6 (ASIM6) is set to 1, and

then bit 6 (TXE6) of ASIM6 is set to 1 after one clock of the base clock (f^XCLK6) has elapsed, transmission

enable status is entered. Transmission can be started by writing transmit data to transmit buffer register 6

(TXB6). The start bit, parity bit, and stop bit are automatically appended to the data.

When transmission is started, the data in TXB6 is transferred to transmit shift register 6 (TXS6). After that,

the data is sequentially output from TXS6 to the T^XD6 pin. When transmission is completed, the parity and

stop bits set by ASIM6 are appended and a transmission completion interrupt request (INTST6) is generated.

Transmission is stopped until the data to be transmitted next is written to TXB6.

Figure 11-15 shows the timing of the transmission completion interrupt request (INTST6). This interrupt

occurs as soon as the last stop bit has been output.

Figure 11-15. Normal Transmission Completion Interrupt Request Timing

1. Stop bit length: 1

Parity

TX

D6 (output)

INTST6

Start

D0

D1

D2

D6

D7

Stop

2. Stop bit length: 2

TXD6 (output)

Start

D0

D1

D2

D6

D7

Parity

Stop

INTST6

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(d) Continuous transmission

The next transmit data can be written to transmit buffer register 6 (TXB6) as soon as transmit shift register 6

(TXS6) has started its shift operation. Consequently, even while the INTST6 interrupt is being serviced after

transmission of one data frame, data can be continuously transmitted and an efficient communication rate

can be realized. In addition, the next transmit data can be written to the TXB6 register without having to wait

for the transmission time of one data frame, by confirming bit 0 (TXSF6) of asynchronous serial interface

transmission status register 6 (ASIF6) after a transmission completion interrupt has occurred.

To transmit data continuously, be sure to reference the ASIF6 register to check the transmission status and

whether the TXB6 register can be written, and then write the data.

For the continuous transmission procedure, refer to Figure 11-16 Example of Continuous Transmission

Processing Flow.

Cautions 1. Use the value of the TXBF6 flag to judge whether continuous transmission is possible.

Do not write the next transmit data, by making a judgment only by the fact that the

TXSF6 flag has been set to 1.

2. When the interface is used in LIN communication operation, the continuous

transmission function cannot be used. Make sure that asynchronous serial interface

transmission status register 6 (ASIF6) is 00H before writing transmit data to transmit

buffer register 6 (TXB6).

TXBF6

Writing to TXB6 Register

0

1

Writing enabled

Writing disabled

Caution To transmit data continuously, write the first transmit data (first byte) to the TXB6 register.

Be sure to check that the TXBF6 flag is “0”. If so, write the next transmit data (second byte)

to the TXB6 register. If data is written to the TXB6 register while the TXBF6 flag is “1”, the

transmit data cannot be guaranteed.

The communication status can be checked using the TXSF6 flag.

TXSF6

Transmission Status

0

1

Transmission is completed.

Transmission is in progress.

Caution To initialize the transmission unit upon completion of continuous transmission, be sure to

check that the TXSF6 flag is “0” after generation of the transmission completion interrupt,

and then execute initialization. If initialization is executed while the TXSF6 flag is “1”, the

transmit data cannot be guaranteed.

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Figure 11-16 shows an example of the continuous transmission processing flow.

Figure 11-16. Example of Continuous Transmission Processing Flow

Set registers.

Write TXB6.

Transfer

executed necessary

number of times?

Yes

No

Read ASIF6

TXBF6 = 0?

Yes

Write TXB6.

Transmission

completion interrupt

occurred?

No

Yes

Transfer

executed necessary

number of times?

Yes

No

Read ASIF6

TXSF6 = 0?

Yes

Completion of

transmission processing

Remark TXB6: Transmit buffer register 6

ASIF6: Asynchronous serial interface transmission status register 6

TXBF6: Bit 1 of ASIF6 (transmit buffer data flag)

TXSF6: Bit 0 of ASIF6 (transmit shift register data flag)

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Figure 11-17 shows the timing of starting continuous transmission, and Figure 11-18 shows the timing of

ending continuous transmission.

Figure 11-17. Timing of Starting Continuous Transmission

Start

TX

D6

Data (1)

Parity Stop

Data (2)

Parity

Stop

INTST6

TXB6

FF

Data (1)

Data (2)

Data (3)

TXS6

Data (1)

Data (2)

Data (3)

TXBF6

TXSF6

Note

Note When ASIF6 is read, there is a period in which TXBF6 and TXSF6 = 1, 1. Therefore, judge whether

writing is enabled using only the TXBF6 bit.

Remark T^XD6:

TXD6 pin (output)

INTST6: Interrupt request signal

TXB6:

TXS6:

Transmit buffer register 6

Transmit shift register 6

ASIF6: Asynchronous serial interface transmission status register 6

TXBF6: Bit 1 of ASIF6

TXSF6: Bit 0 of ASIF6

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Figure 11-18. Timing of Ending Continuous Transmission

Start

T

X

D6

Data (n)

Parity

Stop

Parity

Data (n − 1)

Stop

INTST6

TXB6

Data (n − 1)

Data (n)

TXS6

FF

Data (n − 1)

Data (n)

TXBF6

TXSF6

POWER6 or TXE6

Remark T^XD6:

INTST6:

TXD6 pin (output)

Interrupt request signal

Transmit buffer register 6

Transmit shift register 6

TXB6:

TXS6:

ASIF6:

TXBF6:

TXSF6:

Asynchronous serial interface transmission status register 6

Bit 1 of ASIF6

Bit 0 of ASIF6

POWER6: Bit 7 of asynchronous serial interface operation mode register (ASIM6)

TXE6:

Bit 6 of asynchronous serial interface operation mode register (ASIM6)

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(e) Normal reception

Reception is enabled and the R^XD6 pin input is sampled when bit 7 (POWER6) of asynchronous serial

interface operation mode register 6 (ASIM6) is set to 1 and then bit 5 (RXE6) of ASIM6 is set to 1.

The 8-bit counter of the baud rate generator starts counting when the falling edge of the R^XD6 pin input is

detected. When the set value of baud rate generator control register 6 (BRGC6) has been counted, the

R^XD6 pin input is sampled again ( in Figure 11-19). If the RXD6 pin is low level at this time, it is recognized

as a start bit.

When the start bit is detected, reception is started, and serial data is sequentially stored in the receive shift

register (RXS6) at the set baud rate. When the stop bit has been received, the reception completion interrupt

(INTSR6) is generated and the data of RXS6 is written to receive buffer register 6 (RXB6). If an overrun

error (OVE6) occurs, however, the receive data is not written to RXB6.

Even if a parity error (PE6) occurs while reception is in progress, reception continues to the reception

position of the stop bit, and an error interrupt (INTSR6/INTSRE6) is generated on completion of reception.

Figure 11-19. Reception Completion Interrupt Request Timing

Start

D0

D1

D2

D3

D4

D5

D6

D7

Parity

Stop

RXD6 (input)

INTSR6

RXB6

Cautions 1. Be sure to read receive buffer register 6 (RXB6) even if a reception error occurs.

Otherwise, an overrun error will occur when the next data is received, and the reception

error status will persist.

2. Reception is always performed with the “number of stop bits = 1”. The second stop bit

is ignored.

3. Be sure to read asynchronous serial interface reception error status register 6 (ASIS6)

before reading RXB6.

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(f) Reception error

Three types of errors may occur during reception: a parity error, framing error, or overrun error. If the error

flag of asynchronous serial interface reception error status register 6 (ASIS6) is set as a result of data

reception, a reception error interrupt request (INTSR6/INTSRE6) is generated.

Which error has occurred during reception can be identified by reading the contents of ASIS6 in the reception

error interrupt servicing (INTSR6/INTSRE6) (see Figure 11-6).

The contents of ASIS6 are reset to 0 when ASIS6 is read.

Table 11-3. Cause of Reception Error

Reception Error

Parity error

Cause

The parity specified for transmission does not match the parity of the receive data.

Stop bit is not detected.

Framing error

Overrun error

Reception of the next data is completed before data is read from receive buffer

register 6 (RXB6).

The error interrupt can be separated into reception completion interrupt (INTSR6) and error interrupt

(INTSRE6) by clearing bit 0 (ISRM6) of asynchronous serial interface operation mode register 6 (ASIM6) to

0.

Figure 11-20. Reception Error Interrupt

1. If ISRM6 is cleared to 0 (reception completion interrupt (INTSR6) and error interrupt (INTSRE6) are

separated)

(a) No error during reception

INTSR6

(b) Error during reception

INTSR6

INTSRE6

2. If ISRM6 is set to 1 (error interrupt is included in INTSR6)

(a) No error during reception

(b) Error during reception

INTSR6

INTSRE6

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(g) Noise filter of receive data

The R^XD6 signal is sampled with the base clock (fXCLK6) output by the prescaler block.

If two sampled values are the same, the output of the match detector changes, and the data is sampled as

input data.

Because the circuit is configured as shown in Figure 11-21, the internal processing of the reception operation

is delayed by two clocks from the external signal status.

Figure 11-21. Noise Filter Circuit

Base clock

Internal signal A

RX

D6/P44

Internal signal B

In

Q

In

Q

LD_EN

Match detector

(h) SBF transmission

When the interface is used in LIN communication operation, the SBF (Synchronous Break Field)

transmission control function is used for transmission. For the transmission operation of LIN, see Figure 11-

1 LIN Transmission Operation.

When bit 7 (POWER6) of asynchronous serial interface mode register 6 (ASIM6) is set to 1, the TxD6 pin

outputs high level. Next, when bit 6 (TXE6) of ASIM6 is set to 1, the transmission enabled status is entered,

and SBF transmission is started by setting bit 5 (SBTT6) of asynchronous serial interface control register 6

(ASICL6) to 1.

Thereafter, a low level of bits 13 to 20 (set by bits 4 to 2 (SBL62 to SBL60) of ASICL6) is output. Following

the end of SBF transmission, the transmission completion interrupt request (INTST6) is generated and

SBTT6 is automatically cleared. Thereafter, the normal transmission mode is restored.

Transmission is suspended until the data to be transmitted next is written to transmit buffer register 6 (TXB6),

or until SBTT6 is set to 1.

Figure 11-22. SBF Transmission

1

2

3

4

5

6

7

8

9

10

11

12

13 Stop

TXD6

INTST6

SBTT6

Remark TXD6:

TXD6 pin (output)

INTST6: Transmission completion interrupt request

SBTT6: Bit 5 of asynchronous serial interface control register 6 (ASICL6)

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(i) SBF reception

When the interface is used in LIN communication operation, the SBF (Synchronous Break Field) reception

control function is used for reception. For the reception operation of LIN, see Figure 11-2 LIN Reception

Operation.

Reception is enabled when bit 7 (POWER6) of asynchronous serial interface operation mode register 6

(ASIM6) is set to 1 and then bit 5 (RXE6) of ASIM6 is set to 1. SBF reception is enabled when bit 6 (SBRT6)

of asynchronous serial interface control register 6 (ASICL6) is set to 1. In the SBF reception enabled status,

the R^XD6 pin is sampled and the start bit is detected in the same manner as the normal reception enable

status.

When the start bit has been detected, reception is started, and serial data is sequentially stored in the

receive shift register 6 (RXS6) at the set baud rate. When the stop bit is received and if the width of SBF is

11 bits or more, a reception completion interrupt request (INTSR6) is generated as normal processing. At

this time, the SBRF6 and SBRT6 bits are automatically cleared, and SBF reception ends. Detection of

errors, such as OVE6, PE6, and FE6 (bits 0 to 2 of asynchronous serial interface reception error status

register 6 (ASIS6)) is suppressed, and error detection processing of UART communication is not performed.

In addition, data transfer between receive shift register 6 (RXS6) and receive buffer register 6 (RXB6) is not

performed, and the reset value of FFH is retained. If the width of SBF is 10 bits or less, an interrupt does not

occur as error processing after the stop bit has been received, and the SBF reception mode is restored. In

this case, the SBRF6 and SBRT6 bits are not cleared.

Figure 11-23. SBF Reception

1. Normal SBF reception (stop bit is detected with a width of more than 10.5 bits)

1

2

3

4

5

6

7

8

9

10

RXD6

SBRT6

/SBRF6

INTSR6

2. SBF reception error (stop bit is detected with a width of 10.5 bits or less)

1

2

3

4

5

6

7

8

9

10

RXD6

SBRT6

/SBRF6

INTSR6

“0”

Remark R^XD6:

RXD6 pin (input)

SBRT6: Bit 6 of asynchronous serial interface control register 6 (ASICL6)

SBRF6: Bit 7 of ASICL6

INTSR6: Reception completion interrupt request

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11.4.3 Dedicated baud rate generator

The dedicated baud rate generator consists of a source clock selector and an 8-bit programmable counter, and

generates a serial clock for transmission/reception of UART6.

Separate 8-bit counters are provided for transmission and reception.

(1) Configuration of baud rate generator

•

Base clock

The clock selected by bits 3 to 0 (TPS63 to TPS60) of clock selection register 6 (CKSR6) is supplied to

each module when bit 7 (POWER6) of asynchronous serial interface operation mode register 6 (ASIM6) is

1. This clock is called the base clock and its frequency is called f^XCLK6. The base clock is fixed to low level

when POWER6 = 0.

Transmission counter

This counter stops operation, cleared to 0, when bit 7 (POWER6) or bit 6 (TXE6) of asynchronous serial

interface operation mode register 6 (ASIM6) is 0.

It starts counting when POWER6 = 1 and TXE6 = 1.

The counter is cleared to 0 when the first data transmitted is written to transmit buffer register 6 (TXB6).

If data are continuously transmitted, the counter is cleared to 0 again when one frame of data has been

completely transmitted. If there is no data to be transmitted next, the counter is not cleared to 0 and continues

counting until POWER6 or TXE6 is cleared to 0.

•

Reception counter

This counter stops operation, cleared to 0, when bit 7 (POWER6) or bit 5 (RXE6) of asynchronous serial

interface operation mode register 6 (ASIM6) is 0.

It starts counting when the start bit has been detected.

The counter stops operation after one frame has been received, until the next start bit is detected.

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Figure 11-24. Configuration of Baud Rate Generator

POWER6

f

XP

Baud rate generator

f

XP/2

f

XP/2²

XP/2³

XP/2⁴

XP/2⁵

XP/2⁶

XP/2⁷

XP/2⁸

XP/2⁹

POWER6, TXE6 (or RXE6)

Selector

8-bit counter

f

XCLK6

(Base clock)

f

XP/2¹⁰

XP/2¹¹

Match detector

Baud rate

1/2

CKSR6: TPS63 to TPS60

BRGC6: MDL67 to MDL60

Remark POWER6: Bit 7 of asynchronous serial interface operation mode register 6 (ASIM6)

TXE6:

Bit 6 of ASIM6

RXE6:

Bit 5 of ASIM6

CKSR6:

BRGC6:

Clock selection register 6

Baud rate generator control register 6

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(2) Generation of serial clock

A serial clock can be generated by using clock selection register 6 (CKSR6) and baud rate generator control

register 6 (BRGC6).

Select the clock to be input to the 8-bit counter by using bits 3 to 0 (TPS63 to TPS60) of CKSR6.

Bits 7 to 0 (MDL67 to MDL60) of BRGC6 can be used to select the division value of the 8-bit counter.

(a) Baud rate

The baud rate can be calculated by the following expression.

fXCLK6

• Baud rate =

[bps]

2 × k

f^XCLK6: Frequency of base clock selected by TPS63 to TPS60 bits of CKSR6 register

k: Value set by MDL67 to MDL60 bits of BRGC6 register (k = 8, 9, 10, ..., 255)

(b) Error of baud rate

The baud rate error can be calculated by the following expression.

Actual baud rate (baud rate with error)

• Error (%) =

− 1 × 100 [%]

Desired baud rate (correct baud rate)

Cautions 1. Keep the baud rate error during transmission to within the permissible error range at

the reception destination.

2. Make sure that the baud rate error during reception satisfies the range shown in (4)

Permissible baud rate range during reception.

Example: Frequency of base clock = 10 MHz = 10,000,000 Hz

Set value of MDL67 to MDL60 bits of BRGC6 register = 00100001B (k = 33)

Target baud rate = 153600 bps

Baud rate = 10 M/(2 × 33)

= 10000000/(2 × 33) = 151,515 [bps]

Error = (151515/153600 − 1) × 100

= −1.357 [%]

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(3) Example of setting baud rate

Table 11-4. Set Data of Baud Rate Generator

Baud Rate

[bps]

fXP = 10.0 MHz

fXP = 8.38 MHz

fXP = 4.19 MHz

TPS63 to

TPS60

k

Calculated ERR[%] TPS63 to

k

Calculated ERR[%] TPS63 to

k

Calculated ERR[%]

Value

TPS60

6H

5H

4H

3H

2H

1H

0H

Value

TPS60

5H

4H

3H

2H

1H

0H

Value

600

1200

6H

5H

4H

3H

2H

1H

0H

130

240

130

160

130

65

601

1202

0.16

0.00

0.16

0.94

−1.36

109

201

109

134

109

55

601

0.11

0.22

0.11

0.06

0.11

−0.80

1.03

109

101

109

67

601

0.11

−0.28

0.11

0.06

−0.80

1.03

−2.58

1.03

1201

2400

2404

2403

4800

4808

4805

9600

9615

9610

10400

19200

31250

38400

76800

115200

153600

230400

10417

19231

31250

38462

76923

116279

151515

227272

10423

19220

31268

38440

76182

116389

155185

232778

10475

19220

31268

38090

77693

116389

149643

232778

55

27

43

36

18

33

27

14

22

18

9

Remark TPS63 to TPS60: Bits 3 to 0 of clock selection register 6 (CKSR6) (setting of base clock (fXCLK6))

k:

Value set by MDL67 to MDL60 bits of baud rate generator control register 6

(BRGC6) (k = 8, 9, 10, ..., 255)

f^XP:

Oscillation frequency of clock to peripheral hardware

Baud rate error

ERR:

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(4) Permissible baud rate range during reception

The permissible error from the baud rate at the transmission destination during reception is shown below.

Caution Make sure that the baud rate error during reception is within the permissible error range, by

using the calculation expression shown below.

Figure 11-25. Permissible Baud Rate Range During Reception

Latch timing

Data frame length

Start bit

Bit 0

FL

Bit 1

Bit 7

Parity bit

Stop bit

of UART6

1 data frame (11 × FL)

Minimum permissible

data frame length

Bit 0

Bit 1

Bit 7

Parity bit

Stop bit

FLmin

Maximum permissible

data frame length

Bit 0

Bit 1

Bit 7

Parity bit

Stop bit

FLmax

As shown in Figure 11-25, the latch timing of the receive data is determined by the counter set by baud rate

generator control register 6 (BRGC6) after the start bit has been detected. If the last data (stop bit) meets this

latch timing, the data can be correctly received.

Assuming that 11-bit data is received, the theoretical values can be calculated as follows.

1

FL = (Brate)⁻

Brate: Baud rate of UART6

k:

Set value of BRGC6

1-bit data length

FL:

Margin of latch timing: 2 clocks

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CHAPTER 11 SERIAL INTERFACE UART6

21k + 2

2k

k − 2

2k

Minimum permissible data frame length: FLmin = 11 × FL −

× FL =

FL

Therefore, the maximum receivable baud rate at the transmission source is as follows.

22k

1

BRmax = (FLmin/11)⁻

=

Brate

21k + 2

Similarly, the maximum permissible data frame length can be calculated as follows.

10

11

k + 2

21k − 2

2 × k

× FLmax = 11 × FL −

× FL =

FL

2 × k

21k – 2

FLmax =

FL × 11

20k

Therefore, the minimum receivable baud rate at the transmission source is as follows.

20k

1

BRmin = (FLmax/11)⁻

=

Brate

21k − 2

The permissible baud rate error between UART6 and the transmission source can be calculated from the above

minimum and maximum baud rate expressions, as follows.

Table 11-5. Maximum/Minimum Permissible Baud Rate Error

Division Ratio (k)

Maximum Permissible Baud Rate Error

Minimum Permissible Baud Rate Error

8

+3.53%

+4.26%

+4.56%

+4.66%

+4.72%

−3.61%

−4.31%

−4.58%

−4.67%

−4.73%

20

50

100

255

Remarks 1. The permissible error of reception depends on the number of bits in one frame, input clock

frequency, and division ratio (k). The higher the input clock frequency and the higher the division

ratio (k), the higher the permissible error.

2. k: Set value of BRGC6

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(5) Data frame length during continuous transmission

When data is continuously transmitted, the data frame length from a stop bit to the next start bit is extended by

two clocks of the base clock (f^XCLK6) from the normal value. However, the result of communication is not affected

because the timing is initialized on the reception side when the start bit is detected.

Figure 11-26. Data Frame Length During Continuous Transmission

Start bit of

1 data frame

second byte

Bit 0

FL

Bit 1

FL

Bit 7

FL

Bit 0

FL

Start bit

FL

Start bit

FL

Parity bit

FL

Stop bit

FLstp

Where the 1-bit data length is FL, the stop bit length is FLstp, and base clock frequency is fXCLK6, the following

expression is satisfied.

FLstp = FL + 2/f^XCLK6

Therefore, the data frame length during continuous transmission is:

Data frame length = 11 × FL + 2/f^XCLK6

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CHAPTER 12 MULTIPLIER

12.1 Multiplier Function

The multiplier has the following function.

• Calculation of 8 bits × 8 bits = 16 bits

12.2 Multiplier Configuration

(1) 16-bit multiplication result storage register 0 (MUL0)

This register stores the 16-bit result of multiplication.

This register holds the result of multiplication after 16 CPU clocks have elapsed.

MUL0 can be read by a 16-bit memory manipulation instruction.

Reset signal generation makes MUL0 undefined.

Caution Although this register is manipulated with a 16-bit memory manipulation instruction, it can

be also manipulated with an 8-bit memory manipulation instruction. When using an 8-bit

memory manipulation instruction, however, access the register by means of direct

addressing.

(2) Multiplication data registers A and B (MRA0 and MRB0)

These are 8-bit multiplication data storage registers. The multiplier multiplies the values of MRA0 and MRB0.

MRA0 and MRB0 can be written by an 8-bit memory manipulation instruction.

Reset signal generation makes these registers undefined.

Figure 12-1 shows the block diagram of the multiplier.

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Figure 12-1. Block Diagram of Multiplier

Internal bus

Multiplication data

register A (MRA0)

Multiplication data

register B (MRB0)

Counter value

CPU clock

Selector

3-bit counter

Start Clear

3

16-bit

adder

16-bit multiplication result

storage register 0 (Master) (MUL0)

16-bit multiplication result

storage register 0 (Slave)

Reset

MULST0

Multiplier control

register 0 (MULC0)

Internal bus

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CHAPTER 12 MULTIPLIER

12.3 Multiplier Control Register

The multiplier is controlled by the following register.

• Multiplier control register 0 (MULC0)

(1) Multiplier control register 0 (MULC0)

This register indicates the operating status of the multiplier after operation, as well as controls the multiplier.

MULC0 can be set by a 1-bit or 8-bit memory manipulation instruction.

Reset signal generation clears this register to 00H.

Figure 12-2. Format of Multiplier Control Register 0 (MULC0)

Address: FFD2H After reset: 00H RW

Symbol

MULC0

7

0

6

0

5

0

4

0

3

0

2

0

1

0

<0>

MULST0

Multiplier operation start control bit

Operating status of multiplier

Operation stops

Operation in progress

0

1

Stops operation after resetting counter to 0.

Enables operation

Caution

Be sure to clear bits 1 to 7 to 0.

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CHAPTER 12 MULTIPLIER

12.4 Multiplier Operation

The multiplier of the 78K0S/KB1+ can execute the calculation of 8 bits × 8 bits = 16 bits. Figure 12-3 shows the

operation timing of the multiplier where MRA0 is set to AAH and MRB0 is set to D3H.

<1> Counting is started by setting the MULST0, and then multiplication of MRA0 and MRB0 begins. The

multiplication result is held after 16 clocks, using the CPU clock.

<2> The data generated by the selector is added to the data of MUL0 at each CPU clock, and the counter value is

incremented by one.

<3> When the 3-bit counter value is 111B, MULST0 is cleared and the operation is stopped. At this time, MUL0

holds the operation result.

Remark When MULST0 is low, the 3-bit counter is cleared.

Figure 12-3. Multiplier Operation Timing (Example of AAH × D3H)

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16

CPU clock

MRA0

MRB0

AA

D3

MULST0

<1>

<2>

<3>

3-bit counter

MUL0

000B

001B 010B 011B 100B 101B 110B 111B

Operation in progress^Note

000B

8C1E

Note Mid-calculation results are read by referencing MUL0 while calculating.

The source code of this example is shown in the following page.

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;==============================================================

;

The example of multiplier use

;==============================================================

M_DATA_A

M_DATA_B

EQU

0FE80H

0FE90H

; Address A for multipliers

; Address B for multipliers

; A setup for operation

MOV

M_DATA_A, #0AAH

M_DATA_B, #0D3H

; Multiplication of M_DATA_A and M_DATA_B

MOV

A, M_DATA_A

MRA0, A

A, M_DATA_B

MRB0, A

SET1

MULST0

; Multiplication start

M_LOOP:

BT

MULST0, $M_LOOP

AX, MUL0

; Waiting for multiplication completion

; Multiplication completion

MOVW

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CHAPTER 13 INTERRUPT FUNCTIONS

13.1 Interrupt Function Types

There are two types of interrupts: maskable interrupts and resets.

•

Maskable interrupts

These interrupts undergo mask control. When an interrupt request occurs, the standby release signal occurs,

and if an interrupt can be acknowledged then the program corresponding to the address written in the vector

table address is executed (vector interrupt servicing). When several interrupt requests are generated at the

same time, processing takes place in the priority order of the vector interrupt servicing. For details on the

priority order, see Table 13-1.

There are nine internal sources and four external sources of maskable interrupts.

•

Reset

The CPU and SFR are returned to their initial states by the reset signal. The causes for reset signal

occurrences are shown in Table 13-1.

When a reset signal occurs, program execution starts from the programs at the addresses written in addresses

0000H and 0001H.

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CHAPTER 13 INTERRUPT FUNCTIONS

13.2 Interrupt Sources and Configuration

There are a total of 13 maskable interrupt sources, and up to four reset sources (see Table 13-1).

Table 13-1. Interrupt Sources

Interrupt Type

Maskable

Priority^{Note 1}

Interrupt Source

Trigger

Internal/

External

Vector Table

Address

Basic

Configuration

Type^{Note 2}

Name

INTLVI

1

2

3

4

5

Low-voltage detection^{Note 3}

Pin input edge detection

Internal

0006H

0008H

000AH

000CH

000EH

(A)

(B)

INTP0

External

INTP1

INTTMH1

INTTM000

Match between TMH1 and CMP01

Internal

(A)

Match between TM00 and CR000

(when compare register is specified),

TI010 pin valid edge detection (when

capture register is specified)

6

INTTM010

Match between TM00 and CR010

(when compare register is specified),

TI000 pin valid edge detection (when

capture register is specified)

0010H

7

8

INTAD

INTP2

INTP3

INTTM80

INTSRE6

INTSR6

INTST6

RESET

POC

End of A/D conversion

Pin input edge detection

0012H

0016H

0018H

001AH

001CH

001EH

0020H

0000H

External

Internal

(B)

(A)

9

10

11

12

13

−

Match between TM80 and CR80

UART6 reception error occurrence

End of UART6 reception

End of UART6 transmission

Reset input

Reset

−

Power-on-clear

LVI

Low-voltage detection^{Note 4}

WDT

WDT overflow

Notes 1. Priority is the vector interrupt servicing priority order when several maskable interrupt requests are

generated at the same time. 1 is the highest and 13 is the lowest.

2. Basic configuration types (A) and (B) correspond to (A) and (B) in Figure 13-1.

3. When bit 1 (LVIMD) of low-voltage detection register (LVIM) = 0 is selected.

4. When bit 1 (LVIMD) of low-voltage detection register (LVIM) = 1 is selected.

Caution No interrupt sources correspond to the vector table address 0014H.

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Figure 13-1. Basic Configuration of Interrupt Function

(A) Internal maskable interrupt

Internal bus

IE

MK

Vector table

address generator

IF

Interrupt request

Standby release signal

(B) External maskable interrupt

Internal bus

External interrupt mode

registers 0,1 (INTM0, INTM1)

MK

IE

Vector table

address generator

Edge

detector

Interrupt

request

IF

Standby

release signal

IF: Interrupt request flag

IE: Interrupt enable flag

MK: Interrupt mask flag

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CHAPTER 13 INTERRUPT FUNCTIONS

13.3 Interrupt Function Control Registers

The interrupt functions are controlled by the following four types of registers.

• Interrupt request flag registers 0, 1 (IF0, IF1)

• Interrupt mask flag registers 0, 1 (MK0, MK1)

• External interrupt mode registers 0, 1 (INTM0, INTM1)

• Program status word (PSW)

Table 13-2 lists interrupt requests, the corresponding interrupt request flags, and interrupt mask flags.

Table 13-2. Interrupt Request Signals and Corresponding Flags

Interrupt Request Signal

Interrupt Request Flag

Interrupt Mask Flag

INTLVI

INTP0

INTP1

LVIIF

LVIMK

PIF0

PMK0

PIF1

PMK1

INTTMH1

INTTM000

INTTM010

INTAD

TMIFH1

TMIF000

TMIF010

ADIF

TMMKH1

TMMK000

TMMK010

ADMK

INTP2

PIF2

PMK2

INTP3

PIF3

PMK3

INTTM80

INTSRE6

INTSR6

INTST6

TMIF80

SREIF6

SRIF6

STIF6

TMMK80

SREMK6

SRMK6

STMK6

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CHAPTER 13 INTERRUPT FUNCTIONS

(1) Interrupt request flag registers 0, 1 (IF0, IF1)

An interrupt request flag is set to 1 when the corresponding interrupt request is issued, or when the

instruction is executed. It is cleared to 0 by executing an instruction when the interrupt request is

acknowledged or when a reset signal is generated.

IF0 and IF1 are set with a 1-bit or 8-bit memory manipulation instruction.

Reset signal generation clears IF0 and IF1 to 00H.

Figure 13-2. Format of Interrupt Request Flag Registers 0, 1 (IF0, IF1)

Address: FFE0H After reset: 00H R/W

Symbol

IF0

<7>

<6>

<5>

<4>

<3>

<2>

<1>

0

ADIF

TMIF010 TMIF000 TMIFH1

PIF1

PIF0

LVIIF

Address: FFE1H After reset: 00H R/W

Symbol

IF1

7

0

<6>

<5>

<4>

<3>

<2>

<1>

0

STIF6

SRIF6

SREIF6

TMIF80

PIF3

PIF2

××IF×

Interrupt request flag

No interrupt request signal has been issued.

An interrupt request signal has been issued; an interrupt request status.

0

1

Caution Because P30, P31, P41, and P43 have an alternate function as external interrupt inputs,

when the output level is changed by specifying the output mode of the port function, an

interrupt request flag is set. Therefore, the interrupt mask flag should be set to 1 before

using the output mode.

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CHAPTER 13 INTERRUPT FUNCTIONS

(2) Interrupt mask flag registers 0, 1 (MK0, MK1)

The interrupt mask flag is used to enable and disable the corresponding maskable interrupts.

MK0 and MK1 are set with a 1-bit or 8-bit memory manipulation instruction.

Generation of reset signal sets MK0 and MK1 to FFH.

Figure 13-3. Format of Interrupt Mask Flag Registers 0, 1 (MK0, MK1)

Address: FFE4H After reset: FFH R/W

Symbol

MK0

<7>

<6>

<5>

<4>

<3>

<2>

<1>

0

1

ADMK

TMMK010 TMMK000 TMMKH1

PMK1

PMK0

LVIMK

Address: FFE5H After reset: FFH R/W

Symbol

MK1

7

1

<6>

<5>

<4>

<3>

<2>

<1>

0

1

STMK6

SRMK6 SREMK6 TMMK80

PMK3

PMK2

××MK×

Interrupt servicing control

0

1

Enables interrupt servicing.

Disables interrupt servicing.

Caution Because P30, P31, P41, and P43 have an alternate function as external interrupt inputs,

when the output level is changed by specifying the output mode of the port function, an

interrupt request flag is set. Therefore, the interrupt mask flag should be set to 1 before

using the output mode.

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(3) External interrupt mode register 0 (INTM0)

This register is used to set the valid edge of INTP0 to INTP2.

INTM0 is set with an 8-bit memory manipulation instruction.

Reset signal generation clears INTM0 to 00H.

Figure 13-4. Format of External Interrupt Mode Register 0 (INTM0)

Address: FFECH After reset: 00H R/W

Symbol

INTM0

7

6

5

4

3

2

1

0

ES21

ES20

ES11

ES10

ES01

ES00

ES21

ES20

INTP2 valid edge selection

INTP1 valid edge selection

INTP0 valid edge selection

0

1

0

1

0

1

Falling edge

Rising edge

Setting prohibited

Both rising and falling edges

ES11

ES10

0

1

0

1

0

1

Falling edge

Rising edge

Setting prohibited

Both rising and falling edges

ES01

ES00

0

1

0

1

0

1

Falling edge

Rising edge

Setting prohibited

Both rising and falling edges

Cautions 1. Be sure to clear bits 0 and 1 to 0.

2. Before setting the INTM0 register, be sure to set the corresponding interrupt mask flag

(××MK× = 1) to disable interrupts. After setting the INTM0 register, clear the interrupt

request flag (××IF× = 0), then clear the interrupt mask flag (××MK× = 0), which will

enable interrupts.

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(4) External interrupt mode register 1 (INTM1)

INTM1 is used to specify the valid edge for INTP3.

INTM1 is set with an 8-bit memory manipulation instruction.

Reset signal generation clears INTM1 to 00H.

Figure 13-5. Format of External Interrupt Mode Register 1 (INTM1)

Address: FFEDH After reset: 00H R/W

Symbol

INTM1

7

0

6

0

5

0

4

0

3

0

2

0

1

0

ES31

ES30

ES31

ES30

INTP3 valid edge selection

0

1

0

1

0

1

Falling edge

Rising edge

Setting prohibited

Both rising and falling edges

Cautions 1. Be sure to clear bits 2 to 7 to 0.

2. Before setting INTM1, set PMK3 to 1 to disable interrupts.

To enable interrupts, clear PIF3 to 0, then clear PMK3 to 0.

(5) Program status word (PSW)

The program status word is used to hold the instruction execution result and the current status of the interrupt

requests. The IE flag, used to enable and disable maskable interrupts, is mapped to PSW.

PSW can be read- and write-accessed in 8-bit units, as well as using bit manipulation instructions and

dedicated instructions (EI and DI). When a vectored interrupt is acknowledged, the PSW is automatically

saved to a stack, and the IE flag is reset to 0.

Generation of reset signal sets PSW to 02H.

Figure 13-6. Program Status Word (PSW) Configuration

Symbol

PSW

7

6

Z

5

0

4

3

0

2

0

1

0

After reset

02H

IE

AC

CY

Used in the execution of ordinary instructions

IE

0

Whether to enable/disable interrupt acknowledgment

Disabled

Enabled

1

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CHAPTER 13 INTERRUPT FUNCTIONS

13.4 Interrupt Servicing Operation

13.4.1 Maskable interrupt request acknowledgment operation

A maskable interrupt request can be acknowledged when the interrupt request flag is set to 1 and the

corresponding interrupt mask flag is cleared to 0. If the interrupt enabled status is in effect (when the IE flag is set to

1), then the request is acknowledged as a vector interrupt.

The time required to start the vectored interrupt servicing after a maskable interrupt request has been generated is

shown in Table 13-3.

See Figures 13-8 and 13-9 for the interrupt request acknowledgment timing.

Table 13-3. Time from Generation of Maskable Interrupt Request to Servicing

Minimum Time

9 clocks

Maximum Time^Note

19 clocks

Note The wait time is maximum when an interrupt

request is generated immediately before BT and

BF instructions.

1

f^CPU

Remark 1 clock:

(f^CPU: CPU clock)

When two or more maskable interrupt requests are generated at the same time, they are acknowledged starting

from the interrupt request assigned the highest priority.

A pending interrupt is acknowledged when a status in which it can be acknowledged is set.

Figure 13-7 shows the algorithm of interrupt request acknowledgment.

When a maskable interrupt request is acknowledged, the contents of the PSW and PC are saved to the stack in

that order, the IE flag is reset to 0, and the data in the vector table determined for each interrupt request is loaded to

the PC, and execution branches.

To return from interrupt servicing, use the RETI instruction.

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Figure 13-7. Interrupt Request Acknowledgment Processing Algorithm

Start

No

××IF = 1?

Yes (Interrupt request generated)

No

××MK = 0?

Yes

Interrupt request pending

No

IE = 1?

Yes

Vectored interrupt

servicing

××IF:

Interrupt request flag

××MK: Interrupt mask flag

IE:

Flag to control maskable interrupt request acknowledgment (1 = enable, 0 = disable)

Figure 13-8. Interrupt Request Acknowledgment Timing (Example of MOV A, r)

8 clocks

Clock

Saving PSW and PC, jump

Interrupt servicing program

CPU

MOV A, r

to interrupt servicing

Interrupt

If an interrupt request flag (××IF) is set before an instruction clock n (n = 4 to 10) under execution becomes n − 1,

the interrupt is acknowledged after the instruction under execution is complete. Figure 13-8 shows an example of the

interrupt request acknowledgment timing for an 8-bit data transfer instruction MOV A, r. Since this instruction is

executed for 4 clocks, if an interrupt occurs for 3 clocks after the instruction fetch starts, the interrupt acknowledgment

processing is performed after the MOV A, r instruction is executed.

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Figure 13-9. Interrupt Request Acknowledgment Timing (When Interrupt Request Flag Is Set at Last

Clock During Instruction Execution)

8 clocks

Clock

Interrupt

Saving PSW and PC, jump

servicing

CPU

NOP

MOV A, r

to interrupt servicing

program

Interrupt

If an interrupt request flag (××IF) is set at the last clock of the instruction, the interrupt acknowledgment processing

starts after the next instruction is executed.

Figure 13-9 shows an example of the interrupt request acknowledgment timing for an interrupt request flag that is

set at the second clock of NOP (2-clock instruction). In this case, the MOV A, r instruction after the NOP instruction is

executed, and then the interrupt acknowledgment processing is performed.

Caution Interrupt requests will be held pending while the interrupt request flag registers 0, 1 (IF0, IF1) or

interrupt mask flag registers 0, 1 (MK0, MK1) are being accessed.

13.4.2 Multiple interrupt servicing

In order to perform multiple interrupt servicing in which another interrupt is acknowledged while an interrupt is

being serviced, the interrupt mask function must be used to mask interrupts for which a low priority is to be set.

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CHAPTER 13 INTERRUPT FUNCTIONS

Figure 13-10. Example of Multiple Interrupts (1/2)

Example 1. Multiple interrupts are acknowledged

INTxx servicing

INTyy servicing

Main processing

IE = 0

EI

INTxx

INTyy

RETI

During interrupt INTxx servicing, interrupt request INTyy is acknowledged, and multiple interrupts are generated.

Before each interrupt request acknowledgment, the EI instruction is issued, the interrupt mask is released, and the

interrupt request acknowledgment enable state is set.

Caution Multiple interrupts can be acknowledged even for low-priority interrupts.

Example 2. Multiple interrupts are not generated because interrupts are not enabled

INTxx servicing

INTyy servicing

Main processing

EI

IE = 0

INTyy is held pending

INTyy

RETI

INTxx

IE = 0

RETI

Because interrupts are not enabled in interrupt INTxx servicing (the EI instruction is not issued), interrupt request

INTyy is not acknowledged, and multiple interrupts are not generated. The INTyy request is held pending and

acknowledged after the INTxx servicing is performed.

IE = 0: Interrupt request acknowledgment disabled

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Figure 13-10. Example of Multiple Interrupts (2/2)

Example 3. A priority is controlled by the multiple interrupts

The vector interrupt enable state is set for INTP0, INTP1, and INTTMH1.

(Interrupt priority INTP0 > INTP1 > INTTMH1 (refer to Table13-1))

INTTNH1 servicing

Main processing

INTP1 servicing

EI

IE = 0

PMK0 = 1

EI

IE = 0

INTTMH1

INTP0

INTP1

RETI

INTP0 servicing

PMK0 = 0

IE = 0

RETI

In the interrupt INTTMH1 servicing, servicing is performed such that the INTP1 interrupt is given priority, since the

INTP0 interrupt was first masked.

Afterwards, once the interrupt mask for INTP0 is released, INTP0 processing through multiple interrupts is

performed.

IE = 0: Interrupt request acknowledgment disabled

13.4.3 Interrupt request pending

Some instructions may keep pending the acknowledgment of an instruction request until the completion of the

execution of the next instruction even if the interrupt request (maskable interrupt and external interrupt) is generated

during the execution. The following shows such instructions (interrupt request pending instruction).

• Manipulation instruction for interrupt request flag registers 0, 1 (IF0, IF1)

• Manipulation instruction for interrupt mask flag registers 0, 1 (MK0, MK1)

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CHAPTER 14 STANDBY FUNCTION

14.1 Standby Function and Configuration

14.1.1 Standby function

Table 14-1. Relationship Between Operation Clocks in Each Operation Status

Status

Low-Speed Internal Oscillator

Note 2

System Clock

Clock Supplied to

Peripheral

Note 1

Hardware

Operation Mode

LSRSTOP = 0

LSRSTOP = 1

Reset

STOP

HALT

Stopped

Oscillating

Stopped

Oscillating^{Note 3}

Stopped

Oscillating

Notes 1. When “Cannot be stopped” is selected for low-speed internal oscillator by the option byte.

2. When it is selected that the low-speed internal oscillator “can be stopped by software”, oscillation of the

low-speed internal oscillator can be stopped by LSRSTOP.

3. If the operating clock of the watchdog timer is the low-speed internal oscillation clock, the watchdog

timer is stopped.

Caution The LSRSTOP setting is valid only when “Can be stopped by software” is set for the low-speed

internal oscillator by the option byte.

Remark LSRSTOP: Bit 0 of the low-speed internal oscillation mode register (LSRCM)

The standby function is designed to reduce the operating current of the system. The following two modes are

available.

(1) HALT mode

HALT instruction execution sets the HALT mode. In the HALT mode, the CPU operation clock is stopped.

Oscillation of the system clock oscillator continues. If the low-speed internal oscillator is operating before the

HALT mode is set, oscillation of the clock of the low-speed internal oscillator continues (refer to Table 14-1.

Oscillation of the low-speed internal oscillation clock (whether it cannot be stopped or can be stopped by

software) is set by the option byte). In this mode, the operating current is not decreased as much as in the

STOP mode, but the HALT mode is effective for restarting operation immediately upon interrupt request

generation and frequently carrying out intermittent operations.

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CHAPTER 14 STANDBY FUNCTION

(2) STOP mode

STOP instruction execution sets the STOP mode. In the STOP mode, the system clock oscillator stops,

stopping the whole system, thereby considerably reducing the CPU operating current.

Because this mode can be cleared by an interrupt request, it enables intermittent operations to be carried out.

However, select the HALT mode if processing must be immediately started by an interrupt request when the

operation stop time^Noteis generated after the STOP mode is released (because an additional wait time for

stabilizing oscillation elapses when crystal/ceramic oscillation is used).

Note The operation stop time is 17 μs (MIN.), 34 μs (TYP.), and 67 μs (MAX.).

In either of these two modes, all the contents of registers, flags and data memory just before the standby mode is

set are held. The I/O port output latches and output buffer statuses are also held.

Cautions 1. When shifting to the STOP mode, be sure to stop the peripheral hardware operation before

executing STOP instruction (except the peripheral hardware that operates on the low-speed

internal oscillation clock).

2. The following sequence is recommended for operating current reduction of the A/D converter

when the standby function is used: First clear bit 7 (ADCS) and bit 0 (ADCE) of the A/D

converter mode register (ADM) to 0 to stop the A/D conversion operation, and then execute

the HALT or STOP instruction.

3. If the low-speed internal oscillator is operating before the STOP mode is set, oscillation of the

low-speed internal oscillation clock cannot be stopped in the STOP mode (refer to Table 14-1).

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CHAPTER 14 STANDBY FUNCTION

14.1.2 Registers used during standby

The oscillation stabilization time after the standby mode is released is controlled by the oscillation stabilization time

select register (OSTS).

Remark For the registers that start, stop, or select the clock, see CHAPTER 5 CLOCK GENERATORS.

(1) Oscillation stabilization time select register (OSTS)

This register is used to select oscillation stabilization time of the clock supplied from the oscillator when the

STOP mode is released. The wait time set by OSTS is valid only when the crystal/ceramic oscillation clock is

selected as the system clock and after the STOP mode is released. If the high-speed internal oscillation or

external clock input is selected as the system clock source, no wait time elapses.

The system clock oscillator and the oscillation stabilization time that elapses after power application or release

of reset are selected by the option byte. For details, refer to CHAPTER 18 OPTION BYTE.

OSTS is set by using the 8-bit memory manipulation instruction.

Figure 14-1. Format of Oscillation Stabilization Time Select Register (OSTS)

Address: FFF4H After reset: Undefined R/W

Symbol

OSTS

7

0

6

0

5

0

4

0

3

0

2

0

1

0

OSTS1

OSTS0

OSTS1

OSTS0

Selection of oscillation stabilization time

0

1

0

1

0

1

2¹⁰/fX (102.4 μs)

2¹²/fX (409.6 μs)

2¹⁵/fX (3.27 ms)

2¹⁷/fX (13.1 ms)

Cautions 1. To set and then release the STOP mode, set the oscillation stabilization time as follows.

Expected oscillation stabilization time of resonator ≤ Oscillation stabilization time set

by OSTS

2. The wait time after the STOP mode is released does not include the time from the

release of the STOP mode to the start of clock oscillation (“a” in the figure below),

regardless of whether STOP mode was released by reset signal generation or interrupt

generation.

STOP mode is released

Voltage

waveform

of X1 pin

a

3. The oscillation stabilization time that elapses on power application or after release of

reset is selected by the option byte. For details, refer to CHAPTER 18 OPTION BYTE.

Remarks 1. ( ): f^X= 10 MHz

2. Determine the oscillation stabilization time of the resonator by checking the characteristics of

the resonator to be used.

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CHAPTER 14 STANDBY FUNCTION

14.2 Standby Function Operation

14.2.1 HALT mode

(1) HALT mode

The HALT mode is set by executing the HALT instruction.

The operating statuses in the HALT mode are shown below.

Caution Because an interrupt request signal is used to clear the standby mode, if there is an interrupt

source with the interrupt request flag set and the interrupt mask flag clear, the standby mode

is immediately cleared if set.

Table 14-2. Operating Statuses in HALT Mode

Setting of HALT Mode

Low-Speed Internal

Oscillator Cannot Be

Stopped^Note

Low-Speed Internal Oscillator Can Be Stopped^Note

When Low-Speed Internal When Low-Speed Internal

Item

Oscillation Continues

Oscillation Stops

System clock

CPU

Clock supply to CPU is stopped.

Operation stops.

Port (latch)

Holds status before HALT mode was set.

16-bit timer/event counter 00

8-bit timer 80

Operable

8-bit timer

H1

Sets count clock to fXP to fXP/2¹²Operable

Sets count clock to f^RL/2⁷

Operable

Operation stops.

Watchdog

timer

System clock selected as

operating clock

Setting prohibited

Operation stops.

“Low-speed internal oscillation

clock” selected as operating

clock

Operable (Operation

continues.)

Operation stops.

A/D converter

Operable

Serial interface UART6

Power-on-clear circuit

Low-voltage detector

External interrupt

Operable

Always operates.

Operable

Note “Cannot be stopped” or “Stopped by software” is selected for low-speed internal oscillator by the option byte

(for the option byte, see CHAPTER 18 OPTION BYTE).

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CHAPTER 14 STANDBY FUNCTION

(2) HALT mode release

The HALT mode can be released by the following two sources.

(a) Release by unmasked interrupt request

When an unmasked interrupt request is generated, the HALT mode is released. If interrupt

acknowledgment is enabled, vectored interrupt servicing is carried out. If interrupt acknowledgment is

disabled, the next address instruction is executed.

Figure 14-2. HALT Mode Release by Interrupt Request Generation

Interrupt

request

HALT

instruction

Wait

Standby

release signal

Operating mode

HALT mode

Operating mode

Status of CPU

Oscillation

System clock

oscillation

Remarks 1. The broken lines indicate the case when the interrupt request which has released the

standby mode is acknowledged.

2. The wait time is as follows:

• When vectored interrupt servicing is carried out: 11 to 13 clocks

• When vectored interrupt servicing is not carried out: 3 to 5 clocks

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CHAPTER 14 STANDBY FUNCTION

(b) Release by reset signal generation

When the reset signal is generated, HALT mode is released, and then, as in the case with a normal reset

operation, the program is executed after branching to the reset vector address.

Figure 14-3. HALT Mode Release by Reset Signal Generation

(1) When CPU clock is high-speed internal oscillation clock or external input clock

HALT

instruction

Reset signal

Operation

stops^Note

Reset

period

Operation

mode

CPU status

HALT mode

Oscillates

Operation mode

Oscillates

Oscillation stops

System clock

oscillation

Note Operation is stopped (277 μs (MIN.), 544 μs (TYP.), 1.075 ms (MAX.)) because the option byte is

referenced.

(2) When CPU clock is crystal/ceramic oscillation clock

HALT

instruction

Reset signal

Oscillation

stabilization waits

Operation

stops^Note

Reset

period

Operation

mode

Operation

mode

CPU status

HALT mode

Oscillates

Oscillation stops

Oscillates

System clock

oscillation

Oscillation stabilization time

(2¹⁰/f to 2¹⁷/f

X

X)

Note Operation is stopped (276 μs (MIN.), 544 μs (TYP.), 1.074 ms (MAX.)) because the option byte is

referenced.

Remark f^X: System clock oscillation frequency

Table 14-3. Operation in Response to Interrupt Request in HALT Mode

Release Source

MK××

IE

0

Operation

Next address instruction execution

Interrupt servicing execution

HALT mode held

Maskable interrupt request

0

1

−

1

×

Reset signal generation

×

Reset processing

×: don’t care

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CHAPTER 14 STANDBY FUNCTION

14.2.2 STOP mode

(1) STOP mode setting and operating statuses

The STOP mode is set by executing the STOP instruction.

Caution Because an interrupt request signal is used to clear the standby mode, if there is an interrupt

source with the interrupt request flag set and the interrupt mask flag reset, the standby

mode is immediately cleared if set. Thus, in the STOP mode, the normal operation mode is

restored after the STOP instruction is executed and then the operation is stopped for 34 μs

(TYP.) (after an additional wait time for stabilizing the oscillation set by the oscillation

stabilization time select register (OSTS) has elapsed when crystal/ceramic oscillation is

used).

The operating statuses in the STOP mode are shown below.

Table 14-4. Operating Statuses in STOP Mode

Setting of HALT Mode

Low-Speed Internal

Oscillator Cannot Be

Stopped^Note

Low-Speed Internal Oscillator Can Be Stopped^Note

When Low-Speed Internal When Low-Speed Internal

Item

Oscillation Continues

Oscillation Stops

System clock

CPU

Oscillation stops.

Operation stops.

Port (latch)

Holds status before STOP mode is set.

Operation stops.

16-bit timer/event counter 00

8-bit timer 80

Operation stops.

8-bit timer

H1

Sets count clock to fXP to fXP/2¹²Operation stops.

Sets count clock to f^RL/2⁷

Operable

Operation stops.

Watchdog

timer

“Clock to peripheral hardware” Setting prohibited

selected as operating clock

Operation stops.

“Low-speed internal oscillation Operable (Operation

Operation stops.

clock” selected as operating

clock

continues.)

A/D converter

Operation stops.

Always operates.

Operable

Serial interface UART6

Power-on-clear circuit

Low-voltage detector

External interrupt

Operable

Note “Cannot be stopped” or “Stopped by software” is selected for low-speed internal oscillator by the option byte

(for the option byte, see CHAPTER 18 OPTION BYTE).

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CHAPTER 14 STANDBY FUNCTION

(2) STOP mode release

Figure 14-4. Operation Timing When STOP Mode Is Released

<1> If high-speed internal oscillation clock or external input clock is selected as system clock to be supplied

STOP mode

is released.

STOP mode

System clock

oscillation

CPU clock

Operation

High-speed internal oscillation clock or external clock input

stops^Note

.

<2> If crystal/ceramic oscillation clock is selected as system clock to be supplied

STOP mode

is released.

STOP mode

System clock

oscillation

CPU clock

HALT status

(oscillation stabilization time set by OSTS)

Operation

stops^Note

Crystal/ceramic oscillation clock

.

Note The operation stop time is 17 μs (MIN.), 34 μs (TYP.), and 67 μs (MAX.).

The STOP mode can be released by the following two sources.

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CHAPTER 14 STANDBY FUNCTION

(a) Release by unmasked interrupt request

When an unmasked interrupt request (8-bit timer H1^Note, low-voltage detector, external interrupt request) is

generated, the STOP mode is released. After the oscillation stabilization time has elapsed, if interrupt

acknowledgment is enabled, vectored interrupt servicing is carried out. If interrupt acknowledgment is

disabled, the next address instruction is executed.

Note Only when sets count clock to f^RL/2⁷

Figure 14-5. STOP Mode Release by Interrupt Request Generation

(1) If CPU clock is high-speed internal oscillation clock or external input clock

Interrupt

request

STOP

instruction

Standby release

signal

Operation

mode

Operation

stops^Note

STOP mode

Operation mode

Oscillation

.

CPU status

Oscillation stops.

Oscillation

System clock

oscillation

(2) If CPU clock is crystal/ceramic oscillation clock

Interrupt

request

STOP

instruction

Standby release

signal

Operation

mode

Waiting for stabilization

.

of oscillation

Operation

mode

stops^Note

CPU status

STOP mode

(HALT mode status)

Oscillation

Oscillation stops.

Oscillation

System clock

Oscillation stabilization time

(set by OSTS)

Note The operation stop time is 17 μs (MIN.), 34 μs (TYP.), and 67 μs (MAX.).

Remark The broken lines indicate the case when the interrupt request that has released the standby mode is

acknowledged.

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CHAPTER 14 STANDBY FUNCTION

(b) Release by reset signal generation

When the reset signal is generated, STOP mode is released and a reset operation is performed after the

oscillation stabilization time has elapsed.

Figure 14-6. STOP Mode Release by Reset Signal Generation

(1) If CPU clock is high-speed internal oscillation clock or external input clock

STOP

instruction

Reset signal

Operation

stops^Note

Reset

period

Operation

mode

CPU status

STOP mode

.

Operation mode

Oscillation

System clock

oscillation

Oscillation

Oscillation stops.

Note Operation is stopped (277 μs (MIN.), 544 μs (TYP.), 1.075 ms (MAX.)) because the option byte is

referenced.

(2) If CPU clock is crystal/ceramic oscillation clock

STOP

instruction

Reset signal

Reset

period

Oscillation

Operation

mode

Operation

mode

stops^Note

.

stabilization waits

CPU status

STOP mode

Oscillation

Oscillation stops.

Oscillation

System clock

oscillation

Oscillation stabilization time

(2¹⁰/f to 2¹⁷/f

X

X)

Note Operation is stopped (276 μs (MIN.), 544 μs (TYP.), 1.074 ms (MAX.)) because the option byte is

referenced.

Remark f^X: System clock oscillation frequency

Table 14-5. Operation in Response to Interrupt Request in STOP Mode

Release Source

MK××

IE

0

Operation

Next address instruction execution

Interrupt servicing execution

STOP mode held

Maskable interrupt request

0

1

−

1

×

Reset signal generation

×

Reset processing

×: don’t care

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CHAPTER 15 RESET FUNCTION

The following four operations are available to generate a reset signal.

(1) External reset input via RESET pin

(2) Internal reset by watchdog timer overflows

(3) Internal reset by comparison of supply voltage and detection voltage of power-on-clear (POC) circuit

(4) Internal reset by comparison of supply voltage and detection voltage of low-power-supply detector (LVI)

External and internal resets have no functional differences. In both cases, program execution starts from the

programs at the address written in addresses 0000H and 0001H when the reset signal is generated.

A reset is applied when a low level is input to the RESET pin, the watchdog timer overflows, or by POC and LVI

circuit voltage detection, and each item of hardware is set to the status shown in Table 15-1. Each pin is high

impedance during reset signal generation or during the oscillation stabilization time just after reset release, except for

P130, which is low-level output.

When a low level is input to the RESET pin, a reset occurs, and when a high level is input to the RESET pin, the

reset is released and the CPU starts program execution after referencing the option byte (after the option byte is

referenced and the clock oscillation stabilization time elapses if crystal/ceramic oscillation is selected). A reset

generated by the watchdog timer source is automatically released after the reset, and the CPU starts program

execution after referencing the option byte (after the option byte is referenced and the clock oscillation stabilization

time elapses if crystal/ceramic oscillation is selected). (see Figures 15-2 to 15-4). Reset by POC and LVI circuit

power supply detection is automatically released when V^DD> VPOC or VDD > VLVI after the reset, and the CPU starts

program execution after referencing the option byte (after the option byte is referenced and the clock oscillation

stabilization time elapses if crystal/ceramic oscillation is selected) (see CHAPTER 16 POWER-ON-CLEAR CIRCUIT

and CHAPTER 17 LOW-VOLTAGE DETECTOR).

Cautions 1. For an external reset, input a low level for 2 μs or more to the RESET pin.

2. During reset signal generation, the system clock and low-speed internal oscillation clock

stop oscillating.

3. When the RESET pin is used as an input-only port pin (P34), the 78K0S/KB1+ is reset if a low

level is input to the RESET pin after reset is released by the POC circuit, the LVI circuit and

the watchdog timer and before the option byte is referenced again. The reset status is

retained until a high level is input to the RESET pin.

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CHAPTER 15 RESET FUNCTION

Figure 15-1. Block Diagram of Reset Function

Internal bus

Reset control flag register (RESF)

WDTRF

Clear

LVIRF

Set

Set Clear

Reset signal of WDT

Reset signal to LVIM/LVIS register

RESET

Reset signal of POC

Reset signal of LVI

Internal reset signal

Caution The LVI circuit is not reset by the internal reset signal of the LVI circuit.

Remarks 1. LVIM: Low-voltage detect register

2. LVIS: Low-voltage detection level select register

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Figure 15-2. Timing of Reset by RESET Input

<1> With high-speed internal oscillation clock or external clock input

High-speed internal oscillation clock or

external clock input

Normal operation

in progress

Reset period

(oscillation stops)

CPU clock

Normal operation (reset processing, CPU clock)

Operation stops because option

RESET

byte is referenced^{Note 1}

.

Internal reset signal

Delay

100 ns (TYP.)

Delay

100 ns (TYP.)

Hi-Z

Port pin

(except P130)

Port pin

(P130)

Note 2

Notes 1. The operation stop time is 277 μs (MIN.), 544 μs (TYP.), and 1.075 ms (MAX.).

2. Set high level output using software.

Remark When reset is effected, P130 outputs a low level. If P130 is set to output a high level before reset is

effected, the output signal of P130 can be dummy-output as the reset signal to the CPU.

<2> With crystal/ceramic oscillation clock

Crystal/ceramic

oscillation clock

Oscillation stabilization

Normal operation

(reset processing, CPU clock)

Normal operation

in progress

Reset period

(oscillation stops)

time (2¹⁰/f

X

to 2¹⁷/f

)

X

RESET

Operation stops because option

byte is referenced^{Note 1}

.

Internal reset signal

Delay

100 ns (TYP.)

Delay

100 ns (TYP.)

Hi-Z

Port pin

(except P130)

Port pin

(P130)

Note 2

Notes 1. The operation stop time is 276 μs (MIN.), 544 μs (TYP.), and 1.074 ms (MAX.).

2. Set high level output using software.

Remarks 1. f^X: System clock oscillation frequency

2. When reset is effected, P130 outputs a low level. If P130 is set to output a high level before reset is

effected, the output signal of P130 can be dummy-output as the reset signal to the CPU.

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CHAPTER 15 RESET FUNCTION

Figure 15-3. Timing of Reset by Overflow of Watchdog Timer

<1> With high-speed internal oscillation clock or external clock input

High-speed internal oscillation clock or

external clock input

Reset period

(oscillation stops)

Normal operation

in progress

Normal operation (reset processing, CPU clock)

Operation stops because option

CPU clock

Watchdog overflow

byte is referenced^{Note 1}

.

Internal reset signal

Port pin

Hi-Z

(except P130)

Port pin

(P130)

Note 2

Notes 1. The operation stop time is 277 μs (MIN.), 544 μs (TYP.), and 1.075 ms (MAX.).

2. Set high level output using software.

Caution The watchdog timer is also reset in the case of an internal reset of the watchdog timer.

Remark When reset is effected, P130 outputs a low level. If P130 is set to output a high level before reset is

effected, the output signal of P130 can be dummy-output as the reset signal to the CPU.

<2> With crystal/ceramic oscillation clock

Crystal/ceramic

oscillation clock

Normal operation

(reset processing, CPU clock)

Normal operation

in progress

Reset period

(oscillation stops)

Oscillation stabilization

time (2¹⁰/fX to 2¹⁷/fX)

CPU clock

Operation stops because option

byte is referenced^{Note 1}

Watchdog overflow

.

Internal reset signal

Hi-Z

Port pin

(except P130)

Port pin

(P130)

Note 2

Notes 1. The operation stop time is 276 μs (MIN.), 544 μs (TYP.), and 1.074 ms (MAX.).

2. Set high level output using software.

Caution The watchdog timer is also reset in the case of an internal reset of the watchdog timer.

Remarks 1. f^X: System clock oscillation frequency

2. When reset is effected, P130 outputs a low level. If P130 is set to output a high level before reset is

effected, the output signal of P130 can be dummy-output as the reset signal to the CPU.

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CHAPTER 15 RESET FUNCTION

Figure 15-4. Reset Timing by RESET Input in STOP Mode

<1> With high-speed internal oscillation clock or external clock input

STOP instruction is executed.

High-speed internal oscillation clock or

external clock input

Normal

operation

in progress

Stop status

Reset period

(oscillation stops) (oscillation stops)

Normal operation (reset processing, CPU clock)

Operation stops because option

CPU clock

RESET

byte is referenced^{Note 1}

.

Internal reset signal

Delay

100 ns (TYP.)

Delay

100 ns (TYP.)

Hi-Z

Port pin

(except P130)

Port pin

(P130)

Note 2

Notes 1. The operation stop time is 277 μs (MIN.), 544 μs (TYP.), and 1.075 ms (MAX.).

2. Set high level output using software.

Remark When reset is effected, P130 outputs a low level. If P130 is set to output a high level before reset is

effected, the output signal of P130 can be dummy-output as the reset signal to the CPU.

<2> With crystal/ceramic oscillation clock

STOP instruction is executed.

Crystal/ceramic

oscillation clock

Normal

operation

in progress

Oscillation stabilization

Stop status

(oscillation stops)

Reset period

(oscillation stops)

Normal operation

(reset processing, CPU clock)

CPU clock

RESET

time (2¹⁰/f

X

to 2¹⁷/f

)

X

Operation stops because option

byte is referenced^{Note 1}

.

Internal reset signal

Delay

100 ns (TYP.)

Hi-Z

Port pin

(except P130)

Port pin

(P130)

Note 2

Notes 1. The operation stop time is 276 μs (MIN.), 544 μs (TYP.), and 1.074 ms (MAX.).

2. Set high level output using software.

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CHAPTER 15 RESET FUNCTION

Remarks 1. For the reset timing of the power-on-clear circuit and low-voltage detector, refer to CHAPTER 16

POWER-ON-CLEAR CIRCUIT and CHAPTER 17 LOW-VOLTAGE DETECTOR.

2. f^X: System clock oscillation frequency

3. When reset is effected, P130 outputs a low level. If P130 is set to output a high level before reset is

effected, the output signal of P130 can be dummy-output as the reset signal to the CPU.

Table 15-1. Hardware Statuses After Reset Acknowledgment (1/2)

Hardware

Status After Reset

Program counter (PC)^{Note 1}

Contents of reset vector

table (0000H and

0001H) are set.

Stack pointer (SP)

Program status word (PSW)

RAM

Undefined

02H

Undefined ^{Note 2}

00H

Data memory

General-purpose registers

Ports (P0, P2 to P4, P12, P13) (output latches)

Port mode registers (PM0, PM2 to PM4, PM12)

Port mode control register (PMC2)

FFH

00H

Pull-up resistor option registers (PU0, PU2, PU3, PU4, PU12)

Processor clock control register (PCC)

00H

02H

Preprocessor clock control register (PPCC)

Low-speed internal oscillation mode register (LSRCM)

Oscillation stabilization time select register (OSTS)

02H

00H

Undefined

0000H

00H

16-bit timer 00

Timer counter 00 (TM00)

Capture/compare registers 000, 010 (CR000, CR010)

Mode control register 00 (TMC00)

Prescaler mode register 00 (PRM00)

Capture/compare control register 00 (CRC00)

00H

Timer output control register 00 (TOC00)

Timer counter 80 (TM80)

00H

8-bit timer 80

00H

Compare register (CR80)

Undefined

00H

Mode control register 80 (TMC80)

Compare registers (CMP01, CMP11)

Mode register 1 (TMHMD1)

8-bit timer H1

Watchdog timer

A/D converter

00H

Mode register (WDTM)

67H

Enable register (WDTE)

9AH

Conversion result registers (ADCR, ADCRH)

Mode register (ADM)

Undefined

00H

Analog input channel specification register (ADS)

00H

Notes 1. Only the contents of PC are undefined while reset signal generation and while the oscillation stabilization

time elapses. The statuses of the other hardware units remain unchanged.

2. The status after reset is held in the standby mode.

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Table 15-1. Hardware Statuses After Reset Acknowledgment (2/2)

Hardware

Status After Reset

FFH

Serial interface UART6

Receive buffer register 6 (RXB6)

Transmit buffer register 6 (TXB6)

Asynchronous serial interface operation mode register 6 (ASIM6)

01H

00H

Asynchronous serial interface reception error status register 6

(ASIS6)

Asynchronous serial interface transmission error status register 6

(ASIF6)

00H

Clock select register 6 (CKSR6)

00H

FFH

16H

Baud rate generator control register 6 (BRGC6)

Asynchronous serial interface control register 6 (ASICL6)

Input select control register (ISC)

00H

Multiplier

16-bit Multiplication result storage register (MUL0)

Data registers (MRA0, MRB0)

Undefined

00H

Control register (MULC0)

00H^Note

00H

Reset function

Reset control flag register (RESF)

Low-voltage detector

Low-voltage detection register (LVIM)

Low-voltage detection level select register (LVIS)

Request flag registers (IF0, IF1)

Interrupt

Mask flag registers (MK0, MK1)

FFH

External interrupt mode registers (INTM0, INTM1)

Flash protect command register (PFCMD)

Flash status register (PFS)

00H

Flash memory

Undefined

00H

Flash programming mode control register (FLPMC)

Flash programming command register (FLCMD)

Flash address pointer L (FLAPL)

Undefined

00H

Undefined

Flash address pointer H (FLAPH)

Flash address pointer H compare register (FLAPHC)

Flash address pointer L compare register (FLAPLC)

Flash write buffer register (FLW)

00H

Note These values change as follows depending on the reset source.

Reset Source

RESET Input

Cleared (0)

Reset by POC

Cleared (0)

Reset by WDT

Reset by LVI

Register

RESF

WDTRF

LVIRF

Set (1)

Held

Set (1)

Held

LVIM

LVIS

Cleared (00H)

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CHAPTER 15 RESET FUNCTION

15.1 Register for Confirming Reset Source

Many internal reset generation sources exist in the 78K0S/KB1+. The reset control flag register (RESF) is used to

store which source has generated the reset request.

RESF can be read by an 8-bit memory manipulation instruction.

Reset signal generation by RESET input or power-on-clear (POC) circuit, and reading RESF clear RESF to 00H.

Figure 15-5. Format of Reset Control Flag Register (RESF)

Address: FF54H After reset: 00H^Note

R

Symbol

RESF

7

0

6

0

5

0

4

3

0

2

0

1

0

WDTRF

LVIRF

WDTRF

Internal reset request by watchdog timer (WDT)

0

1

Internal reset request is not generated, or RESF is cleared.

Internal reset request is generated.

LVIRF

Internal reset request by low-voltage detector (LVI)

Internal reset request is not generated, or RESF is cleared.

Internal reset request is generated.

0

1

Note The value after reset varies depending on the reset source.

Caution Do not read data by a 1-bit memory manipulation instruction.

The status of RESF when a reset request is generated is shown in Table 15-2.

Table 15-2. RESF Status When Reset Request Is Generated

Reset Source

RESET Input

Cleared (0)

Reset by POC

Cleared (0)

Reset by WDT

Reset by LVI

Flag

WDTRF

LVIRF

Set (1)

Held

Set (1)

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CHAPTER 16 POWER-ON-CLEAR CIRCUIT

16.1 Functions of Power-on-Clear Circuit

The power-on-clear circuit (POC) has the following functions.

•

Generates internal reset signal at power on.

Compares supply voltage (V^DD) and detection voltage (VPOC = 2.1 V (TYP.)), and generates internal reset signal

when V^DD< VPOC.

•

Compares supply voltage (V^DD) and detection voltage (VPOC = 2.1 V (TYP.)), and releases internal reset signal

when VDD ≥ VPOC.

Cautions 1. If an internal reset signal is generated in the POC circuit, the reset control flag register

(RESF) is cleared to 00H.

2. Use these products in the following voltage range because the detection voltage (V^POC) of the

POC circuit is the supply voltage range.

Standard product, (A) grade product: 2.2 to 5.5 V, (A2) grade product: 2.26 to 5.5 V

Remark This product incorporates multiple hardware functions that generate an internal reset signal. A flag that

indicates the reset cause is located in the reset control flag register (RESF) for when an internal reset

signal is generated by the watchdog timer (WDT) or low-voltage-detection (LVI) circuit. RESF is not

cleared to 00H and the flag is set to 1 when an internal reset signal is generated by WDT or LVI.

For details of RESF, see CHAPTER 15 RESET FUNCTION.

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CHAPTER 16 POWER-ON-CLEAR CIRCUIT

16.2 Configuration of Power-on-Clear Circuit

The block diagram of the power-on-clear circuit is shown in Figure 16-1.

Figure 16-1. Block Diagram of Power-on-Clear Circuit

VDD

+

Internal reset signal

−

Reference

voltage

source

16.3 Operation of Power-on-Clear Circuit

In the power-on-clear circuit, the supply voltage (V^DD) and detection voltage (VPOC = 2.1 V (TYP.)) are compared,

and an internal reset signal is generated when V^DD< VPOC, and an internal reset is released when VDD ≥ VPOC.

Figure 16-2. Timing of Internal Reset Signal Generation in Power-on-Clear Circuit

Supply voltage (V^DD

)

POC detection voltage

(V^POC= 2.1 V (TYP.))

Time

Internal reset signal

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CHAPTER 16 POWER-ON-CLEAR CIRCUIT

16.4 Cautions for Power-on-Clear Circuit

In a system where the supply voltage (VDD) fluctuates for a certain period in the vicinity of the POC detection

voltage (V^POC), the system may be repeatedly reset and released from the reset status. In this case, the time from

release of reset to the start of the operation of the microcontroller can be arbitrarily set by taking the following action.

After releasing the reset signal, wait for the supply voltage fluctuation period of each system by means of a

software counter that uses a timer, and then initialize the ports.

Figure 16-3. Example of Software Processing After Release of Reset (1/2)

• If supply voltage fluctuation is 50 ms or less in vicinity of POC detection voltage

Reset

; Check reset source^{Note 2}

Initialization of ports

processing <1>

Setting WDT

Initialization

Power-on-clear

; f^XP= High-speed internal oscillation clock (8.4 MHz (MAX.))/2²(default value)

Source: f^XP(2.1 MHz (MAX.))/2¹²,

Setting 8-bit timer H1

51 ms when the compare value is 25

(50 ms is measured)

Timer starts (TMHE1 = 1)

Clears WDT

Note 1

No

50 ms has passed?

(TMIFH1 = 1?)

Yes

; Setting the division ratio of the system clock,

timer, A/D converter, etc.

Initialization

processing <2>

Notes 1. If reset is generated again during this period, initialization processing <2> is not started.

2. A flowchart is shown on the next page.

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Figure 16-3. Example of Software Processing After Release of Reset (2/2)

• Checking reset cause

Check reset source

Yes

WDTRF of RESF

register = 1?

No

Reset processing by

watchdog timer

Yes

LVIRF of RESF

register = 1?

No

Reset processing by low-voltage

detector

Power-on-clear/external

reset generated

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CHAPTER 17 LOW-VOLTAGE DETECTOR

17.1 Functions of Low-Voltage Detector

The low-voltage detector (LVI) has following functions.

•

Compares supply voltage (V^DD) and detection voltage (VLVI), and generates an internal interrupt signal or

internal reset signal when VDD < VLVI.

•

Detection levels (ten levels) of supply voltage can be changed by software.

Interrupt or reset function can be selected by software.

Operable in STOP mode.

When the low-voltage detector is used to reset, bit 0 (LVIRF) of the reset control flag register (RESF) is set to 1 if

reset occurs. For details of RESF, refer to CHAPTER 15 RESET FUNCTION.

17.2 Configuration of Low-Voltage Detector

The block diagram of the low-voltage detector is shown in Figure 17-1.

Figure 17-1. Block Diagram of Low-Voltage Detector

V

DD

V

DD

N-ch

Internal reset signal

+

−

INTLVI

Reference

voltage source

4

LVION LVIMD LVIF

LVIS3 LVIS2 LVIS1 LVIS0

Low-voltage detection

level select register (LVIS)

Low-voltage detect

register (LVIM)

Internal bus

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CHAPTER 17 LOW-VOLTAGE DETECTOR

17.3 Registers Controlling Low-Voltage Detector

The low-voltage detector is controlled by the following registers.

•

Low-voltage detect register (LVIM)

Low-voltage detection level select register (LVIS)

(1) Low-voltage detect register (LVIM)

This register sets low-voltage detection and the operation mode.

This register can be set by a 1-bit or 8-bit memory manipulation instruction.

Reset signal generation clears this register to 00H^{Note 1}

.

Figure 17-2. Format of Low-Voltage Detect Register (LVIM)

Address: FF50H After reset: 00H^{Note 1}R/W^{Note 2}

<7>

6

0

5

0

4

0

3

0

2

0

<1>

<0>

Symbol

LVIM

LVION

LVIMD

LVIF

LVION^{Note 3}

Enabling low-voltage detection operation

0

1

Disable operation

Enable operation

LVIMD

Low-voltage detection operation mode selection

Generate interrupt signal when supply voltage (VDD) < detection voltage (VLVI)

0

1

Generate internal reset signal when supply voltage (VDD) < detection voltage (VLVI)

LVIF^{Note 4}

Low-voltage detection flag

Supply voltage (VDD) ≥ detection voltage (VLVI), or when operation is disabled

Supply voltage (VDD) < detection voltage (VLVI)

0

1

Notes 1. Retained only after a reset by LVI.

2. Bit 0 is a read-only bit.

3. When LVION is set to 1, operation of the comparator in the LVI circuit is started. Use

software to instigate a wait of at least 0.2 ms from when LVION is set to 1 until the voltage is

confirmed at LVIF.

4. The value of LVIF is output as the interrupt request signal INTLVI when LVION = 1 and

LVIMD = 0.

Cautions 1. To stop LVI, follow either of the procedures below.

• When using 8-bit manipulation instruction: Write 00H to LVIM.

• When using 1-bit memory manipulation instruction: Clear LVION to 0.

2. Be sure to set bits 2 to 6 to 0.

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CHAPTER 17 LOW-VOLTAGE DETECTOR

(2) Low-voltage detection level select register (LVIS)

This register selects the low-voltage detection level.

This register can be set by an 8-bit memory manipulation instruction.

Reset signal generation clears this register to 00H^Note

.

Figure 17-3. Format of Low-Voltage Detection Level Select Register (LVIS)

Address: FF51H, After reset: 00H^NoteR/W

Symbol

LVIS

7

0

6

0

5

0

4

0

3

2

1

0

LVIS3

LVIS2

LVIS1

LVIS0

LVIS3

LVIS2

LVIS1

LVIS0

Detection level

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

VLVI0 (4.3 V 0.2 V)

VLVI1 (4.1 V 0.2 V)

VLVI2 (3.9 V 0.2 V)

VLVI3 (3.7 V 0.2 V)

VLVI4 (3.5 V 0.2 V)

VLVI5 (3.3 V 0.15 V)

VLVI6 (3.1 V 0.15 V)

VLVI7 (2.85 V 0.15 V)

VLVI8 (2.6 V 0.1 V)

VLVI9 (2.35 V 0.1 V)

Setting prohibited

Other than above

Note Retained only after a reset by LVI.

Cautions 1. Bits 4 to 7 must be set to 0.

2. If values other than same values are written during LVI operation, the value

becomes undefined at the very moment it is written, and thus be sure to stop LVI

(bit 7 of LVIM register (LVION) = 0) before writing.

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CHAPTER 17 LOW-VOLTAGE DETECTOR

17.4 Operation of Low-Voltage Detector

The low-voltage detector can be used in the following two modes.

•

Used as reset

Compares the supply voltage (V^DD) and detection voltage (VLVI), and generates an internal reset signal when

V^DD< VLVI, and releases internal reset when VDD ≥ VLVI.

Used as interrupt

Compares the supply voltage (V^DD) and detection voltage (VLVI), and generates an interrupt signal (INTLVI)

when V^DD< VLVI.

The operation is set as follows.

(1) When used as reset

•

When starting operation

<1> Mask the LVI interrupt (LVIMK = 1).

<2> Set the detection voltage using bits 3 to 0 (LVIS3 to LVIS0) of the low-voltage detection level select

register (LVIS).

<3> Set bit 7 (LVION) of LVIM to 1 (enables LVI operation).

<4> Use software to instigate a wait of at least 0.2 ms.

<5> Wait until “supply voltage (V^DD) ≥ detection voltage (VLVI)” at bit 0 (LVIF) of LVIM is confirmed.

<6> Set bit 1 (LVIMD) of LVIM to 1 (generates internal reset signal when supply voltage (V^DD) < detection

voltage (V^LVI)).

Figure 17-4 shows the timing of generating the internal reset signal of the low-voltage detector. Numbers <1>

to <6> in this figure correspond to <1> to <6> above.

Cautions 1. <1> must always be executed. When LVIMK = 0, an interrupt may occur immediately

after the processing in <3>.

2. If supply voltage (V^DD) ≥ detection voltage (VLVI) when LVIM is set to 1, an internal reset

signal is not generated.

•

When stopping operation

Either of the following procedures must be executed.

•

When using 8-bit memory manipulation instruction: Write 00H to LVIM.

•

When using 1-bit memory manipulation instruction: Clear LVIMD to 0 and LVION to 0 in that order.

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Figure 17-4. Timing of Low-Voltage Detector Internal Reset Signal Generation

Supply voltage (V^DD

)

LVI detection voltage

(V^LVI

POC detection voltage

(V^POC

)

<2>

H

Time

LVIMK flag

(set by software)

<1>

Note 1

LVION flag

(set by software)

Not cleared

<3>

Clear

<4> 0.2 ms or longer

LVIF flag

<5>

Clear

Note 2

LVIMD flag

(set by software)

Not cleared

<6>

LVIRF flag^{Note 3}

LVI reset signal

Cleared by

software

Cleared by

software

POC reset signal

Internal reset signal

Notes 1. The LVIMK flag is set to “1” by reset signal generation.

2. The LVIF flag may be set (1).

3. LVIRF is bit 0 of the reset control flag register (RESF). For details of RESF, refer to CHAPTER 15

RESET FUNCTION.

Remark <1> to <6> in Figure 17-4 above correspond to <1> to <6> in the description of “when starting operation”

in 17.4 (1) When used as reset.

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CHAPTER 17 LOW-VOLTAGE DETECTOR

(2) When used as interrupt

When starting operation

•

<1> Mask the LVI interrupt (LVIMK = 1).

<2> Set the detection voltage using bits 3 to 0 (LVIS3 to LVIS0) of the low-voltage detection level select

register (LVIS).

<3> Set bit 7 (LVION) of LVIM to 1 (enables LVI operation).

<4> Use software to instigate a wait of at least 0.2 ms.

<5> Wait until “supply voltage (V^DD) ≥ detection voltage (VLVI)” at bit 0 (LVIF) of LVIM is confirmed.

<6> Clear the interrupt request flag of LVI (LVIIF) to 0.

<7> Release the interrupt mask flag of LVI (LVIMK).

<8> Execute the EI instruction (when vector interrupts are used).

Figure 17-5 shows the timing of generating the interrupt signal of the low-voltage detector. Numbers <1> to

<7> in this figure correspond to <1> to <7> above.

•

When stopping operation

Either of the following procedures must be executed.

• When using 8-bit memory manipulation instruction: Write 00H to LVIM.

• When using 1-bit memory manipulation instruction: Clear LVION to 0.

Figure 17-5. Timing of Low-Voltage Detector Interrupt Signal Generation

Supply voltage (VDD

)

LVI detection voltage

(V^LVI

)

POC detection voltage

(V^POC

)

Time

<2>

LVIMK flag

(set by software)

<1>

Note 1

<7> Cleared by software

LVION flag

(set by software)

<3>

<4> 0.2 ms or longer

<5>

LVIF flag

INTLVI

Note 2

LVIIF flag

<6>

Cleared by software

Internal reset signal

Notes 1. The LVIMK flag is set to “1” by reset signal generation.

2. An interrupt request signal (INTLVI) may be generated, and the LVIF and LVIIF flags may be set to 1.

Remark <1> to <7> in Figure 17-5 above correspond to <1> to <7> in the description of “when starting operation”

in 17.4 (2) When used as interrupt.

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CHAPTER 17 LOW-VOLTAGE DETECTOR

17.5 Cautions for Low-Voltage Detector

In a system where the supply voltage (VDD) fluctuates for a certain period in the vicinity of the LVI detection voltage

(V^LVI), the operation is as follows depending on how the low-voltage detector is used.

<1> When used as reset

The system may be repeatedly reset and released from the reset status.

In this case, the time from release of reset to the start of the operation of the microcontroller can be arbitrarily

set by taking action (1) below.

<2> When used as interrupt

Interrupt requests may be frequently generated. Take (b) of action (2) below.

In this system, take the following actions.

(1) When used as reset

After releasing the reset signal, wait for the supply voltage fluctuation period of each system by means of a

software counter that uses a timer, and then initialize the ports (see Figure 17-6).

(2) When used as interrupt

(a) Perform the processing^Notefor low voltage detection. Check that “supply voltage (VDD) ≥ detection voltage

(V^LVI)” in the servicing routine of the LVI interrupt by using bit 0 (LVIF) of the low-voltage detection register

(LVIM). Clear bit 1 (LVIIF) of interrupt request flag register 0 (IF0) to 0.

(b) In a system where the supply voltage fluctuation period is long in the vicinity of the LVI detection voltage, wait

for the supply voltage fluctuation period, check that “supply voltage (V^DD) ≥ detection voltage (VLVI)” using the

LVIF flag and clear LVIIF flag to 0.

Note For low voltage detection processing, the CPU clock speed is switched to slow speed and the A/D

converter is stopped, etc.

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Figure 17-6. Example of Software Processing After Release of Reset (1/2)

• If supply voltage fluctuation is 50 ms or less in vicinity of LVI detection voltage

Reset

; Check reset source^Note

Initialization of ports

processing <1>

Setting WDT

Initialization

LVI reset

; The detection level is set with LVIS.

The low-voltage detector is operated (LVION = 1)

Setting LVI

; f^XP= High-speed internal oscillation clock (8.4 MHz (MAX.))/2²(default value)

Source: fXP (2.1 MHz (MAX.))/2¹²,

51 ms when the compare value is 25

Setting 8-bit timer H1

(50 ms is measured)

Timer starts (TMHE1 = 1)

Clears WDT

Yes

Detection voltage or more

(LVIF = 0 ?)

No

; Clear low-voltage detection flag.

LVIF = 0

Restarting the timer H1

(TMHE1 = 0 → TMHE1 = 1)

; Clear timer counter and timer starts.

No

50 ms has passed?

(TMIFH1 = 1?)

Yes

; Setting the division ratio of the system clock,

timer, A/D converter, etc.

Initialization

processing <2>

Note A flowchart is shown on the next page.

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CHAPTER 17 LOW-VOLTAGE DETECTOR

Figure 17-6. Example of Software Processing After Release of Reset (2/2)

• Checking reset source

Check reset source

Yes

WDTRF of RESF

register = 1?

No

Reset processing by

watchdog timer

No

LVIRF of RESF

register = 1?

Yes

Power-on-clear/external

reset generated

Reset processing by

low-voltage detector

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CHAPTER 18 OPTION BYTE

18.1 Functions of Option Byte

The address 0080H of the flash memory of the 78K0S/KB1+ is an option byte area. When power is supplied or

when starting after a reset, the option byte is automatically referenced, and settings for the specified functions are

performed. When using the product, be sure to set the following functions by using the option byte.

(1) Selection of system clock source

• High-speed internal oscillation clock

• Crystal/ceramic oscillation clock

• External clock input

(2) Low-speed internal oscillation clock oscillation

• Cannot be stopped.

• Can be stopped by software.

(3) Control of RESET pin

• Used as RESET pin

• RESET pin is used as an input port pin (P34) (refer to 18.3 Caution When the RESET Pin Is Used as an

Input-Only Port Pin (P34)).

(4) Oscillation stabilization time on power application or after reset release

• 2¹⁰/fX

• 2¹²/fX

• 2¹⁵/fX

• 2¹⁷/fX

Figure 18-1. Positioning of Option Byte

0FFFH/1FFFH

Flash memory

(4096/8192 × 8 bits)

0080H

Option byte

DEF

1

RMCE OSCSEL1 OSCSEL0 LIOCP

OSTS1 OSTS0

0000H

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CHAPTER 18 OPTION BYTE

18.2 Format of Option Byte

Format of option bytes is shown below.

Figure 18-2. Format of Option Byte (1/2)

Address: 0080H

7

6

5

4

1

3

2

1

0

1

DEFOSTS1 DEFOSTS0

RMCE

OSCSEL1

OSCSEL0

LIOCP

DEFOSTS1 DEFOSTS0

Oscillation stabilization time on power application or after reset release

2¹⁰/fx (102.4 μs)

2¹²/fx (409.6 μs)

2¹⁵/fx (3.27 ms)

2¹⁷/fx (13.1 ms)

0

1

0

1

0

1

Caution The setting of this option is valid only when the crystal/ceramic oscillation clock is selected

as the system clock source. No wait time elapses if the high-speed internal oscillation clock

or external clock input is selected as the system clock source.

RMCE

Control of RESET pin

1

0

RESET pin is used as is.

RESET pin is used as input port pin (P34).

Caution Because the option byte is referenced after reset release, if a low level is input to the RESET

pin before the option byte is referenced, then the reset state is not released.

Also, when setting 0 to RMCE, connect the pull-up resistor.

OSCSEL1

OSCSEL0

Selection of system clock source

Crystal/ceramic oscillation clock

0

1

0

1

×

External clock input

High-speed internal oscillation clock

Caution Because the X1 and X2 pins are also used as the P121 and P122 pins, the conditions under

which the X1 and X2 pins can be used differ depending on the selected system clock source.

(1) Crystal/ceramic oscillation clock is selected

The X1 and X2 pins cannot be used as I/O port pins because they are used as clock input

pins.

(2) External clock input is selected

Because the X1 pin is used as an external clock input pin, P121 cannot be used as an I/O

port pin.

(3) High-speed internal oscillation clock is selected

P121 and P122 can be used as I/O port pins.

Remark × : don’t care

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CHAPTER 18 OPTION BYTE

Figure 18-2. Format of Option Byte (2/2)

LIOCP

Low-speed internal oscillates

1

0

Cannot be stopped (oscillation does not stop even if 1 is written to the LSRSTOP bit)

Can be stopped by software (oscillation stops when 1 is written to the LSRSTOP bit)

Cautions 1. If it is selected that low-speed internal oscillator cannot be stopped, the count clock to

the watchdog timer (WDT) is fixed to low-speed internal oscillation clock.

2. If it is selected that low-speed internal oscillator can be stopped by software, supply of

the count clock to WDT is stopped in the HALT/STOP mode, regardless of the setting of

bit 0 (LSRSTOP) of the low-speed internal oscillation mode register (LSRCM). Similarly,

clock supply is also stopped when a clock other than the low-speed internal oscillation

clock is selected as a count clock to WDT.

While the low-speed internal oscillator is operating (LSRSTOP = 0), the clock can be

supplied to the 8-bit timer H1 even in the STOP mode.

Remarks 1. ( ): f^X= 10 MHz

2. For the oscillation stabilization time of the resonator, refer to the characteristics of the resonator

to be used.

3. An example of software coding for setting the option bytes is shown below.

OPB OSEG AT 0080H

DB 10010001B

; Set to option byte

; Low-speed internal oscillator cannot be stopped

; The system clock is a crystal or ceramic resonator.

; The RESET pin is used as an input-only port pin (P34).

; Minimum oscillation stabilization time (2¹⁰/fX

)

4. For details on the timing at which the option byte is referenced, see CHAPTER 15 RESET

FUNCTION.

18.3 Caution When the RESET Pin Is Used as an Input-Only Port Pin (P34)

Be aware of the following when re-erasing/-writing (by on-board programming using a dedicated flash memory

programmer) an already-written device which has been set as “The RESET pin is used as an input-only port pin

(P34)” by the option byte function.

Before supplying power to the target system, connect a dedicated flash memory programmer and turn its power on.

If the power is supplied to the target system beforehand, the flash memory programming mode cannot be switched

to.

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CHAPTER 19 FLASH MEMORY

19.1 Features

The internal flash memory of the 78K0S/KB1+ has the following features.

{ Erase/write even without preparing a separate dedicated power supply

{ Capacity: 4 KB/8 KB

• Erase unit: 1 block (256 bytes)

• Write unit: 1 block (at on-board/off-board programming time), 1 byte (at self programming time)

{ Rewriting method

• Rewriting by communication with dedicated flash memory programmer (on-board/off-board programming)

• Rewriting flash memory by user program (self programming)

{ Supports rewriting of the flash memory at on-board/off-board programming time through security functions

{ Supports security functions in block units at self programming time through protect bytes

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CHAPTER 19 FLASH MEMORY

19.2 Memory Configuration

The 4/8 KB internal flash memory area is divided into 16/32 blocks and can be programmed/erased in block units.

All the blocks can also be erased at once, by using a dedicated flash memory programmer.

Figure 19-1. Flash Memory Mapping

FFFFH

Special function resister

(256 bytes)

FF00H

FEFFH

•

μ

PD78F9234

1FFFH

Internal high-speed RAM

(256 bytes)

Block 31 (256 bytes)

1F00H

1EFFH

FE00H

FDFFH

Block 30 (256 bytes)

Block 29 (256 bytes)

1E00H

1DFFH

1D00H

1CFFH

Use prohibited

•

μ

PD78F9232

1000H

0FFFH

Block 15 (256 bytes)

Block 14 (256 bytes)

Block 13 (256 bytes)

0F00H

0EFFH

Block 14 (256 bytes)

Block 13 (256 bytes)

0E00H

0DFFH

0D00H

0CFFH

0300H

02FFH

Flash memory

(4/8 KB)

Block 2 (256 bytes)

Block 1 (256 bytes)

Block 2 (256 bytes)

Block 1 (256 bytes)

0200H

01FFH

0100H

00FFH

Block 0 (256 bytes)

4 KB

Block 0 (256 bytes)

8 KB

0000H

19.3 Functional Outline

The internal flash memory of the 78K0S/KB1+ can be rewritten by using the rewrite function of the dedicated flash

memory programmer, regardless of whether the 78K0S/KB1+ has already been mounted on the target system or not

(on-board/off-board programming).

The function for rewriting a program with the user program (self programming), which is ideal for an application

when it is assumed that the program is changed after production/shipment of the target system, is provided.

Refer to Table 19-1 for the flash memory writing control function.

In addition, a security function that prohibits rewriting the user program written to the internal flash memory is also

supported, so that the program cannot be changed by an unauthorized person.

Refer to 19.7.3 Security settings for details on the security function.

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Table 19-1. Rewrite Method

Rewrite Method

Functional Outline

Operation Mode

Flash memory

On-board programming

Flash memory can be rewritten after the device is mounted on the

target system, by using a dedicated flash memory programmer.

programming mode

Off-board programming

Self programming

Flash memory can be rewritten before the device is mounted on the

target system, by using a dedicated flash memory programmer and a

dedicated program adapter board (FA series).

Flash memory can be rewritten by executing a user program that has

been written to the flash memory in advance by means of on-board/off-

board programming.

Self programming mode

Remarks 1. The FA series is a product of Naito Densei Machida Mfg. Co., Ltd.

2. Refer to the following sections for details on the flash memory writing control function.

• 19.7 On-Board and Off-Board Flash Memory Programming

• 19.8 Flash Memory Programming by Self Programming

19.4 Writing with Flash Memory Programmer

The following two types of dedicated flash memory programmers can be used for writing data to the internal flash

memory of the 78K0S/KB1+.

• FlashPro5 (PG-FP5, FL-PR5)

• QB-MINI2

<R>

Data can be written to the flash memory on-board or off-board, by using a dedicated flash memory programmer.

(1) On-board programming

The contents of the flash memory can be rewritten after the 78K0S/KB1+ has been mounted on the target

system. The connectors that connect the dedicated flash memory programmer and the test pad must be

mounted on the target system. The test pad is required only when writing data with the crystal/ceramic

resonator mounted (refer to Figure 19-4 for mounting of the test pad).

(2) Off-board programming

Data can be written to the flash memory with a dedicated program adapter (FA series) before the 78K0S/KB1+

is mounted on the target system.

<R>

Remark The FL-PR5 and FA series are products of Naito Densei Machida Mfg. Co., Ltd.

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CHAPTER 19 FLASH MEMORY

19.5 Programming Environment

The environment required for writing a program to the flash memory is illustrated below.

<R>

Figure 19-2. Environment for Writing Program to Flash Memory (FlashPro5/QB-MINI2)

V

DD

SS

V

QB-MINI2

FlashPro5

RS-232-C

USB

RESET

SO/TxD

CLK

Dedicated flash memory

programmer

Host machine

78K0S/KB1+

<R>

Remark For QB-MINI2, the name of the SO/TxD signal is DATA.

A host machine that controls the dedicated flash memory programmer is necessary. When using the PG-FP5 or

FL-PR5, data can be written with just the dedicated flash memory programmer after downloading the program from

the host machine.

UART is used for manipulation such as writing and erasing when interfacing between the dedicated flash memory

programmer and the 78K0S/KB1+. To write the flash memory off-board, a dedicated program adapter (FA series) is

necessary.

Download the latest firmware for flash memory programmer, programming GUI, and parameter file from the

download site for development tools (http://www.necel.com/micro/en/ods/).

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CHAPTER 19 FLASH MEMORY

<R>

Table 19-2. Wiring Between 78K0S/KB1+ and FlashPro5/QB-MINI2

FlashPro5/QB-MINI2 Connection Pin

78K0S/KB1+ Connection Pin

Pin Name

CLK

I/O

Output

–

Pin Function

Clock to 78K0S/KB1+

Receive signal/on-board mode signal

Reset signal

X1/P121

X2/P122

RESET/P34

V^DD

SO/TxD

/RESET

VDD

VDD voltage generation/voltage monitor

Ground

V^SS

GND

–

Figure 19-3. Communication with FlashPro5/QB-MINI2 (30-Pin Products)

<R>

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

FlashPro5/

QB-MINI2 signal name

CLK

SO/TxD

/RESET

VDD

GND

78K0S/KB1+

<R>

Remark For QB-MINI2, the name of the SO/TxD signal is DATA.

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CHAPTER 19 FLASH MEMORY

19.6 Pin Connection on Board

To write the flash memory on-board, connectors that connect the dedicated flash memory programmer must be

provided on the target system. First provide a function that selects the normal operation mode or flash memory

programming mode on the board.

When the flash memory programming mode is set, all the pins not used for programming the flash memory are in

the same status as immediately after reset. Therefore, if the external device does not recognize the state immediately

after reset, the pins must be processed as described below.

The state of the pins in the self programming mode is the same as that in the HALT mode.

19.6.1 X1 and X2 pins

The X1 and X2 pins are used as the serial interface of flash memory programming. Therefore, if the X1 and X2

pins are connected to an external device, a signal conflict occurs. To prevent the conflict of signals, isolate the

connection with the external device.

Similarly, when a capacitor is connected to the X1 and X2 pins, the waveform during communication is changed,

and thus communication may be disabled depending on the capacitor capacitance. Make sure to isolate the

connection with the capacitor during flash programming.

Perform the following processing (1) and (2) when on-board programming is performed with the resonator mounted,

when it is difficult to isolate the resonator, while a crystal or ceramic resonator is selected as the system clock.

(1) Mount the minimum-possible test pads between the device and the resonator, and connect the programmer via

the test pad. Keep the wiring as short as possible (refer to Figure 19-4 and Table 19-3).

(2) Set the oscillation frequency of the communication clock for writing using the programming GUI of the

dedicated flash memory programmer. Research the series/parallel resonant and antiresonant frequencies of

the resonator used, and set the oscillation frequency so that it is outside the range of the resonant frequency

10% (refer to Figure 19-5 and Table 19-4).

Figure 19-4. Example of Mounting Test Pads

Test pad

V

SS

X1

X2

Table 19-3. Clock to Be Used and Mounting of Test Pads

Clock to Be Used

High-speed internal oscillation clock

External clock

Mounting of Test Pads

Not required

Required

Crystal/ceramic oscillation

clock

Before resonator is mounted

After resonator is mounted

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CHAPTER 19 FLASH MEMORY

Figure 19-5. PG-FP5 Programming GUI Setting Example

Set oscillation frequency

Click

(Standard tab in Device setup window)

(Main window)

Table 19-4. Oscillation Frequency and PG-FP5 Programming GUI Setting Value Example

Oscillation Frequency

PG-FP5 Programming GUI Setting Value Example

(Communication Frequency)

2 MHz ≤ fX < 4 MHz

8 MHz

9 MHz

10 MHz

8 MHz

4 MHz ≤ fX < 8 MHz

8 MHz ≤ fX < 9 MHz

9 MHz ≤ fX ≤ 10 MHz

Caution The above values are recommended values. Depending on the usage environment these

values may change, so set them after having performed sufficient evaluations.

19.6.2 RESET pin

If the reset signal of the dedicated flash memory programmer is connected to the RESET pin that is connected to

the reset signal generator on the board, signal collision takes place. To prevent this collision, isolate the connection

with the reset signal generator.

If the reset signal is input from the user system while the flash memory programming mode is set, the flash

memory will not be correctly programmed. Do not input any signal other than the reset signal of the dedicated flash

memory programmer.

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CHAPTER 19 FLASH MEMORY

Figure 19-6. Signal Collision (RESET Pin)

78K0S/KB1+

RESET

Dedicated flash memory programmer

Signal collision

connection signal

Reset signal generator

Output pin

In the flash memory programming mode, the signal output by the reset signal

generator collides with the signal output by the dedicated flash memory

programmer. Therefore, isolate the signal of the reset signal generator.

19.6.3 Port pins

When the flash memory programming mode is set, all the pins not used for flash memory programming enter the

same status as that immediately after reset. If external devices connected to the ports do not recognize the port

status immediately after reset, the port pin must be connected to V^DDor VSS via a resistor.

The state of the pins in the self programming mode is the same as that in the HALT mode.

19.6.4 Power supply

Connect the V^DDpin to VDD of the flash memory programmer, and the VSS pin to VSS of the flash memory

programmer.

Supply the same other power supplies (AV^REFand AVSS) as those in the normal operation mode.

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19.7 On-Board and Off-Board Flash Memory Programming

19.7.1 Flash memory programming mode

To rewrite the contents of the flash memory by using the dedicated flash memory programmer, set the

78K0S/KB1+ in the flash memory programming mode. When the 78K0S/KB1+ is connected to the flash memory

programmer and a communication command is transmitted to the microcontroller, the microcontroller is set in the flash

memory programming mode.

Change the mode by using a jumper when writing the flash memory on-board.

19.7.2 Communication commands

The dedicated flash memory programmer controls the 78K0S/KB1+ by using commands. The signals sent from

the dedicated flash memory programmer to the 78K0S/KB1+ are called communication commands, and the

commands sent from the 78K0S/KB1+ to the dedicated flash memory programmer are called response.

<R>

Figure 19-7. Communication Commands

QB-MINI2

FlashPro5

Communication

Command

MINICUBE2

Response

Dedicated flash memory programmer

78K0S/KB1+

Communication commands are listed in the table below. All these communication commands are issued from the

flash memory programmer and the 78K0S/KB1+ performs processing corresponding to the respective communication

commands.

Table 19-5. Communication Commands

Classification

Command Name

Batch erase (chip erase) command

Block erase command

Function

Erase

Write

Erases the contents of the entire memory

Erases the contents of the memory of the specified block

Write command

Writes to the specified address range and executes a verify

check of the contents.

Checksum

Checksum command

Reads the checksum of the specified address range and

compares with the written data.

Blank check

Security

Blank check command

Confirms the erasure status of the entire memory.

Security setting command

Prohibits batch erase (chip erase) command, block erase

command, and write command to prevent operation by third

parties.

The 78K0S/KB1+ returns a response for the communication command issued by the dedicated flash memory

programmer. The response names sent from the 78K0S/KB1+ are listed below.

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Table 19-6. Response Name

Response Name

Function

ACK

NAK

Acknowledges command/data.

Acknowledges illegal command/data.

19.7.3 Security settings

The operations shown below can be prohibited using the security setting command.

• Batch erase (chip erase) is prohibited

Execution of the block erase and batch erase (chip erase) commands for entire blocks in the flash memory is

prohibited. Once execution of the batch erase (chip erase) command is prohibited, all the prohibition settings can

no longer be cancelled.

Caution After the security setting of the batch erase is set, erasure cannot be performed for the device.

In addition, even if a write command is executed, data different from that which has already

been written to the flash memory cannot be written because the erase command is disabled.

• Block erase is prohibited

Execution of the block erase command in the flash memory is prohibited. This prohibition setting can be

cancelled using the batch erase (chip erase) command.

• Write is prohibited

Execution of the write and block erase commands for entire blocks in the flash memory is prohibited. This

prohibition setting can be cancelled using the batch erase (chip erase) command.

Remark The security setting is valid when the programming mode is set next time.

The batch erase (chip erase), block erase, and write commands are enabled by the default setting when the flash

memory is shipped. The above security settings are possible only for on-board/off-board programming. Each security

setting can be used in combination.

Table 19-7 shows the relationship between the erase and write commands when the 78K0S/KB1+ security function

is enabled.

Table 19-7. Relationship Between Commands When Security Function Is Enabled

Command Batch Erase (Chip

Erase) Command

Block Erase

Command

Write Command

Security

When batch erase (chip erase) security

operation is enabled

Disabled

Enabled

Disabled

Enabled^Note

Enabled

When block erase security operation is

enabled

When write security operation is enabled

Disabled

Note Since the erase command is disabled, data different from that which has already been written to the

flash memory cannot be written.

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Table 19-8 shows the relationship between the security setting and the operation in each programming mode.

Table 19-8. Relationship Between Security Setting and Operation In Each Programming Mode

Programming Mode

Security Setting

On-Board/Off-Board Programming

Self Programming

Security Setting Security Operation

Impossible

Invalid^{Note 2}

Security Setting

Possible

Security Operation

Valid^{Note 1}

Batch erase (chip erase)

Block erase

Write

Notes 1. Execution of each command is prohibited by the security setting.

2. Execution of self programming command is possible regardless of the security setting.

19.8 Flash Memory Programming by Self Programming

The 78K0S/KB1+ supports a self programming function that can be used to rewrite the flash memory via a user

program, making it possible to upgrade programs in the field.

Caution Self programming processing must be included in the program before performing self

programming.

Remarks 1. For usage of self programming, refer to the examples from 19.8.4 onward.

2. To use the internal flash memory of the 78K0S/KB1+ as the external EEPROM for storing data, refer

to 78K0S/Kx1+ EEPROM Emulation Application Note (U17379E).

19.8.1 Outline of self programming

To execute self programming, shift the mode from the normal operation of the user program (normal mode) to the

self programming mode. Write/erase processing for the flash memory, which has been set to the register in advance,

is performed by executing the HALT instruction during self programming mode. The HALT state is automatically

released when processing is completed.

To shift to the self programming mode, execute a specific sequence for a specific register. Refer to 19.8.4

Example of shifting normal mode to self programming mode for details.

Remark Data written by self programming can be referenced with the MOV instruction.

Table 19-9. Self Programming Mode

Mode

User Program Execution

Execution of Write/erase for Flash

Memory with HALT Instruction

Normal mode

Self programming mode

Enabled

−

Enabled^Note

Enabled

Note Maskable interrupt servicing is disabled during self programming mode.

Figure 19-8 shows a block diagram for self programming, Figure 19-9 shows the self programming state transition

diagram, Table 19-10 lists the commands for controlling self programming.

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Figure 19-9. Self Programming State Transition Diagram

User program

Operation setting

Normal mode

Specific sequence

Operation

setting

Register for

Self programming mode

self programming

Self programming command

execution by HALT instruction

Self programming

command completion/error

Flash memory

control block (hardware)

Operation reference

Self programming

command under execution

Flash memory

Table 19-10. Self Programming Controlling Commands

Command Name

Internal verify 1

Function

Time Taken from HALT Instruction Execution

to Command Execution End

This command is used to check if data has been

correctly written to the flash memory. It is used to

check whether data has been written to an entire

block.

Internal verify for 1 block (internal verify

command executed once): 6.8 ms

Internal verify 2

This command is used to check if data has been

correctly written to the flash memory. It is used to

check whether data has been written to multiple

addresses in the same block.

Internal verify of 1 byte: 27 μs

Block erasure^Note

Block blank check

This command is used to erase a specified block.

Specify the block number before execution.

8.5 ms

This command is used to check if data in a specified

block has been erased. Specify the block number,

then execute this command.

480 μs

Byte write

This command is used to write 1-byte data to the

specified address in the flash memory. Specify the

write address and write data, then execute this

command.

150 μs

Note Set the number of retrials larger than the block erasure time divided by the time (8.5 ms) for one erase, in

accordance with the time (MAX. value) required for flash memory block erasures.

Remark The internal verify 1 command can be executed by specifying an address in the same block, but internal

verify 2 command is recommended if data is written to multiple addresses in the same block.

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19.8.2 Cautions on self programming function

• No instructions can be executed while a self programming command is being executed. Therefore, clear and

restart the watchdog timer counter in advance so that the watchdog timer does not overflow during self

programming. Refer to Table 19-10 for the time taken for the execution of self programming.

• Interrupts that occur during self programming can be acknowledged after self programming mode ends. To avoid

this operation, disable interrupt servicing (by setting MK0 and MK1 to FFH, and executing the DI instruction)

when shifting from the normal mode to the self programming mode with a specific sequence.

• RAM is not used while a self programming command is being executed.

• If the supply voltage drops or the reset signal is input while the flash memory is being written or erased,

writing/erasing is not guaranteed.

• The value of the blank data set during block erasure is FFH.

• Set the CPU clock beforehand so that it is 1 MHz or higher during self programming.

• Execute self programming after executing the NOP and HALT instructions immediately after executing a specific

sequence to set self programming mode. At this time, the HALT instruction is automatically released after 10 μs

(MAX.) + 2 CPU clocks (fCPU).

• If the clock of the oscillator or an external clock is selected as the system clock, execute the NOP and HALT

instructions immediately after executing a specific sequence to set self programming mode, wait for 8 μs after

releasing the HALT status, and then execute self programming.

• Check FPRERR using a 1-bit memory manipulation instruction.

• The state of the pins in self programming mode is the same as that in HALT mode.

• Since the security function set via on-board/off-board programming is disabled in self programming mode, the

self programming command can be executed regardless of the security function setting. To disable write or erase

processing during self programming, set the protect byte.

• Be sure to clear bits 5 to 7 of flash address pointer H (FLAPH) and flash address pointer H compare register

(FLAPHC) to 0 before executing the self programming command. If the self programming command is executed

with these bits set to 1, the device may malfunction.

• Clear the value of the FLCMD register to 00H immediately before setting to self programming mode and normal

mode.

19.8.3 Registers used for self programming function

The following registers are used for the self programming function.

• Flash programming mode control register (FLPMC)

• Flash protect command register (PFCMD)

• Flash status register (PFS)

• Flash programming command register (FLCMD)

• Flash address pointers H and L (FLAPH and FLAPL)

• Flash address pointer H compare register and flash address pointer L compare register (FLAPHC and FLAPLC)

• Flash write buffer register (FLW)

The 78K0S/KB1+ has an area called a protect byte at address 0081H of the flash memory.

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(1) Flash programming mode control register (FLPMC)

This register is used to set the operation mode when data is written to the flash memory in the self

programming mode, and to read the set value of the protect byte.

Data can be written to FLPMC only in a specific sequence (refer to 19.8.3 (2) Flash protect command

register (PFCMD)) so that the application system does not stop by accident because of malfunctions due to

noise or program hang-ups.

This register is set with an 8-bit memory manipulation instruction.

Reset signal generation makes the contents of this register undefined.

Figure 19-10. Format of Flash Programming Mode Control Register (FLPMC)

Address: FFA2H

After reset: Undefined^{Note 1}

R/W^{Note 2}

Symbol

FLPMC

7

6

5

4

3

2

1

0

PRSELF4 PRSELF3 PRSELF2 PRSELF1 PRSELF0

FLSPM

0

Selection of operation mode during self programming mode

Normal mode

This is the normal operation status. Executing the HALT instruction sets

standby status.

Self programming mode

1

Self programming commands can be executed by executing the specific

sequence to change modes while in normal mode.

Set a command, an address, and data to be written, then execute the HALT

instruction to execute self programming.

The set value of the protect byte

PRSELF4 PRSELF3 PRSELF2 PRSELF1 PRSELF0

is read to these bits.

Notes 1. Bit 0 (FLSPM) is cleared to 0 when reset is released. The set value of the protect

byte is read to bits 2 to 6 (PRSELF0 to PRSELF4) after reset is released.

2. Bits 2 to 6 (PRSELF0 to PRSELF4) are read-only.

Cautions 1. Cautions in the case of setting the self programming mode, refer to 19.8.2

Cautions on self programming function.

2. Set the CPU clock beforehand so that it is 1 MHz or higher during self

programming.

3. Execute self programming after executing the NOP and HALT instructions

immediately after executing a specific sequence to set self programming

mode. At this time, the HALT instruction is automatically released after 10

μs (MAX.) + 2 CPU clocks (fCPU).

4. If the clock of the oscillator or an external clock is selected as the system

clock, execute the NOP and HALT instructions immediately after executing a

specific sequence to set self programming mode, wait for 8 μs after

releasing the HALT status, and then execute self programming.

5. Clear the value of the FLCMD register to 00H immediately before setting to

self programming mode and normal mode.

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(2) Flash protect command register (PFCMD)

If the application system stops inadvertently due to malfunction caused by noise or program hang-up, an

operation to write the flash programming mode control register (FLPMC) may have a serious effect on the

system. PFCMD is used to protect FLPMC from being written, so that the application system does not stop

inadvertently.

Writing FLPMC is enabled only when a write operation is performed in the following specific sequence.

<1> Write a specific value to PFCMD (A5H)

<2> Write the value to be set to bit 0 (FLSPM) of the FLPMC (writing in this step is invalid)

<3> Write the inverted value of the value to be set to bit 0 (FLSPM) of the FLPMC (writing in this step is

invalid)

<4> Write the value to be set to bit 0 (FLSPM) of the FLPMC (writing in this step is valid)

Caution Interrupt servicing cannot be executed in self programming mode. Disable interrupt

servicing (by executing the DI instruction while MK0 and MK1 = FFH) between the points

before executing the specific sequence that sets self programming mode and after executing

the specific sequence that changes the mode to the normal mode.

This rewrites the value of the register, so that the register cannot be written illegally.

Occurrence of an illegal write operation can be checked by bit 0 (FPRERR) of the flash status register (PFS).

A5H must be written to PFCMD each time the value of FLPMC is changed. Check FPRERR using a 1-bit

memory manipulation instruction.

PFCMD can be set with an 8-bit memory manipulation instruction.

Reset signal generation makes PFCMD undefined.

Figure 19-11. Format of Flash Protect Command Register (PFCMD)

Address: FFA0H

After reset: Undefined

W

4

Symbol

PFCMD

7

6

5

3

2

1

0

REG7

REG6

REG5

REG4

REG3

REG2

REG1

REG0

(3) Flash status register (PFS)

If data is not written to the flash programming mode control register (FLPMC), which is protected, in the correct

sequence (writing the flash protect command register (PFCMD)), FLPMC is not written and a protection error

occurs. If this happens, bit 0 of PFS (FPRERR) is set to 1.

When FPRERR is 1, it can be cleared to 0 by writing 0 to it.

Errors that may occur during self programming are reflected in bit 1 (VCERR) and bit 2 (WEPRERR) of PFS.

VCERR or WEPRERR can be cleared by writing 0 to them.

All the flags of the PFS register must be pre-cleared to 0 to check if the operation is performed correctly.

PFS can be set with a 1-bit or 8-bit memory manipulation instruction.

Reset signal generation clears PFS to 00H.

Caution Check FPRERR using a 1-bit memory manipulation instruction.

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Figure 19-12. Format of Flash Status Register (PFS)

Address: FFA1H

After reset: 00H

R/W

Symbol

PFS

7

6

0

5

0

4

0

3

0

2

1

0

WEPRERR

VCERR

FPRERR

1. Operating conditions of FPRERR flag

• If PFCMD is written when the store instruction operation recently performed on a peripheral register is not to

write a specific value (A5H) to FLPMC

• If the first store instruction operation after <1> is on a peripheral register other than FLPMC

• If the first store instruction operation after <2> is on a peripheral register other than FLPMC

• If a value other than the inverted value of the value to be set to FLPMC is written by the first store instruction

after <2>

• If the first store instruction operation after <3> is on a peripheral register other than FLPMC

• If a value other than the value to be set to FLPMC (value written in <2>) is written by the first store instruction

after <3>

Remark The numbers in angle brackets above correspond to the those in (2) Flash protect command

register (PFCMD).

• If 0 is written to the FPRERR flag

• If the reset signal is generated

2. Operating conditions of VCERR flag

• Erasure verification error

• Internal writing verification error

If VCERR is set, it means that the flash memory has not been erased or written correctly. Erase or write the

memory again in the specified procedure.

Remark The VCERR flag may also be set if an erase or write protect error occurs.

• When 0 is written to the VCERR flag

• When the reset signal is generated

3. Operating conditions of WEPRERR flag

• If the area specified by the protect byte to be protected from erasing or writing is specified by the flash

address pointer H (FLAPH) and a command is executed to this area

• If 1 is written to a bit that has not been erased (a bit for which the data is 0).

• When 0 is written to the WEPRERR flag

• When the reset signal is generated

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(4) Flash programming command register (FLCMD)

This register is used to specify whether the flash memory is erased, written, or verified in the self programming

mode.

This register is set with a 1-bit or 8-bit memory manipulation instruction.

Reset signal generation clears this register to 00H.

Figure 19-13. Format of Flash Programming Command Register (FLCMD)

Address: FFA3H

After reset: 00H

R/W

Symbol

FLCMD

7

6

0

5

0

4

0

3

0

2

1

0

FLCMD2 FLCMD1 FLCMD0

FLCMD2 FLCMD1 FLCMD0 Command Name

0 0 1 Internal verify 1

Function

This command is used to check if

data has been correctly written to the

flash memory. It is used to check

whether data has been written to an

entire block. If an error occurs, bit 1

(VCERR) or bit 2 (WEPRERR) of the

flash status register (PFS) is set to 1.

0

1

0

Internal verify 2

This command is used to check if

data has been correctly written to the

flash memory. It is used to check

whether data has been written to

multiple addresses in the same block.

If an error occurs, bit 1 (VCERR) or

bit 2 (WEPRERR) of the flash status

register (PFS) is set to 1.

0

1

Block erase

This command is used to erase

specified block. It is used both in the

on-board mode and self

programming mode.

1

0

1

Block blank check This command is used to check if the

specified block has been erased.

Byte write

This command is used to write 1-byte

data to the specified address in the

flash memory. Specify the write

address and write data, then execute

this command.

If 1 is written to a bit that has not

been erased (a bit for which the data

is 0), then bit 2 (WEPRERR) of the

flash status register (PFS) becomes

1.

Other than above^Note

Setting prohibited

Note If any command other than those above is executed, command execution may immediately be

terminated, and bits 1 and 2 (WEPRERR and VCERR) of the flash status register (PFS) may be set

to 1.

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(5) Flash address pointers H and L (FLAPH and FLAPL)

These registers are used to specify the start address of the flash memory when the memory is erased, written,

or verified in the self programming mode.

FLAPH and FLAPL consist of counters, and they are incremented until the values match with those of

FLAPHC and FLAPLC when the programming command is not executed. When the programming command

is executed, therefore, set the value again.

These registers are set with a 1-bit or 8-bit memory manipulation instruction.

Reset signal generation makes these registers undefined.

Figure 19-14. Format of Flash Address Pointers H/L (FLAPH/FLAPL)

Address: FFA4H, FFA5H

After reset: Undefined

R/W

FLAPH (FFA5H)

FLAPL (FFA4H)

0

FLA FLA FLA FLA FLA FLA FLA FLA FLA FLA FLA FLA FLA

P12 P11 P10 P9 P8 P7 P6 P5 P4 P3 P2 P1 P0

Caution Be sure to clear bits 5 to 7 of FLAPH and FLAPHC to 0 before executing the self

programming command. If the self programming command is executed with these bits

set to 1, the device may malfunction.

(6) Flash address pointer H compare register and flash address pointer L compare register (FLAPHC and

FLAPLC)

These registers are used to specify the address range in which the internal sequencer operates when the flash

memory is verified in the self programming mode.

Set FLAPHC to the same value as that of FLAPH. Set the last address of the range in which verification is to

be executed to FLAPLC.

These registers are set with a 1-bit or 8-bit memory manipulation instruction.

Reset signal generation clears these registers to 00H.

Figure 19-15. Format of Flash Address Pointer H/L Compare Registers (FLAPHC/FLAPLC)

Address: FFA6H, FFA7H

After reset: 00H

R/W

FLAPHC (FFA7H)

FLAPLC (FFA6H)

0

FLAP FLAP FLAP FLAP FLAP FLAP FLAP FLAP FLAP FLAP FLAP FLAP FLAP

C12 C11 C10 C9 C8 C7 C6 C5 C4 C3 C2 C1 C0

Cautions 1. Be sure to clear bits 5 to 7 of FLAPH and FLAPHC to 0 before executing the self

programming command. If the self programming command is executed with these bits

set to 1, the device may malfunction.

2. Set the number of the block subject to a block erase, verify, or blank check (same

value as FLAPH) to FLAPHC.

3. Clear FLAPLC to 00H when a block erase is performed, and FFH when a blank check is

performed.

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(7) Flash write buffer register (FLW)

This register is used to store the data to be written to the flash memory.

This register is set with a 1-bit or 8-bit memory manipulation instruction.

Reset signal generation clears these registers to 00H.

Figure 19-16. Format of Flash Write Buffer Register (FLW)

Address: FFA8H

After reset: 00H

6

R/W

Symbol

FLW

7

5

4

3

2

1

0

FLW7

FLW6

FLW5

FLW4

FLW3

FLW2

FLW1

FLW0

(8) Protect byte

This protect byte is used to specify the area that is to be protected from writing or erasing. The specified area

is valid only in the self programming mode. Because self programming of the protected area is invalid, the data

written to the protected area is guaranteed.

Figure 19-17. Format of Protect Byte (1/2)

Address: 0081H

7

1

6

5

4

3

2

1

0

1

PRSELF4

PRSELF3

PRSELF2

PRSELF1

PRSELF0

• μPD78F9232

PRSELF4

PRSELF3

1

PRSELF2

0

PRSELF1

0

PRSELF0

0

Status

0

Blocks 15 to 0 are protected.

Blocks 13 to 0 are protected.

0

1

0

1

0

1

0

1

0

1

0

1

0

Blocks 14 and 15 can be written or erased.

Blocks 11 to 0 are protected.

0

Blocks 12 to 15 can be written or erased.

Blocks 9 to 0 are protected.

Blocks 10 to 15 can be written or erased.

Blocks 7 to 0 are protected.

Blocks 8 to 15 can be written or erased.

Blocks 5 to 0 are protected.

Blocks 6 to 15 can be written or erased.

Blocks 3 to 0 are protected.

Blocks 4 to 15 can be written or erased.

Blocks 1 and 0 are protected.

0

1

Blocks 2 to 15 can be written or erased.

All blocks can be written or erased.

Setting prohibited

1

Other than above

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Figure 19-17. Format of Protect Byte (2/2)

• μPD78F9234

PRSELF4

PRSELF3

0

PRSELF2

0

PRSELF1

0

PRSELF0

0

Status

0

Blocks 31 to 0 are protected.

Blocks 29 to 0 are protected.

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

Blocks 30 and 31 can be written or erased.

Blocks 27 to 0 are protected.

0

Blocks 28 to 31 can be written or erased.

Blocks 25 to 0 are protected.

Blocks 26 and 31 can be written or erased.

Blocks 23 to 0 are protected.

Blocks 24 to 31 can be written or erased.

Blocks 21 to 0 are protected.

Blocks 22 to 31 can be written or erased.

Blocks 19 to 0 are protected.

Blocks 20 to 31 can be written or erased.

Blocks 17 to 0 are protected.

Blocks 18 to 31 can be written or erased.

Blocks 15 to 0 are protected.

Blocks 16 to 31 can be written or erased.

Blocks 13 to 0 are protected.

Blocks 14 to 31 can be written or erased.

Blocks 11 to 0 are protected.

Blocks 12 to 31 can be written or erased.

Blocks 9 to 0 are protected.

Blocks 10 to 31 can be written or erased.

Blocks 7 to 0 are protected.

Blocks 8 to 31 can be written or erased.

Blocks 5 to 0 are protected.

Blocks 6 to 31 can be written or erased.

Blocks 3 to 0 are protected.

Blocks 4 to 31 can be written or erased.

Blocks 1 and 0 are protected.

0

1

Blocks 2 to 31 can be written or erased.

All blocks can be written or erased.

Setting prohibited

1

Other than above

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19.8.4 Example of shifting normal mode to self programming mode

The operating mode must be shifted from normal mode to self programming mode before performing self

programming.

An example of shifting to self programming mode is explained below.

<1> Disable interrupts if the interrupt function is used (by setting the interrupt mask flag registers (MK0, MK1) to

FFH and executing the DI instruction).

<2> Clear FLCMD (FLCMD = 00H).

<3> Clear the flash status register (PFS).

<4> Set self programming mode using a specific sequence^Note

.

• Write a specific value (A5H) to PFCMD.

• Write 01H to FLPMC (writing in this step is invalid).

• Write 0FEH (inverted value of 01H) to FLPMC (writing in this step is invalid).

• Write 01H to FLPMC (writing in this step is valid).

<5> Execute NOP instruction and HALT instruction.

<6> Check the execution result of the specific sequence using bit 0 (FPRERR) of PFS.

Abnormal → <3>, normal → <7>

<7> Mode shift is completed.

Note If the CPU clock is lower than 1 MHz, set it to be 1 MHz or higher.

Caution Be sure to perform the series of operations described above using the user program at an

address where data is not erased or written.

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Figure 19-18. Example of Shifting to Self Programming Mode

Shift to self programming mode

<1> Disable interrupts (by setting

MK0 and MK1 to FFH and

; When interrupt function is used

executing DI instruction)

<2> Clear FLCMD

(FLCMD = 00H)

<3> Clear PFS

If the CPU clock is lower than 1 MHz,

set it to be 1 MHz or higher.

PFCMD = A5H

; Set value is invalid

FLPMC = 01H (set value)

FLPMC = 0FEH (inverted set value)

FLPMC = 01H (set value)

NOP instruction

<4>

; Set value is valid

<5>

HALT instruction

Abnormal

<6> Check execution result

(FPRERR flag)

Normal

<7> Termination

Caution Be sure to perform the series of operations described above using the user program at an

address where data is not erased or written.

Remark <1> to <7> in Figure 19-18 correspond to <1> to <7> in 19.8.4 (previous page).

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An example of the program that shifts the mode to self programming mode is shown below.

;----------------------------

;START

;----------------------------

MOV

MK0,#11111111B

MK1,#11111111B

FLCMD,#00H

; Masks all interrupts

; Clear FLCMD register

DI

ModeOnLoop:

; Configure settings so that the CPU clock ≥ 1 MHz

; Clears flash status register

MOV

PFS,#00H

PFCMD,#0A5H

FLPMC,#01H

FLPMC,#0FEH

FLPMC,#01H

; PFCMD register control

; FLPMC register control (sets value)

; FLPMC register control (inverts set value)

; Sets self programming mode with FLPMC register

; control (sets value)

NOP

HALT

BT

PFS.O,$ModeOnLoop ; Checks completion of write to specific registers

; Repeats the same processing when an error occurs

;----------------------------

;END

;----------------------------

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19.8.5 Example of shifting self programming mode to normal mode

The operating mode must be returned from self programming mode to normal mode after performing self

programming.

An example of shifting to normal mode is explained below.

<1> Clear FLCMD (FLCMD = 00H).

<2> Clear the flash status register (PFS).

<3> Set normal mode using a specific sequence.

• Write the specific value (A5H) to PFCMD.

• Write 00H to FLPMC (writing in this step is invalid)

• Write 0FFH (inverted value of 00H) to FLPMC (writing in this step is invalid)

• Write 00H to FLPMC (writing in this step is valid)

<4> Check the execution result of the specific sequence using bit 0 (FPRERR) of PFS^Note

.

Abnormal → <2>, normal → <5>

<5> Enable interrupt servicing (by executing the EI instruction and changing MK0 and MK1) to restore the original

state.

<6> Mode shift is completed

Note Restore the CPU clock to its setting before self programming, after normal execution of the specific

sequence.

Caution Be sure to perform the series of operations described above using the user program at an

address where data is not erased or written.

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Figure 19-19. Example of Shifting to Normal Mode

Shift to normal mode

<1> Clear FLCMD

(FLCMD = 00H)

<2> Clear PFS

PFCMD = A5H

FLPMC = 00H (set value)

FLPMC = 0FFH (inverted set value)

FLPMC = 00H (set value)

; Set value is invalid

<3>

; Set value is valid

Abnormal

<4> Check execution result

(FPRERR flag)

Normal

Restore the CPU clock to its setting

before the self programming

<5> Enable interrupts

(by executing EI instruction

and changing MK0 and MK1)

; When interrupt function is used

<6> Termination

Caution Be sure to perform the series of operations described above using the user program at an

address where data is not erased or written.

Remark <1> to <6> in Figure 19-19 correspond to <1> to <6> in 19.8.5 (previous page).

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An example of a program that shifts the mode to normal mode is shown below.

;----------------------------

;START

;----------------------------

MOV

FLCMD,#00H

; Clear FLCMD register

ModeOffLoop:

MOV

PFS,#00H

; Clears flash status register

PFCMD,#0A5H

FLPMC,#00H

FLPMC,#0FFH

FLPMC,#00H

; PFCMD register control

; FLPMC register control (sets value)

; FLPMC register control (inverts set value)

; Sets normal mode via FLPMC register control (sets value)

BT

PFS.0,$ModeOffLoop; Checks completion of write to specific registers

; Repeats the same processing when an error occurs

; Restore the CPU clock to its setting before the self

; programming, after normal completion of the specific

; sequence

MOV

MK0,#INT_MK0

MK1,#INT_MK1

; Restores interrupt mask flag

EI

;----------------------------

;END

;----------------------------

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19.8.6 Example of block erase operation in self programming mode

An example of the block erase operation in self programming mode is explained below.

<1> Set 03H (block erase) to the flash program command register (FLCMD).

<2> Set the block number to be erased, to flash address pointer H (FLAPH).

<3> Set flash address pointer L (FLAPL) to 00H.

<4> Write the same value as FLAPH to the flash address pointer H compare register (FLAPHC).

<5> Set the flash address pointer L compare register (FLAPLC) to 00H.

<6> Clear the flash status register (PFS).

<7> Write ACH to the watchdog timer enable register (WDTE) (clear and restart the watchdog timer counter)^{Note 1}

.

<8> Execute the HALT instruction then start self programming. (Execute an instruction immediately after the

HALT instruction if self programming has been executed.)

<9> Check if a self programming error has occurred using bit 1 (VCERR) and bit 2 (WEPRERR) of PFS^{Note 2}

.

Abnormal → <10>

Normal

→ <12>

<R>

<10> If the number of times the erase command can be executed has not been exceeded, return to step <6> and

re-execute the command. If the number of times the erase command can be executed has been exceeded,

block erasure ends abnormally.

<11> Block erase processing is abnormally terminated.

<12> Block erase processing is normally terminated.

Notes 1. This setting is not required when the watchdog timer is not used.

2. Separately check the WEPRERR bit to check for errors in executing the erase command on a write-

prohibited area.

<R>

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<R>

Figure 19-20. Example of Block Erase Operation in Self Programming Mode

Block erasure

<1> Set erase command

(FLCMD = 03H)

<2> Set no. of block to be erased

to FLAPH

<3> Set FLAPL to 00H

<4> Set the same value as

that of FLAPH to FLAPHC

<5> Set FLAPLC to 00H

<6> Clear PFS

<7> Clear & restart WDT counter

(WDTE = ACH)^Note

<8> Execute HALT instruction

<9> Check execution result

Abnormal

<10> Check

the number of executions of

the erase command

Normal

The erase command

can be re-executed.

<12> Normal termination

The erase command

cannot be re-executed.

<11> Abnormal termination

Note This setting is not required when the watchdog timer is not used.

Remark <1> to <12> in Figure 19-20 correspond to <1> to <12> in 19.8.6 (previous page).

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An example of a program that performs a block erase in self programming mode is shown below.

;----------------------------

;START

;----------------------------

<R>

MOV

B,#48

; Specifies the number of times the erase command can be

; executed.

; (4.0 V to 5.5 V Time for executing block erasure 100 times)

FlashBlockErase:

MOV

FLCMD,#03H

FLAPH,#07H

FLAPL,#00H

FLAPHC,#07H

FLAPLC,#00H

; Sets flash control command (block erase)

; Sets number of block to be erased (block 7 is specified here)

; Fixes FLAPL to “00H”

; Sets erase block compare number (same value as that of FLAPH)

; Fixes FLAPLC to “00H”

EraseRetry:

MOV

PFS,#00H

; Clears flash status register

; Clears & restarts WDT

MOV

WDTE,#0ACH

HALT

MOV

; Self programming is started

A,PFS

CMP

A,#00H

; Checks execution result

<R>

BZ

$StatusNormal ; Normal termination

DBNZ

B,$EraseRetry ; Checks whether to re-execute the erase command.

;---------------------------------------------------------------------

;END (abnormal termination processing); Perform processing to shift to

normal mode in order to return to normal processing

;---------------------------------------------------------------------

StatusError:

;---------------------------------------------------------------------

;END (normal termination processing)

;---------------------------------------------------------------------

StatusNormal:

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19.8.7 Example of block blank check operation in self programming mode

An example of the block blank check operation in self programming mode is explained below.

<1> Set 04H (block blank check) to the flash program command register (FLCMD).

<2> Set the number of block for which a blank check is performed, to flash address pointer H (FLAPH).

<3> Set flash address pointer L (FLAPL) to 00H.

<4> Write the same value as FLAPH to the flash address pointer H compare register (FLAPHC).

<5> Set the flash address pointer L compare register (FLAPLC) to FFH.

<6> Clear the flash status register (PFS).

<7> Write ACH to the watchdog timer enable register (WDTE) (clear and restart the watchdog timer counter)^Note

.

<8> Execute the HALT instruction then start self programming. (Execute an instruction immediately after the

HALT instruction if self programming has been executed.)

<9> Check if a self programming error has occurred using bit 1 (VCERR) and bit 2 (WEPRERR) of PFS.

Abnormal → <10>

Normal

→ <11>

<10> Block blank check is abnormally terminated.

<11> Block blank check is normally terminated.

Note This setting is not required when the watchdog timer is not used.

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Figure 19-21. Example of Block Blank Check Operation in Self Programming Mode

Block blank check

<1> Set block blank check

command (FLCMD = 04H)

<2> Set no. of block for

blank check to FLAPH

<3> Set FLAPL to 00H

<4> Set the same value as

that of FLAPH to FLAPHC

<5> Set FLAPLC to 00H

<6> Clear PFS

<7> Clear & restart WDT counter

(WDTE = ACH)^Note

<8> Execute HALT instruction

Abnormal

<9> Check execution result

(VCERR and WEPRERR flags)

Normal

<10> Abnormal termination

<11> Normal termination

Note This setting is not required when the watchdog timer is not used.

Remark <1> to <11>in Figure 19-21 correspond to <1> to <11> in 19.8.7 (previous page).

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An example of a program that performs a block blank check in self programming mode is shown below.

;----------------------------

;START

;----------------------------

FlashBlockBlankCheck:

MOV

FLCMD,#04H

FLAPH,#07H

; Sets flash control command (block blank check)

; Sets number of block for blank check (block 7 is specified

; here)

MOV

FLAPL,#00H

; Fixes FLAPL to “00H”

FLAPHC,#07H

; Sets blank check block compare number (same value as that of

; FLAPH)

MOV

FLAPLC,#0FFH

; Fixes FLAPLC to “FFH”

MOV

HALT

MOV

PFS,#00H

; Clears flash status register

; Clears & restarts WDT

WDTE,#0ACH

; Self programming is started

A,PFS

CmdStatus,A

; Execution result is stored in variable

; (CmdStatus = 0: normal termination, other than 0: abnormal

; termination)

;----------------------------

;END

;----------------------------

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19.8.8 Example of byte write operation in self programming mode

An example of the byte write operation in self programming mode is explained below.

<1> Set 05H (byte write) to the flash program command register (FLCMD).

<2> Set the number of block to which data is to be written, to flash address pointer H (FLAPH).

<3> Set the address at which data is to be written, to flash address pointer L (FLAPL).

<4> Set the data to be written, to the flash write buffer register (FLW).

<5> Clear the flash status register (PFS).

<6> Write ACH to the watchdog timer enable register (WDTE) (clear and restart the watchdog timer counter)^Note

.

<7> Execute the HALT instruction then start self programming. (Execute an instruction immediately after the

HALT instruction if self programming has been executed.)

<8> Check if a self programming error has occurred using bit 1 (VCERR) and bit 2 (WEPRERR) of PFS.

Abnormal → <9>

Normal

→ <10>

<9> Byte write processing is abnormally terminated.

<10> Byte write processing is normally terminated.

Note This setting is not required when the watchdog timer is not used.

Caution If a write results in failure, erase the block once and write to it again.

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Figure 19-22. Example of Byte Write Operation in Self Programming Mode

Byte write

<1> Set byte write command

(FLCMD = 05H)

<2> Set no. of block to be

written, to FLAPH

<3> Set address at which data

is to be written, to FLAPL

<4> Set data to be written to FLW

<5> Clear PFS

<6> Clear & restart WDT counter

(WDTE = ACH)^Note

<7> Execute HALT instruction

Abnormal

<8> Check execution result

(VCERR and WEPRERR flags)

Normal

<10> Normal termination

<9> Abnormal termination

Note This setting is not required when the watchdog timer is not used.

Remark <1> to <10> in Figure 19-22 correspond to <1> to <10> in 19.8.8 (previous page).

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An example of a program that performs a byte write in self programming mode is shown below.

;----------------------------

;START

;----------------------------

FlashWrite:

MOV

FLCMD,#05H

FLAPH,#07H

; Sets flash control command (byte write)

; Sets address to which data is to be written, with

; FLAPH (block 7 is specified here)

MOV

FLAPL,#20H

FLW,#10H

; Sets address to which data is to be written, with

; FLAPL (address 20H is specified here)

; Sets data to be written (10H is specified here)

MOV

HALT

MOV

PFS,#00H

; Clears flash status register

; Clears & restarts WDT

WDTE,#0ACH

; Self programming is started

A,PFS

CmdStatus,A

; Execution result is stored in variable

; (CmdStatus = 0: normal termination, other than 0: abnormal

; termination)

;----------------------------

;END

;----------------------------

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19.8.9 Examples of internal verify operation in self programming mode

Examples of internal verify 1 and 2 operations in self programming mode are explained below.

• Internal verify 1

<1> Set 01H (internal verify 1) to the flash program command register (FLCMD).

<2> Set the block number for which internal verify is performed, to flash address pointer H (FLAPH).

<3> Set 00H to the flash address pointer L (FLAPL).

<4> Write the same value as that of FLAPH to the flash address pointer H compare register (FLAPHC).

<5> Set FFH to the flash address pointer L compare register (FLAPLC).

<6> Clear the flash status register (PFS).

<7> Write ACH to the watchdog timer enable register (WDTE) (clear and restart the watchdog timer counter)^Note

.

<8> Execute the HALT instruction then start self programming. (Execute an instruction immediately after the

HALT instruction if self programming has been executed.)

<9> Check if a self programming error has occurred using bit 1 (VCERR) and bit 2 (WEPRERR) of PFS.

Abnormal → <10>

Normal → <11>

<10> Internal verify processing is terminated abnormally.

<11> Internal verify processing is terminated normally.

• Internal verify 2

<1> Set 02H (internal verify 2) to the flash program command register (FLCMD).

<2> Set the block number for which internal verify is performed, to flash address pointer H (FLAPH).

<3> Set the verify start address to the flash address pointer L (FLAPL).

<4> Write the same value as that of FLAPH to the flash address pointer H compare register (FLAPHC).

<5> Set the verify end address to the flash address pointer L compare register (FLAPLC).

<6> Clear the flash status register (PFS).

<7> Write ACH to the watchdog timer enable register (WDTE) (clear and restart the watchdog timer counter)^Note

.

<8> Execute the HALT instruction then start self programming. (Execute an instruction immediately after the

HALT instruction if self programming has been executed.)

<9> Check if a self programming error has occurred using bit 1 (VCERR) and bit 2 (WEPRERR) of PFS.

Abnormal → <10>

Normal → <11>

<10> Internal verify processing is terminated abnormally.

<11> Internal verify processing is terminated normally.

Note This setting is not required when the watchdog timer is not used.

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Figure 19-23. Example of Internal Verify 1 Operation in Self Programming Mode

Internal verify 1

<1> Set internal verify 1

command (FLCMD = 01H)

<2> Set block no. for

internal verify, to FLAPH

<3> Set 00H to FLAPL

<4> Set the same value as

that of FLAPH to FLAPHC

<5> Set FFH to FLAPLC

<6> Clear PFS

<7> Clear & restart WDT counter

(WDTE = ACH)^Note

<8> Execute HALT instruction

Abnormal

<9> Check execution result

(VCERR and WEPRERR flags)

Normal

<11> Normal termination

<10> Abnormal termination

Note This setting is not required when the watchdog timer is not used.

Remark <1> to <11> in Figure 19-23 correspond to <1> to <11> of internal verify 1 in 19.8.9 (previous page).

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Figure 19-24. Example of Internal Verify 2 Operation in Self Programming Mode

Internal verify 2

<1> Set internal verify 2

command (FLCMD = 02H)

<2> Set block no. for

internal verify, to FLAPH

<3> Sets FLAPL to the start address

<4> Set the same value as

that of FLAPH to FLAPHC

<5> Sets FLAPLC to the end address

<6> Clear PFS

<7> Clear & restart WDT counter

(WDTE = ACH)^Note

<8> Execute HALT instruction

<9> Check execution result

Abnormal

(VCERR and WEPRERR flags)

Normal

<11> Normal termination

<10> Abnormal termination

Note This setting is not required when the watchdog timer is not used.

Remark <1> to <11> in Figure 19-24 correspond to <1> to <11> of internal verify 2 in 19.8.9 (the page before

last).

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Example programs that perform internal verify 1 and 2 in self programming mode are shown below.

• Internal verify 1

;----------------------------

;START

;----------------------------

FlashVerify:

MOV

FLCMD,#01H

FLAPH,#07H

; Sets flash control command (internal verify 1)

; Sets block number for which internal verify is performed,

; to FLAPH (Example: Block 7 is specified here)

; Sets 00H

MOV

FLAPL,#00H

FLAPHC,#07H

FLAPLC,#FFH

; Sets FFH

MOV

HALT

MOV

PFS,#00H

; Clears flash status register

; Clears & restarts WDT

WDTE,#0ACH

; Self programming is started

A,PFS

CmdStatus,A

; Execution result is stored in variable

; (CmdStatus = 0: normal termination, other than 0: abnormal

; termination)

;----------------------------

;END

;----------------------------

• Internal verify 2

;----------------------------

;START

;----------------------------

FlashVerify:

MOV

FLCMD,#02H

FLAPH,#07H

; Sets flash control command (internal verify 2)

; Sets block number for which internal verify is

; performed, to FLAPH (Example: Block 7 is specified here)

; Sets FLAPL to the start address for verify (Example: Address

; 00H is specified here)

MOV

FLAPL,#00H

MOV

FLAPHC,#07H

FLAPLC,#20H

; Sets FLAPLC to the end address for verify (Example: Address

; 20H is specified here)

MOV

HALT

MOV

PFS,#00H

; Clears flash status register

; Clears & restarts WDT

WDTE,#0ACH

; Self programming is started

A,PFS

CmdStatus,A

; Execution result is stored in variable

; (CmdStatus = 0: normal termination, other than 0: abnormal

; termination)

;----------------------------

;END

;----------------------------

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19.8.10 Examples of operation when command execution time should be minimized in self programming

mode

Examples of operation when the command execution time should be minimized in self programming mode are

explained below.

(1) Erasure to blank check

<1> Mode is shifted from normal mode to self programming mode (<1> to <7> in 19.8.4)

<2> Execution of block erase → Error check (<1> to <12> in 19.8.6)

<3> Execution of block blank check → Error check (<1> to <11> in 19.8.7)

<4> Mode is shifted from self programming mode to normal mode (<1> to <6> in 19.8.5)

Figure 19-25. Example of Operation When Command Execution Time Should Be Minimized

(from Erasure to Blank Check)

Erasure to blank check

Figure 19-18

<1> to <7>

<1> Shift to self programming

mode

<2> Execute block erase

Figure 19-20

<1> to <12>

Abnormal

<2> Check execution result

(VCERR and WEPRERR flags)

Normal

<3> Execute block blank check

Figure 19-21

<1> to <11>

Abnormal

<3> Check execution result

(VCERR and WEPRERR flags)

Normal

Figure 19-19

<1> to <6>

<4> Shift to normal mode

Normal termination

Abnormal termination^Note

Note Perform processing to shift to normal mode in order to return to normal processing.

Remark <1> to <4> in Figure 19-25 correspond to <1> to <4> in 19.8.10 (1) above.

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An example of a program when the command execution time (from erasure to black check) should be minimized in

self programming mode is shown below.

;---------------------------------------------------------------------

;START

;---------------------------------------------------------------------

MOV

MK0,#11111111B

MK1,#11111111B

FLCMD,#00H

; Masks all interrupts

; Clears FLCMD register

DI

ModeOnLoop:

; Configure settings so that the CPU clock ≥ 1 MHz

; Clears flash status register

MOV

PFS,#00H

PFCMD,#0A5H

FLPMC,#01H

FLPMC,#0FEH

FLPMC,#01H

; PFCMD register control

; FLPMC register control (sets value)

; FLPMC register control (inverts set value)

; Sets self programming mode with FLPMC register control (sets

; value)

NOP

HALT

BT

PFS.0,$ModeOnLoop ; Checks completion of write to specific registers

; Repeats the same processing when an error occurs

FlashBlockErase:

MOV

FLCMD,#03H

FLAPH,#07H

; Sets flash control command (block erase)

; Sets number of block to be erased (block 7 is specified

; here)

MOV

FLAPL,#00H

; Fixes FLAPL to “00H”

FLAPHC,#07H

; Sets erase block compare number (same value as that of

; FLAPH)

MOV

FLAPLC,#00H

WDTE,#0ACH

; Fixes FLAPLC to “00H”

MOV

HALT

MOV

CMP

BNZ

; Clears & restarts WDT

; Self programming is started

A,PFS

A,#00H

$StatusError

; Checks erase error

; Performs abnormal termination processing when an error

; occurs

FlashBlockBlankCheck:

MOV

FLCMD,#04H

; Sets flash control command (block blank check)

; Sets number of block for blank check (block 7 is specified

; here)

FLAPH,#07H

MOV

FLAPL,#00H

; Fixes FLAPL to “00H”

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MOV

FLAPHC,#07H

; Sets blank check block compare number (same value as of

; FLAPH)

MOV

HALT

MOV

CMP

BNZ

FLAPLC,#0FFH

WDTE,#0ACH

; Fixes FLAPLC to “FFH”

; Clears & restarts WDT

; Self programming is started

A,PFS

A,#00H

$StatusError

; Checks blank check error

; Performs abnormal termination processing when an error

; occurs

MOV

FLCMD,#00H

; Clears FLCMD register

ModeOffLoop:

MOV

PFS,#00H

; Clears flash status register

PFCMD,#0A5H

FLPMC,#00H

FLPMC,#0FFH

FLPMC,#00H

; PFCMD register control

; FLPMC register control (sets value)

; FLPMC register control (inverts set value)

; Sets normal mode via FLPMC register control (sets value)

BT

PFS.0,$ModeOffLoop ; Checks completion of write to specific registers

; Repeats the same processing when an error occurs

; Restore the CPU clock to its setting before the self

; programming, after normal completion of the specific

; sequence

MOV

MK0,#INT_MK0

MK1,#INT_MK1

; Restores interrupt mask flag

EI

BR

StatusNormal

;---------------------------------------------------------------------

;END (abnormal termination processing); Perform processing to shift to

normal mode in order to return to normal processing

;---------------------------------------------------------------------

StatusError:

;---------------------------------------------------------------------

;END (normal termination processing)

;---------------------------------------------------------------------

StatusNormal:

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(2) Write to internal verify

<1> Mode is shifted from normal mode to self programming mode (<1> to <7> in 19.8.4)

<2> Specification of source data for write

<3> Execution of byte write → Error check (<1> to <10> in 19.8.8)

<4> <3> is repeated until all data are written.

<5> Execution of internal verify 2 → Error check (<1> to <11> in 19.8.9)

<6> Mode is shifted from self programming mode to normal mode (<1> to <6> in 19.8.5)

Figure 19-26. Example of Operation When Command Execution Time Should Be Minimized

(from Write to Internal Verify)

Write to internal verify

<1> Shift to self programming

mode

Figure 19-18

<1> to <7>

<2> Set source data for write

<3> Execute byte write command

Figure 19-22

<1> to <10>

<3> Check execution result

Abnormal

(VCERR and WEPRERR flags)

Normal

Yes

<4> All data written?

No

<5> Execute internal verify 2

command

Figure 19-23

<1> to <11>

Abnormal

<5> Check execution result

(VCERR and WEPRERR flags)

Normal

Figure 19-19

<1> to <6>

<6> Shift to normal mode

Normal termination

Abnormal termination^Note

Note Perform processing to shift to normal mode in order to return to normal processing.

Remark <1> to <6> in Figure 19-26 correspond to <1> to <6> in 19.8.10 (2) above.

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An example of a program when the command execution time (from write to internal verify) should be minimized in

self programming mode is shown below.

;---------------------------------------------------------------------

;START

;---------------------------------------------------------------------

MOV

DI

MK0,#11111111B

MK1,#11111111B

FLCMD,#00H

; Masks all interrupts

; Clears FLCMD register

ModeOnLoop:

; Configure settings so that the CPU clock ≥ 1 MHz

; Clears flash status register

MOV

PFS,#00H

PFCMD,#0A5H

FLPMC,#01H

FLPMC,#0FEH

FLPMC,#01H

; PFCMD register control

; FLPMC register control (sets value)

; FLPMC register control (inverts set value)

; Sets self programming mode with FLPMC register control

; (sets value)

NOP

HALT

BT

PFS.0,$ModeOnLoop ; Checks completion of write to specific registers

; Repeats the same processing when an error occurs

FlashWrite:

MOVW

HL,#DataAdrTop

DE,#WriteAdr

; Sets address at which data to be written is located

; Sets address at which data is to be written

MOVW

FlashWriteLoop:

MOV

FLCMD,#05H

A,D

; Sets flash control command (byte write)

; Sets address at which data is to be written

; Sets data to be written

FLAPH,A

A,E

FLAPL,A

A,[HL]

FLW,A

MOV

HALT

MOV

CMP

BNZ

WDTE,#0ACH

; Clears & restarts WDT

; Self programming is started

A,PFS

A,#00H

$StatusError

; Checks write error

; Performs abnormal termination processing when an error

; occurs

INCW

MOVW

CMPW

BNC

HL

; Address at which data to be written is located + 1

AX,HL

AX,#DataAdrBtm

$FlashVerify

; Performs internal verify processing

; if write of all data is completed

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INCW

BR

DE

; Address at which data is to be written + 1

FlashWriteLoop

FlashVerify:

MOVW

HL,#WriteAdr

; Sets verify address

MOV

FLCMD,#02H

A,H

; Sets flash control command (internal verify 2)

; Sets verify start address

; Sets verify end address

FLAPH,A

A,L

FLAPL,A

A,D

FLAPHC,A

A,E

FLAPLC,A

; Sets verify end address

MOV

HALT

MOV

CMP

BNZ

WDTE,#0ACH

; Clears & restarts WDT

; Self programming is started

A,PFS

A,#00H

$StatusError

; Checks internal verify error

; Performs abnormal termination processing when an error

; occurs

MOV

FLCMD,#00H

; Clears FLCMD register

ModeOffLoop:

MOV

PFS,#00H

; Clears flash status register

PFCMD,#0A5H

FLPMC,#00H

FLPMC,#0FFH

FLPMC,#00H

; PFCMD register control

; FLPMC register control (sets value)

; FLPMC register control (inverts set value)

; Sets normal mode via FLPMC register control (sets value)

BT

PFS.0,$ModeOffLoop ; Checks completion of write to specific registers

; Repeats the same processing when an error occurs

; Restore the CPU clock to its setting before the self

; programming, after normal completion of the specific

; sequence

MOV

MK0,#INT_MK0

MK1,#INT_MK1

; Restores interrupt mask flag

EI

BR

StatusNormal

;---------------------------------------------------------------------

;END (abnormal termination processing); Perform processing to shift to

normal mode in order to return to normal processing

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;---------------------------------------------------------------------

StatusError:

;---------------------------------------------------------------------

;END (normal termination processing)

;---------------------------------------------------------------------

StatusNormal:

;---------------------------------------------------------------------

; Data to be written

;---------------------------------------------------------------------

DataAdrTop:

DB

XXH

DB

:

DB

XXH

DataAdrBtm:

;---------------------------------------------------------------------

Remark Internal verify 2 is used in the above program example. Use internal verify 1 to verify a whole block.

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CHAPTER 19 FLASH MEMORY

19.8.11 Examples of operation when interrupt-disabled time should be minimized in self programming mode

Examples of operation when the interrupt-disabled time should be minimized in self programming mode are

explained below.

(1) Erasure to blank check

<1> Specification of block erase command (<1> to <5> in 19.8.6)

<2> Mode is shifted from normal mode to self programming mode (<1> to <7> in 19.8.4)

<3> Execution of block erase command → Error check (<6> to <12> in 19.8.6)

<4> Mode is shifted from self programming mode to normal mode (<1> to <6> in 19.8.5)

<5> Specification of block blank check command (<1> to <5> in 19.8.7)

<6> Mode is shifted from normal mode to self programming mode (<1> to <7> in 19.8.4)

<7> Execution of block blank check command → Error check (<6> to <11> in 19.8.7)

<8> Mode is shifted from self programming mode to normal mode (<1> to <6> in 19.8.5)

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<R>

Figure 19-27. Example of Operation When Interrupt-Disabled Time Should Be Minimized

(from Erasure to Blank Check)

Erasure to blank check

Figure 19-20

<1> to <5>

<1> Specify block erase command

<2> Shift to self programming

mode

Figure 19-18

<1> to <7>

<3> Execute block erase command

Figure 19-20

<6> to <12>

Abnormal

<3> Check execution result

Normal

Figure 19-19

<1> to <6>

<4> Shift to normal mode

<5> Specify block blank

check command

Figure 19-21

<1> to <5>

<6> Shift to self programming

mode

Figure 19-18

<1> to <7>

<7> Execute block blank

check command

Figure 19-21

<6> to <11>

<7> Check execution result

Abnormal

(VCERR and WEPRERR flags)

Normal

Figure 19-19

<1> to <6>

<8> Shift to normal mode

Normal termination

Abnormal termination^Note

Note Perform processing to shift to normal mode in order to return to normal processing.

Remark <1> to <8> in Figure 19-27 correspond to <1> to <8> in 19.8.11 (1) (previous page).

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An example of a program when the interrupt-disabled time (from erasure to blank check) should be minimized in

self programming mode is shown below.

;---------------------------------------------------------------------

;START

;---------------------------------------------------------------------

MOV

B,#48

; Specifies the number of times the erase command can be

; executed.

<R>

; (4.0 V to 5.5 V Time for executing block erasure 100 times)

FlashBlockErase:

; Sets erase command

MOV

FLCMD,#03H

FLAPH,#07H

FLAPL,#00H

FLAPHC,#07H

FLAPLC,#00H

; Sets flash control command (block erase)

; Sets number of block to be erased (block 7 is specified here)

; Fixes FLAPL to “00H”

; Sets erase block compare number (same value as that of FLAPH)

; Fixes FLAPLC to “00H”

CALL

!ModeOn

; Shift to self programming mode

EraseRetry:

; Execution of erase command

MOV

HALT

MOV

CMP

BNZ

PFS,#00H

; Clears flash status register

; Clears & restarts WDT

WDTE,#0ACH

; Self programming is started

A,PFS

A,#00H

; Checks execution result

; Checks erase error

$RetryCheck

; Performs abnormal termination processing when an error

; occurs.

CALL

!ModeOff

; Shift to normal mode

; Sets blank check command

MOV

FLCMD,#04H

FLAPH,#07H

FLAPL,#00H

FLAPHC,#07H

; Sets flash control command (block blank check)

; Sets block number for blank check (block 7 is specified here)

; Fixes FLAPL to “00H”

; Sets blank check block compare number (same value as that of

; FLAPH)

MOV

FLAPLC,#0FFH

!ModeOn

; Fixes FLAPLC to “FFH”

CALL

; Shift to self programming mode

; Execution of blank check command

MOV

HALT

MOV

PFS,#00H

; Clears flash status register

; Clears & restarts WDT

WDTE,#0ACH

; Self programming is started

A,PFS

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CMP

BNZ

A,#00H

; Checks execution result

$StatusError

; Checks blank check error

; Performs abnormal termination processing when an error occurs

CALL

!ModeOff

; Shift to normal mode

BR

RetryCheck:

DBNZ

StatusNormal

B,$EraseRetry

<R>

;---------------------------------------------------------------------

;END (abnormal termination processing); Perform processing to shift to

normal mode in order to return to normal processing

;---------------------------------------------------------------------

StatusError:

;---------------------------------------------------------------------

;END (normal termination processing)

;---------------------------------------------------------------------

StatusNormal:

;---------------------------------------------------------------------

;Processing to shift to self programming mode

;---------------------------------------------------------------------

ModeOn:

MOV

MK0,#11111111B

MK1,#11111111B

FLCMD,#00H

; Masks all interrupts

; Clears FLCMD register

DI

ModeOnLoop:

; Configure settings so that the CPU clock ≥ 1 MHz

; Clears flash status register

MOV

PFS,#00H

PFCMD,#0A5H

FLPMC,#01H

FLPMC,#0FEH

FLPMC,#01H

; PFCMD register control

; FLPMC register control (sets value)

; FLPMC register control (inverts set value)

; Sets self programming mode via FLPMC register control (sets

; value)

NOP

HALT

BT

PFS.0,$ModeOnLoop ; Checks completion of write to specific registers

; Repeats the same processing when an error occurs

RET

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;---------------------------------------------------------------------

; Processing to shift to normal mode

;---------------------------------------------------------------------

ModeOffLoop:

MOV

FLCMD,#00H

PFS,#00H

; Clears FLCMD register

; Clears flash status register

PFCMD,#0A5H

FLPMC,#00H

FLPMC,#0FFH

FLPMC,#00H

; PFCMD register control

; FLPMC register control (sets value)

; FLPMC register control (inverts set value)

; Sets normal mode via FLPMC register control (sets value)

BT

PFS.0,$ModeOffLoop ; Checks completion of write to specific registers

; Repeats the same processing when an error occurs

; Restore the CPU clock to its setting before the self

; programming, after normal completion of the specific

; sequence

MOV

MK0,#INT_MK0

MK1,#INT_MK1

; Restores interrupt mask flag

EI

RET

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(2) Write to internal verify

<1> Specification of source data for write

<2> Specification of byte write command (<1> to <4> in 19.8.8)

<3> Mode is shifted from normal mode to self programming mode (<1> to <7> in 19.8.4)

<4> Execution of byte write command → Error check (<5> to <10> in 19.8.8)

<5> Mode is shifted from self programming mode to normal mode (<1> to <6> in 19.8.5)

<6> <2> to <5> is repeated until all data are written.

<7> The internal verify command is specified (<1> to <5> in 19.8.9)

<8> Mode is shifted from normal mode to self programming mode (<1> to <7> in 19.8.4)

<9> Execution of internal verify command → Error check (<6> to <11> in 19.8.9)

<10> Mode is shifted from self programming mode to normal mode (<1> to <6> in 19.8.5)

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Figure 19-28. Example of Operation When Interrupt-Disabled Time Should Be Minimized

(from Write to Internal Verify)

Write to internal verify

<1> Set source data for write

Figure 19-22

<1> to <4>

<2> Specify byte write command

<3> Shift to self programming

mode

Figure 19-18

<1> to <7>

<4> Execute byte write command

Figure 19-22

<5> to <10>

Abnormal

<4> Check execution result

(VCERR and WEPRERR flags)

Normal

Figure 19-19

<1> to <6>

<5> Shift to normal mode

Yes

<6> All data written?

No

Figure 19-23

<1> to <5>

<7> Specify internal verify command

<8> Shift to self programming

mode

Figure 19-18

<1> to <7>

<9> Execute internal verify command

Figure 19-23

<6> to <11>

<9> Check execution result

Abnormal

(VCERR and WEPRERR flags)

Normal

Figure 19-19

<1> to <6>

<10> Shift to normal mode

Normal termination

Abnormal termination^Note

Note Perform processing to shift to normal mode in order to return to normal processing.

Remark <1> to <10> in Figure 19-28 correspond to <1> to <10> in 19.8.11 (2) (previous page).

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An example of a program when the interrupt-disabled time (from write to internal verify) should be minimized in self

programming mode is shown below.

;---------------------------------------------------------------------

;START

;---------------------------------------------------------------------

; Sets write command

FlashWrite:

MOVW

HL,#DataAdrTop ; Sets address at which data to be written is located

DE,#WriteAdr

; Sets address at which data is to be written

FlashWriteLoop:

MOV

FLCMD,#05H

A,D

; Sets flash control command (byte write)

; Sets address at which data is to be written

; Sets data to be written

FLAPH,A

A,E

FLAPL,A

A,[HL]

FLW,A

CALL

!ModeOn

; Shift to self programming mode

; Execution of write command

MOV

HALT

MOV

CMP

BNZ

PFS,#00H

; Clears flash status register

; Clears & restarts WDT

WDTE,#0ACH

; Self programming is started

A,PFS

A,#00H

$StatusError

; Checks write error

; Performs abnormal termination processing when an error

; occurs

CALL

!ModeOff

; Shift to normal mode

MOV

MK0,#INT_MK0

MK1,#INT_MK1

; Restores interrupt mask flag

EI

; Judgment of writing all data

INCW

MOVW

CMPW

BNC

HL

; Address at which data to be written is located + 1

AX,HL

AX,#DataAdrBtm ; Performs internal verify processing

$FlashVerify

; if write of all data is completed

INCW

BR

DE

; Address at which data is to be written + 1

FlashWriteLoop

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; Setting internal verify command

FlashVerify:

MOVW

HL,#WriteAdr

; Sets verify address

MOV

FLCMD,#02H

A,H

; Sets flash control command (internal verify 2)

; Sets verify start address

; Sets verify end address

FLAPH,A

A,L

FLAPL,A

A,D

FLAPHC,A

A,E

FLAPLC,A

; Sets verify end address

CALL

!ModeOn

; Shift to self programming mode

; Execution of internal verify command

MOV

HALT

MOV

CMP

BNZ

PFS,#00H

; Clears flash status register

; Clears & restarts WDT

WDTE,#0ACH

; Self programming is started

A,PFS

A,#00H

$StatusError

; Checks internal verify error

; Performs abnormal termination processing when an error occurs

CALL

BR

!ModeOff

; Shift to normal mode

StatusNormal

;---------------------------------------------------------------------

;END (abnormal termination processing); Perform processing to shift to

normal mode in order to return to normal processing

;---------------------------------------------------------------------

StatusError:

;---------------------------------------------------------------------

;END (normal termination processing)

;---------------------------------------------------------------------

StatusNormal:

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;---------------------------------------------------------------------

;Processing to shift to self programming mode

;---------------------------------------------------------------------

ModeOn:

MOV

MK0,#11111111B ; Masks all interrupts

MK1,#11111111B

FLCMD,#00H

; Clears FLCMD register

DI

ModeOnLoop:

; Configure settings so that the CPU clock ≥ 1 MHz

; Clears flash status register

MOV

PFS,#00H

PFCMD,#0A5H

FLPMC,#01H

FLPMC,#0FEH

FLPMC,#01H

; PFCMD register control

; FLPMC register control (sets value)

; FLPMC register control (inverts set value)

; Sets self programming mode via FLPMC register control (sets

; value)

NOP

HALT

BT

PFS.0,$ModeOnLoop ; Checks completion of write to specific registers

; Repeats the same processing when an error occurs

RET

;---------------------------------------------------------------------

; Processing to shift to normal mode

;---------------------------------------------------------------------

ModeOffLoop:

MOV

FLCMD,#00H

PFS,#00H

; Clears FLCMD register

; Clears flash status register

PFCMD,#0A5H

FLPMC,#00H

FLPMC,#0FFH

FLPMC,#00H

; PFCMD register control

; FLPMC register control (sets value)

; FLPMC register control (inverts set value)

; Sets normal mode via FLPMC register control (sets value)

BT

PFS.0,$ModeOffloop; Checks completion of write to specific registers

; Repeats the same processing when an error occurs

; Restore the CPU clock to its setting before the self

; programming, after normal completion of the specific

; sequence

MOV

MK0,#INT_MK0

MK1,#INT_MK1

; Restores interrupt mask flag

EI

RET

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CHAPTER 19 FLASH MEMORY

;---------------------------------------------------------------------

;Data to be written

;---------------------------------------------------------------------

DataAdrTop:

DB

XXH

:

DB

XXH

DataAdrBtm:

;---------------------------------------------------------------------

Remark Internal verify 2 is used in the above program example. Use internal verify 1 to verify a whole block.

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CHAPTER 20 ON-CHIP DEBUG FUNCTION

20.1 Connecting QB-MINI2 to 78K0S/KB1+

The 78K0S/KB1+ uses RESET, X1, X2, INTP3, VDD, and GND pins to communicate with the host machine via an

on-chip debug emulator (QB-MINI2).

<R>

Caution The 78K0S/KB1+ has an on-chip debug function, which is provided for development and

evaluation. Do not use the on-chip debug function in products designated for mass production,

because the guaranteed number of rewritable times of the flash memory may be exceeded when

this function is used, and product reliability therefore cannot be guaranteed. NEC Electronics is

not liable for problems occurring when the on-chip debug function is used.

Figure 20-1. Recommended Circuit Connection

V

DD

VDD

Target connector

Target device

3 to 10 kΩ

1

GND

RESET_OUT

DATA

2

RESET^{Note 1}

X2^{Note 2}

3

4

V

DD

Note 3

5

DATA

R.F.U.

H/S^{Note 4}

CLK

V

DD

6

VDD

7

1 kΩ

8

V

DD

9

X1^{Note 2}

GND

10

11

12

13

14

15

16

R.F.U.

INTP

INTP3^{Note 5}

R.F.U.

CLK

10 kΩ

1 to 10 kΩ

VDD

RESET_IN

R.F.U.

1 kΩ

Reset circuit

RESET signal

Caution The constants described in the circuit connection example are reference values. If you

perform flash programming aiming at mass production, thoroughly evaluate whether the

specifications of the target device are satisfied.

Notes 1. The RESET pin is used to download the monitor program at debugger startup or to implement

forced reset. Therefore, a pin that alternately functions as the RESET pin cannot be used. For

reset pin connection, refer to QB-MINI2 User’s Manual (U18371E).

2. This is the pin connection when the X1 and X2 pins are not used in the target system. When using

the X1 and X2 pins, refer to 20.1.2 Connection of X1 and X2 pins.

3. No problem will occur if the dashed line portions are connected.

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CHAPTER 20 ON-CHIP DEBUG FUNCTION

Notes 4. This pin is connected to enhance the accuracy of time measurement between run and break during

debugging. Debugging is possible even if this pin is left open, but measurement error occurs in

several ms units.

5. The INTP3 pin is used for communication between QB-MINI2 and the target device during

debugging. When debugging is performed with QB-MINI2, therefore, the INTP3 pin and its

alternate-function pin cannot be used. For INTP3 pin connection, refer to 20.1.1 Connection of

INTP3 pin.

Pins for communication depend on whether the monitor program has been written or not. (refer to Table 20-1)

X1 and X2 pins can be used as I/O port pins or the pins for oscillation, after the monitor program has been written.

Table 20-1. Pins for communication with QB-MINI2

Before writing the monitor program

X1, X2, RESET, INTP3, VDD, VSS

After writing the monitor program

RESET, INTP3, VDD, VSS

20.1.1 Connection of INTP3 pin

The INTP3 pin is used only for communication between QB-MINI2 and the target device during debugging.

Design circuits appropriately according to the relevant case among the cases shown below.

(1) INTP3 pin is not used in target system (as is illustrated in Figure 20-1. Recommended Circuit

Connection)

→ See Figure 20-2.

(2) QB-MINI2 is used only for programming, not for debugging

→ See Figure 20-3.

(3) QB-MINI2 is used for debugging and debugging of the INTP3 pin is performed only with a real machine

→ See Figure 20-4.

Figure 20-2. Circuit Connection for the Case Where INTP3 Pin Is Not Used in Target System

V

DD

Target device

INTP3

Target connector

INTP

1 kΩ

12

Figure 20-3. Circuit Connection for the Case Where QB-MINI2 Is Used Only for Programming

Target device

Target connector

12

INTP

INTP3

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CHAPTER 20 ON-CHIP DEBUG FUNCTION

Figure 20-4. Circuit Connection for the Case Where QB-MINI2 Is Used for Debugging and

Debugging of INTP3 Pin Is Performed Only with Real Machine

V

DD

Target connector

INTP

1 kΩ

Target device

INTP3

1

12

2

3

External device

I/O to INTP3

* Jumper setting

When debugging with QB-MINI2 connected:

Other than above:

1-2 shorted

2-3 shorted

Caution If debugging is performed with a real machine running, without using QB-MINI2, write the user

program using the QB-Programmer. Programs downloaded by the debugger include the monitor

program, and such a program malfunctions if it is not controlled via QB-MINI2.

20.1.2 Connection of X1 and X2 pins

The X1 and X2 pins are used when the debugger is started for the first time (when downloading the monitor

program) and when programming is performed with the QB-Programmer.

Figure 20-5. Circuit Connection for the Case Where X1 and X2 Pins Are Used in Target System

Target device

Target connector

X2

3

9

1

X2

2

3

1

X1

2

3

External components

Oscillator or

external device

* Jumper setting

When debugger is started for the first time

(downloading the monitor program) or when

programming is performed with QB-Programmer: 1-2 shorted

Other than above:

2-3 shorted

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CHAPTER 20 ON-CHIP DEBUG FUNCTION

20.2 Securing of user resources

The user must prepare the following to perform communication between QB-MINI2 and the target device and

implement each debug function. For details of the setting, refer to QB-MINI2 User’s Manual (U18371E).

• Securement of memory space

The shaded portions in Figure 20-6 are the areas reserved for placing the debug monitor program, so user

programs cannot be allocated in these spaces.

Figure 20-6. Memory Spaces Where Debug Monitor Programs Are Allocated

Internal ROM space

304 bytes

Internal RAM space

Internal RAM

end address

Internal ROM

end address

Stack area for debugging

(5 bytes)

0x7EH

0x18H

for software break (2 bytes)

INTP3 interrupt vector (2 bytes)

• Securement of serial interface for communication

The register settings, concerning the INTP3 pin used for communication between QB-MINI2 and the target

device, performed by the debug monitor program must not be changed.

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CHAPTER 21 INSTRUCTION SET OVERVIEW

This chapter lists the instruction set of the 78K0S/KB1+. For details of the operation and machine language

(instruction code) of each instruction, refer to 78K/0S Series Instructions User’s Manual (U11047E).

21.1 Operation

21.1.1 Operand identifiers and description methods

Operands are described in “Operand” column of each instruction in accordance with the description method of the

instruction operand identifier (refer to the assembler specifications for details). When there are two or more

description methods, select one of them. Uppercase letters and the symbols #, !, $, and [ ] are key words and are

described as they are. Each symbol has the following meaning.

• #:

• !:

Immediate data specification

Absolute address specification

Relative address specification

• $:

• [ ]: Indirect address specification

In the case of immediate data, describe an appropriate numeric value or a label. When using a label, be sure to

describe the #, !, $ and [ ] symbols.

For operand register identifiers, r and rp, either function names (X, A, C, etc.) or absolute names (names in

parentheses in the table below, R0, R1, R2, etc.) can be used for description.

Table 21-1. Operand Identifiers and Description Methods

Identifier

Description Method

r

X (R0), A (R1), C (R2), B (R3), E (R4), D (R5), L (R6), H (R7)

AX (RP0), BC (RP1), DE (RP2), HL (RP3)

Special function register symbol

rp

sfr

saddr

FE20H to FF1FH Immediate data or labels

saddrp

FE20H to FF1FH Immediate data or labels (even addresses only)

addr16

addr5

0000H to FFFFH Immediate data or labels (only even addresses for 16-bit data transfer instructions)

0040H to 007FH Immediate data or labels (even addresses only)

word

byte

bit

16-bit immediate data or label

8-bit immediate data or label

3-bit immediate data or label

Remark For symbols of special function registers, see Table 3-3 Special Function Registers.

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21.1.2 Description of “Operation” column

A:

A register; 8-bit accumulator

X:

X register

B:

B register

C:

C register

D:

D register

E:

E register

H:

H register

L:

L register

AX:

BC:

DE:

HL:

PC:

SP:

PSW:

CY:

AC:

Z:

AX register pair; 16-bit accumulator

BC register pair

DE register pair

HL register pair

Program counter

Stack pointer

Program status word

Carry flag

Auxiliary carry flag

Zero flag

IE:

( ):

×^H, ×L:

∧:

Interrupt request enable flag

Memory contents indicated by address or register contents in parentheses

Higher 8 bits and lower 8 bits of 16-bit register

Logical product (AND)

∨:

Logical sum (OR)

∨:

⎯

Exclusive logical sum (exclusive OR)

Inverted data

:

addr16: 16-bit immediate data or label

jdisp8: Signed 8-bit data (displacement value)

21.1.3 Description of “Flag” column

(Blank): Unchanged

0:

1:

×:

R:

Cleared to 0

Set to 1

Set/cleared according to the result

Previously saved value is stored

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CHAPTER 21 INSTRUCTION SET OVERVIEW

21.2 Operation List

Mnemonic

Operand

Bytes Clocks

Operation

Flag

Z

AC CY

MOV

r, #byte

3

2

3

2

1

2

1

2

1

2

6

4

8

6

4

6

4

6

8

r ← byte

saddr, #byte

sfr, #byte

A, r

(saddr) ← byte

sfr ← byte

A ← r

Note 1

r, A

r ← A

A, saddr

saddr, A

A, sfr

A ← (saddr)

(saddr) ← A

A ← sfr

sfr, A

sfr ← A

A, !addr16

!addr16, A

PSW, #byte

A, PSW

PSW, A

A, [DE]

A ← (addr16)

(addr16) ← A

PSW ← byte

A ← PSW

PSW ← A

A ← (DE)

(DE) ← A

A ← (HL)

×

[DE], A

A, [HL]

[HL], A

(HL) ← A

A, [HL + byte]

[HL + byte], A

A, X

A ← (HL + byte)

(HL + byte) ← A

A ↔ X

XCH

Note 2

A, r

A ↔ r

A, saddr

A, sfr

A ↔ (saddr)

A ↔ sfr

A, [DE]

A ↔ (DE)

A ↔ (HL)

A, [HL]

A, [HL, byte]

A ↔ (HL + byte)

Notes1. Except r = A.

2. Except r = A, X.

Remark One instruction clock cycle is one CPU clock cycle (f^CPU) selected by the processor clock control

register (PCC).

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Mnemonic

MOVW

Operand

Bytes Clocks

Operation

Flag

Z

AC CY

rp, #word

3

2

1

2

3

2

3

1

2

3

2

3

1

2

3

2

3

1

2

6

8

4

8

4

6

4

8

6

4

6

4

8

6

4

6

4

8

6

rp ← word

AX, saddrp

saddrp, AX

AX, rp

AX ← (saddrp)

(saddrp) ← AX

Note

AX ← rp

rp, AX

rp ← AX

XCHW

ADD

AX, rp

AX ↔ rp

A, #byte

saddr, #byte

A, r

A, CY ← A + byte

×

(saddr), CY ← (saddr) + byte

A, CY ← A + r

A, saddr

A, !addr16

A, [HL]

A, CY ← A + (saddr)

A, CY ← A + (addr16)

A, CY ← A + (HL)

A, [HL + byte]

A, #byte

saddr, #byte

A, r

A, CY ← A + (HL + byte)

A, CY ← A + byte + CY

(saddr), CY ← (saddr) + byte + CY

A, CY ← A + r + CY

A, CY ← A + (saddr) + CY

A, CY ← A + (addr16) + CY

A, CY ← A + (HL) + CY

A, CY ← A + (HL + byte) + CY

A, CY ← A − byte

ADDC

A, saddr

A, !addr16

A, [HL]

A, [HL + byte]

A, #byte

saddr, #byte

A, r

SUB

(saddr), CY ← (saddr) − byte

A, CY ← A − r

A, saddr

A, !addr16

A, [HL]

A, CY ← A − (saddr)

A, CY ← A − (addr16)

A, CY ← A − (HL)

A, [HL + byte]

A, CY ← A − (HL + byte)

Note Only when rp = BC, DE, or HL.

Remark One instruction clock cycle is one CPU clock cycle (f^CPU) selected by the processor clock control

register (PCC).

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Mnemonic

SUBC

Operand

Bytes Clocks

Operation

Flag

Z

×

AC CY

A, #byte

2

3

2

3

1

2

3

2

3

1

2

3

2

3

1

2

3

2

3

1

2

4

6

4

8

6

4

6

4

8

6

4

6

4

8

6

4

6

4

8

6

A, CY ← A − byte − CY

(saddr), CY ← (saddr) − byte − CY

A, CY ← A − r − CY

A, CY ← A − (saddr) − CY

A, CY ← A − (addr16) − CY

A, CY ← A − (HL) − CY

A, CY ← A − (HL + byte) − CY

A ← A ∧ byte

×

saddr, #byte

A, r

A, saddr

A, !addr16

A, [HL]

A, [HL + byte]

A, #byte

AND

saddr, #byte

A, r

(saddr) ← (saddr) ∧ byte

A ← A ∧ r

A, saddr

A, !addr16

A, [HL]

A ← A ∧ (saddr)

A ← A ∧ (addr16)

A ← A ∧ (HL)

A, [HL + byte]

A, #byte

A ← A ∧ (HL + byte)

A ← A ∨ byte

OR

saddr, #byte

A, r

(saddr) ← (saddr) ∨ byte

A ← A ∨ r

A, saddr

A, !addr16

A, [HL]

A ← A ∨ (saddr)

A ← A ∨ (addr16)

A ← A ∨ (HL)

A, [HL + byte]

A, #byte

A ← A ∨ (HL + byte)

A ← A ∨ byte

XOR

saddr, #byte

A, r

(saddr) ← (saddr) ∨ byte

A ← A ∨ r

A, saddr

A, !addr16

A, [HL]

A ← A ∨ (saddr)

A ← A ∨ (addr16)

A ← A ∨ (HL)

A, [HL + byte]

A ← A ∨ (HL + byte)

Remark One instruction clock cycle is one CPU clock cycle (f^CPU) selected by the processor clock control

register (PCC).

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CHAPTER 21 INSTRUCTION SET OVERVIEW

Mnemonic

CMP

Operand

Bytes Clocks

Operation

Flag

Z

×

AC CY

A, #byte

2

3

2

3

1

2

3

2

1

3

2

3

2

3

2

3

2

1

4

6

4

8

6

4

2

6

4

6

10

6

4

6

10

2

A − byte

×

saddr, #byte

A, r

(saddr) − byte

A − r

A, saddr

A, !addr16

A, [HL]

A, [HL + byte]

AX, #word

r

A − (saddr)

A − (addr16)

A − (HL)

A − (HL + byte)

AX, CY ← AX + word

AX, CY ← AX − word

AX − word

ADDW

SUBW

CMPW

INC

r ← r + 1

saddr

r

(saddr) ← (saddr) + 1

r ← r − 1

DEC

saddr

rp

(saddr) ← (saddr) − 1

rp ← rp + 1

INCW

DECW

ROR

rp

rp ← rp − 1

A, 1

(CY, A7 ← A0, Am−1 ← Am) × 1

(CY, A0 ← A7, Am+1 ← Am) × 1

(CY ← A0, A7 ← CY, Am−1 ← Am) × 1

(CY ← A7, A0 ← CY, Am+1 ← Am) × 1

(saddr.bit) ← 1

sfr.bit ← 1

×

ROL

A, 1

RORC

ROLC

SET1

A, 1

saddr.bit

sfr.bit

A.bit

A.bit ← 1

PSW.bit

[HL].bit

saddr.bit

sfr.bit

PSW.bit ← 1

×

(HL).bit ← 1

CLR1

(saddr.bit) ← 0

sfr.bit ← 0

A.bit

A.bit ← 0

PSW.bit

[HL].bit

CY

PSW.bit ← 0

×

(HL).bit ← 0

SET1

CLR1

NOT1

CY ← 1

1

0

×

CY

CY ← 0

CY

CY ← CY

Remark One instruction clock cycle is one CPU clock cycle (f^CPU) selected by the processor clock control

register (PCC).

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Mnemonic

Operand

Bytes Clocks

Operation

Flag

Z

AC CY

CALL

!addr16

[addr5]

3

1

6

8

(SP − 1) ← (PC + 3)H, (SP − 2) ← (PC + 3)L,

PC ← addr16, SP ← SP − 2

CALLT

(SP − 1) ← (PC + 1)H, (SP − 2) ← (PC + 1)L,

PC^H← (00000000, addr5 + 1),

PC^L← (00000000, addr5), SP ← SP − 2

RET

1

6

8

PCH ← (SP + 1), PCL ← (SP), SP ← SP + 2

RETI

PCH ← (SP + 1), PCL ← (SP), PSW ← (SP + 2),

SP ← SP + 3

R

PUSH

POP

PSW

1

2

3

2

1

2

4

3

4

3

4

2

3

2

4

(SP − 1) ← PSW, SP ← SP − 1

(SP − 1) ← rp^H, (SP − 2) ← rpL, SP ← SP − 2

PSW ← (SP), SP ← SP + 1

rp

PSW

4

rp

6

rp^H← (SP + 1), rpL ← (SP), SP ← SP + 2

SP ← AX

MOVW

BR

SP, AX

AX, SP

!addr16

$addr16

AX

8

6

AX ← SP

6

PC ← addr16

6

PC ← PC + 2 + jdisp8

6

PC^H← A, PCL ← X

BC

$saddr16

6

PC ← PC + 2 + jdisp8 if CY = 1

PC ← PC + 2 + jdisp8 if CY = 0

PC ← PC + 2 + jdisp8 if Z = 1

PC ← PC + 2 + jdisp8 if Z = 0

PC ← PC + 4 + jdisp8 if (saddr.bit) = 1

PC ← PC + 4 + jdisp8 if sfr.bit = 1

PC ← PC + 3 + jdisp8 if A.bit = 1

PC ← PC + 4 + jdisp8 if PSW.bit = 1

PC ← PC + 4 + jdisp8 if (saddr.bit) = 0

PC ← PC + 4 + jdisp8 if sfr.bit = 0

PC ← PC + 3 + jdisp8 if A.bit = 0

PC ← PC + 4 + jdisp8 if PSW.bit = 0

B ← B − 1, then PC ← PC + 2 + jdisp8 if B ≠ 0

C ← C − 1, then PC ← PC + 2 + jdisp8 if C ≠ 0

BNC

BZ

6

BNZ

BT

6

saddr.bit, $addr16

sfr.bit, $addr16

A.bit, $addr16

PSW.bit, $addr16

saddr.bit, $addr16

sfr.bit, $addr16

A.bit, $addr16

PSW.bit, $addr16

B, $addr16

10

8

10

8

BF

10

6

DBNZ

C, $addr16

6

saddr, $addr16

8

(saddr) ← (saddr) − 1, then

PC ← PC + 3 + jdisp8 if (saddr) ≠ 0

NOP

EI

1

3

1

2

6

2

No Operation

IE ← 1 (Enable Interrupt)

IE ← 0 (Disable Interrupt)

Set HALT Mode

DI

HALT

STOP

Set STOP Mode

Remark One instruction clock cycle is one CPU clock cycle (f^CPU) selected by the processor clock control

register (PCC).

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21.3 Instructions Listed by Addressing Type

(1) 8-bit instructions

MOV, XCH, ADD, ADDC, SUB, SUBC, AND, OR, XOR, CMP, INC, DEC, ROR, ROL, RORC, ROLC, PUSH,

POP, DBNZ

2nd Operand

1st Operand

#byte

A

r

sfr

saddr !addr16 PSW

[DE]

[HL]

$addr16

1

None

[HL + byte]

A

ADD

ADDC

SUB

SUBC

AND

OR

MOV^NoteMOV

MOV

XCH

ADD

ADDC

SUB

SUBC

AND

OR

MOV

XCH

MOV

XCH

ADD

ADDC

SUB

SUBC

AND

OR

MOV

XCH

ADD

ADDC

SUB

SUBC

AND

OR

ROR

XCH^Note

XCH

ROL

ADD

ADDC

SUB

SUBC

AND

OR

RORC

ROLC

ADDC

SUB

SUBC

AND

XOR

CMP

OR

XOR

CMP

XOR

CMP

XOR

CMP

XOR

CMP

XOR

CMP

r

MOV

INC

DEC

B, C

sfr

DBNZ

MOV

saddr

MOV

ADD

ADDC

SUB

SUBC

AND

OR

INC

DEC

XOR

CMP

!addr16

PSW

MOV

PUSH

POP

[DE]

MOV

[HL]

[HL + byte]

Note Except r = A.

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CHAPTER 21 INSTRUCTION SET OVERVIEW

(2) 16-bit instructions

MOVW, XCHW, ADDW, SUBW, CMPW, PUSH, POP, INCW, DECW

2nd Operand

1st Operand

#word

AX

rp^Note

saddrp

SP

None

AX

ADDW SUBW

CMPW

MOVW

XCHW

MOVW

rp

MOVW

MOVW^Note

INCW

DECW

PUSH

POP

saddrp

sp

MOVW

Note Only when rp = BC, DE, or HL.

(3) Bit manipulation instructions

SET1, CLR1, NOT1, BT, BF

2nd Operand

1st Operand

$addr16

None

A.bit

BT

BF

SET1

CLR1

sfr.bit

BT

BF

SET1

CLR1

saddr.bit

PSW.bit

[HL].bit

CY

BT

BF

SET1

CLR1

BT

BF

SET1

CLR1

SET1

CLR1

SET1

CLR1

NOT1

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CHAPTER 21 INSTRUCTION SET OVERVIEW

(4) Call instructions/branch instructions

CALL, CALLT, BR, BC, BNC, BZ, BNZ, DBNZ

2nd Operand

1st Operand

AX

!addr16

[addr5]

$addr16

Basic instructions

BR

CALL

BR

CALLT

BR

BC

BNC

BZ

BNZ

Compound instructions

DBNZ

(5) Other instructions

RET, RETI, NOP, EI, DI, HALT, STOP

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CHAPTER 22 ELECTRICAL SPECIFICATIONS (Standard product, (A) grade product)

Absolute Maximum Ratings (T^A= 25°C)

Parameter

Supply voltage

Symbol

Conditions

Ratings

−0.3 to +6.5

Unit

V

VDD

VSS

−0.3 to +0.3

V

AVREF

AV^SS

VI1

−0.3 to VDD + 0.3^Note

V

−0.3 to +0.3

−0.3 to V^DD+ 0.3^Note

V

Input voltage

P00 to P03, P30 to P34, P40 to P47, P120 to

P123

V

V^I2

P20 to P23

−0.3 to AV^REF+ 0.3^Note

and −0.3 to V^DD+ 0.3^Note

V

Output voltage

VO

−0.3 to VDD + 0.3^Note

V

Analog input voltage

VAN

−0.3 to AV^REF+ 0.3^Note

and −0.3 to V^DD+ 0.3^Note

Output current, high

Output current, low

IOH

IOL

Per pin

−10.0

−44.0

20.0

mA

°C

Total of pins other than P20 to P23

Total of P20 to P23

Per pin

Total of pins other than P20 to P23

Total of P20 to P23

44.0

Operating ambient

temperature

T^A

In normal operation mode

During flash memory programming

Flash memory blank status

Flash memory programming already performed

−40 to +85

Storage temperature

Tstg

−65 to +150

−40 to +125

°C

Note Must be 6.5 V or lower

Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any

parameter. That is, the absolute maximum ratings are rated values at which the product is on the

verge of suffering physical damage, and therefore the product must be used under conditions that

ensure that the absolute maximum ratings are not exceeded.

Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins.

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CHAPTER 22 ELECTRICAL SPECIFICATIONS (Standard product, (A) grade product)

Standard product, (A) grade product TA = −40 to +85°C

X1 Oscillator Characteristics (TA = −40 to +85°C, VDD = 2.0 to 5.5 V^{Note 1}, VSS = 0 V)

Resonator Recommended Circuit Parameter Conditions

MIN.

2.0

TYP. MAX.

10.0

Unit

Ceramic

Oscillation

frequency (f^X)^{Note 2}

MHz

VSS X1

X2

resonator

C1

C2

Crystal

Oscillation

frequency (f^X)^{Note 2}

2.0

10.0

MHz

V

SS X1

C1

X2

resonator

External

clock

X1 input

2.7 V ≤ VDD ≤ 5.5 V

2.0

10.0

5.0

MHz

X1

frequency (f^X)^{Note 2}

2.0 V ≤ V^DD< 2.7 V

2.7 V ≤ VDD ≤ 5.5 V

X1 input high-

/low-level width

(t^XH, tXL)

0.045

0.25

μs

2.0 V ≤ V^DD< 2.7 V

0.09

0.25

Notes 1. Use this product in a voltage range of 2.2 to 5.5 V because the detection voltage (V^POC) of the power-on-

clear (POC) circuit is 2.1 V 0.1 V.

2. Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time.

Caution When using the X1 oscillator, wire as follows in the area enclosed by the broken lines in the above

figures to avoid an adverse effect from wiring capacitance.

• Keep the wiring length as short as possible.

• Do not cross the wiring with the other signal lines.

• Do not route the wiring near a signal line through which a high fluctuating current flows.

• Always make the ground point of the oscillator capacitor the same potential as V^SS.

• Do not ground the capacitor to a ground pattern through which a high current flows.

• Do not fetch signals from the oscillator.

Remark For the resonator selection and oscillator constant, users are required to either evaluate the oscillation

themselves or apply to the resonator manufacturer for evaluation.

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CHAPTER 22 ELECTRICAL SPECIFICATIONS (Standard product, (A) grade product)

Standard product, (A) grade product TA = −40 to +85°C

High-Speed Internal Oscillator Characteristics (TA = −40 to +85°C, VDD = 2.0 to 5.5 V^{Note 1}, VSS = 0 V)

Resonator

Parameter

Conditions

2.7 V ≤ V^DD≤ 5.5 V TA = −10 to +80°C

T^A= −40 to +85°C

MIN.

TYP. MAX.

Unit

%

High-speed internal Oscillation frequency (fX = 8

3

5

oscillator

MHz^{Note 2}) deviation

%

Oscillation frequency (f^X)^{Note 2}

2.0 V ≤ VDD < 2.7 V

5.5

MHz

Notes 1. Use this product in a voltage range of 2.2 to 5.5 V because the detection voltage (V^POC) of the power-on-

clear (POC) circuit is 2.1 V 0.1 V.

2. Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time.

Low-Speed Internal Oscillator Characteristics (TA = −40 to +85°C, VDD = 2.0 to 5.5 V^Note, VSS = 0 V)

Resonator

Parameter

Conditions

MIN.

120

TYP. MAX.

240 480

Unit

kHz

Low-speed internal oscillator

Oscillation frequency (fRL)

Note Use this product in a voltage range of 2.2 to 5.5 V because the detection voltage (V^POC) of the power-on-clear

(POC) circuit is 2.1 V 0.1 V.

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CHAPTER 22 ELECTRICAL SPECIFICATIONS (Standard product, (A) grade product)

Standard product, (A) grade product TA = −40 to +85°C

DC Characteristics (TA = −40 to +85°C, VDD = 2.0 to 5.5 V^Note, VSS = 0 V) (1/2)

Parameter

Symbol

Conditions

MIN.

TYP.

MAX.

–5

Unit

mA

V

Output current, high

IOH1

Pins other than Per pin 2.0 V ≤ VDD ≤ 5.5 V

P20 to P23

Total

4.0 V ≤ VDD ≤ 5.5 V

2.0 V ≤ V^DD< 4.0 V

–25

–15

–5

I^OH2

P20 to P23

Per pin 2.0 V ≤ AVREF ≤ 5.5 V

Total 2.0 V ≤ AV^REF≤ 5.5 V

–15

10

Output current, low

IOL1

Pins other than Per pin 2.0 V ≤ VDD ≤ 5.5 V

P20 to P23

Total

4.0 V ≤ VDD ≤ 5.5 V

2.0 V ≤ V^DD< 4.0 V

30

15

I^OL2

P20 to P23

Per pin 2.0 V ≤ AVREF ≤ 5.5 V

10

Total

4.0 V ≤ AVREF ≤ 5.5 V

2.0 V ≤ AV^REF< 4.0 V

30

15

Input voltage, high

Input voltage, low

Output voltage, high

VIH1

VIH2

V^IH3

VIL1

VIL2

V^IL3

VOH1

P00 to P03, P30 to P34, P40 to P47, P120, P123

0.8VDD

VDD

P20 to P23

0.7AVREF

AVREF

VDD

V

P121, P122

0.8VDD

V

P00 to P03, P30 to P34, P40 to P47, P120, P123

0

0.2VDD

0.3AVREF

0.2VDD

V

P20 to P23

P121, P122

0

V

Total of pins other than

P20 to P23

4.0 V ≤ V^DD≤ 5.5 V

I^OH1= –5 mA

V^DD− 1.0

V

I^OH1= –15 mA

I^OH1= –100 μA

2.0 V ≤ VDD < 4.0 V

VDD – 0.5

V

V^OH2

VOL1

V^OL2

Total of pins P20 to P23 4.0 V ≤ AV^REF≤ 5.5 V AV^REF– 1.0

I^OH2= –10 mA

I^OH2= –5 mA

2.0 V ≤ AV^REF< 4.0 V

I^OH2= –100 μA

AV^REF– 0.5

V

Output voltage, low

Total of pins other than

P20 to P23

4.0 V ≤ V^DD≤ 5.5 V

I^OL1= 10 mA

1.3

I^OL1= 30 mA

I^OL1= 400 μA

2.0 V ≤ VDD < 4.0 V

0.4

1.3

V

Total of pins P20 to P23 4.0 V ≤ AV^REF≤ 5.5 V

I^OL2= 30 mA

I^OL2= 400 μA

VI = VDD

I^OL2= 10 mA

2.0 V ≤ AVREF < 4.0 V

Pins other than X1

Pins other than X2

0.4

1

V

Input leakage current, high ILIH

Input leakage current, low ILIL

Output leakage current, high ILOH

Output leakage current, low ILOL

μA

kΩ

VI = 0 V

–1

1

VO = VDD

VO = 0 V

–1

100

Pull-up resistance

RPU

RPD

VI = 0 V

10

30

Pull-down resistance

P121, P122, reset status

Note Use this product in a voltage range of 2.2 to 5.5 V because the detection voltage (V^POC) of the power-on-clear

(POC) circuit is 2.1 V 0.1 V.

Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins.

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CHAPTER 22 ELECTRICAL SPECIFICATIONS (Standard product, (A) grade product)

Standard product, (A) grade product TA = −40 to +85°C

DC Characteristics (TA = −40 to +85°C, VDD = 2.0 to 5.5 V^{Note 1}, VSS = 0 V) (2/2)

Parameter Symbol

Conditions

MIN. TYP. MAX. Unit

6.1 12.2 mA

7.6 15.2

Note 3

IDD1

Supply

current^{Note 2}

Crystal/ceramic

fX = 10 MHz

V^DD= 5.0 V 10%^{Note 4}

When A/D converter is stopped

When A/D converter is operating^{Note 8}

When A/D converter is stopped

When A/D converter is operating^{Note 8}

When A/D converter is stopped

When A/D converter is operating^{Note 8}

When peripheral functions are stopped

When peripheral functions are operating

When peripheral functions are stopped

When peripheral functions are operating

When peripheral functions are stopped

When peripheral functions are operating

When A/D converter is stopped

When A/D converter is operating^{Note 8}

oscillation, external

clock input oscillation

operating mode^{Note 6}

fX = 6 MHz

5.5 11.0 mA

14.0

V^DD= 5.0 V 10%^{Note 4}

f^X= 5 MHz

3.0

4.5

1.7

6.0

9.0

3.8

6.7

3.0

6.0

1

mA

V^DD= 3.0 V 10%^{Note 5}

IDD2

Crystal/ceramic

oscillation, external

clock input HALT

mode^{Note 6}

fX = 10 MHz

V^DD= 5.0 V 10%^{Note 4}

fX = 6 MHz

1.3

V^DD= 5.0 V 10%^{Note 4}

f^X= 5 MHz

0.48

V^DD= 3.0 V 10%^{Note 5}

2.1

Note 3

IDD3

IDD4

I^DD5

High-speed internal

oscillation operating

mode^{Note 7}

f^X= 8 MHz

5.0 10.0 mA

6.5 13.0

V^DD= 5.0 V 10%^{Note 4}

High-speed internal

oscillation HALT

mode^{Note 7}

f^X= 8 MHz

When peripheral functions are stopped

When peripheral functions are operating

1.4

3.2

5.9

mA

V^DD= 5.0 V 10%^{Note 4}

STOP mode

VDD = 5.0 V 10%

V^DD= 3.0 V 10%

When low-speed internal

oscillation is stopped

3.5 20.0 μA

17.5 32.0

When low-speed internal

oscillation is operating

When low-speed internal

oscillation is stopped

3.5 15.5 μA

11.0 26.0

When low-speed internal

oscillation is operating

Notes 1. Use this product in a voltage range of 2.2 to 5.5 V because the detection voltage (VPOC) of the power-on-

clear (POC) circuit is 2.1 V 0.1 V.

2. Total current flowing through the internal power supply (V^DD). Peripheral operation current is included

(however, the current that flows through the pull-up resistors of ports is not included).

3. Peripheral operation current is included.

4. When the processor clock control register (PCC) is set to 00H.

5. When the processor clock control register (PCC) is set to 02H.

6. When crystal/ceramic oscillation clock, external clock input is selected as the system clock source using

the option byte.

7. When the high-speed internal oscillation clock is selected as the system clock source using the option

byte.

8. The current that flows through the AV^REFpin is included.

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CHAPTER 22 ELECTRICAL SPECIFICATIONS (Standard product, (A) grade product)

Standard product, (A) grade product TA = −40 to +85°C

AC Characteristics

(1) Basic operation (T^A= −40 to +85°C, VDD = 2.0 to 5.5 V^{Note 1}, VSS = 0 V)

Parameter

Symbol

T^CY

Conditions

Crystal/ceramic oscillation

MIN.

0.2

TYP.

MAX.

16

Unit

μs

Cycle time (minimum

4.0 V ≤ VDD ≤ 5.5 V

3.0 V ≤ VDD < 4.0 V

2.7 V ≤ VDD < 3.0 V

2.0 V ≤ V^DD< 2.7 V

4.0 V ≤ VDD ≤ 5.5 V

2.7 V ≤ VDD < 4.0 V

2.0 V ≤ V^DD< 2.7 V

instruction execution time)

clock, external clock input

0.33

0.4

16

1

16

High-speed internal

oscillation clock

0.23

0.47

0.95

4.22

TI000 input high-level width, t^TIH,

4.0 V ≤ VDD ≤ 5.5 V

2.0 V ≤ V^DD< 4.0 V

2/fsam+

0.1^{Note 2}

low-level width

t^TIL

2/fsam+

0.2^{Note 2}

μs

Interrupt input high-level

width, low-level width

t^INTH,

t^INTL

t^RSL

1

RESET input low-level

width

2

μs

Notes 1. Use this product in a voltage range of 2.2 to 5.5 V because the detection voltage (V^POC) of the power-on-

clear (POC) circuit is 2.1 V 0.1 V.

2. Selection of fsam = f^XP, fXP/4, or fXP/256 is possible using bits 0 and 1 (PRM000, PRM001) of prescaler

mode register 00 (PRM00). Note that when selecting the valid edge of the TI000 pin as the count clock,

fsam = f^XP.

CPU Clock Frequency, Peripheral Clock Frequency

Parameter

Conditions

CPU Clock (fCPU)

125 kHz ≤ fCPU ≤ 10 MHz

125 kHz ≤ fCPU ≤ 6 MHz

125 kHz ≤ fCPU ≤ 5 MHz

125 kHz ≤ fCPU ≤ 2 MHz

Peripheral Clock (fXP)

500 kHz ≤ fXP ≤ 10 MHz

Ceramic resonator,

crystal resonator,

external clock

4.0 to 5.5 V

3.0 to 4.0 V

2.7 to 3.0 V

2.0 to 2.7 V^Note

4.0 to 5.5 V

2.7 to 4.0 V

2.0 to 2.7 V^Note

500 kHz ≤ fXP ≤ 5 MHz

High-speed internal

oscillator

500 kHz (TYP.) ≤ fCPU ≤ 8 MHz (TYP.) 2 MHz (TYP.) ≤ fXP ≤ 8 MHz (TYP.)

500 kHz (TYP.) ≤ fCPU ≤ 4 MHz (TYP.)

500 kHz (TYP.) ≤ fCPU ≤ 2 MHz (TYP.) 2 MHz (TYP.) ≤ fXP ≤ 4 MHz (TYP.)

Note Use this product in a voltage range of 2.2 to 5.5 V because the detection voltage (VPOC) of the power-on-clear

(POC) circuit is 2.1 V 0.1 V.

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CHAPTER 22 ELECTRICAL SPECIFICATIONS (Standard product, (A) grade product)

Standard product, (A) grade product TA = −40 to +85°C

TCY vs. VDD (Crystal/Ceramic Oscillation Clock, External Clock Input)

60

16

10

μ

Guaranteed

operation range

1.0

0.4

0.33

0.1

1

2

3

4

5

6

2.7

Supply voltage VDD [V]

5.5

T^CYvs. VDD (High-speed internal oscillator Clock)

60

10

μ

4.22

Guaranteed

operation range

1.0

0.95

0.47

0.23

0.1

1

2

3

4

5

6

2.7

Supply voltage VDD [V]

5.5

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CHAPTER 22 ELECTRICAL SPECIFICATIONS (Standard product, (A) grade product)

Standard product, (A) grade product TA = −40 to +85°C

(2) Serial interface (TA = −40 to +85°C, VDD = 2.0 to 5.5 V^Note, VSS = 0 V)

UART mode (UART6, dedicated baud rate generator output)

Parameter

Transfer rate

Symbol

Conditions

MIN.

TYP.

MAX.

312.5

Unit

kbps

Note Use this product in a voltage range of 2.2 to 5.5 V because the detection voltage (VPOC) of the power-on-clear

(POC) circuit is 2.1 V 0.1 V.

AC Timing Test Points (Excluding X1 Input)

0.8VDD

0.2VDD

0.8VDD

0.2VDD

Test points

Clock Timing

1/fX

t

XL

tXH

X1 input

TI000 Timing

t

TIL

t

TIH

TI000

Interrupt Input Timing

tINTL

tINTH

INTP0 to INTP3

RESET Input Timing

tRSL

RESET

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User’s Manual U17446EJ5V0UD

CHAPTER 22 ELECTRICAL SPECIFICATIONS (Standard product, (A) grade product)

Standard product, (A) grade product TA = −40 to +85°C

A/D Converter Characteristics (TA = −40 to +85°C, 2.7 V ≤ AVREF ≤ VDD ≤ 5.5 V, VSS = AVSS = 0 V)

Parameter

Symbol

Conditions

MIN.

10

TYP.

10

MAX.

10

Unit

bit

Resolution

Overall error^{Notes 1, 2}

AINL

4.0 V ≤ AVREF ≤ 5.5 V

0.2

0.3

0.4

%FSR

μs

2.7 V ≤ AV^REF< 4.0 V

4.5 V ≤ AVREF ≤ 5.5 V

4.0 V ≤ AVREF < 4.5 V

2.85 V ≤ AVREF < 4.0 V

2.7 V ≤ AV^REF< 2.85 V

4.0 V ≤ AVREF ≤ 5.5 V

2.7 V ≤ AV^REF< 4.0 V

4.0 V ≤ AVREF ≤ 5.5 V

2.7 V ≤ AV^REF< 4.0 V

4.0 V ≤ AVREF ≤ 5.5 V

2.7 V ≤ AV^REF< 4.0 V

4.0 V ≤ AVREF ≤ 5.5 V

2.7 V ≤ AV^REF< 4.0 V

0.6

Conversion time

tCONV

3.0

4.8

100

0.4

μs

6.0

μs

14.0

μs

Zero-scale error^{Notes 1, 2}

Ezs

Efs

%FSR

LSB

V

0.6

Full-scale error^{Notes 1, 2}

0.4

0.6

Integral non-linearity error^{Note 1}

Differential non-linearity error^{Note 1}

Analog input voltage

ILE

DLE

VAIN

2.5

4.5

1.5

2.0

VSS

AVREF

Notes 1. Excludes quantization error ( 1/2 LSB).

2. This value is indicated as a ratio (%FSR) to the full-scale value.

Caution The conversion accuracy may be degraded if the analog input pin is used as an alternate I/O port or

if a port is changed during A/D conversion.

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CHAPTER 22 ELECTRICAL SPECIFICATIONS (Standard product, (A) grade product)

Standard product, (A) grade product TA = −40 to +85°C

POC Circuit Characteristics (TA = −40 to +85°C)

Parameter

Detection voltage

Symbol

V^POC

Conditions

MIN.

2.0

TYP.

2.1

MAX.

2.2

Unit

V

Power supply boot time

tPTH

VDD: 0 V → 2.1 V

1.5

μs

Response delay time 1^{Note 1}

tPTHD

When power supply rises, after reaching

detection voltage (MAX.)

3.0

1.0

ms

Response delay time 2^{Note 2}

Minimum pulse width

tPD

ms

When power supply falls

tPW

0.2

Notes 1. Time required from voltage detection to internal reset release.

2. Time required from voltage detection to internal reset signal generation.

POC Circuit Timing

Supply voltage

(V^DD

)

Detection voltage (MAX.)

Detection voltage (TYP.)

Detection voltage (MIN.)

t

PW

t

PTH

tPTHD

t

PD

Time

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User’s Manual U17446EJ5V0UD

CHAPTER 22 ELECTRICAL SPECIFICATIONS (Standard product, (A) grade product)

Standard product, (A) grade product TA = −40 to +85°C

LVI Circuit Characteristics (TA = −40 to +85°C)

Parameter

Detection voltage

Symbol

VLVI0

VLVI1

VLVI2

VLVI3

VLVI4

VLVI5

VLVI6

VLVI7

VLVI8

V^LVI9

tLD

Conditions

MIN.

4.1

TYP.

4.3

MAX.

4.5

Unit

V

3.9

4.1

4.3

V

3.7

3.9

4.1

V

3.5

3.7

3.9

V

3.3

3.5

3.7

V

3.15

2.95

2.7

3.3

3.45

3.25

3.0

V

3.1

V

2.85

2.6

V

2.5

2.7

V

2.25

2.35

0.2

2.45

2.0

V

Response time^{Note 1}

ms

Minimum pulse width

tLW

0.2

Operation stabilization wait time^{Note 2}

tLWAIT

0.1

0.2

Notes 1. Time required from voltage detection to interrupt output or internal reset signal generation.

2. Time required from setting LVION to 1 to operation stabilization.

Remarks 1. V^LVI0> VLVI1 > VLVI2 > VLVI3 > VLVI4 > VLVI5 > VLVI6 > VLVI7 > VLVI8 > VLVI9

2. V^POC< VLVIm (m = 0 to 9)

LVI Circuit Timing

Supply voltage

(V^DD

)

Detection voltage (MAX.)

Detection voltage (TYP.)

Detection voltage (MIN.)

t

LW

t

LWAIT

t

LD

LVION

1

Time

Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics (T^A= −40 to +85°C)

Parameter

Symbol

VDDDR

tSREL

Conditions

MIN.

2.0

0

TYP.

MAX.

5.5

Unit

V

Data retention supply voltage

Release signal set time

μs

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CHAPTER 22 ELECTRICAL SPECIFICATIONS (Standard product, (A) grade product)

Standard product, (A) grade product TA = −40 to +85°C

Flash Memory Programming Characteristics (TA = –40 to +85°C, 2.7 V ≤ VDD ≤ 5.5 V, VSS = 0 V)

Parameter

Symbol

IDD

Conditions

MIN.

TYP.

MAX.

7.0

Unit

mA

Supply current

VDD = 5.5 V

Erasure count^{Note 1}

(per 1 block)

N^ERASE

TA = −40 to +85°C

1000

Times

Chip erase time

TCERASE

TA = −10 to +85°C,

N^ERASE≤ 100

4.5 V ≤ VDD ≤ 5.5 V

3.5 V ≤ VDD < 4.5 V

2.7 V ≤ V^DD< 3.5 V

4.5 V ≤ VDD ≤ 5.5 V

3.5 V ≤ VDD < 4.5 V

2.7 V ≤ V^DD< 3.5 V

4.5 V ≤ VDD ≤ 5.5 V

3.5 V ≤ VDD < 4.5 V

2.7 V ≤ V^DD< 3.5 V

4.5 V ≤ VDD ≤ 5.5 V

3.5 V ≤ VDD < 4.5 V

2.7 V ≤ V^DD< 3.5 V

4.5 V ≤ VDD ≤ 5.5 V

3.5 V ≤ VDD < 4.5 V

2.7 V ≤ V^DD< 3.5 V

4.5 V ≤ VDD ≤ 5.5 V

3.5 V ≤ VDD < 4.5 V

2.7 V ≤ V^DD< 3.5 V

4.5 V ≤ VDD ≤ 5.5 V

3.5 V ≤ VDD < 4.5 V

2.7 V ≤ V^DD< 3.5 V

4.5 V ≤ VDD ≤ 5.5 V

3.5 V ≤ VDD < 4.5 V

2.7 V ≤ V^DD< 3.5 V

0.8

1.0

1.2

4.8

5.2

6.1

1.6

1.8

2.0

9.1

10.1

12.3

0.4

0.5

0.6

2.6

2.8

2.3

0.9

1.0

1.1

4.9

5.4

6.6

150

6.8

27

s

TA = −10 to +85°C,

N^ERASE≤ 1000

s

TA = −40 to +85°C,

N^ERASE≤ 100

s

T^A= −40 to +85°C,

N^ERASE≤ 1000

s

Block erase time

TBERASE

TA = −10 to +85°C,

N^ERASE≤ 100

s

TA = −10 to +85°C,

N^ERASE≤ 1000

s

TA = −40 to +85°C,

N^ERASE≤ 100

s

T^A= −40 to +85°C,

N^ERASE≤ 1000

s

Byte write time

Internal verify

TWRITE

TVERIFY

TA = −40 to +85°C, NERASE ≤ 1000

Per 1 block

μs

ms

μs

Years

Per 1 byte

Blank check

TBLKCHK

Per 1 block

480

Retention years

TA = 85°C^{Note 2}, NERASE ≤ 1000

10

Note 1. Depending on the erasure count (N^ERASE), the erase time varies. Refer to the chip erase time and block

erase time parameters.

2. When the average temperature when operating and not operating is 85°C.

Remark When a product is first written after shipment, “erase → write” and “write only” are both taken as one rewrite.

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User’s Manual U17446EJ5V0UD

<R>

CHAPTER 23 ELECTRICAL SPECIFICATIONS ((A2) grade product)

Absolute Maximum Ratings (T^A= 25°C)

Parameter

Supply voltage

Symbol

Conditions

Ratings

−0.3 to +6.5

Unit

V

VDD

VSS

−0.3 to +0.3

V

AVREF

AV^SS

VI1

−0.3 to VDD + 0.3^{Note 1}

V

−0.3 to +0.3

−0.3 to V^DD+ 0.3^{Note 1}

V

Input voltage

P00 to P03, P30 to P34, P40 to P47, P120 to

P123

V

V^I2

P20 to P23

−0.3 to AV^REF+ 0.3^{Note 1}

and −0.3 to V^DD+ 0.3^{Note 1}

V

Output voltage

VO

−0.3 to VDD + 0.3^{Note 1}

V

Analog input voltage

VAN

−0.3 to AV^REF+ 0.3^{Note 1}

and −0.3 to V^DD+ 0.3^{Note 1}

Output current, high

Output current, low

Total loss

IOH

IOL

Per pin

−7.0

−30.0

mA

mW

°C

Total of pins other than P20 to P23

Total of P20 to P23

−30.0

Per pin

14.0

Total of pins other than P20 to P23

Total of P20 to P23

30.0

Note 2

PT

TA = −40 to +85°C

120

T^A= +85 to +125°C

110

Operating ambient

temperature

T^A

In normal operation mode

During flash memory programming

Flash memory blank status

Flash memory programming already performed

−40 to +125

−40 to +105

−65 to +150

−40 to +125

°C

Storage temperature

Tstg

°C

Note 1.

Must be 6.5 V or lower

Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any

parameter. That is, the absolute maximum ratings are rated values at which the product is on the

verge of suffering physical damage, and therefore the product must be used under conditions that

ensure that the absolute maximum ratings are not exceeded.

Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins.

(Note 2 is listed on the next page.)

356

User’s Manual U17446EJ5V0UD

CHAPTER 23 ELECTRICAL SPECIFICATIONS ((A2) grade product)

(A2) grade product TA = −40 to +125°C

Note 2.

This varies depending on the allowable total loss (see the figure below).

150

120

110

100

50

−40

0

+40

+80

+120

+125

Temperature [˚C]

+85

Use the following formula to perform design such that the sum of the power consumption of the device is

less than or equal to the total loss P^T(use at 80% or less of the rated value is recommended).

• Total power consumption = V^DD× {IDD − ∑IOH} + ∑{(VDD − VOH) × IOH} + ∑(VOL × IOL)

When guaranteeing the internal pull-up resistor, use the following formula to calculate its power

consumption, and add the result to the result above.

• Power consumption of internal pull-up resistor = Σ(V^DD/RPU × VDD)

357

User’s Manual U17446EJ5V0UD

CHAPTER 23 ELECTRICAL SPECIFICATIONS ((A2) grade product)

(A2) grade product TA = −40 to +125°C

X1 Oscillator Characteristics (TA = −40 to +125°C, VDD = 2.0 to 5.5 V^{Note 1}, VSS = 0 V)

Resonator Recommended Circuit Parameter Conditions

MIN.

2.0

TYP. MAX.

8.0

Unit

Ceramic

Oscillation

frequency (f^X)^{Note 2}

MHz

VSS X1

X2

resonator

C1

C2

Crystal

Oscillation

frequency (f^X)^{Note 2}

2.0

8.0

MHz

V

SS X1

X2

resonator

C1

External

clock

X1 input

2.7 V ≤ VDD ≤ 5.5 V

2.0

8.0

5.0

MHz

X1

frequency (f^X)^{Note 2}

2.0 V ≤ V^DD< 2.7 V

2.7 V ≤ VDD ≤ 5.5 V

X1 input high-

/low-level width

(t^XH, tXL)

0.057

0.25

μs

2.0 V ≤ V^DD< 2.7 V

0.09

0.25

Notes 1. Use this product in a voltage range of 2.26 to 5.5 V because the detection voltage (V^POC) of the power-on-

clear (POC) circuit is 2.26 V (MAX.).

2. Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time.

Caution When using the X1 oscillator, wire as follows in the area enclosed by the broken lines in the above

figures to avoid an adverse effect from wiring capacitance.

• Keep the wiring length as short as possible.

• Do not cross the wiring with the other signal lines.

• Do not route the wiring near a signal line through which a high fluctuating current flows.

• Always make the ground point of the oscillator capacitor the same potential as V^SS.

• Do not ground the capacitor to a ground pattern through which a high current flows.

• Do not fetch signals from the oscillator.

Remark For the resonator selection and oscillator constant, users are required to either evaluate the oscillation

themselves or apply to the resonator manufacturer for evaluation.

358

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CHAPTER 23 ELECTRICAL SPECIFICATIONS ((A2) grade product)

(A2) grade product TA = −40 to +125°C

High-Speed Internal Oscillator Characteristics (TA = −40 to +125°C, VDD = 2.0 to 5.5 V^{Note 1}, VSS = 0 V)

Resonator

Parameter

Conditions

2.7 V ≤ V^DD≤ 5.5 V TA = −10 to +80°C

T^A= −40 to +125°C

MIN.

TYP. MAX.

Unit

%

High-speed internal Oscillation frequency (fX = 8

3

5

oscillator

MHz^{Note 2}) deviation

%

Oscillation frequency (f^X)^{Note 2}

2.0 V ≤ VDD < 2.7 V

5.5

MHz

Notes 1. Use this product in a voltage range of 2.26 to 5.5 V because the detection voltage (V^POC) of the power-on-

clear (POC) circuit is 2.26 V (MAX.).

2. Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time.

Low-Speed Internal Oscillator Characteristics (TA = −40 to +125°C, VDD = 2.0 to 5.5 V^Note, VSS = 0 V)

Resonator

Parameter

Conditions

MIN.

120

TYP. MAX.

240 495

Unit

kHz

Low-speed internal Oscillation frequency (f^RL)

oscillator

Note Use this product in a voltage range of 2.26 to 5.5 V because the detection voltage (V^POC) of the power-on-clear

(POC) circuit is 2.26 V (MAX.).

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CHAPTER 23 ELECTRICAL SPECIFICATIONS ((A2) grade product)

(A2) grade product TA = −40 to +125°C

DC Characteristics (TA = −40 to +125°C, VDD = 2.0 to 5.5 V^Note, VSS = 0 V) (1/2)

Parameter

Symbol

Conditions

MIN.

TYP.

MAX.

–3.5

Unit

mA

V

Output current, high

IOH1

Pins other than Per pin 2.0 V ≤ VDD ≤ 5.5 V

P20 to P23

Total

4.0 V ≤ VDD ≤ 5.5 V

2.0 V ≤ V^DD< 4.0 V

–17.5

–10.5

–3.5

I^OH2

P20 to P23

Per pin 2.0 V ≤ AVREF ≤ 5.5 V

Total 2.0 V ≤ AV^REF≤ 5.5 V

–10.5

7.0

Output current, low

IOL1

Pins other than Per pin 2.0 V ≤ VDD ≤ 5.5 V

P20 to P23

Total

4.0 V ≤ VDD ≤ 5.5 V

2.0 V ≤ V^DD< 4.0 V

21.0

10.5

I^OL2

P20 to P23

Per pin 2.0 V ≤ AVREF ≤ 5.5 V

7.0

Total

4.0 V ≤ AVREF ≤ 5.5 V

2.0 V ≤ AV^REF< 4.0 V

21.0

10.5

Input voltage, high

Input voltage, low

Output voltage, high

VIH1

VIH2

V^IH3

VIL1

VIL2

V^IL3

VOH1

P00 to P03, P30 to P34, P40 to P47, P120, P123

0.8VDD

VDD

P20 to P23

0.7AVREF

AVREF

VDD

V

P121, P122

0.8VDD

V

P00 to P03, P30 to P34, P40 to P47, P120, P123

0

0.2VDD

0.3AVREF

0.2VDD

V

P20 to P23

P121, P122

0

V

Total of pins other than

P20 to P23

4.0 V ≤ V^DD≤ 5.5 V

I^OH1= –3.5 mA

V^DD− 1.0

V

I^OH1= –10.5 mA

I^OH1= –100 μA

2.0 V ≤ VDD < 4.0 V

VDD – 0.5

V

V^OH2

VOL1

V^OL2

Total of pins P20 to P23 4.0 V ≤ AV^REF≤ 5.5 V AV^REF– 1.0

I^OH2= –7 mA

I^OH2= –3.5 mA

2.0 V ≤ AV^REF< 4.0 V

I^OH2= –100 μA

AV^REF– 0.5

V

Output voltage, low

Total of pins other than

P20 to P23

4.0 V ≤ V^DD≤ 5.5 V

I^OL1= 7 mA

1.3

I^OL1= 21 mA

2.0 V ≤ V^DD< 4.0 V

IOL1 = 400 μA

0.4

1.3

V

Total of pins P20 to P23 4.0 V ≤ AV^REF≤ 5.5 V

I^OL2= 21 mA I^OL2= 7 mA

2.0 V ≤ AV^REF< 4.0 V IOL2 = 400 μA

0.4

10

V

Input leakage current, high ILIH

Input leakage current, low ILIL

Output leakage current, high ILOH

Output leakage current, low ILOL

VI = VDD

Pins other than X1

μA

kΩ

VI = 0 V

Pins other than X1

Pins other than X2

–10

10

VO = VDD

VO = 0 V

–10

120

Pull-up resistance

RPU

RPD

VI = 0 V

10

30

Pull-down resistance

P121, P122, reset status

Note Use this product in a voltage range of 2.26 to 5.5 V because the detection voltage (V^POC) of the power-on-clear

(POC) circuit is 2.26 (MAX.).

Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins.

360

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CHAPTER 23 ELECTRICAL SPECIFICATIONS ((A2) grade product)

(A2) grade product TA = −40 to +125°C

DC Characteristics (TA = −40 to +125°C, VDD = 2.0 to 5.5 V^{Note 1}, VSS = 0 V) (2/2)

Parameter

Symbol

Conditions

MIN. TYP. MAX. Unit

5.8 12.8 mA

7.3 15.8

Note 3

IDD1

Supply

current^{Note 2}

Crystal/ceramic

fX = 8 MHz

When A/D converter is stopped

When A/D converter is operating^{Note 8}

When A/D converter is stopped

When A/D converter is operating^{Note 8}

When A/D converter is stopped

When A/D converter is operating^{Note 8}

When peripheral functions are stopped

When peripheral functions are operating

When peripheral functions are stopped

When peripheral functions are operating

When peripheral functions are stopped

When peripheral functions are operating

When A/D converter is stopped

When A/D converter is operating^{Note 8}

oscillation, external V^DD= 5.0 V 10%^{Note 4}

clock input

fX = 6 MHz

5.5 12.2 mA

15.2

oscillation operating

mode^{Note 6}

V^DD= 5.0 V 10%^{Note 4}

f^X= 5 MHz

3.0

4.5

1.5

6.6

9.6

4.6

7.6

4.2

7.2

mA

V^DD= 3.0 V 10%^{Note 5}

IDD2

Crystal/ceramic

fX = 8 MHz

oscillation, external V^DD= 5.0 V 10%^{Note 4}

clock input HALT

fX = 6 MHz

mode^{Note 6}

1.3

V^DD= 5.0 V 10%^{Note 4}

f^X= 5 MHz

0.48 1.6

2.7

V^DD= 3.0 V 10%^{Note 5}

Note 3

IDD3

IDD4

I^DD5

High-speed internal

oscillation operating

mode^{Note 7}

f^X= 8 MHz

5.0 12.2 mA

6.5 15.2

V^DD= 5.0 V 10%^{Note 4}

High-speed internal f^X= 8 MHz

When peripheral functions are stopped

When peripheral functions are operating

1.4

4.4

7.1

mA

oscillation HALT

mode^{Note 7}

VDD = 5.0 V 10%^{Note 4}

STOP mode

VDD = 5.0 V 10%

V^DD= 3.0 V 10%

When low-speed internal

oscillation is stopped

3.5 1200 μA

When low-speed internal

oscillation is operating

17.5 1300

When low-speed internal

oscillation is stopped

3.5 600

11.0 700

μA

When low-speed internal

oscillation is operating

Notes 1. Use this product in a voltage range of 2.26 to 5.5 V because the detection voltage (VPOC) of the power-on-

clear (POC) circuit is 2.26 V (MAX.).

2. Total current flowing through the internal power supply (V^DD). Peripheral operation current is included

(however, the current that flows through the pull-up resistors of ports is not included).

3. Peripheral operation current is included.

4. When the processor clock control register (PCC) is set to 00H.

5. When the processor clock control register (PCC) is set to 02H.

6. When crystal/ceramic oscillation clock, external clock input is selected as the system clock source using

the option byte.

7. When the high-speed internal oscillation clock is selected as the system clock source using the option

byte.

8. The current that flows through the AV^REFpin is included.

361

User’s Manual U17446EJ5V0UD

CHAPTER 23 ELECTRICAL SPECIFICATIONS ((A2) grade product)

(A2) grade product TA = −40 to +125°C

AC Characteristics

(1) Basic operation (T^A= −40 to +125°C, VDD = 2.0 to 5.5 V^{Note 1}, VSS = 0 V)

Parameter

Symbol

T^CY

Conditions

Crystal/ceramic oscillation

MIN.

0.25

0.33

0.4

TYP.

MAX.

16

Unit

μs

Cycle time (minimum

4.0 V ≤ VDD ≤ 5.5 V

3.0 V ≤ VDD < 4.0 V

2.7 V ≤ VDD < 3.0 V

2.0 V ≤ V^DD< 2.7 V

4.0 V ≤ VDD ≤ 5.5 V

2.7 V ≤ VDD < 4.0 V

2.0 V ≤ V^DD< 2.7 V

instruction execution time)

clock, external clock input

16

1

16

High-speed internal

oscillation clock

0.23

0.47

0.95

4.22

TI000 input high-level width, t^TIH,

4.0 V ≤ VDD ≤ 5.5 V

2.0 V ≤ V^DD< 4.0 V

2/fsam+

0.1^{Note 2}

low-level width

t^TIL

2/fsam+

0.2^{Note 2}

μs

Interrupt input high-level

width, low-level width

t^INTH,

t^INTL

t^RSL

1

RESET input low-level

width

2

μs

Notes 1. Use this product in a voltage range of 2.26 to 5.5 V because the detection voltage (V^POC) of the power-on-

clear (POC) circuit is 2.26 V (MAX.).

2. Selection of fsam = f^XP, fXP/4, or fXP/256 is possible using bits 0 and 1 (PRM000, PRM001) of prescaler

mode register 00 (PRM00). Note that when selecting the valid edge of the TI000 pin as the count clock,

fsam = f^XP.

CPU Clock Frequency, Peripheral Clock Frequency

Parameter

Conditions

CPU Clock (fCPU)

125 kHz ≤ fCPU ≤ 8 MHz

125 kHz ≤ fCPU ≤ 6 MHz

125 kHz ≤ fCPU ≤ 5 MHz

125 kHz ≤ fCPU ≤ 2 MHz

Peripheral Clock (fXP)

500 kHz ≤ fXP ≤ 8 MHz

Ceramic resonator,

crystal resonator,

external clock

4.0 to 5.5 V

3.0 to 4.0 V

2.7 to 3.0 V

2.0 to 2.7 V^Note

4.0 to 5.5 V

2.7 to 4.0 V

2.0 to 2.7 V^Note

500 kHz ≤ fXP ≤ 5 MHz

High-speed internal

oscillator

500 kHz (TYP.) ≤ fCPU ≤ 8 MHz (TYP.) 2 MHz (TYP.) ≤ fXP ≤ 8 MHz (TYP.)

500 kHz (TYP.) ≤ fCPU ≤ 4 MHz (TYP.)

500 kHz (TYP.) ≤ fCPU ≤ 2 MHz (TYP.) 2 MHz (TYP.) ≤ fXP ≤ 4 MHz (TYP.)

Note Use this product in a voltage range of 2.26 to 5.5 V because the detection voltage (VPOC) of the power-on-clear

(POC) circuit is 2.26 V (MAX.).

362

User’s Manual U17446EJ5V0UD

CHAPTER 23 ELECTRICAL SPECIFICATIONS ((A2) grade product)

(A2) grade product TA = −40 to +125°C

TCY vs. VDD (Crystal/Ceramic Oscillation Clock, External Clock Input)

60

16

10

μ

Guaranteed

operation range

1.0

0.4

0.33

0.25

0.1

1

2

3

4

5

6

2.7

Supply voltage VDD [V]

5.5

T^CYvs. VDD (High-speed internal oscillator Clock)

60

10

μ

4.22

Guaranteed

operation range

1.0

0.95

0.47

0.23

0.1

1

2

3

4

5

6

2.7

Supply voltage VDD [V]

5.5

363

User’s Manual U17446EJ5V0UD

CHAPTER 23 ELECTRICAL SPECIFICATIONS ((A2) grade product)

(A2) grade product TA = −40 to +125°C

(2) Serial interface (TA = −40 to +125°C, VDD = 2.0 to 5.5 V^Note, VSS = 0 V)

UART mode (UART6, dedicated baud rate generator output)

Parameter

Transfer rate

Symbol

Conditions

MIN.

TYP.

MAX.

312.5

Unit

kbps

Note Use this product in a voltage range of 2.26 to 5.5 V because the detection voltage (V^POC) of the power-on-clear

(POC) circuit is 2.26 V (MAX.).

AC Timing Test Points (Excluding X1 Input)

0.8VDD

0.2VDD

0.8VDD

0.2VDD

Test points

Clock Timing

1/f

X

t

XL

t

XH

X1 input

TI000 Timing

tTIL

tTIH

TI000

Interrupt Input Timing

t

INTL

t

INTH

INTP0 to INTP3

RESET Input Timing

tRSL

RESET

364

User’s Manual U17446EJ5V0UD

CHAPTER 23 ELECTRICAL SPECIFICATIONS ((A2) grade product)

(A2) grade product TA = −40 to +125°C

A/D Converter Characteristics (TA = −40 to +125°C, 2.7 V ≤ AVREF ≤ VDD ≤ 5.5 V, VSS = AVSS = 0 V)

Parameter

Symbol

Conditions

MIN.

10

TYP.

10

MAX.

10

Unit

bit

Resolution

Overall error^{Notes 1, 2}

AINL

4.0 V ≤ AVREF ≤ 5.5 V

0.2

0.3

0.7

0.9

30

%FSR

μs

2.7 V ≤ AV^REF< 4.0 V

4.5 V ≤ AVREF ≤ 5.5 V

4.0 V ≤ AVREF < 4.5 V

2.85 V ≤ AVREF < 4.0 V

2.7 V ≤ AV^REF< 2.85 V

4.0 V ≤ AVREF ≤ 5.5 V

2.7 V ≤ AV^REF< 4.0 V

4.0 V ≤ AVREF ≤ 5.5 V

2.7 V ≤ AV^REF< 4.0 V

4.0 V ≤ AVREF ≤ 5.5 V

2.7 V ≤ AV^REF< 4.0 V

4.0 V ≤ AVREF ≤ 5.5 V

2.7 V ≤ AV^REF< 4.0 V

Conversion time

tCONV

3.0

4.8

30

μs

6.0

30

μs

14.0

30

μs

Zero-scale error^{Notes 1, 2}

Ezs

Efs

0.7

0.9

0.7

0.9

5.5

7.5

2.5

3.0

AVREF

%FSR

LSB

V

Full-scale error^{Notes 1, 2}

Integral non-linearity error^{Note 1}

Differential non-linearity error^{Note 1}

Analog input voltage

ILE

DLE

VAIN

VSS

Notes 1. Excludes quantization error ( 1/2 LSB).

2. This value is indicated as a ratio (%FSR) to the full-scale value.

Caution The conversion accuracy may be degraded if the analog input pin is used as an alternate I/O port or

if a port is changed during A/D conversion.

365

User’s Manual U17446EJ5V0UD

CHAPTER 23 ELECTRICAL SPECIFICATIONS ((A2) grade product)

(A2) grade product TA = −40 to +125°C

POC Circuit Characteristics (TA = −40 to +125°C)

Parameter

Detection voltage

Symbol

V^POC

Conditions

MIN.

2.0

TYP.

2.1

MAX.

2.26

Unit

V

Power supply boot time

tPTH

VDD: 0 V → 2.1 V

1.5

μs

Response delay time 1^{Note 1}

tPTHD

When power supply rises, after reaching

detection voltage (MAX.)

3.0

1.0

ms

Response delay time 2^{Note 2}

Minimum pulse width

tPD

ms

When power supply falls

tPW

0.2

Notes 1. Time required from voltage detection to internal reset release.

2. Time required from voltage detection to internal reset signal generation.

POC Circuit Timing

Supply voltage

(V^DD

)

Detection voltage (MAX.)

Detection voltage (TYP.)

Detection voltage (MIN.)

t

PW

t

PTH

t

PTHD

t

PD

Time

366

User’s Manual U17446EJ5V0UD

CHAPTER 23 ELECTRICAL SPECIFICATIONS ((A2) grade product)

(A2) grade product TA = −40 to +125°C

LVI Circuit Characteristics (TA = −40 to +125°C)

Parameter

Detection voltage

Symbol

VLVI0

VLVI1

VLVI2

VLVI3

VLVI4

VLVI5

VLVI6

VLVI7

VLVI8

V^LVI9

tLD

Conditions

MIN.

4.1

TYP.

4.3

MAX.

4.65

4.45

4.25

4.05

3.85

3.60

3.40

3.15

2.85

2.60

2.0

Unit

V

3.9

4.1

V

3.7

3.9

V

3.5

3.7

V

3.3

3.5

V

3.15

2.95

2.70

2.50

2.25

3.3

V

3.1

V

2.85

2.60

2.35

0.2

V

Response time^{Note 1}

ms

Minimum pulse width

tLW

0.2

Operation stabilization wait time^{Note 2}

tLWAIT

0.1

0.2

Notes 1. Time required from voltage detection to interrupt output or internal reset signal generation.

2. Time required from setting LVION to 1 to operation stabilization.

Remarks 1. V^LVI0> VLVI1 > VLVI2 > VLVI3 > VLVI4 > VLVI5 > VLVI6 > VLVI7 > VLVI8 > VLVI9

2. V^POC< VLVIm (m = 0 to 9)

LVI Circuit Timing

Supply voltage

(V^DD

)

Detection voltage (MAX.)

Detection voltage (TYP.)

Detection voltage (MIN.)

tLW

t

LWAIT

tLD

LVION

1

Time

Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics (T^A= −40 to +125°C)

Parameter

Symbol

VDDDR

tSREL

Conditions

MIN.

2.0

0

TYP.

MAX.

5.5

Unit

V

Data retention supply voltage

Release signal set time

μs

367

User’s Manual U17446EJ5V0UD

CHAPTER 23 ELECTRICAL SPECIFICATIONS ((A2) grade product)

(A2) grade product TA = −40 to +125°C

Flash Memory Programming Characteristics (TA = –40 to +105°C, 2.7 V ≤ VDD ≤ 5.5 V, VSS = 0 V)

Parameter

Symbol

IDD

Conditions

MIN.

TYP.

MAX.

7.0

Unit

mA

Supply current

VDD = 5.5 V

Erasure count^{Note 1}

(per 1 block)

N^ERASE

TA = −40 to +105°C

1000

Times

Chip erase time

TCERASE

TA = −10 to +105°C,

N^ERASE≤ 100

4.5 V ≤ VDD ≤ 5.5 V

3.5 V ≤ VDD < 4.5 V

2.7 V ≤ V^DD< 3.5 V

4.5 V ≤ VDD ≤ 5.5 V

3.5 V ≤ VDD < 4.5 V

2.7 V ≤ V^DD< 3.5 V

4.5 V ≤ VDD ≤ 5.5 V

3.5 V ≤ VDD < 4.5 V

2.7 V ≤ V^DD< 3.5 V

4.5 V ≤ VDD ≤ 5.5 V

3.5 V ≤ VDD < 4.5 V

2.7 V ≤ V^DD< 3.5 V

4.5 V ≤ VDD ≤ 5.5 V

3.5 V ≤ VDD < 4.5 V

2.7 V ≤ V^DD< 3.5 V

4.5 V ≤ VDD ≤ 5.5 V

3.5 V ≤ VDD < 4.5 V

2.7 V ≤ V^DD< 3.5 V

4.5 V ≤ VDD ≤ 5.5 V

3.5 V ≤ VDD < 4.5 V

2.7 V ≤ V^DD< 3.5 V

4.5 V ≤ VDD ≤ 5.5 V

3.5 V ≤ VDD < 4.5 V

2.7 V ≤ V^DD< 3.5 V

0.8

1.0

1.2

4.8

5.2

6.1

1.6

1.8

2.0

9.1

10.1

12.3

0.4

0.5

0.6

2.6

2.8

3.3

0.9

1.0

1.1

4.9

5.4

6.6

150

6.8

27

s

TA = −10 to +105°C,

N^ERASE≤ 1000

s

TA = −40 to +105°C,

N^ERASE≤ 100

s

T^A= −40 to +105°C,

N^ERASE≤ 1000

s

Block erase time

TBERASE

TA = −10 to +105°C,

N^ERASE≤ 100

s

TA = −10 to +105°C,

N^ERASE≤ 1000

s

TA = −40 to +105°C,

N^ERASE≤ 100

s

T^A= −40 to +105°C,

N^ERASE≤ 1000

s

Byte write time

Internal verify

TWRITE

TVERIFY

TA = −40 to +105°C, NERASE ≤ 1000

Per 1 block

μs

ms

μs

mW

Years

Per 1 byte

Blank check

Total loss

TBLKCHK

Per 1 block

480

120

Note 3

PT

TA = −40 to +105°C

TA = 85°C^{Note 2}, NERASE ≤ 1000

Retention years

10

Notes 1. Depending on the erasure count (N^ERASE), the erase time varies. Refer to the chip erase time and block

erase time parameters.

2. When the average temperature when operating and not operating is 85°C.

Remark When a product is first written after shipment, “erase → write” and “write only” are both taken as one rewrite.

(Note 3 is listed on the next page.)

368

User’s Manual U17446EJ5V0UD

CHAPTER 23 ELECTRICAL SPECIFICATIONS ((A2) grade product)

(A2) grade product TA = −40 to +125°C

Note 3. When guaranteeing the flash self programming, use the following formula to perform design such that the

sum of the power consumption of the device is less than or equal to the total loss P^T(use at 80% or less of

the rated value is recommended).

• Total power consumption = V^DD× {IDD − ∑IOH} + ∑{(VDD − VOH) × IOH} + ∑(VOL × IOL)

When guaranteeing the internal pull-up resistor, use the following formula to calculate its power

consumption, and add the result to the result above.

• Power consumption of internal pull-up resistor = Σ(V^DD/RPU × VDD)

Remark During flash memory programming, I^DD= 7.0 mA (MAX.).

369

User’s Manual U17446EJ5V0UD

CHAPTER 24 PACKAGE DRAWING

• μ PD78F9232MC-5A4-A, 78F9234MC-5A4-A, 78F9232MC(A)-5A4-A, 78F9234MC(A)-5A4-A,

78F9232MC(A2)-5A4-A, 78F9234MC(A2)-5A4-A

30-PIN PLASTIC SSOP (7.62 mm (300))

30

16

detail of lead end

F

G

T

P

L

1

5

U

E

A

H

I

J

S

B

C

N

S

M

D

M

K

NOTE

ITEM MILLIMETERS

Each lead centerline is located within 0.13 mm of

its true position (T.P.) at maximum material condition.

A

B

C

9.85 0.15

0.45 MAX.

0.65 (T.P.)

+0.08

0.24

D

−0.07

E

F

G

H

I

0.1 0.05

1.3 0.1

1.2

8.1 0.2

6.1 0.2

1.0 0.2

0.17 0.03

0.5

J

K

L

M

N

0.13

0.10

+5°

3°

P

−3°

T

0.25

U

0.6 0.15

S30MC-65-5A4-2

370

User’s Manual U17446EJ5V0UD

CHAPTER 24 PACKAGE DRAWING

• μ PD78F9232MC(A)-CAB-AX, 78F9234MC(A)-CAB-AX, 78F9232MC(A2)-CAB-AX, 78F9234MC(A2)-CAB-AX

30-PIN PLASTIC SSOP (7.62mm (300))

V

30

16

detail of lead end

T

I

P

L

U

1

15

W

F

A

H

G

J

S

B

K

C

N

S

E

(UNIT:mm)

ITEM DIMENSIONS

D

M

A

B

C

9.70 0.10

0.30

0.65 (T.P.)

NOTE

+0.10

0.22

D

−0.05

Each lead centerline is located within 0.13 mm of its

true position (T.P.) at maximum material condition.

E

F

G

H

I

0.10 0.05

1.30 0.10

1.20

8.10 0.20

6.10 0.10

1.00 0.20

J

+0.05

0.15

K

−0.01

L

M

N

0.50

0.13

0.10

+5°

3°

P

T

−3°

0.25(T.P.)

0.60 0.15

0.25 MAX.

U

V

0.15 MAX.

W

P30MC-65-CAB

371

User’s Manual U17446EJ5V0UD

CHAPTER 24 PACKAGE DRAWING

• μ PD78F9232CS-CAA-A, 78F9234CS-CAA-A

32-PIN PLASTIC SDIP (7.62mm(300))

D

17

16

32

1

E

B

A

A2

e1

C

e

c

Z

A

θ

b2

A1

b1

b

M

x

C

A B

(UNIT:mm)

L

ITEM DIMENSIONS

28.05 0.15

6.60 0.20

3.45 0.15

0.65 0.10

2.80

D

E

A

A1

A2

e

1.778

e1

7.62

0.50

0.10

b

1.02 0.10

b1

0.75 0.10

b2

c

+ 0.10

0.25

0.05

2.86

0.25

0.20

L

x

θ

to 15°

0°

Z

0.615

P32CS-70-CAA

372

User’s Manual U17446EJ5V0UD

CHAPTER 25 RECOMMENDED SOLDERING CONDITIONS

These products should be soldered and mounted under the following recommended conditions.

For technical information, see the following website.

Semiconductor Device Mount Manual (http://www.necel.com/pkg/en/mount/index.html)

Cautions 1. Products with –A or –AX at the end of the part number are lead-free products.

2. For soldering methods and conditions other than those recommended below, contact an NEC

Electronics sales representative.

Table 25-1. Surface Mounting Type Soldering Conditions (1/2)

• 30-pin plastic SSOP (lead-free products)

μPD78F9232MC-5A4-A, 78F9234MC-5A4-A, 78F9232MC(A)-5A4-A, 78F9234MC(A)-5A4-A,

78F9232MC(A2)-5A4-A, 78F9234MC(A2)-5A4-A

Soldering Method

Infrared reflow

Soldering Conditions

Recommended

Condition Symbol

Package peak temperature: 260°C, Time: 60 seconds max. (at 220°C or higher),

Count: 3 times or less, Exposure limit: 7 days^Note(after that, prebake at 125°C for

20 to 72 hours)

IR60-207-3

Wave soldering

Partial heating

For details, contact an NEC Electronics sales representative.

−

Pin temperature: 350°C max., Time: 3 seconds max. (per pin row)

Note After opening the dry pack, store it at 25°C or less and 65% RH or less for the allowable storage period.

Caution Do not use different soldering methods together (except for partial heating).

373

User’s Manual U17446EJ5V0UD

CHAPTER 25 RECOMMENDED SOLDERING CONDITIONS

Table 25-1. Surface Mounting Type Soldering Conditions (2/2)

• 30-pin plastic SSOP (lead-free products)

μPD78F9232MC(A)-CAB-AX, 78F9234MC(A)-CAB-AX, 78F9232MC(A2)-CAB-AX,

78F9234MC(A2)-CAB-AX

Soldering Method

Infrared reflow

Soldering Conditions

Recommended

Condition Symbol

Package peak temperature: 260°C, Time: 60 seconds max. (at 220°C or higher),

Count: 3 times or less, Exposure limit: 7 days^Note(after that, prebake at 125°C for

10 to 72 hours)

IR60-107-3

WS60-107-1

−

Wave soldering

Partial heating

Solder bath temperature: 260°C max., Time: 10 seconds max., Count: Once,

Preheating temperature: 120°C max. (package surface temperature), Exposure

limit: 7 days^Note(after that, prebake at 125°C for 10 to 72 hours)

Pin temperature: 350°C max., Time: 3 seconds max. (per pin row)

Note After opening the dry pack, store it at 25°C or less and 65% RH or less for the allowable storage period.

Caution Do not use different soldering methods together (except for partial heating).

• 32-pin plastic SDIP (lead-free products)

μPD78F9232CS-CAA-A, 78F9234CS-CAA-A

Soldering Method

Soldering Conditions

Recommended

Condition Symbol

Wave soldering

(only for pins)

Solder bath temperature: 260°C max., Time: 10 seconds max.

Pin temperature: 350°C max., Time: 3 seconds max. (per one pin)

−

Partial heating

Caution Only the pins of the THD are heated when performing wave soldering.

Make sure that flow solder does not come in contact with the package.

374

User’s Manual U17446EJ5V0UD

APPENDIX A DEVELOPMENT TOOLS

<R>

The following development tools are available for development of systems using the 78K0S/KB1+.

Figure A-1 shows the development tool configuration.

375

User’s Manual U17446EJ5V0UD

APPENDIX A DEVELOPMENT TOOLS

Figure A-1. Development Tool Configuration (1/2)

(1) When using the in-circuit emulator QB-78K0SKX1

Software package

· Software package

Debugging software

Language processing software

· Assembler package

· C compiler package

· Device file^{Note 1}

· Integrated debugger^{Note 1}

· System simulator^{Note 2}

Control software

· Project manager

(Windows only)^{Note 3}

Host machine

(PC or EWS)

USB interface cable^{Note 4}

Power supply unit

QB-78K0SKX1^{Note 4}

< Flash memory write environment >

Flash memory

Emulation probe

programmer^{Note 4}

Off-board

programming

On-board

programming

Conversion adapter

Flash memory

write adapter

78K0/Kx1+

Target connector

Target system

Notes 1. Download the device file for 78K0S/Kx1+ microcontrollers (DF789234) and the integrated debugger

ID78K0S-QB from the download site for development tools (http://www.necel.com/micro/en/ods/).

2. SM+ for 78K0S (instruction simulation version) is included in the software package. SM+ for

78K0S/Kx1+ (instruction + peripheral simulation version) is not included.

3. The project manager PM+ is included in the assembler package.

PM+ cannot be used other than with Windows^TM.

4. QB-78K0SKX1 is supplied with the integrated debugger ID78K0S-QB, a USB interface cable, the on-

chip debug emulator with programming function QB-MINI2, a connection cable, and a target cable.

Any other products are sold separately.

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APPENDIX A DEVELOPMENT TOOLS

Figure A-1. Development Tools (2/2)

(2) When using the on-chip debug emulator with programming function QB-MINI2

Software package

• Software package

Debugging software

Language processing software

• Integrated debugger^{Note 1}

• System simulator^{Note 2}

• Assembler package

• C compiler package

• Device file^{Note 1}

Control software

• Project manager

(Windows only)^{Note 3}

Host machine

(PC or EWS)

USB interface cable^{Note 4}

QB-MINI2^{Note 4}

Connection cable^{Note 4}

Target connector

Target system

Notes 1. Download the device file for 78K0S/Kx1+ microcontrollers (DF789234) and the integrated debugger

ID78K0S-QB from the download site for development tools (http://www.necel.com/micro/en/ods/).

2. SM+ for 78K0S (instruction simulation version) is included in the software package. SM+ for

78K0S/Kx1+ (instruction + peripheral simulation version) is not included.

3. The project manager PM+ is included in the assembler package.

PM+ cannot be used other than with Windows.

4. QB-MINI2 is supplied with USB interface cable and connection cable. Any other products are sold

separately. In addition, download the software for operating the QB-MINI2 from the download site for

development tools (http://www.necel.com/micro/en/ods/).

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APPENDIX A DEVELOPMENT TOOLS

A.1 Software Package

Development tools (software) common to the 78K0S microcontrollers are combined in this package.

SP78K0S

78K0S microcontroller

software package

A.2 Language Processing Software

RA78K0S^{Note 1}

This assembler converts programs written in mnemonics into object codes executable with a

microcontroller.

Assembler package

This assembler is also provided with functions capable of automatically creating symbol tables and

branch instruction optimization.

This assembler should be used in combination with a device file (DF789234).

This assembler package is a DOS-based application. It can also be used in Windows, however, by

using the Project Manager (PM+) on Windows. PM+ is included in assembler package.

CC78K0S^{Note 1}

This compiler converts programs written in C language into object codes executable with a

microcontroller.

C compiler package

This compiler should be used in combination with an assembler package and device file.

This C compiler package is a DOS-based application. It can also be used in Windows, however, by

using the Project Manager (PM+) on Windows. PM+ is included in assembler package.

DF789234^{Note 2}

Device file

This file contains information peculiar to the device.

This device file should be used in combination with a tool (RA78K0S, CC78K0S, ID78K0S-QB, and

the system simulator).

The corresponding OS and host machine differ depending on the tool to be used.

Notes 1. If the versions of RA78K0S and CC78K0S are Ver.2.00 or later, different versions of RA78K0S and

CC78K0S can be installed on the same machine.

2. The DF789234 can be used in common with the RA78K0S, CC78K0S, ID78K0S-QB, and the system

simulator. Download the DF789234 from the download site for development tools

(http://www.necel.com/micro/en/ods/).

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APPENDIX A DEVELOPMENT TOOLS

A.3 Flash Memory Writing Tools

A.3.1 When using flash memory programmer PG-FP5 and FL-PR5

FL-PR5, PG-FP5

This is a flash memory programmer dedicated to microcontrollers incorporating a flash

Flash memory programmer

memory.

FA-78F9234MC-5A4-RX

This is a flash memory writing adapter which is used in connection with the flash

memory programmer.

Flash memory writing adapter

Remarks 1. FL-PR5 and FA-78F9234MC-5A4-RX are products of Naito Densei Machida Mfg. Co., Ltd

(http://www.ndk-m.co.jp/, e-mail: info@ndk-m.co.jp).

2. Use the latest version of the flash memory programming adapter.

A.3.2 When using on-chip debug emulator with programming function QB-MINI2

QB-MINI2

This is a flash memory programmer dedicated to microcontrollers with on-chip flash

memory. It is available also as on-chip debug emulator which serves to debug hardware

and software when developing application systems using the 78K0S/Kx1+

microcontrollers. When using this as flash memory programmer, it should be used in

combination with a connection cable and a USB interface cable that is used to connect

the host machine.

On-chip debug emulator with

programming function

Target connector specifications

16-pin general-purpose connector (2.54 mm pitch)

Remark Download the software for operating the QB-MINI2 from the download site for development tools

(http://www.necel.com/micro/en/ods/).

A.4 Debugging Tools (Hardware)

A.4.1 When using in-circuit emulator QB-78K0SKX1

QB-78K0SKX1

This in-circuit emulator serves to debug hardware and software when developing application

systems using the 78K0S/Kx1+ microcontrollers. It supports the integrated debugger

(ID78K0S-QB). This emulator should be used in combination with a power supply unit and

emulation probe, and the USB is used to connect this emulator to the host machine.

In-circuit emulator

QB-50-EP-01T^Note

Emulation probe

This is a flexible type emulation probe and is used to connect the in-circuit emulator and target

system.

QB-30MC-EA-04T^Note

Exchange adapter

This exchange adapter is used to perform pin conversion from the in-circuit emulator to target

connector.

QB-30MC -NQ-02T^Note

Target connector

This target connector is used to mount on the target system.

Specifications of pin header on 0.635 mm × 0.635 mm (height: 6 mm)

target system

(Note and Remarks are listed on the next page or later.)

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APPENDIX A DEVELOPMENT TOOLS

Note The part numbers of the exchange adapter and target connector and the packages of the target device are

described below.

Package

Exchange Adapter

QB-30MC-EA-04T

Target Connector

QB-30MC-NQ-02T

30-pin plastic SSOP

(MC-5A4 and MC-CAB types)

32-pin plastic SDIP

(CS-CAA type)

None

Remarks 1. For the SDIP package, use the target cable.

2. The QB-78K0SKX1 is supplied with the integrated debugger ID78K0S-QB, a USB interface cable, the

on-chip debug emulator QB-MINI2, and a connection cable.

Download the software for operating the QB-MINI2 from the download site for development tools

(http://www.necel.com/micro/en/ods/) when using the QB-MINI2.

3. The packed contents of QB-78K0SKX1 differ depending on the part number, as follows.

Packed Contents In-Circuit Emulator

Part Number

Emulation Probe

Exchange Adapter Target Connector

QB-30MC-EA-04T QB-30MC-NQ-02T

QB-78K0SKX1-ZZZ

QB-78K0SKX1

None

QB-50-EP-01T

QB-78K0SKX1-T30MC

A.4.2 When using on-chip debug emulator with programming function QB-MINI2

QB-MINI2

This on-chip debug emulator serves to debug hardware and software when developing

On-chip debug emulator with

programming function

application systems using the 78K0S/Kx1+ microcontrollers. It is available also as flash

memory programmer dedicated to microcontrollers with on-chip flash memory. When

using this as on-chip debug emulator, it should be used in combination with a connection

cable and a USB interface cable that is used to connect the host machine.

Target connector specifications

16-pin general-purpose connector (2.54 mm pitch)

Remark Download the software for operating the QB-MINI2 from the download site for development tools

(http://www.necel.com/micro/en/ods/).

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APPENDIX A DEVELOPMENT TOOLS

A.5 Debugging Tools (Software)

ID78K0S-QB^Note

(supporting

This debugger supports the in-circuit emulators for the 78K0S/Kx1+ microcontrollers. The

ID78K0S-QB is Windows-based software.

QB-78K0SKX1, QB-MINI2) Provided with the debug function supporting C language, source programming, disassemble

Integrated debugger

display, and memory display are possible.

It should be used in combination with the device file (DF789234).

SM+ for 78K0S

System simulator is Windows-based software.

SM+ for 78K0S/Kx1+^Note

It is used to perform debugging at the C source level or assembler level while simulating the

operation of the target system on a host machine.

System simulator

Use of system simulator allows the execution of application logical testing and performance testing

on an independent basis from hardware development, thereby providing higher development

efficiency and software quality.

System simulator should be used in combination with the device file (DF789234).

The following two types of system simulators supporting the 78K0S/Kx1+ microcontrollers are

available.

• SM+ for 78K0S (instruction simulation version)

This can only simulate a CPU. It is included in the software package.

• SM+ for 78K0S/Kx1+ (instruction + peripheral simulation version)

This can simulate a CPU and peripheral hardware (ports, timers, serial interfaces, etc.).

Note Download the ID78K0S-QB from the download site for development tools

(http://www.necel.com/micro/en/ods/).

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APPENDIX B NOTES ON DESIGNING TARGET SYSTEM

This chapter shows areas on the target system where component mounting is prohibited and areas where there

are component mounting height restrictions when the QB-78K0SKX1 is used.

For the package drawings of the target connector, exchange adapter, and emulation probe, see the following

website.

http://www.necel.com/micro/en/development/asia/iecube/outline_QB.html

Figure B-1. When using the 78K0S/Kx1+ emulation probe (For 30-Pin MC Package)

Top view

Unit : mm

: 1pin

Center point of

Target connector

8.1

17.0

: Exchange adapter tip area → Components up to 11 mm high can be mounted.

: Target connector area

Overview

Viewing direction

IECUBE

TC

EP

EA

Note EP: Emulation probe

EA: Exchange adapter

TC: Target connector

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APPENDIX B NOTES ON TARGET SYSTEM DESIGN

Figure B-2. When using the 78K0S/Kx1+ target cable (single track)

Top view

Unit : mm

2.54

: A interval pin header → More than 2.54mm

: A contact area of a pin header → 0.635 × 0.635mm (Height: 6mm)

Overview

Viewing direction

IECUBE

Target cable

Pin header

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User’s Manual U17446EJ5V0UD

APPENDIX C REGISTER INDEX

C.1 Register Index (Register Name)

8-bit A/D conversion result register (ADCRH) … 171

8-bit compare register 80 (CR80) … 131

8-bit timer counter 80 (TM80) … 131

8-bit timer H compare register 01 (CMP01) … 138

8-bit timer H compare register 11 (CMP11) … 138

8-bit timer H mode register 1 (TMHMD1) … 139

8-bit timer mode control register 80 (TMC80) … 132

10-bit A/D conversion result register (ADCR) … 170

16-bit timer capture/compare register 000 (CR000) … 90

16-bit timer capture/compare register 010 (CR010) … 92

16-bit timer counter 00 (TM00) … 90

16-bit timer mode control register 00 (TMC00) … 93

16-bit timer output control register 00 (TOC00) … 96

16-bit multiplication result storage register 0 (MUL0) … 220

[A]

A/D converter mode register (ADM) … 168

Analog input channel specification register (ADS) … 170

Asynchronous serial interface control register 6 (ASICL6) … 195

Asynchronous serial interface operation mode register 6 (ASIM6) … 189

Asynchronous serial interface reception error status register 6 (ASIS6) … 191

Asynchronous serial interface transmission status register 6 (ASIF6) … 192

[B]

Baud rate generator control register 6 (BRGC6) … 194

[C]

Capture/compare control register 00 (CRC00) … 95

Clock selection register 6 (CKSR6) … 193

[E]

External interrupt mode register 0 (INTM0) … 231

External interrupt mode register 1 (INTM1) … 232

[F]

Flash address pointer H (FLAPH) … 290

Flash address pointer L (FLAPL) … 290

Flash address pointer H compare register (FLAPHC) … 290

Flash address pointer L compare register (FLAPLC) … 290

Flash programming command register (FLCMD) … 289

Flash programming mode control register (FLPMC) … 286

Flash protect command register (PFCMD) … 287

Flash status register (PFS) … 287

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APPENDIX C REGISTER INDEX

Flash write buffer register (FLW) … 291

[I]

Input switch control register (ISC) … 197

Interrupt mask flag register 0 (MK0) … 230

Interrupt mask flag register 1 (MK1) … 230

Interrupt request flag register 0 (IF0) … 229

Interrupt request flag register 1 (IF1) … 229

[L]

Low-voltage detect register (LVIM) … 261

Low-voltage detection level select register (LVIS) … 262

Low-speed internal oscillation mode register (LSRCM) … 76

[M]

Multiplication data register A (MRA0) … 220

Multiplication data register B (MRB0) … 220

Multiplier control register 0 (MULC0) … 222

[O]

Oscillation stabilization time select register (OSTS) … 77, 240

[P]

Port mode control register 2 (PMC2) … 69, 171

Port mode register 0 (PM0) … 67

Port mode register 2 (PM2) … 67, 171

Port mode register 3 (PM3) … 67, 98

Port mode register 4 (PM4) … 67, 141, 197

Port mode register 12 (PM12) … 67

Port register 0 (P0) … 68

Port register 2 (P2) … 68

Port register 3 (P3) … 68

Port register 4 (P4) … 68

Port register 12 (P12) … 68

Port register 13 (P13) … 68

Preprocessor clock control register (PPCC) … 75

Prescaler mode register 00 (PRM00) … 97

Processor clock control register (PCC) … 75

Pull-up resistor option register 0 (PU0) … 70

Pull-up resistor option register 2 (PU2) … 70

Pull-up resistor option register 3 (PU3) … 70

Pull-up resistor option register 4 (PU4) … 70

Pull-up resistor option register 12 (PU12) … 70

[R]

Receive buffer register 6 (RXB6) … 188

Receive shift register 6 (RXS6) … 188

Reset control flag register (RESF) … 255

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APPENDIX C REGISTER INDEX

[T]

Transmit buffer register 6 (TXB6) … 188

Transmit shift register 6 (TXS6) … 188

[W]

Watchdog timer enable register (WDTE) … 155

Watchdog timer mode register (WDTM) … 154

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APPENDIX C REGISTER INDEX

C.2 Register Index (Symbol)

[A]

ADCR:

ADCRH:

ADM:

10-bit A/D conversion result register … 170

8-bit A/D conversion result register … 171

A/D converter mode register … 168

ADS:

Analog input channel specification register … 170

ASICL6:

ASIF6:

ASIM6:

ASIS6:

Asynchronous serial interface control register 6 … 195

Asynchronous serial interface transmission status register 6 … 192

Asynchronous serial interface operation mode register 6 … 189

Asynchronous serial interface reception error status register 6 … 191

[B]

BRGC6:

Baud rate generator control register 6 … 194

[C]

CKSR6:

CMP01:

CMP11:

CR000:

CR010:

CR80:

Clock selection register 6 … 193

8-bit timer H compare register 01 … 138

8-bit timer H compare register 11 … 138

16-bit timer capture/compare register 000 … 90

16-bit timer capture/compare register 010 … 92

8-bit compare register 80 … 131

CRC00:

Capture/compare control register 00 … 95

[F]

FLAPH:

Flash address pointer H … 290

FLAPHC: Flash address pointer H compare register … 290

FLAPL: Flash address pointer L … 290

FLAPLC: Flash address pointer L compare register … 290

FLCMD:

FLPMC:

FLW:

Flash programming command register … 289

Flash programming mode control register … 286

Flash write buffer register … 291

[I]

IF0:

Interrupt request flag register 0 … 229

Interrupt request flag register 1 … 229

External interrupt mode register 0 … 231

External interrupt mode register 1 … 232

Input switch control register … 197

IF1:

INTM0:

INTM1:

ISC:

[L]

LSRCM:

LVIM:

LVIS:

Low-speed internal oscillation mode register … 76

Low-voltage detect register … 261

Low-voltage detection level select register … 262

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APPENDIX C REGISTER INDEX

[M]

MK0:

Interrupt mask flag register 0 … 230

MK1:

Interrupt mask flag register 1 … 230

Multiplication data register A … 220

Multiplication data register B … 220

16-bit multiplication result storage register 0 … 220

Multiplier control register 0 … 222

MRA0:

MRB0:

MUL0:

MULC0:

[O]

OSTS:

Oscillation stabilization time select register … 77, 240

[P]

P0:

Port register 0 … 68

P2:

Port register 2 … 68

P3:

Port register 3 … 68

P4:

Port register 4 … 68

P12:

P13:

PCC:

Port register 12 … 68

Port register 13 … 68

Processor clock control register … 75

PFCMD: Flash protect command register … 287

PFS:

Flash status register … 287

PM0:

PM2:

PM3:

PM4:

PM12:

PMC2:

PPCC:

PRM00:

PU0:

Port mode register 0 … 67

Port mode register 2 … 67, 171

Port mode register 3 … 67, 98

Port mode register 4 … 67, 141, 197

Port mode register 12 … 67

Port mode control register 2 … 69, 171

Preprocessor clock control register … 75

Prescaler mode register 00 … 97

Pull-up resistor option register 0 … 70

Pull-up resistor option register 2 … 70

Pull-up resistor option register 3 … 70

Pull-up resistor option register 4 … 70

Pull-up resistor option register 12 … 70

PU2:

PU3:

PU4:

PU12:

[R]

RESF:

RXB6:

RXS6:

Reset control flag register … 255

Receive buffer register 6 … 188

Receive shift register 6 … 188

[T]

TM00:

TM80:

TMC00:

TMC80:

16-bit timer counter 00 … 90

8-bit timer counter 80 … 131

16-bit timer mode control register 00 … 93

8-bit timer mode control register 80 … 132

TMHMD1: 8-bit timer H mode register 1 … 139

TOC00:

16-bit timer output control register 00 … 96

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APPENDIX C REGISTER INDEX

TXB6:

TXS6:

Transmit buffer register 6 … 188

Transmit shift register 6 … 188

[W]

WDTE:

WDTM:

Watchdog timer enable register … 155

Watchdog timer mode register … 154

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APPENDIX D LIST OF CAUTIONS

This appendix lists cautions described in this document.

“Classification (hard/soft)” in table is as follows.

Hard: Cautions for microcontroller internal/external hardware

Soft: Cautions for software such as register settings or programs

(1/20)

Page

Function

Details of

Function

Cautions

AVSS pin

Connect the AVSS pin to VSS.

p.16

configu-

ration

P121/X1 and

P122/X2 pins

The P121/X1 and P122/X2 pins are pulled down during reset.

No interrupt sources correspond to the vector table address 0014H.

pp.

functions

21, 22,

24, 25

Memory

space

Vector table

address

p.30

SP: Stack pointer Since generation of reset signal makes the SP contents undefined, be sure to p.34

initialize the SP before using the stack memory.

Stack pointers can be set only to the high-speed RAM area, and only the lower p.34

10 bits can be actually set. Thus, if the stack pointer is specified to 0FF00H, it

is converted to 0FB00H in the high-speed RAM area, since 0FF00H is in the

SFR area and not in the high-speed RAM area.

When the value is actually pushed onto the stack, 1 is subtracted from

0FB00H to become 0FAFFH, but since that value is not in the high-speed

RAM area, it is converted to 0FEFFH, which is the same value as when

0FF00H is set to the stack pointer.

Port

P121/X1 and

P122/X2 pins

The P121/X1 and P122/X2 pins are pulled down during reset.

p.53

functions

P34 pin

Because the P34 pin functions alternately as the RESET pin, if it is used as an p.59

input port pin, the function to input an external reset signal to the RESET pin

cannot be used. The function of the port is selected by the option byte. For

details, refer to CHAPTER 18 OPTION BYTE.

Also, since the option byte is referenced after the reset release, if low level is

input to the RESET pin before the referencing, then the reset state is not

released. When it is used as an input port pin, connect the pull-up resistor.

P30, P31, and

P43 pins

Because P30, P31, and P43 are also used as external interrupt pins, the

corresponding interrupt request flag is set if each of these pins is set to the

output mode and its output level is changed. To use the port pin in the output

mode, therefore, set the corresponding interrupt mask flag to 1 in advance.

p.67

PMC: Port mode When PMC20 to PMC23 are set to 1, the P20/ANI0 to P23/ANI3 pins cannot

control register 2 be used as port pins. Moreover, be sure to set the pull-up resistor option

registers (PU20 to PU23) to 0 for the pins set to A/D converter mode.

p.69

p.71

−

Although a 1-bit memory manipulation instruction manipulates 1 bit, it

accesses a port in 8-bit units. Therefore, the contents of the output latch of a

pin in the input mode, even if it is not subject to manipulation by the

instruction, are undefined in a port with a mixture of inputs and outputs.

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APPENDIX D LIST OF CAUTIONS

(2/20)

Page

Function

Details of

Function

Cautions

Main clock OSTS: Oscillation To set and then release the STOP mode, set the oscillation stabilization time

stabilization time as follows.

p.77

select register

Expected oscillation stabilization time of resonator ≤ Oscillation stabilization

time set by OSTS

The wait time after the STOP mode is released does not include the time from p.77

the release of the STOP mode to the start of clock oscillation (“a” in the figure

below), regardless of whether STOP mode was released by reset signal

generation or interrupt generation.

The oscillation stabilization time that elapses on power application or after

release of reset is selected by the option byte. For details, refer to CHAPTER

18 OPTION BYTE.

p.77

Crystal/

ceramic

oscillator

−

When using the crystal/ceramic oscillator, wire as follows in the area enclosed p.78

by the broken lines in Figure 5-6 to avoid an adverse effect from wiring

capacitance.

• Keep the wiring length as short as possible.

• Do not cross the wiring with the other signal lines. Do not route the wiring

near a signal line through which a high fluctuating current flows.

• Always make the ground point of the oscillator capacitor the same potential

as V^SS. Do not ground the capacitor to a ground pattern through which a

high current flows.

• Do not fetch signals from the oscillator.

16-bit

TM00: 16-bit

Even if TM00 is read, the value is not captured by CR010.

pp.

timer/event timer counter 00

counter 00

90, 122

pp.

When TM00 is read, count misses do not occur, since the input of the count

clock is temporarily stopped and then resumed after the read.

90, 122

pp.

CR000: 16-bit

timer capture/

Set CR000 to other than 0000H in the clear & start mode entered on match

between TM00 and CR000. This means a 1-pulse count operation cannot be

91, 122

compare register performed when this register is used as an external event counter.

000

In the free-running mode and in the clear & start mode using the valid edge of pp.

TI000 pin, if CR000 is set to 0000H, an interrupt request (INTTM000) is

91, 122

generated when CR000 changes from 0000H to 0001H following overflow

(FFFFH).

If the new value of CR000 is less than the value of 16-bit timer counter 0

(TM00), TM00 continues counting, overflows, and then starts counting from 0

again. If the new value of CR000 is less than the old value, therefore, the

timer must be reset to be restarted after the value of CR000 is changed.

pp.

91, 122

The value of CR000 after 16-bit timer/event counter 00 has stopped is not

guaranteed.

pp.

91, 123

The capture operation may not be performed for CR000 set in compare mode pp.

even if a capture trigger is input.

91, 126

pp.

91, 127

When using P31 as the input pin (TI010) of the valid edge, it cannot be used

as a timer output pin (TO00). When using P31 as the timer output pin (TO00),

it cannot be used as the input pin (TI010) of the valid edge.

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APPENDIX D LIST OF CAUTIONS

(3/20)

Page

Function

Details of

Function

Cautions

16-bit

CR000: 16-bit

If the register read period and the input of the capture trigger conflict when

CR000 is used as a capture register, the capture trigger input takes

pp.

91, 125

timer/event timer capture/

counter 00 compare register precedence and the read data is undefined. Also, if the count stop of the timer

000

and the input of the capture trigger conflict, the capture trigger is undefined.

Changing the CR000 setting during TM00 operation may cause a malfunction. p.92

To change the setting, refer to 6.5 Cautions Related to 16-bit Timer/Event

Counter 00 (17) Changing compare register during timer operation.

CR010: 16-bit

timer capture/

In the free-running mode and in the clear & start mode using the valid edge of pp.

the TI000 pin, if CR010 is set to 0000H, an interrupt request (INTTM010) is

92, 122

compare register generated when CR010 changes from 0000H to 0001H following overflow

010

(FFFFH).

If the new value of CR010 is less than the value of 16-bit timer counter 0

(TM00), TM00 continues counting, overflows, and then starts counting from 0

again. If the new value of CR010 is less than the old value, therefore, the

timer must be reset to be restarted after the value of CR010 is changed.

pp.

92, 122

The value of CR010 after 16-bit timer/event counter 00 has stopped is not

guaranteed.

pp.

92, 123

The capture operation may not be performed for CR010 set in compare mode pp.

even if a capture trigger is input.

92, 126

pp.

93, 125

If the register read period and the input of the capture trigger conflict when

CR010 is used as a capture register, the capture trigger input takes

precedence and the read data is undefined. Also, if the timer count stop and

the input of the capture trigger conflict, the capture data is undefined.

Changing the CR010 setting during TM00 operation may cause a malfunction. p.93

To change the setting, refer to 6.5 Cautions Related to 16-bit Timer/Event

Counter 00 (17) Changing compare register during timer operation.

TMC00: 16-bit

timer mode

control register

00

16-bit timer counter 00 (TM00) starts operation at the moment TMC002 and

TMC003 (operation stop mode) are set to a value other than 0, 0, respectively.

Set TMC002 and TMC003 to 0, 0 to stop the operation.

pp.

93, 122

The timer operation must be stopped before writing to bits other than the

OVF00 flag.

pp.

94, 123

If the timer is stopped, timer counts and timer interrupts do not occur, even if a pp.

signal is input to the TI000/TI010 pins.

94, 122

pp.

94, 127

Except when the valid edge of the TI000 pin is selected as the count clock,

stop the timer operation before setting STOP mode or system clock stop

mode; otherwise the timer may malfunction when the system clock starts.

Set the valid edge of the TI000 pin with bits 4 and 5 of prescaler mode register pp.

00 (PRM00) after stopping the timer operation.

94, 123

If the clear & start mode entered on a match between TM00 and CR000, clear p.94

& start mode at the valid edge of the TI000 pin, or free-running mode is

selected, when the set value of CR000 is FFFFH and the TM00 value changes

from FFFFH to 0000H, the OVF00 flag is set to 1.

Even if the OVF00 flag is cleared before the next count clock is counted

(before TM00 becomes 0001H) after the occurrence of a TM00 overflow, the

OVF00 flag is re-set newly and clear is disabled.

pp.

94, 124

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Function

Details of

Function

Cautions

16-bit

The capture operation is performed at the fall of the count clock. An interrupt

request input (INTTM0n0), however, occurs at the rise of the next count clock.

pp.

TMC00: 16-bit

timer mode control

register 00

timer/event

counter 00

94, 125

CRC00: Capture The timer operation must be stopped before setting CRC00.

pp.

/compare control

register 00

95, 123

When the clear & start mode entered on a match between TM00 and CR000 is pp.

selected by 16-bit timer mode control register 00 (TMC00), CR000 should not

be specified as a capture register.

95, 122

To ensure the reliability of the capture operation, the capture trigger requires a pp.

pulse longer than two cycles of the count clock selected by prescaler mode

95, 125

register 00 (PRM00) (refer to Figure 6-17).

TOC00: 16-bit

timer output

control register

00

The timer operation must be stopped before setting other than OSPT00.

pp.

96, 123

If LVS00 and LVR00 are read, 0 is read.

pp.

96, 123

pp.

OSPT00 is automatically cleared after data is set, so 0 is read.

Do not set OSPT00 to 1 other than in one-shot pulse output mode.

96, 123

pp.

96, 123

A write interval of two cycles or more of the count clock selected by prescaler pp.

mode register 00 (PRM00) is required, when OSPT00 is set to 1 successively.

96, 123

When TOE00 is 0, set TOE00, LVS00, and LVR00 at the same time with the

8-bit memory manipulation instruction. When TOE00 is 1, LVS00 and LVR00

can be set with the 1-bit memory manipulation instruction.

p.96

PRM00:

Always set data to PRM00 after stopping the timer operation.

pp.

Prescaler mode

register 00

98, 123

pp.

If the valid edge of the TI000 pin is to be set as the count clock, do not set the

clear/start mode and the capture trigger at the valid edge of the TI000 pin.

98, 125

pp.

In the following cases, note with caution that the valid edge of the TI0n0 pin is

detected.

98, 127

<1> Immediately after a system reset, if a high level is input to the TI0n0 pin,

the operation of the 16-bit timer counter 00 (TM00) is enabled

→ If the rising edge or both rising and falling edges are specified as the

valid edge of the TI0n0 pin, a rising edge is detected immediately after

the TM00 operation is enabled.

<2> If the TM00 operation is stopped while the TI0n0 pin is high level, TM00

operation is then enabled after a low level is input to the TI0n0 pin

→ If the falling edge or both rising and falling edges are specified as the

valid edge of the TI0n0 pin, a falling edge is detected immediately after

the TM00 operation is enabled.

<3> If the TM00 operation is stopped while the TI0n0 pin is low level, TM00

operation is then enabled after a high level is input to the TI0n0 pin

→ If the rising edge or both rising and falling edges are specified as the

valid edge of the TI0n0 pin, a rising edge is detected immediately after

the TM00 operation is enabled.

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Cautions

16-bit

PRM00:

The sampling clock used to eliminate noise differs when a TI000 valid edge is pp.

used as the count clock and when it is used as a capture trigger. In the former

timer/event Prescaler mode

counter 00 register 00

98, 127

case, the count clock is fXP, and in the latter case the count clock is selected

by prescaler mode register 00 (PRM00). The capture operation is not

performed until the valid edge is sampled and the valid level is detected twice,

thus eliminating noise with a short pulse width.

When using P31 as the input pin (TI010) of the valid edge, it cannot be used

as a timer output pin (TO00). When using P31 as the timer output pin (TO00),

it cannot be used as the input pin (TI010) of the valid edge.

pp.

98, 127

Interval timer

Changing the CR000 setting during TM00 operation may cause a malfunction. p.99

To change the setting, refer to 6.5 Cautions Related to 16-bit Timer/Event

Counter 00 (17) Changing compare register during timer operation.

External event

counter

When reading the external event counter count value, TM00 should be read.

pp.

103, 127

pp.

To use two capture registers, set the TI000 and TI010 pins.

Pulse width

measurement

104, 125

pp.

The measurable pulse width in this operation example is up to 1 cycle of the

timer counter.

105, 107,

108, 110

Square-wave

output

Changing the CR000 setting during TM00 operation may cause a malfunction. p.112

To change the setting, refer to 6.5 Cautions Related to 16-bit Timer/Event

Counter 00 (17) Changing compare register during timer operation.

PPG output

Changing the CRC0n0 setting during TM00 operation may cause a

malfunction. To change the setting, refer to 6.5 Cautions Related to 16-bit

Timer/Event Counter 00 (17) Changing compare register during timer

operation.

p.114

Values in the following range should be set in CR000 and CR010.

pp.

0000H < CR010 < CR000 ≤ FFFFH

115, 127

The cycle of the pulse generated through PPG output (CR000 setting value + pp.

1) has a duty of (CR010 setting value + 1)/(CR000 setting value + 1).

115, 127

One-shot pulse

output by

Do not set the OSPT00 bit to 1 again while the one-shot pulse is being output. pp.

To output the one-shot pulse again, wait until the current one-shot pulse

117, 123

software

output is completed.

When using the one-shot pulse output of 16-bit timer/event counter 00 with a

software trigger, do not change the level of the TI000 pin or its alternate-

function port pin.

pp.

117, 123

Because the external trigger is valid even in this case, the timer is cleared and

started even at the level of the TI000 pin or its alternate-function port pin,

resulting in the output of a pulse at an undesired timing.

Do not set 0000H to the CR000 and CR010 registers.

pp.

118, 123

pp.

16-bit timer counter 00 starts operating as soon as a value other than 00

(operation stop mode) is set to the TMC003 and TMC002 bits.

119, 122

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Function

Details of

Function

Cautions

16-bit

One-shot pulse

Do not input the external trigger again while the one-shot pulse is being

output. To output the one-shot pulse again, wait until the current one-shot

pulse output is completed.

pp.

timer/event output with

119, 124

counter 00 external trigger

Do not set 0000H to the CR000 and CR010 registers.

pp.

120, 124

pp.

16-bit timer counter 00 starts operating as soon as a value other than 00

(operation stop mode) is set to the TMC003 and TMC002 bits.

121, 122

Timer start errors An error of up to one clock may occur in the time required for a match signal to p.122

be generated after timer start. This is because 16-bit timer counter 00 (TM00)

is started asynchronously to the count clock.

One-shot pulse

output

One-shot pulse output normally operates only in the free-running mode or in

the clear & start mode at the valid edge of the TI000 pin. Because an overflow

does not occur in the clear & start mode on a match between TM00 and

CR000, one-shot pulse output is not possible.

p.123

Capture

If both the rising and falling edges are selected as the valid edges of the TI000 p.125

pin, capture is not performed.

operation

When the CRC001 bit value is 1, the TM00 count value is not captured in the

CR000 register when a valid edge of the TI010 pin is detected, but the input

from the TI010 pin can be used as an external interrupt source because

INTTM000 is generated at that timing.

p.125

Changing

With the 16-bit timer capture/compare register 0n0 (CR0n0) used as a

p.126

compare register compare register, when changing CR0n0 around the timing of a match

during timer

operation

between 16-bit timer counter 00 (TM00) and 16-bit timer capture/compare

register 0n0 (CR0n0) during timer counting, the change timing may conflict

with the timing of the match, so the operation is not guaranteed in such cases.

To change CR0n0 during timer counting, follow the procedure below using an

INTTM000 interrupt.

If CR010 is changed during timer counting without performing processing <1> p.126

above, the value in CR010 may be rewritten twice or more, causing an

inversion of the output level of the TO00 pin at each rewrite.

External event

counter

The timing of the count start is after two valid edge detections.

p.127

External clock

limitation

When using an input pulse of the TI000 pin as a count clock (external trigger), p.128

be sure to input the pulse width which satisfies the AC characteristics. For the

AC characteristics, refer to CHAPTER 22 and CHAPTER 23 ELECTRICAL

SPECIFICATIONS.

When an external waveform is input to 16-bit timer/event counter 00, it is

sampled by the noise limiter circuit and thus an error occurs on the timing to

become valid inside the device.

p.128

8-bit timer

80

CR80: 8-bit

When changing the value of CR80, be sure to stop the timer operation. If the p.131

compare register value of CR80 is changed with the timer operation enabled, a match interrupt

80

request signal is generated immediately and the timer may be cleared.

TMC80: 8-bit

timer mode

control register

80

Be sure to set TMC80 after stopping the timer operation.

p.132

Be sure to clear bits 0 and 6 to 0.

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Function

Details of

Function

Cautions

8-bit timer

80

Interval timer

When changing the value of CR80, be sure to stop the timer operation. If the p.133

value of CR80 is changed with the timer operation enabled, a match interrupt

request signal may be generated immediately.

If the count clock of TMC80 is set and the operation of TM80 is enabled at the p.133

same time by using an 8-bit memory manipulation instruction, the error of one

cycle after the timer is started may be 1 clock or more. Therefore, be sure to

follow the above sequence when using TM80 as an interval timer.

Error when timer The time from starting the timer to generation of the match signal includes an

p.135

starts

error of up to 1.5 clocks. This is because, if the timer is started while the count

clock is high, the rising edge may be immediately detected and the counter

may be incremented (refer to Figure 7-6).

CR80: 8-bit

compare register

80

8-bit compare register 80 (CR80) can be set to 00H.

p.135

STOP mode

Before executing the STOP instruction, be sure to stop the timer operation

(TCE80 = 0).

p.135

p.138

8-bit timer

H1

CMP01: 8-bit

timer H compare

register 01

CMP01 cannot be rewritten during timer count operation.

CMP11: 8-bit

In the PWM output mode, be sure to set CMP11 when starting the timer count p.138

timer H compare operation (TMHE1 = 1) after the timer count operation was stopped (TMHE1 =

register 11

0) (be sure to set again even if setting the same value to CMP11).

TMHMD1: 8-bit

timer H mode

register 1

When TMHE1 = 1, setting the other bits of the TMHMD1 register is prohibited. p.140

In the PWM output mode, be sure to set 8-bit timer H compare register 11

(CMP11) when starting the timer count operation (TMHE1 = 1) after the timer

count operation was stopped (TMHE1 = 0) (be sure to set again even if setting

the same value to the CMP11 register).

p.140

PWM output

In PWM output mode, the setting value for the CMP11 register can be

changed during timer count operation. However, three operation clocks

(signal selected using the CKS12 to CKS10 bits of the TMHMD1 register) or

more are required to transfer the register value after rewriting the CMP11

register value.

p.146

Be sure to set the CMP11 register when starting the timer count operation

(TMHE1 = 1) after the timer count operation was stopped (TMHE1 = 0) (be

sure to set again even if setting the same value to the CMP11 register).

p.146

p.147

Make sure that the CMP11 register setting value (M) and CMP01 register

setting value (N) are within the following range.

00H ≤ CMP11 (M) < CMP01 (N) ≤ FFH

Watchdog

timer

WDTM:

Set bits 7, 6, and 5 to 0, 1, and 1, respectively. Do not set the other values.

p.155

Watchdog timer

mode register

After reset is released, WDTM can be written only once by an 8-bit memory

manipulation instruction. If writing is attempted a second time, an internal

reset signal is generated. However, at the first write, if “1” and “x” are set for

WDCS4 and WDCS3 respectively and the watchdog timer is stopped, then the

internal reset signal does not occur even if the following are executed.

• Second write to WDTM

• 1-bit memory manipulation instruction to WDTE

• Writing of a value other than “ACH” to WDTE

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Function

Cautions

Watchdog

timer

WDTM:

WDTM cannot be set by a 1-bit memory manipulation instruction.

p.155

Watchdog timer

mode register

When using the flash memory programming by self programming, set the

overflow time for the watchdog timer so that enough overflow time is secured

(Example 1-byte writing: 200 μs MIN., 1-block deletion: 10 ms MIN.).

p.155

WDTE:

If a value other than ACH is written to WDTE, an internal reset signal is

generated.

p.155

Watchdog timer

enable register

If a 1-bit memory manipulation instruction is executed for WDTE, an internal

reset signal is generated.

The value read from WDTE is 9AH (this differs from the written value (ACH)). p.155

When “low-speed In this mode, operation of the watchdog timer cannot be stopped even during

internal oscillator STOP instruction execution. For 8-bit timer H1 (TMH1), a division of the low-

p.156

cannot be

stopped” is

selected by

option byte

speed internal oscillation clock can be selected as the count source, so clear

the watchdog timer using the interrupt request of TMH1 before the watchdog

timer overflows after STOP instruction execution. If this processing is not

performed, an internal reset signal is generated when the watchdog timer

overflows after STOP instruction execution.

When “low-speed In this mode, watchdog timer operation is stopped during HALT/STOP

internal oscillator instruction execution. After HALT/STOP mode is released, counting is started

p.158

can be stopped

by software” is

selected by

again using the operation clock of the watchdog timer set before HALT/STOP

instruction execution by WDTM. At this time, the counter is not cleared to 0

but holds its value.

option byte

A/D

Sampling time

and conversion

time

The above sampling time and conversion time do not include the clock

frequency error. Select the sampling time and conversion time such that

Notes 2 and 3 above are satisfied, while taking the clock frequency error into

consideration (an error margin maximum of ±5% when using the high-speed

internal oscillator).

p.164

p.169

p.170

converter

ADM: A/D

The above sampling time and conversion time do not include the clock

frequency error. Select the sampling time and conversion time such that

Notes 3 and 4 above are satisfied, while taking the clock frequency error into

consideration (an error margin maximum of ±5% when using the high-speed

internal oscillator).

converter mode

register

If a bit other than ADCS of ADM is manipulated while A/D conversion is

stopped (ADCS = 0) and then A/D conversion is started, execute two NOP

instructions or an instruction equivalent to two machine cycles, and set ADCS

to 1.

A/D conversion must be stopped (ADCS = 0) before rewriting bits FR0 to FR2. p.170

Be sure to clear bits 6, 2, and 1 to 0.

Be sure to clear bits 2 to 7 of ADS to 0.

p.170

ADS: Analog

input channel

specification

register

ADCR: 10-bit A/D When writing to the A/D converter mode register (ADM) and analog input

conversion result channel specification register (ADS), the contents of ADCR may become

p.170

register

undefined. Read the conversion result following conversion completion before

writing to ADM and ADS. Using timing other than the above may cause an

incorrect conversion result to be read.

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Cautions

A/D

converter

PMC2: Port

mode control

register 2

When PMC20 to PMC23 are set to 1, the P20/ANI0 to P23/ANI3 pins cannot

be used as port pins. Be sure to set the pull-up resistor option registers (PU20

to PU23) to 0 for the pins set to A/D converter mode.

p.171

A/D converter

operations

Make sure the period of <1> to <4> is 1 μs or more.

pp.

172, 176

pp.

It is no problem if the order of <1> and <2> is reversed.

172, 176

p.176

<1> can be omitted. However, ignore the data resulting from the first

conversion after <4> in this case.

The period from <5> to <8> differs from the conversion time set using bits 5 to p.176

3 (FR2 to FR0) of ADM. The period from <7> to <8> is the conversion time

set using FR2 to FR0.

Operating current To satisfy the DC characteristics of the supply current in the STOP mode,

p.179

in STOP mode

clear bit 7 (ADCS) and bit 0 (ADCE) of the A/D converter mode register (ADM)

to 0 before executing the STOP instruction.

Input range of

ANI0 to ANI3

Observe the rated range of the ANI0 to ANI3 input voltage. If a voltage of

AV^REFor higher and AVSS or lower (even in the range of absolute maximum

ratings) is input to an analog input channel, the converted value of that

channel becomes undefined. In addition, the converted values of the other

channels may also be affected.

p.179

Conflicting

operations

ADCR, ADCRH read has priority. After the read operation, the new

conversion result is written to ADCR, ADCRH.

p.179

ADM or ADS write has priority. ADCR, ADCRH write is not performed, nor is

the conversion end interrupt signal (INTAD) generated.

Noise

To maintain the 10-bit resolution, attention must be paid to noise input to the

countermeasures AV^REFpin and pins ANI0 to ANI3.

<1> Connect a capacitor with a low equivalent resistance and a high

frequency response to the power supply.

<2> Because the effect increases in proportion to the output impedance of the

analog input source, it is recommended that a capacitor be connected

externally, as shown in Figure 10-19, to reduce noise.

<3> Do not switch the A/D conversion function of the ANI0 to ANI3 pins to

their alternate functions during conversion.

<4> The conversion accuracy can be improved by setting HALT mode

immediately after the conversion starts.

ANI0/P20 to

ANI3/P23

The analog input pins (ANI0 to ANI3) are also used as input port pins (P20 to

P23).

p.180

When A/D conversion is performed with any of ANI0 to ANI3 selected, do not

access port 2 (P20 to P23) while conversion is in progress; otherwise the

conversion resolution may be degraded.

If a digital pulse is applied to the pins adjacent to the pins currently used for

A/D conversion, the expected value of the A/D conversion may not be

obtained due to coupling noise. Therefore, do not apply a pulse to the pins

adjacent to the pin undergoing A/D conversion.

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Function

Cautions

A/D

Input impedance In this A/D converter, the internal sampling capacitor is charged and sampling p.180

converter

of ANI0 to ANI3

pins

is performed during sampling time.

Since only the leakage current flows other than during sampling and the

current for charging the capacitor also flows during sampling, the input

impedance fluctuates both during sampling and otherwise.

If the shortest conversion time of the reference voltage is used, to perform

sufficient sampling, it is recommended to make the output impedance of the

analog input source 1 kΩ or lower, or attach a capacitor of around 0.01 μ F to

0.1 μ F to the ANI0 to ANI3 pins (see Figure 10-19).

ADIF: Interrupt

request flag

The interrupt request flag (ADIF) is not cleared even if the analog input

channel specification register (ADS) is changed.

p.180

Therefore, if an analog input pin is changed during A/D conversion, the A/D

conversion result and ADIF for the pre-change analog input may be set just

before the ADS rewrite. Caution is therefore required since, at this time, when

ADIF is read immediately after the ADS rewrite, ADIF is set despite the fact

A/D conversion for the post-change analog input has not ended.

When A/D conversion is stopped and then resumed, clear ADIF before the

A/D conversion operation is resumed.

Conversion

results just after

A/D conversion

start

The first A/D conversion value immediately after A/D conversion starts may

not fall within the rating range if the ADCS bit is set to 1 within 1 μs after the

ADCE bit was set to 1, or if the ADCS bit is set to 1 with the ADCE bit = 0.

Take measures such as polling the A/D conversion end interrupt request

(INTAD) and removing the first conversion result.

p.181

A/D conversion

result register

When a write operation is performed to the A/D converter mode register

(ADM) and analog input channel specification register (ADS), the contents of

(ADCR, ADCRH) ADCR and ADCRH may become undefined. Read the conversion result

read operation

following conversion completion before writing to ADM and ADS. Using a

timing other than the above may cause an incorrect conversion result to be

read.

Operating current The DC characteristic of the operating current during the STOP mode is not

p.181

at conversion

waiting mode

satisfied due to the conversion waiting mode (only the comparator consumes

power), when bit 7 (ADCS) and bit 0 (ADCE) of the A/D converter mode

register (ADM) are set to 0 and 1 respectively.

UART mode

The TXD6 output inversion function inverts only the transmission side and not p.182

the reception side. To use this function, the reception side must be ready for

reception of inverted data.

Serial

interface

UART6

If clock supply to serial interface UART6 is not stopped (e.g., in the HALT

mode), normal operation continues. If clock supply to serial interface UART6

is stopped (e.g., in the STOP mode), each register stops operating, and holds

the value immediately before clock supply was stopped. The TxD6 pin also

holds the value immediately before clock supply was stopped and outputs it.

However, the operation is not guaranteed after clock supply is resumed.

Therefore, reset the circuit so that POWER6 = 0, RXE6 = 0, and TXE6 = 0.

p.182

If data is continuously transmitted, the communication timing from the stop bit p.182

to the next start bit is extended two operating clocks of the macro. However,

this does not affect the result of communication because the reception side

initializes the timing when it has detected a start bit. Do not use the

continuous transmission function if the interface used in LIN communication

operation.

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Function

Cautions

RXB6: Receive

buffer register 6

Reception enable status is entered, after having set RXE6 to 1 and one clock p.188

of the base clock (f^XCLK6) has elapsed.

Serial

interface

UART6

TXB6: Transmit

buffer register 6

When starting transmission, write transmit data to TXB6, after having set TXE6 p.188

to 1 and a wait of one clock or more of the base clock (f^XCLK6) has been

performed.

p.188

Do not write data to TXB6 when bit 1 (TXBF6) of asynchronous serial interface

transmission status register 6 (ASIF6) is 1.

p.188

Do not refresh (write the same value to) TXB6 by software during a

communication operation (when bit 7 (POWER6) and bit 6 (TXE6) of

asynchronous serial interface operation mode register 6 (ASIM6) are 1 or

when bit 7 (POWER6) and bit 5 (RXE6) of ASIM6 are 1). When outputting

same values in continuous transmission, be sure to confirm that TXBF6 is 0

before writing the same values to TXB6.

ASIM6:

At startup, transmission operation is started by setting TXE6 to 1 after having

set POWER6 to 1, then setting the transmit data to TXB6 after having waited

for one clock or more of the base clock (f^XCLK6). When stopping transmission

operation, set POWER6 to 0 after having set TXE6 to 0.

p.190

p.191

Asynchronous

serial interface

operation mode

register 6

At startup, reception enable status is entered after having set POWER6 to 1,

then setting RXE6 to 1, and one clock of the base clock (f^XCLK6) has elapsed.

When stopping reception operation, set POWER6 to 0 after having set RXE6

to 0.

Set POWER6 = 1 → RXE6 = 1 in a state where a high level has been input to p.191

the RxD6 pin. If POWER6 = 1 → RXE6 = 1 is set during low-level input,

reception is started and correct data will not be received.

Clear the TXE6 and RXE6 bits to 0 before rewriting the PS61, PS60, and CL6 p.191

bits.

Fix the PS61 and PS60 bits to 0 when the interface is used in LIN

communication operation.

p.191

Make sure that TXE6 = 0 when rewriting the SL6 bit. Reception is always

performed with “the number of stop bits = 1”, and therefore, is not affected by

the set value of the SL6 bit.

p.191

Make sure that RXE6 = 0 when rewriting the ISRM6 bit.

p.191

ASIS6:

The operation of the PE6 bit differs depending on the set values of the PS61

and PS60 bits of asynchronous serial interface operation mode register 6

(ASIM6).

Asynchronous

serial interface

reception error

status register 6

The first bit of the receive data is checked as the stop bit, regardless of the

number of stop bits.

p.191

If an overrun error occurs, the next receive data is not written to receive buffer p.191

register 6 (RXB6) but discarded.

Be sure to read ASIS6 before reading receive buffer register 6 (RXB6).

pp.

191, 209

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Cautions

Serial

ASIF6:

To transmit data continuously, write the first transmit data (first byte) to the

TXB6 register. Be sure to check that the TXBF6 flag is “0”. If so, write the

next transmit data (second byte) to the TXB6 register. If data is written to the

TXB6 register while the TXBF6 flag is “1”, the transmit data cannot be

guaranteed.

p.192

interface

UART6

Asynchronous

serial interface

transmission

status register 6

To initialize the transmission unit upon completion of continuous transmission, p.192

be sure to check that the TXSF6 flag is “0” after generation of the transmission

completion interrupt, and then execute initialization. If initialization is executed

while the TXSF6 flag is “1”, the transmit data cannot be guaranteed.

CKSR6:

Make sure POWER6 = 0 when rewriting TPS63 to TPS60.

p.193

Clock selection

register 6

BRGC6: Baud

rate generator

control register 6

Make sure that bit 6 (TXE6) and bit 5 (RXE6) of the ASIM6 register = 0 when

rewriting the MDL67 to MDL60 bits.

p.194

p.195

The baud rate is the output clock of the 8-bit counter divided by 2.

ASICL6:

ASICL6 can be refreshed (the same value is written) by software during a

communication operation (when bit 7 (POWER6) and bit 6 (TXE6) of ASIM6

are 1 or when bit 7 (POWER6) and bit 5 (RXE6) of ASIM6 are 1), if 0 data has

Asynchronous

serial interface

control register 6 been written to ASICL6 by SBRT6 and SBTT6.

In the case of an SBF reception error, return to SBF reception mode again.

p.196

The status of the SBRF6 flag will be held (1). For details on SBF reception

refer to (2) – (i) SBF reception in 11.4.2 Asynchronous serial interface (UART)

mode described later.

Before setting the SBRT6 bit to 1, make sure that bit 7 (POWER6) and bit 5

(RXE6) of ASIM6 = 1. Moreover, after setting the SBRT6 bit to 1, do not clear

the SBRT6 bit to 0 before the SBF reception ends (an interrupt request signal

is generated).

The read value of the SBRT6 bit is always 0. SBRT6 is automatically cleared p.196

to 0 after SBF reception has been correctly completed.

Before setting the SBTT6 bit to 1, make sure that bit 7 (POWER6) and bit 6

(TXE6) of ASIM6 = 1. Moreover, after setting the SBTT6 bit to 1, do not clear

the SBTT6 bit to 0 before the SBF transmission ends (an interrupt request

signal is generated).

p.196

The read value of the SBTT6 bit is always 0. SBTT6 is automatically cleared

to 0 at the end of SBF transmission.

p.196

p.198

Before rewriting the DIR6 and TXDLV6 bits, clear the TXE6 and RXE6 bits to

0.

Bits 7, 6, and 5

(POWER6,

Clear POWER6 to 0 after clearing TXE6 and RXE6 to 0 to set the operation

stop mode.

TXE6, and

To start the operation, set POWER6 to 1, and then set TXE6 and RXE6 to 1.

RXE6) of ASIM6

401

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APPENDIX D LIST OF CAUTIONS

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Page

Function

Details of

Function

Cautions

Serial

UART mode

Take the relationship with the other party of communication into consideration

when setting the port mode register and port register. In order to avoid the

generation of unintended start bits (falling signals), set PM43 to 0 (output) after

having set P43 to 1.

p.199

interface

UART6

Parity types and

operation

Fix the PS61 and PS60 bits to 0 when the interface is used in LIN

communication operation.

p.203

p.205

Continuous

Use the value of the TXBF6 flag to judge whether continuous transmission is

possible. Do not write the next transmit data, by making a judgment only by

the fact that the TXSF6 flag has been set to 1.

transmission

When the interface is used in LIN communication operation, the continuous

transmission function cannot be used. Make sure that asynchronous serial

interface transmission status register 6 (ASIF6) is 00H before writing transmit

data to transmit buffer register 6 (TXB6).

p.205

TXBF6 during

continuous

To transmit data continuously, write the first transmit data (first byte) to the

TXB6 register. Be sure to check that the TXBF6 flag is “0”. If so, write the

next transmit data (second byte) to the TXB6 register. If data is written to the

TXB6 register while the TXBF6 flag is “1”, the transmit data cannot be

guaranteed.

transmission: Bit

1 of ASIF6

TXSF6 during

continuous

To initialize the transmission unit upon completion of continuous transmission,

be sure to check that the TXSF6 flag is “0” after generation of the transmission

completion interrupt, and then execute initialization. If initialization is executed

while the TXSF6 flag is “1”, the transmit data cannot be guaranteed.

p.205

p.209

transmission: Bit

0 of ASIF6

Normal reception Be sure to read receive buffer register 6 (RXB6) even if a reception error

occurs. Otherwise, an overrun error will occur when the next data is received,

and the reception error status will persist.

p.209

p.215

p.217

Reception is always performed with the “number of stop bits = 1”. The second

stop bit is ignored.

Be sure to read asynchronous serial interface reception error status register 6

(ASIS6) before reading RXB6.

Generation of

serial clock

Keep the baud rate error during transmission to within the permissible error

range at the reception destination.

Make sure that the baud rate error during reception satisfies the range shown

in (4) Permissible baud rate range during reception.

Permissible baud Make sure that the baud rate error during reception is within the permissible

rate range during error range, by using the calculation expression shown below.

reception

p.220

p.222

Multiplier

MUL0: 16-bit

multiplication

result storage

register 0

Although this register is manipulated with a 16-bit memory manipulation

instruction, it can be also manipulated with an 8-bit memory manipulation

instruction. When using an 8-bit memory manipulation instruction, however,

access the register by means of direct addressing.

MULC0: control

register 0

Be sure to clear bits 1 to 7 to 0.

402

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APPENDIX D LIST OF CAUTIONS

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Page

Function

Details of

Function

Cautions

Interrupt

function

Vector table

address

No interrupt sources correspond to the vector table address 0014H.

p.226

IF0, IF1: Interrupt Because P30, P31, P41, and P43 have an alternate function as external

pp.

request flag

interrupt inputs, when the output level is changed by specifying the output

mode of the port function, an interrupt request flag is set. Therefore, the

interrupt mask flag should be set to 1 before using the output mode.

229, 230

registers 0, 1

MK0, MK1:

Interrupt mask

flag registers 0, 1

INTM0: External

interrupt mode

register 0

Be sure to clear bits 0 and 1 to 0.

p.231

Before setting the INTM0 register, be sure to set the corresponding interrupt

mask flag (××MK× = 1) to disable interrupts. After setting the INTM0 register,

clear the interrupt request flag (××IF× = 0), then clear the interrupt mask flag

(××MK× = 0), which will enable interrupts.

INTM1: External

interrupt mode

register 1

Be sure to clear bits 2 to 7 to 0.

p.232

Before setting INTM1, set PMK3 to 1 to disable interrupts.

To enable interrupts, clear PIF3 to 0, then clear PMK3 to 0.

Interrupt request

pending

Interrupt requests will be held pending while the interrupt request flag registers p.235

0, 1 (IF0, IF1) or interrupt mask flag registers 0, 1 (MK0, MK1) are being

accessed.

Multiple interrupt Multiple interrupts can be acknowledged even for low-priority interrupts.

servicing

p.236

p.238

p.239

Standby

function

−

The LSRSTOP setting is valid only when “Can be stopped by software” is set

for the low-speed internal oscillator by the option byte.

STOP mode

When shifting to the STOP mode, be sure to stop the peripheral hardware

operation before executing STOP instruction (except the peripheral hardware

that operates on the low-speed internal oscillation clock).

STOP mode,

HALT mode

The following sequence is recommended for operating current reduction of the p.239

A/D converter when the standby function is used: First clear bit 7 (ADCS) and

bit 0 (ADCE) of the A/D converter mode register (ADM) to 0 to stop the A/D

conversion operation, and then execute the HALT or STOP instruction.

STOP mode

If the low-speed internal oscillator is operating before the STOP mode is set,

oscillation of the low-speed internal oscillation clock cannot be stopped in the

STOP mode (refer to Table 14-1).

p.239

OSTS:

To set and then release the STOP mode, set the oscillation stabilization time

as follows.

p.240

Oscillation

stabilization time Expected oscillation stabilization time of resonator ≤ Oscillation stabilization

select register time set by OSTS

The wait time after the STOP mode is released does not include the time from p.240

the release of the STOP mode to the start of clock oscillation (“a” in the figure

below), regardless of whether STOP mode was released by reset signal

generation or interrupt generation.

The oscillation stabilization time that elapses on power application or after

release of reset is selected by the option byte. For details, refer to CHAPTER

18 OPTION BYTE.

p.240

403

User’s Manual U17446EJ5V0UD

APPENDIX D LIST OF CAUTIONS

(15/20)

Page

Function

Details of

Function

Cautions

Standby

function

Settings and

operating

Because an interrupt request signal is used to clear the standby mode, if there p.241

is an interrupt source with the interrupt request flag set and the interrupt mask

statuses in HALT flag reset, the standby mode is immediately cleared if set.

mode

Settings and

operating

Because an interrupt request signal is used to clear the standby mode, if there p.244

is an interrupt source with the interrupt request flag set and the interrupt mask

statuses in STOP flag reset, the standby mode is immediately cleared if set. Thus, in the STOP

mode

mode, the normal operation mode is restored after the STOP instruction is

executed and then the operation is stopped for 34 μs (TYP.) (after an

additional wait time for stabilizing the oscillation set by the oscillation

stabilization time select register (OSTS) has elapsed when crystal/ceramic

oscillation is used).

Reset

−

For an external reset, input a low level for 2 μs or more to the RESET pin.

p.248

function

During reset signal generation, the system clock and low-speed internal

oscillation clock stop oscillating.

When the RESET pin is used as an input-only port pin (P34), the 78K0S/KB1+ p.248

is reset if a low level is input to the RESET pin after reset is released by the

POC circuit, the LVI circuit and the watchdog timer and before the option byte

is referenced again. The reset status is retained until a high level is input to

the RESET pin.

The LVI circuit is not reset by the internal reset signal of the LVI circuit.

p.249

p.251

Timing of reset

by overflow of

watchdog timer

The watchdog timer is also reset in the case of an internal reset of the

watchdog timer.

RESF: Reset

control flag

register

Do not read data by a 1-bit memory manipulation instruction.

p.255

Power-on-

Functions of

If an internal reset signal is generated in the POC circuit, the reset control flag p.256

register (RESF) is cleared to 00H.

clear circuit power-on-clear

circuit

Use these products in the following voltage range because the detection

voltage (V^POC) of the POC circuit is the supply voltage range.

Standard product, (A) grade product: 2.2 to 5.5 V, (A2) grade product: 2.26 to

5.5 V

p.256

Cautions for

power-on-clear

circuit

In a system where the supply voltage (VDD) fluctuates for a certain period in

the vicinity of the POC detection voltage (VPOC), the system may be

repeatedly reset and released from the reset status. In this case, the time

from release of reset to the start of the operation of the microcontroller can be

arbitrarily set by taking the following action.

p.258

Low-

LVIM: Low-

voltage detect

register

To stop LVI, follow either of the procedures below.

p.261

voltage

detector

• When using 8-bit manipulation instruction: Write 00H to LVIM.

• When using 1-bit memory manipulation instruction: Clear LVION to 0.

Be sure to set bits 2 to 6 to 0.

Bits 4 to 7 must be set to 0.

p.261

p.262

LVIS: Low-

voltage detection

level select

register

If values other than same values are written during LVI operation, the value

becomes undefined at the very moment it is written, and thus be sure to stop

LVI (bit 7 of LVIM register (LVION) = 0) before writing.

404

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APPENDIX D LIST OF CAUTIONS

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Page

Function

Details of

Function

Cautions

Low-

When used as

reset

<1> must always be executed. When LVIMK = 0, an interrupt may occur

immediately after the processing in <3>.

p.263

p.266

voltage

detector

If supply voltage (VDD) ≥ detection voltage (VLVI) when LVIM is set to 1, an

internal reset signal is not generated.

Cautions for low- In a system where the supply voltage (VDD) fluctuates for a certain period in

voltage detector

the vicinity of the LVI detection voltage (VLVI), the operation is as follows

depending on how the low-voltage detector is used.

<1> When used as reset

The system may be repeatedly reset and released from the reset status.

In this case, the time from release of reset to the start of the operation of the

microcontroller can be arbitrarily set by taking action (1) below.

<2> When used as interrupt

Interrupt requests may be frequently generated. Take action (2) below.

Option byte Oscillation

The setting of this option is valid only when the crystal/ceramic oscillation clock p.270

stabilization time is selected as the system clock source. No wait time elapses if the high-speed

on power

application or

after reset

release

internal oscillation clock or external clock input is selected as the system clock

source.

Control of

Because the option byte is referenced after reset release, if a low level is input p.270

to the RESET pin before the option byte is referenced, then the reset state is

not released.

RESET pin

Also, when setting 0 to RMCE, connect the pull-up resistor.

Selection of

system clock

source

Because the X1 and X2 pins are also used as the P121 and P122 pins, the

conditions under which the X1 and X2 pins can be used differ depending on

the selected system clock source.

p.270

(1) Crystal/ceramic oscillation clock is selected

The X1 and X2 pins cannot be used as I/O port pins because they are used

as clock input pins.

(2) External clock input is selected

Because the X1 pin is used as an external clock input pin, P121 cannot be

used as an I/O port pin.

(3) High-speed internal oscillation clock is selected

P121 and P122 can be used as I/O port pins.

Low-speed

If it is selected that low-speed internal oscillator cannot be stopped, the count p.271

internal oscillates clock to the watchdog timer (WDT) is fixed to low-speed internal oscillation

clock.

If it is selected that low-speed internal oscillator can be stopped by software,

supply of the count clock to WDT is stopped in the HALT/STOP mode,

regardless of the setting of bit 0 (LSRSTOP) of the low-speed internal

oscillation mode register (LSRCM). Similarly, clock supply is also stopped

when a clock other than the low-speed internal oscillation clock is selected as

a count clock to WDT.

p.271

While the low-speed internal oscillator is operating (LSRSTOP = 0), the clock

can be supplied to the 8-bit timer H1 even in the STOP mode.

405

User’s Manual U17446EJ5V0UD

APPENDIX D LIST OF CAUTIONS

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Page

Function

Details of

Function

Cautions

Option byte Use of RESET

pin as an input-

only port pin

Be aware of the following when re-erasing/-writing (by on-board programming p.271

using a dedicated flash memory programmer) an already-written device which

has been set as “The RESET pin is used as an input-only port pin (P34)” by

the option byte function.

(P34)

Before supplying power to the target system, connect a dedicated flash

memory programmer and turn its power on. If the power is supplied to the

target system beforehand, the flash memory programming mode cannot be

switched to.

Flash

PG-FP5 GUI

The above values are recommended values. Depending on the usage

environment these values may change, so set them after having performed

sufficient evaluations.

p.278

p.281

memory

Software setting

value example

Security settings After the security setting of the batch erase is set, erasure cannot be

performed for the device. In addition, even if a write command is executed,

data different from that which has already been written to the flash memory

cannot be written because the erase command is disabled.

Self

Self programming processing must be included in the program before

performing self programming.

p.282

programming

function

No instructions can be executed while a self programming command is being p.285

executed. Therefore, clear and restart the watchdog timer counter in advance

so that the watchdog timer does not overflow during self programming. Refer

to Table 19-10 for the time taken for the execution of self programming.

Interrupts that occur during self programming can be acknowledged after self p.285

programming mode ends. To avoid this operation, disable interrupt servicing

(by setting MK0 and MK1 to FFH, and executing the DI instruction) before a

mode is shifted from the normal mode to the self programming mode with a

specific sequence.

RAM is not used while a self programming command is being executed.

p.285

If the supply voltage drops or the reset signal is input while the flash memory

is being written or erased, writing/erasing is not guaranteed.

The value of the blank data set during block erasure is FFH.

p.285

Set the CPU clock beforehand so that it is 1 MHz or higher during self

programming.

Execute self programming after executing the NOP and HALT instructions

immediately after executing a specific sequence to set self programming

mode. At this time, the HALT instruction is automatically released after 10 μs

(MAX.) + 2 CPU clocks (f^CPU).

p.285

If the clock of the oscillator or an external clock is selected as the system

clock, execute the NOP and HALT instructions immediately after executing a

specific sequence to set self programming mode, wait for 8 μs after releasing

the HALT status, and then execute self programming.

p.285

Check FPRERR using a 1-bit memory manipulation instruction.

p.285

The state of the pins in self programming mode is the same as that in HALT

mode.

406

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APPENDIX D LIST OF CAUTIONS

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Page

Function

Details of

Function

Cautions

Flash

memory

Self

Since the security function set via on-board/off-board programming is disabled p.285

in self programming mode, the self programming command can be executed

regardless of the security function setting. To disable write or erase

processing during self programming, set the protect byte.

programming

function

Be sure to clear bits 5 to 7 of flash address pointer H (FLAPH) and flash

address pointer H compare register (FLAPHC) to 0 before executing the self

programming command. If the self programming command is executed with

these bits set to 1, the device may malfunction.

p.285

Clear the value of the FLCMD register to 00H immediately before setting to

self programming mode and normal mode.

p.285

p.286

FLPMC: Flash

programming

mode control

register

Cautions in the case of setting the self programming mode, refer to 19.8.2

Cautions on self programming function.

Set the CPU clock beforehand so that it is 1 MHz or higher during self

programming.

Execute self programming after executing the NOP and HALT instructions

immediately after executing a specific sequence to set self programming

mode. At this time, the HALT instruction is automatically released after 10 μs

(MAX.) + 2 CPU clocks (f^CPU).

If the clock of the oscillator or an external clock is selected as the system

clock, execute the NOP and HALT instructions immediately after executing a

specific sequence to set self programming mode, wait for 8 μs after releasing

the HALT status, and then execute self programming.

p.286

Clear the value of the FLCMD register to 00H immediately before setting to

self programming mode and normal mode.

p.286

p.287

PFCMD: Flash

Interrupt servicing cannot be executed in self programming mode. Disable

protect command interrupt servicing (by executing the DI instruction while MK0 and MK1 = FFH)

register

between the points before executing the specific sequence that sets self

programming mode and after executing the specific sequence that changes

the mode to the normal mode.

PFS: Flash

Check FPRERR using a 1-bit memory manipulation instruction.

p.287

p.290

status register

FLAPH and

Be sure to clear bits 5 to 7 of FLAPH and FLAPHC to 0 before executing the

self programming command. If the self programming command is executed

FLAPL: Flash

address pointers with these bits set to 1, the device may malfunction.

H and L

FLAPHC and

Be sure to clear bits 5 to 7 of FLAPH and FLAPHC to 0 before executing the

p.290

FLAPLC: Flash

address pointer

H compare

self programming command. If the self programming command is executed

with these bits set to 1, the device may malfunction.

Set the number of the block subject to a block erase, verify, or blank check

(same value as FLAPH) to FLAPHC.

p.290

register and flash

address pointer L

compare register

Clear FLAPLC to 00H when a block erase is performed, and FFH when a

blank check is performed.

407

User’s Manual U17446EJ5V0UD

APPENDIX D LIST OF CAUTIONS

(19/20)

Page

Function

Details of

Function

Cautions

Flash

Shifting to self

programming

mode

Be sure to perform the series of operations described above using the user

program at an address where data is not erased or written.

pp.

memory

293,

294,

Shifting to normal

mode

296, 297

If a write results in failure, erase the block once and write to it again.

Byte write

operation

p.305

p.330

On-chip

debug

Connecting QB-

MINI2 to

The 78K0S/KB1+ has an on-chip debug function, which is provided for

development and evaluation. Do not use the on-chip debug function in

products designated for mass production, because the guaranteed number of

rewritable times of the flash memory may be exceeded when this function is

used, and product reliability therefore cannot be guaranteed. NEC Electronics

is not liable for problems occurring when the on-chip debug function is used.

function

78K0S/KB1+

The constants described in the circuit connection example are reference

values. If you perform flash programming aiming at mass production,

thoroughly evaluate whether the specifications of the target device are

satisfied.

p.330

p.332

p.344

If debugging is performed with a real machine running, without using QB-

MINI2, write the user program using the QB-Programmer. Programs

downloaded by the debugger include the monitor program, and such a

program malfunctions if it is not controlled via QB-MINI2.

Product quality may suffer if the absolute maximum rating is exceeded even

momentarily for any parameter. That is, the absolute maximum ratings are

rated values at which the product is on the verge of suffering physical

damage, and therefore the product must be used under conditions that ensure

that the absolute maximum ratings are not exceeded.

Electrical

specifica-

tions

Absolute

maximum ratings

(Standard

product, (A)

grade

When using the X1 oscillator, wire as follows in the area enclosed by the

broken lines in the above figures to avoid an adverse effect from wiring

capacitance.

X1 oscillator

p.345

product)

• Keep the wiring length as short as possible.

• Do not cross the wiring with the other signal lines.

• Do not route the wiring near a signal line through which a high fluctuating

current flows.

• Always make the ground point of the oscillator capacitor the same potential

as V^SS.

• Do not ground the capacitor to a ground pattern through which a high current

flows.

• Do not fetch signals from the oscillator.

The conversion accuracy may be degraded if the analog input pin is used as

an alternate I/O port or if a port is changed during A/D conversion.

A/D converter

p.352

408

User’s Manual U17446EJ5V0UD

APPENDIX D LIST OF CAUTIONS

(20/20)

Page

Function

Details of

Function

Cautions

Electrical

specifica-

tions ((A2)

grade

Absolute

Product quality may suffer if the absolute maximum rating is exceeded even

p.356

maximum ratings momentarily for any parameter. That is, the absolute maximum ratings are

rated values at which the product is on the verge of suffering physical

damage, and therefore the product must be used under conditions that ensure

that the absolute maximum ratings are not exceeded.

product)

When using the X1 oscillator, wire as follows in the area enclosed by the

broken lines in the above figures to avoid an adverse effect from wiring

capacitance.

X1 oscillator

p.358

• Keep the wiring length as short as possible.

• Do not cross the wiring with the other signal lines.

• Do not route the wiring near a signal line through which a high fluctuating

current flows.

• Always make the ground point of the oscillator capacitor the same potential

as V^SS.

• Do not ground the capacitor to a ground pattern through which a high current

flows.

• Do not fetch signals from the oscillator.

A/D converter

The conversion accuracy may be degraded if the analog input pin is used as

an alternate I/O port or if a port is changed during A/D conversion.

p.365

p.373

Products with –A or –AX at the end of the part number are lead-free products.

Recom-

Lead-free

products

mended

soldering

conditions

For soldering methods and conditions other than those recommended below,

contact an NEC Electronics sales representative.

−

Do not use different soldering methods together (except for partial heating).

pp.

373, 374

p.374

Only the pins of the THD are heated when performing wave soldering.

Make sure that flow solder does not come in contact with the package.

409

User’s Manual U17446EJ5V0UD

APPENDIX E REVISION HISTORY

E.1 Major Revisions in This Edition

Page

Description

Throughout

Deletion of μPD78F9232MC-5A4, 78F9234MC-5A4, 78F9232MC(A)-5A4, 78F9234MC(A)-5A4, 78F9232MC(A2)-

5A4, 78F9234MC(A2)-5A4

p. 6

Modification of Documents Related to Development Software Tools (User’s Manuals)

Modification of 1.4 78K0S/Kx1+ Product Lineup

p. 18

Modification of Table 3-3 Special Function Registers

pp. 38 to 41

p. 274

19.4 Writing with Flash Memory Programmer

• Deletion of FlashPro4 and addition of QB-MINI2

• Modification of Remark

p. 275

Modification of and addition of Remark to Figure 19-2 Environment for Writing Program to Flash Memory

(FlashPro5/QB-MINI2)

Modification of Table 19-2 Wiring Between 78K0S/KB1+ and FlashPro5/QB-MINI2

p. 276

Modification of and addition of Remark to Figure 19-3 Wiring diagram with FlashPro5/QB-MINI2 (30-pin

Products)

Modification of Figure 19-7 Communication Commands

p. 280

pp. 299 to 301 19.8.6 Example of block erase operation in self programming mode

•

Modification of description and addition of Note 2

Modification of Figure 19-20 Example of Block Erase Operation in Self Programming Mode

Modification of an example of a program

pp. 320 to 322 19.8.11 Examples of operation when interrupt-disabled time should be minimized in self programming

mode

•

Modification of Figure 19-27 Example of Operation When Interrupt-Disabled Time Should Be Minimized

(from Erasure to Blank Check)

Modification of an example of a program

Modification of Caution in 20.1 Connecting QB-MINI2 to 78K0S/KB1+

p. 330

p. 356

CHAPTER 23 ELECTRICAL SPECIFICATIONS ((A2) grade product)

• Target specifications → Specifications

Modification of APPENDIX A DEVELOPMENT TOOLS

p. 375

410

User’s Manual U17446EJ5V0UD

APPENDIX E REVISION HISTORY

E.2 Revision History up to Previous Editions

The following table shows the revision history up to this edition. The “Applied to:” column indicates the chapters of

each edition in which the revision was applied.

(1/6)

Edition

Description

Applied to:

2nd edition Addition of part number to 1.3 Ordering Information

Modification of operating temperature range in 1.5 78K0S/Kx1+ Product Lineup

Addition of Note to P34/RESET, P121/X1 and P122/X2 in 2.1 Pin Function List

Addition of description to 2.2.3 P30 to P34 (Port 3)

CHAPTER 1 OVERVIEW

CHAPTER 2 PIN

FUNCTIONS

Addition of description to 2.2.7 RESET

Addition of description to and modification of Cautions in 4.2.3 Port 3

CHAPTER 4 PORT

FUNCTIONS

Modification of description in (2) External event counter in 6.1 Functions of 16-bit

CHAPTER 6 16-BIT

TIMER/EVENT COUNTER

00

Timer/Event Counter 00

Modification of Caution 2 in Figure 6-2 Format of 16-bit Timer Counter 00 (TM00)

Modification of Caution 2 in Figure 6-5 Format of 16-bit Timer Mode Control

Register 00 (TMC00)

Addition of Caution to (1), (2), (3), and (4) in 6.4.3 Pulse width measurement

operations

Modification of Figure 6-19 Configuration Diagram for Pulse Width Measurement

by Free-Running Counter

Modification of Figure 6-20 Timing of Pulse Width Measurement Operation by

Free-Running Counter and One Capture Register (with Both Edges Specified)

and Note

Modification of Figure 6-22 Timing of Pulse Width Measurement Operation with

Free-Running Counter (with Both Edges Specified) and Note

Modification of Figure 6-24 Timing of Pulse Width Measurement Operation by

Free-Running Counter and Two Capture Registers (with Rising Edge Specified)

and Note

Modification of <3> and <4> in (2) 16-bit timer counter 00 (TM00) operation of 6.5

Cautions Related to 16-bit Timer/Event Counter 00

Modification of Caution in (1) 8-bit compare register 80 (CR80) of 7.2

CHAPTER 7 8-BIT TIMER

80

Configuration of 8-bit Timer 80

Modification of description in (2) 8-bit timer H compare register 11 (CMP11) of 8.2

CHAPTER 8 8-BIT TIMER

H1

Configuration of 8-bit Timer H1

Modification of Caution 1 in 8.4.2 Operation as PWM output mode

Modification of (e) Operation by changing CMP11 (CMP11 = 02H → 03H, CMP01 =

A5H) in Figure 8-9 Operation Timing in PWM Output Mode

Addition of description to Caution 2 in Figure 9-2 Format of Watchdog Timer Mode CHAPTER 9 WATCHDOG

Register (WDTM)

TIMER

Modification of Table 10-1 Sampling Time and A/D Conversion Time and Note 1

CHAPTER 10 A/D

CONVERTER

Modification of Figure 10-3 Format of A/D Converter Mode Register (ADM) and

Note 2

Addition of description to (7) Input switch control register (ISC) in 11.3 Registers

CHAPTER 11 SERIAL

INTERFACE UART6

Controlling Serial Interface UART6

Modification of value in Table 11-4 Set Data of Baud Rate Generator

411

User’s Manual U17446EJ5V0UD

APPENDIX E REVISION HISTORY

(2/6)

Edition

Description

Applied to:

2nd edition Modification of 13.4.2 Multiple interrupt servicing

CHAPTER 13 INTERRUPT

FUNCTIONS

Addition of Caution to Example 1 in Figure 13-10 Example of Multiple Interrupts

(1/2)

Addition of Example 3 to Figure 13-10 Example of Multiple Interrupts (2/2)

Modification of reset signal in Figure 14-3 HALT Mode Release by Reset Signal

CHAPTER 14 STANDBY

FUNCTION

Generation

Modification of description in and addition of Note to (a) Release by unmasked

interrupt request in (2) of 14.2.2 STOP mode

Modification of reset signal in Figure 14-6 STOP Mode Release by Reset Signal

Generation

Modification of Figure 15-1 Block Diagram of Reset Function

CHAPTER 15 RESET

FUNCTION

Modification of Figure 16-3 Example of Software Processing After Release of

CHAPTER 16 POWER-ON-

CLEAR CIRCUIT

Reset (1/2)

Modification of Figure 17-1 Block Diagram of Low-Voltage Detector

CHAPTER 17 LOW-

VOLTAGE DETECTOR

Modification of INTLVI and Note 2 in Figure 17-5 Timing of Low-Voltage Detector

Interrupt Signal Generation

Modification of (2) in <Action> of 17.5 Cautions for Low-Voltage Detector

Modification of Figure 17-6 Example of Software Processing After Release of

Reset (1/2)

Modification of description and configuration in CHAPTER 18 OPTION BYTE

CHAPTER 18 OPTION

BYTE

Modification of and addition to 19.1 Features

CHAPTER 19 FLASH

MEMORY

Figure 19-2 Environment for Writing Program to Flash Memory is divided into two

figures, in the case of FlashPro4 and in the case of PG-FPL2

Deletion of 19.7.1 Flash memory programming mode

Modification of and addition to 19.8.2 Cautions on self programming function

Addition of <Setting conditions> in 3. Operating conditions of WEPRERR flag of

19.8.3 Registers used for self programming function (3)

Addition of description to Figure 19-15 Format of Flash Programming Command

Register (FLCMD)

Complete revision of CHAPTER 21 ELECTRICAL SPECIFICATIONS (TARGET

CHAPTER 21

VALUES)

ELECTRICAL

SPECIFICATIONS

(TARGET VALUES)

Addition of CHAPTER 25 PACKAGE MARKING INFORMATION and CHAPTER 26

CHAPTER 25 PACKAGE

MARKING INFORMATION

RECOMMENDED SOLDERING CONDITIONS

CHAPTER 26

RECOMMENDED

SOLDERING CONDITIONS

Addition of included software tools to A.1 Software Package

Addition of APPENDIX D LIST OF CAUTIONS

APPENDIX A

DEVELOPMENT TOOLS

APPENDIX D LIST OF

CAUTIONS

412

User’s Manual U17446EJ5V0UD

APPENDIX E REVISION HISTORY

(3/6)

Edition

Description

Applied to:

Throughout

3rd edition Deletion of description on (T) product, (S) product, (R) product, (T2) product

Modification of 1.4 78K0S/Kx1+ Product Lineup

CHAPTER 1 OVERVIEW

Addition of Caution 2 to 3.2.1 (3) Stack pointer (SP)

CHAPTER 3 CPU

ARCHITECTURE

Modification of Figure 4-7 Block Diagram of P34

CHAPTER 4 PORT

FUNCTIONS

Addition of Caution to Figure 4-17 Format of Port Mode Control Register 2

Modification of Caution 2 in 6.2 (1) 16-bit timer counter 00 (TM00)

Addition of 6.5 (23) External clock limitation

CHAPTER 6 16-BIT

TIMER/EVENT COUNTER

00

Addition of Caution to Figure 10-8 Format of Port Mode Control Register 2

CHAPTER 10 A/D

CONVERTER

(PMC2)

Addition of 10.6 (10) Operating current at conversion waiting mode

Addition of Caution to 11.2 (1) Receive buffer register 6 (RXB6)

CHAPTER 11 SERIAL

INTERFACE UART6

Addition of Caution 1 to and modification of Caution 3 in 11.2 (3) Transmit buffer

register 6 (TXB6)

Correction of Note 3 in Figure 11-5 Format of Asynchronous Serial Interface

Operation Mode Register 6 (ASIM6) (1/2)

Addition of Notes 1 and 2 to and modification of Cautions 1, 2 and 3 in Figure 11-5

Format of Asynchronous Serial Interface Operation Mode Register 6 (ASIM6)

(2/2)

Modification of Caution in 11.3 (6) Asynchronous serial interface control register

6 (ASICL6)

Modification of Caution 1 in Figure 11-10 Format of Asynchronous Serial

Interface Control Register 6 (ASICL6)

Modification of Caution in 11.4.2 (1) Registers used

Partial modification of description in 11.4.2 (2) (c) Normal transmission

Partial modification of description in and addition of Caution 1 to 11.4.2 (2) (d)

Continuous transmission

Addition of Caution 2 to 17.3 (2) Low-voltage detection level select register (LVIS) CHAPTER 17 LOW-

VOLTAGE DETECTOR

Addition of 18.3 Caution When the RESET Pin Is Used as an Input-Only Port Pin

CHAPTER 18 OPTION

BYTE

(P34)

Addition of description to 19.6.1 X1 and X2 pins

CHAPTER 19 FLASH

MEMORY

Addition of Remark 1 to 19.8 Flash Memory Programming by Self Writing

Modification of description of internal verify 1 in and addition of description and

Remark of internal verify 2 to Table 19-11 Self Programming Controlling

Commands

Partial modification of and addition to 19.8.2 Cautions on self programming

function

Addition of Cautions 2, 3 and 5 to and modification of Caution 4 in Figure 19-12

Format of Flash Programming Mode Control Register (FLPMC)

Modification of Caution in and addition of description on FPRERR to 19.8.3 (2) Flash

protect command register (PFCMD)

Addition of Caution to 19.8.3 (3) Flash status register (PFS)

413

User’s Manual U17446EJ5V0UD

APPENDIX E REVISION HISTORY

(4/6)

Edition

Description

Applied to:

3rd edition Modification of description and Note of internal verify 1 in and addition of description

of internal verify 2 to Figure 19-15 Format of Flash Programming Command

Register (FLCMD)

CHAPTER 19 FLASH

MEMORY

Modification of Caution in Figure 19-16 Format of Flash Address Pointer H/L

(FLAPH/FLAPL) and Caution 1 in Format of Flash Address Pointer H/L Compare

Registers (FLAPHC/FLAPLC)

Addition of description to 19.8.4 Example of shifting normal mode to self

programming mode and 19.8.5 Example of shifting self programming mode to

normal mode

Addition of description of internal verify 1 and 2 to 19.8.9 Examples of internal verify

operation in self programming mode

Addition of description to 19.8.10 Examples of operation when command

execution time should be minimized in self programming mode and 19.8.11

Examples of operation when interrupt-disabled time should be minimized in self

programming mode

• Correction of MAX. value of low-level input voltage (VIL3)

• Correction of conditions of high-level output voltage (V^OH2)

• Modification of MAX. values of high-level input leakage current, low-level input

leakage current, high-level output leakage current and low-level output leakage

current

CHAPTER 21

ELECTRICAL

SPECIFICATIONS

(Standard product, (A)

grade product)

• Modification of MAX. values of supply current (I^DD5) in STOP mode

• Addition of setting range of CPU clock and peripheral clock frequency to AC

Characteristics

• Modification of Caution in A/D Converter Characteristics

• Correction of MAX. value of low-level input voltage (VIL3)

• Correction of conditions of high-level output voltage (V^OH2)

• Addition of formula to calculate power consumption of internal pull-up resistor

• Addition of setting range of CPU clock and peripheral clock frequency to AC

Characteristics

CHAPTER 22

ELECTRICAL

SPECIFICATIONS

(TARGET VALUES) ((A2)

grade product)

• Modification of Caution in A/D Converter Characteristics

Deletion of CHAPTER 25 PACKAGE MARKING INFORMATION

CHAPTER 25 PACKAGE

MARKING INFORMATION

Modification of A.4 Flash Memory Writing Tools

APPENDIX A

DEVELOPMENT TOOLS

Addition of A.5.1 When using in-circuit emulator QB-78K0SKX1 (under

development) and A.5.2 When using in-circuit emulator QB-MINI2

414

User’s Manual U17446EJ5V0UD

APPENDIX E REVISION HISTORY

(5/6)

Edition

Description

Applied to:

Throughout

4th edition • Addition of SDIP package products (μPD78F9232CS-CAA-A, 78F9234CS-CAA-A)

• Addition of products (μPD78F9232MC(A)-CAB-AX, 78F9234MC(A)-CAB-AX,

78F9232MC(A2)-CAB-AX, 78F9234MC(A2)-CAB-AX) to SSOP package

Modification of 1.1 Features

CHAPTER 1 OVERVIEW

Modification of 1.2 Ordering Information

1.3 Pin Configuration (Top View)

• Modification of description of AV^REF

Modification of 1.4 78K0S/Kx1+ Product Lineup

Modification of 1.6 Functional Outline

2.1 Pin Function List, 2.2.9 AVREF

CHAPTER 2 PIN

FUNCTIONS

• Modification of description of AVREF function

• Addition of Note 4 to Table 10-1 Sampling Time and A/D Conversion Time

• Addition of Note 5 to Figure 10-3 Format of A/D Converter Mode Register

(ADM)

CHAPTER 10 A/D

CONVERTER

Modification of Caution 3

CHAPTER 15 RESET

FUNCTION

19.4 Writing with Flash Memory Programmer

CHAPTER 19 FLASH

• Modification of the dedicated flash memory programmer (Addition of FlashPro5 and MEMORY

deletion of PG-FPL2)

• Modification of Remark

19.5 Programming Environment

• Addition of FlashPro5 and QB-MINI2 to the dedicated flash memory programmer

• Addition of description about connection to FlashPro5/QB-MINI2

• Deletion of PG-FPL2 from the dedicated flash memory programmer

Modification of Figure 19-5 PG-FP5 GUI Software Setting Example

Figure 19-7 Communication Commands

• Addition of FlashPro5 and QB-MINI2 to the dedicated flash memory programmer

• Deletion of PG-FPL2 from the dedicated flash memory programmer

Addition of Note to Table 19-10 Self Programming Controlling Commands

Addition of this chapter

CHAPTER 20 ON-CHIP

DEBUG FUNCTION

• Modification of X1 Oscillator Characteristics

• Addition of setting range of CPU clock and peripheral clock frequency to AC

Characteristics

CHAPTER 22

ELECTRICAL

SPECIFICATIONS

(Standard product, (A)

grade product)

• Modification of X1 Oscillator Characteristics

• Addition of setting range of CPU clock and peripheral clock frequency to AC

Characteristics

CHAPTER 23

ELECTRICAL

SPECIFICATIONS

(TARGET VALUES) ((A2)

grade product)

Addition of package drawings of additional products

CHAPTER 24 PACKAGE

DRAWING

Addition of recommended soldering conditions of additional products

CHAPTER 25

RECOMMENDED

SOLDERING CONDITIONS

415

User’s Manual U17446EJ5V0UD

APPENDIX E REVISION HISTORY

(6/6)

Edition

Description

Applied to:

APPENDIX A

4th edition Modification of Figure A-1 Development Tools

DEVELOPMENT TOOLS

A.4 Flash Memory Writing Tools

• Addition of FlashPro5 and QB-MINI2

• Deletion of PG-FPL2

Modification of A.5.1 When using in-circuit emulator QB-78K0SKX1

Deletion of A.5.3 When using in-circuit emulator IE-78K0S-NS or IE-78K0S-NS-A

and A.5.4 When using in-circuit emulator QB-78K0SKX1MINI

Modification of A.6 Debugging Tools (Software)

Modification of this chapter

APPENDIX B NOTES ON

DESIGNING TARGET

SYSTEM

416

User’s Manual U17446EJ5V0UD

Published by: NEC Electronics Corporation (http://www.necel.com/)

Contact: http://www.necel.com/support/


型号：	UPD78F9234MC(A2)-5A4-A
厂家：	RENESAS TECHNOLOGY CORP
描述：	Compact, Low-power, Low Pin-count 8-bit Microcontrollers for General Purpose Applications (Non Promotion), , / 时钟微控制器 ISM频段光电二极管外围集成电路
文件：	总419页 (文件大小：2588K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

UPD78F9234MC(A2)-5A4-A [RENESAS]

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