X1226S8Z-T1 [RENESAS]
1 TIMER(S), REAL TIME CLOCK, PDSO8, 0.150 INCH, ROHS COMPLIANT, SOIC-8;
| 型号： | X1226S8Z-T1 |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | 1 TIMER(S), REAL TIME CLOCK, PDSO8, 0.150 INCH, ROHS COMPLIANT, SOIC-8 时钟 光电二极管 外围集成电路 |
| 文件： | 总25页 (文件大小：372K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
X1226
®
™
4K (512 x 8), 2-Wire RTC
Data Sheet
May 8, 2006
FN8098.3
APPLICATIONS
Real Time Clock/Calendar with EEPROM
• Utility Meters
FEATURES
• HVAC Equipment
• Audio/Video Components
• Set Top Box/Television
• Modems
• Network Routers, Hubs, Switches, Bridges
• Cellular Infrastructure Equipment
• Fixed Broadband Wireless Equipment
• Pagers/PDA
• POS Equipment
• Test Meters/Fixtures
• Office Automation (Copiers, Fax)
• Home Appliances
• Computer Products
• Real Time Clock/Calendar
—Tracks Time in Hours, Minutes, and Seconds
—Day of the Week, Day, Month, and Year
• 2 Polled Alarms (Non-volatile)
—Settable on the Second, Minute, Hour, Day of
the Week, Day, or Month
—Repeat Mode (periodic interrupts)
• Oscillator Compensation On Chip
—Internal Feedback Resistor and Compensation
Capacitors
—64 Position Digitally Controlled Trim Capacitor
—6 Digital Frequency Adjustment Settings to
±30ppm
• Other Industrial/Medical/Automotive
• Battery Switch or Super Cap Input
• 512 x 8 Bits of EEPROM
DESCRIPTION
—64-Byte Page Write Mode
The X1226 device is a Real Time Clock with
clock/calendar, two polled alarms with integrated
512x8 EEPROM, oscillator compensation, and battery
backup switch.
—8 Modes of Block Lock™ Protection
—Single Byte Write Capability
• High Reliability
—Data Retention: 100 Years
—Endurance: 100,000 Cycles Per Byte
• 2-Wire™ Interface Interoperable with I C
—400kHz Data Transfer Rate
• Frequency Output (SW Selectable: Off, 1Hz,
4096Hz or 32.768kHz)
The oscillator uses an external, low-cost 32.768kHz
crystal. All compensation and trim components are
integrated on the chip. This eliminates several external
discrete components and a trim capacitor, saving
board area and component cost.
2
• Low Power CMOS
—1.25µA Operating Current (Typical)
• Small Package Options
—8 Ld SOIC and 8 Ld TSSOP
• Repetitive Alarms
• Temperature Compensation
• Pb-Free Plus Anneal Available (RoHS Compliant)
BLOCK DIAGRAM
OSC
Compensation
X1
Timer
Calendar
Logic
Battery
Switch
Circuitry
Time
Keeping
Registers
VCC
Frequency
Divider
1Hz
Oscillator
32.768kHz
VBACK
X2
Select
(SRAM)
PHZ/IRQ
Status
Control/
Control
Decode
Logic
Compare
Serial
Interface
Decoder
Registers
SCL
SDA
Registers
Alarm
(EEPROM)
(SRAM)
Alarm Regs
(EEPROM)
8
4K
EEPROM
ARRAY
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2005-2006. All Rights Reserved
1
All other trademarks mentioned are the property of their respective owners.
X1226
Ordering Information
TEMP
PART NUMBER
X1226S8*
PART MARKING
VDD (V)
RANGE (°C)
PACKAGE
8 Ld SOIC (150 mil)
PKG. DWG. #
MDP0027
MDP0027
MDP0027
MDP0027
M8.173
X1226
X1226Z
X1226I
X1226ZI
1226
2.7 to 5.5
0 to 70
0 to 70
X1226S8Z* (Note)
X1226S8I*
8 Ld SOIC (150 mil) (Pb-free)
8 Ld SOIC (150 mil)
-40 to 85
-40 to 85
0 to 70
X1226S8IZ* (Note)
X1226V8*
8 Ld SOIC (150 mil) (Pb-free)
8 Ld TSSOP (4.4mm)
X1226V8Z* (Note)
X1226V8I*
1226Z
1226I
0 to 70
8 Ld TSSOP (4.4mm) (Pb-free)
8 Ld TSSOP (4.4mm)
M8.173
-40 to 85
-40 to 85
M8.173
X1226V8IZ* (Note)
1226IZ
8 Ld TSSOP (4.4mm) (Pb-free)
M8.173
*Add "T1" suffix for tape and reel.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
PIN CONFIGURATION
8 LD SOIC
8 LD TSSOP
VBACK
VCC
SCL
V
V
X1
X2
1
2
CC
8
7
6
5
1
8
7
6
5
SDA
2
BACK
VSS
X1
X2
3
4
SCL
SDA
PHZ/IRQ
3
4
PHZ/IRQ
V
SS
FN8098.3
May 8, 2006
2
X1226
PIN ASSIGNMENTS
Pin Number
SOIC
TSSOP Symbol
Brief Description
1
3
4
5
X1
X1. The X1pin is the input of an inverting amplifier. An external 32.768kHz quartz
crystal is used with the X1226 to supply a timebase for the real time clock. The
recommended crystal is a Citizen CFS206-32.768KDZF. Internal compensation circuitry is
included to form a complete oscillator circuit. Care should be taken in the placement of the
crystal and the layout of the circuit. Plenty of ground plane around the device and short
traces to X1 are highly recommended. See Application section for more recommendations.
2
3
X2
X2. The X2 pin is the output of an inverting amplifier. An external 32.768kHz quartz
crystal is used with the X1226 to supply a timebase for the real time clock. The
recommended crystal is a Citizen CFS206-32.768KDZF. Internal compensation circuitry is
included to form a complete oscillator circuit. Care should be taken in the placement of the
crystal and the layout of the circuit. Plenty of ground plane around the device and short
traces to X2 are highly recommended. See Application section for more recommendations.
PHZ/IRQ
Programmable Frequency/Interrupt Output – PHZ/IRQ. This is either an output from
the internal oscillator or an interrupt signal output. It is an open drain output.
When used as frequency output, this signal has a frequency of 32.768kHz, 4096Hz,
1Hz or inactive.
When used as interrupt output, this signal notifies a host processor that an alarm has
occurred and an action is required. It is an active LOW output.
The control bits for this function are FO1 and FO0 and are found in address 0011h of
the Clock Control Memory map. See “Programmable Frequency Output Bits—FO1,
FO0” on page 9.
4
5
6
7
VSS
VSS.
SDA
Serial Data (SDA). SDA is a bidirectional pin used to transfer data into and out of the
device. It has an open drain output and may be wire ORed with other open drain or
open collector outputs. The input buffer is always active (not gated).
An open drain output requires the use of a pull-up resistor. The output circuitry controls
the fall time of the output signal with the use of a slope controlled pull-down. The circuit
is designed for 400kHz 2-wire interface speed.
6
7
8
1
SCL
Serial Clock (SCL). The SCL input is used to clock all data into and out of the device.
The input buffer on this pin is always active (not gated).
VBACK
VBACK. This input provides a backup supply voltage to the device. VBACK supplies
power to the device in the event the VCC supply fails. This pin can be connected to a
battery, a Supercap or tied to ground if not used.
8
2
VCC
VCC.
FN8098.3
May 8, 2006
3
X1226
DESCRIPTION (continued)
Serial Data (SDA)
SDA is a bidirectional pin used to transfer data into and
out of the device. It has an open drain output and may
be wire ORed with other open drain or open collector
outputs. The input buffer is always active (not gated).
The Real-Time Clock keeps track of time with
separate registers for Hours, Minutes, Seconds. The
Calendar has separate registers for Date, Month, Year
and Day-of-week. The calendar is correct through
2099, with automatic leap year correction.
An open drain output requires the use of a pull-up
resistor. The output circuitry controls the fall time of
the output signal with the use of a slope controlled
pull-down. The circuit is designed for 400kHz 2-wire
interface speed.
The powerful Dual Alarms can be set to any
Clock/Calendar value for a match. For instance, every
minute, every Tuesday, or 5:23 AM on March 21. The
alarms can be polled in the Status Register or provide
a hardware interrupt (IRQ Pin). There is a repeat
mode for the alarms allowing a periodic interrupt.
V
BACK
This input provides a backup supply voltage to the
device. V supplies power to the device in the
The PHZ/IRQ pin may be software selected to provide
a frequency output of 1 Hz, 4096 Hz, or 32,768 Hz.
BACK
event the V supply fails. This pin can be connected
CC
to a battery, a Supercap or tied to ground if not used.
The device offers a backup power input pin. This
V
pin allows the device to be backed up by
BACK
Programmable Frequency/Interrupt Output – PHZ/IRQ
battery or SuperCap. The entire X1226 device is fully
operational from 2.7 to 5.5 volts and the
clock/calendar portion of the X1226 device remains
fully operational down to 1.8 volts (Standby Mode).
This is either an output from the internal oscillator or an
interrupt signal output. It is an open drain output.
When used as frequency output, this signal has a
frequency of 32.768kHz, 4096Hz, 1Hz or inactive.
The X1226 device provides 4K bits of EEPROM with 8
modes of BlockLock™ control. The BlockLock allows a
safe, secure memory for critical user and configuration
data, while allowing a large user storage area.
When used as interrupt output, this signal notifies a
host processor that an alarm has occurred and an
action is required. It is an active LOW output.
The control bits for this function are FO1 and FO0 and
are found in address 0011h of the Clock Control Mem-
ory map. See “Programmable Frequency Output
Bits—FO1, FO0” on page 9.
PIN DESCRIPTIONS
X1226
8 LD SOIC
8 LD TSSOP
X1, X2
VBACK
VCC
SCL
1
2
VCC
X1
X2
8
7
6
5
1
2
8
7
6
5
The X1 and X2 pins are the input and output,
respectively, of an inverting amplifier. An external
32.768kHz quartz crystal is used with the X1226 to
supply a timebase for the real time clock. The
recommended crystal is a Citizen CFS206-32.768KDZF.
Internal compensation circuitry is included to form a
complete oscillator circuit. Care should be taken in the
placement of the crystal and the layout of the circuit.
Plenty of ground plane around the device and short
traces to X1 and X2 are highly recommended. See
Application section for more recommendations.
SDA
VSS
VBACK
SCL
X1
X2
3
4
PHZ/IRQ
VSS
3
4
PHZ/IRQ
SDA
NC = No internal connection
Serial Clock (SCL)
The SCL input is used to clock all data into and out of
the device. The input buffer on this pin is always active
(not gated).
Figure 1. Recommended Crystal Connection
X1
X2
FN8098.3
May 8, 2006
4
X1226
POWER CONTROL OPERATION
the stop bit is written. The RTC continues to update
the time while an RTC register write is in progress and
the RTC continues to run during any nonvolatile write
sequences. A single byte may be written to the RTC
without affecting the other bytes.
The power control circuit accepts a V
and a V
BACK
CC
input. The power control circuit powers the clock from
when V < V – 0.2V. It will switch back to
V
BACK
CC
BACK
power the device from V when V exceeds V
.
CC
CC
BACK
Figure 2. Power Control
Accuracy of the Real Time Clock
The accuracy of the Real Time Clock depends on the
frequency of the quartz crystal that is used as the time
base for the RTC. Since the resonant frequency of a
crystal is temperature dependent, the RTC perfor-
mance will also be dependent upon temperature. The
frequency deviation of the crystal is a fuction of the
turnover temperature of the crystal from the crystal’s
nominal frequency. For example, a >20ppm frequency
deviation translates into an accuracy of >1 minute per
month. These parameters are available from the crystal
manufacturer. Intersil’s RTC family provides on-chip
crystal compensation networks to adjust load-
capacitance to tune oscillator frequency from +116 ppm
to -37 ppm when using a 12.5 pF load crystal. For more
detail information see the Application section.
VCC
Voltage
On
VBACK
In
Off
REAL TIME CLOCK OPERATION
The Real Time Clock (RTC) uses an external
32.768kHz quartz crystal to maintain an accurate inter-
nal representation of the second, minute, hour, day,
date, month, and year. The RTC has leap-year correc-
tion. The clock also corrects for months having fewer
than 31 days and has a bit that controls 24 hour or
AM/PM format. When the X1226 powers up after the
CLOCK/CONTROL REGISTERS (CCR)
loss of both V and V
, the clock will not operate
CC
BACK
The Control/Clock Registers are located in an area
separate from the EEPROM array and are only
accessible following a slave byte of “1101111x” and
reads or writes to addresses [0000h:003Fh]. The
clock/control memory map has memory addresses
from 0000h to 003Fh. The defined addresses are
described in the Table 1. Writing to and reading from
the undefined addresses are not recommended.
until at least one byte is written to the clock register.
Reading the Real Time Clock
The RTC is read by initiating a Read command and
specifying the address corresponding to the register of
the Real Time Clock. The RTC Registers can then be
read in a Sequential Read Mode. Since the clock runs
continuously and a read takes a finite amount of time,
there is the possibility that the clock could change during
the course of a read operation. In this device, the time is
latched by the read command (falling edge of the clock
on the ACK bit prior to RTC data output) into a separate
latch to avoid time changes during the read operation.
The clock continues to run. Alarms occurring during a
read are unaffected by the read operation.
CCR Access
The contents of the CCR can be modified by perform-
ing a byte or a page write operation directly to any
address in the CCR. Prior to writing to the CCR
(except the status register), however, the WEL and
RWEL bits must be set using a two step process (See
section “Writing to the Clock/Control Registers.”)
Writing to the Real Time Clock
The CCR is divided into 5 sections. These are:
The time and date may be set by writing to the RTC
registers. To avoid changing the current time by an
uncompleted write operation, the current time value is
loaded into a separate buffer at the falling edge of the
clock on the ACK bit before the RTC data input bytes,
the clock continues to run. The new serial input data
replaces the values in the buffer. This new RTC value
is loaded back into the RTC Register by a stop bit at
the end of a valid write sequence. An invalid write
operation aborts the time update procedure and the
contents of the buffer are discarded. After a valid write
operation the RTC will reflect the newly loaded data
beginning with the next “one second” clock cycle after
1. Alarm 0 (8 bytes; non-volatile)
2. Alarm 1 (8 bytes; non-volatile)
3. Control (4 bytes; non-volatile)
4. Real Time Clock (8 bytes; volatile)
5. Status (1 byte; volatile)
Each register is read and written through buffers. The
non-volatile portion (or the counter portion of the RTC) is
updated only if RWEL is set and only after a valid write
operation and stop bit. A sequential read or page write
operation provides access to the contents of only one
section of the CCR per operation. Access to another sec-
tion requires a new operation. Continued reads or writes,
FN8098.3
May 8, 2006
5
X1226
once reaching the end of a section, will wrap around to
the start of the section. A read or write can begin at any
address in the CCR.
registers are read by performing a sequential read.
The read instruction latches all Clock registers into a
buffer, so an update of the clock does not change the
time being read. A sequential read of the CCR will not
result in the output of data from the memory array. At
the end of a read, the master supplies a stop condition
to end the operation and free the bus. After a read of
the CCR, the address remains at the previous address
+1 so the user can execute a current address read of
the CCR and continue reading the next Register.
It is not necessary to set the RWEL bit prior to writing
the status register. Section 5 (status register) supports
a single byte read or write only. Continued reads or
writes from this section terminates the operation.
The state of the CCR can be read by performing a ran-
dom read at any address in the CCR at any time. This
returns the contents of that register location. Additional
Table 1. Clock/Control Memory Map
Bit
Reg
Name
Addr.
Type
Range
7
6
5
4
3
2
1
0 (optional)
003F
0037
0036
0035
0034
0033
0032
0031
0030
0013
0012
0011
0010
000F
000E
000D
000C
000B
000A
0009
0008
0007
0006
0005
0004
0003
0002
0001
0000
Status
SR
Y2K
DW
YR
BAT
0
AL1
0
AL0
Y2K21
0
0
Y2K20
0
0
Y2K13
0
RWEL
0
WEL
0
RTCF
Y2K10
DY0
Y10
G10
D10
H10
M10
S10
DTR0
ATR0
X
01h
20h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
20h
00h
RTC
(SRAM)
19/20
0-6
0
0
DY2
Y12
G12
D12
H12
M12
S12
DTR2
ATR2
X
DY1
Y11
G11
D11
H11
M11
S11
DTR1
ATR1
X
Y23
0
Y22
0
Y21
0
Y20
G20
D20
H20
M20
S20
0
Y13
G13
D13
H13
M13
S13
0
0-99
1-12
1-31
0-23
0-59
0-59
MO
DT
0
0
D21
H21
M21
S21
0
HR
MIL
0
0
MN
SC
M22
S22
0
0
Control
(EEPROM)
DTR
ATR
INT
BL
0
0
0
ATR5
AL0E
BP0
ATR4
FO1
0
ATR3
FO0
0
IM
BP2
0
AL1E
BP1
0
0
0
0
Alarm1
(EEPROM)
Y2K1
A1Y2K21 A1Y2K20 A1Y2K13
0
0
A1Y2K10 19/20
DWA1 EDW1
YRA1
0
0
0
0
DY2
DY1
DY0
0-6
Unused - Default = RTC Year value (No EEPROM) - Future expansion
MOA1 EMO1
0
0
A1G20
A1D20
A1H20
A1M20
A1S20
A1G13
A1D13
A1H13
A1M13
A1S13
A1G12
A1D12
A1H12
A1M12
A1S12
0
A1G11
A1D11
A1H11
A1M11
A1S11
0
A1G10
A1D10
A1H10
A1M10
A1S10
1-12
1-31
0-23
0-59
0-59
00h
00h
00h
00h
00h
20h
00h
DTA1
HRA1
EDT1
EHR1
0
A1D21
A1H21
A1M21
A1S21
0
A1M22
A1S22
0
MNA1 EMN1
SCA1
Y2K0
ESC1
0
Alarm0
(EEPROM)
A0Y2K21 A0Y2K20 A0Y2K13
A0Y2K10 19/20
DWA0 EDW0
YRA0
0
0
0
0
DY2
DY1
DY0
0-6
Unused - Default = RTC Year value (No EEPROM) - Future expansion
MOA0 EMO0
0
0
0
A0G20
A0D20
A0H20
A0M20
A0S20
A0G13
A0D13
A0H13
A0M13
A0S13
A0G12
A0D12
A0H12
A0M12
A0S12
A0G11
A0D11
A0H11
A0M11
A0S11
A0G10
A0D10
A0H10
A0M10
A0S10
1-12
1-31
0-23
0-59
0-59
00h
00h
00h
00h
00h
DTA0
HRA0
EDT0
EHR0
A0D21
A0H21
A0M21
A0S21
0
MNA0 EMN0
A0M22
A0S22
SCA0
ESC0
FN8098.3
May 8, 2006
6
X1226
ALARM REGISTERS
Leap Years
Leap years add the day February 29 and are defined
as those years that are divisible by 4. Years divisible
by 100 are not leap years, unless they are also divisi-
ble by 400. This means that the year 2000 is a leap
year, the year 2100 is not. The X1226 does not correct
for the leap year in the year 2100.
There are two alarm registers whose contents mimic the
contents of the RTC register, but add enable bits and
exclude the 24 hour time selection bit. The enable bits
specify which registers to use in the comparison between
the Alarm and Real Time Registers. For example:
– Setting the Enable Month bit (EMOn*) bit in combi-
nation with other enable bits and a specific alarm
time, the user can establish an alarm that triggers at
the same time once a year.
STATUS REGISTER (SR)
The Status Register is located in the CCR memory
map at address 003Fh. This is a volatile register only
and is used to control the WEL and RWEL write
enable latches, read power status and two alarm bits.
This register is separate from both the array and the
Clock/Control Registers (CCR).
*n = 0 for Alarm 0: N = 1 for Alarm 1
When there is a match, an alarm flag is set. The occur-
rence of an alarm can be determined by polling the
AL0 and AL1 bits or by enabling the IRQ output, using
it as hardware flag.
Table 2. Status Register (SR)
The alarm enable bits are located in the MSB of the
particular register. When all enable bits are set to ‘0’,
there are no alarms.
Addr
003Fh BAT AL1 AL0
Default
7
6
5
4
3
2
1
0
0
0
0
0
RWEL WEL RTCF
0
0
0
0
0
1
– The user can set the X1226 to alarm every Wednes-
day at 8:00 AM by setting the EDWn*, the EHRn*
and EMNn* enable bits to ‘1’ and setting the DWAn*,
HRAn* and MNAn* Alarm registers to 8:00 AM
Wednesday.
BAT: Battery Supply—Volatile
This bit set to “1” indicates that the device is operating
from V , not V . It is a read-only bit and is
BACK
CC
– A daily alarm for 9:30PM results when the EHRn*
and EMNn* enable bits are set to ‘1’ and the HRAn*
and MNAn* registers are set to 9:30 PM.
set/reset by hardware (X1226 internally). Once the
device begins operating from V , the device sets this
CC
bit to “0”.
*n = 0 for Alarm 0: N = 1 for Alarm 1
AL1, AL0: Alarm bits—Volatile
REAL TIME CLOCK REGISTERS
These bits announce if either alarm 0 or alarm 1 match
the real time clock. If there is a match, the respective
bit is set to ‘1’. The falling edge of the last data bit in a
SR Read operation resets the flags. Note: Only the AL
bits that are set when an SR read starts will be reset.
An alarm bit that is set by an alarm occurring during an
SR read operation will remain set after the read opera-
tion is complete.
Clock/Calendar Registers (SC, MN, HR, DT, MO, YR)
These registers depict BCD representations of the
time. As such, SC (Seconds) and MN (Minutes) range
from 00 to 59, HR (Hour) is 1 to 12 with an AM or PM
indicator (H21 bit) or 0 to 23 (with MIL = 1), DT (Date)
is 1 to 31, MO (Month) is 1 to 12, YR (Year) is 0 to 99.
Date of the Week Register (DW)
RWEL: Register Write Enable Latch—Volatile
This register provides a Day of the Week status and
uses three bits DY2 to DY0 to represent the seven
days of the week. The counter advances in the cycle
0-1-2-3-4-5-6-0-1-2-… The assignment of a numerical
value to a specific day of the week is arbitrary and may
be decided by the system software designer. The
default value is defined as ‘0’.
This bit is a volatile latch that powers up in the LOW
(disabled) state. The RWEL bit must be set to “1” prior
to any writes to the Clock/Control Registers. Writes to
RWEL bit do not cause a nonvolatile write cycle, so
the device is ready for the next operation immediately
after the stop condition. A write to the CCR requires
both the RWEL and WEL bits to be set in a specific
sequence.
24 Hour Time
If the MIL bit of the HR register is 1, the RTC uses a
24-hour format. If the MIL bit is 0, the RTC uses a 12-
hour format and H21 bit functions as an AM/PM
indicator with a ‘1’ representing PM. The clock defaults
to standard time with H21 = 0.
FN8098.3
May 8, 2006
7
X1226
WEL: Write Enable Latch—Volatile
INTERRUPT CONTROL AND FREQUENCY
OUTPUT REGISTER (INT)
The WEL bit controls the access to the CCR and mem-
ory array during a write operation. This bit is a volatile
latch that powers up in the LOW (disabled) state. While
the WEL bit is LOW, writes to the CCR or any array
address will be ignored (no acknowledge will be issued
after the Data Byte). The WEL bit is set by writing a “1”
to the WEL bit and zeroes to the other bits of the Status
Register. Once set, WEL remains set until either reset
to 0 (by writing a “0” to the WEL bit and zeroes to the
other bits of the Status Register) or until the part powers
up again. Writes to WEL bit do not cause a nonvolatile
write cycle, so the device is ready for the next operation
immediately after the stop condition.
Interrupt Control and Status Bits (IM, AL1E, AL0E)
There are two Interrupt Control bits, Alarm 1 Interrupt
Enable (AL1E) and Alarm 0 Interrupt Enable (AL0E) to
specifically enable or disable the alarm interrupt signal
output (IRQ). The interrupts are enabled when either the
AL1E and AL0E bits are set to ‘1’, respectively.
Table 3. Block Protect Bits
Protected
Addresses
X1226
Array Lock
None
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
None
RTCF: Real Time Clock Fail Bit—Volatile
6000h – 7FFFh
4000h – 7FFFh
0000h – 7FFFh
0000h – 007Fh
0000h – 00FFh
0000h – 01FFh
0000h – 03FFh
Upper 1/4
Upper 1/2
Full Array
First Page
First 2 pgs
First 4 pgs
First 8 Pgs
This bit is set to a “1” after a total power failure. This is
a read only bit that is set by hardware (X1226 inter-
nally) when the device powers up after having lost all
power to the device (both V
and V
go to 0V).
CC
BACK
The bit is set regardless of whether V
or V
is
BACK
CC
applied first. The loss of only one of the supplies does
not set the RTCF bit to “1”. On power-up after a total
power failure, all registers are set to their default
states and the clock will not increment until at least
one byte is written to the clock register. The first valid
write to the RTC section after a complete power failure
resets the RTCF bit to “0” (writing one byte is suffi-
cient).
Two volatile bits (AL1 and AL0), associated with the two
alarms respectively, indicate if an alarm has happened.
These bits are set on an alarm condition regardless of
whether the IRQ interrupt is enabled. The AL1 and AL0
bits in the status register are reset by the falling edge of
the eighth clock of a read of the register containing the
bits.
Unused Bits:
This device does not use bits 3 or 4 in the SR, but
must have a zero in these bit positions. The Data Byte
output during a SR read will contain zeros in these bit
locations.
Pulse Interrupt Mode
The pulsed interrrupt mode allows for repetitive or
recurring alarm functionality. Hence an repetitive or
CONTROL REGISTERS
th
th
recurring alarm can be set for every n second, or n
The Control Bits and Registers, described under this
section, are nonvolatile.
th
th
minute, or n hour, or n date, or for the same day of
the week. The pulsed interrupt mode can be consid-
ered a repetitive interrupt mode, with the repetition
rate set by the time setting fo the alarm.
Block Protect Bits—BP2, BP1, BP0
The Block Protect Bits, BP2, BP1 and BP0, determine
which blocks of the array are write protected. A write to a
protected block of memory is ignored. The block protect
bits will prevent write operations to one of eight segments
of the array. The partitions are described in Table 3.
The Pulse Interrupt Mode is enabled when the IM bit is
set.
IM Bit
Interrupt/Alarm Frequency
0
Single Time Event Set By Alarm
Repetitive/Recurring Time Event Set By
Alarm
1
The Alarm IRQ output will output a single pulse of
short duration (approximately 10-40ms) once the
alarm condition is met. If the interrupt mode bit (IM bit)
is set, then this pulse will be periodic.
FN8098.3
May 8, 2006
8
X1226
Programmable Frequency Output Bits—FO1, FO0
with different ATR bit combinations provides an esti-
mated ppm range from +116ppm to -37ppm to the
nominal frequency compensation. The combination of
digital and analog trimming can give up to +146ppm
adjustment.
These are two output control bits. They select one of
three divisions of the internal oscillator, that is applied
to the PHZ output pin. Table 4 shows the selection bits
for this output. When using the PHZ output function,
the Alarm IRQ output function is disabled.
The on-chip capacitance can be calculated as follows:
Table 4. Programmable Frequency Output Bits
Output Frequency
C
= [(ATR value, decimal) x 0.25pF] + 11.0pF
ATR
Note that the ATR values are in two’s complement,
with ATR(000000) = 11.0pF, so the entire range runs
from 3.25pF to 18.75pF in 0.25pF steps.
FO1 FO0
(average of 100 samples)
Alarm IRQ output
32.768kHz
0
0
1
1
0
1
0
1
The values calculated above are typical, and total load
capacitance seen by the crystal will include approxi-
mately 2pF of package and board capacitance in addi-
tion to the ATR value.
4096Hz
1Hz
See Application Section and Intersil’s Application Note
AN154 for more information.
ON-CHIP OSCILLATOR COMPENSATION
Digital Trimming Register (DTR) — DTR2, DTR1
and DTR0 (Non-Volatile)
WRITING TO THE CLOCK/CONTROL REGISTERS
The digital trimming Bits DTR2, DTR1 and DTR0
adjust the number of counts per second and average
the ppm error to achieve better accuracy.
Changing any of the nonvolatile bits of the
clock/control register requires the following steps:
– Write a 02h to the Status Register to set the Write
Enable Latch (WEL). This is a volatile operation, so
there is no delay after the write. (Operation pre-
ceeded by a start and ended with a stop).
DTR2 is a sign bit. DTR2 = 0 means frequency
compensation is > 0. DTR2 = 1 means frequency
compensation is < 0.
– Write a 06h to the Status Register to set both the
Register Write Enable Latch (RWEL) and the WEL
bit. This is also a volatile cycle. The zeros in the data
byte are required. (Operation preceeded by a start
and ended with a stop).
DTR1 and DTR0 are scale bits. DTR1 gives 10 ppm
adjustment and DTR0 gives 20 ppm adjustment.
A range from -30ppm to +30ppm can be represented
by using three bits above.
– Write one to 8 bytes to the Clock/Control Registers
with the desired clock, alarm, or control data. This
sequence starts with a start bit, requires a slave byte
of “11011110” and an address within the CCR and is
terminated by a stop bit. A write to the CCR changes
EEPROM values so these initiate a nonvolatile write
cycle and will take up to 10ms to complete. Writes to
undefined areas have no effect. The RWEL bit is
reset by the completion of a nonvolatile write cycle,
so the sequence must be repeated to again initiate
another change to the CCR contents. If the
Table 5. Digital Trimming Registers
DTR Register
Estimated frequency
DTR2
DTR1
DTR0
PPM
0
0
0
0
1
1
1
1
0
1
0
1
0
1
0
1
0
0
1
1
0
0
1
1
0
+10
+20
+30
0
-10
-20
-30
sequence is not completed for any reason (by send-
ing an incorrect number of bits or sending a start
instead of a stop, for example) the RWEL bit is not
reset and the device remains in an active mode.
– Writing all zeros to the status register resets both the
WEL and RWEL bits.
Analog Trimming Register (ATR) (Non-volatile)
Six analog trimming Bits from ATR5 to ATR0 are pro-
vided to adjust the on-chip loading capacitance range.
The on-chip load capacitance ranges from 3.25pF to
18.75pF. Each bit has a different weight for capaci-
tance adjustment. Using a Citizen CFS-206 crystal
– A read operation occurring between any of the previ-
ous operations will not interrupt the register write
operation.
FN8098.3
May 8, 2006
9
X1226
SERIAL COMMUNICATION
Interface Conventions
Acknowledge
Acknowledge is a software convention used to indi-
cate successful data transfer. The transmitting device,
either master or slave, will release the bus after trans-
mitting eight bits. During the ninth clock cycle, the
receiver will pull the SDA line LOW to acknowledge
that it received the eight bits of data. Refer to Figure 5.
The device supports a bidirectional bus oriented proto-
col. The protocol defines any device that sends data
onto the bus as a transmitter, and the receiving device
as the receiver. The device controlling the transfer is
called the master and the device being controlled is
called the slave. The master always initiates data
transfers, and provides the clock for both transmit and
receive operations. Therefore, the devices in this fam-
ily operate as slaves in all applications.
The device will respond with an acknowledge after
recognition of a start condition and if the correct
Device Identifier and Select bits are contained in the
Slave Address Byte. If a write operation is selected,
the device will respond with an acknowledge after the
receipt of each subsequent eight bit word. The device
will acknowledge all incoming data and address bytes,
except for:
Clock and Data
Data states on the SDA line can change only during
SCL LOW. SDA state changes during SCL HIGH are
reserved for indicating start and stop conditions. See
Figure 3.
– The Slave Address Byte when the Device Identifier
and/or Select bits are incorrect
– All Data Bytes of a write when the WEL in the Write
Protect Register is LOW
Start Condition
All commands are preceded by the start condition,
which is a HIGH to LOW transition of SDA when SCL
is HIGH. The device continuously monitors the SDA
and SCL lines for the start condition and will not
respond to any command until this condition has been
met. See Figure 4.
– The 2nd Data Byte of a Status Register Write Oper-
ation (only 1 data byte is allowed)
In the read mode, the device will transmit eight bits of
data, release the SDA line, then monitor the line for an
acknowledge. If an acknowledge is detected and no
stop condition is generated by the master, the device
will continue to transmit data. The device will terminate
further data transmissions if an acknowledge is not
detected. The master must then issue a stop condition
to return the device to Standby mode and place the
device into a known state.
Stop Condition
All communications must be terminated by a stop
condition, which is a LOW to HIGH transition of SDA
when SCL is HIGH. The stop condition is also used to
place the device into the Standby power mode after a
read sequence. A stop condition can only be issued
after the transmitting device has released the bus. See
Figure 4.
Figure 3. Valid Data Changes on the SDA Bus
SCL
SDA
Data Stable
Data Change
Data Stable
FN8098.3
May 8, 2006
10
X1226
Figure 4. Valid Start and Stop Conditions
SCL
SDA
Start
Stop
Figure 5. Acknowledge Response From Receiver
SCL from
Master
1
8
9
Data Output
from Transmitter
Data Output
from Receiver
Start
Acknowledge
DEVICE ADDRESSING
Following a start condition, the master must output a
Slave Address Byte. The first four bits of the Slave
Address Byte specify access to either the EEPROM
array or to the CCR. Slave bits ‘1010’ access the
EEPROM array. Slave bits ‘1101’ access the CCR.
Following the Slave Byte is a two byte word address.
The word address is either supplied by the master
device or obtained from an internal counter. On power-
up the internal address counter is set to address 0h,
so a current address read of the EEPROM array starts
at address 0. When required, as part of a random
read, the master must supply the 2 Word Address
Bytes as shown in Figure 6.
When shipped from the factory, EEPROM array is
UNDEFINED, and should be programmed by the cus-
tomer to a known state.
In a random read operation, the slave byte in the
“dummy write” portion must match the slave byte in
the “read” section. That is if the random read is from
the array the slave byte must be 1010111x in both
instances. Similarly, for a random read of the
Clock/Control Registers, the slave byte must be
1101111x in both places.
Bit 3 through Bit 1 of the slave byte specify the device
select bits. These are set to ‘111’.
The last bit of the Slave Address Byte defines the
operation to be performed. When this R/W bit is a one,
then a read operation is selected. A zero selects a
write operation. Refer to Figure 6.
After loading the entire Slave Address Byte from the
SDA bus, the X1226 compares the device identifier
and device select bits with ‘1010111’ or ‘1101111’.
Upon a correct compare, the device outputs an
acknowledge on the SDA line.
FN8098.3
May 8, 2006
11
X1226
Figure 6. Slave Address, Word Address, and Data Bytes (64 Byte pages)
Device Identifier
Array
CCR
Slave Address Byte
Byte 0
1
1
0
1
1
0
0
1
1
0
1
1
0
R/W
A8
Word Address 1
Byte 1
0
0
0
0
0
Word Address 0
Byte 2
A7
D7
A6
D6
A5
D5
A4
D4
A3
D3
A2
D2
A1
D1
A0
D0
Data Byte
Byte 3
Write Operations
Byte Write
an acknowledge. After receiving both address bytes
the X1226 awaits the eight bits of data. After receiving
the 8 data bits, the X1226 again responds with an
acknowledge. The master then terminates the transfer
by generating a stop condition. The X1226 then
begins an internal write cycle of the data to the nonvol-
atile memory. During the internal write cycle, the
device inputs are disabled, so the device will not
respond to any requests from the master. The SDA out-
put is at high impedance. See Figure 7.
For a write operation, the device requires the Slave
Address Byte and the Word Address Bytes. This gives
the master access to any one of the words in the array
or CCR. (Note: Prior to writing to the CCR, the master
must write a 02h, then 06h to the status register in two
preceding operations to enable the write operation.
See “Writing to the Clock/Control Registers.” Upon
receipt of each address byte, the X1226 responds with
Figure 7. Byte Write Sequence
S
t
a
r
Signals from
the Master
S
t
Word
Address 1
Word
Address 0
Slave
Address
o
p
t
Data
SDA Bus
1
1 1 1 0 0 0 0 0 0 0 0
A
C
K
A
C
K
A
C
K
A
C
K
Signals From
The Slave
Figure 8. Writing 30 bytes to a 64-byte memory page starting at address 40.
7 Bytes
23 Bytes
Address Pointer
Ends Here
Addr = 7
Address
Address
= 6
Address
40
63
FN8098.3
May 8, 2006
12
X1226
A write to a protected block of memory is ignored, but
will still receive an acknowledge. At the end of the
write command, the X1226 will not initiate an internal
write cycle, and will continue to ACK commands.
page. For example, if the master begins writing at
location 60 of the memory and loads 30 bytes, then
the first 23 bytes are written to addresses 40 through
63, and the last 7 bytes are written to columns 0
through 6. Afterwards, the address counter would
point to location 7 on the page that was just written. If
the master supplies more than the maximum bytes in
a page, then the previously loaded data is over written
by the new data, one byte at a time. Refer to Figure 8.
The master terminates the Data Byte loading by issu-
ing a stop condition, which causes the X1226 to begin
the nonvolatile write cycle. As with the byte write oper-
ation, all inputs are disabled until completion of the
internal write cycle. Refer to Figure 9 for the address,
acknowledge, and data transfer sequence.
Page Write
The X1226 has a page write operation. It is initiated in
the same manner as the byte write operation; but
instead of terminating the write cycle after the first data
byte is transferred, the master can transmit up to 63
more bytes to the memory array and up to 7 more
bytes to the clock/control registers. (Note: Prior to writ-
ing to the CCR, the master must write a 02h, then 06h
to the status register in two preceding operations to
enable the write operation. See “Writing to the
Clock/Control Registers.”
Stops and Write Modes
After the receipt of each byte, the X1226 responds
with an acknowledge, and the address is internally
incremented by one. When the counter reaches the
end of the page, it “rolls over” and goes back to the
first address on the same page. This means that the
master can write 64 bytes to a memory array page or 8
bytes to a CCR section starting at any location on that
Stop conditions that terminate write operations must be
sent by the master after sending at least 1 full data byte
and it’s associated ACK signal. If a stop is issued in the
middle of a data byte, or before 1 full data byte + ACK is
sent, then the X1226 resets itself without performing the
write. The contents of the array are not affected.
Figure 9. Page Write Sequence
1 ≤ n ≤ 64 for EEPROM array
1 ≤ n ≤ 8 for CCR
S
t
a
r
Signals from
the Master
S
t
o
p
Word
Address 1
Slave
Address
Word
Address 0
Data
(1)
Data
(n)
t
SDA Bus
1
1 1 1 0
0 0 0 0 0 0 0
A
C
K
A
C
K
A
C
K
A
C
K
Signals from
the Slave
FN8098.3
May 8, 2006
13
X1226
Acknowledge Polling
Figure 11. Acknowledge Polling Sequence
Disabling of the inputs during nonvolatile write cycles
can be used to take advantage of the typical 5mS write
cycle time. Once the stop condition is issued to indi-
cate the end of the master’s byte load operation, the
X1226 initiates the internal nonvolatile write cycle.
Acknowledge polling can begin immediately. To do
this, the master issues a start condition followed by the
Memory Array Slave Address Byte for a write or read
operation (AEh or AFh). If the X1226 is still busy with
the nonvolatile write cycle then no ACK will be
returned. When the X1226 has completed the write
operation, an ACK is returned and the host can pro-
ceed with the read or write operation. Refer to the flow
chart in Figure 11. Note: Do not use the CCR Salve
byte (DEh or DFh) for Acknowledge Polling.
Byte load completed
by issuing STOP.
Enter ACK Polling
Issue START
Issue Memory Array Slave
Address Byte
AFh (Read) or AEh (Write)
Issue STOP
NO
ACK
returned?
YES
Read Operations
NO
There are three basic read operations: Current
Address Read, Random Read, and Sequential Read.
nonvolatile write
Cycle complete. Continue
command sequence?
Issue STOP
Current Address Read
YES
Internally the X1226 contains an address counter that
maintains the address of the last word read incre-
mented by one. Therefore, if the last read was to
address n, the next read operation would access data
from address n+1. On power-up, the sixteen bit
address is initialized to 0h. In this way, a current
address read immediately after the power-on reset
can download the entire contents of memory starting
at the first location.Upon receipt of the Slave Address
Byte with the R/W bit set to one, the X1226 issues an
acknowledge, then transmits eight data bits. The mas-
ter terminates the read operation by not responding
with an acknowledge during the ninth clock and issu-
ing a stop condition. Refer to Figure 10 for the
address, acknowledge, and data transfer sequence.
Continue normal
Read or Write
command
sequence
PROCEED
It should be noted that the ninth clock cycle of the read
operation is not a “don’t care.” To terminate a read
operation, the master must either issue a stop condi-
tion during the ninth cycle or hold SDA HIGH during
the ninth clock cycle and then issue a stop condition.
Figure 10. Current Address Read Sequence
S
t
S
t
o
p
Signals from
a
Slave
Address
the Master
r
t
SDA Bus
1
1 1 1 1
A
C
K
Signals from
the Slave
Data
FN8098.3
May 8, 2006
14
X1226
Random Read
read from the newly loaded address. This operation
could be useful if the master knows the next address it
needs to read, but is not ready for the data.
Random read operations allow the master to access
any location in the X1226. Prior to issuing the Slave
Address Byte with the R/W bit set to zero, the master
must first perform a “dummy” write operation.
Sequential Read
Sequential reads can be initiated as either a current
address read or random address read. The first data
byte is transmitted as with the other modes; however,
the master now responds with an acknowledge, indi-
cating it requires additional data. The device continues
to output data for each acknowledge received. The
master terminates the read operation by not responding
with an acknowledge and then issuing a stop condition.
The master issues the start condition and the slave
address byte, receives an acknowledge, then issues
the word address bytes. After acknowledging receipt
of each word address byte, the master immediately
issues another start condition and the slave address
byte with the R/W bit set to one. This is followed by an
acknowledge from the device and then by the eight bit
data word. The master terminates the read operation
by not responding with an acknowledge and then issu-
ing a stop condition. Refer to Figure 12 for the
address, acknowledge, and data transfer sequence.
The data output is sequential, with the data from
address n followed by the data from address n + 1.
The address counter for read operations increments
through all page and column addresses, allowing the
entire memory contents to be serially read during one
operation. At the end of the address space the counter
“rolls over” to the start of the address space and the
X1226 continues to output data for each acknowledge
received. Refer to Figure 13 for the acknowledge and
data transfer sequence.
In a similar operation called “Set Current Address,” the
device sets the address if a stop is issued instead of
the second start shown in Figure 12. The X1226 then
goes into standby mode after the stop and all bus
activity will be ignored until a start is detected. This
operation loads the new address into the address
counter. The next Current Address Read operation will
Figure 12. Random Address Read Sequence
S
t
S
S
t
o
p
t
a
r
Signals from
the Master
Slave
Address
Word
Address 0
a
r
Slave
Address
Word
Address 1
t
t
SDA Bus
1
1 1 1 1
1
1 1 1 0
0 0 0 0 0 0 0
A
C
K
A
C
K
A
C
K
A
C
K
Signals from
the Slave
Data
Figure 13. Sequential Read Sequence
S
t
o
p
Slave
Address
A
C
K
A
C
K
A
C
K
Signals from
the Master
SDA Bus
1
A
C
K
Signals from
the Slave
Data
(2)
Data
(n-1)
Data
(1)
Data
(n)
(n is any integer greater than 1)
FN8098.3
May 8, 2006
15
X1226
ABSOLUTE MAXIMUM RATINGS
COMMENT
Temperature Under Bias................... -65°C to +135°C
Storage Temperature ........................ -65°C to +150°C
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only and the functional operation
of the device at these or any other conditions above
those indicated in the operational sections of this
specification is not implied. Exposure to absolute max-
imum rating conditions for extended periods may
affect device reliability.
Voltage on V , V
and PHZ/IRQ
CC BACK
pin (respect to ground) ............................-0.5V to 7.0V
Voltage on SCL, SDA, X1 and X2
pin (respect to ground) ............... -0.5V to 7.0V or 0.5V
above V or V
(whichever is higher)
CC
BACK
DC Output Current ..............................................5 mA
Lead Temperature (Soldering, 10s)................... 300°C
DC OPERATING CHARACTERISTICS (Temperature = -40°C to +85°C, unless otherwise stated.)
Symbol
VCC
Parameter
Conditions
Min
2.7
Typ
Max
5.5
Unit
V
Notes
Main Power Supply
Backup Power Supply
Switch to Backup Supply
Switch to Main Supply
VBACK
VCB
1.8
5.5
V
VBACK -0.2
VBACK
VBACK -0.1
VBACK +0.2
V
VBC
V
OPERATING CHARACTERISTICS
Symbol
Parameter
Conditions
Min
Typ
Max
400
800
2.5
3.0
10
Unit
µA
Notes
VCC = 2.7V
Read Active Supply Cur-
rent
ICC1
1, 5, 7, 14
V
CC = 5.0V
VCC = 2.7V
CC = 5.0V
VCC = 2.7V
CC = 5.0V
BACK = 1.8V
µA
mA
mA
µA
Program Supply Current
(nonvolatile)
ICC2
ICC3
2, 5, 7, 14
V
Main Timekeeping
Current
3, 7, 8, 14, 15
V
20
µA
V
1.25
1.5
µA
3, 6, 9, 14, 15
“See Perfor-
mance Data”
IBACK
Timekeeping Current
VBACK = 3.3V
µA
ILI
Input Leakage Current
Output Leakage Current
10
10
µA
µA
10
10
ILO
V
CC x 0.2 or
VIL
VIH
Input LOW Voltage
Input HIGH Voltage
-0.5
V
V
V
13
13
13
VBACK x 0.2
V
V
CC x 0.7 or
BACK x 0.7
VCC + 0.5 or
V
BACK + 0.5
Schmitt Trigger Input
Hysteresis
.05 x VCC or
.05 x VBACK
VHYS
VCC related level
VCC = 2.7V
VCC = 5.5V
VCC = 2.7V
0.4
0.4
Output LOW Voltage for
SDA
VOL1
VOL2
VOH2
V
V
V
11
11
12
VCC x 0.3
VCC x 0.3
Output LOW Voltage for
PHZ/IRQ
V
CC = 5.5V
VCC = 2.7V
CC = 5.5V
VCC x 0.7
VCC x 0.7
Output HIGH Voltage for
PHZ/IRQ
V
FN8098.3
May 8, 2006
16
X1226
Notes: (1) The device enters the Active state after any start, and remains active: for 9 clock cycles if the Device Select Bits in the Slave Address
Byte are incorrect or until 200nS after a stop ending a read or write operation.
(2) The device enters the Program state 200nS after a stop ending a write operation and continues for tWC
.
(3) The device goes into the Timekeeping state 200nS after any stop, except those that initiate a nonvolatile write cycle; tWC after a stop
that initiates a nonvolatile write cycle; or 9 clock cycles after any start that is not followed by the correct Device Select Bits in the Slave
Address Byte.
(4) For reference only and not tested.
(5)
(6)
(7)
(8)
V
V
V
V
IL = VCC x 0.1, VIH = VCC x 0.9, fSCL = 400KHz
CC = 0V
BACK = 0V
SDA = VSCL=VCC, Others = GND or VCC
(9) VSDA =VSCL=VBACK, Others = GND or VBACK
(10) VSDA = GND or VCC, VSCL = GND or VCC
(11) IOL = 3.0mA at 5.5V, 1.5mA at 2.7V
(12) IOH = -1.0mA at 5.5V, -0.4mA at 2.7V
(13) Threshold voltages based on the higher of Vcc or Vback.
(14) Using recommended crystal and oscillator network applied to X1 and X2 (25°C).
(15) Typical values are for TA = 25°C
Capacitance T = 25°C, f = 1.0 MHz, V = 5V
A
CC
Symbol
Parameter
Max.
10
Units
pF
Test Conditions
VOUT = 0V
(1)
COUT
Output Capacitance (SDA, PHZ/IRQ)
Input Capacitance (SCL)
(1)
CIN
10
pF
VIN = 0V
Notes: (1) This parameter is not 100% tested.
(2) The input capacitance between x1 and x2 pins can be varied between 5pF and 19.75pF by using analog trimming registers
AC CHARACTERISTICS
AC Test Conditions
Input Pulse Levels
VCC x 0.1 to VCC x 0.9
Input Rise and Fall Times
10ns
Input and Output Timing
Levels
VCC x 0.5
Output Load
Standard Output Load
Figure 14. Standard Output Load for testing the device with V = 5.0V
CC
Equivalent AC Output Load Circuit for V = 5V
CC
5.0V
5.0V
For VOL= 0.4V
1316Ω
806Ω
1533Ω
and IOL = 3 mA
PHZ/IRQ
SDA
100pF
100pF
FN8098.3
May 8, 2006
17
X1226
AC Specifications (T = -40°C to +85°C, VCC = +2.7V to +5.5V, unless otherwise specified.)
A
Symbol
Parameter
Min.
Max. Units
fSCL
tIN
SCL Clock Frequency
400
kHz
ns
μs
μs
μs
μs
μs
μs
ns
μs
μs
ns
ns
ns
pF
Pulse width Suppression Time at inputs
SCL LOW to SDA Data Out Valid
Time the bus must be free before a new transmission can start
Clock LOW Time
50(1)
tAA
0.1
0.9
tBUF
1.3
tLOW
tHIGH
tSU:STA
tHD:STA
tSU:DAT
tHD:DAT
tSU:STO
tDH
1.3
Clock HIGH Time
0.6
Start Condition Setup Time
Start Condition Hold Time
Data In Setup Time
0.6
0.6
100
Data In Hold Time
0
0.6
Stop Condition Setup Time
Data Output Hold Time
50
tR
SDA and SCL Rise Time
20 +.1Cb(2)
20 +.1Cb(2)
300
300
400
tF
SDA and SCL Fall Time
Cb
Capacitive load for each bus line
Notes: (1) This parameter is not 100% tested.
(2) Cb = total capacitance of one bus line in pF.
TIMING DIAGRAMS
Bus Timing
tF
tHIGH
tLOW
tR
SCL
tSU:DAT
tSU:STA
tHD:DAT
tSU:STO
tHD:STA
SDA IN
tAA tDH
tBUF
SDA OUT
FN8098.3
May 8, 2006
18
X1226
Write Cycle Timing
SCL
SDA
8th Bit of Last Byte
ACK
tWC
Stop
Condition
Start
Condition
Power-up Timing
Symbol
(2)
Parameter
Min.
Typ.
Max.
Units
ms
(1)
tPUR
Time from Power-up to Read
Time from Power-up to Write
1
5
(1)
tPUW
ms
Notes: (1) Delays are measured from the time VCC is stable until the specified operation can be initiated. These parameters are not 100% tested.
CC slew rate should be between 0.2mV/µsec and 50mV/µsec.
V
(2) Typical values are for TA = 25°C and VCC = 5.0V
Nonvolatile Write Cycle Timing
(1)
Symbol
Parameter
Write Cycle Time
Min.
Typ.
Max.
Units
(1)
tWC
5
10
ms
Note: (1) tWC is the time from a valid stop condition at the end of a write sequence to the end of the self-timed internal nonvolatile write cycle. It is
the minimum cycle time to be allowed for any nonvolatile write by the user, unless Acknowledge Polling is used.
FN8098.3
May 8, 2006
19
X1226
APPLICATION SECTION
the temperature extremes of -40 and +85 deg C. It is
possible to address this variable drift by adjusting the
load capacitance of the crystal, which will result in pre-
dictable change to the crystal frequency. The Intersil
RTC family allows this adjustment over temperature
since the devices include on-chip load capacitor trim-
ming. This control is handled by the Analog Trimming
Register, or ATR, which has 6 bits of control. The load
capacitance range covered by the ATR circuit is
approximately 3.25pF to 18.75pF, in 0.25pf incre-
ments. Note that actual capacitance would also
include about 2pF of package related capacitance. In-
circuit tests with commercially available crystals dem-
onstrate that this range of capacitance allows fre-
quency control from +116ppm to -37ppm, using a
12.5pF load crystal.
CRYSTAL OSCILLATOR AND TEMPERATURE
COMPENSATION
Intersil has now integrated the oscillator compensation
circuity on-chip, to eliminate the need for external
components and adjust for crystal drift over tempera-
ture and enable very high accuracy time keeping
(<5ppm drift).
The Intersil RTC family uses an oscillator circuit with
on-chip crystal compensation network, including
adjustable load-capacitance. The only external com-
ponent required is the crystal. The compensation net-
work is optimized for operation with certain crystal
parameters which are common in many of the surface
mount or tuning-fork crystals available today. Table 6
summarizes these parameters.
In addition to the analog compensation afforded by the
adjustable load capacitance, a digital compensation
feature is available for the Intersil RTC family. There
are three bits known as the Digital Trimming Register
or DTR, and they operate by adding or skipping pulses
in the clock signal. The range provided is ±30ppm in
increments of 10ppm. The default setting is 0ppm. The
DTR control can be used for coarse adjustments of
frequency drift over temperature or for crystal initial
accuracy correction.
Table 7 contains some crystal manufacturers and part
numbers that meet the requirements for the Intersil
RTC products.
The turnover temperature in Table 6 describes the
temperature where the apex of the of the drift vs. tem-
perature curve occurs. This curve is parabolic with the
drift increasing as (T-T0) . For an Epson MC-405
device, for example, the turnover temperature is typi-
cally 25 deg C, and a peak drift of >110ppm occurs at
2
Table 6. Crystal Parameters Required for Intersil RTC’s
Parameter
Min
Typ
Max
Units
kHz
Notes
Frequency
32.768
Freq. Tolerance
±100
30
ppm
Down to 20ppm if desired
Typically the value used for most
crystals
Turnover Temperature
20
25
°C
Operating Temperature Range
Parallel Load Capacitance
Equivalent Series Resistance
-40
85
°C
pF
kΩ
12.5
50
For best oscillator performance
Table 7. Crystal Manufacturers
Manufacturer
Citizen
Part Number
CM201, CM202, CM200S
MC-405, MC-406
RSM-200S-A or B
32S12A or B
Temp Range
-40 to +85°C
-40 to +85°C
-40 to +85°C
-40 to +85°C
-10 to +60°C
-10 to +60°C
-40 to +85°C
+25°C Freq Toler.
±20ppm
Epson
±20ppm
Raltron
SaRonix
Ecliptek
ECS
±20ppm
±20ppm
ECPSM29T-32.768K
ECX-306/ECX-306I
FSM-327
±20ppm
±20ppm
Fox
±20ppm
FN8098.3
May 8, 2006
20
X1226
A final application for the ATR control is in-circuit cali-
bration for high accuracy applications, along with a
temperature sensor chip. Once the RTC circuit is
powered up with battery backup, the PHZ output is
set at 32.768kHz and frequency drift is measured.
The ATR control is then adjusted to a setting which
minimizes drift. Once adjusted at a particular temper-
ature, it is possible to adjust at other discrete temper-
atures for minimal overall drift, and store the resulting
settings in the EEPROM. Extremely low overall tem-
perature drift is possible with this method. The Intersil
evaluation board contains the circuitry necessary to
implement this control.
The X1226 product has a special consideration. The
PHZ/IRQ- pin on the 8 Ld SOIC package is located
next to the X2 pin. When this pin is used as a fre-
quency output (PHZ) and is set to 32.768kHz output
frequency, noise can couple to the X1 or X2 pins and
cause double-clocking. The layout in figure 15 can
help minimize this by running the PHZ output away
from the X1 and X2 pins. Also, minimizing the switch-
ing current at this pin by careful selection of the pullup
resistor value will reduce noise. Intersil suggests a
minimum value of 5.1kΩ for 32.768kHz, and higher
values (up to 20kΩ) for lower frequency PHZ outputs.
For other RTC products, the same rules stated above
should be observed, but adjusted slightly since the
packages and pinouts are slightly different.
For more detailed operation see Intersil’s application
note AN154 on Intersil’s website at www.intersil.com.
Layout Considerations
Assembly
The crystal input at X1 has a very high impedance and
will pick up high frequency signals from other circuits on
the board. Since the X2 pin is tied to the other side of
the crystal, it is also a sensitive node. These signals can
couple into the oscillator circuit and produce double
clocking or mis-clocking, seriously affecting the accu-
racy of the RTC. Care needs to be taken in layout of the
RTC circuit to avoid noise pickup. Below in Figure 15 is
a suggested layout for the X1226 or X1227 devices.
Most electronic circuits do not have to deal with
assembly issues, but with the RTC devices assembly
includes insertion or soldering of a live battery into an
unpowered circuit. If a socket is soldered to the board,
and a battery is inserted in final assembly, then there
are no issues with operation of the RTC. If the battery
is soldered to the board directly, then the RTC device
Vback pin will see some transient upset from either
soldering tools or intermittent battery connections
which can stop the circuit from oscillating. Once the
battery is soldered to the board, the only way to assure
the circuit will start up is to momentarily (very short
period of time!) short the Vback pin to ground and the
circuit will begin to oscillate.
Figure 15. Suggested Layout for Intersil RTC in SO-8
Oscillator Measurements
When a proper crystal is selected and the layout guide-
lines above are observed, the oscillator should start up
in most circuits in less than one second. Some circuits
may take slightly longer, but startup should definitely
occur in less than 5 seconds. When testing RTC cir-
cuits, the most common impulse is to apply a scope
probe to the circuit at the X2 pin (oscillator output) and
observe the waveform. DO NOT DO THIS! Although in
some cases you may see a useable waveform, due to
the parasitics (usually 10pF to ground) applied with the
scope probe, there will be no useful information in that
waveform other than the fact that the circuit is oscillat-
ing. The X2 output is sensitive to capacitive impedance
so the voltage levels and the frequency will be affected
by the parasitic elements in the scope probe. Applying a
scope probe can possibly cause a faulty oscillator to
start up, hiding other issues (although in the Intersil
RTC’s, the internal circuitry assures startup when using
the proper crystal and layout).
The X1 and X2 connections to the crystal are to be
kept as short as possible. A thick ground trace around
the crystal is advised to minimize noise intrusion, but
ground near the X1 and X2 pins should be avoided as
it will add to the load capacitance at those pins. Keep
in mind these guidelines for other PCB layers in the
vicinity of the RTC device. A small decoupling capaci-
tor at the Vcc pin of the chip is mandatory, with a solid
connection to ground.
FN8098.3
May 8, 2006
21
X1226
The best way to analyze the RTC circuit is to power it
up and read the real time clock as time advances, or if
the chip has the PHZ output, look at the output of that
pin on an oscilloscope (after enabling it with the con-
trol register, and using a pullup resistor for an open-
drain output). Alternaltively, the X1226 device has an
IRQ- output which can be checked by setting an alarm
for each minute. Using the pulse interrupt mode set-
ting, the once-per-minute interrupt functions as an
indication of proper oscillation.
pacitor, which is connected to the Vback pin. Do not
use the diode to charge a battery (especially lithium
batteries!).
Figure 16. Supercapactor charging circuit
2.7-5.5V
VCC
Vback
Supercapacitor
Backup Battery Operation
VSS
Many types of batteries can be used with the Intersil
RTC products. 3.0V or 3.6V Lithium batteries are
appropriate, and sizes are available that can power a
Intersil RTC device for up to 10 years. Another option
is to use a supercapacitor for applications where Vcc
may disappear intermittently for short periods of time.
Depending on the value of supercapacitor used,
backup time can last from a few days to two weeks
(with >1F). A simple silicon or Schottky barrier diode
can be used in series with Vcc to charge the superca-
Since the battery switchover occurs at Vcc = Vback-
0.1V (see Figure 16), the battery voltage must always
be lower than the Vcc voltage during normal operation
or the battery will be drained.
The summary of conditions for backup battery opera-
tion is given in Table 8:
Table 8. Battery Backup Operation
1. Example Application, Vcc=5V, Vback=3.0V
Condition
a. Normal Operation
Vcc
5.00
Vback
Vtrip
4.38
4.38
4.38
Iback
<<1µA
0
Notes
3.00
0
b. Vcc on with no battery
c. Backup Mode
5.00
0–1.8
1.8-3.0
<2µA
Timekeeping only
2. Example Application, Vcc=3.3V,Vback=3.0V
Condition Vcc
a. Normal Operation
Vback
3.00
Vtrip
2.65
2.65
2.65
Iback
<<1µA
0
3.30
3.30
b. Vcc on with no battery
c. Backup Mode
0
0–1.8
1.8–3.0*
<2µA*
Timekeeping only
d. UNWANTED - Vcc ON, Vback
powering
Internal
Vcc = Vback
2.65 - 3.30
> Vcc
2.65
up to 3mA
*since Vback>2.65V is higher than Vtrip, the battery is powering the entire device
FN8098.3
May 8, 2006
22
X1226
Referring to Figure 16, Vtrip applies to the “Internal
Vcc” node which powers the entire device. This means
that if Vcc is powered down and the battery voltage at
Vback is higher than the Vtrip voltage, then the entire
chip will be running from the battery. If Vback falls to
lower than Vtrip, then the chip shuts down and all out-
puts are disabled except for the oscillator and time-
keeping circuitry. The fact that the chip can be
powered from Vback is not necessarily an issue since
standby current for the RTC devices is <2µA for this
mode (called “main timekeeping current” in the data
sheet). Only when the serial interface is active is there
an increase in supply current, and with Vcc powered
down, the serial interface will most likely be inactive.
PERFORMANCE DATA
Performance
I
BACK
IBACK vs. Temperature
Multi-Lot Process Variation Data
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
3.3V
1.8V
One way to prevent operation in battery backup mode
above the Vtrip level is to add a diode drop (silicon
diode preferred) to the battery to insure it is below
Vtrip. This will also provide reverse leakage protection
which may be needed to get safety agency approval.
-40
25
60
85
Temperature °C
One mode that should always be avoided is the oper-
ation of the RTC device with Vback greater than both
Vcc and Vtrip (Condition 2d in Table 8). This will
cause the battery to drain quickly as serial bus com-
munication and non-volatile writes will require higher
supplier current.
FN8098.3
May 8, 2006
23
X1226
Small Outline Package Family (SO)
A
D
h X 45°
(N/2)+1
N
A
PIN #1
I.D. MARK
E1
E
c
SEE DETAIL “X”
1
(N/2)
B
L1
0.010 M
C A B
e
H
C
A2
A1
GAUGE
PLANE
SEATING
PLANE
0.010
L
4° ±4°
0.004 C
b
0.010 M
C
A
B
DETAIL X
MDP0027
SMALL OUTLINE PACKAGE FAMILY (SO)
SO16
(0.150”)
SO16 (0.300”)
(SOL-16)
SO20
SO24
(SOL-24)
SO28
(SOL-28)
SYMBOL
SO-8
0.068
0.006
0.057
0.017
0.009
0.193
0.236
0.154
0.050
0.025
0.041
0.013
8
SO-14
0.068
0.006
0.057
0.017
0.009
0.341
0.236
0.154
0.050
0.025
0.041
0.013
14
(SOL-20)
0.104
0.007
0.092
0.017
0.011
0.504
0.406
0.295
0.050
0.030
0.056
0.020
20
TOLERANCE
MAX
NOTES
A
A1
A2
b
0.068
0.006
0.057
0.017
0.009
0.390
0.236
0.154
0.050
0.025
0.041
0.013
16
0.104
0.007
0.092
0.017
0.011
0.406
0.406
0.295
0.050
0.030
0.056
0.020
16
0.104
0.007
0.092
0.017
0.011
0.606
0.406
0.295
0.050
0.030
0.056
0.020
24
0.104
0.007
0.092
0.017
0.011
0.704
0.406
0.295
0.050
0.030
0.056
0.020
28
-
±0.003
±0.002
±0.003
±0.001
±0.004
±0.008
±0.004
Basic
-
-
-
c
-
D
1, 3
E
-
E1
e
2, 3
-
L
±0.009
Basic
-
L1
h
-
Reference
Reference
-
N
-
Rev. L 2/01
NOTES:
1. Plastic or metal protrusions of 0.006” maximum per side are not included.
2. Plastic interlead protrusions of 0.010” maximum per side are not included.
3. Dimensions “D” and “E1” are measured at Datum Plane “H”.
4. Dimensioning and tolerancing per ASME Y14.5M-1994
FN8098.3
May 8, 2006
24
X1226
Thin Shrink Small Outline Plastic Packages (TSSOP)
M8.173
N
8 LEAD THIN SHRINK NARROW BODY SMALL OUTLINE
PLASTIC PACKAGE
INDEX
AREA
0.25(0.010)
M
B M
E
E1
-B-
INCHES
MIN
MILLIMETERS
GAUGE
PLANE
SYMBOL
MAX
0.047
0.006
0.051
0.0118
0.0079
0.120
0.177
MIN
-
MAX
1.20
0.15
1.05
0.30
0.20
3.05
4.50
NOTES
A
A1
A2
b
-
-
1
2
3
0.002
0.031
0.0075
0.0035
0.116
0.169
0.05
0.80
0.19
0.09
2.95
4.30
-
L
0.25
0.010
-
0.05(0.002)
SEATING PLANE
A
9
-A-
D
c
-
D
3
-C-
α
E1
e
4
A2
e
A1
0.026 BSC
0.65 BSC
-
c
b
0.10(0.004)
E
0.246
0.256
6.25
0.45
6.50
0.75
-
0.10(0.004) M
C
A M B S
L
0.0177
0.0295
6
N
8
8
7
NOTES:
0o
8o
0o
8o
-
α
1. These package dimensions are within allowable dimensions of
JEDEC MO-153-AC, Issue E.
Rev. 1 12/00
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm
(0.006 inch) per side.
4. Dimension “E1” does not include interlead flash or protrusions. Inter-
lead flash and protrusions shall not exceed 0.15mm (0.006 inch) per
side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “b” does not include dambar protrusion. Allowable dambar
protrusion shall be 0.08mm (0.003 inch) total in excess of “b” dimen-
sion at maximum material condition. Minimum space between protru-
sion and adjacent lead is 0.07mm (0.0027 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact. (Angles in degrees)
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN8098.3
May 8, 2006
25
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