X1227S8Z-2.7A [RENESAS]
1 TIMER(S), REAL TIME CLOCK, PDSO8, ROHS COMPLIANT, PLASTIC, SOIC-8;
| 型号： | X1227S8Z-2.7A |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | 1 TIMER(S), REAL TIME CLOCK, PDSO8, ROHS COMPLIANT, PLASTIC, SOIC-8 时钟 光电二极管 外围集成电路 |
| 文件： | 总28页 (文件大小：1080K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATASHEET
X1227
FN8099
Rev 2.00
May 8, 2006
2-Wire™ RTC Real TimeClock/Calendar/CPU Supervisor with EEPROM
FEATURES
APPLICATIONS
• Real Time Clock/Calendar
• Utility Meters
• HVAC Equipment
• Audio/Video Components
• Set Top Box/Television
• Modems
— Tracks Time in Hours, Minutes, and Seconds
— Day of the Week, Day, Month, and Year
• 2 Polled Alarms (Non-volatile)
— Settable on the Second, Minute, Hour, Day of the
Week, Day, or Month
• Network Routers, Hubs, Switches, Bridges
• Cellular Infrastructure Equipment
• Fixed Broadband Wireless Equipment
• Pagers/PDA
• POS Equipment
• Test Meters/Fixtures
• Office Automation (Copiers, Fax)
• Home Appliances
• Computer Products
— Repeat Mode (periodic interrupts)
• Oscillator Compensation on Chip
— Internal Feedback Resistor and Compensation
Capacitors
— 64 Position Digitally Controlled Trim Capacitor
— 6 Digital Frequency Adjustment Settings to ±30ppm
• CPU Supervisor Functions
— Power-On Reset, Low Voltage Sense
— Watchdog Timer (SW Selectable: 0.25s, 0.75s,
1.75s, off)
• Other Industrial/Medical/Automotive
• Battery Switch or Super Cap Input
• 512 x 8 Bits of EEPROM
— 64-Byte Page Write Mode
— 8 Modes of Block Lock™ Protection
— Single Byte Write Capability
• High Reliability
— Data Retention: 100 Years
— Endurance: 100,000 Cycles Per Byte
• 2-Wire™ Interface Interoperable with I2C*
— 400kHz Data Transfer Rate
• Low Power CMOS
— 1.25µA Operating Current (Typical)
• Small Package Options
DESCRIPTION
The X1227 device is a Real Time Clock with
clock/calendar, two polled alarms with integrated 512x8
EEPROM, oscillator compensation, CPU Supervisor
(POR/LVS and WDT) and battery backup switch.
The oscillator uses an external, low-cost 32.768kHz
crystal. All compensation and trim components are
integrated on the chip. This eliminates several external
discrete components and a trim capacitor, saving
board area and component cost.
— 8 Ld SOIC and 8 Ld TSSOP
• Repetitive Alarms
• Temperature Compensation
• Pb-Free Plus Anneal Available (RoHS Compliant)
BLOCK DIAGRAM
OSC
Compensation
X1
Timer
Calendar
Logic
Battery
Switch
Circuitry
Time
Keeping
Registers
VCC
Frequency
Divider
1Hz
Oscillator
32.768kHz
VBACK
X2
(SRAM)
Status
Control/
Control
Decode
Logic
Compare
Serial
Interface
Decoder
Registers
SCL
SDA
Registers
Alarm
(EEPROM)
(SRAM)
Alarm Regs
(EEPROM)
8
4K
EEPROM
ARRAY
Watchdog
Timer
Low Voltage
Reset
RESET
FN8099 Rev 2.00
May 8, 2006
Page 1 of 28
X1227
ORDERING INFORMATION
TEMPERATURE
RANGE (°C)
PART NUMBER
X1227S8-4.5A
PART MARKING VCC RANGE (V)
VTRIP
PACKAGE
8 Ld SOIC
PKG. DWG. #
MDP0027
MDP0027
MDP0027
MDP0027
M8.173
X1227AL
X1227ZAL
X1227AM
X1227ZAM
1227AL
1227ALZ
1227AM
1227AMZ
X1227
4.5 to 5.5
4.63V ± 112mV
0 to 70
0 to 70
X1227S8Z-4.5A (Note 1)
X1227S8I-4.5A
8 Ld SOIC (Pb-free)
8 Ld SOIC
-40 to 85
-40 to 85
0 to 70
X1227S8IZ-4.5A (Note 1)
X1227V8-4.5A
8 Ld SOIC (Pb-free)
8 Ld TSSOP
X1227V8Z-4.5A (Note 1)
X1227V8I-4.5A
0 to 70
8 Ld TSSOP (Pb-free) M8.173
8 Ld TSSOP M8.173
8 Ld TSSOP (Pb-free) M8.173
-40 to 85
-40 to 85
0 to 70
X1227V8IZ-4.5A (Note 1)
X1227S8*
4.38V ± 112mV
2.85V ± 100mV
2.65V ± 100mV
8 Ld SOIC
MDP0027
MDP0027
MDP0027
MDP0027
M8.173
X1227S8Z* (Note 1)
X1227S8I
X1227Z
X1227I
0 to 70
8 Ld SOIC (Pb-free)
8 Ld SOIC
-40 to 85
-40 to 85
0 to 70
X1227S8IZ (Note 1)
X1227V8
X1227ZI
1227
8 Ld SOIC (Pb-free)
8 Ld TSSOP
X1227V8Z (Note 1)
X1227V8I
1227Z
0 to 70
8 Ld TSSOP (Pb-free) M8.173
8 Ld TSSOP M8.173
8 Ld TSSOP (Pb-free) M8.173
1227I
-40 to 85
-40 to 85
0 to 70
X1227V8IZ (Note 1)
X1227S8-2.7A
1227IZ
X1227AN
X1227ZAN
X1227AP
8 Ld SOIC
MDP0027
2.7 to 5.5
X1227S8Z-2.7A (Note 1)
X1227S8I-2.7A*
0 to 70
8 Ld SOIC (Pb-free)
8 Ld SOIC
MDP0027
MDP0027
MDP0027
M8.173
-40 to 85
-40 to 85
0 to 70
X1227S8IZ-2.7A* (Note 1) X1227ZAP
8 Ld SOIC (Pb-free)
8 Ld TSSOP
X1227V8-2.7A
1227AN
1227ANZ
1227AP
1227APZ
X1227F
X1227ZF
X1227G
X1227ZG
1227F
X1227V8Z-2.7A (Note 1)
X1227V8I-2.7A
0 to 70
8 Ld TSSOP (Pb-free) M8.173
8 Ld TSSOP M8.173
8 Ld TSSOP (Pb-free) M8.173
-40 to 85
-40 to 85
0 to 70
X1227V8IZ-2.7A (Note 1)
X1227S8-2.7*
8 Ld SOIC
MDP0027
MDP0027
MDP0027
MDP0027
M8.173
X1227S8Z-2.7 (Note 1)
X1227S8I-2.7*
0 to 70
8 Ld SOIC (Pb-free)
8 Ld SOIC
-40 to 85
-40 to 85
0 to 70
X1227S8IZ-2.7 (Note 1)
X1227V8-2.7
8 Ld SOIC (Pb-free)
8 Ld TSSOP
X1227V8Z-2.7 (Note 1)
X1227V8I-2.7
1227FZ
1227G
0 to 70
8 Ld TSSOP (Pb-free) M8.173
8 Ld TSSOP M8.173
8 Ld TSSOP (Pb-free) M8.173
-40 to 85
-40 to 85
X1227V8IZ-2.7 (Note 1)
1227GZ
*Add "T1" suffix for tape and reel.
NOTES:
1. Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are
MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
2. For appropriate volume, any VTRIP value from 2.6 to 4.7V may be ordered via Intersil’s Customer Specification Program (CSPEC).
FN8099 Rev 2.00
May 8, 2006
Page 2 of 28
X1227
PIN DESCRIPTIONS
X1227
X1227
8 LD TSSOP
8 LD SOIC
V
SCL
SDA
BACK
1
2
8
7
6
5
1
2
V
V
X1
X2
8
7
6
5
CC
V
CC
BACK
V
SS
X1
X2
3
4
RESET
3
4
SCL
SDA
RESET
V
SS
NC = No internal connection
PIN ASSIGNMENTS
Pin Number
SOIC
TSSOP
Symbol
Brief Description
1
3
X1
X1. The X1 pin is the input of an inverting amplifier and should be connected to one
pin of a 32.768kHz quartz crystal.
2
3
4
5
X2
X2. The X2 pin is the output of an inverting amplifier and should be connected to
one pin of a 32.768kHz quartz crystal..
RESET
Reset Output – RESET. This is a reset signal output. This signal notifies a host
processor that the watchdog time period has expired or that the voltage has
dropped below a fixed V
threshold. It is an open drain active LOW output.
TRIP
4
5
6
7
VSS
VSS.
SDA
Serial Data (SDA). SDA is a bidirectional pin used to transfer data into and out of
the device. It has an open drain output and may be wire ORed with other open drain
or open collector outputs.
6
7
8
1
SCL
Serial Clock (SCL). The SCL input is used to clock all data into and out of the
device. The input buffer on this pin is always active (not gated).
VBACK
VBACK. This input provides a backup supply voltage to the device. VBACK supplies
power to the device in the event the VCC supply fails. This pin can be connected to
a battery, a Supercap or tied to ground if not used.
8
2
VCC
VCC.
FN8099 Rev 2.00
May 8, 2006
Page 3 of 28
X1227
ABSOLUTE MAXIMUM RATINGS
Temperature Under Bias................... -65°C to +135°C
Storage Temperature ........................ -65°C to +150°C
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only and the functional operation
of the device at these or any other conditions above
those indicated in the operational sections of this specifi-
cation is not implied. Exposure to absolute maximum rat-
ing conditions for extended periods may affect device
reliability.
Voltage on V , V
pin
CC BACK
(respect to ground)...............................-0.5V to 7.0V
Voltage on SCL, SDA, X1 and X2
pin (respect to ground) ............... -0.5V to 7.0V or 0.5V
above V or V
(whichever is higher)
CC
BACK
DC Output Current ..............................................5 mA
Lead Temperature (Soldering, 10 sec).............. 300°C
DC OPERATING CHARACTERISTICS (Temperature = -40°C to +85°C, unless otherwise stated.)
Symbol
VCC
Parameter
Conditions
Min
2.7
Typ
Max
5.5
Unit
V
Notes
Main Power Supply
Backup Power Supply
Switch to Backup Supply
Switch to Main Supply
VBACK
VCB
1.8
5.5
V
VBACK -0.2
VBACK
VBACK -0.1
VBACK +0.2
V
VBC
V
OPERATING CHARACTERISTICS
Symbol
Parameter
Conditions
VCC = 2.7V
VCC = 5.0V
VCC = 2.7V
VCC = 5.0V
VCC = 2.7V
VCC = 5.0V
VBACK = 1.8V
VBACK = 3.3V
Min
Typ
Max
400
800
2.5
3.0
10
Unit
µA
Notes
ICC1
Read Active Supply
Current
1, 5, 7, 14
µA
ICC2
ICC3
Program Supply Current
(nonvolatile)
mA
mA
µA
2, 5, 7, 14
Main Timekeeping
Current
3, 7, 8, 14, 15
20
µA
IBACK
Timekeeping Current –
(Low Voltage Sense
and Watchdog Timer
disabled
1.25
1.5
µA
3, 6, 9, 14, 15
“See Perfor-
mance Data”
µA
ILI
Input Leakage Current
Output Leakage Current
Input LOW Voltage
10
10
µA
µA
V
10
10
13
ILO
VIL
-0.5
VCC x 0.2 or
VBACK x 0.2
VIH
Input HIGH Voltage
VCC x 0.7 or
VBACK x 0.7
V
CC + 0.5 or
V
V
V
13
13
11
VBACK + 0.5
VHYS
VOL1
Schmitt Trigger Input
Hysteresis
VCC related level .05 x VCC or
.05 x VBACK
Output LOW Voltage for
SDA and RESET
VCC = 2.7V
VCC = 5.5V
0.4
0.4
Notes: (1) The device enters the Active state after any start, and remains active: for 9 clock cycles if the Device Select Bits in the Slave Address
Byte are incorrect or until 200nS after a stop ending a read or write operation.
(2) The device enters the Program state 200nS after a stop ending a write operation and continues for tWC
.
(3) The device goes into the Timekeeping state 200nS after any stop, except those that initiate a nonvolatile write cycle; tWC after a stop
that initiates a nonvolatile write cycle; or 9 clock cycles after any start that is not followed by the correct Device Select Bits in the Slave
Address Byte.
(4) For reference only and not tested.
(5) VIL = VCC x 0.1, VIH = VCC x 0.9, fSCL = 400KHz
(6) VCC = 0V
(7) VBACK = 0V
(8) VSDA = VSCL=VCC, Others = GND or VCC
FN8099 Rev 2.00
May 8, 2006
Page 4 of 28
X1227
(9) VSDA =VSCL=VBACK, Others = GND or VBACK
(10)VSDA = GND or VCC, VSCL = GND or VCC, VRESET = GND or VCC
(11)IOL = 3.0mA at 5.5V, 1.5mA at 2.7V
(12)
IOH = -1.0mA at 5.5V, -0.4mA at 2.7V
(13)Threshold voltages based on the higher of Vcc or Vback.
(14)Using recommended crystal and oscillator network applied to X1 and X2 (25°C).
(15)Typical values are for TA = 25°C
Capacitance T = 25°C, f = 1.0 MHz, V = 5V
A
CC
Symbol
Parameter
Max.
10
Units
pF
Test Conditions
VOUT = 0V
(1)
COUT
Output Capacitance (SDA, RESET)
Input Capacitance (SCL)
(1)
CIN
10
pF
VIN = 0V
Notes: (1) This parameter is not 100% tested.
(2) The input capacitance between x1 and x2 pins can be varied between 5pF and 19.75pF by using analog trimming registers
AC CHARACTERISTICS
AC Test Conditions
Input Pulse Levels
VCC x 0.1 to VCC x 0.9
Input Rise and Fall Times
10ns
Input and Output Timing
Levels
VCC x 0.5
Output Load
Standard Output Load
Figure 1. Standard Output Load for testing the device with V = 5.0V
CC
Equivalent AC Output Load Circuit for V = 5V
CC
5.0V
For VOL= 0.4V
1533
and IOL = 3 mA
SDA
100pF
FN8099 Rev 2.00
May 8, 2006
Page 5 of 28
X1227
AC Specifications (T = -40°C to +85°C, VCC = +2.7V to +5.5V, unless otherwise specified.)
A
Symbol
Parameter
Min.
Max. Units
fSCL
tIN
SCL Clock Frequency
400
kHz
ns
s
s
s
s
s
s
ns
s
s
ns
ns
ns
pF
Pulse width Suppression Time at inputs
SCL LOW to SDA Data Out Valid
Time the bus must be free before a new transmission can start
Clock LOW Time
50(1)
tAA
0.1
0.9
tBUF
1.3
tLOW
tHIGH
tSU:STA
tHD:STA
tSU:DAT
tHD:DAT
tSU:STO
tDH
1.3
Clock HIGH Time
0.6
Start Condition Setup Time
Start Condition Hold Time
Data In Setup Time
0.6
0.6
100
Data In Hold Time
0
0.6
Stop Condition Setup Time
Data Output Hold Time
50
tR
SDA and SCL Rise Time
20 +.1Cb(2)
20 +.1Cb(2)
300
300
400
tF
SDA and SCL Fall Time
Cb
Capacitive load for each bus line
Notes: (1) This parameter is not 100% tested.
(2) Cb = total capacitance of one bus line in pF.
TIMING DIAGRAMS
Bus Timing
tF
tHIGH
tLOW
tR
SCL
tSU:DAT
tSU:STA
tHD:DAT
tSU:STO
tHD:STA
SDA IN
tAA tDH
tBUF
SDA OUT
FN8099 Rev 2.00
May 8, 2006
Page 6 of 28
X1227
Write Cycle Timing
SCL
SDA
8th Bit of Last Byte
ACK
tWC
Stop
Start
Condition
Condition
Power-up Timing
Symbol
(2)
Parameter
Min.
Typ.
Max.
Units
ms
(1)
tPUR
Time from Power-up to Read
Time from Power-up to Write
1
5
(1)
tPUW
ms
Notes: (1) Delays are measured from the time VCC is stable until the specified operation can be initiated. These parameters are periodically
sampled and not 100% tested.
(2) Typical values are for TA = 25°C and VCC = 5.0V
Nonvolatile Write Cycle Timing
(1)
Symbol
Parameter
Write Cycle Time
Min.
Typ.
Max.
Units
(1)
tWC
5
10
ms
Notes: (1) tWC is the time from a valid stop condition at the end of a write sequence to the end of the self-timed internal nonvolatile write cycle. It is
the minimum cycle time to be allowed for any nonvolatile write by the user, unless Acknowledge Polling is used.
WATCHDOG TIMER/LOW VOLTAGE RESET OPERATING CHARACTERISTICS
Watchdog/Low Voltage Reset Parameters
Symbols
Parameters
Min.
Typ.
Max.
Unit
VPTRIP
Programmed Reset Trip Voltage
X1227-4.5A
X1227
X1227-2.7A
X1227-2.7
V
4.5
4.25
2.7
4.68
4.38
2.93
2.68
4.75
4.5
3.0
2.55
2.7
tRPD
VCC Detect to RESET LOW
500
400
ns
tPURST
Power-up Reset Time-out Delay
100
200
ms
tF
tR
VCC Fall Time
VCC Rise Time
10
10
µs
µs
tWDO
Watchdog Timer Period:
WD1 = 0, WD0 = 0
WD1 = 0, WD0 = 1
WD1 = 1, WD0 = 0
1.7
725
225
1.75
750
250
1.8
775
275
s
ms
ms
tRST
Watchdog Reset Time-out Delay
225
250
275
ms
tRSP
2-Wire interface
Reset Valid VCC
1
µs
V
VRVALID
1.0
FN8099 Rev 2.00
May 8, 2006
Page 7 of 28
X1227
V
Programming Timing Diagram
TRIP
VCC
(VTRIP
)
VTRIP
tTSU
tTHD
VP = 15V
RESET
VCC
VCC
tVPH
0 1 2 3 4 5 6 7
tVPO
tVPS
0 1 2 3 4 5 6
7
0 1 2 3 4 5 6 7
0 1 2 3 4 5 6 7
SCL
SDA
tRP
AEh
00h
03h/01h
00h
V
Programming Parameters
TRIP
Parameter
tVPS
Description
VTRIP Program Enable Voltage Setup time
VTRIP Program Enable Voltage Hold time
VTRIP Setup time
Min.
1
Max.
Units
µs
tVPH
1
µs
tTSU
1
µs
tTHD
VTRIP Hold (stable) time
10
0
ms
µs
tVPO
VTRIP Program Enable Voltage Off time
(Between successive adjustments)
tRP
VTRIP Program Recovery Period
(Between successive adjustments)
10
ms
VP
VTRAN
Vtv
Programming Voltage
14
1.7
-25
16
5.0
+25
V
V
VTRIP Programmed Voltage Range
VTRIP Program variation after programming
(Programmed at 25°C)
mV
VTRIP programming parameters are not 100% Tested.
FN8099 Rev 2.00
May 8, 2006
Page 8 of 28
X1227
DESCRIPTION (continued)
Serial Clock (SCL)
The SCL input is used to clock all data into and out of
the device. The input buffer on this pin is always active
(not gated).
The Real-Time Clock keeps track of time with separate
registers for Hours, Minutes, Seconds. The Calendar
has separate registers for Date, Month, Year and Day-
of-week. The calendar is correct through 2099, with
automatic leap year correction.
Serial Data (SDA)
SDA is a bidirectional pin used to transfer data into and
out of the device. It has an open drain output and may be
wire ORed with other open drain or open collector out-
puts. The input buffer is always active (not gated).
The powerful Dual Alarms can be set to any
Clock/Calendar value for a match. For instance, every
minute, every Tuesday, or 5:23 AM on March 21. The
alarms can be polled in the Status Register. There is a
repeat mode for the alarms allowing a periodic interrupt.
An open drain output requires the use of a pull-up resis-
tor. The output circuitry controls the fall time of the out-
put signal with the use of a slope controlled pull-down.
The circuit is designed for 400kHz 2-wire interface
speeds.
The X1227 device integrates CPU Supervisor func-tions
and a Battery Switch. There is a Power-On Reset
(RESET output) with typically 250 ms delay from power-
on. It will also assert RESET when Vcc goes below the
specified threshold. The V
threshold is user repro-
V
BACK
trip
grammable. There is a WatchDog Timer (WDT) with 3
selectable time-out periods (0.25s, 0.75s, 1.75s) and a
disabled setting. The watchdog activates the RESET pin
when it expires.
This input provides a backup supply voltage to the
device. V supplies power to the device in the event
BACK
the V supply fails. This pin can be connected to a bat-
CC
tery, a Supercap or tied to ground if not used.
The device offers a backup power input pin. This V
BACK
RESET Output – RESET
pin allows the device to be backed up by battery or
SuperCap. The entire X1227 device is fully operational
from 2.7 to 5.5 volts and the clock/calendar portion of the
X1227 device remains fully operational down to 1.8 volts
(Standby Mode).
This is a reset signal output. This signal notifies a host pro-
cessor that the watchdog time period has expired or that
the voltage has dropped below a fixed V
an open drain active LOW output. Recommended value for
the pullup resistor is 5k. If unused, tie to ground.
threshold. It is
TRIP
The X1227 device provides 4K bits of EEPROM with 8
modes of BlockLock™ control. The BlockLock allows a
safe, secure memory for critical user and configuration
data, while allowing a large user storage area.
X1, X2
The X1 and X2 pins are the input and output,
respectively, of an inverting amplifier. An external
32.768kHz quartz crystal is used with the X1227 to
supply
a timebase for the real time clock. The
PIN DESCRIPTIONS
recommended crystal is a Citizen CFS206-32.768KDZF.
Internal compensation circuitry is included to form a
complete oscillator circuit. Care should be taken in the
placement of the crystal and the layout of the circuit. Plenty
of ground plane around the device and short traces to X1
and X2 are highly recommended. See Application section
for more recommendations.
X1227
8 LD SOIC
1
2
VCC
X1
X2
8
7
6
5
VBACK
SCL
RESET
VSS
3
4
SDA
Figure 2. Recommended Crystal connection
X1227
8 LD TSSOP
VBACK
VCC
SCL
1
2
8
7
6
5
X1
X2
SDA
VSS
X1
X2
3
4
RESET
NC = No internal connection
FN8099 Rev 2.00
May 8, 2006
Page 9 of 28
X1227
POWER CONTROL OPERATION
RTC continues to update the time while an RTC register
write is in progress and the RTC continues to run during
any nonvolatile write sequences. A single byte may be
written to the RTC without affecting the other bytes.
The power control circuit accepts a V
and a V
BACK
CC
input. The power control circuit powers the device from
when V < V - 0.2V. It will switch back to
V
BACK
CC
BACK
power the device from V when V exceeds V
.
CC
CC
BACK
Accuracy of the Real Time Clock
Figure 3. Power Control
The accuracy of the Real Time Clock depends on the
frequency of the quartz crystal that is used as the time
base for the RTC. Since the resonant frequency of a
crystal is temperature dependent, the RTC perfor-mance
will also be dependent upon temperature. The frequency
deviation of the crystal is a fuction of the turnover
temperature of the crystal from the crystal’s nominal
frequency. For example, a >20ppm frequency deviation
translates into an accuracy of >1 minute per month.
These parameters are available from the crystal
manufacturer. Intersil’s RTC family provides on-chip
crystal compensation networks to adjust load-
capacitance to tune oscillator frequency from +116 ppm
to -37 ppm when using a 12.5 pF load crystal. For more
detail information see the Application section.
VCC
Voltage
On
VBACK
In
Off
REAL TIME CLOCK OPERATION
The Real Time Clock (RTC) uses an external 32.768kHz
quartz crystal to maintain an accurate internal representa-
tion of the second, minute, hour, day, date, month, and
year. The RTC has leap-year correction. The clock also
corrects for months having fewer than 31 days and has a
bit that controls 24 hour or AM/PM format. When the
CLOCK/CONTROL REGISTERS (CCR)
X1227 powers up after the loss of both V and V
,
CC
BACK
The Control/Clock Registers are located in an area
separate from the EEPROM array and are only
accessible following a slave byte of “1101111x” and
reads or writes to addresses [0000h:003Fh]. The
clock/control memory map has memory addresses from
0000h to 003Fh. The defined addresses are described in
the Table 1. Writing to and reading from the undefined
addresses are not recommended.
the clock will not operate until at least one byte is written
to the clock register.
Reading the Real Time Clock
The RTC is read by initiating a Read command and
specifying the address corresponding to the register of the
Real Time Clock. The RTC Registers can then be read in a
Sequential Read Mode. Since the clock runs continuously
and a read takes a finite amount of time, there is the
possibility that the clock could change during the course of
a read operation. In this device, the time is latched by the
read command (falling edge of the clock on the ACK bit
prior to RTC data output) into a separate latch to avoid time
changes during the read operation. The clock continues to
run. Alarms occurring during a read are unaffected by the
read operation.
CCR access
The contents of the CCR can be modified by performing
a byte or a page write operation directly to any address
in the CCR. Prior to writing to the CCR (except the sta-
tus register), however, the WEL and RWEL bits must be
set using a two step process (See section “Writing to the
Clock/Control Registers.”)
The CCR is divided into 5 sections. These are:
Writing to the Real Time Clock
1. Alarm 0 (8 bytes; non-volatile)
2. Alarm 1 (8 bytes; non-volatile)
3. Control (4 bytes; non-volatile)
4. Real Time Clock (8 bytes; volatile)
5. Status (1 byte; volatile)
The time and date may be set by writing to the RTC reg-
isters. To avoid changing the current time by an uncom-
pleted write operation, the current time value is loaded
into a separate buffer at the falling edge of the clock on
the ACK bit before the RTC data input bytes, the clock
continues to run. The new serial input data replaces the
values in the buffer. This new RTC value is loaded back
into the RTC Register by a stop bit at the end of a valid
write sequence. An invalid write operation aborts the
time update procedure and the contents of the buffer are
discarded. After a valid write operation the RTC will
reflect the newly loaded data beginning with the next
“one second” clock cycle after the stop bit is written. The
Each register is read and written through buffers. The
non-volatile portion (or the counter portion of the RTC) is
updated only if RWEL is set and only after a valid write
operation and stop bit. A sequential read or page write
operation provides access to the contents of only one
section of the CCR per operation. Access to another sec-
tion requires a new operation. Continued reads or writes,
FN8099 Rev 2.00
May 8, 2006
Page 10 of 28
X1227
once reaching the end of a section, will wrap around to
the start of the section. A read or write can begin at any
address in the CCR.
address remains at the previous address +1 so the user
can execute a current address read of the CCR and con-
tinue reading the next Register.
It is not necessary to set the RWEL bit prior to writing the
status register. Section 5 supports a single byte read or
write only. Continued reads or writes from this section ter-
minates the operation.
ALARM REGISTERS
There are two alarm registers whose contents mimic the
contents of the RTC register, but add enable bits and
exclude the 24 hour time selection bit. The enable bits
specify which registers to use in the comparison between
the Alarm and Real Time Registers. For example:
The state of the CCR can be read by performing a ran-
dom read at any address in the CCR at any time. This
returns the contents of that register location. Additional
registers are read by performing a sequential read. The
read instruction latches all Clock registers into a buffer,
so an update of the clock does not change the time
being read. A sequential read of the CCR will not result
in the output of data from the memory array. At the end
of a read, the master supplies a stop condition to end the
operation and free the bus. After a read of the CCR, the
– Setting the Enable Month bit (EMOn*) bit in combina-
tion with other enable bits and a specific alarm time,
the user can establish an alarm that triggers at the
same time once a year.
– *n = 0 for Alarm 0: N = 1 for Alarm 1
Table 1. Clock/Control Memory Map
Bit
Reg
Name
Addr.
003F
Type
Range
7
6
5
4
3
2
1
0 (optional)
Status
SR
Y2K
DW
YR
MO
DT
HR
MN
SC
BAT
0
0
Y23
0
0
MIL
0
0
0
0
AL1
0
0
Y22
0
0
AL0
Y2K21
0
Y21
0
D21
H21
M21
S21
0
0
Y2K20
0
Y20
G20
D20
H20
M20
S20
0
0
Y2K13
0
Y13
G13
D13
H13
M13
S13
0
ATR3
Unused
WD0
A1Y2K13
0
RWEL
0
DY2
Y12
G12
D12
H12
M12
S12
WEL
0
RTCF
Y2K10
DY0
Y10
G10
D10
H10
M10
S10
01h
20h
00h
00h
00h
00h
00h
00h
00h
00h
00h
0037 RTC (SRAM)
19/20
0-6
0036
0035
0034
0033
0032
0031
0030
DY1
Y11
G11
D11
H11
M11
S11
DTR1
ATR1
0-99
1-12
1-31
0-23
0-59
0-59
0
M22
S22
0
0013
0012
0011
0010
000F
000E
000D
000C
000B
000A
0009
0008
0007
0006
0005
0004
0003
0002
0001
0000
Control
(EEPROM)
DTR
ATR
INT
DTR2
ATR2
DTR0
ATR0
0
ATR5
ATR4
BL
BP2
0
EDW1
BP1
0
0
BP0
A1Y2K21
0
WD1
A1Y2K20
0
0
0
DY2
0
0
DY1
0
18h
20h
00h
Alarm1
(EEPROM)
Y2K1
DWA1
YRA1
MOA1
DTA1
HRA1
MNA1
SCA1
Y2K0
DWA0
YRA0
MOA0
DTA0
HRA0
MNA0
SCA0
A1Y2K10
DY0
19/20
0-6
Unused - Default = RTC Year value (No EEPROM) - Future expansion
EMO1
EDT1
EHR1
EMN1
ESC1
0
0
0
0
A1G20
A1D20
A1H20
A1M20
A1S20
A0Y2K20
0
A1G13
A1D13
A1H13
A1M13
A1S13
A0Y2K13
0
A1G12
A1D12
A1H12
A1M12
A1S12
0
A1G11
A1D11
A1H11
A1M11
A1S11
0
A1G10
A1D10
A1H10
A1M10
A1S10
A0Y2K10
DY0
1-12
1-31
0-23
0-59
0-59
19/20
0-6
00h
00h
00h
00h
00h
20h
00h
A1D21
A1H21
A1M21
A1S21
A0Y2K21
0
0
A1M22
A1S22
0
Alarm0
(EEPROM)
EDW0
0
DY2
DY1
Unused - Default = RTC Year value (No EEPROM) - Future expansion
EMO0
EDT0
EHR0
EMN0
ESC0
0
0
0
0
A0G20
A0D20
A0H20
A0M20
A0S20
A0G13
A0D13
A0H13
A0M13
A0S13
A0G12
A0D12
A0H12
A0M12
A0S12
A0G11
A0D11
A0H11
A0M11
A0S11
A0G10
A0D10
A0H10
A0M10
A0S10
1-12
1-31
0-23
0-59
0-59
00h
00h
00h
00h
00h
A0D21
A0H21
A0M21
A0S21
A0M22
A0S22
FN8099 Rev 2.00
May 8, 2006
Page 11 of 28
X1227
When there is a match, an alarm flag is set. The occur-
rence of an alarm can be determined by polling the AL0
and AL1 bits or by enabling the IRQ output, using it as
hardware flag.
latches, read two power status and two alarm bits. This
register is separate from both the array and the
Clock/Control Registers (CCR).
Table 2. Status Register (SR)
The alarm enable bits are located in the MSB of the par-
ticular register. When all enable bits are set to ‘0’, there
are no alarms.
Addr
003Fh BAT AL1 AL0
Default
7
6
5
4
3
2
1
0
0
0
0
0
RWEL WEL RTCF
– The user can set the X1227 to alarm every Wednes-
day at 8:00 AM by setting the EDWn*, the EHRn* and
EMNn* enable bits to ‘1’ and setting the DWAn*,
HRAn* and MNAn* Alarm registers to 8:00 AM
Wednesday.
0
0
0
0
0
1
BAT: Battery Supply—Volatile
This bit set to “1” indicates that the device is operating from
, not V . It is a read-only bit and is set/reset by
V
BACK
CC
– A daily alarm for 9:30PM results when the EHRn* and
EMNn* enable bits are set to ‘1’ and the HRAn* and
MNAn* registers are set to 9:30 PM.
hardware (X1227 internally). Once the device begins oper-
ating from V , the device sets this bit to “0”.
CC
AL1, AL0: Alarm bits—Volatile
*n = 0 for Alarm 0: N = 1 for Alarm 1
These bits announce if either alarm 0 or alarm 1 match
the real time clock. If there is a match, the respective bit
is set to ‘1’. The falling edge of the last data bit in a SR
Read operation resets the flags. Note: Only the AL bits
that are set when an SR read starts will be reset. An
alarm bit that is set by an alarm occurring during an SR
read operation will remain set after the read operation is
complete.
REAL TIME CLOCK REGISTERS
Clock/Calendar Registers (SC, MN, HR, DT, MO, YR)
These registers depict BCD representations of the time.
As such, SC (Seconds) and MN (Minutes) range from 00
to 59, HR (Hour) is 1 to 12 with an AM or PM indicator
(H21 bit) or 0 to 23 (with MIL = 1), DT (Date) is 1 to 31,
MO (Month) is 1 to 12, YR (Year) is 0 to 99.
RWEL: Register Write Enable Latch—Volatile
Date of the Week Register (DW)
This bit is a volatile latch that powers up in the LOW (dis-
abled) state. The RWEL bit must be set to “1” prior to any
writes to the Clock/Control Registers. Writes to RWEL bit
do not cause a nonvolatile write cycle, so the device is
ready for the next operation immediately after the stop
condition. A write to the CCR requires both the RWEL and
WEL bits to be set in a specific sequence.
This register provides a Day of the Week status and
uses three bits DY2 to DY0 to represent the seven days
of the week. The counter advances in the cycle 0-1-2-3-
4-5-6-0-1-2-… The assignment of a numerical value to a
specific day of the week is arbitrary and may be decided
by the system software designer. The default value is
defined as ‘0’.
WEL: Write Enable Latch—Volatile
24 Hour Time
The WEL bit controls the access to the CCR and memory
array during a write operation. This bit is a volatile latch
that powers up in the LOW (disabled) state. While the
WEL bit is LOW, writes to the CCR or any array address
will be ignored (no acknowledge will be issued after the
Data Byte). The WEL bit is set by writing a “1” to the WEL
bit and zeroes to the other bits of the Status Register.
Once set, WEL remains set until either reset to 0 (by writ-
ing a “0” to the WEL bit and zeroes to the other bits of the
Status Register) or until the part powers up again. Writes
to WEL bit do not cause a nonvolatile write cycle, so the
device is ready for the next operation immediately after
the stop condition.
If the MIL bit of the HR register is 1, the RTC uses a 24-
hour format. If the MIL bit is 0, the RTC uses a 12-hour
format and H21 bit functions as an AM/PM indicator with
a ‘1’ representing PM. The clock defaults to standard
time with H21 = 0.
Leap Years
Leap years add the day February 29 and are defined as
those years that are divisible by 4. Years divisible by 100
are not leap years, unless they are also divisible by 400.
This means that the year 2000 is a leap year, the year
2100 is not. The X1227 does not correct for the leap
year in the year 2100.
RTCF: Real Time Clock Fail Bit—Volatile
STATUS REGISTER (SR)
This bit is set to a “1” after a total power failure. This is a
read only bit that is set by hardware (X1227 internally)
when the device powers up after having lost all power to
The Status Register is located in the CCR Memory Map
at address 003Fh. This is a volatile register only and is
used to control the WEL and RWEL write enable
the device (both V and V
go to 0V). The bit is set
CC
BACK
FN8099 Rev 2.00
May 8, 2006
Page 12 of 28
X1227
regardless of whether V or V
is applied first. The
BACK
Watchdog Timer Control Bits—WD1, WD0
CC
loss of only one of the supplies does not set the RTCF
bit to “1”. On power-up after a total power failure, all reg-
isters are set to their default states and the clock will not
increment until at least one byte is written to the clock
register. The first valid write to the RTC section after a
complete power failure resets the RTCF bit to “0” (writing
one byte is sufficient).
The bits WD1 and WD0 control the period of the Watch-
dog Timer. See Table 4 for options.
Table 4. Watchdog Timer Time-Out Options
Watchdog Time-Out Period
WD1 WD0
0
0
1
1
0
1
0
1
1.75 seconds
750 milliseconds
250 milliseconds
Disabled (default)
Unused Bits:
This device does not use bits 3 or 4 in the SR, but must
have a zero in these bit positions. The Data Byte output
during a SR read will contain zeros in these bit locations.
ON-CHIP OSCILLATOR COMPENSATION
CONTROL REGISTERS
Digital Trimming Register (DTR) — DTR2, DTR1 and
DTR0 (Non-Volatile)
The Control Bits and Registers, described under this
section, are nonvolatile.
The digital trimming Bits DTR2, DTR1 and DTR0 adjust
the number of counts per second and average the ppm
error to achieve better accuracy.
Block Protect Bits—BP2, BP1, BP0
The Block Protect Bits, BP2, BP1 and BP0, determine
which blocks of the array are write protected. A write to a
protected block of memory is ignored. The block protect
bits will prevent write operations to one of eight segments
of the array. The partitions are described in Table 3 .
DTR2 is a sign bit. DTR2=0 means frequency
compensation is > 0. DTR2=1 means frequency
compensation is < 0.
DTR1 and DTR0 are scale bits. DTR1 gives 10 ppm
adjustment and DTR0 gives 20 ppm adjustment.
Table 3. Block Protect Bits
Protected Addresses
A range from -30ppm to +30ppm can be represented by
using three bits above.
X1227
Array Lock
None
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
None (Default)
180h - 1FFh
Table 5. Digital Trimming Registers
Upper 1/4
DTR Register
Estimated frequency
100h - 1FFh
000h - 1FFh
000h - 03Fh
000h - 07Fh
000h - 0FFh
000h - 1FFh
Upper 1/2
Full Array
First Page
First 2 pgs
First 4 pgs
First 8 pgs
DTR2
DTR1
DTR0
PPM
0 (Default)
+10
0
0
0
0
1
1
1
1
0
1
0
1
0
1
0
1
0
0
1
1
0
0
1
1
+20
+30
0
-10
-20
-30
FN8099 Rev 2.00
May 8, 2006
Page 13 of 28
X1227
Analog Trimming Register (ATR) (Non-volatile)
– Write one to 8 bytes to the Clock/Control Registers
with the desired clock, alarm, or control data. This
sequence starts with a start bit, requires a slave byte
of “11011110” and an address within the CCR and is
terminated by a stop bit. A write to the CCR changes
EEPROM values so these initiate a nonvolatile write
cycle and will take up to 10ms to complete. Writes to
undefined areas have no effect. The RWEL bit is reset
by the completion of a nonvolatile write cycle, so the
sequence must be repeated to again initiate another
change to the CCR contents. If the sequence is not
completed for any reason (by sending an incorrect
number of bits or sending a start instead of a stop, for
example) the RWEL bit is not reset and the device
remains in an active mode.
Six analog trimming Bits from ATR5 to ATR0 are provided
to adjust the on-chip loading capacitance range. The on-
chip load capacitance ranges from 3.25pF to 18.75pF.
Each bit has a different weight for capacitance adjust-
ment. Using a Citizen CFS-206 crystal with different ATR
bit combinations provides an estimated ppm range from
+116ppm to -37ppm to the nominal frequency compensa-
tion. The combination of digital and analog trimming can
give up to +146ppm adjustment.
The on-chip capacitance can be calculated as follows:
C
= [(ATR value, decimal) x 0.25pF] + 11.0pF
ATR
Note that the ATR values are in two’s complement, with
ATR(000000) = 11.0pF, so the entire range runs from
3.25pF to 18.75pF in 0.25pF steps.
– Writing all zeros to the status register resets both the
WEL and RWEL bits.
The values calculated above are typical, and total load
capacitance seen by the crystal will include approxi-
mately 2pF of package and board capacitance in addi-
tion to the ATR value.
– A read operation occurring between any of the
previous operations will not interrupt the register write
operation.
See Application section and Intersil’s Application Note
AN154 for more information.
WRITING TO THE CLOCK/CONTROL REGISTERS
Changing any of the nonvolatile bits of the clock/control
register requires the following steps:
– Write a 02h to the Status Register to set the Write
Enable Latch (WEL). This is a volatile operation,
so there is no delay after the write. (Operation
preceeded by a start and ended with a stop).
– Write a 06h to the Status Register to set both the Reg-
ister Write Enable Latch (RWEL) and the WEL bit.
This is also a volatile cycle. The zeros in the data byte
are required. (Operation preceeded by a start and
ended with a stop).
FN8099 Rev 2.00
May 8, 2006
Page 14 of 28
X1227
POWER-ON RESET
Watchdog Timer Restart
The Watchdog Timer is started by a falling edge of SDA
when the SCL line is high and followed by a stop bit. The
start signal restarts the watchdog timer counter, reset-
ting the period of the counter back to the maximum. If
another start fails to be detected prior to the watchdog
timer expiration, then the RESET pin becomes active. In
the event that the start signal occurs during a reset time
out period, the start will have no effect. When using a
single START to refresh watchdog timer, a STOP bit
should be followed to reset the device back to stand-by
mode.
Application of power to the X1227 activates a Power-on
Reset Circuit that pulls the RESET pin active. This signal
provides several benefits.
– It prevents the system microprocessor from starting to
operate with insufficient voltage.
– It prevents the processor from operating prior to stabi-
lization of the oscillator.
– It allows time for an FPGA to download its configura-
tion prior to initialization of the circuit.
– It prevents communication to the EEPROM, greatly
reducing the likelihood of data corruption on power-up.
LOW VOLTAGE RESET OPERATION
When V exceeds the device V
threshold value for
TRIP
CC
When a power failure occurs, and the voltage to the part
typically 250ms the circuit releases RESET, allowing the
system to begin operation. Recommended slew rate is
between 0.2V/ms and 50V/ms.
drops below a fixed v
voltage, a reset pulse is issued
TRIP
to the host microcontroller. The circuitry monitors the
line with a voltage comparator which senses a pre-
V
CC
set threshold voltage. Power-up and power-down wave-
forms are shown in Figure 5. The Low Voltage Reset
circuit is to be designed so the RESET signal is valid
down to 1.0V.
WATCHDOG TIMER OPERATION
The watchdog timer is selectable. By writing a value to
WD1 and WD0, the watchdog timer can be set to 3 dif-
ferent time out periods or off. When the Watchdog timer
is set to off, the watchdog circuit is configured for low
power operation.
When the low voltage reset signal is active, the operation of
any in progress nonvolatile write cycle is unaffected, allow-
ing a nonvolatile write to continue as long as possible
(down to the power-on reset voltage). The low voltage
reset signal, when active, terminates in progress communi-
cations to the device and prevents new commands, to
reduce the likelihood of data corruption.
Figure 4. Watchdog Restart/Time Out
tRSP
tRSP>tWDO
tRST
tRSP>tWDO
tRST
tRSP<tWDO
SCL
SDA
RESET
Stop
Start
Start
Note: All inputs are ignored during the active reset period (tRST).
FN8099 Rev 2.00
May 8, 2006
Page 15 of 28
X1227
Figure 5. Power-on Reset and Low Voltage Reset
V
TRIP
V
CC
t
t
PURST
PURST
t
RPD
t
F
t
R
RESET
V
RVALID
V
THRESHOLD RESET PROCEDURE
Setting the V
Voltage
CC
TRIP
[OPTIONAL]
It is necessary to reset the trip point before setting the
new value.
The X1227 is shipped with a standard V
threshold
CC
(V
) voltage. This value will not change over normal
TRIP
To set the new V
threshold voltage to the V pin and tie the RESET pin
to the programming voltage V . Then write data 00h to
address 01h. The stop bit following a valid write opera-
voltage, apply the desired V
TRIP
TRIP
operating and storage conditions. However, in applica-
tions where the standard V is not exactly right, or if
higher precision is needed in the V
threshold may be adjusted. The procedure is described
below, and uses the application of a nonvolatile write
control signal.
CC
TRIP
P
value, the X1227
TRIP
tion initiates the V
programming sequence. Bring
TRIP
RESET to V
to complete the operation. Note: this
CC
operation may take up to 10 milliseconds to complete
and also writes 00h to address 01h of the EEPROM
array.
Figure 6. Set V
Level Sequence (V = desired V value)
TRIP
TRIP
CC
VP = 15V
RESET
VCC
VCC
0
1
2
3
4
5 6 7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5 6 7
SCL
SDA
AEh
00h
01h
00h
Note: BP0, BP1, BP2 must be disabled.
Resetting the V
Voltage
For best accuracy in setting V
following sequence be used.
, it is advised that the
TRIP
TRIP
This procedure is used to set the V
to a “native” volt-
TRIP
age level. For example, if the current V
is 4.4V and
TRIP
1.Program V
as above.
TRIP
the new V
must be 4.0V, then the V
must be
TRIP
TRIP
2.Measure resulting V
where a RESET occurs. Calculate Delta = (Desired -
Measured) V value.
by measuring the V value
CC
TRIP
reset. When V
is reset, the new V
is something
TRIP
TRIP
less than 1.7V. This procedure must be used to set the
voltage to a lower value.
TRIP
3.Perform a V
to set the voltage of the RESET pin:
program using the following formula
TRIP
To reset the new V
voltage, apply more than 3.0V to
TRIP
the V
pin and tie the RESET pin to the programming
CC
V
= (Desired Value – Delta) + 0.025V
RESET
voltage V . Then write 00h to address 03h. The stop bit
P
of a valid write operation initiates the V
programming
TRIP
sequence. Bring RESET to V
to complete the
CC
operation. Note: this operation takes up to 10
milliseconds to complete and also writes 00h to address
03h of the EEPROM array.
FN8099 Rev 2.00
May 8, 2006
Page 16 of 28
X1227
Figure 7. Reset V
Level Sequence
TRIP
VP = 15V
RESET
VCC
VCC
0
1 2 3 4 5 6 7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5 6 7
SCL
SDA
AEh
00h
03h
00h
Note: BP0, BP1, BP2 must be disabled.
SERIAL COMMUNICATION
Interface Conventions
Acknowledge
Acknowledge is a software convention used to indicate
successful data transfer. The transmitting device, either
master or slave, will release the bus after transmitting
eight bits. During the ninth clock cycle, the receiver will
pull the SDA line LOW to acknowledge that it received
the eight bits of data. Refer to Figure 10.
The device supports a bidirectional bus oriented proto-
col. The protocol defines any device that sends data
onto the bus as a transmitter, and the receiving device
as the receiver. The device controlling the transfer is
called the master and the device being controlled is
called the slave. The master always initiates data trans-
fers, and provides the clock for both transmit and receive
operations. Therefore, the devices in this family operate
as slaves in all applications.
The device will respond with an acknowledge after rec-
ognition of a start condition and if the correct Device
Identifier and Select bits are contained in the Slave
Address Byte. If a write operation is selected, the device
will respond with an acknowledge after the receipt of
each subsequent eight bit word. The device will
acknowledge all incoming data and address bytes,
except for:
Clock and Data
Data states on the SDA line can change only during SCL
LOW. SDA state changes during SCL HIGH are
reserved for indicating start and stop conditions. See
Figure 8.
– The Slave Address Byte when the Device Identifier
and/or Select bits are incorrect
– All Data Bytes of a write when the WEL in the Write
Protect Register is LOW
Start Condition
All commands are preceded by the start condition, which
is a HIGH to LOW transition of SDA when SCL is HIGH.
The device continuously monitors the SDA and SCL
lines for the start condition and will not respond to any
command until this condition has been met. See
Figure 9.
– The 2nd Data Byte of a Status Register Write Opera-
tion (only 1 data byte is allowed)
In the read mode, the device will transmit eight bits of
data, release the SDA line, then monitor the line for an
acknowledge. If an acknowledge is detected and no stop
condition is generated by the master, the device will con-
tinue to transmit data. The device will terminate further
data transmissions if an acknowledge is not detected.
The master must then issue a stop condition to return
the device to Standby mode and place the device into a
known state.
Stop Condition
All communications must be terminated by a stop
condition, which is a LOW to HIGH transition of SDA
when SCL is HIGH. The stop condition is also used to
place the device into the Standby power mode after a
read sequence. A stop condition can only be issued after
the transmitting device has released the bus. See
Figure 9.
FN8099 Rev 2.00
May 8, 2006
Page 17 of 28
X1227
Figure 8. Valid Data Changes on the SDA Bus
SCL
SDA
Data Stable
Data Change
Data Stable
Figure 9. Valid Start and Stop Conditions
SCL
SDA
Start
Stop
Figure 10. Acknowledge Response From Receiver
SCL from
Master
1
8
9
Data Output
from Transmitter
Data Output
from Receiver
Start
Acknowledge
DEVICE ADDRESSING
Following the Slave Byte is a two byte word address.
The word address is either supplied by the master
device or obtained from an internal counter. On power-
up the internal address counter is set to address 0h, so a
current address read of the EEPROM array starts at
address 0. When required, as part of a random read, the
master must supply the 2 Word Address Bytes as shown
in Figure 11.
Following a start condition, the master must output a
Slave Address Byte. The first four bits of the Slave
Address Byte specify access to either the EEPROM
array or to the CCR. Slave bits ‘1010’ access the
EEPROM array. Slave bits ‘1101’ access the CCR.
When shipped from the factory, EEPROM array is
UNDEFINED, and should be programmed by the cus-
tomer to a known state.
In a random read operation, the slave byte in the
“dummy write” portion must match the slave byte in the
“read” section. That is if the random read is from the
array the slave byte must be 1010111x in both
instances. Similarly, for a random read of the Clock/Con-
trol Registers, the slave byte must be 1101111x in both
places.
Bit 3 through Bit 1 of the slave byte specify the device
select bits. These are set to ‘111’.
The last bit of the Slave Address Byte defines the opera-
tion to be performed. When this R/W bit is a one, then a
read operation is selected. A zero selects a write opera-
tion. Refer to Figure 11.
After loading the entire Slave Address Byte from the
SDA bus, the X1227 compares the device identifier and
device select bits with ‘1010111’ or ‘1101111’. Upon a
correct compare, the device outputs an acknowledge on
the SDA line.
FN8099 Rev 2.00
May 8, 2006
Page 18 of 28
X1227
Figure 11. Slave Address, Word Address, and Data Bytes (64 Byte pages)
Device Identifier
Slave Address Byte
Array
CCR
1
1
0
1
1
0
0
1
1
1
1
0
R/W
A8
Byte 0
Word Address 1
Byte 1
0
0
0
0
0
0
Word Address 0
Byte 2
A7
D7
A6
D6
A5
D5
A4
D4
A3
D3
A2
D2
A1
D1
A0
D0
Data Byte
Byte 3
Write Operations
Byte Write
data bits, the X1227 again responds with an acknowl-
edge. The master then terminates the transfer by gener-
ating a stop condition. The X1227 then begins an
internal write cycle of the data to the nonvolatile mem-
ory. During the internal write cycle, the device inputs are
disabled, so the device will not respond to any requests
from the master. The SDA output is at high impedance.
See Figure 12.
For a write operation, the device requires the Slave
Address Byte and the Word Address Bytes. This gives
the master access to any one of the words in the array or
CCR. (Note: Prior to writing to the CCR, the master must
write a 02h, then 06h to the status register in two pre-
ceding operations to enable the write operation. See
“Writing to the Clock/Control Registers.” Upon receipt of
each address byte, the X1227 responds with an
acknowledge. After receiving both address bytes the
X1227 awaits the eight bits of data. After receiving the 8
A write to a protected block of memory is ignored, but
will still receive an acknowledge. At the end of the write
command, the X1227 will not initiate an internal write
cycle, and will continue to ACK commands.
Figure 12. Byte Write Sequence
S
t
a
r
Signals from
the Master
S
t
Slave
Address
Word
Address 1
Word
Address 0
o
p
t
Data
SDA Bus
1
1 1 1 0 0 0 0 0 0 0 0
A
C
K
A
C
K
A
C
K
A
C
K
Signals From
The Slave
Figure 13. Writing 30 bytes to a 64-byte memory page starting at address 40.
7 Bytes
23 Bytes
Address Pointer
Ends Here
Addr = 7
Address
Address
= 6
Address
40
63
FN8099 Rev 2.00
May 8, 2006
Page 19 of 28
X1227
Page Write
through 63, and the last 7 bytes are written to columns 0
through 6. Afterwards, the address counter would point to
location 7 on the page that was just written. If the master
supplies more than the maximum bytes in a page, then
the previously loaded data is over written by the new data,
one byte at a time. Refer to Figure 13.
The X1227 has a page write operation. It is initiated in
the same manner as the byte write operation; but
instead of terminating the write cycle after the first data
byte is transferred, the master can transmit up to 63
more bytes to the memory array and up to 7 more bytes
to the clock/control registers. (Note: Prior to writing to
the CCR, the master must write a 02h, then 06h to the
status register in two preceding operations to enable the
write operation. See “Writing to the Clock/Control Regis-
ters.”
The master terminates the Data Byte loading by issuing
a stop condition, which causes the X1227 to begin the
nonvolatile write cycle. As with the byte write operation,
all inputs are disabled until completion of the internal
write cycle. Refer to Figure 14 for the address, acknowl-
edge, and data transfer sequence.
After the receipt of each byte, the X1227 responds with an
acknowledge, and the address is internally incremented
by one. When the counter reaches the end of the page, it
“rolls over” and goes back to the first address on the same
page. This means that the master can write 64 bytes to a
memory array page or 8 bytes to a CCR section starting
at any location on that page. For example, if the master
begins writing at location 40 of the memory and loads 30
bytes, then the first 23 bytes are written to addresses 45
Stops and Write Modes
Stop conditions that terminate write operations must be
sent by the master after sending at least 1 full data byte
and it’s associated ACK signal. If a stop is issued in the
middle of a data byte, or before 1 full data byte + ACK is
sent, then the X1227 resets itself without performing the
write. The contents of the array are not affected.
Figure 14. Page Write Sequence
1 ð n ð 64 for EEPROM array
1 ð n ð 8 for CCR
S
t
a
r
Signals from
the Master
S
t
o
p
Word
Address 1
Slave
Address
Word
Address 0
Data
(1)
Data
(n)
t
SDA Bus
1
1 1 1 0
0 0 0 0 0 0 0
A
C
K
A
C
K
A
C
K
A
C
K
Signals from
the Slave
FN8099 Rev 2.00
May 8, 2006
Page 20 of 28
X1227
Acknowledge Polling
Figure 16. Acknowledge Polling Sequence
Disabling of the inputs during nonvolatile write cycles
can be used to take advantage of the typical 5mS write
cycle time. Once the stop condition is issued to indicate
the end of the master’s byte load operation, the X1227
initiates the internal nonvolatile write cycle. Acknowl-
edge polling can begin immediately. To do this, the mas-
ter issues a start condition followed by the Memory Array
Slave Address Byte for a write or read operation (AEh or
AFh). If the X1227 is still busy with the nonvolatile write
cycle then no ACK will be returned. When the X1227 has
completed the write operation, an ACK is returned and
the host can proceed with the read or write operation.
Refer to the flow chart in Figure 16. Note: Do not use the
CCR slave byte (DEh or DFh) for acknowledge polling.
Byte load completed
by issuing STOP.
Enter ACK Polling
Issue START
Issue Memory Array Slave
Issue STOP
Address Byte AFh (Read)
or AEh (Write)
NO
ACK
returned?
Read Operations
YES
There are three basic read operations: Current Address
Read, Random Read, and Sequential Read.
NO
nonvolatile write
Cycle complete. Continue
command sequence?
Issue STOP
Current Address Read
Internally the X1227 contains an address counter that
maintains the address of the last word read incremented
by one. Therefore, if the last read was to address n, the
next read operation would access data from address
n+1. On power-up, the sixteen bit address is initialized to
0h. In this way, a current address read immediately after
the power-on reset can download the entire contents of
memory starting at the first location.Upon receipt of the
Slave Address Byte with the R/W bit set to one, the
X1227 issues an acknowledge, then transmits eight data
bits. The master terminates the read operation by not
responding with an acknowledge during the ninth clock
and issuing a stop condition. Refer to Figure 15 for the
address, acknowledge, and data transfer sequence.
YES
Continue normal
Read or Write
command
sequence
PROCEED
It should be noted that the ninth clock cycle of the read
operation is not a “don’t care.” To terminate a read oper-
ation, the master must either issue a stop condition
during the ninth cycle or hold SDA HIGH during the ninth
clock cycle and then issue a stop condition.
Figure 15. Current Address Read Sequence
S
t
S
t
o
p
Signals from
the Master
Slave
Address
a
r
t
SDA Bus
1
1 1 1 1
A
C
K
Signals from
the Slave
Data
FN8099 Rev 2.00
May 8, 2006
Page 21 of 28
X1227
Random Read
loaded address. This operation could be useful if the
master knows the next address it needs to read, but is
not ready for the data.
Random read operations allows the master to access
any location in the X1227. Prior to issuing the Slave
Address Byte with the R/W bit set to zero, the master
must first perform a “dummy” write operation.
Sequential Read
Sequential reads can be initiated as either a current
address read or random address read. The first data
byte is transmitted as with the other modes; however,
the master now responds with an acknowledge, indicat-
ing it requires additional data. The device continues to
output data for each acknowledge received. The master
terminates the read operation by not responding with an
acknowledge and then issuing a stop condition.
The master issues the start condition and the slave
address byte, receives an acknowledge, then issues the
word address bytes. After acknowledging receipt of each
word address byte, the master immediately issues
another start condition and the slave address byte with
the R/W bit set to one. This is followed by an acknowl-
edge from the device and then by the eight bit data
word. The master terminates the read operation by not
responding with an acknowledge and then issuing a stop
condition. Refer to Figure 17 for the address, acknowl-
edge, and data transfer sequence.
The data output is sequential, with the data from
address n followed by the data from address n + 1. The
address counter for read operations increments through
all page and column addresses, allowing the entire
memory contents to be serially read during one opera-
tion. At the end of the address space the counter “rolls
over” to the start of the address space and the X1227
continues to output data for each acknowledge received.
Refer to Figure 18 for the acknowledge and data transfer
sequence.
In a similar operation called “Set Current Address,” the
device sets the address if a stop is issued instead of the
second start shown in Figure 17. The X1227 then goes
into standby mode after the stop and all bus activity will
be ignored until a start is detected. This operation loads
the new address into the address counter. The next Cur-
rent Address Read operation will read from the newly
Figure 17. Random Address Read Sequence
S
t
S
S
t
o
p
t
a
r
Signals from
the Master
Slave
Address
Word
Address 0
Slave
Address
a
r
Word
Address 1
t
t
SDA Bus
1
1 1 1 1
1
1 1 1 0
0 0 0 0 0 0 0
A
C
K
A
C
K
A
C
K
A
C
K
Signals from
the Slave
Data
Figure 18. Sequential Read Sequence
S
t
o
p
Slave
Address
A
C
K
A
C
K
A
C
K
Signals from
the Master
SDA Bus
1
A
C
K
Signals from
the Slave
Data
(2)
Data
(n-1)
Data
(1)
Data
(n)
(n is any integer greater than 1)
FN8099 Rev 2.00
May 8, 2006
Page 22 of 28
X1227
APPLICATION SECTION
extremes of -40 and +85 deg C. It is possible to address
this variable drift by adjusting the load capacitance of the
crystal, which will result in predictable change to the
crystal frequency. The Intersil RTC family allows this
adjustment over temperature since the devices include
on-chip load capacitor trimming. This control is handled
by the Analog Trimming Register, or ATR, which has 6
bits of control. The load capacitance range covered by
the ATR circuit is approximately 3.25pF to 18.75pF, in
0.25pf increments. Note that actual capacitance would
also include about 2pF of package related capacitance.
In-circuit tests with commercially available crystals
demonstrate that this range of capacitance allows fre-
quency control from +116ppm to -37ppm, using a
12.5pF load crystal.
CRYSTAL OSCILLATOR AND TEMPERATURE COM-
PENSATION
Intersil has now integrated the oscillator compensation
circuity on-chip, to eliminate the need for external com-
ponents and adjust for crystal drift over temperature and
enable very high accuracy time keeping (<5ppm drift.
The Intersil RTC family uses an oscillator circuit with on-
chip crystal compensation network, including adjustable
load-capacitance. The only external component required
is the crystal. The compensation network is optimized for
operation with certain crystal parameters which are com-
mon in many of the surface mount or tuning-fork crystals
available today. Table 6 summarizes these parameters.
In addition to the analog compensation afforded by the
adjustable load capacitance, a digital compensation fea-
ture is available for the Intersil RTC family. There are
three bits known as the Digital Trimming Register or
DTR, and they operate by adding or skipping pulses in
the clock signal. The range provided is ±30ppm in incre-
ments of 10ppm. The default setting is 0ppm. The DTR
control can be used for coarse adjustments of frequency
drift over temperature or for crystal initial accuracy cor-
rection.
Table 7 contains some crystal manufacturers and part
numbers that meet the requirements for the Intersil RTC
products.
The turnover temperature in Table 6 describes the tem-
perature where the apex of the of the drift vs. tempera-
ture curve occurs. This curve is parabolic with the drift
2
increasing as (T-T0) . For an Epson MC-405 device, for
example, the turnover temperature is typically 25 deg C,
and a peak drift of >110ppm occurs at the temperature
Table 6. Crystal Parameters Required for Intersil RTC’s
Parameter
Min
Typ
Max
Units
kHz
ppm
°C
Notes
Frequency
32.768
Freq. Tolerance
±100
30
Down to 20ppm if desired
Turnover Temperature
20
25
Typically the value used for most
crystals
Operating Temperature Range
Parallel Load Capacitance
Equivalent Series Resistance
-40
85
50
°C
pF
k
12.5
For best oscillator performance
Table 7. Crystal Manufacturers
Manufacturer
Citizen
Part Number
CM201, CM202, CM200S
MC-405, MC-406
RSM-200S-A or B
32S12A or B
Temp Range
-40 to +85°C
-40 to +85°C
-40 to +85°C
-40 to +85°C
-10 to +60°C
-10 to +60°C
-40 to +85°C
+25°C Freq Toler.
±20ppm
Epson
Raltron
SaRonix
Ecliptek
ECS
±20ppm
±20ppm
±20ppm
ECPSM29T-32.768K
ECX-306/ECX-306I
FSM-327
±20ppm
±20ppm
Fox
±20ppm
FN8099 Rev 2.00
May 8, 2006
Page 23 of 28
X1227
A final application for the ATR control is in-circuit calibra-
tion for high accuracy applications, along with a tem-
perature sensor chip. Once the RTC circuit is powered
up with battery backup, the frequency drift is measured.
The ATR control is then adjusted to a setting which mini-
mizes drift. Once adjusted at a particular temperature, it
is possible to adjust at other discrete temperatures for
minimal overall drift, and store the resulting settings in
the EEPROM. Extremely low overall temperature drift is
possible with this method. The Intersil evaluation board
contains the circuitry necessary to implement this con-
trol.
For other RTC products, the same rules stated above
should be observed, but adjusted slightly since the
packages and pinouts are slightly different.
Assembly
Most electronic circuits do not have to deal with assem-
bly issues, but with the RTC devices assembly includes
insertion or soldering of a live battery into an unpowered
circuit. If a socket is soldered to the board, and a battery
is inserted in final assembly, then there are no issues
with operation of the RTC. If the battery is soldered to
the board directly, then the RTC device Vback pin will
see some transient upset from either soldering tools or
intermittent battery connections which can stop the cir-
cuit from oscillating. Once the battery is soldered to the
board, the only way to assure the circuit will start up is to
momentarily (very short period of time!) short the Vback
pin to ground and the circuit will begin to oscillate.
For more detailed operation see Intersil’s application
note AN154 on Intersil’s website at www.intersil.com.
Layout Considerations
The crystal input at X1 has a very high impedance and
will pick up high frequency signals from other circuits on
the board. Since the X2 pin is tied to the other side of the
crystal, it is also a sensitive node. These signals can cou-
ple into the oscillator circuit and produce double clocking
or mis-clocking, seriously affecting the accuracy of the
RTC. Care needs to be taken in layout of the RTC circuit
to avoid noise pickup. Below in Figure 19 is a suggested
layout for the X1226 or X1227 devices.
Oscillator Measurements
When a proper crystal is selected and the layout guide-
lines above are observed, the oscillator should start up in
most circuits in less than one second. Some circuits may
take slightly longer, but startup should definitely occur in
less than 5 seconds. When testing RTC circuits, the most
common impulse is to apply a scope probe to the circuit at
the X2 pin (oscillator output) and observe the waveform.
DO NOT DO THIS! Although in some cases you may see
a useable waveform, due to the parasitics (usually 10pF
to ground) applied with the scope probe, there will be no
useful information in that waveform other than the fact
that the circuit is oscillating. The X2 output is sensitive to
capacitive impedance so the voltage levels and the fre-
quency will be affected by the parasitic elements in the
scope probe. Applying a scope probe can possibly cause
a faulty oscillator to start up, hiding other issues (although
in the Intersil RTC’s, the internal circuitry assures startup
when using the proper crystal and layout). The best way
to analyze the RTC circuit is to power it up and read the
real time clock as time advances.
Figure 19. Suggested Layout for Intersil RTC in SO-8
Backup Battery Operation
Many types of batteries can be used with the Intersil
RTC products. 3.0V or 3.6V Lithium batteries are
appropriate, and sizes are available that can power a
Intersil RTC device for up to 10 years. Another option is
to use a supercapacitor for applications where Vcc may
disappear intermittently for short periods of time.
Depending on the value of supercapacitor used,
backup time can last from a few days to two weeks
(with >1F). A simple silicon or Schottky barrier diode
can be used in series with Vcc to charge the superca-
pacitor, which is connected to the Vback pin. Do not
use the diode to charge a battery (especially lithium
batteries!).
The X1 and X2 connections to the crystal are to be kept
as short as possible. A thick ground trace around the
crystal is advised to minimize noise intrusion, but ground
near the X1 and X2 pins should be avoided as it will add
to the load capacitance at those pins. Keep in mind
these guidelines for other PCB layers in the vicinity of
the RTC device. A small decoupling capacitor at the Vcc
pin of the chip is mandatory, with a solid connection to
ground.
FN8099 Rev 2.00
May 8, 2006
Page 24 of 28
X1227
Figure 20. Supercapacitor charging circuit
the battery will be drained. A second consideration is the
trip point setting for the system RESET- function, known
as Vtrip. Vtrip is set at the factory at levels for systems
with either Vcc = 5V or 3.3V operation, with the following
standard options:
2.7-5.5V
VCC
Vback
Supercapacitor
V
V
V
V
= 4.63V ± 3%
= 4.38V ± 3%
= 2.85V ± 3%
= 2.65V ± 3%
TRIP
TRIP
TRIP
TRIP
VSS
Since the battery switchover occurs at Vcc=Vback-0.1V
(see Figure 20), the battery voltage must always be
lower than the Vcc voltage during normal operation or
The summary of conditions for backup battery operation
is given in Table 8:
Table 8. Battery Backup Operation
1. Example Application, Vcc = 5V, Vback = 3.0V
Condition
a. Normal Operation
Vcc
5.00
5.00
0-1.8
Vback
3.00
Vtrip
4.38
4.38
4.38
Iback
<<1µA
0
Reset
Notes
H
H
L
b. Vcc on with no battery
c. Backup Mode
0
1.8-3.0
<2µA
Timekeeping
only
2. Example Application, Vcc=3.3V,Vback=3.0V
Condition
a. Normal Operation
Vcc
3.30
3.30
0-1.8
Vback
3.00
Vtrip
2.65
2.65
2.65
Iback
<<1µA
0
Reset
H
H
L
b. Vcc on with no battery
c. Backup Mode
0
1.8-3.0*
<2µA*
Timekeeping
only
d. UNWANTED - Vcc ON, Vback
powering
2.65 - 3.30
> Vcc
2.65
up to 3mA
H
Internal
Vcc = Vback
*since Vback>2.65V is higher than Vtrip, the battery is powering the entire device
FN8099 Rev 2.00
May 8, 2006
Page 25 of 28
X1227
Referring to Figure 20, Vtrip applies to the “Internal Vcc”
node which powers the entire device. This means that if
Vcc is powered down and the battery voltage at Vback is
higher than the Vtrip voltage, then the entire chip will be
running from the battery. If Vback falls to lower than
Vtrip, then the chip shuts down and all outputs are dis-
abled except for the oscillator and timekeeping circuitry.
The fact that the chip can be powered from Vback is not
necessarily an issue since standby current for the RTC
devices is <2µA for this mode (called “main timekeeping
current” in the data sheet). Only when the serial inter-
face is active is there an increase in supply current, and
with Vcc powered down, the serial interface will most
likely be inactive.
PERFORMANCE DATA
Performance
I
BACK
IBACK vs. Temperature
Multi-Lot Process Variation Data
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
3.3V
1.8V
One way to prevent operation in battery backup mode
above the Vtrip level is to add a diode drop (silicon diode
preferred) to the battery to insure it is below Vtrip. This
will also provide reverse leakage protection which may
be needed to get safety agency approval.
-40
25
60
85
Temperature °C
One mode that should always be avoided is the operation
of the RTC device with Vback greater than both Vcc and
Vtrip (Condition 2d in Table 8). This will cause the battery to
drain quickly as serial bus communication and non-volatile
writes will require higher supplier current.
FN8099 Rev 2.00
May 8, 2006
Page 26 of 28
X1227
Small Outline Package Family (SO)
A
D
h X 45°
(N/2)+1
N
A
PIN #1
I.D. MARK
E1
E
c
SEE DETAIL “X”
1
(N/2)
B
L1
0.010 M
C A B
e
H
C
A2
A1
GAUGE
PLANE
SEATING
PLANE
0.010
L
4° ±4°
0.004 C
b
0.010 M
C
A
B
DETAIL X
MDP0027
SMALL OUTLINE PACKAGE FAMILY (SO)
SO16
(0.150”)
SO16 (0.300”)
(SOL-16)
SO20
SO24
(SOL-24)
SO28
(SOL-28)
SYMBOL
SO-8
0.068
0.006
0.057
0.017
0.009
0.193
0.236
0.154
0.050
0.025
0.041
0.013
8
SO-14
0.068
0.006
0.057
0.017
0.009
0.341
0.236
0.154
0.050
0.025
0.041
0.013
14
(SOL-20)
0.104
0.007
0.092
0.017
0.011
0.504
0.406
0.295
0.050
0.030
0.056
0.020
20
TOLERANCE
MAX
NOTES
A
A1
A2
b
0.068
0.006
0.057
0.017
0.009
0.390
0.236
0.154
0.050
0.025
0.041
0.013
16
0.104
0.007
0.092
0.017
0.011
0.406
0.406
0.295
0.050
0.030
0.056
0.020
16
0.104
0.007
0.092
0.017
0.011
0.606
0.406
0.295
0.050
0.030
0.056
0.020
24
0.104
0.007
0.092
0.017
0.011
0.704
0.406
0.295
0.050
0.030
0.056
0.020
28
-
0.003
0.002
0.003
0.001
0.004
0.008
0.004
Basic
-
-
-
c
-
D
1, 3
E
-
E1
e
2, 3
-
L
0.009
Basic
-
L1
h
-
Reference
Reference
-
N
-
Rev. L 2/01
NOTES:
1. Plastic or metal protrusions of 0.006” maximum per side are not included.
2. Plastic interlead protrusions of 0.010” maximum per side are not included.
3. Dimensions “D” and “E1” are measured at Datum Plane “H”.
4. Dimensioning and tolerancing per ASME Y14.5M-1994
FN8099 Rev 2.00
May 8, 2006
Page 27 of 28
X1227
Thin Shrink Small Outline Plastic Packages (TSSOP)
M8.173
N
8 LEAD THIN SHRINK NARROW BODY SMALL OUTLINE
PLASTIC PACKAGE
INDEX
AREA
0.25(0.010)
M
B M
E
E1
-B-
INCHES
MIN
MILLIMETERS
GAUGE
PLANE
SYMBOL
MAX
0.047
0.006
0.051
0.0118
0.0079
0.120
0.177
MIN
-
MAX
1.20
0.15
1.05
0.30
0.20
3.05
4.50
NOTES
A
A1
A2
b
-
-
1
2
3
0.002
0.031
0.0075
0.0035
0.116
0.169
0.05
0.80
0.19
0.09
2.95
4.30
-
L
0.25
0.010
-
0.05(0.002)
SEATING PLANE
A
9
-A-
D
c
-
D
3
-C-
E1
e
4
A2
e
A1
0.026 BSC
0.65 BSC
-
c
b
0.10(0.004)
E
0.246
0.256
6.25
0.45
6.50
0.75
-
0.10(0.004) M
C
A M B S
L
0.0177
0.0295
6
N
8
8
7
NOTES:
0o
8o
0o
8o
-
1. These package dimensions are within allowable dimensions of
JEDEC MO-153-AC, Issue E.
Rev. 1 12/00
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm
(0.006 inch) per side.
4. Dimension “E1” does not include interlead flash or protrusions. Inter-
lead flash and protrusions shall not exceed 0.15mm (0.006 inch) per
side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “b” does not include dambar protrusion. Allowable dambar
protrusion shall be 0.08mm (0.003 inch) total in excess of “b” dimen-
sion at maximum material condition. Minimum space between protru-
sion and adjacent lead is 0.07mm (0.0027 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact. (Angles in degrees)
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FN8099 Rev 2.00
May 8, 2006
Page 28 of 28
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