X1287S14I-4.5A [RENESAS]
Real Time Clock, Volatile, CMOS, PDSO14, PLASTIC, SOIC-14;
| 型号： | X1287S14I-4.5A |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | Real Time Clock, Volatile, CMOS, PDSO14, PLASTIC, SOIC-14 光电二极管 |
| 文件： | 总26页 (文件大小：303K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Preliminary Information
256K
2-Wire™ RTC
X1287
Real Time Clock/Calendar/CPU Supervisor with EEPROM
FEATURES
DESCRIPTION
• Selectable Watchdog Timer (0.25,s 0.75s, 1.75s, off)
• Power On Reset (250ms)
• Low Voltage Reset
The X1287 is a Real Time Clock with clock/calendar
CPU Supervisor circuits and two polled alarms. The dual
port clock and alarm registers allow the clock to oper-
ate, without loss of accuracy, even during read and
write operations.
• 2 Polled Alarms
—Settable on the Second, 10s of Seconds,
Minute, 10s of Minutes, Hour, Day, Month, or
Day of the Week
The clock/calendar provides functionality that is con-
trollable and readable through a set of registers. The
clock, using a low cost 32.768kHz crystal input, accu-
rately tracks the time in seconds, minutes, hours, date,
day, month and years. It has leap year correction,
automatic adjustment for the year 2000 and months
with less than 31 days.
• 2 Wire Interface interoperable with I2C.
—400kHz data transfer rate
• Secondary Power Supply Input with internal
switch-over circuitry.
• Year 2000 Compliant RTC
• 32K x 8 Bits of EEPROM
—64 Byte Page Write Mode
—3 bit Block Lock
• Low Power CMOS
—<1µA Operating Current
—<3mA Active Current - EEPROM Program
—<400µA Active Current - EEPROM Read
• Single Byte Write Capability
• Typical Nonvolatile Write Cycle Time: 5ms
• High Reliability
—100,000 Endurance Cycles
—Guaranteed Data Retention: 100 Years
• Small Package Options
The X1287 provides a watchdog timer with 3 selectable
timeout periods and off. The watchdog activates a
RESET pin when it expires. The reset also goes active
when Vcc drops below a fixed trip point. There are two
alarms where a match is monitored by polling status bits.
The device offers a backup power input pin. This Vback
pin allows the device to be backed up by a non-
rechargeable battery. The RTC is fully operational from
1.8 to 6 volts.
The X1287 provides a 256K bits EEPROM array, giv-
ing a safe, secure memory for critical user and configura-
tion data. This memory is unaffected by complete
failure of the main and backup supplies.
—14-Lead SOIC, 14-Lead TSSOP
BLOCK DIAGRAM
X1
Timer
Calendar
Logic
Frequency
Divider
1Hz
Time
Keeping
Registers
32.768kHz
Oscillator
X2
(SRAM)
Serial
Interface
Decoder
Control/
Status
Control
Decode
Logic
Compare
Registers
Registers
SCL
SDA
Alarm
(EEPROM)
(SRAM)
Alarm Regs
(EEPROM)
8
256K
EEPROM
ARRAY
Watchdog
Timer
Low Voltage
Reset
RESET
Xicor, Inc. 2000 Patents Pending
9900-3021.1 3/28/01 EP
Characteristics subject to change without notice. 1 of 26
X1287
PIN DESCRIPTIONS
Figure 1. Recommended Crystal connection
X1287
14 pin SOIC/TSSOP
X1
X2
V
NC
CC
1
2
14
13
12
11
10
9
NC
NC
NC
V
NC
NC
X1
3
4
5
6
POWER CONTROL OPERATION
X2
Back
The Power control circuit accepts a V
and a V
CC
BACK
RESET
SCC
SDA
input. The power control circuit will switch to V
when V < V
BACK
V
7
8
SS
- 0.2V. It will switch back to V
CC
CC
BACK
when V exceeds V
.
CC
BACK
Figure 2. Power Control
Serial Clock (SCL)
The SCL input is used to clock all data into and out of
the device. The input buffer on this pin is always active
(not gated).
V
CC
Internal
Voltage
V
BACK
= V
Serial Data (SDA)
V
-0.2V
BACK
CC
SDA is a bidirectional pin used to transfer data into and
out of the device. It has an open drain output and may
be wire ORed with other open drain or open collector
outputs.The input buffer is always active (not gated).
REAL TIME CLOCK OPERATION
An open drain output requires the use of a pull-up
resistor. The output circuitry controls the fall time of the
output signal with the use of a slope controlled pull-
down. The circuit is designed for 400kHz 2-wire inter-
face speeds.
The Real Time Clock (RTC) uses an external,
32.768KHz quartz crystal to maintain an accurate
internal representation of the year, month, day, date,
hour, minute, and seconds. The RTC has leap-year
correction and century byte. The clock also corrects for
months having fewer than 31 days and has a bit that
controls 24 hour or AM/PM format. When the X1287
V
BACK
This input provides a backup supply voltage to the
device. V supplies power to the device in the
powers up after the loss of both V
and V
, the
CC
BACK
BACK
clock will not increment until at least one byte is written
to the clock register.
event the V supply fails.
CC
RESET Output - RESET
Reading the Real Time Clock
This is a reset signal output. This signal notifies a host
processor that the watchdog time period has expired or
The RTC is read by initiating a Read command and
specifying the address corresponding to the register of
the Real Time Clock. The RTC Registers can then be
read in a Sequential Read Mode. Since the clock runs
continuously and a read takes a finite amount of time,
there is the possibility that the clock could change dur-
ing the course of a read operation. In this device, the
time is latched by the read command (falling edge of
the clock on the ACK bit prior to RTC data output) into
a separate latch to avoid time changes during the read
operation. The clock continues to run. Alarms occuring
during a read are unaffected by the read operation.
that the voltage has dropped below a fixed V
threshold. It is an open drain active LOW output.
TRIP
X1, X2
The X1 and X2 pins are the input and output, respec-
tively, of an inverting amplifier that can be configured
for use as an on-chip oscillator. A 32.768kHz quartz
crystal is used. Recommended crystals are Seiko VT-200
or Espson C-002RX. The crystal supplies a timebase for
a clock/oscillator. The internal clock can be driven by an
external signal on X1, with X2 left unconnected.
Characteristics subject to change without notice. 2 of 26
X1287
Writing to the Real Time Clock
ing the end of a section, will wrap around to the start of
the section. A read or page write can begin at any
address in the CCR.
The time and date may be set by writing to the RTC
registers. To avoid changing the current time by an
uncompleted write operation, the current time value is
loaded into a seperate buffer at the falling edge of the
clock on the ACK bit before the RTC data input bytes,
the clock continues to run. The new serial input data
replaces the values in the buffer. This new RTC value
is loaded back into the RTC Register by a stop bit at
the end of a valid write sequence. An invalid write
operation aborts the time update procedure and the
contents of the buffer are discarded. After a valid write
operation the RTC will reflect the newly loaded data
beginning with the first “one second” clock cycle after
the stop bit. The RTC continues to update the time
while an RTC register write is in progress and the RTC
continues to run during any nonvolatile write
sequences. A single byte may be written to the RTC
without affecting the other bytes.
Section 5) is a volatile register. It is not necessary to
set the RWEL bit prior to writing the status register.
Section 5) supports a single byte read or write only.
Continued reads or writes from this section terminates
the operation.
The state of the CCR can be read by performing a ran-
dom read at any address in the CCR at any time. This
returns the contents of that register location. Addi-
tional registers are read by performing a sequential
read. The read instruction latches all Clock registers
into a buffer, so an update of the clock does not
change the time being read. A sequential read of the
CCR will not result in the output of data from the mem-
ory array. At the end of a read, the master supplies a
stop condition to end the operation and free the bus.
After a read of the CCR, the address remains at the
previous address +1 so the user can execute a current
address read of the CCR and continue reading the
next Register.
CLOCK/CONTROL REGISTERS (CCR)
The Control/Clock Registers are located in an area
separate from the EEPROM array and are only acces-
sible following a slave byte of “1101111x” and reads or
writes to addresses [0000h:003Fh].
ALARM REGISTERS
There are two alarm registers whose contents mimic
the contents of the RTC register, but add enable bits
and exclude the 24 hour time selection bit. The enable
bits specify which registers to use in the comparison
between the Alarm and Real Time Registers. For
example:
CCR access
The contents of the CCR can be modified by perform-
ing a byte or a page write operation directly to any
address in the CCR. Prior to writing to the CCR
(except the status register), however, the WEL and
RWEL bits must be set using a two step process (See
section “Writing to the Clock/Control Registers.”)
—The user can set the X1287 to alarm every Wednes-
day at 8:00 AM by setting the EDWn, the EHRn and
EMNn enable bits to ‘0’ and setting the DWAn,
HRAn and MNAn Alarm registers to 8:00 AM
Wednesday.
The CCR is divided into 5 sections.These are:
1. Alarm 0 (8 bytes)
2. Alarm 1 (8 bytes)
3. Control (2 bytes)
4. Real Time Clock (8 bytes)
5. Status (1 byte)
—A daily alarm for 9:30PM results when the EHRn
and EMNn enable bits are set to ‘0’ and the HRAn
and MNAn registers set 9:30 PM.
—Setting the EMOn bit in combination with other
enable bits and a specific alarm time, the user can
establish an alarm that triggers at the same time
once a year.
Sections 1) through 3) are nonvolatile and Sections 4)
and 5) are volatile. Each register is read and written
through buffers. The non-volatile portion (or the
counter portion of the RTC) is updated only if RWEL is
set and only after a valid write operation and stop bit.
A sequential read or page write operation provides
access to the contents of only one section of the CCR
per operation. Access to another section requires a
new operation. Continued reads or writes, once reach-
When there is a match, an alarm flag is set.The occur-
ance of an alarm can only be determined by polling
the AL0 and AL1 bits.
The alarm enable bits are located in the MSB of the
particular register. When all enable bits are set to ‘0’,
there are no alarms.
Characteristics subject to change without notice. 3 of 26
X1287
Table 1. Clock/Control Memory Map
Bit
Reg
Addr.
Type
Range
0
Name
7
6
5
4
3
2
1
(optional)
003F
0037
0036
0035
0034
0033
0032
0031
0030
0013
0012
0011
0010
Status
SR
Y2K
DW
YR
BAT
0
AL1
0
AL0
Y2K21
0
0
Y2K20
0
0
Y2K13
0
RWEL
0
WEL
0
RTCF
Y2K10
DY0
Y10
G10
D10
H10
M10
S10
DTR0
ATR0
x
00h
20h
06h
00h
01h
01h
12h
00h
00h
00h
00h
00h
00h
RTC
(SRAM)
19/20
0-6
0
0
DY2
Y12
G12
D12
H12
M12
S12
DTR2
ATR2
x
DY1
Y11
G11
D11
H11
M11
S11
DTR1
ATR1
x
Y23
0
Y22
0
Y21
0
Y20
G20
D20
H20
M20
S20
0
Y13
G13
D13
H13
M13
S13
0
0-99
1-12
1-31
0-23
0-59
0-59
MO
DT
0
0
D21
H21
M21
S21
0
HR
MIL
0
0
MN
SC
M22
S22
0
0
DTR
ATR
INT
BL
0
0
0
ATR5
AL0E
BP0
ATR4
x
ATR3
x
IM
BP2
AL1E
BP1
Control
(E2PROM)
WD1
WD0
0
0
0
000F
000E
000D
000C
000B
000A
0009
0008
0007
0006
0005
0004
0003
0002
0001
0000
Alarm1
(E2PROM)
Y2K1
0
0
0
A1Y2K21 A1Y2K20 A1Y2K13
0
0
A1Y2K10 19/20
20
DWA1 EDW1
YRA1
0
0
0
DY2
DY1
DY0
0-6
80h
Unused - Default = RTC Year value (No EEPROM) - Future expansion
MOA1 EMO1
0
0
A1G20
A1D20
A1H20
A1M20
A1S20
A1G13
A1D13
A1H13
A1M13
A1S13
A1G12
A1D12
A1H12
A1M12
A1S12
0
A1G11
A1D11
A1H11
A1M11
A1S11
0
A1G10
A1D10
A1H10
A1M10
A1S10
1-12
1-31
0-23
0-59
0-59
80h
80h
80h
80h
80h
20h
80h
DTA1
HRA1
EDT1
EHR1
0
A1D21
A1H21
A1M21
A1S21
0
A1M22
A1S22
0
MNA1 EMN1
SCA1
Y2K0
ESC1
0
Alarm0
(E2PROM)
A0Y2K21 A0Y2K20 A0Y2K13
A0Y2K10 19/20
DWA0 EDW0
YRA0
0
0
0
0
DY2
DY1
DY0
0-6
Unused - Default = RTC Year value (No EEPROM) - Future expansion
MOA0 EMO0
0
0
0
A0G20
A0D20
A0H20
A0M20
A0S20
A0G13
A0D13
A0H13
A0M13
A0S13
A0G12
A0D12
A0H12
A0M12
A0S12
A0G11
A0D11
A0H11
A0M11
A0S11
A0G10
A0D10
A0H10
A0M10
A0S10
1-12
1-31
0-23
0-59
0-59
80h
80h
80h
80h
80h
DTA0
HRA0
EDT0
EHR0
A0D21
A0H21
A0M21
A0S21
0
MNA0 EMN0
SCA0 ESC0
A0M22
A0S22
REAL TIME CLOCK REGISTERS
Year 2000 (Y2K)
Day of the Week Register (DW)
This register provides a Day of the Week status and
uses three bits DY2 to DY0 to represent the seven
days of the week. The counter advances in the cycle
0-1-2-3-4-5-6-0-1-2-... The assignment of a numerical
value to a specific day of the week is arbitrary and may
be decided by the system software designer. The
Clock Default values define 0=Sunday.
The X1287 has a century byte that “rolls over” from 19
to 20 when the years byte changes from 99 to 00. The
Y2K byte can contain only the values of 19 or 20.
Characteristics subject to change without notice. 4 of 26
X1287
Clock/Calendar Register (YR, MO, DT, HR, MN, SC)
RWEL: Register Write Enable Latch—Volatile
These registers depict BCD representations of the
time. As such, SC (Seconds) and MN (Minutes) range
from 00 to 59, HR (Hour) is 1 to 12 with an AM or PM
indicator (H21 bit) or 0 to 23 (with MIL=1), DT (Date) is
1 to 31, MO (Month) is 1 to 12, YR (year) is 0 to 99.
This bit is a volatile latch that powers up in the LOW
(disabled) state. The RWEL bit must be set to “1” prior
to any writes to the Clock/Control Registers. Writes to
RWEL bit do not cause a nonvolatile write cycle, so the
device is ready for the next operation immediately after
the stop condition. A write to the CCR requires both
the RWEL and WEL bits to be set in a specific
sequence.
24 Hour Time
If the MIL bit of the HR register is 1, the RTC uses a
24-hour format. If the MIL bit is 0, the RTC uses a 12-
hour format and bit H21 functions as an AM/PM indi-
cator with a ‘1’ representing PM. The clock defaults to
Standard Time with H21=0.
WEL: Write Enable Latch—Volatile
The WEL bit controls the access to the CCR and
memory array during a write operation. This bit is a
volatile latch that powers up in the LOW (disabled)
state. While the WEL bit is LOW, writes to the CCR or
any array address will be ignored (no acknowledge will
be issued after the Data Byte). The WEL bit is set by
writing a “1” to the WEL bit and zeroes to the other bits
of the Status Register. Once set, WEL remains set
until either reset to 0 (by writing a “0” to the WEL bit
and zeroes to the other bits of the Status Register) or
until the part powers up again. Writes to WEL bit do
not cause a nonvolatile write write cycle, so the device
is ready for the next operation immediately after the
stop condition.
Leap Years
Leap years add the day February 29 and are defined
as those years that are divisible by 4.Years divisible by
100 are not leap years, unless they are also divisible
by 400. This means that the year 2000 is a leap year,
the year 2100 is not. The X1287 does not correct for
the leap year in the year 2100.
STATUS REGISTER (SR)
The Status Register is located in the RTC area at
address 003FH. This is a volatile register only and is
used to control the WEL and RWEL write enable
latches, read two power status and two alarm bits.This
register is seperate from both the array and the Clock/
Control Registers (CCR).
RTCF: Real Time Clock Fail Bit—Volatile
This bit is set to a ‘1’ after a total power failure. This is
a read only bit that is set by hardware when the device
powers up after having lost all power to the device.
Table 2. Status Register (SR)
The bit is set regardless of whether V
or V
is
CC
BACK
applied first.The loss of one or the other supplies does
not result in setting the RTCF bit.The first valid write to
the RTC (writing one byte is sufficient) resets the
RTCF bit to ‘0’.
Addr
003Fh BAT AL1 AL0
Default
7
6
5
4
3
2
1
0
0
0
0
0
RWEL WEL RTCF
0
0
0
0
0
0
Unused Bits:
BAT: Battery Supply—Volatile
This bit set to “1” indicates that the device is operating
These devices do not use bits 3 or 4, but must have a
zero in these bit positions. The Data Byte output dur-
ing a SR read will contain zeros in these bit locations.
from V , not V . It is a read only bit and is set/
BACK
CC
reset by hardware.
CONTROL REGISTER
AL1, AL0: Alarm bits—Volatile
Block Protect Bits—BP2, BP1, BP0—(Nonvolatile)
These bits announce if either alarm 1 or alarm 2 match
the real time clock. If there is a match, the respective
bit is set to ‘1’. The falling edge of the last data bit in a
SR Read operation resets the flags. Note: Only the AL
bits that are set when an SR read starts will be reset.
An alarm bit that is set by an alarm occuring during an
SR read operation will remain set after the read opera-
tion is complete.
The Block Protect Bits, BP2, BP1 and BP0, determine
which blocks of the array are write protected. A write to
a protected block of memory is ignored. The block pro-
tect bits will prevent write operations to one of eight
segments of the array. The partitions are described in
Table 3 .
Characteristics subject to change without notice. 5 of 26
X1287
Table 3. Block Protect Bits
frequency compensation. With the combination of
digital and analog trimming can give up to 90ppm
adjustment! The current design ATR0 is a 0.5pf when
it equals to 1, ATR1 is a 1pf when it equals to 1, ATR2
is a 2pf when it equals to 1, ATR3 is a 4pf when it
equals to 1, ATR4 is a 7pf when it equals to 1 and
ATR5 is a 12.5pf when it equals to 0! When all bits are
zero the loading capacitance is equal to 12.5pf that is
for “Seiko VT200” crystal as a default loading. There is
also a fixed 10pf capacitance for X1 and X2.
Protected
Addresses
Array Lock
X1287
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
None
None
6000h - 7FFFh
4000h - 7FFFh
0000h - 7FFFh
0000h - 003Fh
0000h - 007Fh
0000h - 00FFh
0000h - 01FFh
Upper 1/4
Upper 1/2
Full Array
First Page
First 2 pgs
First 4 pgs
First 8 Pgs
WRITING TO THE CLOCK/CONTROL REGISTERS
Changing any of the nonvolatile bits of the clock/con-
trol register requires the following steps:
—Write a 02H to the Status Register to set the Write
Enable Latch (WEL). This is a volatile operation, so
there is no delay after the write. (Operation pre-
ceeded by a start and ended with a stop).
Watchdog Timer Control Bits
The bits WD1 and WD0 control the period of the
Watchdog Timer. See Table 4 for options.
—Write a 06H to the Status Register to set both the
Register Write Enable Latch (RWEL) and the WEL
bit. This is also a volatile cycle. The zeros in the data
byte are required. (Operation preceeded by a start
and ended with a stop).
Table 4. Watchdog Timer Time Out Options
WD1 WD0
Watchdog Time-Out Period
0
0
1
1
0
1
0
1
1.75 Seconds
750 milliseconds
250 milliseconds
Disabled
—Write one to 8 bytes to the Clock/Control Registers
with the desired clock, alarm, or control data. This
sequence starts with a start bit, requires a slave byte
of “11011110” and an address within the CCR and is
terminated by a stop bit. A write to the CCR changes
EEPROM values so these initiate a nonvolatile write
cycle and will take up to 10ms to complete. Writes to
undefined areas have no effect. The RWEL bit is
reset by the completion of a nonvolatile write write
cycle, so the sequence must be repeated to again
initiate another change to the CCR contents. If the
sequence is not completed for any reason (by send-
ing an incorrect number of bits or sending a start
instead of a stop, for example) the RWEL bit is not
reset and the device remains in an active mode.
Digital Trimming Register (DTR)—DTR2, DFTR1
and DTR0-(Nonvolatile)
The digital trimming Bits DTR2, DTR1 and DTR0
adjust the number of count per second and average
the ppm error to achieve a better time over a long
period. DTR2 is a sign when equal to 1 means positive
ppm and 0 means negative ppm compensation. DTR1
will give 10 ppm adjustment and DTR2 will give 20ppm
adjustment. A range from -30ppm to +30ppm can be
represented by using three bits above.
—Writing all zeros to the status register resets both
the WEL and RWEL bits.
Analog Trimming Register (ATR)—ATR5, ATR4...
and ATR0-(Nonvolatile)
—A read operation occurring between any of the pre-
vious operations will not interrupt the register write
operation.
Six analog trimming Bits from ATR5 to DTR0 are pro-
vided to adjust the on-chip loading capacitance range
from 10pf to 39.5pf for X1 and X2. The effective load
capacitance range from 5pf to 19.75pf. Each bit has
different weight for capacitance adjustment. This will
allow 6pf or 12.5pf crystal being used and widen the
selection. Also it provides +60ppm to -40ppm a better
—The RWEL and WEL bits can be reset by writing a 0
to the Status Register.
Characteristics subject to change without notice. 6 of 26
X1287
POWER ON RESET
Watchdog Timer Restart
The Watchdog Timer is restarted by a falling edge of
SDA when the SCL line is high. This is also referred to
as start condition. The restart signal restarts the
watchdog timer counter, resetting the period of the
counter back to the maximum. If another start fails to
be detected prior to the watchdog timer expiration,
then the reset pin becomes active. In the event that the
restart signal occurs during a reset time-out period,
the restart will have no effect.
Application of power to the X1287 activates a Power
On Reset Circuit that pulls the RESET pin active. This
signal provides several benefits.
—It prevents the system microprocessor from starting to
operate with insufficient voltage.
—It prevents the processor from operating prior to stabili-
zation of the oscillator.
—It allows time for an FPGA to download its configura-
tion prior to initialization of the circuit.
LOW VOLTAGE RESET OPERATION
—It prevents communication to the EEPROM, greatly
reducing the likelihood of data corruption on power up.
When a power failure occurs, and the voltage to the
part drops below a fixed v
voltage, a reset pulse is
TRIP
issued to the host microcontroller. The circuitry moni-
When Vcc exceeds the device V
for 250ms the circuit releases RESET, allowing the
system to begin operation.
threshold value
TRIP
tors the V line with a voltage comparator which
CC
senses a preset threshold voltage. Power up and
power down waveforms are shown in Figure 4. The
Low Voltage Reset circuit is to be designed so the
RESET signal is valid down to 1.0V.
WATCHDOG TIMER OPERATION
The watchdog timer is selectable. By writing a value to
WD1 and WD0, the watchdog timer can be set to 3 dif-
ferent time out periods or off. When the Watchdog
timer is set to off, the watchdog circuit is configured for
low power operation.
When the low voltage reset signal is active, the opera-
tion of any in progress nonvolatile write write cycle is
unaffected, allowing a nonvolatile write to continue as
long as possible (down to the power on reset voltage).
The low voltage reset signal, when active, terminates
in progress communications to the device and pre-
vents new commands, to reduce the likelihod of data
corruption.
Figure 3. Watchdog Restart/Timeout
t
t
>t
RSP
RSP WDO
t
t
>t
t
RST
t
<t
RST
RSP WDO
RSP WDO
SCL
SDA
RESET
Note: All inputs are ignored during the active reset period (t
).
RST
Characteristics subject to change without notice. 7 of 26
X1287
Figure 4. Power On Reset and Low Voltage Reset
v
TRIP
V
CC
t
t
PURST
PURST
t
RPD
t
F
t
R
RESET
V
RVALID
V
THRESHOLD RESET PROCEDURE
make the change. If the new setting is to be lower than
the current setting, then it is necessary to reset the trip
point before setting the new value.
CC
The X1287 is shipped with a standard Vcc threshold
(V ) voltage.This value will not change over normal
TRIP
operating and storage conditions. However, in applica-
tions where the standard V is not exactly right, or if
To set the new V
threshold voltage to the Vcc pin and tie the X1 pin to
voltage, apply the desired V
TRIP
TRIP
TRIP
higher precision is needed in the V
value, the
the programming voltage V . Then write data 00h to
TRIP
P
X1287 threshold may be adjusted. The procedure is
described below, and uses the application of a non-
volatile write control signal.
address 01h. The stop bit following a valid write opera-
tion initiates the V
programming sequence. Bring
TRIP
X1 LOW to complete the operation. Note: this opera-
tion also writes 00h to address 01h of the EEPROM
array.
Setting the V
Voltage
TRIP
This procedure is used to set the V
to a higher
TRIP
voltage value. For example, if the current V
is 4.4V
TRIP
and the new V
is 4.6V, this procedure will directly
TRIP
Figure 5. Set V
Level Sequence (V =desired V value.)
TRIP
TRIP
CC
V
= 15-18V
P
X1
0
1 2 3 4 5 6 7
0
1 2 3 4 5 6 7
0
1 2 3 4 5 6 7
SCL
SDA
A0h
01h
00h
Characteristics subject to change without notice. 8 of 26
X1287
Resetting the V
Voltage
To reset the new V
voltage, apply more than 3V to
TRIP
TRIP
the Vcc pin and tie the X1 pin to the programming volt-
age V . Then write 00h to address 03h. The stop bit of
This procedure is used to set the V
voltage level. For example, if the current V
to a “native”
TRIP
P
is 4.4V
TRIP
a valid write operation initiates the V
programming
TRIP
and the new V
must be 4.0V, then the V
must
TRIP
TRIP
sequence. Bring X1 LOW to complete the operation.
Note: this operation also writes 00h to address 03h of
the EEPROM array.
be reset. When V
is reset, the new V
is some-
TRIP
TRIP
thing less than 1.7V. This procedure must be used to
set the voltage to a lower value.
Figure 6. Reset V
Level Sequence (V
> 3V. WP = 15-18V)
TRIP
CC
V
= 15-18V
P
X1
0
1 2 3 4 5 6 7
0
1
2
3 4 5 6 7
0
1 2 3 4 5 6 7
SCL
SDA
A0h
03h
00h
Figure 7. Sample V
Reset Circuit
TRIP
V
P
4.7K
Adjust
Run
µC
RESET
1
8
2
3
4
7
6
5
X1287
V
TRIP
Adj.
SCL
SDA
SERIAL COMMUNICATION
Interface Conventions
Clock and Data
Data states on the SDA line can change only during
SCL LOW. SDA state changes during SCL HIGH are
reserved for indicating start and stop conditions. See
Figure 8.
The device supports a bidirectional bus oriented proto-
col. The protocol defines any device that sends data
onto the bus as a transmitter, and the receiving device
as the receiver. The device controlling the transfer is
called the master and the device being controlled is
called the slave. The master always initiates data
transfers, and provides the clock for both transmit and
receive operations. Therefore, the devices in this fam-
ily operate as slaves in all applications.
Characteristics subject to change without notice. 9 of 26
X1287
Figure 8. Valid Data Changes on the SDA Bus
SCL
SDA
Data Stable
Data Change
Data Stable
Start Condition
the device into the Standby power mode after a read
sequence. A stop condition can only be issued after the
transmitting device has released the bus. See Figure 8.
All commands are preceded by the start condition,
which is a HIGH to LOW transition of SDA when SCL
is HIGH. The device continuously monitors the SDA
and SCL lines for the start condition and will not
respond to any command until this condition has been
met. See Figure 9.
Acknowledge
Acknowledge is a software convention used to indicate
successful data transfer. The transmitting device,
either master or slave, will release the bus after trans-
mitting eight bits. During the ninth clock cycle, the
receiver will pull the SDA line LOW to acknowledge
that it received the eight bits of data. Refer to Figure 10.
Stop Condition
All communications must be terminated by a stop con-
dition, which is a LOW to HIGH transition of SDA when
SCL is HIGH. The stop condition is also used to place
Figure 9. Valid Start and Stop Conditions
SCL
SDA
Start
Stop
The device will respond with an acknowledge after rec-
ognition of a start condition and if the correct Device
Identifier and Select bits are contained in the Slave
Address Byte. If a write operation is selected, the
device will respond with an acknowledge after the
receipt of each subsequent eight bit word. The device
will acknowledge all incoming data and address bytes,
except for:
—The 2nd Data Byte of a Status Register Write Oper-
ation (only 1 data byte is allowed)
In the read mode, the device will transmit eight bits of
data, release the SDA line, then monitor the line for an
acknowledge. If an acknowledge is detected and no
stop condition is generated by the master, the device
will continue to transmit data. The device will terminate
further data transmissions if an acknowledge is not
detected. The master must then issue a stop condition
to return the device to Standby mode and place the
device into a known state.
—The Slave Address Byte when the Device Identifier
and/or Select bits are incorrect
—All Data Bytes of a write when the WEL in the Write
Protect Register is LOW
Characteristics subject to change without notice. 10 of 26
X1287
Figure 10. Acknowledge Response From Receiver
SCL from
Master
1
8
9
Data Output
from Transmitter
Data Output
from Receiver
Start
Acknowledge
Write Operations
Byte Write
responds with an acknowledge. After receiving both
address bytes the X1287 awaits the eight bits of data.
After receiving the 8 data bits, the X1287 again
responds with an acknowledge. The master then ter-
minates the transfer by generating a stop condition.
The X1287 then begins an internal write cycle of the
data to the nonvolatile memory. During the internal
write cycle, the device inputs are disabled, so the
device will not respond to any requests from the master.
The SDA output is at high impedance. See Figure 11.
For a write operation, the device requires the Slave
Address Byte and the Word Address Bytes. This gives
the master access to any one of the words in the array
or CCR. (Note: Prior to writing to the CCR, the master
must write a 02h, then 06h to the status register in two
preceding operations to enable the write operation.
See “Writing to the Clock/Control Registers” on page
6.) Upon receipt of each address byte, the X1287
Figure 11. Byte Write Sequence
S
t
a
r
Signals from
the Master
S
t
o
p
Slave
Address
Word
Address 1
Word
Address 0
t
Data
SDA Bus
1
1 1 1 0 0 0 00 0
A
C
K
A
C
K
A
C
K
A
C
K
Signals From
The Slave
Figure 12. Writing 30 bytes to a 64-byte memory page starting at adress 40.
7 Bytes
23 Bytes
Address Pointer
Address
40
Address
= 6
Address
63
Ends Here
Addr = 7
Characteristics subject to change without notice. 11 of 26
X1287
A write to a protected block of memory is ignored, but
will still receive an acknowledge. At the end of the
write command, the X1287 will not initiate an internal
write cycle, and will continue to ACK commands.
memory and loads 30 bytes, then the first 23 bytes are
written to addresses 40 through 63, and the last 7
bytes are written to columns 0 through 6. Afterwards,
the address counter would point to location 7 on the
page that was just written. If the master supplies more
than the maximum bytes in a page, then the previously
loaded data is over written by the new data, one byte
at a time.
Page Write
The X1287 has a page write operation. It is initiated in
the same manner as the byte write operation; but
instead of terminating the write cycle after the first
data byte is transferred, the master can transmit up to
63 more bytes to the memory array and up to 7 more
bytes to the clock/control registers. (Note: Prior to writ-
ing to the CCR, the master must write a 02h, then 06h
to the status register in two preceding operations to
enable the write operation. See “Writing to the Clock/
Control Registers” on page 6.)
The master terminates the Data Byte loading by issu-
ing a stop condition, which causes the X1287 to begin
the nonvolatile write cycle. As with the byte write oper-
ation, all inputs are disabled until completion of the
internal write cycle. Refer to Figure 13 for the address,
acknowledge, and data transfer sequence.
Stops and Write Modes
After the receipt of each byte, the X1287 responds
with an acknowledge, and the address is internally
incremented by one. When the counter reaches the
end of the page, it “rolls over” and goes back to the
first address on the same page. This means that the
master can write 64 bytes to a memory array page or 8
bytes to a CCR section starting at any location on that
page. If the master begins writing at location 40 of the
Stop conditions that terminate write operations must
be sent by the master after sending at least 1 full data
byte and it’s associated ACK signal. If a stop is issued
in the middle of a data byte, or before 1 full data byte +
ACK is sent, then the X1287 resets itself without per-
forming the write. The contents of the array are not
affected.
Figure 13. Page Write Sequence
S
(1 ≤ n ≤64)
t
a
r
Signals from
the Master
S
t
Word
Address 1
Slave
Address
Word
Address 0
Data
(1)
Data
(n)
o
p
t
SDA Bus
1
1 1 1 0 0 0 0 0 0
A
C
K
A
C
K
A
C
K
A
C
K
Signals from
the Slave
Figure 14. Current Address Read Sequence
S
t
S
t
o
p
Signals from
the Master
Slave
Address
a
r
t
SDA Bus
1
1 1 1 1
A
C
K
Signals from
the Slave
Data
Characteristics subject to change without notice. 12 of 26
X1287
Acknowledge Polling
Figure 15. Acknowledge Polling Sequence
Disabling of the inputs during nonvolatile write cycles
can be used to take advantage of the typical 5mS write
cycle time. Once the stop condition is issued to indi-
cate the end of the master’s byte load operation, the
X1287 initiates the internal nonvolatile write cycle.
Acknowledge polling can begin immediately. To do
this, the master issues a start condition followed by the
Slave Address Byte for a write or read operation. If the
X1287 is still busy with the nonvolatile write cycle then
no ACK will be returned. When the X1287 has com-
pleted the write operation, an ACK is returned and the
host can proceed with the read or write operation.
Refer to the flow chart in Figure 15.
Byte load completed
by issuing STOP.
Enter ACK Polling
Issue START
Issue Slave
Address Byte
(Read or Write)
Issue STOP
NO
ACK
returned?
Read Operations
There are three basic read operations: Current
Address Read, Random Read, and Sequential Read.
YES
NO
nonvolatile write
Cycle complete.
Continue command
sequence?
Current Address Read
Issue STOP
Internally the X1287 contains an address counter that
maintains the address of the last word read incre-
mented by one. Therefore, if the last read was to
address n, the next read operation would access data
from address n+1. On power up, the sixteen bit
address is initialized to 0h. In this way, a current
address read immediately after the power on reset can
download the entire contents of memory starting at the
first location.Upon receipt of the Slave Address Byte
with the R/W bit set to one, the X1287 issues an
acknowledge, then transmits eight data bits. The mas-
ter terminates the read operation by not responding
with an acknowledge during the ninth clock and issue-
ing a stop condition. Refer to Figure 13 for the
address, acknowledge, and data transfer sequence.
YES
Continue normal
Read or Write
command
sequence
PROCEED
Characteristics subject to change without notice. 13 of 26
X1287
It should be noted that the ninth clock cycle of the read
operation is not a “don’t care.” To terminate a read
operation, the master must either issue a stop condi-
tion during the ninth cycle or hold SDA HIGH during
the ninth clock cycle and then issue a stop condition.
In a similar operation called “Set Current Address,” the
device sets the address if a stop is issued instead of
the second start shown in Figure 16. The X1287 then
goes into standby mode after the stop and all bus
activity will be ignored until a start is detected. This
operation loads the new address into the address
counter. The next Current Address Read operation will
read from the newly loaded address. This operation
could be useful if the master knows the next address it
needs to read, but is not ready for the data.
Random Read
Random read operations allows the master to access
any location in the X1287. Prior to issuing the Slave
Address Byte with the R/W bit set to one, the master
must first perform a “dummy” write operation.
Sequential Read
The master issues the start condition and the slave
address byte, receives an acknowledge, then issues
the word address bytes. After acknowledging receipt
of each word address byte, the master immediately
issues another start condition and the slave address
byte with the R/W bit set to one. This is followed by an
acknowledge from the device and then by the eight bit
data word. The master terminates the read operation
by not responding with an acknowledge and then issu-
ing a stop condition. Refer to Figure 16 for the
address, acknowledge, and data transfer sequence.
Sequential reads can be initiated as either a current
address read or random address read. The first data
byte is transmitted as with the other modes; however,
the master now responds with an acknowledge, indi-
cating it requires additional data. The device continues
to output data for each acknowledge received. The
master terminates the read operation by not responding
with an acknowledge and then issuing a stop condition.
Figure 16. Random Address Read Sequence
S
t
S
S
t
o
p
t
a
r
Signals from
the Master
Slave
Address
Word
Address 0
a
r
Slave
Address
Word
Address 1
t
t
SDA Bus
1
1 1 1 1
1
1 1 1 0 0 0 0 0 0
A
C
K
A
C
K
A
C
K
A
C
K
Signals from
the Slave
Data
The data output is sequential, with the data from
address n followed by the data from address n + 1.
The address counter for read operations increments
through all page and column addresses, allowing the
entire memory contents to be serially read during one
operation. At the end of the address space the counter
“rolls over” to the start of the address space and the
X1287 continues to output data for each acknowledge
received. Refer to Figure 17 for the acknowledge and
data transfer sequence.
Characteristics subject to change without notice. 14 of 26
X1287
Figure 17. Sequential Read Sequence
S
t
o
p
Slave
Address
A
C
K
A
C
K
A
C
K
Signals from
the Master
SDA Bus
1
A
C
K
Signals from
the Slave
Data
(2)
Data
(n-1)
Data
(1)
Data
(n)
(n is any integer greater than 1)
DEVICE ADDRESSING
Following the Slave Byte is a two byte word address.
The word address is either supplied by the master
device or obtained from an internal counter. On power
up the internal address counter is set to address 0h,
so a current address read of the EEPROM array starts
at address 0. When required, as part of a random
read, the master must supply the 2 Word Address
Bytes as shown in Figure 18.
Following a start condition, the master must output a
Slave Address Byte. The first four bits of the Slave
Address Byte specify access to either the EEPROM
array or to the CCR. Slave bits ‘1010’ access the
EEPROM array. Slave bits ‘1101’ access the CCR.
Bit 3 through Bit 1 of the slave byte specify the device
select bits.These are set to ‘111’.
In a random read operation, the slave byte in the
“dummy write” portion must match the slave byte in the
“read” section. That is if the random read is from the
array the slave byte must be 1010111x in both
instances. Similarly, for a random read of the Clock/
Control Registers, the slave byte must be 1101111x in
both places.
The last bit of the Slave Address Byte defines the
operation to be performed. When this R/W bit is a one,
then a read operation is selected. A zero selects a
write operation. Refer to Figure 18.
After loading the entire Slave Address Byte from the
SDA bus, the X1287 compares the device identifier
and device select bits with ‘1010111’ or ‘1101111’.
Upon a correct compare, the device outputs an
acknowledge on the SDA line.
Characteristics subject to change without notice. 15 of 26
X1287
Figure 18. Slave Address, Word Address, and Data Bytes (64 Byte pages)
Device Identifier
Slave Address Byte
Array
CCR
1
1
0
1
1
0
0
1
1
0
1
1
R/W
A8
Byte 0
High Order Word Address
Byte 1
0
0
0
0
A10
A9
Low Order Word Address
Byte 2
A7
D7
A6
D6
A5
D5
A4
D4
A3
D3
A2
D2
A1
D1
A0
D0
Data Byte
Byte 3
Characteristics subject to change without notice. 16 of 26
X1287
ABSOLUTE MAXIMUM RATINGS
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only and the functional operation
of the device at these or any other conditions above
those indicated in the operational sections of this
specification is not implied. Exposure to absolute max-
imum rating conditions for extended periods may affect
device reliability.
Temperature Under Bias ................... -65°C to +135°C
Storage Temperature......................... -65°C to +150°C
Voltage on any pin (respect to ground)....-1.0V to 7.0V
DC Output Current .............................................. 5 mA
Lead Temperature (Soldering, 10 sec) .............. 300°C
DC OPERATING CHARACTERISTICS Temperature = -40°C to +85°C, unless otherwise stated.)
Symbol
Parameter
Min
2.7
Typ
Max
5.5
Unit
V
Notes
V
Main Power Supply
Backup Power Supply
Switch to Backup Supply
Switch to Main Supply
CC
V
1.8
5.5
V
BACK
V
V
V
V
=
=
V
-0.2
V
V
4
4
CB
CC
BACK
BACK -0.1
V
V
V
BC
CC
BACK
BACK +0.1
1.2
V
= 2.7V
µA
µA
mA
mA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
CC
CC
CC
CC
I
I
I
I
Active Supply Current
1, 5, 8, 15
2, 5, 8, 15
3, 8, 9, 15
3, 8, 9, 16
3, 7, 10, 15
3, 7, 10, 16
CC1
CC2
CC3
CC4
V
= 5V
1.7
1.5
3.0
1.7
1.5
5
CC
V
= 2.7V
= 5V
Program Supply
Current (nonvolatile)
V
CC
V
= 2.7V
= 5V
Main Timekeeping
Current
V
CC
V
= 2.7V
3.8
7.5
Main Supply Current
V
= 5V
10
1.0
1.5
2
CC
V
= 1.8V
BACK
Backup Timekeeping
Current
I
I
BACK1
BACK2
V
= 5V
BACK
V
= 1.8V
1.6
7.5
BACK
Backup Supply Current
V
= 5V
10
10
10
BACK
I
Input Leakage Current
OutputLeakageCurrent
11
11
LI
I
LO
V
V
x 0.2 or
CC
V
Input LOW Voltage
Input HIGH Voltage
-0.5
2
V
V
V
4, 14
4, 14
14
IL
x 0.2
BACK
V
V
+ 0.5
CC
V
IH
+ 0.5
BACK
Schmitt Trigger Input
Hysteresis
.05 x V or
CC
V
V
related level
HYS
CC
.05 x V
BACK
V
= 2.7V
0.4
0.4
CC
V
Output LOW Voltage
Output LOW Voltage
V
V
12
13
OL
V
= 5V
CC
V
= 2.7V
= 5V
1.6
2.4
CC
V
OH
V
CC
Characteristics subject to change without notice. 17 of 26
X1287
Notes: (1) The device enters the Active state after any start, and remains active: for 9 clock cycles if the Device Select Bits in the Slave
Address Byte are incorrect or until 200nS after a stop ending a read or write operation.
(2) The device enters the Program state 200nS after a stop ending a write operation and continues for t
.
WC
(3) The device goes into the Timekeeping state 200nS after any stop, except those that initiate a nonvolatile write write cycle; t
after
WC
a stop that initiates a nonvolatile write cycle; or 9 clock cycles after any start that is not followed by the correct Device Select Bits in
the Slave Address Byte.
(4) For reference only and not tested.
(5)
(6)
(7)
(8)
(9)
V
V
V
V
V
= V x 0.1, V = V x 0.9, f
= 400KHz, SDA = Open
IL
CC
IH
CC
SCL
SCL
= V x 0.1, V = V x 0.9, f
= 400KHz, f
= 400KHz, V = 1.22 x V Min
SDA CC CC
IL
CC
IH
CC
= 0V.
CC
= 0V.
BACK
=V
=V , Others=GND or V
CC
SDA SCL CC
(10) V
(11) V
=V
=V
, Others=GND or V
SDA SCL BACK BACK
= GND to V
V
= GND or V
SDA
CC, CLK CC
(12) I = 3.0mA at 5V, 1.5mA at 2.7V
OL
(13) I
= -1.0mA at 5V, -0.4mA at 2.7V
OH
(14) Threshold voltages based on the higher of Vcc or Vback.
(15) Driven by external 32.748Hz square wave oscillator on X1, X2 open.
(16) Using recommended crystal and oscillator network applied to X1 and X2 (25°C). Periodically sampled and not 100% tested.
Capacitance T = 25°C, f = 1.0 MHz, V
= 5V
A
CC
Symbol
Parameter
Output Capacitance (SDA, IRQ)
Input Capacitance (SCL)
Max.
Units
pF
Test Conditions
= 0V
(1)
OUT
C
8
6
V
OUT
(1)
IN
C
pF
V
= 0V
IN
Notes: (1) This parameter is periodically sampled and not 100% tested.
AC CHARACTERISTICS
AC Test Conditions
Figure 19. Standard Output Load for testing the
device with V = 5.0V
CC
Equivalent AC Output Load Circuit for V
= 5V
CC
Input Pulse Levels
V
x 0.1 to V x 0.9
CC
CC
Input Rise and Fall Times
10ns
5.0V
Input and Output Timing
Levels
V
x 0.5
CC
For V = 0.4V
OL
Output Load
Standard Output Load
1533Ω
and I = 3 mA
OL
SDA
100pF
Characteristics subject to change without notice. 18 of 26
X1287
AC Specifications T = -55°C to +125°C, V
= +2.7V to +5.5V, unless otherwise specified.
A
CC
400kHz Option
Symbol
Parameter
Min.
Max. Units
f
SCL Clock Frequency
0
400
0.9
KHz
nS
µS
µS
µS
µS
µS
µS
nS
µS
µS
nS
nS
nS
nS
nS
pF
SCL
t
Pulse width Suppression Time at inputs
SCL LOW to SDA Data Out Valid
Time the bus must be free before a new transmission can start
Clock LOW Time
50
IN
t
0.1
AA
t
1.3
BUF
t
1.3
LOW
t
Clock HIGH Time
0.6
HIGH
t
Start Condition Setup Time
Start Condition Hold Time
0.6
SU:STA
HD:STA
SU:DAT
HD:DAT
SU:STO
t
t
0.6
Data In Setup Time
100
t
t
Data In Hold Time
0
Stop Condition Setup Time
Data Output Hold Time
0.6
t
50
20 +.1Cb(3)
20 +.1Cb(3)
0.6
DH
t
SDA and SCL Rise Time
300
300
R
t
SDA and SCL Fall Time
F
t
S0, S1, S2, and WP Setup Time
S0, S1, S2, and WP Hold Time
Capacitive load for each bus line
SU:S0,S1,S2,WP
t
0
HD:S0,S1,S2,WP
Cb
400
Notes: (1) Typical values are for T = 25°C and V = 5.0V
A
CC
(2) This parameter is periodically sampled and not 100% tested.
(3) Cb = total capacitance of one bus line in pF.
TIMING DIAGRAMS
Bus Timing
t
t
t
t
R
F
HIGH
LOW
SCL
t
SU:DAT
t
t
t
SU:STO
SU:STA
HD:DAT
t
HD:STA
SDA IN
t
t
t
BUF
AA
DH
SDA OUT
Characteristics subject to change without notice. 19 of 26
X1287
S0,S1, S2, and WP Pin Timing
START
SCL
Clk 1
Clk 9
Slave Address Byte
SDA IN
t
t
HD:S0,S1,S2,WP
SU:S0,S1,S2,WP
S0, S1, S2, and WP
Write Cycle Timing
SCL
8th Bit of Last Byte
ACK
SDA
t
WC
Stop
Start
Condition
Condition
Power Up Timing
Symbol
Parameter
Min.
Typ.(2)
Max.
Units
mS
(1)
PUR
t
Time from Power Up to Read
Time from Power Up to Write
1
5
(1)
PUW
t
mS
Notes: (1) Delays are measured from the time V
is stable until the specified operation can be initiated. These parameters are periodically
CC
sampled and not 100% tested.
(2) Typical values are for T = 25°C and V = 5.0V
A
CC
Nonvolatile Write Cycle Timing
Symbol
Parameter
Min.
Typ.(1)
Max.
Units
(1)
WC
t
Write Cycle Time
5
10
mS
Notes: (1)
t
is the time from a valid stop condition at the end of a write sequence to the end of the self-timed internal nonvolatile write
WC
cycle. It is the minimum cycle time to be allowed for any nonvolatile write by the user, unless Acknowledge Polling is used.
Characteristics subject to change without notice. 20 of 26
X1287
WATCHDOG TIMER/LOW VOLTAGE RESET OPERATING CHARACTERISTICS
Watchdog/Low Voltage Reset Parameters
Symbols
Parameters
Min.
Typ.
Max.
Unit
Programmed Reset Trip Voltage
X1287-4.5A
X1287
X1287-2.7A
X1287-2.7
4.5
4.25
2.7
4.68
4.38
2.93
2.68
4.75
4.5
3.0
2.7
V
V
PTRIP
2.55
t
V
Detect to RST LOW (RST HIGH)
500
ns
RPD
CC
Power Up Reset Time-out Delay
(t Option 1) - Default
t
100
200
400
ms
PURST1
PURST
t
V
V
Fall Time
10
10
µs
µs
F
CC
t
Rise Time
R
CC
Watchdog Timer Period:
WD1=0, WD0=0
WD1=0, WD0=1
1.7
725
225
1.75
750
250
1.8
775
275
ms
ms
ms
t
WDO
WD1=1, WD0=0
Watchdog Reset Timeout Delay
t
225
250
275
ms
RST1
(t
Option 1) - Default
RST
t
2-Wire interface
Reset Valid V
1
µs
V
RSP
V
1.0
RVALID
CC
V
Programming Timing Diagram
TRIP
V
CC
V
TRIP
(V
)
TRIP
t
t
THD
TSU
V
P
X1
t
t
t
VPH
VPS
VPO
SCL
SDA
t
RP
01h or 03h
00h
A0h
Characteristics subject to change without notice. 21 of 26
X1287
V
Programming Parameters
TRIP
Parameter
Description
Program Enable Voltage Setup time
Program Enable Voltage Hold time
Setup time
Min.
1
Max.
Units
µs
t
V
V
V
V
V
V
VPS
VPH
TRIP
TRIP
TRIP
TRIP
TRIP
TRIP
t
1
µs
t
1
µs
TSU
t
Hold (stable) time
10
ms
ms
THD
t
Write Cycle Time
10
WC
Program Enable Voltage Off time
(Between successive adjustments)
t
0
µs
VPO
V
Program Recovery Period
TRIP
t
10
ms
RP
(Between successive adjustments)
V
Programming Voltage
15
18
V
V
P
V
V
Programmed Voltage Range
1.7
5.0
TRAN
TRIP
Initial V
(Vcc applied - V
Program Voltage accuracy
TRIP
V
-0.1
-25
-25
-25
+0.4
+25
+25
+25
V
ta1
ta2
) (Programmed at 25°C.)
TRIP
Subsequent V
[(Vcc applied - V ) - V
Program Voltage accuracy
TRIP
V
mV
mV
mV
. Programmed at 25°C.)
ta1
TRIP
V
Program Voltage repeatability
TRIP
V
tr
(Successive program operations. Programmed at 25°C.)
V
Program variation after programming (0-75°C).
TRIP
V
tv
(Programmed at 25°C.)
V
Programming parameters are periodically sampled and are not 100% Tested.
TRIP
Characteristics subject to change without notice. 22 of 26
X1287
14-Lead Plastic, SOIC, Package Code S14
0.150 (3.80) 0.228 (5.80)
0.158 (4.00) 0.244 (6.20)
Pin 1 Index
Pin 1
0.014 (0.35)
0.020 (0.51)
0.336 (8.55)
0.345 (8.75)
(4X) 7°
0.053 (1.35)
0.069 (1.75)
0.004 (0.10)
0.010 (0.25)
0.050 (1.27)
0.050"Typical
0.010 (0.25)
0.020 (0.50)
X 45°
0.050"Typical
0° – 8°
0.250"
0.0075 (0.19)
0.010 (0.25)
0.016 (0.410)
0.037 (0.937)
0.030"Typical
14 Places
FOOTPRINT
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
Characteristics subject to change without notice. 23 of 26
X1287
14-Lead Plastic, TSSOP, Package Code V14
.025 (.65) BSC
.169 (4.3)
.177 (4.5)
.252 (6.4) BSC
.193 (4.9)
.200 (5.1)
.047 (1.20)
.0075 (.19)
.0118 (.30)
.002 (.05)
.006 (.15)
.010 (.25)
Gage Plane
0° - 8°
Seating Plane
.019 (.50)
.029 (.75)
Detail A (20X)
.031 (.80)
.041 (1.05)
See Detail “A”
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
Characteristics subject to change without notice. 24 of 26
X1287
ORDERING INFORMATION
Operating
Temperature Range
Part Number
256Kb EEPROM RESET (LOW)
V
Range
V
Range
Package
14L SOIC
CC
TRIP
0–70°C
-40–85°C
0–70°C
0–70°C
-40–85°C
0–70°C
0–70°C
-40–85°C
0–70°C
0–70°C
-40–85°C
0–70°C
X1287S14-4.5A
X1287S14I-4.5A
X1287V14-4.5A
X1287S14
4.5-5.5V
4.5-5.5V
2.7-5.5V
2.7-5.5V
4.5.4.75
14L TSSOP
14L SOIC
4.25.4.5
2.85-3.0
2.55-2.7
X1287S14I
14L TSSOP
14L SOIC
X1287V14
X1287S14-2.7A
X1287S14I-2.7A
X1287V14-2.7A
X1287S14-2.7
X1287S14I-2.7
X1287V14-2.7
14L TSSOP
14L SOIC
14L TSSOP
PART MARK INFORMATION
8-Lead TSSOP
8-Lead SOIC
Blank = 8-Lead SOIC
X1287 X
XX
EYWW
XXXXX
F = 2.7 to 5.5V, 0 to +70°C, V
G = 2.7 to 5.5V, -40 to +85°C, V
AN = 2.7 to 5.5V, 0 to +70°C, V
AP = 2.7 to 5.5V, -40 to +85°C, V
Blank = 4.5 to 5.5V, 0 to +70°C, V
I = 4.5 to 5.5V, -40 to +85°C, V
AL = 4.5 to 5.5V, 0 to +70°C, V
AM = 4.5 to 5.5V, -40 to +85°C, V
=2.55-2.7V
=2.55-2.7V
1287F = 2.7 to 5.5V, 0 to +70°C, V
1287G = 2.7 to 5.5V, -40 to +85°C, V
127AN = 2.7 to 5.5V, 0 to +70°C, V
127AP = 2.7 to 5.5V, -40 to +85°C, V
X1287 = 4.5 to 5.5V, 0 to +70°C, V
1287I = 4.5 to 5.5V, -40 to +85°C, V
1287AL = 4.5 to 5.5V, 0 to +70°C, V
127AM = 4.5 to 5.5V, -40 to +85°C, V
=2.55-2.7V
TRIP
TRIP
=2.55-2.7V
=2.85-3.0V
=2.85-3.0V
TRIP
TRIP
TRIP
TRIP
TRIP
=2.85-3.0V
=2.85-3.0V
TRIP
TRIP
=4.25-4.5V
=4.25-4.5V
=4.25-4.5V
=4.5-4.75V
=4.5-4.75V
TRIP
TRIP
TRIP
=4.25-4.5V
=4.5-4.75V
TRIP
TRIP
=4.5-4.75V
TRIP
TRIP
Characteristics subject to change without notice. 25 of 26
X1287
LIMITED WARRANTY
©Xicor, Inc. 2001 Patents Pending
Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty,
express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement.
Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and prices
at any time and without notice.
Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, or licenses are implied.
COPYRIGHTS ANDTRADEMARKS
Xicor, Inc., the Xicor logo, E2POT, XDCP, XBGA, AUTOSTORE, Direct Write cell, Concurrent Read-Write, PASS, MPS, PushPOT, Block Lock, IdentiPROM,
E2KEY, X24C16, SecureFlash, and SerialFlash are all trademarks or registered trademarks of Xicor, Inc. All other brand and product names mentioned herein are
used for identification purposes only, and are trademarks or registered trademarks of their respective holders.
U.S. PATENTS
Xicor products are covered by one or more of the following U.S. Patents: 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846;
4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829,482; 4,874,967; 4,883,976; 4,980,859; 5,012,132; 5,003,197; 5,023,694; 5,084,667; 5,153,880; 5,153,691;
5,161,137; 5,219,774; 5,270,927; 5,324,676; 5,434,396; 5,544,103; 5,587,573; 5,835,409; 5,977,585. Foreign patents and additional patents pending.
LIFE RELATED POLICY
In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detection
and correction, redundancy and back-up features to prevent such an occurrence.
Xicor’s products are not authorized for use in critical components in life support devices or systems.
1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to
perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user.
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or effectiveness.
Characteristics subject to change without notice. 26 of 26
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