X28HC256JZ-12T13 [RENESAS]
EEPROM 5V;
| 型号： | X28HC256JZ-12T13 |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | EEPROM 5V 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 内存集成电路 |
| 文件： | 总19页 (文件大小：496K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATASHEET
256k, 32k x 8-Bit, 5V, Byte Alterable EEPROM
X28HC256
Features
The X28HC256 is a second generation high performance
CMOS 32k x 8 EEPROM. It is fabricated with Intersil’s
proprietary, textured poly floating gate technology, providing a
highly reliable 5V only nonvolatile memory.
• Access time: 90ns
• Simple byte and page write
- Single 5V supply
- No external high voltages or VP-P control circuits
- Self timed
The X28HC256 supports a 128-byte page write operation,
effectively providing a 24µs/byte write cycle, and enabling the
entire memory to be typically rewritten in less than 0.8s. The
X28HC256 also features DATA polling and Toggle bit polling,
two methods of providing early end of write detection. The
X28HC256 also supports the JEDEC standard software data
protection feature for protecting against inadvertent writes
during power-up and power-down.
- No erase before write
- No complex programming algorithms
- No overerase problem
• Low power CMOS
- Active: 60mA
- Standby: 500µA
Endurance for the X28HC256 is specified as a minimum
100,000 write cycles per byte and an inherent data retention
of 100 years.
• Software data protection
- Protects data against system level inadvertent writes
• High speed page write capability
• Highly reliable Direct Write™ cell
- Endurance: 100,000 cycles
- Data retention: 100 years
• Early end of write detection
- DATA polling
- Toggle bit polling
• RoHS compliant
256k BIT
EEPROM
ARRAY
X BUFFERS
LATCHES AND
DECODER
A
TO A
14
0
ADDRESS
INPUTS
I/O BUFFERS
AND LATCHES
Y BUFFERS
LATCHES AND
DECODER
I/O TO I/O
0
7
DATA INPUTS/OUTPUTS
CE
CONTROL
LOGIC AND
TIMING
OE
WE
V
V
CC
SS
FIGURE 1. BLOCK DIAGRAM
August 27, 2015
FN8108.5
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2005-2007, 2010, 2011, 2015. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
X28HC256
Ordering Information
PART NUMBER
ACCESS TIME
TEMP. RANGE
(°C)
(Note 4)
PART MARKING
(ns)
150
150
150
PACKAGE
32 Ld PLCC (RoHS Compliant)
32 Ld PLCC
PKG. DWG. #
N32.45x55
N32.45x55
N32.45x55
X28HC256JZ-15 (Notes 1, 3) X28HC256J-15 ZHY
0 to +70
-40 to +85
-40 to +85
X28HC256JI-15 (Note 1)
X28HC256JI-15 HY
X28HC256JI-15 ZHY
X28HC256JIZ-15
(Notes 1, 3)
32 Ld PLCC (RoHS Compliant)
X28HC256PZ-15
(Notes 2, 3)
X28HC256P-15 HYZ
X28HC256PI-15 HYZ
150
150
0 to +70
28 Ld PDIP (RoHS Compliant)
28 Ld PDIP (RoHS Compliant)
E28.6
E28.6
X28HC256PIZ-15
(Notes 2, 3)
-40 to +85
X28HC256JZ-12 (Notes 1, 3) X28HC256J-12 ZHY
120
120
120
0 to +70
-40 to +85
-40 to +85
32 Ld PLCC (RoHS Compliant)
32 Ld PLCC
N32.45x55
N32.45x55
N32.45x55
X28HC256JI-12 (Note 1)
X28HC256JI-12 HY
X28HC256JI-12 ZHY
X28HC256JIZ-12
(Notes 1, 3)
32 Ld PLCC (RoHS Compliant)
X28HC256PZ-12
(Notes 2, 3)
X28HC256P-12 HYZ
X28HC256PI-12 HYZ
120
120
0 to +70
28 Ld PDIP (RoHS Compliant)
28 Ld PDIP (RoHS Compliant)
E28.6
E28.6
X28HC256PIZ-12
(Notes 2, 3)
-40 to +85
X28HC256SZ-12 (Note 3)
X28HC256SI-12
X28HC256S-12 HYZ
X28HC256SI-12 HY
X28HC256SI-12 HYZ
120
120
120
90
0 to +70
-40 to +85
-40 to +85
0 to +70
28 Ld SOIC (300mils RoHS Compliant)
28 Ld SOIC (300mils)
MDP0027
M28.3
X28HC256SIZ-12 (Note 3)
28 Ld SOIC (300mils RoHS Compliant)
32 Ld PLCC (RoHS Compliant)
32 Ld PLCC
MDP0027
N32.45x55
N32.45x55
N32.45x55
X28HC256JZ-90 (Notes 1, 3) X28HC256J-90 ZHY
X28HC256JI-90 (Note 1)
X28HC256JI-90 HY
X28HC256JI-90 ZHY
90
-40 to +85
-40 to +85
X28HC256JIZ-90
(Notes 1, 3)
90
32 Ld PLCC (RoHS Compliant)
X28HC256PZ-90
(Notes 2, 3)
X28HC256P-90 HYZ
90
0 to +70
28 Ld PDIP (RoHS Compliant)
E28.6
X28HC256PIZ-90 (Notes 2, 3) X28HC256PI-90 HYZ
90
90
90
-40 to +85
-40 to +85
-40 to +85
28 Ld PDIP (RoHS Compliant)
28 Ld SOIC (300mils)
E28.6
X28HC256SI-90
X28HC256SIZ-90 (Note 3)
NOTES:
X28HC256SI-90 HY
X28HC256SI-90 HYZ
M28.3
28 Ld SOIC (300mils RoHS Compliant)
MDP0027
1. Add “T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
2. Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications.
3. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin
plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free
products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
4. For Moisture Sensitivity Level (MSL), please see product information page for X28HC256. For more information on MSL, please see tech brief TB363.
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X28HC256
Pin Configurations
X28HC256
(28 LD FLATPACK, PDIP, SOIC)
TOP VIEW
X28HC256
(32 LD PLCC, LCC)
TOP VIEW
A
A
1
28
V
CC
14
12
2
27
26
25
24
23
22
21
20
19
18
17
16
15
WE
4
3
2
1 32 31 30
29
3
A
A
A
A
A
A
A
A
A
13
7
6
5
4
3
2
1
0
A
A
5
6
7
8
9
A
4
A
8
6
5
8
28
27
26
25
24
23
22
21
A
A
5
A
9
9
A
A
6
A
11
4
3
11
NC
OE
7
OE
A
2
8
A
10
A
A
A
10
11
12
13
10
1
0
9
CE
I/O
CE
I/O
10
11
12
13
14
7
NC
I/O
7
I/O
I/O
I/O
I/O
I/O
I/O
0
1
2
6
5
4
3
I/O
0
6
14 15 16 17 18 19 20
I/O
V
SS
Pin Descriptions
PIN #
PIN #
PIN NAME
PDIP, SOIC
PLCC, LCC
DESCRIPTION
A0, A1, A2, A3, A4, A5,
A6, A7, A8, A9, A10, A11
10, 9, 8, 7, 6, 5,
4, 3, 25, 24, 21, 23,
2, 26, 1
11, 10, 9, 8, 7, 6,
5, 4, 29, 28, 24, 27,
3, 30, 2
Addresses (A0 to A14) - Address inputs. The address inputs select
an 8-bit memory location during a read or write operation.
,
A12, A13, A14
I/O0, I/O1, I/O2, I/O3,
I/O4, I/O5, I/O6, I/O7
11, 12, 13, 15
16, 17, 18, 19
13, 14, 15, 18
19, 20, 21, 22
Data In/Data Out (I/O0 to I/O7) - Data input/output- Data is
written to or read from the X28HC256 through the I/O pins.
WE
27
31
Write Enable (WE) - The Write enable input controls the writing of
data to the X28HC256.
CE
20
23
Chip Enable (CE) - The Chip enable input must be LOW to enable
all read/write operations. When CE is HIGH, power consumption is
reduced.
OE
22
25
Output Enable (OE) - The output enable input controls the data
output buffers, and is used to initiate read operations.
VCC
VSS
NC
28
14
-
32
16
+5V
Ground
No Connect
1, 12, 17, 26
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X28HC256
Absolute Maximum Ratings
Thermal Information
Voltage on any Pin with Respect to VSS . . . . . . . . . . . . . . . . . . . . . 1V to +7V
DC Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10mA
Temperature Under Bias
X28HC256. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-10°C to +85°C
X28HC256I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Pb-free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see TB493
*Pb-free PDIPs can be used for through hole wave solder processing only.
They are not intended for use in Reflow solder processing applications.
Recommended Operating Conditions
Temperature Range
Commercial. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C
Industrial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5V ± 10%
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
DC Electrical Specifications Across recommended operating conditions, unless otherwise specified.
LIMITS
MIN
TYP
MAX
PARAMETER
VCC Active Current
(TTL Inputs)
CC Standby Current
(TTL Inputs)
CC Standby Current
SYMBOL
ICC
TEST CONDITIONS
(Note 7) (Note 5)
(Note 7)
UNIT
mA
CE = OE = VIL, WE = VIH, All I/O’s = open,
address inputs = 0.4V/2.4V levels at f = 10MHz
30
60
2
V
ISB1
ISB2
CE = VIH, OE = VIL, All I/O’s = open, other inputs = VIH
1
mA
µA
V
CE = VCC - 0.3V, OE = GND, All I/Os = open, other
inputs = VCC - 0.3V
200
500
(CMOS Inputs)
Input Leakage Current
Output Leakage Current
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
NOTES:
ILI
ILO
VIN = VSS to VCC
10
10
µA
µA
V
VOUT = VSS to VCC, CE = VIH
VlL (Note 6)
VIH (Note 6)
VOL
-1
2
0.8
VCC + 1
0.4
V
IOL = 6mA
IOH = -4mA
V
VOH
2.4
V
5. Typical values are for TA = +25°C and nominal supply voltage.
6. VIL minimum and VIH maximum are for reference only and are not tested.
7. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
Power-up Timing
PARAMETER
SYMBOL
MAX
100
5
UNIT
µs
Power-up to Read
Power-up to Write
NOTE:
tPUR, (Note 8)
tPUW, (Note 8)
ms
8. This parameter is periodically sampled and not 100% tested.
Capacitance TA = +25°C, f = 1MHz, VCC = 5V.
SYMBOL
TEST
Input/output capacitance
Input capacitance
CONDITIONS
VI/O = 0V
VIN = 0V
MAX
10
6
UNIT
C
I/O (Note 8)
pF
pF
CIN (Note 8)
Endurance and Data Retention
PARAMETER
MIN
MAX
UNIT
Endurance
100,000
100
Cycles
Years
Data retention
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X28HC256
Symbol Table
AC Conditions of Test
Input pulse levels
0V to 3V
5ns
WAVEFORM
INPUTS
OUTPUTS
Input rise and fall times
Input and output timing levels
Must be
steady
Will be
steady
1.5V
May change
from LOW
to HIGH
Will change
from LOW
to HIGH
Mode Selection
CE
OE
WE
MODE
Read
Write
I/O
DOUT
DIN
POWER
active
May change
from HIGH
to LOW
Will change
from HIGH
to LOW
L
L
H
Don’t Care:
Changes
Allowed
Changing:
State Not
Known
L
H
L
active
H
X
X
Standby and write
inhibit
High Z
standby
N/A
Center Line
is High
Impedance
X
X
L
X
Write inhibit
Write inhibit
—
—
—
—
X
H
Equivalent AC Load Circuit
5V
1.92k
OUTPUT
1.37k
30pF
FIGURE 2. EQUIVALENT AC LOAD CIRCUIT
AC Electrical Specifications Across recommended operating conditions, unless otherwise specified.
X28HC256-70
X28HC256-90
X28HC256-12
X28HC256-15
PARAMETER
Read Cycle Time
SYMBOL
tRC
MIN
70
MAX
MIN
90
MAX
MIN
120
MAX
MIN
150
MAX
UNIT
ns
Chip Enable Access Time
Address Access Time
tCE
70
70
35
90
90
40
120
120
50
150
150
50
ns
tAA
ns
Output Enable Access Time
CE LOW to Active Output
OE LOW to Active Output
CE HIGH to High Z Output
OE HIGH to High Z Output
Output Hold from Address Change
NOTE:
tOE
ns
tLZ (Note 9)
tOLZ (Note 9)
tHZ (Note 9)
tOHZ (Note 9)
tOH
0
0
0
0
0
0
0
0
ns
ns
35
35
40
40
50
50
50
50
ns
ns
0
0
0
0
ns
9. tLZ minimum, tHZ, tOLZ minimum and tOHZ are periodically sampled and not 100% tested, tHZ and tOHZ are measured with CL = 5pF, from the point
when CE, OE return HIGH (whichever occurs first) to the time when the outputs are no longer driven..
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X28HC256
Read Cycle
t
RC
ADDRESS
t
CE
CE
t
OE
OE
V
IH
WE
t
t
OHZ
OLZ
t
t
t
t
HZ
LZ
OH
AA
HIGH Z
DATA VALID
DATA VALID
DATA I/O
FIGURE 3. READ CYCLE
Write Cycle Limits
TYP
PARAMETER
SYMBOL
MIN
(Note 10)
MAX
5
UNIT
Write Cycle Time
t
WC (Note 11)
3
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address Setup Time
Address Hold Time
Write Setup Time
tAS
tAH
0
50
0
tCS
Write Hold Time
tCH
0
CE Pulse Width
tCW
tOES
tOEH
tWP
50
0
OE HIGH Setup Time
OE HIGH Hold Time
WE Pulse Width
0
50
50
WE HIGH Recovery (page write only)
tWPH
(Note 12)
Data Valid
tDV
tDS
tDH
1
µs
ns
ns
µs
µs
Data Setup
50
0
Data Hold
Delay to Next Write After Polling is True
t
DW (Note 12)
10
Byte Load Cycle
NOTES:
tBLC
0.15
100
10. Typical values are for TA = +25°C and nominal supply voltage.
11. tWC is the minimum cycle time to be allowed from the system perspective unless polling techniques are used. It is the maximum time the device
requires to automatically complete the internal write operation.
12. tWPH and tDW are periodically sampled and not 100% tested.
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X28HC256
WE Controlled Write Cycle
t
WC
ADDRESS
t
t
AH
AS
t
t
CS
CH
CE
OE
t
t
OEH
OES
t
WP
WE
DATA IN
DATA OUT
DATA VALID
HIGH Z
t
t
DH
DS
FIGURE 4. WE CONTROLLED WRITE CYCLE
CE Controlled Write Cycle
t
WC
ADDRESS
t
t
AH
AS
t
CW
CE
OE
t
OES
t
OEH
t
t
CH
CS
WE
DATA VALID
DATA IN
t
t
DH
DS
HIGH Z
DATA OUT
FIGURE 5. CE CONTROLLED WRITE CYCLE
S
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X28HC256
Page Write Cycle
OE
(Note 13)
CE
t
t
BLC
WP
WE
t
WPH
ADDRESS
(Note 14, 15)
LAST BYTE
BYTE n + 2
I/O
BYTE 0
BYTE 1
BYTE 2
BYTE n
BYTE n + 1
t
WC
FIGURE 6. PAGE WRITE CYCLE
NOTES:
13. Between successive byte writes within a page write operation, OE can be strobed LOW: e.g. this can be done with CE and WE HIGH to fetch data
from another memory device within the system for the next write; or with WE HIGH and CE LOW effectively performing a polling operation.
14. The timings shown above are unique to page write operations. Individual byte load operations within the page write must conform to either the CE
or WE controlled write cycle timing.
15. For each successive write within the page write operation, A7 to A15 should be the same or writes to an unknown address could occur.
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X28HC256
DATA Polling Timing Diagram (Note 16)
ADDRESS
A
A
A
n
n
n
CE
WE
t
t
OEH
OES
OE
t
DW
D
= X
D
= X
D = X
OUT
I/O
7
IN
OUT
t
WC
FIGURE 6. DATA POLLING TIMING DIAGRAM
Toggle Bit Timing Diagram (Note 16)
CE
WE
t
OES
t
OEH
OE
t
DW
HIGH Z
(Note 17)
I/O
6
(Note 17)
t
WC
FIGURE 7. TOGGLE BIT TIMING DIAGRAM
NOTES:
16. Polling operations are by definition read cycles and are therefore subject to read cycle timings.
17. I/O6 beginning and ending state will vary, depending upon actual tWC
.
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X28HC256
DATA Polling (I/O )
Device Operation
7
The X28HC256 features DATA polling as a method to indicate to the
host system that the byte write or page write cycle has completed.
DATA polling allows a simple bit test operation to determine the
status of the X28HC256. This eliminates additional interrupt inputs
or external hardware. During the internal programming cycle, any
attempt to read the last byte written will produce the complement of
that data on I/O7 (i.e., write data = 0xxx xxxx, read data = 1xxx xxxx).
Once the programming cycle is complete, I/O7 will reflect true data.
Read
Read operations are initiated by both OE and CE LOW. The read
operation is terminated by either CE or OE returning HIGH. This
two line control architecture eliminates bus contention in a
system environment. The data bus will be in a high impedance
state when either OE or CE is HIGH.
Write
Toggle Bit (I/O )
6
Write operations are initiated when both CE and WE are LOW and
OE is HIGH. The X28HC256 supports both a CE and WE controlled
write cycle. That is, the address is latched by the falling edge of
either CE or WE, whichever occurs last. Similarly, the data is
latched internally by the rising edge of either CE or WE, whichever
occurs first. A byte write operation, once initiated, will
The X28HC256 also provides another method for determining
when the internal write cycle is complete. During the internal
programming cycle I/O6 will toggle from high-to-low and high-to-
low on subsequent attempts to read the device. When the
internal cycle is complete the toggling will cease and the device
will be accessible for additional read and write operations.
automatically continue to completion, typically within 3ms.
DATA Polling I/O
Page Write Operation
DATA polling can effectively halve the time for writing to the
X28HC256. The timing diagram in Figure 8 on page 11
illustrates the sequence of events on the bus. The software flow
diagram in Figure 9 on page 11 illustrates one method of
implementing the routine.
The page write feature of the X28HC256 allows the entire
memory to be written in typically 0.8 seconds. The page write
allows up to 128 bytes of data to be consecutively written to the
X28HC256, prior to the commencement of the internal
programming cycle. The host can fetch data from another device
within the system during a page write operation (change the
source address), but the page address (A7 through A14) for each
subsequent valid write cycle to the part during this operation
must be the same as the initial page address.
The Toggle Bit I/O
The toggle bit can eliminate the chore of saving and fetching the
last address and data in order to implement DATA polling. This
can be especially helpful in an array comprised of multiple
X28HC256 memories that is frequently updated. The timing
diagram in Figure 10 on page 12 illustrates the sequence of
events on the bus. The software flow diagram in Figure 11 on
page 12 illustrates a method for polling the toggle bit.
The page write mode can be initiated during any write operation.
Following the initial byte write cycle, the host can write an
additional one to 127 bytes in the same manner as the first byte
was written. Each successive byte load cycle, started by the WE
high-to-low transition, must begin within 100µs of the falling
edge of the preceding WE. If a subsequent WE high-to-low
transition is not detected within 100µs, the internal automatic
programming cycle will commence. There is no page write
window limitation. Effectively the page write window is infinitely
wide, so long as the host continues to access the device within
the byte load cycle time of 100µs.
Hardware Data Protection
The X28HC256 provides two hardware features that protects
nonvolatile data from inadvertent writes.
• Default VCC Sense — All write functions are inhibited when VCC
is 3.5V typically.
• Write Inhibit — Holding either OE low, WE high, or CE high will
prevent an inadvertent write cycle during power-up and
power-down, maintaining data integrity.
Write Operation Status Bits
The X28HC256 provides the user two write operation status bits.
These can be used to optimize a system write cycle time. The
status bits are mapped onto the I/O bus as shown in Figure 7.
I/O
DP
TB
5
4
3
2
1
0
RESERVED
TOGGLE BIT
DATA POLLING
FIGURE 7. STATUS BIT ASSIGNMENT
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X28HC256
LAST
WRITE
WE
CE
OE
V
IH
V
OH
HIGH Z
I/O
7
V
OL
X28HC256
READY
A
TO A
An
An
An
An
An
An
An
0
14
FIGURE 8. DATA POLLING BUS SEQUENCE
WRITE DATA
NO
WRITES
COMPLETE?
YES
SAVE LAST DATA
AND ADDRESS
READ LAST
ADDRESS
IO
7
NO
COMPARE?
YES
X28HC256
READY
FIGURE 9. DATA POLLING SOFTWARE FLOW
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X28HC256
LAST
WRITE
WE
CE
OE
V
HIGH Z
OH
I/O
6
V
OL
(Note 18)
(Note 18)
X28C512, X28C513
READY
NOTE:
18. I/O6 Beginning and ending state of I/O6 will vary.
FIGURE 10. TOGGLE BIT BUS SEQUENCE
¬
Software Data Protection
The X28HC256 offers a software controlled data protection
feature. The X28HC256 is shipped from Intersil with the software
data protection NOT ENABLED; that is, the device will be in the
standard operating mode. In this mode data should be protected
during power-up/down operations through the use of external
circuits. The host would then have open read and write access of
the device once VCC was stable.
LAST WRITE
YES
LOAD ACCUM
FROM ADDR n
The X28HC256 can be automatically protected during power-up
and power-down (without the need for external circuits) by
employing the software data protection feature. The internal
software data protection circuit is enabled after the first write
operation, utilizing the software algorithm. This circuit is
nonvolatile, and will remain set for the life of the device unless
the reset command is issued.
COMPARE
ACCUM WITH
ADDR n
Once the software protection is enabled, the X28HC256 is also
protected from inadvertent and accidental writes in the powered
up state. That is, the software algorithm must be issued prior to
writing additional data to the device.
NO
COMPARE
OK?
YES
Software Algorithm
X28C256
READY
Selecting the software data protection mode requires the host
system to precede data write operations by a series of three
write operations to three specific addresses. Refer to
Figures 12 and 13 on page 13 for the sequence. The 3 byte
sequence opens the page write window, enabling the host to
write from one to 128 bytes of data. Once the page load cycle
has been completed, the device will automatically be returned
to the data protected state.
FIGURE 11. TOGGLE BIT SOFTWARE FLOW
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X28HC256
Software Data Protection
V
CC
(V
)
CC
0V
DATA
ADDRESS
AA
5555
55
2AAA
A0
5555
WRITES
OK
WRITE
PROTECTED
t
WC
CE
£t
BYTE
OR
BLC MAX
WE
AGE
FIGURE 12. TIMING SEQUENCE BYTE OR PAGE WRITE
Regardless of whether the device has previously been protected
or not, once the software data protection algorithm is used and
data has been written, the X28HC256 will automatically disable
further writes unless another command is issued to cancel it. If
no further commands are issued the X28HC256 will be write
protected during power-down and after any subsequent
power-up.
WRITE DATA AA
TO ADDRESS
5555
WRITE DATA 55
TO ADDRESS
2AAA
Note: Once initiated, the sequence of write operations should not
be interrupted.
Resetting Software Data
Protection
WRITE DATA A0
TO ADDRESS
5555
In the event the user wants to deactivate the software data
protection feature for testing or reprogramming in an EEPROM
programmer, the following six step algorithm will reset the
internal protection circuit. After tWC, the X28HC256 will be in
standard operating mode.
BYTE/PAGE
LOAD ENABLED
WRITE DATA XX
TO ANY
ADDRESS
OPTIONAL
BYTE/PAGE
Note: Once initiated, the sequence of write operations should not
be interrupted.
LOAD OPERATION
WRITE LAST
BYTE TO
LAST ADDRESS
AFTER t
WC
RE-ENTERS DATA
PROTECTED STATE
FIGURE 13. WRITE SEQUENCE FOR SOFTWARE DATA
PROTECTION
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X28HC256
V
CC
AA
5555
55
2AAA
80
5555
AA
5555
55
2AAA
20
5555
STANDARD
OPERATING
MODE
DATA
ADDRESS
t
WC
CE
WE
FIGURE 14. RESET SOFTWARE DATA PROTECTION TIMING SEQUENCE
System Considerations
WRITE DATA AA
TO ADDRESS
5555
Because the X28HC256 is frequently used in large memory
arrays, it is provided with a two line control architecture for both
read and write operations. Proper usage can provide the lowest
possible power dissipation and eliminate the possibility of
contention where multiple I/O pins share the same bus.
WRITE DATA 55
TO ADDRESS
2AAA
To gain the most benefit, it is recommended that CE be decoded
from the address bus and be used as the primary device
selection input. Both OE and WE would then be common among
all devices in the array. For a read operation, this assures that all
deselected devices are in their standby mode and that only the
selected device(s) is/are outputting data on the bus.
WRITE DATA 80
TO ADDRESS
5555
Because the X28HC256 has two power modes, standby and
active, proper decoupling of the memory array is of prime
concern. Enabling CE will cause transient current spikes. The
magnitude of these spikes is dependent on the output capacitive
loading of the l/Os. Therefore, the larger the array sharing a
common bus, the larger the transient spikes. The voltage peaks
associated with the current transients can be suppressed by the
proper selection and placement of decoupling capacitors. As a
minimum, it is recommended that a 0.1µF high frequency
ceramic capacitor be used between VCC and VSS at each device.
Depending on the size of the array, the value of the capacitor
may have to be larger.
WRITE DATA AA
TO ADDRESS
5555
WRITE DATA 55
TO ADDRESS
2AAA
WRITE DATA 20
TO ADDRESS
5555
In addition, it is recommended that a 4.7µF electrolytic bulk
capacitor be placed between VCC and VSS for each eight devices
employed in the array. This bulk capacitor is employed to
overcome the voltage droop caused by the inductive effects of
the PC board traces.
AFTER t
,
WC
RE-ENTERS
UNPROTECTED
STATE
FIGURE 15. WRITE SEQUENCE FOR RESETTING SOFTWARE DATA
PROTECTION
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X28HC256
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web to make sure that
you have the latest revision.
DATE
REVISION
FN8108.5
CHANGE
August 27, 2015
Removed the reference to Military part under “Recommended Operating Conditions” and “Thermal Information”
Removed X28HC256J-15, X28HC256SI-15, X28HC256SIZ-15, X28HC256J-12, X28HC256S-12, and
X28HC256S-90 from the Ordering Information table on page 2.
Updated Pin Description table on page 3.
March 31, 2015
FN8108.4
-Updated entire datasheet to Intersil new standard.
-Added revision history and about Intersil verbiage.
-Third paragraph on page 1 updated From:
Endurance for the X28HC256 is specified as a minimum 1,000,000 write cycles per byte and an inherent data
retention of 100 years.
To:
Endurance for the X28HC256 is specified as a minimum 100,000 write cycles per byte and an inherent data
retention of 100 years.
-Features section on page 1 updated From:
Highly reliable Direct Write™ cell
- Endurance: 1,000,000 cycles
To:
Highly reliable Direct Write™ cell
- Endurance: 100,000 cycles
“Endurance and Data Retention” on page 4 updated Endurance from 1,000,000 to 100,000.
-Ordering information table on page 2: Removed obsolete part numbers X28HC256P-15, X28HC256PI-15,
X28HC256P-12, X28HC256PI-12, X28HC256P-90.
-Ordering information table on page 2 updated the “Access time’ section.
Thermal Information table on page 4 updated “Temperature Under Bias” section for X28HC256 value from 10°C
to +85°C to -10°C to +85°C.
“DC Electrical Specifications” on page 4, added a note to Min and Max values.
Removed note in Electrical Spec Table that referenced an obsolete part.
About Intersil
Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products
address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets.
For the most updated datasheet, application notes, related documentation and related parts, please see the respective product
information page found at www.intersil.com.
You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask.
Reliability reports are also available from our website at www.intersil.com/support
FN8108.5
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15
X28HC256
Small Outline Plastic Packages (SOIC)
M28.3 (JEDEC MS-013-AE ISSUE C)
28 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE
N
INDEX
0.25(0.010)
M
B M
H
AREA
INCHES MILLIMETERS
E
SYMBOL
MIN
MAX
MIN
2.35
0.10
0.33
0.23
MAX
2.65
NOTES
-B-
A
A1
B
C
D
E
e
0.0926
0.0040
0.013
0.1043
0.0118
0.0200
0.0125
-
0.30
-
1
2
3
L
0.51
9
SEATING PLANE
A
0.0091
0.6969
0.2914
0.32
-
0.7125 17.70
18.10
7.60
3
-A-
h x 45o
D
0.2992
7.40
4
0.05 BSC
1.27 BSC
-
-C-
a
H
h
0.394
0.01
0.419
0.029
0.050
10.00
0.25
0.40
10.65
0.75
1.27
-
e
A1
C
5
B
0.10(0.004)
L
0.016
6
0.25(0.010) M
C
A M B S
N
28
28
7
0o
8o
0o
8o
-
Rev. 1, 1/13
NOTES:
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
TYPICAL RECOMMENDED LAND PATTERN
4. Dimension “E” does not include interlead flash or protrusions. Interlead
flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.
(1.50mm)
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
(9.38mm)
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above
the seating plane, shall not exceed a maximum value of 0.61mm
(0.024 inch)
(1.27mm TYP)
(0.51mm TYP)
10. Controlling dimension: MILLIMETER. Converted inch dimensions are
not necessarily exact.
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X28HC256
Plastic Leaded Chip Carrier Packages (PLCC)
0.042 (1.07)
0.056 (1.42)
PIN (1)
IDENTIFIER
0.004 (0.10)
C
0.042 (1.07)
0.048 (1.22)
N32.45x55 (JEDEC MS-016AE ISSUE A)
0.050 (1.27) TP
ND
32 LEAD PLASTIC LEADED CHIP CARRIER PACKAGE
INCHES MILLIMETERS
0.025 (0.64)
0.045 (1.14)
R
C
L
SYMBOL
MIN
MAX
MIN
3.18
MAX
3.55
NOTES
A
A1
D
0.125
0.060
0.485
0.447
0.188
0.585
0.547
0.238
0.140
0.095
0.495
0.453
0.223
0.595
0.553
0.273
-
D2/E2
D2/E2
1.53
2.41
-
12.32
11.36
4.78
12.57
11.50
5.66
-
C
L
D1
D2
E
3
E1
E
4, 5
NE
14.86
13.90
6.05
15.11
14.04
6.93
-
VIEW “A”
E1
E2
N
3
4, 5
0.015 (0.38)
MIN
28
7
28
7
6
A1
D1
D
ND
NE
7
7
A
9
9
SEATING
PLANE
0.020 (0.51) MAX
3 PLCS
-C-
Rev. 0 7/98
0.026 (0.66)
0.032 (0.81)
NOTES:
0.050 (1.27)
MIN
1. Controlling dimension: INCH. Converted millimeter dimen-
sions are not necessarily exact.
2. Dimensions and tolerancing per ANSI Y14.5M-1982.
3. Dimensions D1 and E1 do not include mold protrusions. Al-
lowable mold protrusion is 0.010 inch (0.25mm) per side.
Dimensions D1 and E1 include mold mismatch and are mea-
sured at the extreme material condition at the body parting
line.
0.013 (0.33)
0.021 (0.53)
0.025 (0.64)
MIN
(0.12)
0.005
M
A S - B S D S
-C-
4. To be measured at seating plane
contact point.
VIEW “A” TYP.
5. Centerline to be determined where center leads exit plastic
body.
6. “N” is the number of terminal positions.
7. ND denotes the number of leads on the two shorts sides of the
package, one of which contains pin #1. NE denotes the num-
ber of leads on the two long sides of the package.
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X28HC256
Small Outline Package Family (SO)
A
D
h X 45°
(N/2)+1
N
A
PIN #1
I.D. MARK
E1
E
c
SEE DETAIL “X”
1
(N/2)
B
L1
0.010 M
C A B
e
H
C
A2
A1
GAUGE
PLANE
SEATING
PLANE
0.010
L
4° ±4°
0.004 C
b
0.010 M
C
A
B
DETAIL X
MDP0027
SMALL OUTLINE PACKAGE FAMILY (SO)
INCHES
SO16
(0.150”)
SO16 (0.300”)
(SOL-16)
SO20
(SOL-20)
SO24
(SOL-24)
SO28
(SOL-28)
SYMBOL
SO-8
0.068
0.006
0.057
0.017
0.009
0.193
0.236
0.154
0.050
0.025
0.041
0.013
8
SO-14
0.068
0.006
0.057
0.017
0.009
0.341
0.236
0.154
0.050
0.025
0.041
0.013
14
TOLERANCE
MAX
NOTES
A
A1
A2
b
0.068
0.006
0.057
0.017
0.009
0.390
0.236
0.154
0.050
0.025
0.041
0.013
16
0.104
0.007
0.092
0.017
0.011
0.406
0.406
0.295
0.050
0.030
0.056
0.020
16
0.104
0.007
0.092
0.017
0.011
0.504
0.406
0.295
0.050
0.030
0.056
0.020
20
0.104
0.007
0.092
0.017
0.011
0.606
0.406
0.295
0.050
0.030
0.056
0.020
24
0.104
0.007
0.092
0.017
0.011
0.704
0.406
0.295
0.050
0.030
0.056
0.020
28
-
0.003
0.002
0.003
0.001
0.004
0.008
0.004
Basic
-
-
-
c
-
D
1, 3
E
-
E1
e
2, 3
-
L
0.009
Basic
-
L1
h
-
Reference
Reference
-
N
-
Rev. M 2/07
NOTES:
1. Plastic or metal protrusions of 0.006” maximum per side are not included.
2. Plastic interlead protrusions of 0.010” maximum per side are not included.
3. Dimensions “D” and “E1” are measured at Datum Plane “H”.
4. Dimensioning and tolerancing per ASME Y14.5M-1994
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X28HC256
Dual-In-Line Plastic Packages (PDIP)
E28.6 (JEDEC MS-011-AB ISSUE B)
N
28 LEAD DUAL-IN-LINE PLASTIC PACKAGE
INCHES MILLIMETERS
E1
INDEX
AREA
1 2
3
N/2
SYMBOL
MIN
MAX
0.250
-
MIN
-
MAX
6.35
-
NOTES
-B-
-C-
A
A1
A2
B
-
4
-A-
D
E
0.015
0.125
0.014
0.030
0.008
1.380
0.005
0.600
0.485
0.39
3.18
0.356
0.77
0.204
4
BASE
PLANE
0.195
0.022
0.070
0.015
1.565
-
4.95
0.558
1.77
0.381
39.7
-
-
A2
A
-
SEATING
PLANE
L
C
L
B1
C
8
D1
B1
eA
-
A1
A
D1
e
D
35.1
5
eC
C
B
eB
D1
E
0.13
15.24
12.32
5
0.010 (0.25) M
C
B S
0.625
0.580
15.87
14.73
6
NOTES:
E1
e
5
1. Controlling Dimensions: INCH. In case of conflict between English and
Metric dimensions, the inch dimensions control.
0.100 BSC
0.600 BSC
2.54 BSC
15.24 BSC
-
eA
eB
L
6
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication No. 95.
-
0.700
0.200
-
17.78
5.08
7
0.115
2.93
4
9
4. Dimensions A, A1 and L are measured with the package seated in
N
28
28
JEDEC seating plane gauge GS-3.
Rev. 1 12/00
5. D, D1, and E1 dimensions do not include mold flash or protrusions.
Mold flash or protrusions shall not exceed 0.010 inch (0.25mm).
eA
6. E and
ular to datum
7. eB and eC are measured at the lead tips with the leads unconstrained.
C must be zero or greater.
are measured with the leads constrained to be perpendic-
-C-
.
e
8. B1 maximum dimensions do not include dambar protrusions. Dambar
protrusions shall not exceed 0.010 inch (0.25mm).
9. N is the maximum number of terminal positions.
10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3,
E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm).
For additional products, see www.intersil.com/en/products.html
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
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