X40014S8-BT1 [RENESAS]
2-CHANNEL POWER SUPPLY MANAGEMENT CKT, PDSO8, PLASTIC, SOIC-8;
| 型号： | X40014S8-BT1 |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | 2-CHANNEL POWER SUPPLY MANAGEMENT CKT, PDSO8, PLASTIC, SOIC-8 光电二极管 |
| 文件： | 总24页 (文件大小：922K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATASHEET
X40010, X40011, X40014, X40015
Dual Voltage Monitor with Integrated CPU Supervisor
FN8111
Rev 0.00
March 28, 2005
FEATURES
APPLICATIONS
• Dual voltage detection and reset assertion
—Standard reset threshold settings
See Selection table on page 2.
—Adjust low voltage reset threshold voltages
using special programming sequence
• Communication Equipment
—Routers, Hubs, Switches
—Disk Arrays, Network Storage
• Industrial Systems
—Process Control
—Reset signal valid to V = 1V
—Intelligent Instrumentation
• Computer Systems
—Computers
CC
—Monitor three voltages or detect power fail
• Independent Core Voltage Monitor (V2MON)
• Fault detection register
—Network Servers
• Selectable power on reset timeout (0.05s,
0.2s, 0.4s, 0.8s)
DESCRIPTION
• Selectable watchdog timer interval (25ms,
200ms,1.4s, off)
• Low power CMOS
—25µA typical standby current, watchdog on
—6µA typical standby current, watchdog off
• 400kHz 2-wire interface
The X40010/11/14/15 combines power-on reset con-
trol, watchdog timer, supply voltage supervision, and
secondary voltage supervision, in one package. This
combination lowers system cost, reduces board space
requirements, and increases reliability.
• 2.7V to 5.5V power supply operation
• Available packages
—8-lead SOIC, TSSOP
• Monitor Voltages: 5V to 0.9V
• Independent Core Voltage Monitor
Applying voltage to V
activates the power on reset
CC
circuit which holds RESET/RESET active for a period of
time. This allows the power supply and system oscilla-
tor to stabilize before the processor can execute code.
BLOCK DIAGRAM
Watchdog Timer
and
Reset Logic
Fault Detection
Register
Data
WDO
Register
SDA
Status
Register
Command
Decode Test
& Control
SCL
Logic
RESET
Threshold
Reset Logic
X40010/14
Power on,
Low Voltage
Reset
RESET
X40011/15
VCC
(V1MON)
+
Generation
User Programmable
VTRIP1
-
V2MON
VCC
+
V2FAIL
V2MON
User Programmable
VTRIP2
-
*X40010/11 = V2MON*
X40014/15 = VCC
FN8111 Rev 0.00
March 28, 2005
Page 1 of 24
X40010, X40011, X40014, X40015
Low V detection circuitry protects the user’s system
from low voltage conditions, resetting the system when
The Watchdog Timer provides an independent protec-
tion mechanism for microcontrollers. When the micro-
controller fails to restart a timer within a selectable time
out interval, the device activates the WDO signal. The
user selects the interval from three preset values. Once
selected, the interval does not change, even after
cycling the power.
CC
V
falls below the minimum
V
point.
CC
TRIP1
RESET/RESET is active until V returns to proper
CC
operating level and stabilizes. A second voltage monitor
circuit tracks the unregulated supply to provide a power
fail warning or monitors different power supply voltage.
Three common low voltage combinations are available,
however, Intersil’s unique circuits allows the threshold
for either voltage monitor to be reprogrammed to meet
special needs or to fine-tune the threshold for applica-
tions requiring higher precision.
The device features a 2-wire interface and software pro-
2
®
tocol allowing operation on an I C bus.
Dual Voltage Monitors
Table 1:
Device
Expected System Voltages
Vtrip1(V)
Vtrip2(V)
POR (system)
X40010/11
2.0–4.75*
4.55–4.65*
4.35–4.45*
2.85–2.95*
1.70–4.75
2.85–2.95
2.55–2.65
1.65–1.75
-A
-B
-C
5V; 3V or 3.3V
5V; 3V
3V; 3.3V; 1.8V
RESET = X40010
RESET = X40011
X40014/15
2.0–4.75*
2.85–2.95*
2.55–2.65*
2.85–2.95*
0.90–3.50*
1.25–1.35*
1.25–1.35*
0.95–1.05*
-A
-B
-C
3V; 3.3V; 1.5V
3V; 1.5V
3V or 3.3V; 1.1 or 1.2V
RESET = X40014
RESET = X40015
*Voltage monitor requires VCC to operation. Others are independent of VCC
.
PIN CONFIGURATION
X40010/14, X40011/15
8-Pin TSSOP
X40010/14, X40011/15
8-Pin SOIC
SCL
SDA
VSS
WDO
VCC
V2FAIL
V2MON
VCC
V2FAIL
V2MON
1
2
3
4
8
7
6
5
1
2
3
4
8
7
6
5
WDO
SCL
SDA
RESET/RESET
VSS
RESET/RESET
PIN DESCRIPTION
Pin
SOIC TSSOP Name
Function
1
3
V2FAIL V2 Voltage Fail Output. This open drain output goes LOW when V2MON is less than VTRIP2 and
goes HIGH when V2MON exceeds VTRIP2. There is no power up reset delay circuitry on this pin.
2
4
V2MON V2 Voltage Monitor Input. When the V2MON input is less than the VTRIP2 voltage, V2FAIL goes
LOW. This input can monitor an unregulated power supply with an external resistor divider or can
monitor a second power supply with no external components. Connect V2MON to VSS or V when
CC
not used.The V2MON comparator is supplied by V2MON (X40010/11) or by VCC Input (X40014/15).
3
5
RESET/ RESET Output. (X40011/15) This is an active LOW, open drain output which goes active whenever
VCC falls below VTRIP1. It will remain active until VCC rises above VTRIP1 and for the tPURST thereafter.
RESET
RESET Output. (X40010/14) This is an active HIGH CMOS output which goes active whenever VCC
falls below VTRIP1. It will remain active until V rises above VTRIP1 and for the tPURST thereafter.
CC
4
5
6
7
VSS
Ground
SDA Serial Data. SDA is a bidirectional pin used to transfer data into and out of the device. It has an open
drain output and may be wire ORed with other open drain or open collector outputs. This pin requires
a pull up resistor and the input buffer is always active (not gated).
Watchdog Input. A HIGH to LOW transition on the SDA (while SCL is toggled from HIGH to
LOW and followed by a stop condition) restarts the Watchdog timer. The absence of this transi-
tion within the watchdog time out period results in WDO going active.
FN8111 Rev 0.00
March 28, 2005
Page 2 of 24
X40010, X40011, X40014, X40015
PIN DESCRIPTION (Continued)
Pin
SOIC TSSOP Name
Function
Serial Clock. The Serial Clock controls the serial bus timing for data input and output.
6
7
8
1
SCL
WDO WDO Output. WDO is an active LOW, open drain output which goes active whenever the watch-
dog timer goes active.
8
2
VCC
Supply Voltage
PRINCIPLES OF OPERATION
Power On Reset
For the X40014/15 devices, the V2FAIL signal remains
actice until V drops below 1Vx and remains active until
CC
V2MON returns and exceeds V
. This sense circuitry
TRIP2
is powered by V . If V = 0, V2MON cannot be moni-
tored.
CC
CC
Application of power to the X40010/11/14/15 activates a
Power On Reset Circuit that pulls the RESET/RESET pins
active. This signal provides several benefits.
Figure 1. Two Uses of Multiple Voltage Monitoring
– It prevents the system microprocessor from starting to
operate with insufficient voltage.
– It prevents the processor from operating prior to stabiliza-
tion of the oscillator.
– It allows time for an FPGA to download its configuration
prior to initialization of the circuit.
VCC V2MON
X40011-A
5V
VCC
6–10V
System
Reset
Reg
RESET
1M
V2MON
(2.9V)
V2FAIL
– It prevents communication to the EEPROM, greatly
reducing the likelihood of data corruption on power up.
1M
When V exceeds the device V
threshold value for
CC
TRIP1
t
(selectable) the circuit releases the RESET
PURST
Resistors selected so 3V appears on V2MON when unregulated
supply reaches 6V.
(X40011) and RESET (X40010) pin allowing the system to
begin operation.
VCC
Low Voltage V (V1 Monitoring)
CC
X40014-C
During operation, the X40010/11/14/15 monitors the V
CC
Unreg.
Supply
3.3V
Reg
VCC
level and asserts RESET/RESET if supply voltage falls
below a preset minimum V . The RESET/RESET sig-
TRIP1
System
Reset
RESET
V2FAIL
nal prevents the microprocessor from operating in a
power fail or brownout condition. The V1FAIL signal
remains active until the voltage drops below 1V. It also
1.2V
Reg
V2MON
remains active until V
returns and exceeds V
for
CC
TRIP1
tPURST
.
Notice: No external components required to monitor two voltages.
Low Voltage V2 Monitoring
The X40010/11/14/15 also monitors a second voltage level
and asserts V2FAIL if the voltage falls below a preset
minimum V
. The V2FAIL signal is either ORed with
TRIP2
RESET to prevent the microprocessor from operating in a
power fail or brownout condition or used to interrupt the
microprocessor with notification of an impending power
failure. For the X40010/11 the V2FAIL signal remains
active until the V
drops below 1V (V
falling). It also
CC
CC
remains active until V2MON returns and exceeds V
TRIP2
by 0.2V. This voltage sense circuitry monitors the power
supply connected to the V2MON pin. If V = 0, V2MON
CC
can still be monitored.
FN8111 Rev 0.00
March 28, 2005
Page 3 of 24
X40010, X40011, X40014, X40015
Figure 2. V
Set/Reset Conditions
TRIPX
VTRIPX
(X = 1, 2)
VCC/V2MON
VP
WDO
SCL
7
0
0
7
0
7
SDA
tWC
A0h
00h
WATCHDOG TIMER
Setting a V
Voltage (x = 1, 2)
TRIPx
There are two procedures used to set the threshold volt-
ages (V ), depending if the threshold voltage to be
The Watchdog Timer circuit monitors the microprocessor
activity by monitoring the SDA and SCL pins. The micro-
processor must toggle the SDA pin HIGH to LOW periodi-
cally, while SCL also toggles from HIGH to LOW (this is a
start bit) followed by a stop condition prior to the expiration
of the watchdog time out period to prevent a WDO signal
going active. The state of two nonvolatile control bits in the
Status Register determines the watchdog timer period. The
microprocessor can change these watchdog bits by writing
to the X40010/11/14/15 control register (also refer to page
19).
TRIPx
stored is higher or lower than the present value. For
example, if the present V is 2.9 V and the new
TRIPx
V
is 3.2 V, the new voltage can be stored directly into
TRIPx
the V
cell. If however, the new setting is to be lower
TRIPx
than the present setting, then it is necessary to “reset” the
voltage before setting the new value.
V
TRIPx
Setting a Higher V
Voltage (x = 1, 2)
TRIPx
To set a V
threshold to a new voltage which is
TRIPx
higher than the present threshold, the user must apply
the desired V threshold voltage to the corre-
Figure 3. Watchdog Restart
TRIPx
sponding input pin Vcc(V1MON), or V2MON. The
Vcc(V1MON) and V2MON must be tied together during
this sequence. Then, a programming voltage (Vp) must
be applied to the WDO pin before a START condition is
set up on SDA. Next, issue on the SDA pin the Slave
Address A0h, followed by the Byte Address 01h for
.6µs
1.3µs
SCL
SDA
V
and 09h for V
, and a 00h Data Byte in order
TRIP1
TRIP2
Timer Start
to program V
. The STOP bit following a valid write
TRIPx
operation initiates the programming sequence. Pin WDO
must then be brought LOW to complete the operation.
V1 AND V2 THRESHOLD PROGRAM PROCEDURE
(OPTIONAL)
Note: This operation does not corrupt the memory array.
The X40010/11/14/15is shipped with standard V1 and
Setting a Lower V
Voltage (x = 1, 2)
V2 threshold (V
V
) voltages. These values will
TRIPx
TRIP1, TRIP2
not change over normal operating and storage condi-
tions. However, in applications where the standard
thresholds are not exactly right, or if higher precision is
needed in the threshold value, the X40010/11/14/15trip
points may be adjusted. The procedure is described
below, and uses the application of a high voltage control
signal.
In order to set V
to a lower voltage than the present
must first be “reset” according to the
TRIPx
value, then V
TRIPx
procedure described below. Once V
has been
TRIPx
“reset”, then V
can be set to the desired voltage
TRIPx
using the procedure described in “Setting a Higher
Voltage”.
V
TRIPx
FN8111 Rev 0.00
March 28, 2005
Page 4 of 24
X40010, X40011, X40014, X40015
Resetting the V Voltage
writing to the Control Register, the WEL and RWEL bits
must be set using a two step process, with the whole
sequence requiring 3 steps. See "Writing to the Control
Registers" on page 7.
TRIPx
To reset a V
voltage, apply the programming volt-
TRIPx
age (Vp) to the WDO pin before a START condition is
set up on SDA. Next, issue on the SDA pin the Slave
Address A0h followed by the Byte Address 03h for
The user must issue a stop, after sending this byte to the
register, to initiate the nonvolatile cycle that stores WD1,
WD0, PUP1, PUP0, BP1, and BP0. The
X40010/11/14/15 will not acknowledge any data bytes
written after the first byte is entered.
V
and 0Bh for V
, followed by 00h for the Data
TRIP1
TRIP2
Byte in order to reset V
. The STOP bit following a
TRIPx
valid write operation initiates the programming
sequence. Pin WDO must then be brought LOW to com-
plete the operation.
The state of the Control Register can be read at any time
by performing a random read at address 01Fh, using the
special preamble. Only one byte is read by each register
read operation. The master should supply a stop condi-
tion to be consistent with the bus protocol, but a stop is
not required to end this operation.
After being reset, the value of V
nal value of 1.7V or lesser.
becomes a nomi-
TRIPx
Note: This operation does not corrupt the memory array.
CONTROL REGISTER
The Control Register provides the user a mechanism for
changing the Block Lock and Watchdog Timer settings.
The Block Lock and Watchdog Timer bits are nonvolatile
and do not change when power is removed.
7
6
5
4
3
2
1
0
PUP1 WD1 WD0
BP
0
RWEL WEL PUP0
RWEL: Register Write Enable Latch (Volatile)
The Control Register is accessed with a special preamble
in the slave byte (1011) and is located at address 1FFh. It
can only be modified by performing a byte write operation
directly to the address of the register and only one data
byte is allowed for each register write operation. Prior to
The RWEL bit must be set to “1” prior to a write to the
Control Register.
Figure 4. Sample V
Reset Circuit
TRIP
VP
Adjust
V2FAIL
RESET
µC
1
3
2
4
8
SOIC
X4001x
7
6
5
Run
VTRIP1
Adj.
SCL
SDA
VTRIP2
Adj.
4.7K
FN8111 Rev 0.00
March 28, 2005
Page 5 of 24
X40010, X40011, X40014, X40015
Figure 5. V Set/Reset Sequence (X = 1, 2)
TRIPX
Vx = VCC, VxMON
Note: X = 1, 2
VTRIPX Programming
Let: MDE = Maximum Desired Error
Desired
VTRIPX
Present Value
No
MDE+
Acceptable
Desired Value
YES
Error Range
MDE–
Execute
TRIPX Reset Sequence
V
Error = Actual - Desired
Execute
Set Higher VTRIPX Sequence
New VX applied =
Old VX applied + | Error |
Execute
Set Higher VX Sequence
New VX applied =
Old VX applied - | Error |
Apply VCC and Voltage
Execute Reset VTRIPX
Sequence
> Desired VTRIPX to
VX
NO
Decrease
VX
Output Switches?
YES
V
Error < MDE–
Error > MDE+
Actual
TRIPX -
VTRIPX
Desired
| Error | < | MDE |
DONE
WEL: Write Enable Latch (Volatile)
The WEL bit controls the access to the memory and to
the Register during a write operation. This bit is a volatile
latch that powers up in the LOW (disabled) state. While
the WEL bit is LOW, writes to any address, including any
control registers will be ignored (no acknowledge will be
issued after the Data Byte). The WEL bit is set by writing
a “1” to the WEL bit and zeros to the other bits of the
control register.
Once set, WEL remains set until either it is reset to 0 (by
writing a “0” to the WEL bit and zeros to the other bits of
the control register) or until the part powers up again.
Writes to the WEL bit do not cause a high voltage write
cycle, so the device is ready for the next operation
immediately after the stop condition.
FN8111 Rev 0.00
March 28, 2005
Page 6 of 24
X40010, X40011, X40014, X40015
PUP1, PUP0: Power Up Bits (Nonvolatile)
– A read operation occurring between any of the
previous operations will not interrupt the register write
operation.
The Power Up bits, PUP1 and PUP0, determine the
tPURST time delay. The nominal power up times are
shown in the following table.
– The RWEL bit cannot be reset without writing to the
nonvolatile control bits in the control register, power
cycling the device or attempting a write to a write pro-
tected block.
PUP1 PUP0
Power on Reset Delay (tPURST)
0
0
1
1
0
1
0
1
50ms
200ms (factory setting)
400ms
To illustrate, a sequence of writes to the device consist-
ing of [02H, 06H, 02H] will reset all of the nonvolatile bits
in the Control Register to 0. A sequence of [02H, 06H,
06H] will leave the nonvolatile bits unchanged and the
RWEL bit remains set.
800ms
WD1, WD0: Watchdog Timer Bits (Nonvolatile)
FAULT DETECTION REGISTER
The bits WD1 and WD0 control the period of the Watch-
dog Timer. The options are shown below.
The Fault Detection Register (FDR) provides the user
the status of what causes the system reset active. The
Manual Reset Fail, Watchdog Timer Fail and three Low
Voltage Fail bits are volatile.
WD1
WD0
Watchdog Time Out Period
1.4 seconds
0
0
1
1
0
1
0
1
200 milliseconds
7
6
5
4
3
2
1
0
25 milliseconds
LV1F LV2F
0
WDF
0
0
0
0
disabled (factory setting)
The FDR is accessed with a special preamble in the
slave byte (1011) and is located at address 0FFh. It can
only be modified by performing a byte write operation
directly to the address of the register and only one data
byte is allowed for each register write operation.
Writing to the Control Registers
Changing any of the nonvolatile bits of the control and
trickle registers requires the following steps:
– Write a 02H to the Control Register to set the Write
Enable Latch (WEL). This is a volatile operation, so
there is no delay after the write. (Operation preceded
by a start and ended with a stop).
There is no need to set the WEL or RWEL in the control
register to access this fault detection register.
– Write a 06H to the Control Register to set the Register
Write Enable Latch (RWEL) and the WEL bit. This is
also a volatile cycle. The zeros in the data byte are
required. (Operation proceeded by a start and ended
with a stop).
– Write a one byte value to the Control Register that has
all the control bits set to the desired state. The Control
register can be represented as qxys 001r in binary,
where xy are the WD bits, s isthe BP bit and qr are the
power up bits. This operation proceeded by a start and
ended with a stop bit. Since this is a nonvolatile write
cycle it will take up to 10ms to
complete. The RWEL bit is reset by this cycle and the
sequence must be repeated to change the nonvolatile
bits again. If bit 2 is set to ‘1’ in this third step (qxys
011r) then the RWEL bit is set, but the WD1, WD0,
PUP1, PUP0, and BP bits remain unchanged. Writing
a second byte to the control register is not allowed.
Doing so aborts the write operation and returns a
NACK.
FN8111 Rev 0.00
March 28, 2005
Page 7 of 24
X40010, X40011, X40014, X40015
Figure 6. Valid Data Changes on the SDA Bus
SCL
SDA
Data Stable
Data Change
Data Stable
At power-up, the Fault Detection Register is defaulted to
all “0”. The system needs to initialize this register to all
“1” before the actual monitoring take place. In the event
of any one of the monitored sources failed. The corre-
sponding bits in the register will change from a “1” to a
“0” to indicate the failure. At this moment, the system
should perform a read to the register and noted the
cause of the reset. After reading the register the system
should reset the register back to all “1” again. The state
of the Fault Detection Register can be read at any time
by performing a random read at address 0FFh, using the
special preamble.
SERIAL INTERFACE
Interface Conventions
The device supports a bidirectional bus oriented proto-
col. The protocol defines any device that sends data
onto the bus as a transmitter, and the receiving device
as the receiver. The device controlling the transfer is
called the master and the device being controlled is
called the slave. The master always initiates data trans-
fers, and provides the clock for both transmit and receive
operations. Therefore, the devices in this family operate
as slaves in all applications.
The FDR can be read by performing a random read at
OFFh address of the register at any time. Only one byte
of data is read by the register read operation.
Serial Clock and Data
Data states on the SDA line can change only during SCL
LOW. SDA state changes during SCL HIGH are
reserved for indicating start and stop conditions. See
Figure 6.
WDF, Watchdog Timer Fail Bit (Volatile)
The WDF bit will set to “0” when the WDO goes active.
Serial Start Condition
LV1F, Low V Reset Fail Bit (Volatile)
CC
All commands are preceded by the start condition, which
is a HIGH to LOW transition of SDA when SCL is HIGH.
The device continuously monitors the SDA and SCL
lines for the start condition and will not respond to any
command until this condition has been met. See Figure
6.
The LV1F bit will be set to “0” when V (V1MON) falls
CC
below V
.
TRIP1
LV2F, Low V2MON Reset Fail Bit (Volatile)
The LV2F bit will be set to “0” when V2MON falls below
V
.
TRIP2
Serial Stop Condition
All communications must be terminated by a stop condi-
tion, which is a LOW to HIGH transition of SDA when SCL
is HIGH. The stop condition is also used to place the
device into the Standby power mode after a read
sequence. A stop condition can only be issued after the
transmitting device has released the bus. See Figure 6.
FN8111 Rev 0.00
March 28, 2005
Page 8 of 24
X40010, X40011, X40014, X40015
Figure 7. Valid Start and Stop Conditions
SCL
SDA
Start
Stop
Serial Acknowledge
Acknowledge is a software convention used to indicate
successful data transfer. The transmitting device, either
master or slave, will release the bus after transmitting
eight bits. During the ninth clock cycle, the receiver will
pull the SDA line LOW to acknowledge that it received
the eight bits of data. See Figure 8.
The master must then issue a stop condition to return
the device to Standby mode and place the device into a
known state.
Serial Write Operations
Byte Write
The device will respond with an acknowledge after rec-
ognition of a start condition and if the correct Device
Identifier and Select bits are contained in the Slave
Address Byte. If a write operation is selected, the device
will respond with an acknowledge after the receipt of
each subsequent eight bit word. The device will
acknowledge all incoming data and address bytes,
except for the Slave Address Byte when the Device
Identifier and/or Select bits are incorrect.
For a write operation, the device requires the Slave
Address Byte and a Word Address Byte. This gives the
master access to any one of the words in the array. After
receipt of the Word Address Byte, the device responds
with an acknowledge, and awaits the next eight bits of
data. After receiving the 8 bits of the Data Byte, the
device again responds with an acknowledge. The mas-
ter then terminates the transfer by generating a stop
condition, at which time the device begins the internal
write cycle to the nonvolatile memory. During this internal
write cycle, the device inputs are disabled, so the device
will not respond to any requests from the master. The SDA
output is at high impedance. See Figure 9.
In the read mode, the device will transmit eight bits of
data, release the SDA line, then monitor the line for an
acknowledge. If an acknowledge is detected and no stop
condition is generated by the master, the device will con-
tinue to transmit data. The device will terminate further
data transmissions if an acknowledge is not detected.
A write to a protected block of memory will suppress the
acknowledge bit.
Figure 8. Acknowledge Response From Receiver
SCL from
Master
1
8
9
Data Output
from
Data Output
from Receiver
Start
Acknowledge
FN8111 Rev 0.00
March 28, 2005
Page 9 of 24
X40010, X40011, X40014, X40015
Read Operation
another start condition and the Slave Address Byte with the
R/W bit set to one. This is followed by an acknowledge
from the device and then by the eight bit word. The master
terminates the read operation by not responding with an
acknowledge and then issuing a stop condition. See Figure
12 for the address, acknowledge, and data transfer
sequence.
Prior to issuing the Slave Address Byte with the R/W bit set
to one, the master must first perform a “dummy” write oper-
ation. The master issues the start condition and the Slave
Address Byte, receives an acknowledge, then issues the
Word Address Bytes. After acknowledging receipts of the
Word Address Bytes, the master immediately issues
Figure 9. Read Sequence
S
S
S
t
a
r
Slave
Address
Byte
Address
Slave
Address
t
a
r
Signals from
the Master
t
o
p
t
t
SDA Bus
1
1 0 1
1 0 0
0
1 1 1 1 1 1 1 1
A
C
K
A
C
K
A
C
K
Signals from
the Slave
Data
Stops and Write Modes
Serial Read Operations
Stop conditions that terminate write operations must be
sent by the master after sending at least 1 full data byte
plus the subsequent ACK signal. If a stop is issued in the
middle of a data byte, or before 1 full data byte plus its
associated ACK is sent, then the device will reset itself
without performing the write. The contents of the array
will not be effected.
Read operations are initiated in the same manner as
write operations with the exception that the R/W bit of
the Slave Address Byte is set to one. There are three
basic read operations: Current Address Reads, Random
Reads, and Sequential Reads.
Current Address Read
Internally the device contains an address counter that
maintains the address of the last word read incremented
by one. Therefore, if the last read was to address n, the
next read operation would access data from address
n+1. On power up, the address of the address counter is
undefined, requiring a read or write operation for initial-
ization.
Acknowledge Polling
The disabling of the inputs during high voltage cycles
can be used to take advantage of the typical 5ms write
cycle time. Once the stop condition is issued to indicate
the end of the master’s byte load operation, the device
initiates the internal high voltage cycle. Acknowledge
polling can be initiated immediately. To do this, the mas-
ter issues a start condition followed by the Slave
Address Byte for a write or read operation. If the device
is still busy with the high voltage cycle then no ACK will
be returned. If the device has completed the write opera-
tion, an ACK will be returned and the host can then pro-
ceed with the read or write operation. See Figure 12.
Upon receipt of the Slave Address Byte with the R/W bit
set to one, the device issues an acknowledge and then
transmits the eight bits of the Data Byte. The master ter-
minates the read operation when it does not respond
with an acknowledge during the ninth clock and then
issues a stop condition. See Figure 13 for the address,
acknowledge, and data transfer sequence.
FN8111 Rev 0.00
March 28, 2005
Page 10 of 24
X40010, X40011, X40014, X40015
Figure 10. Acknowledge Polling Sequence
A similar operation called “Set Current Address” where
the device will perform this operation if a stop is issued
instead of the second start shown in Figure 13. The
device will go into standby mode after the stop and all
bus activity will be ignored until a start is detected. This
operation loads the new address into the address
counter. The next Current Address Read operation will
read from the newly loaded address. This operation
could be useful if the master knows the next address it
needs to read, but is not ready for the data.
Byte Load Completed
by Issuing STOP.
Enter ACK Polling
Issue START
Issue Slave Address
Byte (Read or Write)
Issue STOP
Sequential Read
Sequential reads can be initiated as either a current
address read or random address read. The first Data Byte
is transmitted as with the other modes; however, the mas-
ter now responds with an acknowledge, indicating it
requires additional data. The device continues to output
data for each acknowledge received. The master termi-
nates the read operation by not responding with an
acknowledge and then issuing a stop condition.
NO
ACK
Returned?
YES
High Voltage Cycle
Complete. Continue
Command Sequence?
Issue STOP
NO
The data output is sequential, with the data from address
n followed by the data from address n + 1. The address
counter for read operations increments through all page
and column addresses, allowing the entire memory con-
tents to be serially read during one operation. At the end
of the address space the counter “rolls over” to address
YES
Continue Normal
Read or Write
Command Sequence
0000 and the device continues to output data for each
H
acknowledge received. See Figure 15 for the acknowl-
edge and data transfer sequence.
PROCEED
It should be noted that the ninth clock cycle of the read
operation is not a “don’t care.” To terminate a read oper-
ation, the master must either issue a stop condition
during the ninth cycle or hold SDA HIGH during the ninth
clock cycle and then issue a stop condition.
Random Read
Random read operation allows the master to access any
memory location in the array. Prior to issuing the Slave
Address Byte with the R/W bit set to one, the master must
first perform a “dummy” write operation. The master issues
the start condition and the Slave Address Byte, receives an
acknowledge, then issues the Word Address Bytes. After
acknowledging receipts of the Word Address Bytes, the
master immediately issues another start condition and the
Slave Address Byte with the R/W bit set to one. This is fol-
lowed by an acknowledge from the device and then by the
eight bit word. The master terminates the read operation by
not responding with an acknowledge and then issuing a
stop condition. See Figure 14 for the address, acknowl-
edge, and data transfer sequence.
FN8111 Rev 0.00
March 28, 2005
Page 11 of 24
X40010, X40011, X40014, X40015
SERIAL DEVICE ADDRESSING
– One bit of the slave command byte is a R/W bit. The
R/W bit of the Slave Address Byte defines the opera-
tion to be performed. When the R/W bit is a one, then
a read operation is selected. A zero selects a write
operation.
Memory Address Map
CR, Control Register, CR7: CR0
Address: 1FF
hex
FDR, Fault DetectionRegister, FDR7: FDR0
Address: 0FF
Figure 11. X40010/11/14/15 Addressing
hex
Slave Byte
Slave Address Byte
Control Register
1
1
0
0
1
1
1
1
0
0
0
0
1
0
R/W
R/W
Fault Detection Register
Following a start condition, the master must output a
Slave Address Byte. This byte consists of several parts:
– a device type identifier that is always ‘101x’. Where
x=0 is for Array, x=1 is for Control Register or Fault
Detection Register.
Word Address
Control Register
1
1
1
1
1
1
1
1
1
1
1
1
1
Fault Detection Register
1
1
1
– next two bits are ‘0’.
– next bit that becomes the MSB of the address.
Figure 12. Current Address Read Sequence
S
Slave
Address
t
a
r
S
Signals from
the Master
t
o
p
t
SDA Bus
1 0 1 0 0 0
1
Signals from
the Slave
Data
Figure 13. Random Address Read Sequence
S
S
S
t
o
p
t
a
r
Slave
Address
Byte
Address
Slave
Address
t
a
r
Signals from
the Master
t
t
SDA Bus
1 0 1 0 0
1
0
A
C
K
A
C
K
A
C
K
Signals from
the Slave
Data
FN8111 Rev 0.00
March 28, 2005
Page 12 of 24
X40010, X40011, X40014, X40015
Word Address
Data Protection
The word address is either supplied by the master or
obtained from an internal counter. The internal counter is
undefined on a power up condition.
The following circuitry has been included to prevent
inadvertent writes:
– The WEL bit must be set to allow write operations.
– The proper clock count and bit sequence is required
prior to the stop bit in order to start a nonvolatile write
cycle.
Operational Notes
The device powers-up in the following state:
– The device is in the low power standby state.
– A three step sequence is required before writing into
the Control Register to change Watchdog Timer or
Block Lock settings.
– The WEL bit is set to ‘0’. In this state it is not possible
to write to the device.
– SDA pin is the input mode.
– RESET/RESET Signal is active for tPURST
.
Figure 14. Sequential Read Sequence
S
t
Slave
Address
Signals from
the Master
o
A
C
K
A
C
K
A
C
K
p
SDA Bus
1
A
C
K
Signals from
the Slave
Data
(2)
Data
(n-1)
Data
(1)
Data
(n)
(n is any integer greater than 1)
FN8111 Rev 0.00
March 28, 2005
Page 13 of 24
X40010, X40011, X40014, X40015
ABSOLUTE MAXIMUM RATINGS
COMMENT
Temperature under bias.................... -65°C to +135°C
Storage temperature ......................... -65°C to +150°C
Voltage on any pin with
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only; functional operation of the
device (at these or any other conditions above those
listed in the operational sections of this specification) is
not implied. Exposure to absolute maximum rating condi-
tions for extended periods may affect device reliability.
respect to V ...................................... -1.0V to +7V
SS
D.C. output current...............................................5mA
Lead temperature (soldering, 10 seconds)........ 300°C
RECOMMENDED OPERATING CONDITIONS
Temperature
Commercial
Industrial
Min.
0°C
Max.
70°C
Table 2:
Chip Supply Volt-
age
Monitored*
Voltages
–40°C
+85°C
Version
X40010/11
-A or -B
2.7V to 5.5V
2.6V to 5V
D.C. OPERATING CHARACTERISTICS
(Over the recommended operating conditions unless otherwise specified)
(4)
Symbol
Parameter
Min.
Typ.
Max.
Unit
Test Conditions
(1)
ICC1
Active Supply Current (V ) Read
1.5
3.0
mA VIL = V x 0.1
CC
CC
(1)
VIH = V x 0.9,
ICC2
Active Supply Current (V ) Read
mA
CC
CC
fSCL = 400kHz
(1)(6)
ISB1
Standby Current (V ) AC (WDT off)
6
10
µA VIL = V x 0.1
CC
CC
VIH = V x 0.9
CC
fSCL, fSDA = 400kHz
(2)(6)
ISB2
Standby Current (V ) DC (WDT on)
25
30
µA VSDA = VSCL = VCC
Others = GND or VCC
CC
ILI
Input Leakage Current (SCL)
10
10
µA VIL = GND to V
CC
ILO
Output Leakage Current (SDA, V2-
FAIL, WDO, RESET)
µA
VSDA = GND to V
CC
Device is in Standby(2)
(3)
VIL
Input LOW Voltage (SDA, SCL)
Input HIGH Voltage (SDA, SCL)
-0.5
V
V
x 0.3
V
V
CC
(3)
VIH
V
x 0.7
+ 0.5
CC
CC
(6)
VHYS
Schmitt Trigger Input Hysteresis
• Fixed input level
0.2
.05 x V
V
V
• V related level
CC
CC
VOL
VOH
Output LOW Voltage (SDA, RE-
SET/RESET, V2FAIL, WDO)
0.4
V
I
OL = 3.0mA (2.7-5.5V)
IOL = 1.8mA (2.7-3.6V)
OH = -1.0mA (2.7-5.5V)
Output (RESET) HIGH Voltage
V
V
- 0.8
- 0.4
V
I
CC
CC
IOH = -0.4mA (2.7-3.6V)
V
CC Supply
(5)
VTRIP1
V
Trip Point Voltage Range
2.0
4.75
4.65
4.45
2.95
V
V
V
V
CC
4.55
4.35
2.85
4.6
4.4
2.9
X40010/11-A
X40010/11-B
X40010/11-C,
X40014/15-A&C
2.55
2.6
2.65
5
V
X40014/15-B
(6)
tRPD2
VTRIP2 to V2FAIL
µS
FN8111 Rev 0.00
March 28, 2005
Page 14 of 24
X40010, X40011, X40014, X40015
D.C. OPERATING CHARACTERISTICS (Continued)
(Over the recommended operating conditions unless otherwise specified)
(4)
Symbol
Parameter
Min.
Typ.
Max.
Unit
Test Conditions
Second Supply Monitor
IV2
V2MON Current
V2MON Trip Point Voltage Range
15
µA
(5)
VTRIP2
1.7
0.9
4.75
3.5
V
V
X40010/11
X40014/15
2.85
2.55
1.65
1.25
0.95
2.9
2.6
1.7
1.3
1.0
2.95
2.65
1.75
1.35
1.05
V
V
V
V
V
X40010/11-A
X40010/11-B
X40010/11-C
X40014/15-A&B
X40014/15-C
Notes: (1) The device enters the Active state after any start, and remains active until: 9 clock cycles later if the Device Select Bits in the Slave
Address Byte are incorrect; 200ns after a stop ending a read operation; or tWC after a stop ending a write operation.
(2) The device goes into Standby: 200ns after any stop, except those that initiate a high voltage write cycle; tWC after a stop that initiates a
high voltage cycle; or 9 clock cycles after any start that is not followed by the correct Device Select Bits in the Slave Address Byte.
(3) VIL Min. and VIH Max. are for reference only and are not tested.
(4) At 25°C, VCC = 5V.
(5) See Ordering Information for standard programming levels. For custom programmed levels, contact factory.
(6) Based on characterization data.
EQUIVALENT INPUT CIRCUIT FOR VxMON (x = 1, 2)
R
V = 100mV
VxMON
V
Vref
+
–
Output Pin
VREF
C
tRPDX = 5µs worst case
CAPACITANCE
Symbol
Parameter
Max.
Unit
Test Conditions
OUT = 0V
(1)
COUT
Output Capacitance (SDA, RESET, RESET, V2FAIL,
WDO)
8
pF
V
(1)
CIN
Input Capacitance (SCL)
6
pF
VIN = 0V
Note: (1) This parameter is not 100% tested.
FN8111 Rev 0.00
March 28, 2005
Page 15 of 24
X40010, X40011, X40014, X40015
EQUIVALENT A.C. OUTPUT LOAD CIRCUIT FOR V
= 5V
SYMBOL TABLE
CC
WAVEFORM
INPUTS
OUTPUTS
VOUT
5V
V2MON
Must be
steady
Will be
steady
4.6K
4.6K
2.06K
May change
from LOW
Will change
from LOW
to HIGH
RESET
WDO
V2FAIL
30pF
SDA
May change
from HIGH
to LOW
Will change
from HIGH
to LOW
30pF
30pF
Don’t Care:
Changes
Allowed
Changing:
State Not
Known
A.C. TEST CONDITIONS
N/A
Center Line
is High
Impedance
Input pulse levels
V
x 0.1 to V x 0.9
CC
CC
Input rise and fall times
Input and output timing levels
Output load
10ns
V
x 0.5
CC
Standard output load
FN8111 Rev 0.00
March 28, 2005
Page 16 of 24
X40010, X40011, X40014, X40015
A.C. CHARACTERISTICS
400kHz
Symbol
Parameter
Min.
0
Max.
Unit
kHz
ns
fSCL
tIN
SCL Clock Frequency
400
Pulse width Suppression Time at inputs
SCL LOW to SDA Data Out Valid
Time the bus free before start of new transmission
Clock LOW Time
50
tAA
0.1
1.3
1.3
0.6
0.6
0.6
100
0
0.9
µs
tBUF
µs
tLOW
tHIGH
tSU:STA
tHD:STA
tSU:DAT
tHD:DAT
tSU:STO
tDH
µs
Clock HIGH Time
µs
Start Condition Setup Time
Start Condition Hold Time
Data In Setup Time
µs
µs
ns
Data In Hold Time
µs
Stop Condition Setup Time
Data Output Hold Time
0.6
50
µs
ns
tR
SDA and SCL Rise Time
SDA and SCL Fall Time
20 +.1Cb(1)
20 +.1Cb(1)
300
300
400
ns
tF
ns
Cb
Capacitive load for each bus line
pF
Note: (1) Cb = total capacitance of one bus line in pF.
TIMING DIAGRAMS
Bus Timing
tF
tHIGH
tLOW
tR
SCL
SDA IN
tSU:DAT
tSU:STA
tHD:DAT
tSU:STO
tHD:STA
tAA tDH
tBUF
SDA OUT
FN8111 Rev 0.00
March 28, 2005
Page 17 of 24
X40010, X40011, X40014, X40015
Write Cycle Timing
SCL
8th Bit of Last Byte
ACK
SDA
tWC
Stop
Start
Condition
Condition
Nonvolatile Write Cycle Timing
(1)
Symbol
Parameter
Write Cycle Time
Min.
Typ.
Max.
10
Unit
(1)
tWC
5
ms
Note: (1) tWC is the time from a valid stop condition at the end of a write sequence to the end of the self-timed internal nonvolatile write cycle. It is
the minimum cycle time to be allowed for any nonvolatile write by the user, unless Acknowledge Polling is used.
Power Fail Timings
tR
VTRIPX
tRPDL
tRPDX
tRPDL
tRPDX
V
CC or
tRPDL
tRPDX
V2MON
[ ]
tF
LOWLINE or
V2FAIL or
[ ]
VRVALID
V3FAIL
X = 2, 3
FN8111 Rev 0.00
March 28, 2005
Page 18 of 24
X40010, X40011, X40014, X40015
RESET/RESET Timings
VTRIP1
VCC
tPURST
tPURST
tRPD1
tF
tR
RESET
RESET
VRVALID
LOW VOLTAGE AND WATCHDOG TIMING PARAMETERS
Symbol
Parameters
VTRIP1 to RESET/RESET (Power down only)
VTRIP2 to V2FAIL
Min. Typ.(1) Max.
Unit
µs
(2)
tRPD1
5
5
(2)
tRPDX
µs
tPURST
Power On Reset delay:
PUP1=0, PUP0=0
PUP1=0, PUP0=1 (factory setting)
PUP1=1, PUP0=0
50
ms
ms
ms
ms
200(2)
400(2)
800(2)
PUP1=1, PUP0=1
tF
VCC, V2MON, Fall Time
VCC, V2MON, Rise Time
20
20
1
mVµs
mVµs
V
tR
VRVALID Reset Valid VCC
tWDO
Watchdog Timer Period:
WD1=0, WD0=0
WD1=0, WD0=1
WD1=1, WD0=0
1.4(2)
200(2)
25
s
ms
ms
WD1=1, WD0=1 (factory setting)
OFF
tRST1
Watchdog Reset Time Out Delay
WD1=0, WD0=0
100
200
300
ms
WD1=0, WD0=1
tRST2
tRSP
Watchdog Reset Time Out Delay WD1=1, WD0=0
Watchdog timer restart pulse width
12.5
1
25
37.5
ms
µs
Notes: (1) VCC = 5V at 25°C.
(2) Values based on characterization data only.
FN8111 Rev 0.00
March 28, 2005
Page 19 of 24
X40010, X40011, X40014, X40015
Watchdog Time Out For 2-Wire Interface
Start
Start
Clockin (0 or 1)
tRSP
< tWDO
SCL
SDA
tRST
tWDO
tRST
WDO
WDT
Restart
Start
Minimum Sequence to Reset WDT
SCL
SDA
V
Set/Reset Conditions
TRIPX
(VTRIPX
)
VCC/V2MON
tTHD
VP
tTSU
WDO
tVPS
tVPO
tVPH
7
SCL
SDA
0
0
7
0
7
tWC
A0h
00h
Start
resets VTRIP1
resets VTRIP2
01h*
09h*
03h*
0Bh*
sets VTRIP1
sets VTRIP2
* all others reserved
FN8111 Rev 0.00
March 28, 2005
Page 20 of 24
X40010, X40011, X40014, X40015
V
, V
, Programming Specifications: V = 2.0-5.5V; Temperature = 25°C
TRIP1
TRIP2
CC
Parameter
tVPS
Description
WDO Program Voltage Setup time
WDO Program Voltage Hold time
VTRIPX Level Setup time
Min.
10
Max. Unit
µs
µs
tVPH
10
tTSU
10
µs
tTHD
VTRIPX Level Hold (stable) time
10
µs
tWC
VTRIPX Program Cycle
10
ms
ms
tVPO
Program Voltage Off time before next cycle
Programming Voltage
1
VP
15
18
V
V
VTRAN1
VTRAN2
VTRAN2A
Vtv
VTRIP1 Set Voltage Range
2.0
1.7
0.9
-25
10
4.75
4.75
3.5
VTRIP2 Set Voltage Range – X40010/11
VTRIP2 Set to Voltage Range – X40014/15
VTRIPX Set Voltage variation after programming (-40 to +85°C).
WDO Program Voltage Setup time
V
V
+25
mV
µs
tVPS
© Copyright Intersil Americas LLC 2005. All Rights Reserved.
All trademarks and registered trademarks are the property of their respective owners.
For additional products, see www.intersil.com/en/products.html
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such
modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are
current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its
subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN8111 Rev 0.00
March 28, 2005
Page 21 of 24
X40010, X40011, X40014, X40015
PACKAGING INFORMATION
8-Lead Plastic, SOIC, Package Code S8
0.150 (3.80) 0.228 (5.80)
0.158 (4.00) 0.244 (6.20)
Pin 1 Index
Pin 1
0.014 (0.35)
0.019 (0.49)
0.188 (4.78)
0.197 (5.00)
(4X) 7°
0.053 (1.35)
0.069 (1.75)
0.004 (0.19)
0.010 (0.25)
0.050 (1.27)
0.010 (0.25)
0.020 (0.50)
0.050" Typical
X 45°
0.050"
Typical
0° - 8°
0.0075 (0.19)
0.010 (0.25)
0.250"
0.016 (0.410)
0.037 (0.937)
0.030"
Typical
8 Places
FOOTPRINT
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
FN8111 Rev 0.00
March 28, 2005
Page 22 of 24
X40010, X40011, X40014, X40015
PACKAGING INFORMATION
8-Lead Plastic, TSSOP, Package Code V8
.025 (.65) BSC
.169 (4.3)
.252 (6.4) BSC
.177 (4.5)
.114 (2.9)
.122 (3.1)
.047 (1.20)
.0075 (.19)
.0118 (.30)
.002 (.05)
.006 (.15)
.010 (.25)
Gage Plane
0° - 8°
Seating Plane
.019 (.50)
.029 (.75)
(7.72)
(4.16)
Detail A (20X)
(1.78)
(0.42)
.031 (.80)
.041 (1.05)
(0.65)
All Measurements Are Typical
See Detail “A”
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
FN8111 Rev 0.00
March 28, 2005
Page 23 of 24
X40010, X40011, X40014, X40015
ORDERING INFORMATION
V
Operating Tem- Part Number
Part Number
with RESET
CC
Range
V
Range
V
Range
Package
perature Range
with RESET
X40010S8-A
X40010S8I-A
X40010V8-A
X40010V8I-A
X40010S8-B
X40010S8I-B
X40010V8-B
X40010V8I-B
X40010S8-C
X40010S8I-C
X40010V8-C
X40010V8I-C
X40014S8-A
X40014S8I-A
X40014V8-A
X40014V8I-A
X40014S8-B
X40014S8I-B
X40014V8-B
X40014V8I-B
X40014S8-C
X40014S8I-C
X40014V8-C
X40014V8I-C
TRIP1
TRIP2
2.9-5.5
4.6V±50mV
4.4V±50mV
2.9V±50mV
2.9V±50mV
2.6V±50mV
2.9V±50mV
2.9V±50mV
2.6V±50mV
1.7V±50mV
1.3V±50mV
1.3V±50mV
1.0V±50mV
8L SOIC
0oC - 70oC
-40oC - 85oC
0oC - 70oC
X40011S8-A
X40011S8I-A
X40011V8-A
X40011V8I-A
X40011S8-B
X40011S8I-B
X40011V8-B
X40011V8I-B
X40011S8-C
X40011S8I-C
X40011V8-C
X40011V8I-C
X40015S8-A
X40015S8I-A
X40015V8-A
X40015V8I-A
X40015S8-B
X40015S8I-B
X40015V8-B
X40015V8I-B
X40015S8-C
X40015S8I-C
X40015V8-C
X40015V8I-C
8L TSSOP
8L SOIC
-40oC - 85oC
0oC - 70oC
2.6-5.5
1.7-3.6
1.3-3.6
1.3-3.6
1.0-3.6
-40oC - 85oC
0oC - 70oC
8L TSSOP
8L SOIC
-40oC - 85oC
0oC - 70oC
-40oC - 85oC
0oC - 70oC
8L TSSOP
8L SOIC
-40oC - 85oC
0oC - 70oC
-40oC - 85oC
0oC - 70oC
8L TSSOP
8L SOIC
-40oC - 85oC
0oC - 70oC
-40oC - 85oC
0oC - 70oC
8L TSSOP
8L SOIC
-40oC - 85oC
0oC - 70oC
-40oC - 85oC
0oC - 70oC
-40oC - 85oC
8L TSSOP
PART MARK INFORMATION
8-Lead Package
0/1/4/5
X4001XX
YYWWXX
Package - S/V
A, B, or C
I – Industrial
Blank – Commercial
WW – Workweek
YY – Year
FN8111 Rev 0.00
March 28, 2005
Page 24 of 24
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