X40421V14I-A [RENESAS]
2-CHANNEL POWER SUPPLY MANAGEMENT CKT, PDSO14, PLASTIC, TSSOP-14;
| 型号： | X40421V14I-A |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | 2-CHANNEL POWER SUPPLY MANAGEMENT CKT, PDSO14, PLASTIC, TSSOP-14 光电二极管 |
| 文件： | 总25页 (文件大小：963K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SIGNS
MENT
enter at
m/tsc
DED FOR NEW DE
ENDED REPLACE
chnical Support C
or www.intersil.co
NOT RECOMMEN
DATASHEET
NO RECOMM
contact our Te
1-888-INTERSIL
X40420, X40421
FN8117
Rev 1.00
May 25, 2006
4kbit EEPROM Dual Voltage Monitor with Integrated CPU Supervisor and System
Battery Switch
FEATURES
• Battery switch backup
• V 5mA to 50mA
OUT
• Dual voltage detection and reset assertion
—Three standard reset threshold settings
(4.6V/2.9V, 4.6V/2.6V, 2.9V/1.6V)
APPLICATIONS
• Communications equipment
—Routers, hubs, switches
—Disk arrays
• Industrial systems
—Process control
—Intelligent instrumentation
• Computer systems
—Desktop computers
—Network servers
—V
programmable down to 0.9V
TRIP2
—Adjust low voltage reset threshold voltages
using special programming sequence
—Reset signal valid to V = 1V
—Monitor two voltages or detect power fail
• Battery switch backup
CC
• V
V
: 5mA to 50mA from V ; or 250µA from
OUT
BATT
CC
• Fault detection register
• Selectable power-on reset timeout
(0.05s, 0.2s, 0.4s, 0.8s)
• Selectable watchdog timer interval
(25ms, 200ms, 1.4s, off)
• Debounced manual reset input
• Low power CMOS
—25µA typical standby current, watchdog on
—6µA typical standby current, watchdog off
—1µA typical battery current in backup mode
• 4Kbits of EEPROM
X40420, X40421
Standard VTRIP1 Level Standard VTRIP2 Level Suffix
4.6V (±1%)
4.6V (±1%)
2.9V(±1.7%)
2.9V(±1.7%)
2.6V (±2%)
1.6V (±3%)
-A
-B
-C
See “Ordering Information” for more details
For Custom Settings, call Intersil.
DESCRIPTION
—16 byte page write mode
—Self-timed write cycle
The X40420, X40421 combines power-on reset con-
trol, watchdog timer, supply voltage supervision, and
secondary supervision, manual reset, and Block
Lock protect serial EEPROM in one package. This
combination lowers system cost, reduces board space
requirements, and increases reliability.
—5ms write cycle time (typical)
• Built-in inadvertent write protection
—Power-up/power-down protection circuitry
—Block lock protect 0 or 1/2, of EEPROM
• 400kHz 2-wire interface
• 2.7V to 5.5V power supply operation
• Available packages
™
Applying voltage to V
activates the power-on reset
CC
—14 Ld SOIC, TSSOP
circuit which holds RESET/RESET active for a period of
time. This allows the power supply and system oscilla-
tor to stabilize before the processor can execute code.
• Pb-free plus anneal available (RoHS compliant)
• Monitor voltages: 5V to 1.6V
• Memory security
BLOCK DIAGRAM
VOUT
+
-
V2FAIL
WDO
V2MON
VTRIP2
V2 Monitor
Logic
Watchdog
and
Reset Logic
Fault Detection
Register
Data
Register
SDA
WP
VOUT
Status
Register
Command
Decode Test
& Control
Logic
EEPROM
Array
MR
RESET
X40420
SCL
Power-on,
Manual Reset
Low Voltage
Reset
VOUT
RESET
X40421
+
VCC
(V1MON)
VTRIP1
Generation
VCC Monitor
Logic
-
BATT-ON
VOUT
LOWLINE
System
Battery
Switch
VBATT
FN8117 Rev 1.00
May 25, 2006
Page 1 of 25
X40420, X40421
Ordering Information
PART
NUMBER*
WITH RESET
PART
NUMBER*
WITH RESET
MONITORED
VCC
SUPPLIES
PART
MARKING
PART
MARKING
VTRIP1
VTRIP2
TEMP.
PKG.
RANGE
RANGE RANGE (°C) PACKAGE
DWG. #
X40420S14-C X40420S C X40421S14-C X40421S C
X40420S14I-C X40420S IC X40421S14I-C X40421S IC
X40420V14-C X4042 0VC X40421V14-C X40421V C
X40420V14I-C X4042 0VIC X40421V14I-C X40421V IC
X40420S14-B X40420S B X40421S14-B X40421S B
X40420S14Z-B X40420S ZB X40421S14Z-B X40421S ZB
1.6 to 3.6
2.9V ±50mV 1.6V ±50mV
0 to 70
14 Ld SOIC MDP0027
(150 mil)
-40 to +85 14 Ld SOIC MDP0027
(150 mil)
0 to 70
14 Ld TSSOP M14.173
(4.4mm)
-40 to +85 14 Ld TSSOP M14.173
(4.4mm)
2.6 to 5.5
4.6V ±50mV 2.6V ±50mV
0 to 70
14 Ld SOIC MDP0027
(150 mil)
0 to 70
14 Ld SOIC MDP0027
(150 mil)
(Note)
(Note)
(Pb-free)
X40420S14I-B X40420S IB X40421S14I-B X40421S IB
X40420S14IZ-B X40420S ZIB X40421S14IZ-B X40421S ZIB
-40 to +85 14 Ld SOIC MDP0027
(150 mil)
-40 to +85 14 Ld SOIC MDP0027
(Note)
(Note)
(150 mil)
(Pb-free)
X40420V14-B X4042 0VB X40421V14-B X40421V B
0 to 70
0 to 70
14 Ld TSSOP M14.173
(4.4mm)
X40420V14Z-B X4042 0VZB X40421V14Z-B X40421V ZB
14 Ld TSSOP M14.173
(4.4mm)
(Note)
(Note)
(Pb-free)
X40420V14I-B X4042 0VIB X40421V14I-B X40421V IB
-40 to +85 14 Ld TSSOP M14.173
(4.4mm)
X40420V14IZ-B X4042 0VZIB X40421V14IZ-B X40421V ZIB
-40 to +85 14 Ld TSSOP M14.173
(Note)
(Note)
(4.4mm)
(Pb-free)
X40420S14-A X40420S A X40421S14-A X40421S A
X40420S14Z-A X40420S ZA X40421S14Z-A X40421S ZA
2.9 to 5.5
2.9V ±50mV
0 to 70
0 to 70
14 Ld SOIC MDP0027
(150 mil)
14 Ld SOIC MDP0027
(150 mil)
(Note)
(Note)
(Pb-free)
X40420S14I-A X40420S IA X40421S14I-A X40421S IA
-40 to +85 14 Ld SOIC MDP0027
(150 mil)
X40420S14IZ-A X40420S ZIA X40421S14IZ-A X40421S ZIA
-40 to +85 14 Ld SOIC MDP0027
(Note)
(Note)
(150 mil)
(Pb-free)
X40420V14Z-A X4042 0VZA X40421V14Z-A X40421V ZA
(Note) (Note)
0 to 70
0 to 70
14 Ld TSSOP M14.173
(4.4mm)
(Pb-free)
X40420V14-A X4042 0VA X40421V14-A X40421V A
X40420V14I-A X4042 0VIA X40421V14I-A X40421V IA
X40420V14IZ-A X4042 0VZIA X40421V14IZ-A X40421V ZIA
14 Ld TSSOP M14.173
(4.4mm)
-40 to +85 14 Ld TSSOP M14.173
(4.4mm)
-40 to +85 14 Ld TSSOP M14.173
(Note)
(Note)
(4.4mm)
(Pb-free)
*Add "T1" suffix for tape and reel.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
FN8117 Rev 1.00
May 25, 2006
Page 2 of 25
X40420, X40421
Low V detection circuitry protects the user’s system
selected, the interval does not change, even after
cycling the power.
CC
from low voltage conditions, resetting the system when
falls below the minimum point.
RESET/RESET is active until V returns to proper
V
V
TRIP1
CC
The memory portion of the device is a CMOS Serial
EEPROM array with Intersil’s Block Lock protection. The
array is internally organized as x 8. The device features
an 2-wire interface and software protocol allowing oper-
ation on a two-wire bus.
CC
operating level and stabilizes. A second voltage monitor
circuit tracks the unregulated supply to provide a power
fail warning or monitors different power supply voltage.
Three common low voltage combinations are available,
however, Intersil’s unique circuits allows the threshold
for either voltage monitor to be reprogrammed to meet
special needs or to fine-tune the threshold for applica-
tions requiring higher precision.
™
The device utilizes Intersil’s proprietary Direct Write
cell, providing a minimum endurance of 100,000 cycles
and a minimum data retention of 100 years.
Example Application
A manual reset input provides debounce circuitry for
minimum reset component count.
Unreg.
Supply
5V
REG
A battery switch circuit compares V
with V
input
CC
BATT
and connects V
to whichever is higher. This provides
OUT
voltage to external SRAM or other circuits in the event of
main power failure. The X40420, X40421 can drive
BATT-ON
CC
Enable
SRAM
V
V
V
OUT
BATT
50mA from V
to 250µA from V
. The device only
CC
BATT
Addr
+
X40420, X40421
V2MON
switches to V
when V
drops below the low V
BATT
CC CC
Addr
uC
voltage threshold and V
.
BATT
The Watchdog Timer provides an independent protec-
tion mechanism for microcontrollers. When the micro-
controller fails to restart a timer within a selectable time
out interval, the device activates the WDO signal. The
user selects the interval from three preset values. Once
NMI
V
V2FAIL
CC
VDO
RESET
MR
IRQ
RESET
Manual
Reset
SCL SDA
2
I C
PIN CONFIGURATION
X40421
14-Pin SOIC, TSSOP
X40420
14-Pin SOIC, TSSOP
VCC
V2FAIL
V2MON
LOWLINE
WDO
MR
RESET
VSS
VCC
V2FAIL
V2MON
1
2
3
4
14
13
12
11
1
2
3
4
14
13
12
11
BATT-ON
VOUT
VBATT
WP
SCL
SDA
BATT-ON
VOUT
VBATT
WP
SCL
SDA
LOWLINE
WDO
MR
RESET
VSS
5
6
7
10
9
8
5
6
7
10
9
8
PIN DESCRIPTION
Pin
Name
Function
1
V2FAIL
V2 Voltage Fail Output. This open drain output goes LOW when V2MON is less than VTRIP2 and
goes HIGH when V2MON exceeds VTRIP2. There is no power-up reset delay circuitry on this pin.
2
V2MON
V2 Voltage Monitor Input. When the V2MON input is less than the VTRIP2 voltage, V2FAIL goes
LOW. This input can monitor an unregulated power supply with an external resistor divider or can
monitor a second power supply with no external components. Connect V2MON to VSS or V when
CC
not used.
3
4
5
LOWLINE Early Low VCC Detect. This open drain output signal goes LOW when V < VTRIP1.
CC
When V > VTRIP1, this pin is pulled high with the use of an external pull up resistor.
CC
WDO
MR
WDO Output. WDO is an active LOW, open drain output which goes active whenever the watchdog
timer goes active.
Manual Reset Input. Pulling the MR pin LOW initiates a system reset. The RESET/RESET pin will remain
HIGH/LOW until the pin is released and for the tPURST thereafter. It has an internal pull up resistor.
FN8117 Rev 1.00
May 25, 2006
Page 3 of 25
X40420, X40421
PIN DESCRIPTION (Continued)
Pin
Name
Function
6
RESET/
RESET
RESET Output. (X40421) This open drain pin is an active LOW output which goes LOW whenever
VCC falls below VTRIP1 voltage or if manual reset is asserted. This output stays active for the pro-
grammed time period (tPURST) on power-up. It will also stay active until manual reset is released and
for tPURST thereafter.
RESET Output. (X40420) This pin is an active HIGH open drain output which goes HIGH whenever
VCC falls below VTRIP1 voltage or if manual reset is asserted. This output stays active for the pro-
grammed time period (tPURST) on power-up. It will also stay active until manual reset is released and
for tPURST thereafter.
7
8
VSS
Ground
SDA
Serial Data. SDA is a bidirectional pin used to transfer data into and out of the device. It has an open
drain output and may be wire ORed with other open drain or open collector outputs. This pin requires
a pull up resistor and the input buffer is always active (not gated).
Watchdog Input. A HIGH to LOW transition on the SDA (while SCL is toggled from HIGH to LOW
and followed by a stop condition) restarts the Watchdog timer. The absence of this transition within
the watchdog time out period results in WDO going active.
9
SCL
WP
Serial Clock. The Serial Clock controls the serial bus timing for data input and output.
10
Write Protect. WP HIGH prevents writes to any location in the device (including all the registers). It
has an internal pull down resistor. (>10M typical)
11
12
VBATT
Battery Supply Voltage. This input provides a backup supply in the event of a failure of the
primary VCC voltage. The VBATT voltage typically provides the supply voltage necessary to
maintain the contents of SRAM and also powers the internal logic to “stay awake.” If the battery is not
used, connect VBATT to ground.
VOUT
Output Voltage. (V)
VOUT = VCC if VCC > VTRIP1
IF VCC < VTRIP1
.
then VOUT = VCC if VCC > VBATT + 0.03V
else VOUT = VBATT (ie if VCC < VBATT - 0.03V)
Note: There is hysteresis around VBATT ± 0.03V point to avoid oscillation at or near the
switchover voltage. A capacitance of 0.1µF must be connected to VOUT to ensure stability.
13
14
BATT-ON Battery On. This CMOS output goes HIGH when the VOUT switches to VBATT and goes LOW when
VOUT switches to VCC. It is used to drive an external PNP pass transistor when VCC = VOUT and current
requirements are greater than 50mA.
The purpose of this output is to drive an external transistor to get higher operating currents when the
V
CC supply is fully functional. In the event of a VCC failure, the battery voltage is applied to the VOUT
pin and the external transistor is turned off. In this “backup condition,” the battery only needs to supply
enough voltage and current to keep SRAM devices from losing their data–there is no communication
at this time.
VCC
Supply Voltage
FN8117 Rev 1.00
May 25, 2006
Page 4 of 25
X40420, X40421
PRINCIPLES OF OPERATION
Power-on Reset
Low Voltage V2 Monitoring
The X40420, X40421 also monitors a second voltage level
and asserts V2FAIL if the voltage falls below a preset mini-
Applying power to the X40420, X40421 activates a
Power-on Reset Circuit that pulls the RESET/RESET
pins active. This signal provides several benefits.
mum V
. The V2FAIL signal is either ORed with
TRIP2
RESET to prevent the microprocessor from operating in a
power fail or brownout condition or used to interrupt the
microprocessor with notification of an impending power fail-
ure. The V2FAIL signal remains active until the V drops
below 1V (V falling). It also remains active until V2MON
– It prevents the system microprocessor from starting to
operate with insufficient voltage.
CC
CC
– It prevents the processor from operating prior to stabi-
lization of the oscillator.
returns and exceeds V
.
TRIP2
V2MON voltage monitor is powered by V
If V and
CC
OUT.
– It allows time for an FPGA to download its configura-
tion prior to initialization of the circuit.
V
go away, V2MON cannot be monitored.
BATT
– It prevents communication to the EEPROM, greatly
reducing the likelihood of data corruption on power-up.
Figure 2. Two Uses of Multiple Voltage Monitoring
VOUT
When V
exceeds the device V
(selectable) the circuit releases the RESET
threshold value
TRIP1
CC
X40420
for t
PURST
(X40421) and RESET (X40420) pin allowing the system
to begin operation.
5V
Unreg.
Supply
VCC
System
Reset
Reg
RESET
V2MON
V2FAIL
R
Figure 1. Connecting a Manual Reset Push-Button
R
X40420, X40421
System
Reset
Resistors selected so 3V appears on V2MON when unregulated
supply reaches 6V.
RESET
VOUT
MR
Manual
Reset
X40421
Unreg.
Supply
5V
Reg
VCC
RESET
V2FAIL
System
Reset
3V
Reg
V2MON
Manual Reset
By connecting a push-button directly from MR to ground,
the designer adds manual system reset capability. The
MR pin is LOW while the push-button is closed and
RESET/RESET pin remains LOW for tPURST or till the
Notice: No external components required to monitor two voltages.
push-button is released and for t
weak pull up resistor is connected to the MR pin.
thereafter. A
PURST
WATCHDOG TIMER
The Watchdog Timer circuit monitors the microproces-
sor activity by monitoring the SDA and SCL pins. A stan-
dard read or write sequence to any slave address byte
restarts the watchdog timer and prevents the WDO sig-
nal to go active. A minimum sequence to reset the
watchdog timer requires four microprocessor instruc-
tions namely, a Start, Clock Low, Clock High and Stop.
The state of two nonvolatile control bits in the Status
Register determine the watchdog timer period. The
microprocessor can change these watchdog bits by writ-
ing to the X40420, X40421 control register.
Low Voltage V1 Monitoring
During operation, the X40420, X40421 monitors the V
CC
level and asserts RESET if supply voltage falls below a
preset minimum V . The RESET signal prevents the
TRIP1
microprocessor from operating in a power fail or brown-
out condition. The V1FAIL signal remains active until the
voltage drops below 1V. It also remains active until V
CC
returns and exceeds V
for tPURST.
TRIP1
FN8117 Rev 1.00
May 25, 2006
Page 5 of 25
X40420, X40421
Figure 3. V
Set/Reset Conditions
TRIPX
V
(X = 1, 2)
V
/V2MON
TRIPX
CC
V
P
WDO
0
7
0
7
0
7
SCL
SDA
t
WC
A0h
00h
Figure 4. Watchdog Restart
To check if the V
has been set, set VXMON to a value
TRIPX
slightly greater than V
Slowly ramp down VXMON and observe when the corre-
sponding outputs (LOWLINE and V2FAIL) switch. The volt-
(that was previously set).
TRIPX
.6µs
1.3µs
SCL
SDA
age at which this occurs is the V
(actual).
TRIPX
CASE A
Start
Stop
WDT Reset
Now if the desired V
is greater than the V
TRIPX
TRIPX
(actual), then add the difference between V
(desired)
V1 AND V2 THRESHOLD PROGRAM PROCEDURE
(OPTIONAL)
TRIPX
- V
(actual) to the original V
desired. This is your
TRIPX
TRIPX
new V
that should be applied to VXMON and the
TRIPX
The X40420, X40421 is shipped with standard V1 and V2
whole sequence should be repeated again (see Figure 5).
threshold (V
V
) voltages. These values will not
TRIP1, TRIP2
change over normal operating and storage conditions.
However, in applications where the standard thresholds
are not exactly right, or if higher precision is needed in the
threshold value, the X40420 trip points may be adjusted.
The procedure is described below, and uses the applica-
tion of a high voltage control signal.
CASE B
Now if the V
(actual), is higher than the V
TRIPX
TRIPX
(desired), perform the reset sequence as described in the
next section. The new V voltage to be applied to
VXMON will now be: V
TRIPX
(desired) - (V
(actual) -
TRIPX
TRIPX
V
(desired)).
TRIPX
Setting a V
Voltage (x = 1, 2)
TRIPx
Note: 1. This operation does not corrupt the memory array.
2. Set V = 5V, when V is being programmed
There are two procedures used to set the threshold volt-
ages (V ), depending if the threshold voltage to be
CC
TRIP2
TRIPx
stored is higher or lower than the present value. For exam-
ple, if the present V is 2.9 V and the new V is 3.2
Setting a Lower V
Voltage (x = 1, 2)
TRIPx
TRIPx
TRIPx
In order to set V
to a lower voltage than the present
must first be “reset” according to the
TRIPx
V, the new voltage can be stored directly into the V
TRIPx
value, then V
TRIPx
cell. If however, the new setting is to be lower than the
procedure described in the following section. Once
has been “reset”, then V can be set to the
present setting, then it is necessary to “reset” the V
voltage before setting the new value.
TRIPx
V
TRIPx
TRIPx
desired voltage using the procedure described in “Set-
ting a Higher V Voltage”.
Setting a Higher V
Voltage (x = 1, 2)
TRIPx
TRIPx
To set a V
threshold to a new voltage which is higher
TRIPx
Resetting the V
Voltage
TRIPx
than the present threshold, the user must apply the desired
threshold voltage to the corresponding input pin
To reset a V
voltage, apply the programming voltage
V
TRIPx
TRIPx
(Vp) to the WDO pin before a START condition is set up on
SDA. Next, issue on the SDA pin the Slave Address A0h
followed by the Byte Address 03h for V
(Vcc(V1MON) or V2MON). Then, a program-ming voltage
(Vp) must be applied to the WDO pin before a START
condition is set up on SDA. Next, issue on the SDA pin the
Slave Address A0h, followed by the Byte Address 01h for
and 0Bh for
TRIP1
V
V
, followed by 00h for the Data Byte in order to reset
. The STOP bit following a valid write operation initi-
TRIP2
V
, and 09h for V
, and a 00h Data Byte in order to
TRIPx
TRIP1
TRIP2
ates the programming sequence. Pin WDO must then be
brought LOW to complete the operation.
program V
. The STOP bit following a valid write
TRIPx
operation initiates the programming sequence. Pin WDO
must then be brought LOW to complete the operation.
FN8117 Rev 1.00
May 25, 2006
Page 6 of 25
X40420, X40421
After being reset, the value of V
value of 1.7V or lesser.
becomes a nominal
TRIPx
Condition
Mode of Operation
Normal Operation
VCC > VTRIP1
Note: This operation does not corrupt the memory array.
VCC > VTRIP1
VBATT = 0
&
Normal Operation without battery
backup capability
System Battery Switch
0 VCC VTRIP1
and VCC < VBATT signal is asserted. No communica-
tion to the device is allowed.
Battery Backup mode; RESET
As long as V exceeds the low voltage detect threshold
CC
V
, V
is connected to V
through a 5 (typical)
TRIP
OUT
CC
switch. When the V has fallen below V1
, then V is
CC
CC
TRIP
applied to V
if V is or equal to or greater than V -
Control Register
OUT
CC
BATT
0.03V. When V drops to less than V
- 0.03V, then
CC
BATT
The Control Register provides the user a mechanism for
changing the Block Lock and Watchdog Timer settings.
The Block Lock and Watchdog Timer bits are nonvolatile
and do not change when power is removed.
V
is connected to V
through an 80 (typical)
OUT
BATT
switch. V
typically supplies the system static RAM volt-
OUT
age, so the switchover circuit operates to protect the con-
tents of the static RAM during a power failure. Typically,
The Control Register is accessed with a special preamble
in the slave byte (1011) and is located at address 1FFh. It
can only be modified by performing a byte write operation
directly to the address of the register and only one data
byte is allowed for each register write operation. Prior to
writing to the Control Register, the WEL and RWEL bits
must be set using a two step process, with the whole
sequence requiring 3 steps. See "Writing to the Control
Registers" on page 9.
when V
has failed, the SRAMs go into a lower power
CC
state and draw much less current than in their active mode.
When V returns, V switches back to V when V
CC
exceeds V
around this battery switch threshold to prevent oscillations
between supplies.
CC
OUT
CC
+ 0.03V. There is a 60mV hysteresis
BATT
While V is connected to V
the BATT-ON pin is pulled
CC
OUT
LOW. The signal can drive an external PNP transistor to
provide additional current to the external circuits during nor-
mal operation.
The user must issue a stop, after sending this byte to the
register, to initiate the nonvolatile cycle that stores WD1,
WD0, PUP1, PUP0, and BP. The X40420 will not
acknowledge any data bytes written after the first byte is
entered.
Operation
The device is in normal operation with V
as long as
CC
V
> V
. It switches to the battery backup mode
CC
TRIP1
The state of the Control Register can be read at any time
by performing a random read at address 01Fh, using the
special preamble. Only one byte is read by each register
read operation. The master should supply a stop condition
to be consistent with the bus protocol, but a stop is not
required to end this operation.
when V goes away.
CC
7
6
5
4
3
2
1
0
PUP1 WD1 WD0
BP
0
RWEL WEL PUP0
RWEL: Register Write Enable Latch (Volatile)
The RWEL bit must be set to “1” prior to a write to the
Control Register.
Figure 5. Sample V
Reset Circuit
TRIP
VP
Adjust
V2FAIL
RESET
µC
1
6
2
7
14
13
X40420
Run
9
8
VTRIP1
Adj.
SCL
SDA
VTRIP2
Adj.
4.7K
FN8117 Rev 1.00
May 25, 2006
Page 7 of 25
X40420, X40421
Figure 6. V
Set/Reset Sequence (X = 1, 2)
TRIPX
Vx = VCC, VxMON
Note: X = 1, 2
VTRIPX Programming
Let: MDE = Maximum Desired Error
Desired
VTRIPX
Present Value
No
<
MDE+
Acceptable
Desired Value
YES
Error Range
MDE–
Execute
TRIPX Reset Sequence
V
Error = Actual - Desired
Set VX = desired VTRIPX
New VX applied =
Old VX applied + | Error |
Execute
Set Higher VX Sequence
New VX applied =
Old VX applied - | Error |
Apply VCC and Voltage
Execute Reset VTRIPX
Sequence
> Desired VTRIPX to
VX
NO
Decrease
VX
Output Switches?
YES
V
Error < MDE–
Error > MDE+
Actual
TRIPX -
VTRIPX
Desired
| Error | < | MDE |
DONE
WEL: Write Enable Latch (Volatile)
Once set, WEL remains set until either it is reset to 0 (by
writing a “0” to the WEL bit and zeroes to the other bits
of the control register) or until the part powers up again.
Writes to the WEL bit do not cause a high voltage write
cycle, so the device is ready for the next operation
immediately after the stop condition.
The WEL bit controls the access to the memory and to
the Register during a write operation. This bit is a volatile
latch that powers up in the LOW (disabled) state. While
the WEL bit is LOW, writes to any address, including any
control registers will be ignored (no acknowledge will be
issued after the Data Byte). The WEL bit is set by writing
a “1” to the WEL bit and zeroes to the other bits of the
control register.
FN8117 Rev 1.00
May 25, 2006
Page 8 of 25
X40420, X40421
BP: Block Protect Bit (Nonvolatile)
– Write a one byte value to the Control Register that has
all the control bits set to the desired state. The Control
register can be represented as qxys 001r in binary,
where xy are the WD bits, and st are the BP bits and
qr are the power-up bits. This operation proceeded by
a start and ended with a stop bit. Since this is a non-
volatile write cycle it will take up to 10ms to complete.
The RWEL bit is reset by this cycle and the sequence
must be repeated to change the nonvolatile bits again.
If bit 2 is set to ‘1’ in this third step (qxys 011r) then the
RWEL bit is set, but the WD1, WD0, PUP1, PUP0, and
BP bits remain unchanged. Writing a second byte to
the control register is not allowed. Doing so aborts the
write operation and returns a NACK.
The Block Protect Bits BP determines which blocks of
the array are write protected. A write to a protected block
of memory is ignored. The block protect bit will prevent
write operations to half the array segment.
Protected Addresses
(Size)
Memory
Array Lock
0
1
None
None
100h – 1FFh (256 bytes)
Upper Half of
Memory Array
PUP1, PUP0: Power-uppower-up Bits (Nonvolatile)
The Power-up bits, PUP1 and PUP0, determine the
tPURST time delay. The nominal power-up times are
shown in the following table.
– A read operation occurring between any of the previ-
ous operations will not interrupt the register write oper-
ation.
PUP1 PUP0
Power-on Reset Delay (tPURST)
– The RWEL bit cannot be reset without writing to the
nonvolatile control bits in the control register, power
cycling the device or attempting a write to a write pro-
tected block.
0
0
1
1
0
1
0
1
50ms
200ms (default)
400ms
To illustrate, a sequence of writes to the device consist-
ing of [02H, 06H, 02H] will reset all of the nonvolatile bits
in the Control Register to 0. A sequence of [02H, 06H,
06H] will leave the nonvolatile bits unchanged and the
RWEL bit remains set.
800ms
WD1, WD0: Watchdog Timer Bits
The bits WD1 and WD0 control the period of the Watch-
dog Timer. The options are shown below.
Note: 1. t
is set to 200ms as factory default.
PURST
2. Watchdog timer bits are shipped disabled.
WD1
WD0
Watchdog Time Out Period
1.4 seconds
0
0
1
1
0
1
0
1
Fault Detection Register (FDR)
200 milliseconds
The Fault Detection Register provides the user the sta-
tus of what causes the system reset active. The Manual
Reset Fail, Watchdog Timer Fail and Three Low Voltage
Fail bits are volatile
25 milliseconds
disabled (factory default)
Writing to the Control Registers
7
6
5
4
3
2
1
0
Changing any of the nonvolatile bits of the control and
trickle registers requires the following steps:
LV1F LV2F
0
WDF MRF
0
0
0
– Write a 02H to the Control Register to set the Write
Enable Latch (WEL). This is a volatile operation, so
there is no delay after the write. (Operation preceded
by a start and ended with a stop).
The FDR is accessed with a special preamble in the
slave byte (1011) and is located at address 0FFh. It can
only be modified by performing a byte write operation
directly to the address of the register and only one data
byte is allowed for each register write operation.
– Write a 06H to the Control Register to set the Register
Write Enable Latch (RWEL) and the WEL bit. This is
also a volatile cycle. The zeros in the data byte are
required. (Operation proceeded by a start and ended
with a stop).
There is no need to set the WEL or RWEL in the control
register to access this fault detection register.
FN8117 Rev 1.00
May 25, 2006
Page 9 of 25
X40420, X40421
Figure 7. Valid Data Changes on the SDA Bus
SCL
SDA
Data Stable
Data Change
Data Stable
At power-up, the Fault Detection Register is defaulted
to all “0”. The system needs to initialize this register to
all “1” before the actual monitoring take place. In the
event of any one of the monitored sources failed. The
corresponding bits in the register will change from a
“1” to a “0” to indicate the failure. At this moment, the
system should perform a read to the register and
noted the cause of the reset. After reading the register
the system should reset the register back to all “1”
again. The state of the Fault Detection Register can be
read at any time by performing a random read at
address 0FFh, using the special preamble.
Interface Conventions
The device supports a bidirectional bus oriented proto-
col. The protocol defines any device that sends data
onto the bus as a transmitter, and the receiving device
as the receiver. The device controlling the transfer is
called the master and the device being controlled is
called the slave. The master always initiates data
transfers, and provides the clock for both transmit and
receive operations. Therefore, the devices in this fam-
ily operate as slaves in all applications.
Serial Clock and Data
Data states on the SDA line can change only during
SCL LOW. SDA state changes during SCL HIGH are
reserved for indicating start and stop conditions. See
Figure 7.
The FDR can be read by performing a random read at
0FFh address of the register at any time. Only one
byte of data is read by the register read operation.
MRF: Manual Reset Fail Bit (Volatile)
Serial Start Condition
The MRF bit will set to “0” when Manual Reset input
goes active.
All commands are preceded by the start condition,
which is a HIGH to LOW transition of SDA when SCL
is HIGH. The device continuously monitors the SDA
and SCL lines for the start condition and will not
respond to any command until this condition has been
met. See Figure 8.
WDF: Watchdog Timer Fail Bit (Volatile)
The WDF bit will set to “0” when WDO goes active.
LV1F: Low V Reset Fail Bit (Volatile)
CC
The LV1F bit will be set to “0” when V
(V1MON)
CC
Serial Stop Condition
falls below V
.
TRIP1
All communications must be terminated by a stop con-
dition, which is a LOW to HIGH transition of SDA when
SCL is HIGH. The stop condition is also used to place
the device into the Standby power mode after a read
sequence. A stop condition can only be issued after the
transmitting device has released the bus. See Figure 8.
LV2F: Low V2MON Reset Fail Bit (Volatile)
The LV2F bit will be set to “0” when V2MON falls
below V
.
TRIP2
FN8117 Rev 1.00
May 25, 2006
Page 10 of 25
X40420, X40421
Figure 8. Valid Start and Stop Conditions
SCL
SDA
Start
Stop
Serial Acknowledge
The master must then issue a stop condition to return
the device to Standby mode and place the device into a
known state.
Acknowledge is a software convention used to indicate
successful data transfer. The transmitting device, either
master or slave, will release the bus after transmitting
eight bits. During the ninth clock cycle, the receiver will
pull the SDA line LOW to acknowledge that it received
the eight bits of data. See Figure 9.
Serial Write Operations
Byte Write
For a write operation, the device requires the Slave
Address Byte and a Word Address Byte. This gives the
master access to any one of the words in the array. After
receipt of the Word Address Byte, the device responds
with an acknowledge, and awaits the next eight bits of
data. After receiving the 8 bits of the Data Byte, the
device again responds with an acknowledge. The mas-
ter then terminates the transfer by generating a stop
condition, at which time the device begins the internal
write cycle to the nonvolatile memory. During this internal
write cycle, the device inputs are disabled, so the device
will not respond to any requests from the master. The SDA
output is at high impedance. See Figure 12.
The device will respond with an acknowledge after rec-
ognition of a start condition and if the correct Device
Identifier and Select bits are contained in the Slave
Address Byte. If a write operation is selected, the device
will respond with an acknowledge after the receipt of
each subsequent eight bit word. The device will
acknowledge all incoming data and address bytes,
except for the Slave Address Byte when the Device
Identifier and/or Select bits are incorrect.
In the read mode, the device will transmit eight bits of
data, release the SDA line, then monitor the line for an
acknowledge. If an acknowledge is detected and no stop
condition is generated by the master, the device will con-
tinue to transmit data. The device will terminate further
data transmissions if an acknowledge is not detected.
A write to a protected block of memory will suppress the
acknowledge bit.
Figure 9. Acknowledge Response From Receiver
SCL from
Master
1
8
9
Data Output
from
Data Output
from Receiver
Start
Acknowledge
FN8117 Rev 1.00
May 25, 2006
Page 11 of 25
X40420, X40421
Figure 10. Byte Write Sequence
S
t
a
r
S
t
o
p
Signals from
the Master
Byte
Address
Slave
Address
Data
t
SDA Bus
0
A
C
K
A
C
K
A
C
K
Signals from
the Slave
Page Write
This means that the master can write 16 bytes to the page
starting at any location on that page. If the master begins
writing at location 10, and loads 12 bytes, then the first 6
bytes are written to locations 10 through 15, and the last 6
bytes are written to locations 0 through 5. Afterwards, the
address counter would point to location 6 of the page that
was just written. If the master supplies more than 16 bytes
of data, then new data over-writes the previous data, one
byte at a time.
The device is capable of a page write operation. It is initi-
ated in the same manner as the byte write operation; but
instead of terminating the write cycle after the first data
byte is transferred, the master can transmit an unlimited
number of 8-bit bytes. After the receipt of each byte, the
device will respond with an acknowledge, and the
address is internally incremented by one. The page
address remains constant. When the counter reaches
the end of the page, it “rolls over” and goes back to ‘0’ on
the same page.
Figure 11. Page Write Operation
(1 n 16)
S
S
t
o
p
t
a
r
Signals from
the Master
Byte
Address
Slave
Address
Data
(1)
Data
(n)
t
SDA Bus
1 0 1
0 0
0
A
C
K
A
C
K
A
C
K
A
C
K
Signals from
the Slave
Figure 12. Writing 12 bytes to a 16-byte Page Starting at Location 10
6 Bytes
6 Bytes
address pointer
ends here
Addr = 6
address
10
address
= 5
address
n-1
The master terminates the Data Byte loading by issuing a
stop condition, which causes the device to begin the non-
volatile write cycle. As with the byte write operation, all
inputs are disabled until completion of the internal write
cycle. See Figure 11 for the address, acknowledge, and
data transfer sequence.
FN8117 Rev 1.00
May 25, 2006
Page 12 of 25
X40420, X40421
Stops and Write Modes
Figure 13. Acknowledge Polling Sequence
Stop conditions that terminate write operations must be
sent by the master after sending at least 1 full data byte
plus the subsequent ACK signal. If a stop is issued in the
middle of a data byte, or before 1 full data byte plus its
associated ACK is sent, then the device will reset itself
without performing the write. The contents of the array
will not be effected.
Byte Load Completed
by Issuing STOP.
Enter ACK Polling
Issue START
Acknowledge Polling
Issue Slave Address
Byte (Read or Write)
Issue STOP
The disabling of the inputs during high voltage cycles
can be used to take advantage of the typical 5ms write
cycle time. Once the stop condition is issued to indicate
the end of the master’s byte load operation, the device
initiates the internal high voltage cycle. Acknowledge
polling can be initiated immediately. To do this, the mas-
ter issues a start condition followed by the Slave
Address Byte for a write or read operation. If the device
is still busy with the high voltage cycle then no ACK will
be returned. If the device has completed the write opera-
tion, an ACK will be returned and the host can then pro-
ceed with the read or write operation. See Figure 13.
NO
ACK
Returned?
YES
High Voltage Cycle
Complete. Continue
Command Sequence?
Issue STOP
NO
YES
Serial Read Operations
Continue Normal
Read or Write
Command Sequence
Read operations are initiated in the same manner as
write operations with the exception that the R/W bit of
the Slave Address Byte is set to one. There are three
basic read operations: Current Address Reads, Random
Reads, and Sequential Reads.
PROCEED
Current Address Read
It should be noted that the ninth clock cycle of the read
operation is not a “don’t care.” To terminate a read oper-
ation, the master must either issue a stop condition
during the ninth cycle or hold SDA HIGH during the ninth
clock cycle and then issue a stop condition.
Internally the device contains an address counter that
maintains the address of the last word read incremented
by one. Therefore, if the last read was to address n, the
next read operation would access data from address
n+1. On power-up, the address of the address counter is
undefined, requiring a read or write operation for initial-
ization.
Random Read
Random read operation allows the master to access any
memory location in the array. Prior to issuing the Slave
Address Byte with the R/W bit set to one, the master must
first perform a “dummy” write operation. The master issues
the start condition and the Slave Address Byte, receives an
acknowledge, then issues the Word Address Bytes. After
acknowledging receipts of the Word Address Bytes, the
master immediately issues another start condition and the
Slave Address Byte with the R/W bit set to one. This is fol-
lowed by an acknowledge from the device and then by the
eight bit word. The master terminates the read operation by
not responding with an acknowledge and then issuing a
stop condition. See Figure 15 for the address, acknowl-
edge, and data transfer sequence.
Upon receipt of the Slave Address Byte with the R/W bit
set to one, the device issues an acknowledge and then
transmits the eight bits of the Data Byte. The master ter-
minates the read operation when it does not respond
with an acknowledge during the ninth clock and then
issues a stop condition. See Figure 14 for the address,
acknowledge, and data transfer sequence.
FN8117 Rev 1.00
May 25, 2006
Page 13 of 25
X40420, X40421
A similar operation called “Set Current Address” where
the device will perform this operation if a stop is issued
instead of the second start is shown in Figure 15. The
device will go into standby mode after the stop and all
bus activity will be ignored until a start is detected. This
operation loads the new address into the address
counter. The next Current Address Read operation will
read from the newly loaded address. This operation
could be useful if the master knows the next address it
needs to read, but is not ready for the data.
SERIAL DEVICE ADDRESSING
Memory Address Map
CR, Control Register, CR7: CR0
Address: 1FF
hex
FDR, Fault DetectionRegister, FDR7: FDR0
Address: 0FF
hex
General Purpose Memory Organization, A8:A0
Address: 00h to 1FFh
Sequential Read
General Purpose Memory Array Configuration
Sequential reads can be initiated as either a current
address read or random address read. The first Data Byte
is transmitted as with the other modes; however, the mas-
ter now responds with an acknowledge, indicating it
requires additional data. The device continues to output
data for each acknowledge received. The master termi-
nates the read operation by not responding with an
acknowledge and then issuing a stop condition.
Memory Address
A8:A0
000h
Lower 256 bytes
0FFh
100h
Upper 256 bytes
Block Protect Option
1FFh
Slave Address Byte
The data output is sequential, with the data from address
n followed by the data from address n + 1. The address
counter for read operations increments through all page
and column addresses, allowing the entire memory con-
tents to be serially read during one operation. At the end
of the address space the counter “rolls over” to address
Following a start condition, the master must output a
Slave Address Byte. This byte consists of several parts:
– a device type identifier that is always “1010” when
accessing the array and “1011” when accessing the
control register and fault detection register.
0000 and the device continues to output data for each
H
– two bits of “0”.
acknowledge received. See Figure 17 for the acknowl-
edge and data transfer sequence.
– one bit that becomes the MSB of the memory address
X .
4
– last bit of the slave command byte is a R/W bit. The
R/W bit of the Slave Address Byte defines the opera-
tion to be performed. When the R/W bit is a one, then
a read operation is selected. A zero selects a write
operation. See Figure 16.
Figure 14. Current Address Read Sequence
S
Slave
Address
t
a
r
S
t
o
p
Signals from
the Master
t
SDA Bus
1 0 1
0 0
1
A
Signals from
the Slave
C
Data
K
FN8117 Rev 1.00
May 25, 2006
Page 14 of 25
X40420, X40421
Figure 15. Random Address Read Sequence
S
S
t
S
t
o
p
t
a
r
Slave
Address
Byte
Address
Slave
Address
Signals from
the Master
a
r
t
t
SDA Bus
1
1 0 1 0 0
0
A
C
K
A
C
K
A
C
K
Signals from
the Slave
Data
Figure 16. X40410/11 Addressing
Slave Byte
General Purpose Memory
Control Register
1
1
1
0
0
0
1
1
1
0
1
1
0
0
0
0
R/W
R/W
R/W
A8
1
0
0
0
Fault Detection Register
Word Address
General Purpose Memory
Control Register
A0
1
A7 A6 A5 A4 A3 A2 A1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Fault Detection Register
1
Word Address
Data Protection
The word address is either supplied by the master or
obtained from an internal counter.
The following circuitry has been included to prevent
inadvertent writes:
– The WEL bit must be set to allow write operations.
Operational Notes
– The proper clock count and bit sequence is required
prior to the stop bit in order to start a nonvolatile write
cycle.
The device powers-up in the following state:
– The device is in the low power standby state.
– The WEL bit is set to ‘0’. In this state it is not possible
to write to the device.
– A three step sequence is required before writing into
the Control Register to change Watchdog Timer or
Block Lock settings.
– SDA pin is the input mode.
– The WP pin, when held HIGH, prevents all writes to
the array and all the Register.
– RESET/RESET Signal is active for tPURST
.
Figure 17. Sequential Read Sequence
S
t
Slave
Address
Signals from
the Master
o
A
C
K
A
C
K
A
C
K
p
SDA Bus
1
A
C
K
Signals from
the Slave
Data
(2)
Data
(n-1)
Data
(1)
Data
(n)
(n is any integer greater than 1)
FN8117 Rev 1.00
May 25, 2006
Page 15 of 25
X40420, X40421
ABSOLUTE MAXIMUM RATINGS
COMMENT
Temperature under bias.................... -65°C to +135°C
Storage temperature ......................... -65°C to +150°C
Voltage on any pin with
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only; functional operation of the
device (at these or any other conditions above those
listed in the operational sections of this specification) is
not implied. Exposure to absolute maximum rating condi-
tions for extended periods may affect device reliability.
respect to V ...................................... -1.0V to +7V
SS
D.C. output current...............................................5mA
Lead temperature (soldering, 10s) .................... 300°C
RECOMMENDED OPERATING CONDITIONS
Temperature
Commercial
Industrial
Min.
0°C
Max.
70°C
Monitored
Version ChipSupplyVoltage
Voltages*
2.6 to 5.5V
1.6V to 3.6V
-A or -B
-C
2.7V to 5.5V
2.7V to 5.5V
-40°C
+85°C
*See ordering Info
D.C. OPERATING CHARACTERISTICS
(Over the recommended operating conditions unless otherwise specified)
(5)
Symbol
Parameter
Active Supply Current (V ) Read
Min.
Typ.
Max.
Unit
Test Conditions
(1)
ICC1
1.5
mA
VIL = V x 0.1
CC
CC
(Excludes IOUT
)
VIH = V x 0.9,
CC
(1)
fSCL = 400kHz
ICC2
Active Supply Current (V ) Write Non
3.0
10
mA
CC
Volatile Memory (Excludes IOUT
)
(1)(7)
ISB1
Standby Current (V ) AC (WDT off)
6
µA VIL = V x 0.1
CC
CC
VIH = V x 0.9
CC
fSCL, fSDA = 400kHz
(2)(7)
ISB2
Standby Current (V ) DC (WDT on)
25
30
µA VSDA = VSCL = V
CC
CC
Others = GND or V
CC
(3)(7)
IBATT1
VBATT Current (Excludes IOUT
)
0.4
1
6
µA VOUT = V
CC
µA VBATT = 2.8V
VOUT = Open
(7)
IBATT2
VBATT Current (Excludes IOUT
(Battery Backup Mode)
)
(7)
VOUT1
Output Voltage (VCC > VBATT + 0.03V or
VCC > VTRIP1
V
CC-0.05V
V
IOUT = 5mA (4.5-5.5V)
IOUT = 50mA (4.5-5.5V)
)
VCC-0.5V
(7)
VOUT2
Output Voltage (VCC < VBATT – 0.03V and
VCC < VTRIP1) {Battery Backup}
VBATT-0.2
V
IOUT = 250µA
VOLB
VOHB
Output (BATT-ON) LOW Voltage
Output (BATT-ON) HIGH Voltage
Battery Switch Hysteresis
0.4
V
V
IOL = 3.0mA (4.5-5.5V)
IOH = -0.4mA (4.5-5.5V)
VOUT-0.8
(7)
VBSH
30
-30
mV Power-up
Power-down
(VCC < VTRIP1
)
ILI
Input Leakage Current (SCL, MR, WP)
10
10
µA VIL = GND to V
CC
ILO
Output Leakage Current (SDA, V2FAIL,
WDO, RESET)
µA
VSDA = GND to V
CC
Device is in Standby(2)
(3)
VIL
Input LOW Voltage (SDA, SCL, MR, WP)
Input HIGH Voltage (SDA, SCL, MR, WP)
-0.5
x 0.7
V
x 0.3
V
V
CC
(3)
VIH
V
V
+ 0.5
CC
CC
FN8117 Rev 1.00
May 25, 2006
Page 16 of 25
X40420, X40421
D.C. OPERATING CHARACTERISTICS (Continued)
(Over the recommended operating conditions unless otherwise specified)
(5)
Symbol
Parameter
Min.
Typ.
Max.
Unit
Test Conditions
(7)
VHYS
Schmitt Trigger Input Hysteresis
• Fixed input level
0.2
.05 x V
V
V
• V related level
CC
CC
VOL
Output LOW Voltage (SDA, RESET/
RESET, LOWLINE, V2FAIL, WDO)
0.4
V
I
OL = 3.0mA (2.7-5.5V)
IOL = 1.8mA (2.4-3.6V)
V
CC Supply
(6)
VTRIP1
V
Reset Trip Point Voltage Range
2.0
4.75
4.65
2.95
5
V
CC
4.55
2.85
4.6
2.9
A, B Version
C Version
(7)
tRPDL
µS
V
VTRIP1 to LOWLINE
Second Supply Monitor
(6)
VTRIP2
V2MON Reset Trip Point Voltage Range
0.9
3.5
2.95
2.65
1.65
5
2.85
2.55
1.55
2.9
2.6
1.6
A Version
B Version
C Version
(7)
tRPD2
µS
VTRIP2 to V2FAIL
Notes: (1) The device enters the Active state after any start, and remains active until: 9 clock cycles later if the Device Select Bits in the Slave
Address Byte are incorrect; 200ns after a stop ending a read operation; or tWC after a stop ending a write operation.
(2) The device goes into Standby: 200ns after any stop, except those that initiate a high voltage write cycle; tWC after a stop that initiates a
high voltage cycle; or 9 clock cycles after any start that is not followed by the correct Device Select Bits in the Slave Address Byte.
(3) Negative numbers indicate charging current, positive numbers indicate discharge current.
(4) VIL Min. and VIH Max. are for reference only and are not tested.
(5) At 25°C, VCC = 3V.
(6) See ordering information for standard programming levels. For custom programming levels, contact factory.
(7) Based on characterization data only.
EQUIVALENT INPUT CIRCUIT FOR VxMON (x = 1, 2)
V = 100mV
R
V
VREF
VxMON
+
–
Output
VREF
C
tRPDX = 5µs worst case
FN8117 Rev 1.00
May 25, 2006
Page 17 of 25
X40420, X40421
CAPACITANCE
Symbol
Parameter
Max.
Unit
Test Conditions
OUT = 0V
(1)
COUT
Output Capacitance (SDA, RESET, RESET/LOWLINE,
V2FAIL, WDO)
8
pF
V
(1)
CIN
Input Capacitance (SCL, WP)
6
pF
VIN = 0V
Note: (1) This parameter is not 100% tested.
EQUIVALENT A.C. OUTPUT LOAD CIRCUIT FOR V
= 5V
SYMBOL TABLE
CC
WAVEFORM
INPUTS
OUTPUTS
VOUT
5V
V2MON
Must be
steady
Will be
steady
4.6k
4.6k
2.06k
May change
from LOW
Will change
from LOW
to HIGH
RESET
WDO/LOWLINE
SDA
V2FAIL
30pF
May change
from HIGH
to LOW
Will change
from HIGH
to LOW
30pF
30pF
Don’t Care:
Changes
Allowed
Changing:
State Not
Known
A.C. TEST CONDITIONS
N/A
Center Line
is High
Impedance
Input pulse levels
V
x 0.1 to V x 0.9
CC
CC
Input rise and fall times
Input and output timing levels
Output load
10ns
V
x 0.5
CC
Standard output load
FN8117 Rev 1.00
May 25, 2006
Page 18 of 25
X40420, X40421
A.C. CHARACTERISTICS
400kHz
Symbol
Parameter
Min.
Max.
Unit
kHz
ns
µs
µs
µs
µs
µs
µs
ns
µs
µs
ns
ns
ns
µs
µs
pF
fSCL
tIN
SCL Clock Frequency
400
Pulse width Suppression Time at inputs
SCL LOW to SDA Data Out Valid
Time the bus free before start of new transmission
Clock LOW Time
50
0.1
1.3
1.3
0.6
0.6
0.6
100
0
tAA
0.9
tBUF
tLOW
tHIGH
tSU:STA
tHD:STA
tSU:DAT
tHD:DAT
tSU:STO
tDH
Clock HIGH Time
Start Condition Setup Time
Start Condition Hold Time
Data In Setup Time
Data In Hold Time
Stop Condition Setup Time
Data Output Hold Time
0.6
50
tR
SDA and SCL Rise Time
SDA and SCL Fall Time
WP Setup Time
20 +.1Cb(1)
20 +.1Cb(1)
300
300
tF
tSU:WP
tHD:WP
Cb
0.6
0
WP Hold Time
Capacitive load for each bus line
400
Note: (1) Cb = total capacitance of one bus line in pF.
TIMING DIAGRAMS
Bus Timing
tF
tHIGH
tLOW
tR
SCL
SDA IN
tSU:DAT
tSU:STA
tHD:DAT
tSU:STO
tHD:STA
tAA tDH
tBUF
SDA OUT
FN8117 Rev 1.00
May 25, 2006
Page 19 of 25
X40420, X40421
WP Pin Timing
START
SCL
Clk 1
Clk 9
Slave Address Byte
SDA IN
WP
tSU:WP
tHD:WP
Write Cycle Timing
SCL
8th Bit of Last Byte
ACK
SDA
tWC
Stop
Start
Condition
Condition
Nonvolatile Write Cycle Timing
Symbol
(1)
Parameter
Write Cycle Time
Min.
Typ.
Max.
Unit
(1)
tWC
5
10
ms
Note: (1) tWC is the time from a valid stop condition at the end of a write sequence to the end of the self-timed internal nonvolatile write cycle. It is
the minimum cycle time to be allowed for any nonvolatile write by the user, unless Acknowledge Polling is used.
Power Fail Timings
VTRIPX
tRPDL
tRPDX
tRPDL
tRPDX
VCC or
tRPDL
tRPDX
V2MON
tF
tR
LOWLINE or
V2FAIL
VRVALID
X = 1, 2
FN8117 Rev 1.00
May 25, 2006
Page 20 of 25
X40420, X40421
RESET/RESET/MR Timings
VTRIP1
VCC
tPURST
tPURST
tRPD1
tF
tR
RESET
VRVALID
RESET
MR
tMD
LOW VOLTAGE AND WATCHDOG TIMINGS PARAMETERS (@25°C, VCC = 5V)
Symbol
Parameters
Min.
Typ.
Max.
Unit
(1)
tRPD1
VTRIP1 to RESET/RESET (Power-down only)
VTRIP1 to LOWLINE
5
µs
tRPDL
(1)
tLR
LOWLINE to RESET/RESET delay (Power-down only) [= tRPD1-tRPDL
]
500
ns
µs
(1)
tRPD2
VTRIP2 to V2FAIL
5
tPURST
Power-on Reset delay:
PUP1=0, PUP0=0
PUP1=0, PUP0=1 (factory default)
PUP1=1, PUP0=0
50(1)
200
ms
ms
ms
ms
400(1)
800(1)
PUP1=1, PUP0=1
tF
VCC, V2MON Fall Time
VCC, V2MON Rise Time
20
20
1
mVµs
mVµs
V
tR
VRVALID Reset Valid VCC
t MD MR to RESET/ RESET delay (activation only)
tin1
500
50
ns
Pulse width Suppression Time for MR
ns
tWDO
Watchdog Timer Period:
WD1=0, WD0=0
WD1=0, WD0=1
1.4(1)
200(1)
25
s
ms
ms
WD1=1, WD0=0
WD1=1, WD0=1 (factory default)
OFF
tRST1
Watchdog Reset Time Out Delay
WD1=0, WD0=0
100
200
300
ms
WD1=0, WD0=1
tRST2
tRSP
Watchdog Reset Time Out Delay WD1=1, WD0=0
Watchdog timer restart pulse width
12.5
1
25
37.5
ms
µs
Note: (1) Based on characterization data.
FN8117 Rev 1.00
May 25, 2006
Page 21 of 25
X40420, X40421
Watchdog Time Out For 2-Wire Interface
Start
Start
Clockin (0 or 1)
tRSP
< tWDO
SCL
SDA
tRST
tWDO
tRST
WDO
WDT
Restart
Start
Minimum Sequence to Reset WDT
SCL
SDA
V
Set/Reset Conditions
TRIPX
(VTRIPX
)
VCC/V2MON
tTHD
VP
tTSU
WDO
tVPS
tVPO
tVPH
7
SCL
SDA
0
0
7
0
7
tWC
A0h
00h
Start
resets VTRIP1
resets VTRIP2
01h*
09h*
03h*
0Bh*
sets VTRIP1
sets VTRIP2
* all others reserved
FN8117 Rev 1.00
May 25, 2006
Page 22 of 25
X40420, X40421
, V
V
Programming Specifications: V = 2.0-5.5V; Temperature = 25°C
TRIP1
TRIP2
CC
Parameter
tVPS
Description
WDO Program Voltage Setup time
WDO Program Voltage Hold time
VTRIPX Level Setup time
Min.
10
10
10
10
10
Max. Unit
µs
µs
tVPH
tTSU
µs
tTHD
VTRIPX Level Hold (stable) time
VTRIPX Program Cycle
µs
tWC
ms
ms
tVPO
Program Voltage Off time before next cycle
Programming Voltage
1
VP
15
18
4.75
3.5
V
V
VTRAN1
VTRAN2
Vtv
VTRIP1 Set Voltage Range
2.0
0.9
-25
10
VTRIP2 Set Voltage Range
V
VTRIPX Set Voltage variation after programming (0-75°C).
WDO Program Voltage Setup time
+25
mV
µs
tVPS
VTRIPX programming parameters are periodically sampled and are not 100% tested.
FN8117 Rev 1.00
May 25, 2006
Page 23 of 25
X40420, X40421
Small Outline Package Family (SO)
A
D
h X 45°
(N/2)+1
N
A
PIN #1
I.D. MARK
E1
E
c
SEE DETAIL “X”
1
(N/2)
B
L1
0.010 M
C A B
e
H
C
A2
A1
GAUGE
PLANE
SEATING
PLANE
0.010
L
4° ±4°
0.004 C
b
0.010 M
C
A
B
DETAIL X
MDP0027
SMALL OUTLINE PACKAGE FAMILY (SO)
SO16
(0.150”)
SO16 (0.300”)
(SOL-16)
SO20
SO24
(SOL-24)
SO28
(SOL-28)
SYMBOL
SO-8
0.068
0.006
0.057
0.017
0.009
0.193
0.236
0.154
0.050
0.025
0.041
0.013
8
SO-14
0.068
0.006
0.057
0.017
0.009
0.341
0.236
0.154
0.050
0.025
0.041
0.013
14
(SOL-20)
0.104
0.007
0.092
0.017
0.011
0.504
0.406
0.295
0.050
0.030
0.056
0.020
20
TOLERANCE
MAX
NOTES
A
A1
A2
b
0.068
0.006
0.057
0.017
0.009
0.390
0.236
0.154
0.050
0.025
0.041
0.013
16
0.104
0.007
0.092
0.017
0.011
0.406
0.406
0.295
0.050
0.030
0.056
0.020
16
0.104
0.007
0.092
0.017
0.011
0.606
0.406
0.295
0.050
0.030
0.056
0.020
24
0.104
0.007
0.092
0.017
0.011
0.704
0.406
0.295
0.050
0.030
0.056
0.020
28
-
0.003
0.002
0.003
0.001
0.004
0.008
0.004
Basic
-
-
-
c
-
D
1, 3
E
-
E1
e
2, 3
-
L
0.009
Basic
-
L1
h
-
Reference
Reference
-
N
-
Rev. L 2/01
NOTES:
1. Plastic or metal protrusions of 0.006” maximum per side are not included.
2. Plastic interlead protrusions of 0.010” maximum per side are not included.
3. Dimensions “D” and “E1” are measured at Datum Plane “H”.
4. Dimensioning and tolerancing per ASME Y14.5M-1994
FN8117 Rev 1.00
May 25, 2006
Page 24 of 25
X40420, X40421
Thin Shrink Small Outline Plastic Packages (TSSOP)
M14.173
N
14 LEAD THIN SHRINK SMALL OUTLINE PLASTIC
PACKAGE
INDEX
AREA
0.25(0.010)
M
B M
E
E1
-B-
INCHES
MIN
MILLIMETERS
GAUGE
PLANE
SYMBOL
MAX
0.047
0.006
0.041
0.0118
0.0079
0.199
0.177
MIN
-
MAX
1.20
0.15
1.05
0.30
0.20
5.05
4.50
NOTES
A
A1
A2
b
-
-
1
2
3
0.002
0.031
0.0075
0.0035
0.195
0.169
0.05
0.80
0.19
0.09
4.95
4.30
-
L
0.25
0.010
-
0.05(0.002)
SEATING PLANE
A
9
-A-
D
c
-
D
3
-C-
E1
e
4
A2
e
A1
0.026 BSC
0.65 BSC
-
c
b
0.10(0.004)
E
0.246
0.256
6.25
0.45
6.50
0.75
-
0.10(0.004) M
C
A M B S
L
0.0177
0.0295
6
N
14
14
7
NOTES:
0o
8o
0o
8o
-
1. These package dimensions are within allowable dimensions of
JEDEC MO-153-AC, Issue E.
Rev. 2 4/06
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm
(0.006 inch) per side.
4. Dimension “E1” does not include interlead flash or protrusions. Inter-
lead flash and protrusions shall not exceed 0.15mm (0.006 inch) per
side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “b” does not include dambar protrusion. Allowable dambar
protrusion shall be 0.08mm (0.003 inch) total in excess of “b” dimen-
sion at maximum material condition. Minimum space between protru-
sion and adjacent lead is 0.07mm (0.0027 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact. (Angles in degrees)
© Copyright Intersil Americas LLC 2005-2006. All Rights Reserved.
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For additional products, see www.intersil.com/en/products.html
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such
modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are
current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its
subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN8117 Rev 1.00
May 25, 2006
Page 25 of 25
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