X40626V14-2.7T1 [RENESAS]
IC,POWER SUPPLY SUPERVISOR,CMOS,TSSOP,14PIN,PLASTIC;
| 型号： | X40626V14-2.7T1 |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | IC,POWER SUPPLY SUPERVISOR,CMOS,TSSOP,14PIN,PLASTIC 光电二极管 |
| 文件： | 总22页 (文件大小：337K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
X40626
®
64K, 8K x 8 Bit
Data Sheet
March 28, 2005
FN8119.0
PRELIMINARY
• 2.7V to 5.5V power supply operation
• Available Packages
—14-lead SOIC
Dual Voltage CPU Supervisor with 64K
Serial EEPROM
—14-lead TSSOP
FEATURES
• Dual voltage monitoring
DESCRIPTION
—V
operates independent of V
2Mon
CC
The X40626 combines four popular functions, Power-on
Reset Control, Watchdog Timer, Dual Supply Voltage
Supervision, and Serial EEPROM Memory in one pack-
age. This combination lowers system cost, reduces
board space requirements, and increases reliability.
• Watchdog timer with selectable timeout intervals
• Low V detection and reset assertion
CC
—Four standard reset threshold voltages
—User programmable V
threshold
TRIP
—Reset signal valid to V =1V
CC
• Low power CMOS
Applying power to the device activates the power-on
reset circuit which holds RESET active for a period of
time. This allows the power supply and oscillator to stabi-
lize before the processor can execute code.
—20µA max standby current, watchdog on
—1µA standby current, watchdog OFF
• 64Kbits of EEPROM
—64 byte page size
• Built-in inadvertent write protection
—Power-up/power-down protection circuitry
—Protect 0, 1/4, 1/2, all or 64, 128, 256 or 512
bytes of EEPROM array with programmable
Block Lock protection
• 400kHz 2-wire interface
The Watchdog Timer provides an independent protec-
tion mechanism for microcontrollers. When the micro-
controller fails to restart a timer within a selectable time-
out interval, the device activates the RESET signal. The
user selects the interval from three preset values. Once
selected, the interval does not change, even after cycling
the power.
™
—Slave addressing supports up to 4 devices on
the same bus
BLOCK DIAGRAM
V2FAIL
+
V2MON
V
-
TRIP2
V2 Monitor
Logic
Watchdog Transition
Detector
Watchdog
Timer Reset
WP
Protect Logic
RESET
Data
Register
SDA
Status
Register
Command
Reset &
Watchdog
Timebase
SCL
Decode &
Control
Logic
S0
S1
64KB
EEPROM
Array
V
Threshold
CC
Reset logic
Power-on and
Low Voltage
Reset
V
+
-
CC
Generation
V
TRIP
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1
1-888-INTERSIL or 1-888-352-6832 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2005. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
X40626
™
The device’s low V
detection circuitry protects the
The device utilizes Intersil’s proprietary Direct Write
CC
user’s system from low voltage conditions, resetting the
cell, providing a minimum endurance of 100,000 page
write cycles and a minimum data retention of 100 years.
system when V falls below the set minimum V trip
CC
CC
point. RESET is asserted until V
returns to proper
CC
operating level and stabilizes. Four industry standard
Vtrip thresholds are available. However, Intersil’s unique
circuits allow the threshold to be reprogrammed to meet
custom requirements or to fine-tune the threshold for
applications requiring higher precision.
PIN CONFIGURATION
14 Pin SOIC/TSSOP
NC
S0
S1
1
2
3
4
5
6
7
14
13
12
11
VCC
NC
The memory portion of the device is a CMOS Serial
WP
™
EEPROM array with Intersil’s Block Lock Protection.
V2MON
V2FAIL
SCL
NC
The array is internally organized as 64 bytes per page.
The device features an 2-wire interface and software pro-
RESET
10
9
NC
VSS
2
tocol allowing operation on an I C bus.
SDA
8
PIN FUNCTION
Pin
Name
NC
Function
1, 4, 6, 13
No Internal Connections
Device Select Input
Device Select Input
2
3
5
S0
S1
RESET
Reset Output. RESET is an active LOW, open drain output which goes active whenever VCC
falls below the minimum VCC sense level. It will remain active until VCC rises above the mini-
mum VCC sense level for typically 200ms. RESET goes active if the Watchdog Timer is
enabled and SDA remains either HIGH or LOW longer than the selectable Watchdog time-out
period. A falling edge on SDA, while SCL is HIGH, resets the Watchdog Timer. RESET goes
active on power-up and remains active for typically 200ms after the power supply
stabilizes.
7
8
VSS
Ground
SDA
Serial Data. SDA is a bidirectional pin used to transfer data into and out of the device. It has an
open drain output and may be wire ORed with other open drain or open collector outputs. This
pin requires a pull up resistor and the input buffer is always active (not gated).
Watchdog Input. A HIGH to LOW transition on the SDA (while SCL is HIGH) restarts the Watch-
dog timer. The absence of a HIGH to LOW transition within the watchdog time-out
period results in RESET going active.
9
SCL
Serial Clock. The Serial Clock controls the serial bus timing for data input and output.
10
V2FAIL
V2 Voltage Fail Output. This open drain output goes LOW when V2MON is less than VTRIP2
and goes HIGH when V2MON exceeds VTRIP2. There is no power-up reset delay circuitry on
this pin. This circuit works independently from the Low VCC reset and battery switch circuits.
Connect V2FAIL to VSS when not used.
11
V2MON
V2 Voltage Monitor Input. When the V2MON input is less than the VTRIP2 voltage, V2FAIL
goes LOW. This input can monitor an unregulated power supply with an external resistor
divider or can monitor a second power supply with no external components. Connect V2MON
to VSS or VCC when not used. There is no hysteresis in the V2MON comparator circuits.
12
14
WP
Write Protect. WP HIGH used in conjunction with WPEN bit prevents writes to the control reg-
ister.
VCC
Supply Voltage
FN8119.0
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March 28, 2005
X40626
PRINCIPLES OF OPERATION
Power-on Reset
EEPROM INADVERTENT WRITE PROTECTION
When RESET goes active as a result of a low voltage
condition or Watchdog Timer Time-Out, any in-
progress communications are terminated. While
RESET is active, no new communications are allowed
and no non-volatile write operation can start. Non-vol-
atile writes in-progress when RESET goes active are
allowed to finish.
Application of power to the X40626 activates a power-
on Reset Circuit that pulls the RESET pin active. This
signal provides several benefits.
– It prevents the system microprocessor from starting
to operate with insufficient voltage.
Additional protection mechanisms are provided with
memory Block Lock and the Write Protect (WP) pin.
These are discussed elsewhere in this document.
– It prevents the processor from operating prior to sta-
bilization of the oscillator.
– It allows time for an FPGA to download its configura-
tion prior to initialization of the circuit.
V
/V
THRESHOLD RESET PROCEDURE
CC 2MON
– It prevents communication to the EEPROM, greatly
reducing the likelihood of data corruption on power-up.
The X40626 is shipped with a standard V threshold
CC
(V
) voltage. This value will not change over normal
TRIP
When V
exceeds the device V
threshold value
CC
TRIP
operating and storage conditions. However, in applica-
tions where the standard V is not exactly right, or if
for t
(200ms nominal) the circuit releases
PURST
TRIP
RESET allowing the system to begin operation.
higher precision is needed in the V
value, the
TRIP
X40626 threshold may be adjusted. The procedure is
described below, and uses the application of a nonvol-
atile control signal.
LOW VOLTAGE MONITORING
During operation, the X40626 monitors the V
level
CC
and asserts RESET if supply voltage falls below a pre-
set minimum V . The RESET signal prevents the
Setting the V
Voltage
TRIP
TRIP
microprocessor from operating in a power fail or
brownout condition. The RESET signal remains active
until the voltage drops below 1V. It also remains active
This procedure is used to set the V
lower voltage value. It is necessary to reset the trip
point before setting the new value.
to a higher or
TRIP
until V returns and exceeds V
for 200ms.
CC
TRIP
The V and V2MON must be tied together during this
CC
sequence.
WATCHDOG TIMER
To set the new V
bit in the control register, then apply the desired V
threshold voltage to the V pin and the programming
voltage, start by setting the WEL
The Watchdog Timer circuit monitors the microproces-
sor activity by monitoring the SDA and SCL pins. The
microprocessor must toggle the SDA pin HIGH to
LOW periodically, while SCL is HIGH (this is a start bit)
prior to the expiration of the watchdog time-out period to
prevent a RESET signal. The state of two nonvolatile
control bits in the Status Register determine the watch-
dog timer period. The microprocessor can change
these watchdog bits, or they may be “locked” by tying
the WP pin HIGH.
TRIP
TRIP
CC
voltage, V , to the WP pin and 2 byte address and 1
P
byte of “00” data. The stop bit following a valid write
operation initiates the V
Bring WP LOW to complete the operation.
programming sequence.
TRIP
Figure 1. Set V
Level Sequence (V /V
= desired V
values, WP = 12-15V when WEL bit set)
TRIP
TRIP
CC 2MON
V
P = 12-15V
WP
0 1 2 3 4 5 6 7
0 1 2 3 4 5 6 7
0 1 2 3 4 5 6 7
0 1 2 3 4 5 6 7
SCL
SDA
A0H
00H
xxH*
00H
*for VVTRIP2 address is 0DH
for VTRIP address is 01H
FN8119.0
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March 28, 2005
X40626
Resetting the V
Voltage
To reset the new V
voltage start by setting the
TRIP
TRIP
WEL bit in the control register, apply the desired V
TRIP
This procedure is used to set the V
voltage level. For example, if the current V
to a “native”
TRIP
threshold voltage to the V pin and the programming
CC
is 4.4V
TRIP
voltage, V , to the WP pin and 2 byte address and 1
P
and the new V
must be 4.0V, then the V
must
TRIP
TRIP
byte of “00” data. The stop bit of a valid write operation
be reset. When V
is reset, the new V
is some-
TRIP
TRIP
initiates the V
programming sequence. Bring WP
TRIP
thing less than 1.7V. This procedure must be used to
set the voltage to a lower value.
LOW to complete the operation.
Figure 2. Reset V
Level Sequence (V /V
> 3V, WP = 12-15V, WEL bit set)
TRIP
CC 2MON
VP = 12-15V
WP
0 1 2 3 4 5 6 7
0 1 2 3 4 5 6 7
0 1 2 3 4 5 6 7
0 1 2 3 4 5 6 7
SCL
SDA
A0H
00H
xxH*
00H
*for VTRIP2 address is 0FH
for VTRIP address is 03H
Figure 3. Sample V
Reset Circuit
TRIP
VP
14
13
1
Adjust
4.7K
2
3
4
5
µC
12
RESET
Run
X40626
VTRIP
Adj.
6
7
9
8
SCL
SDA
FN8119.0
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March 28, 2005
X40626
Figure 4. V
Programming Sequence
TRIP
Vx = VCC, V2MON
VTRIPX Programming
Let: MDE = Maximum Desired Error
Desired
VTRIPX
Present Value
No
MDE+
Acceptable
Desired Value
YES
Error Range
MDE–
Set VX = Desired VTRIPX
Error = Actual - Desired
Execute
Set Higher VTRIPX Sequence
New VX applied =
Old VX applied + | Error |
Execute
Set Higher VX Sequence
New VX applied =
Old VX applied - | Error |
Apply VCC and Voltage
Execute Reset VTRIPX
Sequence
> Desired VTRIPX to
VX
NO
Decrease
VX
Output Switches?
YES
V
Error < MDE–
Error > MDE+
Actual
TRIPX -
VTRIPX
Desired
| Error | < | MDE |
DONE
FN8119.0
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March 28, 2005
X40626
Control Register
BP2, BP1, BP0: Block Protect Bits - (Nonvolatile)
The Control Register provides the user a mechanism
for changing the Block Lock and Watchdog Timer set-
tings. The Block Lock and Watchdog Timer bits are
nonvolatile and do not change when power is
removed.
The Block Protect Bits, BP2, BP1 and BP0, determine
which blocks of the array are write protected. A write to
a protected block of memory is ignored. The block pro-
tect bits will prevent write operations to one of eight
segments of the array.
The Control Register is accessed at address FFFFh. It
can only be modified by performing a byte write opera-
tion directly to the address of the register and only one
data byte is allowed for each register write operation.
Prior to writing to the Control Register, the WEL and
RWEL bits must be set using a two step process, with
the whole sequence requiring 3 steps. See "Writing to
the Control Register" below.
Protected Addresses
(Size)
Array Lock
None
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
None (factory setting)
1800h - 1FFFH (2K bytes)
Upper 1/4 (Q4)
1000h - 1FFFH (4K bytes) Upper 1/2 (Q3,Q4)
0000h - 1FFFH (8K bytes)
000h - 03FH (64 bytes)
000h - 07FH (128 bytes)
000h - 0FFH (256 bytes)
000h - 1FFH (512 bytes)
Full Array (All)
First Page (P1)
First 2 pgs (P2)
First 4 pgs (P4)
First 8 Pgs (P8)
The user must issue a stop after sending this byte to
the register to initiate the nonvolatile cycle that stores
WD1, WD0, BP2, BP1, and BP0. The X40626 will not
acknowledge any data bytes written after the first byte
is entered.
WD1, WD0: Watchdog Timer Bits
The state of the Control Register can be read at any
time by performing a random read at address FFFFh.
Only one byte is read by each register read operation.
The X40626 resets itself after the first byte is read.
The master should supply a stop condition to be con-
sistent with the bus protocol, but a stop is not required
to end this operation.
The bits WD1 and WD0 control the period of the
Watchdog Timer. The options are shown below.
WD1
WD0
Typ. Watchdog Time-out Period
1.4 Seconds
0
0
1
1
0
1
0
1
600 milliseconds
200 milliseconds
7
6
5
4
3
2
1
0
Disabled (factory setting)
WPEN WD1 WD0 BP1 BP0 RWEL WEL BP2
Write Protect Enable
RWEL: Register Write Enable Latch (Volatile)
These devices have an advanced Block Lock scheme
that protects one of eight blocks of the array when
enabled. It provides hardware write protection through
the use of a WP pin and a nonvolatile Write Protect
Enable (WPEN) bit. Four of the 8 protected blocks
match the original Block Lock segments and this pro-
tection scheme is fully compatible with the current
devices using 2 bits of block lock control (assuming
the BP2 bit is set to 0).
The RWEL bit must be set to “1” prior to a write to the
Control Register.
WEL: Write Enable Latch (Volatile)
The WEL bit controls the access to the memory and to
the Register during a write operation. This bit is a vola-
tile latch that powers up in the LOW (disabled) state.
While the WEL bit is LOW, writes to any address,
including any control registers will be ignored (no
acknowledge will be issued after the Data Byte). The
WEL bit is set by writing a “1” to the WEL bit and
zeroes to the other bits of the control register. Once
set, WEL remains set until either it is reset to 0 (by
writing a “0” to the WEL bit and zeroes to the other bits
of the control register) or until the part powers up
again. Writes to the WEL bit do not cause a nonvolatile
write cycle, so the device is ready for the next opera-
tion immediately after the stop condition.
The Write Protect (WP) pin and the Write Protect
Enable (WPEN) bit in the Control Register control the
programmable Hardware Write Protect feature. Hard-
ware Write Protection is enabled when the WP pin and
the WPEN bit are HIGH and disabled when either the
WP pin or the WPEN bit is LOW. When the chip is
Hardware Write Protected, nonvolatile writes as well as
to the block protected sections in the memory array
cannot be written. Only the sections of the memory
array that are not block protected can be written. Note
that since the WPEN bit is write protected, it cannot be
changed back to a LOW state; so write protection is
enabled as long as the WP pin is held HIGH.
FN8119.0
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March 28, 2005
X40626
Table 1. Write Protect Enable Bit and WP Pin Function
Memory Array not
Block Protected
Memory Array
Block Protected
Block Protect
Bits
WP
WPEN
WPEN Bit
Writes OK
Protection
Software
LOW
HIGH
HIGH
X
0
1
Writes OK
Writes OK
Writes OK
Writes Blocked
Writes Blocked
Writes Blocked
Writes OK
Writes OK
Writes OK
Software
Writes Blocked
Writes Blocked
Hardware
Writing to the Control Register
– The RWEL bit cannot be reset without writing to the
nonvolatile control bits in the control register, power
cycling the device or attempting a write to a write
protected block.
Changing any of the nonvolatile bits of the control reg-
ister requires the following steps:
– Write a 02H to the Control Register to set the Write
Enable Latch (WEL). This is a volatile operation, so
there is no delay after the write. (Operation pro-
ceeded by a start and ended with a stop).
To illustrate, a sequence of writes to the device con-
sisting of [02H, 06H, 02H] will reset all of the nonvola-
tile bits in the Control Register to 0. A sequence of
[02H, 06H, 06H] will leave the nonvolatile bits
unchanged and the RWEL bit remains set.
– Write a 06H to the Control Register to set both the
Register Write Enable Latch (RWEL) and the WEL
bit. This is also a volatile cycle. The zeros in the data
byte are required. (Operation proceeded by a start
and ended with a stop).
SERIAL INTERFACE
Serial Interface Conventions
– Write a value to the Control Register that has all the
control bits set to the desired state. This can be rep-
resented as 0xys t01r in binary, where xy are the
WD bits, and rst are the BP bits. (Operation pre-
ceeded by a start and ended with a stop). Since this
is a nonvolatile write cycle it will take up to 10ms to
complete. The RWEL bit is reset by this cycle and
the sequence must be repeated to change the non-
volatile bits again. If bit 2 is set to ‘1’ in this third step
(0xys t11r) then the RWEL bit is set, but the WD1,
WD0, BP2, BP1 and BP0 bits remain unchanged.
Writing a second byte to the control register is not
allowed. Doing so aborts the write operation and
returns a NACK.
The device supports a bidirectional bus oriented proto-
col. The protocol defines any device that sends data
onto the bus as a transmitter, and the receiving device
as the receiver. The device controlling the transfer is
called the master and the device being controlled is
called the slave. The master always initiates data
transfers, and provides the clock for both transmit and
receive operations. Therefore, the devices in this fam-
ily operate as slaves in all applications.
Serial Clock and Data
Data states on the SDA line can change only during
SCL LOW. SDA state changes during SCL HIGH are
reserved for indicating start and stop conditions. See
Figure 5.
– A read operation occurring between any of the previ-
ous operations will not interrupt the register write
operation.
FN8119.0
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March 28, 2005
X40626
Figure 5. Valid Data Changes on the SDA Bus
SCL
SDA
Data Stable
Data Change
Data Stable
Serial Start Condition
Serial Stop Condition
All commands are preceded by the start condition,
which is a HIGH to LOW transition of SDA when SCL
is HIGH. The device continuously monitors the SDA
and SCL lines for the start condition and will not
respond to any command until this condition has been
met. See Figure 6.
All communications must be terminated by a stop con-
dition, which is a LOW to HIGH transition of SDA when
SCL is HIGH. The stop condition is also used to place
the device into the Standby power mode after a read
sequence. A stop condition can only be issued after the
transmitting device has released the bus. See Figure 6.
Figure 6. Valid Start and Stop Conditions
SCL
SDA
Start
Stop
Serial Acknowledge
In the read mode, the device will transmit eight bits of
data, release the SDA line, then monitor the line for an
acknowledge. If an acknowledge is detected and no
stop condition is generated by the master, the device
will continue to transmit data. The device will terminate
further data transmissions if an acknowledge is not
detected. The master must then issue a stop condition
to return the device to Standby mode and place the
device into a known state.
Acknowledge is a software convention used to indi-
cate successful data transfer. The transmitting device,
either master or slave, will release the bus after trans-
mitting eight bits. During the ninth clock cycle, the
receiver will pull the SDA line LOW to acknowledge
that it received the eight bits of data. Refer to Figure 7.
The device will respond with an acknowledge after
recognition of a start condition and if the correct
Device Identifier and Select bits are contained in the
Slave Address Byte. If a write operation is selected,
the device will respond with an acknowledge after the
receipt of each subsequent eight bit word. The device
will acknowledge all incoming data and address bytes,
except for the Slave Address Byte when the Device
Identifier and/or Select bits are incorrect.
FN8119.0
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March 28, 2005
X40626
Figure 7. Acknowledge Response From Receiver
SCL from
Master
1
8
9
Data Output
from
Data Output
from Receiver
Start
Acknowledge
Serial Write Operations
Byte Write
data. After receiving the 8 bits of the Data Byte, the
device again responds with an acknowledge. The master
then terminates the transfer by generating a stop condi-
tion, at which time the device begins the internal write
cycle to the nonvolatile memory. During this internal write
cycle, the device inputs are disabled, so the device will
not respond to any requests from the master. The SDA
output is at high impedance. See Figure 8.
For a write operation, the device requires the Slave
Address Byte and a Word Address Byte. This gives the
master access to any one of the words in the array. After
receipt of the Word Address Byte, the device responds
with an acknowledge, and awaits the next eight bits of
Figure 8. Byte Write Sequence
S
S
T
A
R
T
Signals from
the Master
Word Address
Byte 1
Word Address
Slave
Address
T
Byte 0
Data
O
P
S S
SDA Bus
S 1 0 1 0 0
P
1
0 0
A
C
K
A
C
K
A
C
K
A
C
K
Signals from
the Slave
A write to a protected block of memory will suppress
the acknowledge bit.
counter reaches the end of the page, it “rolls over” and
goes back to ‘0’ on the same page. This means that
the master can write 64 bytes to the page starting at
any location on that page. If the master begins writing
at location 60, and loads 12 bytes, then the first 4
bytes are written to locations 60 through 63, and the
last 8 bytes are written to locations 0 through 7. After-
wards, the address counter would point to location 8 of
the page that was just written. If the master supplies
more than 64 bytes of data, then new data over-writes
the previous data, one byte at a time.
Page Write
The device is capable of a page write operation. It is
initiated in the same manner as the byte write opera-
tion; but instead of terminating the write cycle after the
first data byte is transferred, the master can transmit
an unlimited number of 8-bit bytes. After the receipt of
each byte, the device will respond with an acknowl-
edge, and the address is internally incremented by
one. The page address remains constant. When the
FN8119.0
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March 28, 2005
X40626
Figure 9. Page Write Operation
(I ≤ n ≤ 63)
S
T
A
R
T
Data
(0)
Data
(n)
S
T
O
P
Word Address
Byte 0
Word Address
Byte 1
Signals from
the Master
Slave
Address
S
S S
0
1 0
P
1 0 1 0
0
SDA Bus
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
Signals from
the Slave
Figure 10. Writing 12 bytes to a 64-byte page starting at location 60 (Wrap around).
8 Bytes
4 Bytes
address pointer
ends here
Addr = 8
address
60
address
= 7
address
63
The master terminates the Data Byte loading by issuing
a stop condition, which causes the device to begin the
nonvolatile write cycle. As with the byte write operation,
all inputs are disabled until completion of the internal
write cycle. See Figure 9 for the address, acknowledge,
and data transfer sequence.
Acknowledge Polling
The disabling of the inputs during nonvolatile cycles
can be used to take advantage of the typical 5mS write
cycle time. Once the stop condition is issued to indi-
cate the end of the master’s byte load operation, the
device initiates the internal nonvolatile cycle. Acknowl-
edge polling can be initiated immediately. To do this,
the master issues a start condition followed by the
Slave Address Byte for a write or read operation. If the
device is still busy with the nonvolatile cycle then no
ACK will be returned. If the device has completed the
write operation, an ACK will be returned and the host
can then proceed with the read or write operation.
Refer to the flow chart in Figure 11.
Stops and Write Modes
Stop conditions that terminate write operations must
be sent by the master after sending at least 1 full data
byte plus the subsequent ACK signal. If a stop is
issued in the middle of a data byte, or before 1 full
data byte plus its associated ACK is sent, then the
device will reset itself without performing the write. The
contents of the array will not be effected.
FN8119.0
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March 28, 2005
X40626
Figure 11. Acknowledge Polling Sequence
Serial Read Operations
Read operations are initiated in the same manner as
write operations with the exception that the R/W bit of
the Slave Address Byte is set to one. There are three
basic read operations: Current Address Reads, Ran-
dom Reads, and Sequential Reads.
Byte load completed
by issuing STOP.
Enter ACK Polling
Issue START
Current Address Read
Internally the device contains an address counter that
maintains the address of the last word read incre-
mented by one. Therefore, if the last read was to
address n, the next read operation would access data
from address n+1. On power-up, the address in the
address counter is 00H.
Issue Slave Address
Byte (Read or Write)
Issue STOP
NO
ACK
returned?
Upon receipt of the Slave Address Byte with the R/W bit
set to one, the device issues an acknowledge and then
transmits the eight bits of the Data Byte. The master
terminates the read operation when it does not respond
with an acknowledge during the ninth clock and then
issues a stop condition. Refer to Figure 12 for the
address, acknowledge, and data transfer sequence.
YES
NO
Nonvolatile Cycle
complete. Continue
command sequence?
Issue STOP
It should be noted that the ninth clock cycle of the read
operation is not a “don’t care.” To terminate a read
operation, the master must either issue a stop condi-
tion during the ninth cycle or hold SDA HIGH during
the ninth clock cycle and then issue a stop condition.
YES
Continue Normal
Read or Write
Command Sequence
PROCEED
Figure 12. Current Address Read Sequence
S
Slave
Address
t
S
t
o
p
Signals from
the Master
a
r
t
SDA Bus
1
0 1 0 0 S S 1
1 0
A
Signals from
the Slave
C
Data
K
FN8119.0
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March 28, 2005
X40626
Random Read
of the Word Address Bytes, the master immediately
issues another start condition and the Slave Address
Byte with the R/W bit set to one. This is followed by an
acknowledge from the device and then by the eight bit
word. The master terminates the read operation by not
responding with an acknowledge and then issuing a
stop condition. Refer to Figure 13 for the address,
acknowledge, and data transfer sequence.
Random read operation allows the master to access
any memory location in the array. Prior to issuing the
Slave Address Byte with the R/W bit set to one, the
master must first perform a “dummy” write operation.
The master issues the start condition and the Slave
Address Byte, receives an acknowledge, then issues
the Word Address Bytes. After acknowledging receipts
Figure 13. Random Address Read Sequence
S
T
S
T
A
R
S
T
O
P
Signals from
the Master
Word Address
Byte 1
Word Address
Byte 0
Slave
Address
Slave
Address
A
R
T
T
1
S S
1 0
S S
SDA Bus
S 1 0 1 0 0
0
S 1 0 1 0 0
P
1
0
A
C
K
A
C
K
A
C
K
A
C
K
Signals from
the Slave
Data
There is a similar operation, called “Set Current
Address” where the device does no operation, but
enters a new address into the address counter if a
stop is issued instead of the second start shown in Fig-
ure 13. The device goes into standby mode after the
stop and all bus activity will be ignored until a start is
detected. The next Current Address Read operation
reads from the newly loaded address. This operation
could be useful if the master knows the next address it
needs to read, but is not ready for the data.
The data output is sequential, with the data from address
n followed by the data from address n + 1. The address
counter for read operations increments through all page
and column addresses, allowing the entire memory con-
tents to be serially read during one operation. At the end
of the address space the counter “rolls over” to address
0000H and the device continues to output data for each
acknowledge received. Refer to Figure 14 for the
acknowledge and data transfer sequence.
Sequential Read
Sequential reads can be initiated as either a current
address read or random address read. The first Data
Byte is transmitted as with the other modes; however,
the master now responds with an acknowledge, indicat-
ing it requires additional data. The device continues to
output data for each acknowledge received. The master
terminates the read operation by not responding with an
acknowledge and then issuing a stop condition.
FN8119.0
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March 28, 2005
X40626
Figure 14. Sequential Read Sequence
S
t
o
p
Signals from
the Master
Slave
Address
A
C
K
A
C
K
A
C
K
SDA Bus
S
S
1
0
1
A
C
K
Signals from
the Slave
Data
(2)
Data
(n-1)
Data
(1)
Data
(n)
(n is any integer greater than 1)
X40626 Addressing
Slave Address Byte
– After loading the entire Slave Address Byte from the
SDA bus, the device compares the input slave byte
data to the proper slave byte. Upon a correct compare,
the device outputs an acknowledge on the SDA line.
Following a start condition, the master must output a
Slave Address Byte. This byte consists of several
parts:
Word Address
The word address is either supplied by the master or
obtained from an internal counter. The internal counter
is 00H on a power-up condition.
– a device type identifier that is ‘1010’ to access the
array
– one bit of ‘0’.
The master must supply the two word address byte as
shown in Figure 15.
– next two bits are the device address. (S1 and S0)
– one bit of the slave command byte is a R/W bit. The
R/W bit of the Slave Address Byte defines the oper-
ation to be performed. When the R/W bit is a one,
then a read operation is selected. A zero selects a
write operation. Refer to Figure 15.
FN8119.0
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March 28, 2005
X40626
Figure 15. X40626 Addressing
Device Identifier
Device Select
1
0
1
0
0
S1
S0
R/W
Slave Address Byte
High Order Word Address
A15
A14
A13
A12
A11
A10
A9
A8
Word Address Byte 1
Low Order Word Address
A7
D7
A6
D6
A5
D5
A4
Word Address Byte 0
A3
A2
A1
D1
A0
D0
D4
D3
D2
Data Byte
Operational Notes
– Communication to the device is inhibited while
RESET is active and any in-progress communica-
tion is terminated.
The device powers-up in the following state:
– The device is in the low power standby state.
– Block Lock bits can protect sections of the memory
array from write operations.
– The WEL bit is set to ‘0’. In this state it is not possi-
ble to write to the device.
– SDA pin is in the input mode.
Symbol Table
– RESET Signal is active for t
.
PURST
WAVEFORM
INPUTS
OUTPUTS
Data Protection
Must be
steady
Will be
steady
The following circuitry has been included to prevent
inadvertent writes:
May change
from LOW
to HIGH
Will change
from LOW
to HIGH
– The WEL bit must be set to allow write operations.
– The proper clock count and bit sequence is required
prior to the stop bit in order to start a nonvolatile
write cycle.
May change
from HIGH
to LOW
Will change
from HIGH
to LOW
– A three step sequence is required before writing into
the Control Register to change Watchdog Timer or
Block Lock settings.
Don’t Care:
Changes
Allowed
Changing:
State Not
Known
N/A
Center Line
is High
Impedance
– The WP pin, when held HIGH, and WPEN bit at logic
HIGH will prevent all writes to the Control Register.
FN8119.0
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March 28, 2005
X40626
ABSOLUTE MAXIMUM RATINGS
COMMENT
Temperature under bias ................... -65°C to +135°C
Storage temperature ........................ -65°C to +150°C
Voltage on any pin with respect to VSS... -1.0V to +7V
D.C. output current (sink) ...................................10mA
Lead temperature (soldering, 10 seconds)........ 300°C
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only; functional operation of the
device (at these or any other conditions above those
listed in the operational sections of this specification) is
not implied. Exposure to absolute maximum rating condi-
tions for extended periods may affect device reliability.
Table 2. Recommended Operating Conditions
Temp
Min.
0°C
Max.
70°C
Commercial
Industrial
-40°C
+85°C
D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.)
V
= 2.7 to 5.5V
CC
Symbol
Parameter
Min
Max
1.0
3.0
1
Unit
mA
mA
µA
Test Conditions
(1)
ICC1
Active Supply Current Read
Active Supply Current Write
Standby Current DC (WDT off)
VIL = VCC x 0.1, VIH = VCC x 0.9
fSCL = 400kHz, SDA = Open
(2)
ICC2
(2)
ISB1
VSDA=VSCL=VCC
Others=GND or VCC
(3)
ISB2
Standby Current DC (WDT on)
30
µA
VSDA=VSCL=VCC
Others=GND or VCC
ILI
Input Leakage Current
Output Leakage Current
10
10
µA
µA
VIN = GND to VCC
ILO
VSDA = GND to VCC
Device is in Standby
VIL
Input LOW Voltage
Input HIGH Voltage
-1
VCC x 0.3
VCC +0.5
V
V
VIH
VCC x 0.7
VHYS
Schmitt Trigger Input Hysteresis
Fixed input level
0.2
.05 x VCC
V
V
VCC related level
VOL
Output LOW Voltage
0.4
V
IOL = 1.0mA (VCC=3V)
IOL = 3.0mA (VCC=5V)
Notes: (1) The device enters the Active state after any start, and remains active until: (a) 9 clock cycles later if the Device Select Bits in the Slave
Address Byte are incorrect; or (b) 200nS after a stop ending a read operation.
(2) The device enters the Active state after any start, and remains active until tWC after a stop ending a write operation.
(3) The device goes into Standby: (a) 200nS after any stop, except those that initiate a nonvolatile write cycle; or (b) tWC after a stop that
initiates a nonvolatile cycle; or 9 clock cycles after any start that is not followed by the correct Device Select Bits in the Slave Address
Byte.
FN8119.0
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March 28, 2005
X40626
CAPACITANCE (T = 25°C, f = 1.0 MHz, V = 5V)
A
CC
Symbol
Parameter
Max.
Units
pF
Test Conditions
VOUT = 0V
(4)
COUT
Output Capacitance (SDA, RESET, V2FAIL)
Input Capacitance (SCL, WP, S0, S1)
8
6
(4)
CIN
pF
VIN = 0V
Notes: (4) This parameter is periodically sampled and not 100% tested.
EQUIVALENT A.C. LOAD CIRCUIT
A.C. TEST CONDITIONS
Input pulse levels
0.1VCC to 0.9VCC
10ns
5V
V2MON
Input rise and fall times
Input and output timing levels 0.5VCC
Output load Standard Output Load
1.53kΩ
1533Ω
SDA
RESET
V2FAIL
30pF
30pF
A.C. CHARACTERISTICS (Over recommended operating conditions, unless otherwise specified)
Symbol
fSCL
Parameter
Min.
Max.
Units
kHz
ns
SCL Clock Frequency
0
400
tIN
Pulse width Suppression Time at inputs
SCL LOW to SDA Data Out Valid
Time the bus free before start of new transmission
Clock LOW Time
50
tAA
0.1
0.9
µs
tBUF
1.3
µs
tLOW
tHIGH
tSU:STA
tHD:STA
tSU:DAT
tHD:DAT
tSU:STO
tDH
1.3
µs
Clock HIGH Time
0.6
µs
Start Condition Setup Time
Start Condition Hold Time
Data In Setup Time
0.6
µs
0.6
µs
100
ns
Data In Hold Time
0
µs
Stop Condition Setup Time
Data Output Hold Time
0.6
µs
50
20 + 0.1Cb(2)
20 + 0.1Cb(2)
0.6
ns
tR
SDA and SCL Rise Time
SDA and SCL Fall Time
WP Setup Time
300
300
ns
tF
ns
tSU:WP
tHD:WP
Cb
µs
WP Hold Time
0
µs
Capacitive load for each bus line
400
pF
Notes: (1) Typical values are for TA = 25°C and VCC = 5.0V
(2) Cb = total capacitance of one bus line in pF.
FN8119.0
March 28, 2005
16
X40626
TIMING DIAGRAMS
Bus Timing
tF
tR
tHIGH
tLOW
SCL
tSU:STA
SDA IN
tSU:DAT
tHD:DAT
tSU:STO
tHD:STA
tAA tDH
tBUF
SDA OUT
WP Pin Timing
START
SCL
Clk 1
Clk 9
Slave Address Byte
SDA IN
WP
tSU:WP
tHD:WP
Write Cycle Timing
SCL
8th bit of Last Byte
ACK
SDA
tWC
Stop
Start
Condition
Condition
Nonvolatile Write Cycle Timing
Symbol
(1)
Parameter
Min.
Typ.
Max.
Units
(1)
tWC
Write Cycle Time
5
10
mS
Notes: (1) tWC is the time from a valid stop condition at the end of a write sequence to the end of the self-timed internal nonvolatile write cycle. It is
the minimum cycle time to be allowed for any nonvolatile write by the user, unless Acknowledge Polling is used.
FN8119.0
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March 28, 2005
X40626
Power-Up and Power-Down Timing
VTRIP/VTRIP2
VCC/V2MON
0 Volts
tPURST
tPURST
tF
tR
tRPD
VRVALID
RESET/V2FAIL
RESET Output Timing
Symbol
Parameter
Min.
Typ.
Max.
400
Units
ms
ns
tPURST
Power-up Reset Timeout
100
200
(8)
tRPD
VCC Detect to Reset/Output (Falling Edge)
VCC/V2MON Fall Time
500
(8)
tF
100
100
1.0
µs
(8)
tR
VCC/V2MON Rise Time
µs
(8)
VRVALID
Reset Valid VCC or V2FAIL Valid V2MON
Voltage Range over which VTRIP/VTRIP2 can be set
V
V
TRIP Range
2.0
VCC
V
Notes: (8) This parameter is periodically sampled and not 100% tested.
SDA vs. RESET Timing
Start
Start
tRSP
< tWDO
SCL
Timer Start
SDA
tRST
tWDO
tRST
RESET
Timer
Restart
Timer Start
FN8119.0
March 28, 2005
18
X40626
RESET Output Timing
Symbol
Parameter
Min.
Typ.
Max.
Units
tWDO
Watchdog Timeout Period,
WD1 = 1, WD0 = 1 (factory setting)
WD1 = 1, WD0 = 0
Disabled
100
Disabled
200
Disabled
400
Factory Setting
ms
ms
sec
WD1 = 0, WD0 = 1
WD1 = 0, WD0 = 0
450
1.0
600
1.4
850
2.0
tRST
Reset Timeout
100
250
400
ms
V
Programming Timing Diagram (WEL = 1)
TRIP
VCC/V2MON
VCC/V2MON
(VTRIP/VTRIP2
)
tTSU
tTHD
VP
WP
tVPS
tVPO
0 1 2
7
0
7
0
7
0
7
SCL
SDA
data
00h
AS1S000h
tWC
0001H*: set VTRIP
Start
000DH: set VTRIP2
0003H: Resets VTRIP
000FH: Resets VTRIP2
FN8119.0
March 28, 2005
19
X40626
Packaging Information
14-Lead Plastic Small Outline Gullwing Package Type S
0.150 (3.80) 0.228 (5.80)
0.158 (4.00) 0.244 (6.20)
Pin 1 Index
Pin 1
0.014 (0.35)
0.020 (0.51)
0.336 (8.55)
0.345 (8.75)
(4X) 7°
0.053 (1.35)
0.069 (1.75)
0.004 (0.10)
0.010 (0.25)
0.050 (1.27)
0.050" Typical
0.010 (0.25)
0.020 (0.50)
X 45°
0.050" Typical
0° - 8°
0.250"
0.0075 (0.19)
0.010 (0.25)
0.016 (0.410)
0.037 (0.937)
0.030" Typical
14 Places
FOOTPRINT
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
FN8119.0
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March 28, 2005
X40626
PACKAGING INFORMATION
14-Lead Plastic, TSSOP, Package Code V14
.025 (.65) BSC
.169 (4.3)
.177 (4.5)
.252 (6.4) BSC
.193 (4.9)
.200 (5.1)
.041 (1.05)
.0075 (.19)
.0118 (.30)
.002 (.05)
.006 (.15)
.010 (.25)
Gage Plane
0° - 8°
Seating Plane
.019 (.50)
.029 (.75)
Detail A (20X)
.031 (.80)
.041 (1.05)
See Detail “A”
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
FN8119.0
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March 28, 2005
X40626
Ordering Information
Operating
Temperature
Range
V
Part Number RESET
(Active LOW)
Park
Mark
TRIP2
V
Range
V
Range
Range
Package
CC
TRIP
4.5-5.5V
4.5-5.5V
2.7-5.5V
2.7-5.5V
4.5-4.75
2.85-3.0
14L SOIC
0°C-70°C
-40°C-85°C
0°C-70°C
X40626S14-4.5A
X40626S14I-4.5A
X40626V14-4.5A
X40626V14I-4.5A
X40626S14
AL
AM
AL
AM
blank
I
14L TSSOP
14L SOIC
-40°C-85°C
0°C-70°C
4.25-4.5
2.85-3.0
2.55-2.7
2.85-3.0
2.15-2.30
2.55-2.7
-40°C-85°C
0°C-70°C
X40626S14I
14L TSSOP
14L SOIC
X40626V14
blank
I
-40°C-85°C
0°C-70°C
X40626V14I
X40626S14-2.7A
X40626S14I-2.7A
X40626V14-2.7A
X40626V14I-2.7A
X40626S14-2.7
X40626S14I-2.7
X40626V14-2.7
X40626V14I-2.7
AN
AP
BN
AP
F
-40°C-85°C
0°C-70°C
14LTSSOP
14L SOIC
-40°C-85°C
0°C-70°C
-40°C-85°C
0°C-70°C
G
14L TSSOP
F
-40°C-85°C
G
PART MARK INFORMATION
14-Lead SOIC/TSSOP
X40626 X
YYWWXX
S = SOIC
V = TSSOP
XX – Part Mark
WW – Workweek
YY – Year
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN8119.0
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March 28, 2005
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