X4165S8 [RENESAS]
1-CHANNEL POWER SUPPLY MANAGEMENT CKT, PDSO8, PLASTIC, SOIC-8;
| 型号： | X4165S8 |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | 1-CHANNEL POWER SUPPLY MANAGEMENT CKT, PDSO8, PLASTIC, SOIC-8 光电二极管 |
| 文件： | 总22页 (文件大小：924K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATASHEET
X4163, X4165
16K, 2K x 8 Bit CPU Supervisor with 16K EEPROM
FN8120
Rev 2.00
November 26, 2007
FEATURES
DESCRIPTION
• Selectable watchdog timer
The X4163, X4165 combines four popular functions,
Power-on Reset Control, Watchdog Timer, Supply Volt-
age Supervision, and Serial EEPROM Memory in one
package. This combination lowers system cost,
reduces board space requirements, and increases reli-
ability.
• Low V detection and reset assertion
CC
—Four standard reset threshold voltages
—Adjust low V reset threshold voltage using
CC
special programming sequence
—Reset signal valid to V = 1V
CC
• Low power CMOS
Applying power to the device activates the power on
reset circuit which holds RESET/RESET active for a
period of time. This allows the power supply and oscilla-
tor to stabilize before the processor can execute code.
—<20µA max standby current, watchdog on
—<1µA standby current, watchdog OFF
—3mA active current
• 16Kbits of EEPROM
—64-byte page write mode
—Self-timed write cycle
The Watchdog Timer provides an independent protec-
tion mechanism for microcontrollers. When the micro-
controller fails to restart a timer within a selectable
time out interval, the device activates the
RESET/RESET signal. The user selects the interval
from three preset values. Once selected, the interval
does not change, even after cycling the power.
—5ms write cycle time (typical)
• Built-in inadvertent write protection
—Power-up/power-down protection circuitry
—Block Lock (1, 2, 4, 8 pages, all, none)
• 400kHz 2-wire interface
• 2.7V to 5.5V power supply operation
• Available Packages
—8 Ld SOIC
The device’s low V
detection circuitry protects the
CC
user’s system from low voltage conditions, resetting the
system when V falls below the set minimum V trip
CC
CC
—8 Ld TSSOP
• Pb-free plus anneal available (RoHS compliant)
point. RESET/RESET is asserted until V
returns to
CC
proper operating level and stabilizes. Four industry
standard V thresholds are available, however, Inter-
TRIP
sil’s unique circuits allow the threshold to be repro-
grammed to meet custom requirements or to fine-tune
the threshold for applications requiring higher precision.
BLOCK DIAGRAM
Watchdog Transition
Detector
Watchdog
Timer Reset
WP
Protect Logic
RESET (X4163)
RESET (X4165)
Data
Register
SDA
Status
Register
EEPROM Array
Command
Reset &
Watchdog
Timebase
SCL
Decode &
Control
Logic
S0
S1
VCC Threshold
Reset logic
Power on and
Low Voltage
Reset
VCC
+
-
VTRIP
Generation
FN8120 Rev 2.00
November 26, 2007
Page 1 of 22
X4163, X4165
Ordering Information
PART NUMBER
PART NUMBER
RESET
RESET
PART
PART
MARKING
V
CC RANGE
(V)
VTRIP
TEMP
PKG.
DWG. #
(ACTIVE LOW)
MARKING
(ACTIVE HIGH)
RANGE (V) RANGE (°C)
PACKAGE
8 Ld SOIC
X4163S8-4.5A
X4163 AL
X4165S8-4.5A
X4165 AL
4.5-5.5
4.5-4.75
0 to 70
0 to 70
MDP0027
MDP0027
X4163S8Z-4.5A X4163 Z AL
(Note)
X4165S8Z-4.5A X4165 Z AL
(Note)
8 Ld SOIC
(Pb-free)
X4163S8I-4.5A X4163 AM
X4165S8I-4.5A
X4165 AM
-40 to 85
-40 to 85
8 Ld SOIC
MDP0027
MDP0027
X4163S8IZ-4.5A X4163 Z AM X4165S8IZ-4.5A X4165 Z AM
(Note)
8 Ld SOIC
(Pb-free)
(Note)
X4163V8-4.5A
4163AL
X4165V8-4.5A
4165AL
0 to 70
0 to 70
8 Ld TSSOP
(4.4mm)
M8.173
M8.173
M8.173
M8.173
X4163V8Z-4.5A 4163AL Z
(Note)
X4165V8Z-4.5A 4165AL Z
(Note)
8 Ld TSSOP
(4.4mm) (Pb-free)
X4163V8I-4.5A 4163AM
X4165V8I-4.5A
4165AM
-40 to 85
-40 to 85
8 Ld TSSOP
(4.4mm)
X4163V8IZ-4.5A 4163AM Z
(Note)
X4165V8IZ-4.5A 4165AM Z
(Note)
8 Ld TSSOP
(4.4mm) (Pb-free)
X4163S8-2.7
X4163 F
X4165S8-2.7
X4165 F
2.7-5.5
2.55-2.7
0 to 70
0 to 70
8 Ld SOIC
MDP0027
MDP0027
X4163S8Z-2.7
(Note)
X4163 Z F
X4165S8Z-2.7
(Note)
X4165 Z F
8 Ld SOIC
(Pb-free)
X4163S8I-2.7
X4163 G
X4165S8I-2.7
X4165 G
-40 to 85
-40 to 85
8 Ld SOIC
MDP0027
MDP0027
X4163S8IZ-2.7 X4163 Z G
(Note)
X4165S8IZ-2.7
(Note)
X4165 Z G
8 Ld SOIC
(Pb-free)
X4163V8-2.7
4163F
X4165V8-2.7
4165F
0 to 70
0 to 70
8 Ld TSSOP
(4.4mm)
M8.173
M8.173
M8.173
M8.173
X4163V8Z-2.7
(Note)
4163F Z
4163G
X4165V8Z-2.7
(Note)
4165F Z
4165G
8 Ld TSSOP
(4.4mm) (Pb-free)
X4163V8I-2.7
X4165V8I-2.7
-40 to 85
-40 to 85
8 Ld TSSOP
(4.4mm)
X4163V8IZ-2.7 4163G Z
(Note)
X4165V8IZ-2.7
(Note)
4165G Z
X4165 AN
8 Ld TSSOP
(4.4mm) (Pb-free)
X4163S8-2.7A* X4163 AN
X4165S8-2.7A
2.7-5.5
2.85-3.0
0 to 70
0 to 70
8 Ld SOIC
MDP0027
MDP0027
X4163S8Z-2.7A* X4163 Z AN X4165S8Z-2.7A X4165 Z AN
(Note)
8 Ld SOIC
(Pb-free)
(Note)
X4163S8I-2.7A X4163 AP
X4165S8I-2.7A
X4165 AP
-40 to 85
-40 to 85
8 Ld SOIC
MDP0027
MDP0027
X4163S8IZ-2.7A X4163 Z AP
(Note)
X4165S8IZ-2.7A X4165 Z AP
(Note)
8 Ld SOIC
(Pb-free)
X4163V8-2.7A
4163AN
X4165V8-2.7A
4165AN
2.7-5.5
2.85-3.0
0 to 70
0 to 70
8 Ld TSSOP
(4.4mm)
M8.173
M8.173
M8.173
M8.173
X4163V8Z-2.7A 4163AN Z
(Note)
X4165V8Z-2.7A 4165AN Z
(Note)
8 Ld TSSOP
(4.4mm) (Pb-free)
X4163V8I-2.7A 4163AP
X4165V8I-2.7A
4165AP
-40 to 85
-40 to 85
8 Ld TSSOP
(4.4mm)
X4163V8IZ-2.7A 4163AP Z
(Note)
X4165V8IZ-2.7A 4165AP Z
(Note)
8 Ld TSSOP
(4.4mm) (Pb-free)
FN8120 Rev 2.00
November 26, 2007
Page 2 of 22
X4163, X4165
Ordering Information (Continued)
PART NUMBER
RESET
(ACTIVE LOW)
PART NUMBER
RESET
(ACTIVE HIGH)
PART
MARKING
PART
MARKING
V
CC RANGE
(V)
VTRIP
TEMP
PKG.
DWG. #
RANGE (V) RANGE (°C)
PACKAGE
8 Ld SOIC
X4163S8
X4163
X4165S8*
X4165
4.5-5.5
4.25-4.5
0 to 70
0 to 70
MDP0027
MDP0027
X4163S8Z
(Note)
X4163 Z
X4165S8Z*
(Note)
X4165 Z
8 Ld SOIC
(Pb-free)
X4163S8I
X4163 I
X4165S8I
X4165 I
-40 to 85
-40 to 85
8 Ld SOIC
MDP0027
MDP0027
X4163S8IZ
(Note)
X4163 Z I
X4165S8IZ
(Note)
X4165 Z I
8 Ld SOIC
(Pb-free)
X4163V8
4163
X4165V8
4165
0 to 70
0 to 70
8 Ld TSSOP
(4.4mm)
M8.173
M8.173
M8.173
M8.173
X4163V8Z
(Note)
4163
X4165V8Z (Note) 4165
8 Ld TSSOP
(4.4mm) (Pb-free)
X4163V8I
4163I
4163I Z
X4165V8I
4165I
-40 to 85
-40 to 85
8 Ld TSSOP
(4.4mm)
X4163V8IZ
(Note)
X4165V8IZ
(Note)
4165I Z
8 Ld TSSOP
(4.4mm) (Pb-free)
*Add "-T1" suffix for tape and reel.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin
plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are
MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
FN8120 Rev 2.00
November 26, 2007
Page 3 of 22
X4163, X4165
PIN CONFIGURATION
8 Ld JEDEC SOIC
8 Ld TSSOP
SCL
SDA
VCC
1
2
3
4
8
7
6
5
1
2
3
4
8
7
6
5
WP
VCC
S0
S1
WP
SCL
SDA
VSS
S0
S1
RESET/RESET
VSS
RESET/RESET
PIN FUNCTION
Pin
(SOIC)
Pin (TS-
SOP)
Name
S0
Function
1
2
3
3
4
5
Device Select Input
Device Select Input
S1
RESET/
RESET
Reset Output. RESET/RESET is an active LOW/HIGH, open drain output which
goes active whenever VCC falls below the minimum VCC sense level. It will remain
active until VCC rises above the minimum VCC sense level for 250ms.
RESET/RESET goes active if the Watchdog Timer is enabled and SDA remains
either HIGH or LOW longer than the selectable Watchdog time out period. A falling
edge on SDA, while SCL is HIGH, resets the Watchdog Timer. RESET/RESET
goes active on power up and remains active for 250ms after the power supply sta-
bilizes.
4
5
6
7
VSS
Ground
SDA
Serial Data. SDA is a bidirectional pin used to transfer data into and out of the
device. It has an open drain output and may be wire ORed with other open drain
or open collector outputs. This pin requires a pull up resistor and the input buffer
is always active (not gated).
Watchdog Input. A HIGH to LOW transition on the SDA (while SCL is HIGH) restarts
the Watchdog timer. The absence of a HIGH to LOW transition within the watchdog
time out period results in RESET/RESET going active.
6
7
8
1
SCL
WP
Serial Clock. The Serial Clock controls the serial bus timing for data input and output.
Write Protect. WP HIGH used in conjunction with WPEN bit prevents writes to
the control register.
8
2
VCC
Supply Voltage
FN8120 Rev 2.00
November 26, 2007
Page 4 of 22
X4163, X4165
PRINCIPLES OF OPERATION
Power On Reset
WATCHDOG TIMER
The Watchdog Timer circuit monitors the microprocessor
activity by monitoring the SDA and SCL pins. The
microprocessor must periodically send a start bit followed by a
stop bit prior to the expiration of the watchdog time out period
to prevent a RESET/RESET signal. The start and stop bits
need to be separated by SCL toggling low then high at least
one time.
Application of power to the X4163, X4165 activates a
Power On Reset Circuit that pulls the RESET/RESET
pin active. This signal provides several benefits.
It prevents the system microprocessor from starting to operate
with insufficient voltage.
The state of two nonvolatile control bits in the Status Register
determine the watchdog timer period. The microprocessor can
change these watchdog bits, or they may be “locked” by tying
the WP pin HIGH.
It prevents the processor from operating prior to stabilization of
the oscillator.
It allows time for an FPGA to download its configuration prior to
initialization of the circuit.
EEPROM INADVERTENT WRITE PROTECTION
It prevents communication to the EEPROM, greatly reducing the
likelihood of data corruption on power up.
When RESET/RESET goes active as a result of a low
voltage condition or Watchdog Timer Time Out, any in-
progress communications are terminated. While
RESET/RESET is active, no new communications are
allowed and no nonvolatile write operation can start.
Nonvolatile writes in-progress when RESET/RESET
goes active are allowed to finish.
When VCC exceeds the device VTRIP threshold value for 200ms
(nominal) the circuit releases RESET/RESET allowing the
system to begin operation.
LOW VOLTAGE MONITORING
During operation, the X4163, X4165 monitors the VCC level
and asserts RESET/RESET if supply voltage falls below a
preset minimum VTRIP. The RESET/RESET signal prevents the
microprocessor from operating in a power fail or brownout
condition. The RESET/RESET signal remains active until the
voltage drops below 1V. It also remains active until VCC returns
and exceeds VTRIP for 200ms.
Additional protection mechanisms are provided with
memory Block Lock and the Write Protect (WP) pin.
These are discussed elsewhere in this document.
V
THRESHOLD RESET PROCEDURE
CC
The X4163, X4165 is shipped with a standard V
CC
threshold (V
) voltage. This value will not change
TRIP
over normal operating and storage conditions. However,
in applications where the standard V is not exactly
TRIP
right, or if higher precision is needed in the V
value,
TRIP
the X4163, X4165 threshold may be adjusted. The pro-
cedure is described below, and uses the application of a
nonvolatile control signal.
Figure 1. Set V
Level Sequence (V = desired V values WEL bit set)
TRIP
TRIP
CC
VP = 12-15V
WP
0 1 2 3 4 5 6 7
0 1 2 3 4 5 6 7
0 1 2 3 4 5 6 7
0 1 2 3 4 5 6 7
SCL
SDA
A0h
00h
01h
00h
FN8120 Rev 2.00
November 26, 2007
Page 5 of 22
X4163, X4165
Setting the V
Voltage
Resetting the V
Voltage
TRIP
TRIP
This procedure is used to set the V
to a higher or
This procedure is used to set the V
to a “native” volt-
TRIP
TRIP
lower voltage value. It is necessary to reset the trip point
before setting the new value.
age level. For example, if the current V
is 4.4V and
must be
TRIP
TRIP
the new V
must be 4.0V, then the V
TRIP
reset. When V
less than 1.7V. This procedure must be used to set the
voltage to a lower value.
is reset, the new V
is something
TRIP
TRIP
To set the new V
bit in the control register, then apply the desired V
threshold voltage to the V
voltage, start by setting the WEL
TRIP
TRIP
pin and the programming
CC
voltage, V , to the WP pin and 2 byte address and 1 byte
To reset the new V
voltage start by setting the WEL
P
TRIP
of “00” data. The stop bit following a valid write operation
bit in the control register, apply V
and the program-
CC
initiates the V
programming sequence. Bring WP
ming voltage, V , to the WP pin and 2 byte address and
TRIP
P
LOW to complete the operation.
1 byte of “00” data. The stop bit of a valid write operation
initiates the V
programming sequence. Bring WP
TRIP
LOW to complete the operation.
Figure 2. Reset V
Level Sequence (V > 3V. WP = 12–15V, WEL bit set)
CC
TRIP
VP = 12-15V
WP
0 1 2 3 4 5 6 7
0 1 2 3 4 5 6 7
0 1 2 3 4 5 6 7
0 1 2 3 4 5 6 7
SCL
SDA
A0h
00h
03h
00h
Figure 3. Sample V
Reset Circuit
TRIP
VP
SOIC
Adjust
4.7K
µC
1
2
3
4
8
7
6
5
RESET
Run
X4163
VTRIP
Adj.
SCL
SDA
FN8120 Rev 2.00
November 26, 2007
Page 6 of 22
X4163, X4165
Figure 4. V
Programming Sequence
TRIP
VTRIP Programming
Execute
Reset VTRIP
Sequence
Set VCC = VCC Applied =
Desired VTRIP
New VCC Applied =
Old VCC Applied + Error
New VCC Applied =
Old VCC Applied - Error
Execute
Set VTRIP
Sequence
Execute
Reset VTRIP
Sequence
Apply 5V to VCC
Decrement VCC
(VCC = VCC - 50mV)
NO
RESET pin
goes active?
YES
Error –Emax
Error Emax
Measured VTRIP
Desired VTRIP
-
–Emax < Error < Emax
DONE
Emax = Maximum Allowed VTRIP Error
Control Register
The user must issue a stop after sending this byte to the
register to initiate the nonvolatile cycle that stores WD1,
and WD0. The X4163, X4165 will not acknowledge any
data bytes written after the first byte is entered.
The Control Register provides the user a mechanism for
changing the Block Lock and Watchdog Timer settings.
The Block Lock and Watchdog Timer bits are nonvolatile
and do not change when power is removed.
The state of the Control Register can be read at any time
by performing a random read at address FFFFh. Only
one byte is read by each register read operation. The
X4163, X4165 resets itself after the first byte is read.
The master should supply a stop condition to be consis-
tent with the bus protocol, but a stop is not required to
end this operation.
The Control Register is accessed at address FFFFh. It
can only be modified by performing a byte write opera-
tion directly to the address of the register and only one
data byte is allowed for each register write operation.
Prior to writing to the Control Register, the WEL and
RWEL bits must be set using a two step process, with
the whole sequence requiring 3 steps. See "Writing to
the Control Register" below.
7
6
5
4
3
2
1
0
WPEN WD1 WD0 BP1 BP0 RWEL WEL BP2
FN8120 Rev 2.00
November 26, 2007
Page 7 of 22
X4163, X4165
BP2, BP1, BP0: Block Protect Bits (Nonvolatile)
ers up again. Writes to the WEL bit do not cause a non-
volatile write cycle, so the device is ready for the next
operation immediately after the stop condition.
The Block Protect Bits, BP2, BP1 and BP0, determine
which blocks of the array are write protected. A write to a
protected block of memory is ignored. The block protect
bits will prevent write operations to the following seg-
ments of the array.
WD1, WD0: Watchdog Timer Bits
The bits WD1 and WD0 control the period of the Watch-
dog Timer. The options are shown below.
Protected Addresses
(Size)
Array Lock
None
WD1
WD0
Watchdog Time Out Period
1.4 seconds
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
None (factory setting)
None
0
0
1
1
0
1
0
1
None
600 milliseconds
None
None
200 milliseconds
0000h - 7FFh (2K bytes)
000h - 03Fh (64 bytes)
000h - 07Fh (128 bytes)
000h - 0FFh (256 bytes)
000h - 1FFh (512 bytes)
Full Array (All)
First Page (P1)
First 2 pgs (P2)
First 4 pgs (P4)
First 8 pgs (P8)
disabled (factory setting)
Write Protect Enable
These devices have an advanced Block Lock scheme
that protects one of five blocks of the array when
enabled. It provides hardware write protection through
the use of a WP pin and a nonvolatile Write Protect
Enable (WPEN) bit.
RWEL: Register Write Enable Latch (Volatile)
The RWEL bit must be set to “1” prior to a write to the
Control Register.
The Write Protect (WP) pin and the Write Protect Enable
(WPEN) bit in the Control Register control the program-
mable Hardware Write Protect feature. Hardware Write
Protection is enabled when the WP pin and the WPEN
bit are HIGH and disabled when either the WP pin or the
WPEN bit is LOW. When the chip is Hardware Write Pro-
tected, nonvolatile writes to the block protected sections
in the memory array cannot be written and the block pro-
tect bits cannot be changed. Only the sections of the
memory array that are not block protected can be writ-
ten. Note that since the WPEN bit is write protected, it
cannot be changed back to a LOW state; so write pro-
tection is enabled as long as the WP pin is held HIGH.
WEL: Write Enable Latch (Volatile)
The WEL bit controls the access to the memory and to
the Register during a write operation. This bit is a volatile
latch that powers up in the LOW (disabled) state. While
the WEL bit is LOW, writes to any address, including any
control registers will be ignored (no acknowledge will be
issued after the Data Byte). The WEL bit is set by writing
a “1” to the WEL bit and zeroes to the other bits of the
control register. Once set, WEL remains set until either it
is reset to 0 (by writing a “0” to the WEL bit and zeroes to
the other bits of the control register) or until the part pow-
Table 1. Write Protect Enable Bit and WP Pin Function
Memory Array not
Block Protected
Memory Array Block
WP
WPEN
Protected
WPEN Bit
Writes OK
Protection
Software
LOW
HIGH
HIGH
X
0
1
Writes OK
Writes OK
Writes OK
Writes Blocked
Writes Blocked
Writes Blocked
Writes OK
Software
Writes Blocked
Hardware
FN8120 Rev 2.00
November 26, 2007
Page 8 of 22
X4163, X4165
Writing to the Control Register
– The RWEL bit cannot be reset without writing to the
nonvolatile control bits in the control register, power
cycling the device or attempting a write to a write pro-
tected block.
Changing any of the nonvolatile bits of the control regis-
ter requires the following steps:
– Write a 02H to the Control Register to set the Write
Enable Latch (WEL). This is a volatile operation, so
there is no delay after the write. (Operation preceeded
by a start and ended with a stop).
To illustrate, a sequence of writes to the device consist-
ing of [02H, 06H, 02H] will reset all of the nonvolatile bits
in the Control Register to 0. A sequence of [02H, 06H,
06H] will leave the nonvolatile bits unchanged and the
RWEL bit remains set.
– Write a 06H to the Control Register to set both the
Register Write Enable Latch (RWEL) and the WEL bit.
This is also a volatile cycle. The zeros in the data byte
are required. (Operation preceeded by a start and
ended with a stop).
SERIAL INTERFACE
Serial Interface Conventions
– Write a value to the Control Register that has all the
control bits set to the desired state. This can be repre-
sented as 0xys t01r in binary, where xy are the WD
bits. (Operation preceeded by a start and ended with a
stop). Since this is a nonvolatile write cycle it will take
up to 10ms to complete. The RWEL bit is reset by this
cycle and the sequence must be repeated to change
the nonvolatile bits again. If bit 2 is set to ‘1’ in this
third step (0xys t11r) then the RWEL bit is set, but the
BP2, BP1, BP0, WD1 and WD0 bits remain
The device supports a bidirectional bus oriented proto-
col. The protocol defines any device that sends data
onto the bus as a transmitter, and the receiving device
as the receiver. The device controlling the transfer is
called the master and the device being controlled is
called the slave. The master always initiates data trans-
fers, and provides the clock for both transmit and receive
operations. Therefore, the devices in this family operate
as slaves in all applications.
unchanged. Writing a second byte to the control regis-
ter is not allowed. Doing so aborts the write operation
and returns a NACK.
Serial Clock and Data
Data states on the SDA line can change only during SCL
LOW. SDA state changes during SCL HIGH are
reserved for indicating start and stop conditions. See
Figure 5.
– A read operation occurring between any of the previ-
ous operations will not interrupt the register write oper-
ation.
Figure 5. Valid Data Changes on the SDA Bus
SCL
SDA
Data Stable
Data Change
Data Stable
FN8120 Rev 2.00
November 26, 2007
Page 9 of 22
X4163, X4165
Figure 6. Valid Start and Stop Conditions
SCL
SDA
Start
Stop
Serial Start Condition
eight bits. During the ninth clock cycle, the receiver will
pull the SDA line LOW to acknowledge that it received
the eight bits of data. Refer to Figure 7.
All commands are preceded by the start condition, which
is a HIGH to LOW transition of SDA when SCL is HIGH.
The device continuously monitors the SDA and SCL
lines for the start condition and will not respond to any
command until this condition has been met. See Figure
6.
The device will respond with an acknowledge after rec-
ognition of a start condition and if the correct Device
Identifier and Select bits are contained in the Slave
Address Byte. If a write operation is selected, the device
will respond with an acknowledge after the receipt of
each subsequent eight bit word. The device will
acknowledge all incoming data and address bytes,
except for the Slave Address Byte when the Device
Identifier and/or Select bits are incorrect.
Serial Stop Condition
All communications must be terminated by a stop condi-
tion, which is a LOW to HIGH transition of SDA when SCL
is HIGH. The stop condition is also used to place the
device into the Standby power mode after a read
sequence. A stop condition can only be issued after the
transmitting device has released the bus. See Figure 6.
In the read mode, the device will transmit eight bits of
data, release the SDA line, then monitor the line for an
acknowledge. If an acknowledge is detected and no stop
condition is generated by the master, the device will con-
tinue to transmit data. The device will terminate further
data transmissions if an acknowledge is not detected.
The master must then issue a stop condition to return
the device to Standby mode and place the device into a
known state.
Serial Acknowledge
Acknowledge is a software convention used to indicate
successful data transfer. The transmitting device, either
master or slave, will release the bus after transmitting
Figure 7. Acknowledge Response From Receiver
SCL from
Master
1
8
9
Data Output
from
Transmitter
Data Output
from Receiver
Start
Acknowledge
FN8120 Rev 2.00
November 26, 2007
Page 10 of 22
X4163, X4165
Figure 8. Byte Write Sequence
S
Signals from
t
S
t
o
p
the Master
a
r
Slave
Address
Word Address
Byte 1
Word Address
Byte 0
Data
t
SDA Bus
1 0 1 0
0
A
C
K
A
C
K
A
C
K
A
C
K
Signals from
the Slave
Serial Write Operations
BYTE WRITE
Page Write
The device is capable of a page write operation. It is initi-
ated in the same manner as the byte write operation; but
instead of terminating the write cycle after the first data
byte is transferred, the master can transmit an unlimited
number of 8-bit bytes. After the receipt of each byte, the
device will respond with an acknowledge, and the
address is internally incremented by one. The page
address remains constant. When the counter reaches
the end of the page, it “rolls over” and goes back to ‘0’ on
the same page. This means that the master can write 64
bytes to the page starting at any location on that page. If
the master begins writing at location 60, and loads 12-
bytes, then the first 4-bytes are written to locations 60
through 63, and the last 8-bytes are written to locations 0
through 7. Afterwards, the address counter would point
to location 8 of the page that was just written. If the mas-
ter supplies more than 64-bytes of data, then new data
over-writes the previous data, one byte at a time.
For a write operation, the device requires the Slave
Address Byte and a Word Address Byte. This gives the
master access to any one of the words in the array.
After receipt of the Word Address Byte, the device
responds with an acknowledge, and awaits the next
eight bits of data. After receiving the 8 bits of the Data
Byte, the device again responds with an acknowledge.
The master then terminates the transfer by generating
a stop condition, at which time the device begins the
internal write cycle to the nonvolatile memory. During
this internal write cycle, the device inputs are disabled,
so the device will not respond to any requests from the
master. The SDA output is at high impedance. See Fig-
ure 8.
A write to a protected block of memory will suppress the
acknowledge bit.
Figure 9. Page Write Operation
(1 < n < 64)
S
t
a
r
t
S
t
o
p
Signals from
the Master
Data
(1)
Data
(n)
Word Address
Byte 1
Word Address
Byte 0
Slave
Address
SDA Bus
1 0 1 0
0
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
Signals from
the Slave
FN8120 Rev 2.00
November 26, 2007
Page 11 of 22
X4163, X4165
Figure 10. Writing 12-bytes to a 64-byte page starting at location 60.
8 Bytes
4 Bytes
Address Pointer
Ends Here
Addr = 8
Address
Address
= 7
Address
n-1
60
The master terminates the Data Byte loading by issuing a
stop condition, which causes the device to begin the non-
volatile write cycle. As with the byte write operation, all
inputs are disabled until completion of the internal write
cycle. See Figure 9 for the address, acknowledge, and
data transfer sequence.
Figure 11. Acknowledge Polling Sequence
Byte load completed
by issuing STOP.
Enter ACK Polling
Issue START
Stops and Write Modes
Stop conditions that terminate write operations must be
sent by the master after sending at least 1 full data byte
plus the subsequent ACK signal. If a stop is issued in the
middle of a data byte, or before 1 full data byte plus its
associated ACK is sent, then the device will reset itself
without performing the write. The contents of the array
will not be effected.
Issue Slave Address
Byte (Read or Write)
Issue STOP
NO
ACK
returned?
Acknowledge Polling
YES
The disabling of the inputs during nonvolatile cycles can
be used to take advantage of the typical 5ms write cycle
time. Once the stop condition is issued to indicate the
end of the master’s byte load operation, the device initi-
ates the internal nonvolatile cycle. Acknowledge polling
can be initiated immediately. To do this, the master
issues a start condition followed by the Slave Address
Byte for a write or read operation. If the device is still
busy with the nonvolatile cycle then no ACK will be
returned. If the device has completed the write opera-
tion, an ACK will be returned and the host can then pro-
ceed with the read or write operation. Refer to the flow
chart in Figure 11.
Nonvolatile Cycle
complete. Continue
command sequence?
NO
Issue STOP
YES
Continue Normal
Read or Write
Command Sequence
PROCEED
FN8120 Rev 2.00
November 26, 2007
Page 12 of 22
X4163, X4165
Figure 12. Current Address Read Sequence
S
t
a
r
Signals from
the Master
S
t
o
p
Slave
Address
t
SDA Bus
1 0 1 0
1
A
C
K
Signals from
the Slave
Data
Serial Read Operations
Random Read
Read operations are initiated in the same manner as
write operations with the exception that the R/W bit of
the Slave Address Byte is set to one. There are three
basic read operations: Current Address Reads, Random
Reads, and Sequential Reads.
Random read operation allows the master to access any
memory location in the array. Prior to issuing the Slave
Address Byte with the R/W bit set to one, the master
must first perform a “dummy” write operation. The mas-
ter issues the start condition and the Slave Address
Byte, receives an acknowledge, then issues the Word
Address Bytes. After acknowledging receipts of the
Word Address Bytes, the master immediately issues
another start condition and the Slave Address Byte with
the R/W bit set to one. This is followed by an acknowl-
edge from the device and then by the eight bit word. The
master terminates the read operation by not responding
with an acknowledge and then issuing a stop condition.
Refer to Figure 13 for the address, acknowledge, and
data transfer sequence.
Current Address Read
Internally the device contains an address counter that
maintains the address of the last word read incremented
by one. Therefore, if the last read was to address n, the
next read operation would access data from address
n+1. On power up, the address of the address counter is
undefined, requiring a read or write operation for initial-
ization.
Upon receipt of the Slave Address Byte with the R/W bit
set to one, the device issues an acknowledge and then
transmits the eight bits of the Data Byte. The master
terminates the read operation when it does not respond
with an acknowledge during the ninth clock and then
issues a stop condition. Refer to Figure 12 for the
address, acknowledge, and data transfer sequence.
There is a similar operation, called “Set Current
Address” where the device does no operation, but enters
a new address into the address counter if a stop is
issued instead of the second start shown in Figure 13.
The device goes into standby mode after the stop and all
bus activity will be ignored until a start is detected. The
next Current Address Read operation reads from the
newly loaded address. This operation could be useful if
the master knows the next address it needs to read, but
is not ready for the data.
It should be noted that the ninth clock cycle of the read
operation is not a “don’t care.” To terminate a read oper-
ation, the master must either issue a stop condition
during the ninth cycle or hold SDA HIGH during the ninth
clock cycle and then issue a stop condition.
Figure 13. Random Address Read Sequence
S
S
Signals from
the Master
t
a
r
S
t
o
p
t
a
r
Slave
Address
Word Address
Byte 1
Word Address
Byte 0
Slave
Address
t
t
SDA Bus
1 0 1 0
0
1
A
C
K
A
C
K
A
C
K
A
C
K
Signals from
the Slave
Data
FN8120 Rev 2.00
November 26, 2007
Page 13 of 22
X4163, X4165
Figure 14. Sequential Read Sequence
S
t
o
p
Signals from
the Master
Slave
Address
A
C
K
A
C
K
A
C
K
SDA Bus
1
A
C
K
Signals from
the Slave
Data
(2)
Data
(n-1)
Data
(1)
Data
(n)
(n is any integer greater than 1)
Sequential Read
X4163, X4165 Addressing
SLAVE ADDRESS BYTE
Sequential reads can be initiated as either a current
address read or random address read. The first Data Byte
is transmitted as with the other modes; however, the mas-
ter now responds with an acknowledge, indicating it
requires additional data. The device continues to output
data for each acknowledge received. The master termi-
nates the read operation by not responding with an
acknowledge and then issuing a stop condition.
Following a start condition, the master must output a
Slave Address Byte. This byte consists of several parts:
– a device type identifier that is ‘1010’ to access the
array.
– one bits of ‘0’.
– next two bits are the device address.
The data output is sequential, with the data from
address n followed by the data from address n + 1. The
address counter for read operations increments through
all page and column addresses, allowing the entire
memory contents to be serially read during one opera-
tion. At the end of the address space the counter “rolls
– one bit of the slave command byte is a R/W bit. The
R/W bit of the Slave Address Byte defines the opera-
tion to be performed. When the R/W bit is a one, then
a read operation is selected. A zero selects a write
operation. Refer to Figure 15.
over” to address 0000 and the device continues to out-
H
– After loading the entire Slave Address Byte from the SDA
bus, the device compares the input slave byte data to the
proper slave byte. Upon a correct compare, the device
outputs an acknowledge on the SDA line.
put data for each acknowledge received. Refer to Figure
14 for the acknowledge and data transfer sequence.
Word Address
The word address is either supplied by the master or
obtained from an internal counter. The internal counter is
undefined on a power up condition.
FN8120 Rev 2.00
November 26, 2007
Page 14 of 22
X4163, X4165
Figure 15. X4163, X4165 Addressing
Device Identifier
Device Select
1
0
1
0
0
S1
S0
R/W
Slave Address Byte
High Order Word Address
A10
(X4)
A9
(X3)
A8
(X2)
0
0
0
0
0
Word Address Byte 0–16K
Low Order Word Address
A7
(X1)
A6
(X0)
A5
(Y5)
A4
(Y4)
A3
(Y3)
A2
(Y2)
A1
(Y1)
A0
(Y0)
Word Address Byte 0 for all options
D7
D6
D5
D4
D3
D2
D1
D0
Data Byte for all options
Operational Notes
– Communication to the device is inhibited while
RESET/RESET is active and any in-progress commu-
nication is terminated.
The device powers-up in the following state:
– The device is in the low power standby state.
– Block Lock bits can protect sections of the memory
array from write operations.
– The WEL bit is set to ‘0’. In this state it is not possible
to write to the device.
SYMBOL TABLE
– SDA pin is the input mode.
– RESET/RESET Signal is active for t
.
PURST
WAVEFORM
INPUTS
OUTPUTS
Data Protection
Must be
steady
Will be
steady
The following circuitry has been included to prevent
inadvertent writes:
May change
from LOW
to HIGH
Will change
from LOW
to HIGH
– The WEL bit must be set to allow write operations.
– The proper clock count and bit sequence is required
prior to the stop bit in order to start a nonvolatile write
cycle.
May change
from HIGH
to LOW
Will change
from HIGH
to LOW
Don’t Care:
Changes
Allowed
Changing:
State Not
Known
– A three step sequence is required before writing into
the Control Register to change Watchdog Timer or
Block Lock settings.
N/A
Center Line
is High
Impedance
– The WP pin, when held HIGH, and WPEN bit at logic
HIGH will prevent all writes to the Control Register.
FN8120 Rev 2.00
November 26, 2007
Page 15 of 22
X4163, X4165
ABSOLUTE MAXIMUM RATINGS
COMMENT
Temperature under bias ................... -65°C to+135°C
Storage temperature ........................ -65°C to+150°C
Voltage on any pin with respect to VSS... -1.0V to +7V
D.C. output current...............................................5mA
Lead temperature (soldering, 10s) .................... 300°C
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only; functional operation of the
device (at these or any other conditions above those
listed in the operational sections of this specification) is
not implied. Exposure to absolute maximum rating condi-
tions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
Temperature
Commercial
Industrial
Min.
0°C
Max.
70°C
Option
Supply Voltage Limits
2.7V to 5.5V
-2.7 and -2.7A
Blank and -4.5A
-40°C
+85°C
4.5V to 5.5V
D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.)
V
= 2.7 to 5.5V
CC
Symbol
Parameter
Min
Max
1.0
3.0
1
Unit
mA
mA
µA
Test Conditions
(1)
ICC1
Active Supply Current Read
Active Supply Current Write
Standby Current DC (WDT off)
VIL = VCC x 0.1, VIH = VCC x 0.9
fSCL = 400kHz, SDA = Commands
(1)
ICC2
(2)
ISB
VSDA = VSCL = VSB
Others = GND or VSB
(2)
ISB
Standby Current DC (WDT on)
20
µA
VSDA=VSCL=VSB
Others = GND or VSB
ILI
Input Leakage Current
Output Leakage Current
10
10
µA
µA
VIN = GND to VCC
ILO
VSDA = GND to VCC
Device is in Standby(2)
(3)
VIL
Input LOW Voltage
Input nonvolatile
-0.5
VCC x 0.3
V
V
(3)
VIH
VCC x 0.7
VCC + 0.5
VHYS
Schmitt Trigger Input Hysteresis
Fixed input level
0.2
V
V
VCC related level .05 x VCC
VOL
Output LOW Voltage
0.4
V
IOL = 3.0mA (2.7- 5.5V)
Notes: (1) The device enters the Active state after any start, and remains active until: 9 clock cycles later if the Device Select Bits in the Slave
Address Byte are incorrect; 200ns after a stop ending a read operation; or tWC after a stop ending a write operation.
(2) The device goes into Standby: 200ns after any stop, except those that initiate a nonvolatile write cycle; tWC after a stop that initiates a
nonvolatile cycle; or 9 clock cycles after any start that is not followed by the correct Device Select Bits in the Slave Address Byte.
(3) VIL Min. and VIH Max. are for reference only and are not tested.
FN8120 Rev 2.00
November 26, 2007
Page 16 of 22
X4163, X4165
CAPACITANCE (T = 25°C, f = 1.0 MHz, V = 5V)
A
CC
Symbol
Parameter
Max.
Unit
pF
Test Conditions
VOUT = 0V
(4)
COUT
Output Capacitance (SDA, RST/RST)
Input Capacitance (SCL, WP)
8
6
(4)
CIN
pF
VIN = 0V
Notes: (4) This parameter is periodically sampled and not 100% tested.
EQUIVALENT A.C. LOAD CIRCUIT
A.C. TEST CONDITIONS
Input pulse levels
0.1VCC to 0.9VCC
10ns
5V
Input rise and fall times
Input and output timing levels 0.5VCC
Output load Standard output load
For VOL= 0.4V
1533
and IOL = 3 mA
SDA
or
RESET
100pF
A.C. CHARACTERISTICS (Over recommended operating conditions, unless otherwise specified)
Symbol
fSCL
Parameter
Min.
Max.
Unit
kHz
ns
µs
µs
µs
µs
µs
µs
ns
µs
µs
ns
ns
ns
µs
µs
pF
SCL Clock Frequency
0
50
400
tIN
Pulse width Suppression Time at inputs
SCL LOW to SDA Data Out Valid
Time the bus free before start of new transmission
Clock LOW Time
tAA
0.1
0.9
tBUF
1.3
tLOW
tHIGH
tSU:STA
tHD:STA
tSU:DAT
tHD:DAT
tSU:STO
tDH
1.3
Clock HIGH Time
0.6
Start Condition Setup Time
Start Condition Hold Time
Data In Setup Time
0.6
0.6
100
0
Data In Hold Time
Stop Condition Setup Time
Data Output Hold Time
0.6
50
tR
SDA and SCL Rise Time
SDA and SCL Fall Time
WP Setup Time
20 + .1Cb
20 + .1Cb
0.6
300
300
tF
tSU:WP
tHD:WP
Cb
WP Hold Time
0
Capacitive load for each bus line
400
Notes: (1) Typical values are for TA = +25°C and VCC = 5.0V
(2) Cb = total capacitance of one bus line in pF.
FN8120 Rev 2.00
November 26, 2007
Page 17 of 22
X4163, X4165
TIMING DIAGRAMS
Bus Timing
tF
tR
tHIGH
tLOW
SCL
tSU:STA
SDA IN
tSU:DAT
tHD:DAT
tSU:STO
tHD:STA
tAA tDH
tBUF
SDA OUT
WP Pin Timing
START
SCL
Clk 1
Clk 9
Slave Address Byte
SDA IN
WP
tSU:WP
tHD:WP
Write Cycle Timing
SCL
8th bit of Last Byte
ACK
SDA
tWC
Stop
Start
Condition
Condition
Nonvolatile Write Cycle Timing
Symbol
(1)
Parameter
Min.
Typ.
Max.
Unit
(1)
tWC
Write Cycle Time
5
10
ms
Notes: (1) tWC is the time from a valid stop condition at the end of a write sequence to the end of the self-timed internal nonvolatile write cycle. It is
the minimum cycle time to be allowed for any nonvolatile write by the user, unless Acknowledge Polling is used.
FN8120 Rev 2.00
November 26, 2007
Page 18 of 22
X4163, X4165
Power-Up and Power-Down Timing
VTRIP
VCC
tPURST
0 Volts
tPURST
tF
tR
tRPD
VRVALID
RESET
(X4165)
VRVALID
RESET
(X4163)
RESET Output Timing
Symbol
Parameter
Min.
Typ.
Max.
Unit
VTRIP
Reset Trip Point Voltage, X4163, X4165-4.5A
Reset Trip Point Voltage, X4163, X4165
Reset Trip Point Voltage, X4163, X4165-2.7A
Reset Trip Point Voltage, X4163, X4165-2.7
4.5
4.62
4.38
2.92
2.62
4.75
4.5
3.0
V
4.25
2.85
2.55
2.7
tPURST
Power-up Reset Time Out
VCC Detect to Reset/Output
VCC Fall Time
100
250
400
500
ms
ns
µs
µs
V
(8)
tRPD
(8)
tF
100
100
1
(8)
tR
VCC Rise Time
VRVALID
Reset Valid VCC
Notes: (8) This parameter is periodically sampled and not 100% tested.
SDA vs. RESET Timing
tRSP
tRSP>tWDO
tRST
tRSP>tWDO
tRST
tRSP<tWDO
SCL
SDA
RESET
Note: All inputs are ignored during the active reset period (tRST).
FN8120 Rev 2.00
November 26, 2007
Page 19 of 22
X4163, X4165
RESET Output Timing
Symbol
Parameter
Min.
Typ.
Max.
Units
tWDO
Watchdog Time Out Period,
WD1 = 1, WD0 = 1 (factory setting)
WD1 = 1, WD0 = 0
OFF
250
650
1.5
100
450
1
400
850
2
ms
ms
sec
WD1 = 0, WD0 = 1
WD1 = 0, WD0 = 0
tRST
Reset Time Out
100
250
400
ms
V
Programming Timing Diagram (WEL = 1)
TRIP
VCC
(VTRIP
VTRIP
)
tTSU
tTHD
VP
WP
tVPH
tVPS
tVPO
SCL
SDA
tRP
01h or 03h
00h
00h
A0h
V
Programming Parameters
TRIP
Parameter
tVPS
Description
Min. Max. Unit
VTRIP Program Enable Voltage Setup time
VTRIP Program Enable Voltage Hold time
VTRIP Setup time
1
1
µs
µs
µs
ms
ms
µs
ms
V
tVPH
tTSU
1
tTHD
VTRIP Hold (stable) time
10
tWC
VTRIP Write Cycle Time
10
tVPO
tRP
VTRIP Program Enable Voltage Off time (Between successive adjustments)
VTRIP Program Recovery Period (Between successive adjustments)
Programming Voltage
0
10
VP
15
18
VTRAN
Vta1
VTRIP Programmed Voltage Range
2.55
-0.1
-25
4.75
+0.4
+25
V
Initial VTRIP Program Voltage accuracy (VCC applied - VTRIP) (Programmed at 25°C.)
V
Vta2
Subsequent VTRIP Program Voltage accuracy [(VCC applied - Vta1) - VTRIP
Programmed at 25°C.]
.
mV
Vtr
VTRIP Program Voltage repeatability (Successive program operations. Programmed
at 25°C.)
-25
-25
+25
+25
mV
mV
Vtv
VTRIP Program variation after programming (0-75°C). (Programmed at 25°C.)
VTRIP programming parameters are periodically sampled and are not 100% tested.
FN8120 Rev 2.00
November 26, 2007
Page 20 of 22
X4163, X4165
Small Outline Package Family (SO)
A
D
h X 45°
(N/2)+1
N
A
PIN #1
I.D. MARK
E1
E
c
SEE DETAIL “X”
1
(N/2)
B
L1
0.010 M
C A B
e
H
C
A2
A1
GAUGE
PLANE
SEATING
PLANE
0.010
L
4° ±4°
0.004 C
b
0.010 M
C
A
B
DETAIL X
MDP0027
SMALL OUTLINE PACKAGE FAMILY (SO)
SO16
(0.150”)
SO16 (0.300”)
(SOL-16)
SO20
SO24
(SOL-24)
SO28
(SOL-28)
SYMBOL
SO-8
0.068
0.006
0.057
0.017
0.009
0.193
0.236
0.154
0.050
0.025
0.041
0.013
8
SO-14
0.068
0.006
0.057
0.017
0.009
0.341
0.236
0.154
0.050
0.025
0.041
0.013
14
(SOL-20)
0.104
0.007
0.092
0.017
0.011
0.504
0.406
0.295
0.050
0.030
0.056
0.020
20
TOLERANCE
MAX
NOTES
A
A1
A2
b
0.068
0.006
0.057
0.017
0.009
0.390
0.236
0.154
0.050
0.025
0.041
0.013
16
0.104
0.007
0.092
0.017
0.011
0.406
0.406
0.295
0.050
0.030
0.056
0.020
16
0.104
0.007
0.092
0.017
0.011
0.606
0.406
0.295
0.050
0.030
0.056
0.020
24
0.104
0.007
0.092
0.017
0.011
0.704
0.406
0.295
0.050
0.030
0.056
0.020
28
-
0.003
0.002
0.003
0.001
0.004
0.008
0.004
Basic
-
-
-
c
-
D
1, 3
E
-
E1
e
2, 3
-
L
0.009
Basic
-
L1
h
-
Reference
Reference
-
N
-
Rev. L 2/01
NOTES:
1. Plastic or metal protrusions of 0.006” maximum per side are not included.
2. Plastic interlead protrusions of 0.010” maximum per side are not included.
3. Dimensions “D” and “E1” are measured at Datum Plane “H”.
4. Dimensioning and tolerancing per ASME Y14.5M-1994
FN8120 Rev 2.00
November 26, 2007
Page 21 of 22
X4163, X4165
Thin Shrink Small Outline Plastic Packages (TSSOP)
M8.173
N
8 LEAD THIN SHRINK NARROW BODY SMALL OUTLINE
PLASTIC PACKAGE
INDEX
AREA
0.25(0.010)
M
B M
E
E1
-B-
INCHES
MIN
MILLIMETERS
GAUGE
PLANE
SYMBOL
MAX
0.047
0.006
0.051
0.0118
0.0079
0.120
0.177
MIN
-
MAX
1.20
0.15
1.05
0.30
0.20
3.05
4.50
NOTES
A
A1
A2
b
-
-
1
2
3
0.002
0.031
0.0075
0.0035
0.116
0.169
0.05
0.80
0.19
0.09
2.95
4.30
-
L
0.25
0.010
-
0.05(0.002)
SEATING PLANE
A
9
-A-
D
c
-
D
3
-C-
E1
e
4
A2
e
A1
0.026 BSC
0.65 BSC
-
c
b
0.10(0.004)
E
0.246
0.256
6.25
0.45
6.50
0.75
-
0.10(0.004) M
C
A M B S
L
0.0177
0.0295
6
N
8
8
7
NOTES:
0o
8o
0o
8o
-
1. These package dimensions are within allowable dimensions of
JEDEC MO-153-AC, Issue E.
Rev. 1 12/00
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm
(0.006 inch) per side.
4. Dimension “E1” does not include interlead flash or protrusions. Inter-
lead flash and protrusions shall not exceed 0.15mm (0.006 inch) per
side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “b” does not include dambar protrusion. Allowable dambar
protrusion shall be 0.08mm (0.003 inch) total in excess of “b” dimen-
sion at maximum material condition. Minimum space between protru-
sion and adjacent lead is 0.07mm (0.0027 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact. (Angles in degrees)
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Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such
modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are
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FN8120 Rev 2.00
November 26, 2007
Page 22 of 22
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