X5043S8Z-2.7AT1 [RENESAS]
CPU Supervisor with 4k SPI EEPROM; MSOP8, PDIP8, SOIC8; Temp Range: See Datasheet;
| 型号： | X5043S8Z-2.7AT1 |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | CPU Supervisor with 4k SPI EEPROM; MSOP8, PDIP8, SOIC8; Temp Range: See Datasheet 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 光电二极管 |
| 文件： | 总21页 (文件大小：839K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATASHEET
X5043, X5045
4K, 512 x 8 Bit CPU Supervisor with 4K SPI EEPROM
FN8126
Rev 3.00
September 23, 2015
These devices combine four popular functions, Power-on
Reset Control, Watchdog Timer, Supply Voltage Supervision,
and Block Lock Protect Serial EEPROM Memory in one
package. This combination lowers system cost, reduces
board space requirements, and increases reliability.
Features
• Low VCC Detection and Reset Assertion
- Four standard reset threshold voltages
4.63V, 4.38V, 2.93V, 2.63V
- Re-program low VCC reset threshold voltage using
special programming sequence.
Applying power to the device activates the power-on reset
circuit which holds RESET/RESET active for a period of
time. This allows the power supply and oscillator to stabilize
before the processor executes code.
- Reset signal valid to VCC = 1V
• Selectable Time Out Watchdog Timer
• Long Battery Life with Low Power Consumption
- <50µA max standby current, watchdog on
- <10µA max standby current, watchdog off
The Watchdog Timer provides an independent protection
mechanism for microcontrollers. When the microcontroller
fails to restart a timer within a selectable time out interval,
the device activates the RESET/RESET signal. The user
selects the interval from three preset values. Once selected,
the interval does not change, even after cycling the power.
• 4Kbits of EEPROM–1M Write Cycle Endurance
• Save Critical Data with Block Lock™ Memory
- Protect 1/4, 1/2, all or none of EEPROM array
The device’s low VCC detection circuitry protects the user’s
system from low voltage conditions, resetting the system
when VCC falls below the minimum VCC trip point.
RESET/RESET is asserted until VCC returns to proper
operating level and stabilizes. Four industry standard VTRIP
thresholds are available, however, Intersil’s unique circuits
allow the threshold to be reprogrammed to meet custom
requirements or to fine-tune the threshold for applications
requiring higher precision.
• Built-in Inadvertent Write Protection
- Write enable latch
- Write protect pin
• SPI Interface - 3.3MHz Clock Rate
• Minimize Programming Time
- 16-byte page write mode
- 5ms write cycle time (typical)
• Available Packages
The memory portion of the device is a CMOS Serial
EEPROM array with Intersil’s block lock protection. The
array is internally organized as 512 x 8. The device features
a Serial Peripheral Interface (SPI) and software protocol
allowing operation on a simple four-wire bus.
- 8 Ld MSOP, 8 Ld SOIC, 8 Ld PDIP
- 14 Ld TSSOP
• Pb-Free Plus Anneal Available (RoHS Compliant)
Applications
The device utilizes Intersil’s proprietary Direct Write™ cell,
providing a minimum endurance of 100,000 cycles and a
minimum data retention of 100 years.
• Communications Equipment
- Routers, Hubs, Switches
- Set Top Boxes
• Industrial Systems
- Process Control
- Intelligent Instrumentation
• Computer Systems
- Desktop Computers
- Network Servers
• Battery Powered Equipment
FN8126 Rev 3.00
Page 1 of 21
September 23, 2015
X5043, X5045
Typical Application
2.7-5.0V
VCC
uC
VCC
10K
X5043
RESET
CS
SCK
SI
RESET
SPI
SO
WP
VSS
VSS
Block Diagram
POR and Low
Voltage Reset
Generation
RESET (X5043)
RESET (X5045)
VCC
+
V
-
TRIP
Reset & Watchdog
Timebase
X5043, X5045
STANDARD VTRIP LEVEL
4.63V (+/-2.5%)
SUFFIX
-4.5A
-4.5
Watchdog
Timer
Reset
Watchdog
Transition
Detector
4.38V (+/-2.5%)
2.93V (+/-2.5%)
-2.7A
-2.7
CS/WDI
SI
Status
Register
Command
Decode &
Control
2.63V (+/-2.5%)
SO
SCK
WP
See “Ordering Information” on page 3. for
more details
For Custom Settings, call Intersil.
EEPROM
Array
4Kbits
Logic
Protect Logic
FN8126 Rev 3.00
Page 2 of 21
September 23, 2015
X5043, X5045
Ordering Information
PART NUMBER
RESET
(ACTIVE LOW)
PART NUMBER
RESET
(ACTIVE HIGH)
TEMP
RANGE
(°C)
PART
MARKING
PART
MARKING
VCC
RANGE
VTRIP
RANGE
PACKAGE
X5043PZ-4.5A (Note) X5043P Z AL X5045PZ-4.5A (Note) X5045P Z AL
X5043PIZ-4.5A (Note) X5043P Z AM X5045PIZ-4.5A (Note) X5045P Z AM
X5043S8Z-4.5A (Note) X5043 Z AL X5045S8Z-4.5A (Note) X5045 Z AL
4.5-5.5V
4.5-4.75
0 to 70
-40 to 85
0 to 70
8 Ld PDIP (Pb-free)
8 Ld PDIP (Pb-free)
8 Ld SOIC (Pb-free)
8 Ld SOIC (Pb-free)
X5043S8IZ-4.5A*
(Note)
X5043 Z AM X5045S8IZ-4.5A*
(Note)
X5045 Z AM
-40 to 85
X5043M8Z-4.5A
(Note)
DBS
X5045M8Z-4.5A (Note) DCB
(No longer available,
recommended
0 to 70
8 Ld MSOP (Pb-free)
replacement:
X5045S8Z-4.5A)
X5043M8IZ-4.5A
(Note)
DBM
X5045M8IZ-4.5A
(Note) (No longer
available,
DBX
-40 to 85
8 Ld MSOP (Pb-free)
recommended
replacement:
X5045S8IZ-4.5A)
X5043PZ (Note)
X5043PIZ (Note)
X5043S8Z* (Note)
X5043S8IZ* (Note)
X5043M8Z (Note)
X5043P Z
X5043P Z I
X5043 Z
X5043 Z I
DBN
X5045PZ (Note)
X5045PIZ (Note)
X5045S8Z* (Note)
X5045S8IZ* (Note)
X5045P Z
X5045P Z I
X5045 Z
4.25-4.5
0 to 70
-40 to 85
0 to 70
8 Ld PDIP (Pb-free)
8 Ld PDIP (Pb-free)
8 Ld SOIC (Pb-free)
8 Ld SOIC (Pb-free)
8 Ld MSOP (Pb-free)
X5045 Z I
-40 to 85
0 to 70
X5045M8Z (Note) (No DBY
longer available,
recommended
replacement:
X5045S8Z)
X5043M8IZ (Note)
DBJ
X5045M8IZ (Note) (No DBT
longer available,
recommended
replacement:
X5045S8IZ-2.7)
-40 to 85
-40 to 85
8 Ld MSOP (Pb-free)
X5043V14IZ (Note)
(No longer available,
recommended
replacement:
X5043V Z I
X5045V14IZ (Note)(No X5045V Z I
longer available or
supported)
14 Ld TSSOP
(Pb-free)
X5043M8IZ)
FN8126 Rev 3.00
Page 3 of 21
September 23, 2015
X5043, X5045
Ordering Information (Continued)
PART NUMBER
RESET
(ACTIVE LOW)
PART NUMBER
RESET
(ACTIVE HIGH)
TEMP
RANGE
(°C)
PART
MARKING
PART
MARKING
VCC
RANGE
VTRIP
RANGE
PACKAGE
X5043PZ-2.7A (Note) X5043P Z AN X5045PZ-2.7A (Note) X5045P Z AN
X5043PIZ-2.7A (Note) X5043P Z AP X5045PIZ-2.7A (Note) X5045P Z AP
2.7-5.5V
2.85-3.0
0 to 70
-40 to 85
0 to 70
8 Ld PDIP (Pb-free)
8 Ld PDIP (Pb-free)
8 Ld SOIC (Pb-free)
X5043S8Z-2.7A*
(Note)
X5043 Z AN X5045S8Z-2.7A (Note) X5045 Z AN
X5043S8IZ-2.7A*
(Note)
X5043 Z AP X5045S8IZ-2.7A (Note) X5045 Z AP
-40 to 85
0 to 70
8 Ld SOIC
(Pb-free)
X5043M8Z-2.7A
(Note)
DBR
DBL
X5045M8Z-2.7A (Note) DCA
(No longer available,
recommended
replacement:
X5045S8Z-2.7A)
8 Ld MSOP (Pb-free)
X5043M8IZ-2.7A*
(Note)
X5045M8IZ-2.7A
(Note) (No longer
available,
DBW
-40 to 85
8 Ld MSOP (Pb-free)
recommended
replacement:
X5045S8IZ-2.7A)
X5043PZ-2.7 (Note)
X5043PIZ-2.7 (Note)
X5043P Z F X5045PZ-2.7 (Note)
X5043P Z G X5045PIZ-2.7 (Note)
X5045P Z F
X5045P Z G
2.55-2.7
0 to 70
-40 to 85
0 to 70
8 Ld PDIP (Pb-free)
8 Ld PDIP (Pb-free)
8 Ld SOIC (Pb-free)
8 Ld SOIC (Pb-free)
8 Ld MSOP (Pb-free)
X5043S8Z-2.7* (Note) X5043 Z F
X5043S8IZ-2.7* (Note) X5043 Z G
X5043M8Z-2.7 (Note) DBP
X5045S8Z-2.7* (Note) X5045 Z F
X5045S8IZ-2.7* (Note) X5045 Z G
-40 to 85
0 to 70
X5045M8Z-2.7 (Note) DBZ
(No longer available,
recommended
replacement:
X5045S8Z-2.7)
X5043M8IZ-2.7*
(Note)
DBK
X5045M8IZ-2.7 (Note) DBU
(No longer available,
recommended
-40 to 85
8 Ld MSOP (Pb-free)
replacement:
X5045S8IZ-2.7)
*Add "-T1" suffix for tape and reel.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
FN8126 Rev 3.00
Page 4 of 21
September 23, 2015
X5043, X5045
Reset (RESET, RESET)
Pin Configuration
X5043, X5045, RESET/RESET is an active low/HIGH, open
drain output which goes active whenever VCC falls below the
minimum VCC sense level. It will remain active until VCC rises
above the minimum VCC sense level for 200ms.
RESET/RESET also goes active if the Watchdog timer is
enabled and CS remains either high or low longer than the
Watchdog time out period. A falling edge of CS will reset the
watchdog timer.
8 Ld SOIC/PDIP/MSOP
V
1
8
CS/WDI
SO
CC
2
3
4
7
6
5
RESET/RESET
X5043, X5045
WP
SCK
SI
V
SS
Pin Names
14 Ld TSSOP
1
SYMBOL
DESCRIPTION
Chip Select Input
Serial Output
V
14
CS
SO
NC
CC
CS/WDI
2
3
4
5
6
7
13
12
RESET/RESET
SO
NC
NC
SI
SCK
Serial Input
X5043, X5045
11
10
9
NC
NC
Serial Clock Input
Write Protect Input
Ground
NC
SCK
SI
WP
WP
VSS
V
8
SS
VCC
Supply Voltage
Reset Output
RESET/RESET
Pin Descriptions
Serial Output (SO)
Principles of Operation
SO is a push/pull serial data output pin. During a read cycle,
data is shifted out on this pin. Data is clocked out by the falling
edge of the serial clock.
Power-on Reset
Application of power to the X5043, X5045 activate a Power-on
Reset Circuit. This circuit pulls the RESET/RESET pin active.
RESET/RESET prevents the system microprocessor from
starting to operate with insufficient voltage or prior to
Serial Input (SI)
SI is the serial data input pin. All opcodes, byte addresses, and
data to be written to the memory are input on this pin. Data is
latched by the rising edge of the serial clock.
stabilization of the oscillator. When VCC exceeds the device
VTRIP value for 200ms (nominal) the circuit releases
RESET/RESET, allowing the processor to begin executing
code.
Serial Clock (SCK)
The Serial Clock controls the serial bus timing for data input
and output. Opcodes, addresses, or data present on the SI pin
is latched on the rising edge of the clock input, while data on
the SO pin changes after the falling edge of the clock input.
Low Voltage Monitoring
During operation, the X5043, X5045 monitor the VCC level and
asserts RESET/RESET if supply voltage falls below a preset
minimum VTRIP. The RESET/RESET signal prevents the
microprocessor from operating in a power fail or brownout
condition. The RESET/RESET signal remains active until the
voltage drops below 1V. It also remains active until VCC returns
and exceeds VTRIP for 200ms.
Chip Select (CS/WDI)
When CS is high, the X5043, X5045 are deselected and the
SO output pin is at high impedance and, unless an internal
write operation is underway, the X5043, X5045 will be in the
standby power mode. CS low enables the X5043, X5045,
placing it in the active power mode. It should be noted that after
power-up, a high to low transition on CS is required prior to the
start of any operation.
Watchdog Timer
The Watchdog Timer circuit monitors the microprocessor
activity by monitoring the WDI input. The microprocessor must
toggle the CS/WDI pin periodically to prevent an active
RESET/RESET signal. The CS/WDI pin must be toggled from
HIGH to LOW prior to the expiration of the watchdog time out
period. The state of two nonvolatile control bits in the Status
Register determines the watchdog timer period. The
microprocessor can change these watchdog bits. With no
microprocessor action, the watchdog timer control bits remain
unchanged, even during total power failure.
Write Protect (WP)
When WP is low, nonvolatile writes to the X5043, X5045 are
disabled, but the part otherwise functions normally. When WP
is held high, all functions, including non volatile writes operate
normally. WP going low while CS is still low will interrupt a write
to the X5043, X5045. If the internal write cycle has already
been initiated, WP going low will have no affect on a write.
FN8126 Rev 3.00
Page 5 of 21
September 23, 2015
X5043, X5045
Threshold Reset Procedure
operation initiates the VTRIP programming sequence. Bring WP
LOW to complete the operation.
V
CC
The X5043, X5045 are shipped with a standard VCC threshold
(VTRIP) voltage. This value will not change over normal
operating and storage conditions. However, in applications
where the standard VTRIP is not exactly right, or if higher
precision is needed in the VTRIP value, the X5043, X5045
threshold may be adjusted. The procedure is described below,
and uses the application of a high voltage control signal.
Note: This operation also writes 00h to array address 01h.
Resetting the V
Voltage
TRIP
This procedure is used to set the VTRIP to a “native” voltage
level. For example, if the current VTRIP is 4.4V and the new
VTRIP must be 4.0V, then the VTRIP must be reset. When VTRIP
is reset, the new VTRIP is something less than 1.7V. This
procedure must be used to set the voltage to a lower value.
Setting the V
Voltage
TRIP
This procedure is used to set the VTRIP to a higher voltage
value. For example, if the current VTRIP is 4.4V and the new
To reset the VTRIP voltage, apply at least 3V to the VCC pin and
tie the WP pin to the programming voltage VP. Then send a
WREN command, followed by a write of Data 00h to address
03h. CS going HIGH on the write operation initiates the VTRIP
programming sequence. Bring WP LOW to complete the
operation.
VTRIP is 4.6V, this procedure will directly make the change. If
the new setting is to be lower than the current setting, then it is
necessary to reset the trip point before setting the new value.
To set the new VTRIP voltage, apply the desired VTRIP threshold
voltage to the VCC pin and tie the WP pin to the programming
voltage VP. Then send a WREN command, followed by a write
of Data 00h to address 01h. CS going HIGH on the write
Note: This operation also writes 00h to array address 03h.
VP = 15-18V
WP
CS
0
1 2 3 4 5 6 7
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
8 Bits
SCK
SI
06h
WREN
02h
00h
03h
Write
Address
Data
FIGURE 2. RESET VTRIP LEVEL SEQUENCE (VCC > 3V. WP = 15–18V)
VP = 15-18V
WP
CS
0
1
2 3
4
5 6 7
0
1
2 3
4
5 6 7 8 9 10 11 12 13 14 15
SCK
8 Bits
SI
06h
02h
00h
01h
WREN
Write
Address
Data
FIGURE 1. SET VTRIP LEVEL SEQUENCE (VCC = DESIRED VTRIP VALUE.)
FN8126 Rev 3.00
September 23, 2015
Page 6 of 21
X5043, X5045
4.7K
VP
µC
RESET
1
2
3
4
8
7
6
5
Adjust
Run
X5043
X5045
SCK
SI
VTRIP
Adj.
SO
CS
FIGURE 3. SAMPLE VTRIP RESET CIRCUIT
VTRIP Programming
Execute
Reset VTRIP
Sequence
Set VCC = VCC Applied =
Desired VTRIP
New VCC Applied
New VCC Applied
Execute
Set VTRIP
Sequence
=
=
Old VCC Applied
Old VCC Applied
- Error
- Error
Apply 5V to VCC
Execute
Reset VTRIP
Sequence
Decrement VCC
(VCC = VCC–10mV)
NO
RESET pin
goes active?
YES
Measured VTRIP
-Desired VTRIP
Error -Emax
Error Emax
-Emax < Error < Emax
DONE
Emax = Maximum Desired Error
FIGURE 4. VTRIP PROGRAMMING SEQUENCE
FN8126 Rev 3.00
September 23, 2015
Page 7 of 21
X5043, X5045
that requires only the instruction byte. There are two read
operations that use the instruction byte to initiate the output
of data. The remainder of the operations require an
instruction byte, an 8-bit address, then data bytes. All
instruction, address and data bits are clocked by the SCK
input. All instructions (Table 1), addresses and data are
transferred MSB first.
SPI Serial Memory
The memory portion of the device is a CMOS Serial
EEPROM array with Intersil’s block lock protection. The array
is internally organized as 512 x 8 bits. The device features a
Serial Peripheral Interface (SPI) and software protocol
allowing operation on a simple four-wire bus.
The device utilizes Intersil’s proprietary Direct Write™ cell,
providing a minimum endurance of 1,000,000 cycles and a
minimum data retention of 100 years.
Clock and Data Timing
Data input on the SI line is latched on the first rising edge of
SCK after CS goes LOW. Data is output on the SO line by
the falling edge of SCK. SCK is static, allowing the user to
stop the clock and then start it again to resume operations
where left off. CS must be LOW during the entire operation.
The device is designed to interface directly with the
synchronous Serial Peripheral Interface (SPI) of many
popular microcontroller families.
The device contains an 8-bit instruction register that controls
the operation of the device. The instruction code is written to
the device via the SI input. There are two write operations
TABLE 1. INSTRUCTION SET
INSTRUCTION NAME
WREN
INSTRUCTION FORMAT*
0000 0110
OPERATION
Set the Write Enable Latch (Enable Write Operations)
Reset the Write Enable Latch (Disable Write Operations)
Read Status Register
WRDI
0000 0100
RSDR
0000 0101
WRSR
0000 0001
Write Status Register (Watchdog and Block Lock)
Read Data from Memory Array Beginning at Selected Address
Write Data to Memory Array Beginning at Selected Address (1 to 16 bytes)
READ
0000 A8011
WRITE
0000 A8010
Note: *Instructions are shown MSB in leftmost position. Instructions are transferred MSB first.
FN8126 Rev 3.00
Page 8 of 21
September 23, 2015
X5043, X5045
The block lock bits, BL0 and BL1, set the level of block lock
protection. These nonvolatile bits are programmed using the
WRSR instruction and allow the user to protect one quarter,
one half, all or none of the EEPROM array. Any portion of the
array that is block lock protected can be read but not written. It
will remain protected until the BL bits are altered to disable
block lock protection of that portion of memory.
Write Enable Latch
The device contains a Write Enable Latch. This latch must be
SET before a Write Operation is initiated. The WREN instruction
will set the latch and the WRDI instruction will reset the latch
(Figure 5). This latch is automatically reset upon a power-up
condition and after the completion of a valid byte, page, or status
register write cycle. The latch is also reset if WP is brought LOW.
When issuing a WREN, WRDI or RDSR commands, it is not
necessary to send a byte address or data.
STATUS REG BITS
ARRAY ADDRESSES PROTECTED
BL1
0
BL0
0
X5043, X5045
None
CS
0
1
$180–$1FF
$100–$1FF
$000–$1FF
1
0
0
1
2
3
4
5
6
7
1
1
SCK
The Watchdog Timer bits, WD0 and WD1, select the Watchdog
Time-out Period. These nonvolatile bits are programmed with
the WRSR instruction.
SI
STATUS REGISTER BITS
WATCHDOG TIME OUT
High Impedance
SO
WD1
WD0
(TYPICAL)
FIGURE 5. WRITE ENABLE/DISABLE LATCH SEQUENCE
(WREN/WRDI INSTRUCTION)
0
0
1
1
0
1
0
1
1.4 seconds
600 milliseconds
200 milliseconds
disabled (factory default)
Status Register
The Status Register contains four nonvolatile control bits and
two volatile status bits. The control bits set the operation of the
watchdog timer and the memory block lock protection. The
Status Register is formatted as shown in “Status Register”.
Read Status Register
To read the Status Register, pull CS low to select the device,
then send the 8-bit RDSR instruction. Then the contents of the
Status Register are shifted out on the SO line, clocked by CLK.
Refer to the Read Status Register Sequence (Figure 6). The
Status Register may be read at any time, even during a Write
Cycle.
Status Register: (Default = 30H)
7
6
5
4
3
2
1
0
0
0
WD1 WD0
BL1
BL0
WEL
WIP
Write Status Register
The Write-In-Progress (WIP) bit is a volatile, read only bit and
indicates whether the device is busy with an internal
nonvolatile write operation. The WIP bit is read using the
RDSR instruction. When set to a “1”, a nonvolatile write
operation is in progress. When set to a “0”, no write is in
progress.
Prior to any attempt to write data into the status register, the
“Write Enable” Latch (WEL) must be set by issuing the WREN
instruction (Figure 5). First pull CS LOW, then clock the WREN
instruction into the device and pull CS HIGH. Then bring CS
LOW again and enter the WRSR instruction followed by 8 bits
of data. These 8 bits of data correspond to the contents of the
status register. The operation ends with CS going HIGH. If CS
does not go HIGH between WREN and WRSR, the WRSR
instruction is ignored.
The Write Enable Latch (WEL) bit indicates the status of the
“write enable” latch. When WEL = 1, the latch is set and when
WEL = 0 the latch is reset. The WEL bit is a volatile, read only
bit. The WREN instruction sets the WEL bit and the WRDS
instruction resets the WEL bit.
TABLE 2. DEVICE PROTECT MATRIX
MEMORY BLOCK
STATUS REGISTER
(BL0, BL1, WD0, WD1)
Protected
WREN CMD
(WEL)
DEVICE PIN (WP)
PROTECTED AREA
Protected
UNPROTECTED AREA
Protected
0
x
x
0
Protected
Protected
Protected
FN8126 Rev 3.00
Page 9 of 21
September 23, 2015
X5043, X5045
TABLE 2. DEVICE PROTECT MATRIX
MEMORY BLOCK
STATUS REGISTER
(BL0, BL1, WD0, WD1)
Writable
WREN CMD
(WEL)
DEVICE PIN (WP)
PROTECTED AREA
Protected
UNPROTECTED AREA
Writable
1
1
CS
SCK
SI
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14
15
Instruction
Data Out
High Impedance
SO
7
6
5
4
3
2
1
0
MSB
FIGURE 6. READ STATUS REGISTER SEQUENCE
CS
0
1
2
3
4
5
6
7
8
7
9
6
10 11 12 13 14 15
SCK
Data Byte
Instruction
5
4
3
2
1
0
SI
High Impedance
FIGURE 7. WRITE STATUS REGISTER SEQUENCE
SO
FN8126 Rev 3.00
Page 10 of 21
September 23, 2015
X5043, X5045
byte to be written is clocked in. If it is brought HIGH at any
other time, the write operation will not be completed (Figure 9).
Read Memory Array
When reading from the EEPROM memory array, CS is first
pulled low to select the device. The 8-bit READ instruction is
transmitted to the device, followed by the 8-bit address. Bit 3 of
the READ instruction selects the upper or lower half of the
device. After the READ opcode and address are sent, the data
stored in the memory at the selected address is shifted out on
the SO line. The data stored in memory at the next address
can be read sequentially by continuing to provide clock pulses.
The address is automatically incremented to the next higher
address after each byte of data is shifted out. When the highest
address is reached, the address counter rolls over to address
000h allowing the read cycle to be continued indefinitely. The
read operation is terminated by taking CS high. Refer to the
Read EEPROM Array Sequence (Figure 8).
While the write is in progress following a status register or
memory array write sequence, the Status Register may be
read to check the WIP bit. WIP is HIGH while the nonvolatile
write is in progress.
Write Memory Array
Prior to any attempt to write data into the memory array, the
“Write Enable” Latch (WEL) must be set by issuing the WREN
instruction (Figure 5). First pull CS LOW, then clock the WREN
instruction into the device and pull CS HIGH. Then bring CS
LOW again and enter the WRITE instruction followed by the 8-
bit address and then the data to be written. Bit 3 of the WRITE
instruction contains address bit A8, which selects the upper or
lower half of the array. If CS does not go HIGH between WREN
and WRITE, the WRITE instruction is ignored.
The WRITE operation requires at least 16 clocks. CS must go
low and remain low for the duration of the operation. The host
may continue to write up to 16 bytes of data. The only
restriction is that the 16 bytes must reside within the same
page. A page address begins with address [x xxxx 0000] and
ends with [x xxxx 1111]. If the byte address reaches the last
byte on the page and the clock continues, the counter will roll
back to the first address of the page and overwrite any data
that has been previously written.
For the write operation (byte or page write) to be completed,
CS must be brought HIGH after bit 0 of the last complete data
CS
0
1
2
3
4
5
6
7
8
9
6
10
12 13 14 15 16 17 18 19 20 21 22
SCK
SI
Instruction
8 Bit Address
7
5
3
2
1
0
8
9th Bit of Address
Data Out
High Impedance
7
6
5
4
3
2
1
0
SO
MSB
FIGURE 8. READ EEPROM ARRAY SEQUENCE
FN8126 Rev 3.00
Page 11 of 21
September 23, 2015
X5043, X5045
CS
0
1
2
3
4
8
5
6
7
8
7
9
10
12 13 14 15 16 17 18 19 20 21 22 23
SCK
SI
Instruction
8 Bit Address
Data Byte 1
6
5
3
2
1
0
7
6
5
4
3
2
1
0
9th Bit of Address
CS
24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
SCK
Data Byte 2
Data Byte 3
Data Byte N
SI
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
6
5
4
3
2
1
0
FIGURE 9. WRITE MEMORY SEQUENCE
Operational Notes
The device powers-up in the following state:
1. The device is in the low power standby state.
2. A HIGH to LOW transition on CS is required to enter an
active state and receive an instruction.
3. SO pin is high impedance.
4. The Write Enable Latch is reset.
5. The Flag Bit is reset.
6. Reset Signal is active for tPURST
.
Data Protection
The following circuitry has been included to prevent
inadvertent writes:
• A WREN instruction must be issued to set the Write Enable
Latch.
• CS must come HIGH at the proper clock count in order to
start a nonvolatile write cycle.
• Block Protect bits provide additional level of write protection
for the memory array.
• The WP pin LOW blocks nonvolatile write operations.
FN8126 Rev 3.00
Page 12 of 21
September 23, 2015
X5043, X5045
Absolute Maximum Ratings
Recommended Operating Conditions
Temperature under bias. . . . . . . . . . . . . . . . . . . . . .-65°C to +135°C
Storage temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Voltage on any pin with
respect to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-1.0V to +7V
D.C. output current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5mA
Lead temperature (soldering, 10 seconds) . . . . . . . . . . . . . . .300°C
Temperature:
Commercial. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C
Industrial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C
Supply Voltage:
-2.7, -2.7A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V to 5.5V
Blank, -4.5A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5V to 5.5V
CAUTION: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only; functional
operation of the device (at these or any other conditions above those listed in the operational sections of this specification) is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
DC Electrical Specifications (Over the recommended operating conditions unless otherwise specified.)
LIMITS
SYMBOL
ICC1
PARAMETER
VCC Write Current (Active)
VCC Read Current (Active)
TEST CONDITIONS/COMMENTS
MIN
TYP(2)
MAX
UNIT
mA
SCK = 3.3MHz(3); SO, RESET, RESET = Open
3
2
ICC2
SCK = 3.3MHz(3); SI = VSS, RESET, RESET =
Open
mA
ISB1
ISB2
ILI
VCC Standby Current WDT = OFF CS = VCC, SCK, SI = VSS, VCC = 5.5V
VCC Standby Current WDT = ON CS = VCC, SCK, SI = VSS, VCC = 5.5V
10
50
µA
µA
µA
µA
V
Input Leakage Current
Output Leakage Current
Input LOW Voltage
SCK, SI, WP = VSS to VCC
SO, RESET, RESET = VSS to VCC
SCK, SI, WP, CS
0.1
0.1
10
ILO
10
(1)
VIL
-0.5
VCC x 0.3
VCC + 0.5
0.4
(1)
VIH
Input HIGH Voltage
SCK, SI, WP, CS
VCC x 0.7
V
VOL
Output LOW Voltage (SO)
IOL = 2mA @ VCC = 2.7V
V
I
OL = 0.5mA @ VCC = 1.8V
VOH1
VOH2
VOH3
VOLRS
Output HIGH Voltage (SO)
Output HIGH Voltage (SO)
Output HIGH Voltage (SO)
VCC > 3.3V, IOH = –1.0mA
2V < VCC 3.3V, IOH = –0.4mA
VCC 2V, IOH = –0.25mA
IOL = 1mA
VCC - 0.8
VCC - 0.4
VCC - 0.2
V
V
V
V
Output LOW Voltage (RESET,
RESET)
0.4
Capacitance TA = +25°C, f = 1MHz, VCC = 5V
SYMBOL
TEST
Output Capacitance (SO, RESET, RESET)
Input Capacitance (SCK, SI, CS, WP)
CONDITIONS
MAX
UNIT
(2)
COUT
VOUT = 0V
VIN = 0V
8
6
pF
pF
(2)
CIN
NOTES:
1. VIL min. and VIH max. are for reference only and are not tested.
2. This parameter is periodically sampled and not 100% tested.
3. SCK frequency measured from VCC x 0.1/VCC x 0.9
FN8126 Rev 3.00
Page 13 of 21
September 23, 2015
X5043, X5045
Equivalent A.C. Load Circuit at 5V V
A.C. Test Conditions
Input pulse levels
CC
VCC x 0.1 to VCC x 0.9
10ns
5V
5V
Input rise and fall times
Input and output timing level
V
CC x 0.5
4.6k
1.64k
Output
1.64k
RESET/RESET
30pF
30pF
AC Electrical Specifications (Over recommended operating conditions, unless otherwise specified)
2.7V–5.5V
SYMBOL
PARAMETER
MIN
MAX
UNIT
DATA INPUT TIMING
fSCK
tCYC
tLEAD
tLAG
tWH
tWL
Clock Frequency
0
3.3
MHz
ns
Cycle Time
300
150
150
130
130
30
CS Lead Time
CS Lag Time
ns
ns
Clock HIGH Time
Clock LOW Time
Data Setup Time
Data Hold Time
Input Rise Time
Input Fall Time
CS Deselect Time
Write Cycle Time
ns
ns
tSU
ns
tH
30
ns
(4)
tRI
2
2
µs
µs
ns
(4)
tFI
tCS
100
(5)
tWC
10
ms
Data Output Timing
2.7–5.5V
SYMBOL
PARAMETER
MIN
MAX
3.3
UNIT
MHz
ns
fSCK
tDIS
tV
Clock Frequency
0
Output Disable Time
Output Valid from Clock Low
Output Hold Time
150
120
ns
tHO
0
ns
(4)
tRO
Output Rise Time
50
50
ns
(4)
tFO
Output Fall Time
ns
NOTES:
4. This parameter is periodically sampled and not 100% tested.
5. tWC is the time from the rising edge of CS after a valid write sequence has been sent to the end of the self-timed internal nonvolatile write cycle.
FN8126 Rev 3.00
Page 14 of 21
September 23, 2015
X5043, X5045
Serial Output Timing
CS
SCK
SO
tCYC
tWH
tLAG
tV
tHO
tWL
tDIS
MSB Out
MSB–1 Out
LSB Out
ADDR
LSB IN
SI
Serial Input Timing
tCS
CS
SCK
SI
tLEAD
tLAG
tSU
tH
tRI
tFI
MSB In
LSB In
High Impedance
SO
Symbol Table
WAVEFORM
INPUTS
OUTPUTS
Must be
steady
Will be
steady
May change
from LOW
to HIGH
Will change
from LOW
to HIGH
May change
from HIGH
to LOW
Will change
from HIGH
to LOW
Don’t Care:
Changes
Allowed
Changing:
State Not
Known
N/A
Center Line
is High
Impedance
FN8126 Rev 3.00
Page 15 of 21
September 23, 2015
X5043, X5045
Power-Up and Power-Down Timing
VTRIP
VTRIP
VCC
tPURST
0 Volts
tPURST
tF
tRPD
tR
RESET (X5043)
RESET (X5045)
RESET Output Timing
SYMBOL
PARAMETER
MIN
TYP
MAX
UNIT
VTRIP
Reset Trip Point Voltage, (-4.5A)
Reset Trip Point Voltage, (Blank)
Reset Trip Point Voltage, (-2.7A)
Reset Trip Point Voltage, (-2.7)
4.5
4.62
4.38
2.92
2.62
4.75
4.5
3.0
V
4.25
2.85
2.55
2.7
tPURST
Power-up Reset Time Out
VCC Detect to Reset/Output
VCC Fall Time
100
200
400
500
ms
ns
µs
ns
V
(6)
tRPD
(6)
tF
10
0.1
1
(6)
tR
VCC Rise Time
VRVALID
Reset Valid VCC
NOTE:
6. This parameter is periodically sampled and not 100% tested.
CS/WDI vs. RESET/RESET Timing
CS/WDI
tCST
RESET
(5043)
tWDO
tRST
tWDO
tRST
RESET
(5045)
RESET/RESET Output Timing
SYMBOL
PARAMETER
MIN
TYP
MAX
UNIT
tWDO
Watchdog Time Out Period,
WD1 = 1, WD0 = 1 (default)
WD1 = 1, WD0 = 0
WD1 = 0, WD0 = 1
OFF
200
600
1.4
100
450
1
300
800
2
ms
ms
sec
WD1 = 0, WD0 = 0
tCST
tRST
CS Pulse Width to Reset the Watchdog
Reset Time Out
400
100
ns
200
400
ms
FN8126 Rev 3.00
Page 16 of 21
September 23, 2015
X5043, X5045
V Programming Timing Diagram
TRIP
VCC
(VTRIP
VTRIP
)
tTHD
tTSU
VP
WP
tVPH
tVPS
tVPO
tPCS
CS
tRP
SCK
SI
06h
02h
01h or
03h
V
Programming Parameters
TRIP
PARAMETER
tVPS
DESCRIPTION
MIN
1
MAX
UNIT
µs
VTRIP Program Enable Voltage Setup time
VTRIP Program Enable Voltage Hold time
VTRIP Programming CS inactive time
VTRIP Setup time
tVPH
1
µs
tPCS
1
µs
tTSU
1
µs
tTHD
VTRIP Hold (stable) time
10
ms
ms
µs
tWC
VTRIP Write Cycle Time
10
tVPO
VTRIP Program Enable Voltage Off time (Between successive adjustments)
VTRIP Program Recovery Period (Between successive adjustments)
Programming Voltage
0
tRP
10
15
1.7
-25
ms
V
VP
18
VTRAN
Vtv
VTRIP Programmed Voltage Range
4.75
+25
V
VTRIP Program variation after programming (0-75°C). (Programmed at 25°C.)
mV
VTRIP programming parameters are periodically sampled and are not 100% tested.
FN8126 Rev 3.00
Page 17 of 21
September 23, 2015
X5043, X5045
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web to make
sure that you have the latest revision.
DATE
REVISION
CHANGE
September 23, 2015
FN8126.3 - Updated Ordering Information Table on page 3.
- Added Revision History.
- Added About Intersil Verbiage.
- Attached current POD.
About Intersil
Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products
address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets.
For the most updated datasheet, application notes, related documentation and related parts, please see the respective product
information page found at www.intersil.com.
You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask.
Reliability reports are also available from our website at www.intersil.com/support.
© Copyright Intersil Americas LLC 2005-2015 All Rights Reserved.
All trademarks and registered trademarks are the property of their respective owners.
For additional products, see www.intersil.com/en/products.html
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such
modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are
current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its
subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN8126 Rev 3.00
Page 18 of 21
September 23, 2015
X5043, X5045
Plastic Dual-In-Line Packages (PDIP)
E
N
1
D
PIN #1
INDEX
A2
A
E1
SEATING
PLANE
L
c
A1
NOTE 5
2
N/2
eA
eB
e
b
b2
MDP0031
PLASTIC DUAL-IN-LINE PACKAGE
INCHES
SYMBOL
PDIP8
0.210
0.015
0.130
0.018
0.060
0.010
0.375
0.310
0.250
0.100
0.300
0.345
0.125
8
PDIP14
0.210
0.015
0.130
0.018
0.060
0.010
0.750
0.310
0.250
0.100
0.300
0.345
0.125
14
PDIP16
0.210
0.015
0.130
0.018
0.060
0.010
0.750
0.310
0.250
0.100
0.300
0.345
0.125
16
PDIP18
PDIP20
0.210
0.015
0.130
0.018
0.060
0.010
1.020
0.310
0.250
0.100
0.300
0.345
0.125
20
TOLERANCE
MAX
NOTES
A
A1
A2
b
0.210
0.015
0.130
0.018
0.060
0.010
0.890
0.310
0.250
0.100
0.300
0.345
0.125
18
MIN
±0.005
±0.002
b2
c
+0.010/-0.015
+0.004/-0.002
±0.010
D
1
2
E
+0.015/-0.010
±0.005
E1
e
Basic
eA
eB
L
Basic
±0.025
±0.010
N
Reference
Rev. C 2/07
NOTES:
1. Plastic or metal protrusions of 0.010” maximum per side are not included.
2. Plastic interlead protrusions of 0.010” maximum per side are not included.
3. Dimensions E and eA are measured with the leads constrained perpendicular to the seating plane.
4. Dimension eB is measured with the lead tips unconstrained.
5. 8 and 16 lead packages have half end-leads as shown.
FN8126 Rev 3.00
Page 19 of 21
September 23, 2015
X5043, X5045
Package Outline Drawing
M8.15
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
Rev 4, 1/12
DETAIL "A"
1.27 (0.050)
0.40 (0.016)
INDEX
AREA
6.20 (0.244)
5.80 (0.228)
0.50 (0.20)
x 45°
0.25 (0.01)
4.00 (0.157)
3.80 (0.150)
8°
0°
1
2
3
0.25 (0.010)
0.19 (0.008)
SIDE VIEW “B”
TOP VIEW
2.20 (0.087)
1
8
SEATING PLANE
0.60 (0.023)
1.27 (0.050)
1.75 (0.069)
5.00 (0.197)
4.80 (0.189)
2
3
7
6
1.35 (0.053)
-C-
4
5
0.25(0.010)
0.10(0.004)
1.27 (0.050)
0.51(0.020)
0.33(0.013)
5.20(0.205)
SIDE VIEW “A
TYPICAL RECOMMENDED LAND PATTERN
NOTES:
6. Dimensioning and tolerancing per ANSI Y14.5M-1994.
7. Package length does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
8. Package width does not include interlead flash or protrusions. Interlead
flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.
9. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
10. Terminal numbers are shown for reference only.
11. The lead width as measured 0.36mm (0.014 inch) or greater above the
seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch).
12. Controlling dimension: MILLIMETER. Converted inch dimensions are not
necessarily exact.
13. This outline conforms to JEDEC publication MS-012-AA ISSUE C.
FN8126 Rev 3.00
Page 20 of 21
September 23, 2015
X5043, X5045
Package Outline Drawing
M8.118
8 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE
Rev 4, 7/11
5
3.0±0.05
A
DETAIL "X"
D
8
1.10 MAX
SIDE VIEW 2
0.09 - 0.20
4.9±0.15
3.0±0.05
5
0.95 REF
PIN# 1 ID
1
2
B
0.65 BSC
GAUGE
PLANE
TOP VIEW
0.25
3°±3°
0.55 ± 0.15
DETAIL "X"
0.85±010
H
C
SEATING PLANE
0.10 C
0.25 - 0.36
0.10 ± 0.05
0.08
C A-B D
M
SIDE VIEW 1
(5.80)
NOTES:
1. Dimensions are in millimeters.
(4.40)
(3.00)
2. Dimensioning and tolerancing conform to JEDEC MO-187-AA
and AMSEY14.5m-1994.
3. Plastic or metal protrusions of 0.15mm max per side are not
included.
(0.65)
4. Plastic interlead protrusions of 0.15mm max per side are not
included.
(0.40)
(1.40)
5. Dimensions are measured at Datum Plane "H".
6. Dimensions in ( ) are for reference only.
TYPICAL RECOMMENDED LAND PATTERN
FN8126 Rev 3.00
Page 21 of 21
September 23, 2015
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