X5169PZ-4.5A [RENESAS]
CPU Supervisor with 16Kbit SPI EEPROM; PDIP8, SOIC8; Temp Range: See Datasheet;
| 型号： | X5169PZ-4.5A |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | CPU Supervisor with 16Kbit SPI EEPROM; PDIP8, SOIC8; Temp Range: See Datasheet 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 光电二极管 |
| 文件： | 总20页 (文件大小：857K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATASHEET
X5168, X5169 (Replaces X25268,
CPU Supervisor with 16Kbit SPI EEPROM
FN8130
Rev 2.00
June 15, 2006
These devices combine three popular functions, Power-on
Reset Control, Supply Voltage Supervision, and Block Lock
Protect Serial EEPROM Memory in one package. This
combination lowers system cost, reduces board space
requirements, and increases reliability.
Features
• Low VCC Detection and Reset Assertion
- Five standard reset threshold voltages
- Re-program low VCC reset threshold voltage using
special programming sequence
Applying power to the device activates the power-on reset
circuit which holds RESET/RESET active for a period of
time. This allows the power supply and oscillator to stabilize
before the processor can execute code.
- Reset signal valid to VCC = 1V
• Long Battery Life with Low Power Consumption
- <50µA max standby current, watchdog on
- <1µA max standby current, watchdog off
- <400µA max active current during read
The device’s low VCC detection circuitry protects the user’s
system from low voltage conditions by holding
• 16Kbits of EEPROM
RESET/RESET active when VCC falls below a minimum VCC
trip point. RESET/RESET remains asserted until VCC returns
to proper operating level and stabilizes. Five industry
standard VTRIP thresholds are available, however, Intersil’s
unique circuits allow the threshold to be reprogrammed to
meet custom requirements or to fine-tune the threshold in
applications requiring higher precision.
• Built-in Inadvertent Write Protection
- Power-up/power-down protection circuitry
- Protect 0, 1/4, 1/2 or all of EEPROM array with Block
Lock™ protection
- In circuit programmable ROM mode
• 2MHz SPI Interface Modes (0,0 & 1,1)
• Minimize EEPROM Programming Time
- 32-byte page write mode
- Self-timed write cycle
- 5ms write cycle time (typical)
• 2.7V to 5.5V and 4.5V to 5.5V Power Supply
Operation
• Available Packages
- 14 Ld TSSOP, 8 Ld SOIC, 8 Ld PDIP
• Pb-Free Plus Anneal Available (RoHS Compliant)
Block Diagram
WP
Protect Logic
SI
Data
Register
Status
Register
SO
Command
Decode &
Control
SCK
CS
4Kbits
4Kbits
Logic
8Kbits
Reset
Timebase
RESET/RESET
Power-on and
Low Voltage
Reset
V
+
-
CC
Generation
X5168 = RESET
X5169 = RESET
V
TRIP
FN8130 Rev 2.00
June 15, 2006
Page 1 of 20
X5168, X5169 (Replaces X25268, X25169)
Ordering Information
PART NUMBER
RESET
PART NUMBER
RESET
PART
PART
VCC RANGE VTRIP RANGE
TEMP
PKG.
(ACTIVE LOW)
MARKING
(ACTIVE HIGH)
MARKING
(V)
(V)
RANGE (°C)
PACKAGE
DWG #
X5168P-4.5A
X5168P AL
X5169P-4.5A
X5169P AL
4.5-5.5
4.5-4.75
0 to 70
0 to 70
8 Ld PDIP
MDP0031
MDP0031
X5168PZ-4.5A
(Note)
X5168P Z AL X5169PZ-4.5A
(Note)
X5169P Z AL
8 Ld PDIP**
(Pb-free)
X5168PI-4.5A
X5168P AM X5169PI-4.5A
X5169P AM
-40 to 85
-40 to 85
8 Ld PDIP
MDP0031
MDP0031
X5168PIZ-4.5A
(Note)
X5168P Z AM X5169PIZ-4.5A
(Note)
X5169P Z AM
8 Ld PDIP**
(Pb-free)
X5168S8-4.5A
X5168 AL
X5169S8-4.5A
X5169 AL
0 to 70
0 to 70
8 Ld SOIC
MDP0027
MDP0027
X5168S8Z-4.5A X5168 Z AL X5169S8Z-4.5A X5169 Z AL
(Note)
8 Ld SOIC
(Pb-free)
(Note)
X5168S8I-4.5A* X5168 AM
X5169S8I-4.5A
X5169 AM
-40 to 85
-40 to 85
8 Ld SOIC
MDP0027
MDP0027
X5168S8IZ-4.5A* X5168 Z AM X5169S8IZ-4.5A X5169 Z AM
(Note)
8 Ld SOIC
(Pb-free)
(Note)
X5168V14-4.5A X5168V AL
X5169V14-4.5A X5169V AL
0 to 70
0 to 70
14 Ld TSSOP M14.173
X5168V14Z-4.5A X5168V Z AL X5169V14Z-4.5A X5169V Z AL
(Note) (Note)
14 Ld TSSOP M14.173
(Pb-free)
X5168V14I-4.5A X5168V AM X5169V14I-4.5A X5169V AM
X5168V14IZ-4.5A X5168V Z AM X5169V14IZ-4.5A X5169V Z AM
-40 to 85
-40 to 85
14 Ld TSSOP M14.173
14 Ld TSSOP M14.173
(Pb-free)
(Note)
(Note)
X5168P
X5168P
X5169P
X5169P
4.5-5.5
4.25-4.5
0 to 70
0 to 70
8 Ld PDIP
MDP0031
MDP0031
X5168PZ (Note) X5168P Z
X5169PZ (Note) X5169P Z
8 Ld PDIP**
(Pb-free)
X5168PI
X5168P I
X5169PI
X5169P I
-40 to 85
-40 to 85
8 Ld PDIP
MDP0031
MDP0031
X5168PIZ (Note) X5168P Z I
X5169PIZ (Note) X5169P Z I
8 Ld PDIP**
(Pb-free)
X5168S8*
X5168
X5169S8*
X5169
0 to 70
0 to 70
8 Ld SOIC
MDP0027
MDP0027
X5168S8Z*
(Note)
X5168 Z
X5169S8Z*
(Note)
X5169 Z
8 Ld SOIC
(Pb-free)
X5168S8I*
X5168 I
X5169S8I*
X5169 I
-40 to 85
-40 to 85
8 Ld SOIC
MDP0027
MDP0027
X5168S8IZ*
(Note)
X5168 Z I
X5169S8IZ*
(Note)
X5169 Z I
8 Ld SOIC
(Pb-free)
X5168V14*
X5168V
X5169V14*
X5169V
0 to 70
0 to 70
14 Ld TSSOP M14.173
X5168V14Z*
(Note)
X5168V Z
X5169V14Z*
(Note)
X5169V Z
14 Ld TSSOP M14.173
(Pb-free)
X5168V14I*
X5168V I
X5169V14I*
X5169V I
-40 to 85
-40 to 85
14 Ld TSSOP M14.173
X5168V14IZ*
(Note)
X5168V Z I
X5169V14IZ*
(Note)
X5169V Z I
14 Ld TSSOP M14.173
(Pb-free)
X5168P-2.7A
X5168P AN
X5169P-2.7A
X5169P AN
2.7-5.5
2.85-3.0
0 to 70
0 to 70
8 Ld PDIP
MDP0031
MDP0031
X5168PZ-2.7A
(Note)
X5168P Z AN X5169PZ-2.7A
(Note)
X5169P Z AN
8 Ld PDIP**
(Pb-free)
X5168PI-2.7A
X5168P AP
X5169PI-2.7A
X5169P AP
-40 to 85
-40 to 85
8 Ld PDIP
MDP0031
MDP0031
X5168PIZ-2.7A
(Note)
X5168P Z AP X5169PIZ-2.7A
(Note)
X5169P Z AP
8 Ld PDIP**
(Pb-free)
X5168S8-2.7A*
X5168 AN
X5169S8-2.7A
X5169 AN
0 to 70
0 to 70
8 Ld SOIC
MDP0027
MDP0027
X5168S8Z-2.7A* X5168 Z AN X5169S8Z-2.7A X5169 Z AN
(Note)
8 Ld SOIC
(Pb-free)
(Note)
X5168S8I-2.7A* X5168 AP
X5169S8I-2.7A
X5169 AP
-40 to 85
-40 to 85
8 Ld SOIC
MDP0027
MDP0027
X5168S8IZ-2.7A X5168 Z AP X5169S8IZ-2.7A X5169 Z AP
(Note)
8 Ld SOIC
(Pb-free)
(Note)
FN8130 Rev 2.00
June 15, 2006
Page 2 of 20
X5168, X5169 (Replaces X25268, X25169)
Ordering Information (Continued)
PART NUMBER
RESET
PART NUMBER
RESET
PART
PART
VCC RANGE VTRIP RANGE
TEMP
PKG.
(ACTIVE LOW)
MARKING
(ACTIVE HIGH)
MARKING
(V)
(V)
RANGE (°C)
PACKAGE
DWG #
X5168V14-2.7A X5168V AN
X5169V14-2.7A X5168V AN
2.7-5.5
2.85-3.0
0 to 70
0 to 70
14 Ld TSSOP M14.173
X5168V14Z-2.7A X5168V Z AN X5169V14Z-2.7A X5169V Z AN
(Note)
14 Ld TSSOP M14.173
(Pb-free)
(Note)
X5168V14I-2.7A X5168V AP
X5169V14I-2.7A X5169V AP
-40 to 85
-40 to 85
14 Ld TSSOP M14.173
X5168V14IZ-2.7A X5168V Z AP X5169V14IZ-2.7A X5169V Z AP
(Note)
14 Ld TSSOP M14.173
(Pb-free)
(Note)
X5168P-2.7
X5168P F
X5169P-2.7
X5169P F
2.7-5.5
2.55-2.7
0 to 70
-40 to 85
0 to 70
8 Ld PDIP
MDP0031
MDP0031
X5168PZ-2.7
(Note)
X5168P Z F X5169PZ-2.7
(Note)
X5169P Z F
8 Ld PDIP**
(Pb-free)
X5168PI-2.7
X5168P G
X5169PI-2.7
X5169P G
8 Ld PDIP
MDP0031
MDP0031
X5168PIZ-2.7
(Note)
X5168P Z G X5169PIZ-2.7
(Note)
X5169P Z G
8 Ld PDIP**
(Pb-free)
X5168S8-2.7*
X5168 F
X5169S8-2.7*
X5169 F
8 Ld SOIC
MDP0027
MDP0027
X5168S8Z-2.7*
(Note)
X5168 Z F
X5169S8Z-2.7*
(Note)
X5169 Z F
8 Ld SOIC
(Pb-free)
X5168S8I-2.7*
X5168 G
X5169S8I-2.7*
X5169 G
-40 to 85
8 Ld SOIC
MDP0027
MDP0027
X5168S8IZ-2.7* X5168 Z G
(Note)
X5169S8IZ-2.7* X5169 Z G
(Note)
8 Ld SOIC
(Pb-free)
X5168V14-2.7*
X5168V F
X5169V14-2.7*
X5169V F
0 to 70
0 to 70
14 Ld TSSOP M14.173
X5168V14Z-2.7* X5168V Z F X5169V14Z-2.7* X5169V Z F
(Note)
14 Ld TSSOP M14.173
(Pb-free)
(Note)
X5168V14I-2.7* X5168V G
X5169V14I-2.7* X5168V G
-40 to 85
-40 to 85
14 Ld TSSOP M14.173
X5168V14IZ-2.7* X5168V Z G X5169V14IZ-2.7* X5168V Z G
(Note) (Note)
14 Ld TSSOP M14.173
(Pb-free)
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin
plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are
MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
*Add "-T1" suffix for tape and reel.
**Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications.
Pin Configuration
14 LD TSSOP
8 LD SOIC/PDIP
X5168/X5169
X5168/X5169
1
V
CS
SO
NC
14
13
12
CC
2
3
4
5
RESET/RESET
V
1
8
CS
SO
WP
CC
NC
NC
2
3
7
6
RESET/RESET
NC
NC
WP
11
10
9
SCK
SI
NC
V
SS
4
5
SCK
6
7
V
SS
SI
8
FN8130 Rev 2.00
June 15, 2006
Page 3 of 20
X5168, X5169 (Replaces X25268, X25169)
Pin Description
PIN
(SOIC/PDIP)
PIN TSSOP
NAME
FUNCTION
1
1
CS
Chip Select Input. CS HIGH, deselects the device and the SO output
pin is at a high impedance state. Unless a nonvolatile write cycle is underway, the device will be
in the standby power mode. CS LOW enables the device, placing it in the active power mode. Prior
to the start of any operation after power-up, a HIGH to LOW transition on CS is required.
2
5
2
8
SO
SI
Serial Output. SO is a push/pull serial data output pin. A read cycle shifts data out on this pin. The
falling edge of the serial clock (SCK) clocks the data out.
Serial Input. SI is a serial data input pin. Input all opcodes, byte addresses, and memory data on this
pin. The rising edge of the serial clock (SCK) latches the input data. Send all opcodes (Table 1),
addresses and data MSB first.
6
3
9
6
SCK
WP
Serial Clock. The serial clock controls the serial bus timing for data input and output. The rising edge
of SCK latches in the opcode, address, or data bits present on the SI pin. The falling edge of SCK
changes the data output on the SO pin.
Write Protect. The WP pin works in conjunction with a nonvolatile WPEN bit to “lock” the setting
of the watchdog timer control and the memory write protect bits.
4
8
7
7
VSS
VCC
Ground
14
13
Supply Voltage
RESET/
RESET
Reset Output. RESET/RESET is an active LOW/HIGH, open drain output which goes active
whenever VCC falls below the minimum VCC sense level. It will remain active until VCC rises above
the minimum VCC sense level for 200ms. RESET/RESET goes active if the watchdog timer is
enabled and CS remains either HIGH or LOW longer than the selectable watchdog time out
period. A falling edge of CS will reset the watchdog timer. RESET/RESET goes active on power-
up at about 1V and remains active for 200ms after the power supply stabilizes.
3-5,10-12
NC
No internal connections
FN8130 Rev 2.00
June 15, 2006
Page 4 of 20
X5168, X5169 (Replaces X25268, X25169)
new VTRIP is something less than 1.7V. This procedure must
be used to set the voltage to a lower value.
Principles of Operation
Power-on Reset
To reset the VTRIP voltage, apply a voltage between 2.7 and
5.5V to the VCC pin. Tie the CS pin, the WP pin, and the SCK pin
HIGH. RESET/RESET and SO pins are left unconnected. Then
apply the programming voltage VP to the SI pin ONLY and pulse
CS LOW then HIGH. Remove VP and the sequence is
complete.
Application of power to the X5168, X5169 activates a power-on
reset circuit. This circuit goes active at about 1V and pulls the
RESET/RESET pin active. This signal prevents the system
microprocessor from starting to operate with insufficient voltage
or prior to stabilization of the oscillator. When VCC exceeds the
device VTRIP value for 200ms (nominal) the circuit releases
RESET/RESET, allowing the processor to begin executing code.
Low Voltage Monitoring
CS
During operation, the X5168, X5169 monitors the VCC level
and asserts RESET/RESET if supply voltage falls below a
preset minimum VTRIP. The RESET/RESET signal prevents
the microprocessor from operating in a power fail or brownout
condition. The RESET/RESET signal remains active until the
voltage drops below 1V. It also remains active until VCC returns
and exceeds VTRIP for 200ms.
VCC
SCK
VP
SI
FIGURE 2. RESET VTRIP VOLTAGE
V
Threshold Reset Procedure
CC
The X5168, X5169 has a standard VCC threshold (VTRIP
)
voltage. This value will not change over normal operating and
storage conditions. However, in applications where the
standard VTRIP is not exactly right, or for higher precision in the
VTRIP value, the X5168, X5169 threshold may be adjusted.
Setting the V Voltage
TRIP
This procedure sets the VTRIP to a higher voltage value. For
example, if the current VTRIP is 4.4V and the new VTRIP is 4.6V,
this procedure directly makes the change. If the new setting is
lower than the current setting, then it is necessary to reset the
trip point before setting the new value.
To set the new VTRIP voltage, apply the desired VTRIP
threshold to the VCC pin and tie the CS pin and the WP pin
HIGH. RESET/RESET and SO pins are left unconnected.
Then apply the programming voltage VP to both SCK and SI
and pulse CS LOW then HIGH. Remove VP and the sequence
is complete.
CS
VP
SCK
VP
SI
FIGURE 1. SET VTRIP VOLTAGE
Resetting the V
Voltage
TRIP
This procedure sets the VTRIP to a “native” voltage level. For
example, if the current VTRIP is 4.4V and the VTRIP is reset, the
FN8130 Rev 2.00
June 15, 2006
Page 5 of 20
X5168, X5169 (Replaces X25268, X25169)
VTRIP Programming
Execute
Reset VTRIP
Sequence
Set VCC = VCC Applied =
Desired VTRIP
Execute
Set VTRIP
Sequence
New VCC Applied =
New VCC Applied =
Old VCC Applied - Error
Old VCC Applied + Error
Execute
Reset VTRIP
Sequence
Apply 5V to VCC
Decrement VCC
(VCC = VCC - 10mV)
NO
RESET pin
goes active?
YES
Error Emax
Error > Emax
Measured VTRIP
Desired VTRIP
-
Error = 0
DONE
Emax = Maximum Desired Error
FIGURE 3. VTRIP PROGRAMMING SEQUENCE FLOW CHART
VP
4.7K
NC
NC
4.7K
RESET
1
2
3
4
8
7
6
5
NC
X5168/
X5169
VTRIP
Adj.
+
Program
Reset VTRIP
Test VTRIP
Set VTRIP
10K
10K
FIGURE 4. SAMPLE VTRIP RESET CIRCUIT
FN8130 Rev 2.00
June 15, 2006
Page 6 of 20
X5168, X5169 (Replaces X25268, X25169)
Write Enable Latch
SPI Serial Memory
The device contains a write enable latch. This latch must be
SET before a write operation is initiated. The WREN instruction
will set the latch and the WRDI instruction will reset the latch
(Figure 3). This latch is automatically reset upon a power-up
condition and after the completion of a valid write cycle.
The memory portion of the device is a CMOS serial EEPROM
array with Intersil’s block lock protection. The array is internally
organized as x 8. The device features a Serial Peripheral
Interface (SPI) and software protocol allowing operation on a
simple four-wire bus.
The device utilizes Intersil’s proprietary Direct Write™ cell,
providing a minimum endurance of 100,000 cycles and a
minimum data retention of 100 years.
Status Register
The RDSR instruction provides access to the status register.
The status register may be read at any time, even during a
write cycle. The status register is formatted as follows:
The device is designed to interface directly with the
synchronous Serial Peripheral Interface (SPI) of many popular
microcontroller families. It contains an 8-bit instruction register
that is accessed via the SI input, with data being clocked in on
the rising edge of SCK. CS must be LOW during the entire
operation.
7
6
5
4
3
2
1
0
WPEN
FLB
0
0
BL1
BL0
WEL
WIP
The Write-In-Progress (WIP) bit is a volatile, read only bit and
indicates whether the device is busy with an internal
nonvolatile write operation. The WIP bit is read using the
RDSR instruction. When set to a “1”, a nonvolatile write
operation is in progress. When set to a “0”, no write is in
progress.
All instructions (Table 1), addresses and data are transferred
MSB first. Data input on the SI line is latched on the first rising
edge of SCK after CS goes LOW. Data is output on the SO line
by the falling edge of SCK. SCK is static, allowing the user to
stop the clock and then start it again to resume operations
where left off.
TABLE 1. INSTRUCTION SET
INSTRUCTION NAME
WREN
INSTRUCTION FORMAT*
0000 0110
OPERATION
Set the write enable latch (enable write operations)
Set flag bit
SFLB
0000 0000
WRDI/RFLB
RDSR
0000 0100
Reset the write enable latch/reset flag bit
Read status register
0000 0101
WRSR
0000 0001
Write status register (watchdog, block lock, WPEN and flag bits)
Read data from memory array beginning at selected address
Write data to memory array beginning at selected address
READ
0000 0011
WRITE
0000 0010
Note: *Instructions are shown MSB in leftmost position. Instructions are transferred MSB first.
TABLE 2. BLOCK PROTECT MATRIX
WREN CMD
STATUS REGISTER
DEVICE PIN
BLOCK
BLOCK
STATUS REGISTER
WPEN, BL0, BL1 WD0,
WD1
WEL
WPEN
WP#
PROTECTED BLOCK
Protected
UNPROTECTED BLOCK
Protected
0
1
1
1
X
1
0
X
X
0
X
1
Protected
Protected
Writable
Writable
Protected
Writable
Protected
Writable
Protected
Writable
FN8130 Rev 2.00
June 15, 2006
Page 7 of 20
X5168, X5169 (Replaces X25268, X25169)
The Write Enable Latch (WEL) bit indicates the status of the
write enable latch. When WEL = 1, the latch is set HIGH and
when WEL = 0 the latch is reset LOW. The WEL bit is a
volatile, read only bit. It can be set by the WREN instruction
and can be reset by the WRDS instruction.
WP is LOW and WPEN bit programmed HIGH disables all
status register write operations.
In Circuit Programmable ROM Mode
This mechanism protects the block lock and watchdog bits
from inadvertent corruption.
The block lock bits, BL0 and BL1, set the level of block lock
protection. These nonvolatile bits are programmed using the
WRSR instruction and allow the user to protect one quarter,
one half, all or none of the EEPROM array. Any portion of the
array that is block lock protected can be read but not written. It
will remain protected until the BL bits are altered to disable
block lock protection of that portion of memory.
In the locked state (programmable ROM mode) the WP pin is
LOW and the nonvolatile bit WPEN is “1”. This mode disables
nonvolatile writes to the device’s status register.
Setting the WP pin LOW while WPEN is a “1” while an internal
write cycle to the status register is in progress will not stop this
write operation, but the operation disables subsequent write
attempts to the status register.
STATUS
REGISTER BITS
ARRAY ADDRESSES PROTECTED
X5168/X5169
When WP is HIGH, all functions, including nonvolatile writes to
the status register operate normally. Setting the WPEN bit in
the status register to “0” blocks the WP pin function, allowing
writes to the status register when WP is HIGH or LOW. Setting
the WPEN bit to “1” while the WP pin is LOW activates the
programmable ROM mode, thus requiring a change in the WP
pin prior to subsequent status register changes. This allows
manufacturing to install the device in a system with WP pin
grounded and still be able to program the status register.
Manufacturing can then load configuration data, manufacturing
time and other parameters into the EEPROM, then set the
portion of memory to be protected by setting the block lock bits,
and finally set the “OTP mode” by setting the WPEN bit. Data
changes now require a hardware change.
BL1
0
BL0
0
None
0
1
$0600-$07FF
1
0
$0400-$07FF
1
1
$0000-$07FF
The FLAG bit shows the status of a volatile latch that can be
set and reset by the system using the SFLB and RFLB
instructions. The flag bit is automatically reset upon power-up.
The nonvolatile WPEN bit is programmed using the WRSR
instruction. This bit works in conjunction with the WP pin to
provide an in-circuit programmable ROM function (Table 2).
CS
0
1
2
3
4
5
6
7
8
9
10
20 21 22 23 24 25 26 27 28 29 30
SCK
SI
Instruction
16 Bit Address
15 14 13
3
2
1
0
Data Out
High Impedance
7
6
5
4
3
2
1
0
SO
MSB
FIGURE 5. READ EEPROM ARRAY SEQUENCE
FN8130 Rev 2.00
June 15, 2006
Page 8 of 20
X5168, X5169 (Replaces X25268, X25169)
Read Sequence
Operational Notes
When reading from the EEPROM memory array, CS is first
pulled low to select the device. The 8-bit READ instruction is
transmitted to the device, followed by the 16-bit address. After
the READ opcode and address are sent, the data stored in the
memory at the selected address is shifted out on the SO line.
The data stored in memory at the next address can be read
sequentially by continuing to provide clock pulses. The
address is automatically incremented to the next higher
address after each byte of data is shifted out. When the highest
address is reached, the address counter rolls over to address
$0000 allowing the read cycle to be continued indefinitely. The
read operation is terminated by taking CS high. Refer to the
read EEPROM array sequence (Figure 1).
The device powers-up in the following state:
• The device is in the low power standby state.
• A HIGH to LOW transition on CS is required to enter an
active state and receive an instruction.
• SO pin is high impedance.
• The write enable latch is reset.
• The flag bit is reset.
• Reset signal is active for tPURST
.
Data Protection
The following circuitry has been included to prevent
inadvertent writes:
To read the status register, the CS line is first pulled low to
select the device followed by the 8-bit RDSR instruction. After
the RDSR opcode is sent, the contents of the status register are
shifted out on the SO line. Refer to the read status register
sequence (Figure 2).
• A WREN instruction must be issued to set the write enable
latch.
• CS must come HIGH at the proper clock count in order to
start a nonvolatile write cycle.
Write Sequence
Prior to any attempt to write data into the device, the “Write
Enable” Latch (WEL) must first be set by issuing the WREN
instruction (Figure 3). CS is first taken LOW, then the WREN
instruction is clocked into the device. After all eight bits of the
instruction are transmitted, CS must then be taken HIGH. If the
user continues the write operation without taking CS HIGH
after issuing the WREN instruction, the write operation will be
ignored.
To write data to the EEPROM memory array, the user then
issues the WRITE instruction followed by the 16 bit address
and then the data to be written. Any unused address bits are
specified to be “0’s”. The WRITE operation minimally takes 32
clocks. CS must go low and remain low for the duration of the
operation. If the address counter reaches the end of a page
and the clock continues, the counter will roll back to the first
address of the page and overwrite any data that may have
been previously written.
For the page write operation (byte or page write) to be
completed, CS can only be brought HIGH after bit 0 of the last
data byte to be written is clocked in. If it is brought HIGH at any
other time, the write operation will not be completed (Figure 4).
To write to the status register, the WRSR instruction is followed
by the data to be written (Figure 5). Data bits 0 and 1 must be
“0”.
While the write is in progress following a status register or
EEPROM sequence, the status register may be read to check
the WIP bit. During this time the WIP bit will be high.
FN8130 Rev 2.00
June 15, 2006
Page 9 of 20
X5168, X5169 (Replaces X25268, X25169)
CS
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14
SCK
Instruction
SI
Data Out
High Impedance
SO
7
6
5
4
3
2
1
0
MSB
FIGURE 6. READ STATUS REGISTER SEQUENCE
CS
0
1
2
3
4
5
6
7
SCK
SI
High Impedance
FIGURE 7. WRITE ENABLE LATCH SEQUENCE
SO
CS
0
1
2
3
4
5
6
7
8
9
10
20 21 22 23 24 25 26 27 28 29 30 31
SCK
Instruction
16 Bit Address
15 14 13
Data Byte 1
3
2
1
0
7
6
5
4
3
2
1
0
SI
CS
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
SCK
SI
Data Byte 2
Data Byte 3
Data Byte N
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
6
5
4
3
2
1
0
FIGURE 8. WRITE SEQUENCE
FN8130 Rev 2.00
June 15, 2006
Page 10 of 20
X5168, X5169 (Replaces X25268, X25169)
CS
0
1
2
3
4
5
6
7
8
7
9
6
10 11 12 13 14 15
SCK
Instruction
Data Byte
5
4
3
2
1
0
SI
High Impedance
FIGURE 9. STATUS REGISTER WRITE SEQUENCE
SO
Symbol Table
WAVEFORM
INPUTS
OUTPUTS
Must be
steady
Will be
steady
May change
from LOW
to HIGH
Will change
from LOW
to HIGH
May change
from HIGH
to LOW
Will change
from HIGH
to LOW
Don’t Care:
Changes
Allowed
Changing:
State Not
Known
N/A
Center Line
is High
Impedance
FN8130 Rev 2.00
June 15, 2006
Page 11 of 20
X5168, X5169 (Replaces X25268, X25169)
Absolute Maximum Ratings
Recommended Operating Conditions
Temperature Under Bias . . . . . . . . . . . . . . . . . . . . .-65°C to +135°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Voltage on any Pin with Respect to VSS . . . . . . . . . . . .-1.0V to +7V
DC Output Current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5mA
Lead Temperature (Soldering, 10s) . . . . . . . . . . . . . . . . . . . . .300°C
Temperature Range
Commercial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C
Industrial. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C
Supply Voltage Limits
-2.7 or -2.7A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V to 5.5V
Blank or -4.5A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5V-5.5V
CAUTION: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only; the functional
operation of the device (at these or any other conditions above those listed in the operational sections of this specification) is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability
DC Electrical Specifications Over the recommended operating conditions unless otherwise specified.
LIMITS
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ICC1
VCC write current (active)
SCK = VCC x 0.1/VCC x 0.9 @ 2MHz,
SO = Open
5
mA
ICC2
VCC read current (active)
SCK = VCC x 0.1/VCC x 0.9 @ 2MHz,
SO = Open
0.4
1
mA
µA
ISB
VCC standby current WDT = OFF CS = VCC, VIN = VSS or VCC
VCC = 5.5V
,
ILI
Input leakage current
Output leakage current
Input LOW voltage
VIN = VSS to VCC
0.1
0.1
10
10
µA
µA
V
ILO
VOUT = VSS to VCC
VIL
-0.5
VCC x 0.3
(NOTE 1)
VIH
Input HIGH voltage
VCC x 0.7
VCC + 0.5
V
(NOTE 1)
VOL1
VOL2
VOL3
VOH1
VOH2
VOH3
VOLS
Output LOW voltage
Output LOW voltage
Output LOW voltage
Output HIGH voltage
Output HIGH voltage
Output HIGH voltage
Reset output LOW voltage
VCC > 3.3V, IOL = 2.1mA
2V < VCC 3.3V, IOL = 1mA
VCC 2V, IOL = 0.5mA
0.4
0.4
0.4
V
V
V
V
V
V
V
VCC > 3.3V, IOH = -1.0mA
VCC - 0.8
VCC - 0.4
VCC - 0.2
2V < VCC 3.3V, IOH = -0.4mA
VCC 2V, IOH = -0.25mA
I
OL = 1mA
0.4
Capacitance TA = +25°C, f = 1MHz, VCC = 5V.
SYMBOL
TEST
CONDITIONS
MAX.
UNIT
COUT
Output capacitance (SO, RESET/RESET)
VOUT = 0V
8
pF
(NOTE 2)
C
IN (NOTE 2) Input capacitance (SCK, SI, CS, WP)
VIN = 0V
6
pF
NOTES:
1. VIL min. and VIH max. are for reference only and are not tested.
2. This parameter is periodically sampled and not 100% tested.
FN8130 Rev 2.00
June 15, 2006
Page 12 of 20
X5168, X5169 (Replaces X25268, X25169)
Equivalent A.C. Load Circuit at 5V V
A.C. Test Conditions
Input pulse levels
CC
VCC x 0.1 to VCC x 0.9
10ns
5V
5V
Input rise and fall times
Input and output timing level
4.6k
VCC x 0.5
2.06k
Output
3.03k
RESET/RESET
30pF
100pF
AC Electrical Specifications (Over recommended operating conditions, unless otherwise specified.)
2.7-5.5V
SYMBOL
PARAMETER
MIN
MAX
UNIT
SERIAL INPUT TIMING
fSCK
tCYC
tLEAD
tLAG
tWH
tWL
Clock frequency
0
2
MHz
ns
Cycle time
500
250
250
200
200
50
CS lead time
ns
CS lag time
ns
Clock HIGH time
Clock LOW time
Data setup time
Data hold time
Input rise time
Input fall time
CS deselect time
Write cycle time
ns
ns
tSU
ns
tH
50
ns
(3)
tRI
100
100
ns
(3)
tFI
ns
tCS
500
ns
(4)
tWC
10
ms
FN8130 Rev 2.00
June 15, 2006
Page 13 of 20
X5168, X5169 (Replaces X25268, X25169)
Serial Input Timing
tCS
CS
tLEAD
tLAG
SCK
tSU
tH
tRI
tFI
SI
MSB IN
LSB IN
High Impedance
SO
Serial Output Timing
2.7-5.5V
SYMBOL
PARAMETER
MIN
MAX
2
UNIT
MHz
ns
fSCK
tDIS
tV
Clock frequency
Output disable time
0
250
200
Output valid from clock low
Output hold time
ns
tHO
0
ns
(3)
tRO
Output rise time
100
100
ns
(3)
tFO
Output fall time
ns
Notes: (3) This parameter is periodically sampled and not 100% tested.
(4) tWC is the time from the rising edge of CS after a valid write sequence has been sent to the end of the self-timed internal nonvolatile
write cycle.
Serial Output Timing
CS
SCK
SO
tCYC
tWH
tLAG
tV
tHO
tWL
tDIS
MSB Out
MSB–1 Out
LSB Out
ADDR
LSB IN
SI
FN8130 Rev 2.00
June 15, 2006
Page 14 of 20
X5168, X5169 (Replaces X25268, X25169)
Power-Up and Power-Down Timing
VTRIP
VTRIP
VCC
tPURST
0 Volts
tPURST
tF
tRPD
tR
RESET (X5168)
RESET (X5169)
RESET Output Timing
SYMBOL
PARAMETER
MIN
TYP
MAX
UNIT
VTRIP
Reset trip point voltage, X5168-4.5A, X5168-4.5A
Reset trip point voltage, X5168, X5169
Reset trip point voltage, X5168-2.7A, X5169-2.7A
Reset trip point voltage, X5168-2.7, X5169-2.7
4.5
4.63
4.38
2.93
2.63
4.75
4.5
3.0
V
4.25
2.85
2.55
2.7
VTH
VTRIP hysteresis (HIGH to LOW vs. LOW to HIGH VTRIP voltage)
20
mV
ms
ns
µs
µs
V
tPURST
Power-up reset time out
VCC detect to reset/output
VCC fall time
100
200
280
500
(5)
tRPD
(5)
tF
100
100
1
(5)
tR
VCC rise time
VRVALID
Reset valid VCC
Note: (5) This parameter is periodically sampled and not 100% tested.
V
Set Conditions
TRIP
tTHD
VCC
VTRIP
tTSU
tRP
tP
tVPH
tVPS
CS
tVPO
tVPH
tVPS
VP
SCK
SI
VP
tVPO
FN8130 Rev 2.00
June 15, 2006
Page 15 of 20
X5168, X5169 (Replaces X25268, X25169)
V
Reset Conditions
TRIP
VCC
*
tRP
tP
tVP1
tVPS
CS
tVPS
tVPO
tVPH
VCC
SCK
SI
VP
tVPO
*VCC > Programmed VTRIP
V
Programming Specifications VCC = 1.7-5.5V; Temperature = 0°C to 70°C
TRIP
PARAMETER
tVPS
tVPH
tP
DESCRIPTION
MIN
1
MAX
UNIT
µs
SCK VTRIP program voltage setup time
SCK VTRIP program voltage hold time
VTRIP program pulse width
1
µs
1
µs
tTSU
tTHD
tWC
VTRIP level setup time
10
10
µs
VTRIP level hold (stable) time
VTRIP write cycle time
ms
ms
ms
ms
V
10
tRP
VTRIP program cycle recovery period (between successive programming cycles)
SCK VTRIP program voltage off time before next cycle
10
0
tVPO
VP
VTRAN
Vta1
Programming voltage
15
18
5.0
VTRIP programmed voltage range
1.7
-0.1
-25
-25
-25
V
Initial VTRIP program voltage accuracy (VCC applied-VTRIP) (programmed at 25°C)
Subsequent VTRIP program voltage accuracy [(VCC applied-Vta1)-VTRIP] (programmed at 25°C)
VTRIP program voltage repeatability (successive program operations) (programmed at 25°C)
VTRIP Program variation after programming (0-75°C). (programmed at 25°C)
+0.4
+25
+25
+25
V
Vta2
mV
mV
mV
Vtr
Vtv
V
TRIP programming parameters are periodically sampled and are not 100% tested.
FN8130 Rev 2.00
June 15, 2006
Page 16 of 20
X5168, X5169 (Replaces X25268, X25169)
Typical Performance
t
PURST vs. Temperature
VCC Supply Current vs. Temperature (ISB
)
205
200
195
190
185
180
175
170
165
18
Watchdog Timer On (VCC = 5V)
16
14
12
Watchdog Timer On (VCC = 5V)
10
8
6
4
Watchdog Timer Off (VCC = 3V, 5V)
2
160
-40
0
25
Degrees °C
90
-40C
25C
Temp (°C)
90C
VTRIP vs. Temperature (programmed at 25°C)
5.025
VTRIP = 5V
5.000
4.975
3.525
V
TRIP = 3.5V
3.500
3.475
2.525
2.500
2.475
VTRIP = 2.5V
0
25
85
Temperature
FN8130 Rev 2.00
June 15, 2006
Page 17 of 20
X5168, X5169 (Replaces X25268, X25169)
Small Outline Package Family (SO)
A
D
h X 45°
(N/2)+1
N
A
PIN #1
I.D. MARK
E1
E
c
SEE DETAIL “X”
1
(N/2)
B
L1
0.010 M
C A B
e
H
C
A2
A1
GAUGE
PLANE
SEATING
PLANE
0.010
L
4° ±4°
0.004 C
b
0.010 M
C
A
B
DETAIL X
MDP0027
SMALL OUTLINE PACKAGE FAMILY (SO)
SO16
(0.150”)
SO16 (0.300”)
(SOL-16)
SO20
SO24
(SOL-24)
SO28
(SOL-28)
SYMBOL
SO-8
0.068
0.006
0.057
0.017
0.009
0.193
0.236
0.154
0.050
0.025
0.041
0.013
8
SO-14
0.068
0.006
0.057
0.017
0.009
0.341
0.236
0.154
0.050
0.025
0.041
0.013
14
(SOL-20)
0.104
0.007
0.092
0.017
0.011
0.504
0.406
0.295
0.050
0.030
0.056
0.020
20
TOLERANCE
MAX
NOTES
A
A1
A2
b
0.068
0.006
0.057
0.017
0.009
0.390
0.236
0.154
0.050
0.025
0.041
0.013
16
0.104
0.007
0.092
0.017
0.011
0.406
0.406
0.295
0.050
0.030
0.056
0.020
16
0.104
0.007
0.092
0.017
0.011
0.606
0.406
0.295
0.050
0.030
0.056
0.020
24
0.104
0.007
0.092
0.017
0.011
0.704
0.406
0.295
0.050
0.030
0.056
0.020
28
-
0.003
0.002
0.003
0.001
0.004
0.008
0.004
Basic
-
-
-
c
-
D
1, 3
E
-
E1
e
2, 3
-
L
0.009
Basic
-
L1
h
-
Reference
Reference
-
N
-
Rev. L 2/01
NOTES:
1. Plastic or metal protrusions of 0.006” maximum per side are not included.
2. Plastic interlead protrusions of 0.010” maximum per side are not included.
3. Dimensions “D” and “E1” are measured at Datum Plane “H”.
4. Dimensioning and tolerancing per ASME Y14.5M-1994
FN8130 Rev 2.00
June 15, 2006
Page 18 of 20
X5168, X5169 (Replaces X25268, X25169)
Plastic Dual-In-Line Packages (PDIP)
E
N
1
D
PIN #1
INDEX
A2
A
E1
SEATING
PLANE
L
c
A1
NOTE 5
2
N/2
eA
eB
e
b
b2
MDP0031
PLASTIC DUAL-IN-LINE PACKAGE
SYMBOL
PDIP8
0.210
0.015
0.130
0.018
0.060
0.010
0.375
0.310
0.250
0.100
0.300
0.345
0.125
8
PDIP14
0.210
0.015
0.130
0.018
0.060
0.010
0.750
0.310
0.250
0.100
0.300
0.345
0.125
14
PDIP16
0.210
0.015
0.130
0.018
0.060
0.010
0.750
0.310
0.250
0.100
0.300
0.345
0.125
16
PDIP18
PDIP20
0.210
0.015
0.130
0.018
0.060
0.010
1.020
0.310
0.250
0.100
0.300
0.345
0.125
20
TOLERANCE
MAX
NOTES
A
A1
A2
b
0.210
0.015
0.130
0.018
0.060
0.010
0.890
0.310
0.250
0.100
0.300
0.345
0.125
18
MIN
±0.005
±0.002
b2
c
+0.010/-0.015
+0.004/-0.002
±0.010
D
1
2
E
+0.015/-0.010
±0.005
E1
e
Basic
eA
eB
L
Basic
±0.025
±0.010
N
Reference
Rev. B 2/99
NOTES:
1. Plastic or metal protrusions of 0.010” maximum per side are not included.
2. Plastic interlead protrusions of 0.010” maximum per side are not included.
3. Dimensions E and eA are measured with the leads constrained perpendicular to the seating plane.
4. Dimension eB is measured with the lead tips unconstrained.
5. 8 and 16 lead packages have half end-leads as shown.
FN8130 Rev 2.00
June 15, 2006
Page 19 of 20
X5168, X5169 (Replaces X25268, X25169)
Thin Shrink Small Outline Plastic Packages (TSSOP)
M14.173
N
14 LEAD THIN SHRINK SMALL OUTLINE PLASTIC
PACKAGE
INDEX
AREA
0.25(0.010)
M
B M
E
E1
-B-
INCHES
MIN
MILLIMETERS
GAUGE
PLANE
SYMBOL
MAX
0.047
0.006
0.041
0.0118
0.0079
0.199
0.177
MIN
-
MAX
1.20
0.15
1.05
0.30
0.20
5.05
4.50
NOTES
A
A1
A2
b
-
-
1
2
3
0.002
0.031
0.0075
0.0035
0.195
0.169
0.05
0.80
0.19
0.09
4.95
4.30
-
L
0.25
0.010
-
0.05(0.002)
SEATING PLANE
A
9
-A-
D
c
-
D
3
-C-
E1
e
4
A2
e
A1
0.026 BSC
0.65 BSC
-
c
b
0.10(0.004)
E
0.246
0.256
6.25
0.45
6.50
0.75
-
0.10(0.004) M
C
A M B S
L
0.0177
0.0295
6
N
14
14
7
NOTES:
0o
8o
0o
8o
-
1. These package dimensions are within allowable dimensions of
JEDEC MO-153-AC, Issue E.
Rev. 2 4/06
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm
(0.006 inch) per side.
4. Dimension “E1” does not include interlead flash or protrusions. Inter-
lead flash and protrusions shall not exceed 0.15mm (0.006 inch) per
side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “b” does not include dambar protrusion. Allowable dambar
protrusion shall be 0.08mm (0.003 inch) total in excess of “b” dimen-
sion at maximum material condition. Minimum space between protru-
sion and adjacent lead is 0.07mm (0.0027 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact. (Angles in degrees)
© Copyright Intersil Americas LLC 2005-2006. All Rights Reserved.
All trademarks and registered trademarks are the property of their respective owners.
For additional products, see www.intersil.com/en/products.html
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such
modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are
current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its
subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN8130 Rev 2.00
June 15, 2006
Page 20 of 20
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