X5323PZ-4.5A [RENESAS]
CPU Supervisor with 32Kb SPI EEPROM; PDIP8, SOIC8; Temp Range: See Datasheet;
| 型号： | X5323PZ-4.5A |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | CPU Supervisor with 32Kb SPI EEPROM; PDIP8, SOIC8; Temp Range: See Datasheet 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 光电二极管 |
| 文件： | 总19页 (文件大小：826K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATASHEET
X5323, X5325 (Replaces X25323, X25325)
CPU Supervisor with 32kBit SPI EEPROM
FN8131
Rev 3.00
December 9, 2015
These devices combine four popular functions, Power-on
Reset Control, Watchdog Timer, Supply Voltage Supervision,
and Block Lock Protect Serial EEPROM Memory in one
package. This combination lowers system cost, reduces
board space requirements, and increases reliability.
Features
• Selectable watchdog timer
• Low VCC detection and reset assertion
- Five standard reset threshold voltages
- Re-program low VCC reset threshold voltage using
special programming sequence
Applying power to the device activates the power-on reset
circuit which holds RESET/RESET active for a period of
time. This allows the power supply and oscillator to stabilize
before the processor can execute code.
- Reset signal valid to VCC = 1V
• Determine watchdog or low voltage reset with a volatile
flag bit
The Watchdog Timer provides an independent protection
mechanism for microcontrollers. When the microcontroller
fails to restart a timer within a selectable time out interval,
the device activates the RESET/RESET signal. The user
selects the interval from three preset values. Once selected,
the interval does not change, even after cycling the power.
• Long battery life with low power consumption
- <50µA max standby current, watchdog on
- <1µA max standby current, watchdog off
- <400µA max active current during read
• 32kbits of EEPROM
• Built-in inadvertent write protection
- Power-up/power-down protection circuitry
- Protect 0, 1/4, 1/2 or all of EEPROM array with Block
Lock™ protection
The device’s low VCC detection circuitry protects the user’s
system from low voltage conditions, resetting the system
when VCC falls below the minimum VCC trip point.
RESET/RESET is asserted until VCC returns to proper
operating level and stabilizes. Five industry standard VTRIP
thresholds are available, however, Intersil’s unique circuits
allow the threshold to be reprogrammed to meet custom
requirements or to fine-tune the threshold for applications
requiring higher precision.
- In circuit programmable ROM mode
• 2MHz SPI interface modes (0,0 and 1,1)
• Minimize EEPROM programming time
- 32-byte page write mode
- Self-timed write cycle
- 5ms write cycle time (typical)
• 2.7V to 5.5V and 4.5V to 5.5V power supply
operation
• Available packages
- 14 Ld TSSOP, 8 Ld SOIC, 8 Ld PDIP
• Pb-free (RoHS compliant)
Block Diagram
WATCHDOG TRANSITION
DETECTOR
WATCHDOG
TIMER RESET
WP
PROTECT LOGIC
RESET/RESET
X5323 = RESET
SI
DATA
REGISTER
STATUS
REGISTER
SO
RESET AND
WATCHDOG
TIMEBASE
COMMAND
DECODE AND
CONTROL
LOGIC
X5325 = RESET
SCK
8kBITS
8kBITS
CS/WDI
V
THRESHOLD
RESET LOGIC
CC
16kBITS
POWER-ON AND
LOW VOLTAGE
RESET
V
+
-
CC
GENERATION
V
TRIP
FN8131 Rev 3.00
December 9, 2015
Page 1 of 19
X5323, X5325 (Replaces X25323, X25325)
Ordering Information
VCC RANGE VTRIP RANGE TEMP RANGE
PART NUMBER
RESET (Active Low)
PART MARKING
(V)
(V)
(°C)
PACKAGE
X5323PZ-4.5A (Note)
(No longer available, recommended
replacement: X5323S8Z-4.5A)
X5323P ZAL
X5323P ZAM
4.5 to 5.5
4.5 to 4.75
0 to +70
8 Ld PDIP** (Pb-free)
X5323PIZ-4.5A (Note)
-40 to +85
8 Ld PDIP** (Pb-free)
(No longer available, recommended
replacement: X5323S8IZ-4.5A)
X5323S8Z-4.5A (Note)
X5323S8IZ-4.5A* (Note)
X5323V14-4.5A
X5323 ZAL
X5323 ZAM
X5323 VAL
X5323P Z
0 to +70
-40 to +85
0 to +70
0 to +70
8 Ld SOIC (Pb-free)
8 Ld SOIC (Pb-free)
14 Ld TSSOP
X5323PZ (Note)
4.5 to 5.5
2.7 to 5.5
2.7 to 5.5
4.25 to 4.5
2.85 to 3.0
2.55 to 2.7
8 Ld PDIP** (Pb-free)
(No longer available, recommended
replacement: X5323S8Z)
X5323PIZ (Note)
(No longer available, recommended
replacement: X5323S8IZ)
X5323P ZI
-40 to +85
8 Ld PDIP** (Pb-free)
X5323S8Z* (Note)
X5323S8IZ* (Note)
X5323 Z
0 to +70
-40 to +85
0 to +70
8 Ld SOIC (Pb-free)
8 Ld SOIC (Pb-free)
8 Ld PDIP** (Pb-free)
X5323 ZI
X5323PZ-2.7A (Note)
(No longer available, recommended
replacement: X5323S8Z-2.7A)
X5323P ZAN
X5323PIZ-2.7A (Note)
(No longer available, recommended
replacement: X5323S8IZ-2.7A)
X5323P ZAP
-40 to +85
8 Ld PDIP** (Pb-free)
X5323S8Z-2.7A* (Note)
X5323S8IZ-2.7A* (Note)
X5323 ZAN
X5323 ZAP
X5323P ZF
0 to +70
-40 to +85
0 to +70
8 Ld SOIC (Pb-free)
8 Ld SOIC (Pb-free)
8 Ld PDIP** (Pb-free)
X5323PZ-2.7 (Note)
(No longer available, recommended
replacement: X5323S8Z-2.7)
X5323PIZ-2.7 (Note)
X5323P ZG
-40 to +85
8 Ld PDIP** (Pb-free)
(No longer available, recommended
replacement: X5323S8IZ-2.7)
X5323S8Z-2.7* (Note)
X5323S8IZ-2.7* (Note)
RESET (Active High)
X5325S8Z-4.5A (Note)
X5325S8IZ-4.5A (Note)
X5325S8Z* (Note)
X5323 ZF
X5323 ZG
0 to +70
8 Ld SOIC (Pb-free)
8 Ld SOIC (Pb-free)
-40 to +85
X5325 ZAL
X5325 ZAM
X5325 Z
4.5 to 5.5
4.5 to 5.5
2.7 to 5.5
2.7 to 5.5
4.5 to 4.75
4.25 to 4.5
2.85 to 3.0
2.55 to 2.7
0 to +70
-40 to +85
0 to +70
8 Ld SOIC (Pb-free)
8 Ld SOIC (Pb-free)
8 Ld SOIC (Pb-free)
8 Ld SOIC (Pb-free)
8 Ld SOIC (Pb-free)
8 Ld SOIC (Pb-free)
8 Ld SOIC (Pb-free)
8 Ld SOIC (Pb-free)
X5325S8IZ* (Note)
X5325 ZI
-40 to +85
0 to +70
X5325S8Z-2.7A (Note)
X5325S8IZ-2.7A (Note)
X5325S8Z-2.7* (Note)
X5325S8IZ-2.7* (Note)
X5325 ZAN
X5325 ZAP
X5325 ZF
X5325 ZG
-40 to +85
0 to +70
-40 to +85
*Add “-T1” for tape and reel. Please refer to TB347 for details on reel specifications.
**Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications.
NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and 100%
matte tin plate PLUS ANNEAL - e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations.
Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J
STD-020.
FN8131 Rev 3.00
December 9, 2015
Page 2 of 19
X5323, X5325 (Replaces X25323, X25325)
Pinouts
X5323, X5325
(8 LD SOIC, PDIP)
TOP VIEW
X5323, X5325
(14 LD TSSOP)
TOP VIEW
1
2
14
13
12
V
CS/WDI
SO
1
8
V
CC
CS/WDI
SO
CC
RESET/RESET
2
3
7
6
RESET/RESET
3
4
5
NC
NC
NC
WP
SCK
SI
11
10
9
NC
NC
WP
V
SS
4
5
NC
SCK
6
7
V
8
SI
SS
Pin Descriptions
PIN NUMBER
(SOIC/PDIP)
PIN NUMBER
TSSOP
PIN NAME
PIN FUNCTION
1
1
CS/WDI
Chip Select Input. CS HIGH, deselects the device and the SO output pin is at a high impedance
state. Unless a nonvolatile write cycle is underway, the device will be in the stand-by power mode.
CS LOW enables the device, placing it in the active power mode. Prior to the start of any operation
after power-up, a HIGH to LOW transition on CS is required.
Watchdog Input. A HIGH to LOW transition on the WDI pin restarts the watchdog timer. The
absence of a HIGH to LOW transition within the watchdog time out period results in
RESET/RESET going active.
2
5
2
8
SO
SI
Serial Output. SO is a push/pull serial data output pin. A read cycle shifts data out on this pin. The
falling edge of the serial clock (SCK) clocks the data out.
Serial Input. SI is a serial data input pin. Input all opcodes, byte addresses, and memory data on this
pin. The rising edge of the serial clock (SCK) latches the input data. Send all opcodes (Table 1),
addresses and data MSB first.
6
3
9
6
SCK
WP
Serial Clock. The serial clock controls the serial bus timing for data input and output. The rising edge
of SCK latches in the opcode, address, or data bits present on the SI pin. The falling edge of SCK
changes the data output on the SO pin.
Write Protect. The WP pin works in conjunction with a nonvolatile WPEN bit to “lock” the setting
of the watchdog timer control and the memory write protect bits.
4
8
7
7
VSS
VCC
Ground
14
13
Supply Voltage
RESET/
RESET
Reset Output. RESET/RESET is an active LOW/HIGH, open drain output which goes active
whenever VCC falls below the minimum VCC sense level. It will remain active until VCC rises above
the minimum VCC sense level for 200ms. RESET/RESET goes active if the watchdog timer is
enabled and CS remains either HIGH or LOW longer than the selectable watchdog time out
period. A falling edge of CS will reset the watchdog timer. RESET/RESET goes active on power-
up at about 1V and remains active for 200ms after the power supply stabilizes.
3 to 5,10 to 12
NC
No internal connections
FN8131 Rev 3.00
December 9, 2015
Page 3 of 19
X5323, X5325 (Replaces X25323, X25325)
and pulse CS/WDI LOW then HIGH. Remove VP and the
sequence is complete.
Principles of Operation
Power-on Reset
Application of power to the X5323/X5325 activates a power-on
reset circuit. This circuit goes active at about 1V and pulls the
RESET/RESET pin active. This signal prevents the system
microprocessor from starting to operate with insufficient voltage
or prior to stabilization of the oscillator. As long as
RESET/RESET pin is active, the device will not respond to any
Read/Write instruction. When VCC exceeds the device VTRIP
value for 200ms (nominal) the circuit releases RESET/RESET,
allowing the processor to begin executing code.
CS
V
P
SCK
SI
V
P
FIGURE 1. SET VTRIP VOLTAGE
Low Voltage Monitoring
Resetting the V
Voltage
TRIP
During operation, the X5323/X5325 monitors the VCC level and
asserts RESET/RESET if supply voltage falls below a preset
minimum VTRIP. The RESET/RESET signal prevents the
microprocessor from operating in a power fail or brown-out
condition. The RESET/RESET signal remains active until the
voltage drops below 1V. It also remains active until VCC returns
and exceeds VTRIP for 200ms.
This procedure sets the VTRIP to a “native” voltage level. For
example, if the current VTRIP is 4.4V and the VTRIP is reset, the
new VTRIP is something less than 1.7V. This procedure must
be used to set the voltage to a lower value.
To reset the VTRIP voltage, apply a voltage between 2.7V and
5.5V to the VCC pin. Tie the CS/WDI pin, the WP pin, and the
SCK pin HIGH. RESET/RESET and SO pins are left
unconnected. Then apply the programming voltage VP to the
SI pin ONLY and pulse CS/WDI LOW then HIGH. Remove VP
and the sequence is complete.
Watchdog Timer
The watchdog timer circuit monitors the microprocessor activity
by monitoring the WDI input. The microprocessor must toggle the
CS/WDI pin periodically to prevent a RESET/RESET signal.
The CS/WDI pin must be toggled from HIGH to LOW prior to
the expiration of the watchdog time out period. The state of two
nonvolatile control bits in the status register determine the
watchdog timer period. The microprocessor can change these
watchdog bits, or they may be “locked” by tying the WP pin
LOW and setting the WPEN bit HIGH.
CS
V
CC
SCK
SI
V
P
V
Threshold Reset Procedure
CC
The X5323/X5325 has a standard VCC threshold (VTRIP
)
FIGURE 2. RESET VTRIP VOLTAGE
voltage. This value will not change over normal operating and
storage conditions. However, in applications where the
standard VTRIP is not exactly right, or for higher precision in the
VTRIP value, the X5323/X5325 threshold may be adjusted.
Setting the V Voltage
TRIP
This procedure sets the VTRIP to a higher voltage value. For
example, if the current VTRIP is 4.4V and the new VTRIP is 4.6V,
this procedure directly makes the change. If the new setting is
lower than the current setting, then it is necessary to reset the
trip point before setting the new value.
To set the new VTRIP voltage, apply the desired VTRIP
threshold to the VCC pin and tie the CS/WDI pin and the WP
pin HIGH. RESET/RESET and SO pins are left unconnected.
Then apply the programming voltage VP to both SCK and SI
FN8131 Rev 3.00
December 9, 2015
Page 4 of 19
X5323, X5325 (Replaces X25323, X25325)
V
PROGRAMMING
EXECUTE
TRIP
RESET V
TRIP
SEQUENCE
SET V = V APPLIED =
CC
CC
DESIRED V
TRIP
EXECUTE
SET V
SEQUENCE
NEW V APPLIED =
CC
NEW V APPLIED =
CC
TRIP
OLD V APPLIED - ERROR
CC
OLD V APPLIED + ERROR
CC
EXECUTE
APPLY 5V TO V
CC
RESET V
TRIP
SEQUENCE
DECREMENT V
CC
(V = V - 10mV)
CC
CC
NO
RESET PIN
GOES ACTIVE?
YES
ERROR EMAX
ERROR EMAX
MEASURED V
-
TRIP
DESIRED V
TRIP
ERROR < EMAX
EMAX = MAXIMUM DESIRED ERROR
DONE
FIGURE 3. VTRIP PROGRAMMING SEQUENCE FLOW CHART
V
P
NC
NC
4.7k
RESET
4.7k
V
TRIP
1
2
3
4
8
7
6
5
ADJ.
NC
X5323,
X5325
+
PROGRAM
RESET V
TRIP
10k
10k
TEST V
TRIP
SET V
TRIP
FIGURE 4. SAMPLE VTRIP RESET CIRCUIT
FN8131 Rev 3.00
December 9, 2015
Page 5 of 19
X5323, X5325 (Replaces X25323, X25325)
Status Register
SPI Serial Memory
The RDSR instruction provides access to the status register.
The status register may be read at any time, even during a write
cycle. The status register is formatted as follows:
The memory portion of the device is a CMOS serial EEPROM
array with Intersil’s block lock protection. The array is internally
organized as x8. The device features a Serial Peripheral
Interface (SPI) and software protocol allowing operation on a
simple four-wire bus.
7
6
5
4
3
2
1
0
WPEN
FLB
WD1
WD0
BL1
BL0
WEL
WIP
The device utilizes Intersil’s proprietary Direct Write™ cell,
providing a minimum endurance of 100,000 cycles and a
minimum data retention of 100 years.
The Write-In-Progress (WIP) bit is a volatile, read only bit and
indicates whether the device is busy with an internal
nonvolatile write operation. The WIP bit is read using the
RDSR instruction. When set to a “1”, a nonvolatile write
operation is in progress. When set to a “0”, no write is in
progress.
The device is designed to interface directly with the
synchronous Serial Peripheral Interface (SPI) of many popular
microcontroller families. It contains an 8-bit instruction register
that is accessed via the SI input, with data being clocked in on
the rising edge of SCK. CS must be LOW during the entire
operation.
The Write Enable Latch (WEL) bit indicates the status of the
write enable latch. When WEL = 1, the latch is set HIGH and
when WEL = 0 the latch is reset LOW. The WEL bit is a
volatile, read only bit. It can be set by the WREN instruction
and can be reset by the WRDS instruction.
All instructions (Table 1), addresses and data are transferred
MSB first. Data input on the SI line is latched on the first rising
edge of SCK after CS goes LOW. Data is output on the SO line
by the falling edge of SCK. SCK is static, allowing the user to
stop the clock and then start it again to resume operations
where left off.
The block lock bits, BL0 and BL1, set the level of block lock
protection. These nonvolatile bits are programmed using the
WRSR instruction and allow the user to protect one quarter, one
half, all or none of the EEPROM array. Any portion of the array
that is block lock protected can be read but not written. It will
remain protected until the BL bits are altered to disable block lock
protection of that portion of memory.
Write Enable Latch
The device contains a write enable latch. This latch must be
SET before a write operation is initiated. The WREN instruction
will set the latch and the WRDI instruction will reset the latch
(Figure 3). This latch is automatically reset upon a power-up
condition and after the completion of a valid write cycle.
TABLE 1. INSTRUCTION SET
INSTRUCTION NAME
WREN
INSTRUCTION FORMAT*
0000 0110
OPERATION
Set the write enable latch (enable write operations)
Set flag bit
SFLB
0000 0000
WRDI/RFLB
RSDR
0000 0100
Reset the write enable latch/reset flag bit
Read status register
0000 0101
WRSR
0000 0001
Write status register (watchdog, block lock, WPEN and flag bits)
Read data from memory array beginning at selected address
Write data to memory array beginning at selected address
READ
0000 0011
WRITE
0000 0010
NOTE: *Instructions are shown MSB in leftmost position. Instructions are transferred MSB first.
TABLE 2. BLOCK PROTECT MATRIX
WREN CMD
STATUS REGISTER
DEVICE PIN
BLOCK
Protected Block
Protected
BLOCK
Unprotected Block
Protected
STATUS REGISTER
WPEN, BL0, BL1 WD0, WD1
Protected
WEL
WPEN
WP
X
0
1
1
1
X
1
0
X
0
Protected
Writable
Protected
X
Protected
Writable
Writable
1
Protected
Writable
Writable
FN8131 Rev 3.00
Page 6 of 19
December 9, 2015
X5323, X5325 (Replaces X25323, X25325)
.
In Circuit Programmable ROM Mode
STATUS
This mechanism protects the block lock and watchdog bits
from inadvertent corruption.
REGISTER BITS
ARRAY ADDRESSES PROTECTED
BL1
0
BL0
0
X5323/X5325
None (factory default)
$0C00 to $0FFF
$0800 to $0FFF
$0000 to $0FFF
In the locked state (programmable ROM mode) the WP pin is
LOW and the nonvolatile bit WPEN is “1”. This mode disables
nonvolatile writes to the device’s status register.
0
1
1
0
Setting the WP pin LOW while WPEN is a “1” while an internal
write cycle to the status register is in progress will not stop this
write operation, but the operation disables subsequent write
attempts to the status register.
1
1
The watchdog timer bits, WD0 and WD1, select the watchdog
time out period. These nonvolatile bits are programmed with
the WRSR instruction.
When WP is HIGH, all functions, including nonvolatile writes to
the status register operate normally. Setting the WPEN bit in
the status register to “0” blocks the WP pin function, allowing
writes to the status register when WP is HIGH or LOW. Setting
the WPEN bit to “1” while the WP pin is LOW activates the
programmable ROM mode, thus requiring a change in the WP
pin prior to subsequent status register changes. This allows
manufacturing to install the device in a system with WP pin
grounded and still be able to program the status register.
Manufacturing can then load configuration data, manufacturing
time and other parameters into the EEPROM, then set the
portion of memory to be protected by setting the block lock bits,
and finally set the “OTP mode” by setting the WPEN bit. Data
changes now require a hardware change.
STATUS REGISTER BITS
WATCHDOG TIME-OUT
WD1
WD0
(TYPICAL)
0
0
1
1
0
1
0
1
1.4s
600ms
200ms
disabled (factory default)
The FLAG bit shows the status of a volatile latch that can be
set and reset by the system using the SFLB and RFLB
instructions. The flag bit is automatically reset upon power-up.
This flag can be used by the system to determine whether a
reset occurs as a result of a watchdog time out or power
failure.
Read Sequence
When reading from the EEPROM memory array, CS is first
pulled low to select the device. The 8-bit READ instruction is
transmitted to the device, followed by the 16-bit address. After
the READ opcode and address are sent, the data stored in the
memory at the selected address is shifted out on the SO line.
The data stored in memory at the next address can be read
sequentially by continuing to provide clock pulses. The
address is automatically incremented to the next higher
address after each byte of data is shifted out. When the highest
address is reached, the address counter rolls over to address
Note: The Watch Dog Timer is shipped disabled. (WD1 = 1, WD0
= 1. The factory default for Memory Block Protection is ‘None’.
(BL1 = 0, BL0 = 0).
The nonvolatile WPEN bit is programmed using the WRSR
instruction. This bit works in conjunction with the WP pin to
provide an in-circuit programmable ROM function (Table 2). WP is
LOW and WPEN bit programmed HIGH disables all status
register write operations.
CS
0
1
2
3
4
5
6
7
8
9
10
20 21 22 23 24 25 26 27 28 29 30
SCK
SI
16-BIT ADDRESS
15 14 13
INSTRUCTION
3
2
1
0
DATA OUT
HIGH IMPEDANCE
SO
7
6
5
4
3
2
1
0
MSB
FIGURE 5. READ EEPROM ARRAY SEQUENCE
FN8131 Rev 3.00
December 9, 2015
Page 7 of 19
X5323, X5325 (Replaces X25323, X25325)
$0000 allowing the read cycle to be continued indefinitely. The
read operation is terminated by taking CS high. Refer to the
read EEPROM Array Sequence (Figure 1).
For the page write operation (byte or page write) to be
completed, CS can only be brought HIGH after bit 0 of the last
data byte to be written is clocked in. If it is brought HIGH at any
other time, the write operation will not be completed (Figure 4).
To read the status register, the CS line is first pulled low to
select the device followed by the 8-bit RDSR instruction. After
the RDSR opcode is sent, the contents of the status register
are shifted out on the SO line. Refer to the read status register
sequence (Figure 2).
To write to the status register, the WRSR instruction is followed
by the data to be written (Figure 5). Data bits 0 and 1 must be
“0”.
While the write is in progress following a status register or
EEPROM Sequence, the status register may be read to check
the WIP bit. During this time the WIP bit will be high.
Write Sequence
Prior to any attempt to write data into the device, the “Write
Enable” Latch (WEL) must first be set by issuing the WREN
instruction (Figure 3). CS is first taken LOW, then the WREN
instruction is clocked into the device. After all eight bits of the
instruction are transmitted, CS must then be taken HIGH. If the
user continues the write operation without taking CS HIGH
after issuing the WREN instruction, the write operation will be
ignored.
Operational Notes
The device powers-up in the following state:
• The device is in the low power standby state.
• A HIGH to LOW transition on CS is required to enter an
active state and receive an instruction.
• SO pin is high impedance.
• The write enable latch is reset.
• The flag bit is reset.
To write data to the EEPROM memory array, the user then
issues the WRITE instruction followed by the 16-bit address
and then the data to be written. Any unused address bits are
specified to be “0’s”. The WRITE operation minimally takes 32
clocks. CS must go low and remain low for the duration of the
operation. If the address counter reaches the end of a page
and the clock continues, the counter will roll back to the first
address of the page and overwrite any data that may have
been previously written.
• Reset signal is active for tPURST
.
Data Protection
The following circuitry has been included to prevent
inadvertent writes:
• A WREN instruction must be issued to set the write enable
latch.
Note: When writing more than one page, you must wait one
write cycle (10ms typical) when going from one page to
another. This is required for the internal nonvolatile memory to
be programmed correctly.
• CS must come HIGH at the proper clock count in order to
start a nonvolatile write cycle.
CS
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14
SCK
INSTRUCTION
SI
DATA OUT
HIGH IMPEDANCE
SO
7
6
5
4
3
2
1
0
MSB
FIGURE 6. READ STATUS REGISTER SEQUENCE
FN8131 Rev 3.00
December 9, 2015
Page 8 of 19
X5323, X5325 (Replaces X25323, X25325)
Symbol Table
CS
WAVEFORM
INPUTS
OUTPUTS
0
1
2
3
4
5
6
7
Must be
steady
Will be
steady
SCK
SI
May change
from LOW
to HIGH
Will change
from LOW
to HIGH
May change
from HIGH
to LOW
Will change
from HIGH
to LOW
HIGH IMPEDANCE
SO
Don’t Care:
Changes
Allowed
Changing:
State Not
Known
FIGURE 7. WRITE ENABLE LATCH SEQUENCE
N/A
Center Line
is High
Impedance
CS
0
1
2
3
4
5
6
7
8
9
10
20 21 22 23 24 25 26 27 28 29 30 31
SCK
INSTRUCTION
16-BIT ADDRESS
15 14 13
DATA BYTE 1
3
2
1
0
7
6
5
4
3
2
1
0
SI
CS
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
SCK
SI
DATA BYTE 2
DATA BYTE 3
DATA BYTE N
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
6
5
4
3
2
1
0
FIGURE 8. WRITE SEQUENCE
CS
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
SCK
INSTRUCTION
DATA BYTE
7
6
5
4
3
2
1
0
SI
HIGH IMPEDANCE
SO
FIGURE 9. STATUS REGISTER WRITE SEQUENCE
FN8131 Rev 3.00
December 9, 2015
Page 9 of 19
X5323, X5325 (Replaces X25323, X25325)
Absolute Maximum Ratings
Thermal Information
Temperature Under Bias . . . . . . . . . . . . . . . . . . . . .-65°C to +135°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Voltage on any Pin with Respect to VSS . . . . . . . . . . . .-1.0V to +7V
DC Output Current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5mA
Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
*Pb-free PDIPs can be used for through hole wave solder
processing only. They are not intended for use in Reflow solder
processing applications.
Operating Conditions
Temperature Range (Industrial) . . . . . . . . . . . . . . . . .-40°C to +85°C
Temperature Range (Commercial). . . . . . . . . . . . . . . . 0°C to +70°C
Supply Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V to 5.5V
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
DC Electrical Specifications Over the recommended operating conditions, unless otherwise specified
PARAMETER
SYMBOL
ICC1
ICC2
ISB1
ISB2
ISB3
ILI
TEST CONDITIONS
SCK = VCC x 0.1/VCC x 0.9 @ 2MHz, SO = Open
SCK = VCC x 0.1/VCC x 0.9 @ 2MHz, SO = Open
CS = VCC, VIN = VSS or VCC, VCC = 5.5V
CS = VCC, VIN = VSS or VCC, VCC = 5.5V
CS = VCC, VIN = VSS or VCC, VCC =3.6V
VIN = VSS to VCC
MIN
TYP
MAX
UNIT
mA
mA
µA
µA
µA
µA
µA
V
V
CC Write Current (active)
5
VCC Read Current (active)
0.4
V
V
CC Standby Current WDT = OFF
CC Standby Current WDT = ON
1
50
VCC Standby Current WDT = ON
Input Leakage Current
Output Leakage Current
Input LOW Voltage
20
0.1
0.1
10
ILO
VOUT = VSS to VCC
10
VIL
-0.5
VCC x 0.3
(Note 1)
Input HIGH Voltage
VIH
VCC x 0.7
VCC + 0.5
V
(Note 1)
Output LOW Voltage
Output LOW Voltage
Output LOW Voltage
Output HIGH Voltage
Output HIGH Voltage
Output HIGH Voltage
Reset Output LOW Voltage
VOL1
VOL2
VOL3
VOH1
VOH2
VOH3
VOLS
VCC > 3.3V, IOL = 2.1mA
2V < VCC 3.3V, IOL = 1mA
VCC 2V, IOL = 0.5mA
VCC > 3.3V, IOH = -1.0mA
2V < VCC 3.3V, IOH = -0.4mA
VCC 2V, IOH = -0.25mA
IOL = 1mA
0.4
0.4
0.4
V
V
V
V
V
V
V
VCC - 0.8
VCC - 0.4
VCC - 0.2
0.4
Capacitance
TA = +25°C, f = 1MHz, VCC = 5V
SYMBOL
TEST
CONDITIONS
VOUT = 0V
VIN = 0V
MAX
UNIT
pF
C
OUT (Note 2) Output Capacitance (SO, RESET/RESET)
IN (Note 2) Input Capacitance (SCK, SI, CS, WP)
NOTES:
8
6
C
pF
1. VIL min and VIH max are for reference only and are not tested.
2. This parameter is periodically sampled and not 100% tested.
FN8131 Rev 3.00
December 9, 2015
Page 10 of 19
X5323, X5325 (Replaces X25323, X25325)
Equivalent AC Load Circuit at 5V V
AC Test Conditions
Input pulse levels
CC
VCC x 0.1 to VCC x 0.9
10ns
5V
5V
Input rise and fall times
Input and output timing level
4.6k
VCC x 0.5
2.06k
OUTPUT
3.03k
RESET/RESET
30pF
100pF
AC Electrical Specifications
Input pulse levels = VCC x 0.1 to VCC x 0.9; input rise and fall times = 10ns; input and ouput timing
level = VCC x 0.5. Over recommended operating conditions, unless otherwise specified.
2.7 TO 5.5V
PARAMETER
SYMBOL
MIN
MAX
UNIT
SERIAL INPUT TIMING
Clock Frequency
Cycle Time
fSCK
tCYC
tLEAD
tLAG
0
2
MHz
ns
500
250
250
200
250
50
CS Lead Time
ns
CS Lag Time
ns
Clock HIGH Time
Clock LOW Time
Data Set-up Time
Data Hold Time
Input Rise Time
Input Fall Time
tWH
ns
tWL
ns
tSU
ns
tH
50
ns
t
RI (Note 3)
100
100
ns
tFI (Note 3)
tCS
ns
CS Deselect Time
Write Cycle Time
500
ns
t
WC (Note 4)
10
ms
Serial Input Timing
t
CS
CS
t
t
LAG
LEAD
SCK
t
t
t
t
FI
SU
H
RI
SI
MSB IN
LSB IN
HIGH IMPEDANCE
SO
FN8131 Rev 3.00
December 9, 2015
Page 11 of 19
X5323, X5325 (Replaces X25323, X25325)
Serial Output Timing
2.7 TO 5.5V
MAX
PARAMETER
Clock Frequency
SYMBOL
MIN
UNIT
MHz
ns
fSCK
tDIS
0
2
Output Disable Time
250
250
Output Valid From Clock Low
Output Hold Time
tV
ns
tHO
0
ns
Output Rise Time
tRO (Note 3)
100
100
ns
Output Fall Time
t
FO (Note 3)
ns
NOTES:
3. This parameter is periodically sampled and not 100% tested.
4. tWC is the time from the rising edge of CS after a valid write sequence has been sent to the end of the self-timed internal nonvolatile write cycle.
Serial Output Timing
CS
t
t
t
LAG
CYC
WH
SCK
SO
SI
t
t
t
t
DIS
V
HO
WL
MSB OUT
MSB–1 OUT
LSB OUT
ADDR
LSB IN
Power-Up and Power-Down Timing
V
V
TRIP
TRIP
V
CC
t
PURST
0V
t
t
F
PURST
t
RPD
t
R
RESET (X5323)
RESET (X5323)
FN8131 Rev 3.00
December 9, 2015
Page 12 of 19
X5323, X5325 (Replaces X25323, X25325)
RESET Output Timing
SYMBOL
PARAMETER
MIN
4.5
TYP
4.63
4.38
2.92
2.63
20
MAX
4.75
4.5
UNIT
V
VTRIP
Reset Trip Point Voltage, X5323-4.5A, X5323-4.5A
Reset Trip Point Voltage, X5323, X5325
4.25
2.85
2.55
V
Reset Trip Point Voltage, X5323-2.7A, X5325-2.7A
Reset Trip Point Voltage, X5323-2.7, X5325-2.7
VTRIP Hysteresis (HIGH to LOW vs LOW to HIGH VTRIP Voltage)
Power-up Reset Time-Out
3.0
V
2.7
V
VTH
mV
ms
ns
µs
µs
V
tPURST
100
200
280
500
t
RPD (Note 5) VCC Detect To Reset/Output
tF (Note 5) VCC Fall Time
100
100
1
tR (Note 5) VCC Rise Time
VRVALID
NOTE:
Reset Valid VCC
5. This parameter is periodically sampled and not 100% tested.
CS/WDI vs RESET/RESET Timing
CS/WDI
t
CST
RESET
t
t
t
t
RST
WDO
RST
WDO
RESET
RESET/RESET Output Timing
SYMBOL
PARAMETER
MIN
TYP
MAX
UNIT
tWDO
Watchdog Time-Out Period
WD1 = 1, WD0 = 0
100
450
1
200
600
1.4
300
800
2
ms
ms
s
WD1 = 0, WD0 = 1
WD1 = 0, WD0 = 0
tCST
tRST
CS Pulse Width to Reset the Watchdog
Reset Time-Out
400
100
ns
ms
200
300
FN8131 Rev 3.00
December 9, 2015
Page 13 of 19
X5323, X5325 (Replaces X25323, X25325)
V
Set Conditions
TRIP
t
THD
V
V
CC
TRIP
t
TSU
t
RP
t
t
VPH
t
P
VPS
CS
t
t
t
VPO
VPH
VPS
V
P
SCK
SI
V
t
P
VPO
V
Reset Conditions
TRIP
V
*
CC
t
RP
t
t
VP1
t
P
VPS
CS
t
t
t
VPS
VPO
VPH
V
CC
V
SCK
SI
t
P
VPO
*V > PROGRAMMED V
CC
TRIP
V
Programming Specifications VCC = 1.7 to 5.5V; Temperature = 0°C to +70°C.
TRIP
PARAMETER
DESCRIPTION
MIN
1
MAX
UNIT
µs
tVPS
tVPH
tP
SCK VTRIP Program Voltage Set-up Time
SCK VTRIP Program Voltage Hold Time
VTRIP Program Pulse Width
1
µs
1
µs
tTSU
tTHD
VTRIP Level Set-up Time
10
10
µs
VTRIP Level Hold (Stable) Time
ms
FN8131 Rev 3.00
December 9, 2015
Page 14 of 19
X5323, X5325 (Replaces X25323, X25325)
V
Programming Specifications VCC = 1.7 to 5.5V; Temperature = 0°C to +70°C. (Continued)
TRIP
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
ms
ms
ms
V
tWC
tRP
tVPO
VP
VTRAN
Vta1
VTRIP Write Cycle Time
10
VTRIP Program Cycle Recovery Period (Between Successive Programming Cycles)
SCK VTRIP Program Voltage Off-Time Before Next Cycle
10
0
Programming Voltage
15
18
5.0
VTRIP Programed Voltage Range
1.7
-0.1
-25
-25
-25
V
Initial VTRIP Program Voltage Accuracy (VCC Applied-VTRIP) (Programmed at +25°C)
Subsequent VTRIP Program Voltage Accuracy [(VCC Applied-Vta1)-VTRIP] (Programmed at +25°C)
VTRIP Program Voltage Repeatability (Successive Program Operations; Programmed at +25°C)
VTRIP Program Variation After Programming (0°C to +75°C; Programmed at +25°C)
+0.4
+25
+25
+25
V
Vta2
mV
mV
mV
Vtr
Vtv
NOTE:
6. VTRIP programming parameters are periodically sampled and are not 100% tested.
Typical Performance Curves
1.9
1.8
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1.0
18
WATCHDOG TIMER ON (V = 5V)
CC
16
14
12
10
8
-40°C
WATCHDOG TIMER ON (V = 5V)
+25°C
CC
+90°C
6
4
2
WATCHDOG TIMER OFF (V = 3V, 5V)
CC
0
-40
25
90
)
1.7
2.4
3.1
3.8
4.5
5.2
TEMPERATURE (°C)
VOLTAGE (V)
FIGURE 10. V SUPPLY CURRENT vs TEMPERATURE (I
FIGURE 11. T
vs VOLTAGE/TEMPERATURE (WD1, 0 = 1, 1)
WDO
CC
SB
0.80
0.75
0.70
0.65
0.60
0.55
0.50
5.025
5.000
V
= 5V
TRIP
-40°C
4.975
3.525
3.500
3.475
2.525
2.500
2.475
+25°C
+90°C
V
= 3.5V
= 2.5V
TRIP
V
TRIP
0.45
1.7
0
25
85
2.4
3.1
3.8
4.5
5.2
TEMPERATURE (°C)
VOLTAGE (V)
FIGURE 12. V
vs TEMPERATURE (PROGRAMMED AT +25°C)
FIGURE 13. T
vs VOLTAGE/TEMPERATURE (WD1, 0 = 1, 0)
WDO
TRIP
FN8131 Rev 3.00
December 9, 2015
Page 15 of 19
X5323, X5325 (Replaces X25323, X25325)
Typical Performance Curves
205
200
195
190
185
180
175
170
165
160
205
200
195
190
185
180
175
170
165
160
-40°C
+25°C
+90°C
-40
25
90
1.7
2.4
3.1
3.8
4.5
5.2
VOLTAGE (V)
TEMPERATURE (°C)
FIGURE 14. T
vs TEMPERATURE
FIGURE 15. T
vs VOLTAGE/TEMPERATURE (WD1, 0 0 = 0, 1)
WDO
PURST
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web to make sure that
you have the latest revision.
DATE
REVISION
FN8131.3
CHANGE
Updated Ordering Information Table on page 2.
December 9, 2015
Added Revision History and About Intersil sections.
Replaced POD MDP0027 with M8.15E
About Intersil
Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products
address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets.
For the most updated datasheet, application notes, related documentation and related parts, please see the respective product
information page found at www.intersil.com.
You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask.
Reliability reports are also available from our website at www.intersil.com/support
FN8131 Rev 3.00
December 9, 2015
Page 16 of 19
X5323, X5325 (Replaces X25323, X25325)
Plastic Dual-In-Line Packages (PDIP)
E
N
1
D
PIN #1
INDEX
A2
A
E1
SEATING
PLANE
L
c
A1
NOTE 5
2
N/2
eA
eB
e
b
b2
MDP0031
PLASTIC DUAL-IN-LINE PACKAGE
INCHES
SYMBOL
PDIP8
0.210
0.015
0.130
0.018
0.060
0.010
0.375
0.310
0.250
0.100
0.300
0.345
0.125
8
PDIP14
0.210
0.015
0.130
0.018
0.060
0.010
0.750
0.310
0.250
0.100
0.300
0.345
0.125
14
PDIP16
0.210
0.015
0.130
0.018
0.060
0.010
0.750
0.310
0.250
0.100
0.300
0.345
0.125
16
PDIP18
PDIP20
0.210
0.015
0.130
0.018
0.060
0.010
1.020
0.310
0.250
0.100
0.300
0.345
0.125
20
TOLERANCE
MAX
NOTES
A
A1
A2
b
0.210
0.015
0.130
0.018
0.060
0.010
0.890
0.310
0.250
0.100
0.300
0.345
0.125
18
MIN
±0.005
±0.002
b2
c
+0.010/-0.015
+0.004/-0.002
±0.010
D
1
2
E
+0.015/-0.010
±0.005
E1
e
Basic
eA
eB
L
Basic
±0.025
±0.010
N
Reference
Rev. C 2/07
NOTES:
1. Plastic or metal protrusions of 0.010” maximum per side are not included.
2. Plastic interlead protrusions of 0.010” maximum per side are not included.
3. Dimensions E and eA are measured with the leads constrained perpendicular to the seating plane.
4. Dimension eB is measured with the lead tips unconstrained.
5. 8 and 16 lead packages have half end-leads as shown.
FN8131 Rev 3.00
December 9, 2015
Page 17 of 19
X5323, X5325 (Replaces X25323, X25325)
Package Outline Drawing
M8.15E
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
Rev 0, 08/09
4
4.90 ± 0.10
A
DETAIL "A"
0.22 ± 0.03
B
6.0 ± 0.20
3.90 ± 0.10
4
PIN NO.1
ID MARK
5
(0.35) x 45°
4° ± 4°
0.43 ± 0.076
1.27
0.25 M C A B
SIDE VIEW “B”
TOP VIEW
1.75 MAX
1.45 ± 0.1
0.25
GAUGE PLANE
C
SEATING PLANE
0.175 ± 0.075
SIDE VIEW “A
0.10 C
0.63 ±0.23
DETAIL "A"
(0.60)
(1.27)
NOTES:
(1.50)
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3. Unless otherwise specified, tolerance : Decimal ± 0.05
(5.40)
4. Dimension does not include interlead flash or protrusions.
Interlead flash or protrusions shall not exceed 0.25mm per side.
The pin #1 identifier may be either a mold or mark feature.
Reference to JEDEC MS-012.
5.
6.
TYPICAL RECOMMENDED LAND PATTERN
FN8131 Rev 3.00
December 9, 2015
Page 18 of 19
X5323, X5325 (Replaces X25323, X25325)
Thin Shrink Small Outline Plastic Packages (TSSOP)
M14.173
N
14 LEAD THIN SHRINK SMALL OUTLINE PLASTIC
PACKAGE
INDEX
AREA
0.25(0.010)
M
B M
E
E1
-B-
INCHES
MIN
MILLIMETERS
GAUGE
PLANE
SYMBOL
MAX
0.047
0.006
0.041
0.0118
0.0079
0.199
0.177
MIN
-
MAX
1.20
0.15
1.05
0.30
0.20
5.05
4.50
NOTES
A
A1
A2
b
-
-
1
2
3
0.002
0.031
0.0075
0.0035
0.195
0.169
0.05
0.80
0.19
0.09
4.95
4.30
-
L
0.25
0.010
-
0.05(0.002)
SEATING PLANE
A
9
-A-
D
c
-
D
3
-C-
E1
e
4
A2
e
A1
0.026 BSC
0.65 BSC
-
c
b
0.10(0.004)
E
0.246
0.256
6.25
0.45
6.50
0.75
-
0.10(0.004) M
C
A M B S
L
0.0177
0.0295
6
N
14
14
7
NOTES:
0o
8o
0o
8o
-
1. These package dimensions are within allowable dimensions of
JEDEC MO-153-AC, Issue E.
Rev. 2 4/06
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm
(0.006 inch) per side.
4. Dimension “E1” does not include interlead flash or protrusions. Inter-
lead flash and protrusions shall not exceed 0.15mm (0.006 inch) per
side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “b” does not include dambar protrusion. Allowable dambar
protrusion shall be 0.08mm (0.003 inch) total in excess of “b” dimen-
sion at maximum material condition. Minimum space between protru-
sion and adjacent lead is 0.07mm (0.0027 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact. (Angles in degrees)
© Copyright Intersil Americas LLC 2003-2015. All Rights Reserved.
All trademarks and registered trademarks are the property of their respective owners.
For additional products, see www.intersil.com/en/products.html
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such
modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are
current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its
subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN8131 Rev 3.00
December 9, 2015
Page 19 of 19
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