X5328V14Z-4.5A [RENESAS]
1-CHANNEL POWER SUPPLY MANAGEMENT CKT, PDSO14, ROHS COMPLIANT, PLASTIC, TSSOP-14;
| 型号： | X5328V14Z-4.5A |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | 1-CHANNEL POWER SUPPLY MANAGEMENT CKT, PDSO14, ROHS COMPLIANT, PLASTIC, TSSOP-14 光电二极管 |
| 文件： | 总21页 (文件大小：330K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
X5328, X5329
®
(Replaces X25328, X25329)
Data Sheet
October 17, 2005
FN8132.1
DESCRIPTION
CPU Supervisor with 32Kbit SPI EEPROM
These devices combine three popular functions, Power-
on Reset Control, Supply Voltage Supervision, and Block
Lock Protect Serial EEPROM Memory in one package.
This combination lowers system cost, reduces board
space requirements, and increases reliability.
FEATURES
• Low V detection and reset assertion
CC
—Five standard reset threshold voltages
—Re-program low V reset threshold voltage
CC
using special programming sequence
Applying power to the device activates the power-on
reset circuit which holds RESET/RESET active for a
period of time. This allows the power supply and oscilla-
tor to stabilize before the processor can execute code.
—Reset signal valid to V = 1V
CC
• Long battery life with low power consumption
—<1µA max standby current
—<400µA max active current during read
• 32Kbits of EEPROM
The device’s low V
detection circuitry protects the
CC
• Built-in inadvertent write protection
—Power-up/power-down protection circuitry
—Protect 0, 1/4, 1/2 or all of EEPROM array with
user’s system from low voltage conditions by holding
RESET/RESET active when V falls below a mini-
CC
mum V trip point. RESET/RESET remains asserted
CC
™
Block Lock protection
until V
returns to proper operating level and stabi-
CC
—In circuit programmable ROM mode
• 2MHz SPI interface modes (0,0 & 1,1)
• Minimize EEPROM programming time
—32-byte page write mode
lizes. Five industry standard V
thresholds are
TRIP
available, however, Intersil’s unique circuits allow the
threshold to be reprogrammed to meet custom
requirements or to fine-tune the threshold in applica-
tions requiring higher precision.
—Self-timed write cycle
—5ms write cycle time (typical)
• 2.7V to 5.5V and 4.5V to 5.5V power supply
operation
• Available packages
—14 Ld TSSOP, 8 Ld SOIC, 8 Ld PDIP
• Pb-free plus anneal available (RoHS compliant)
BLOCK DIAGRAM
WP
Protect Logic
SI
Data
Status
Register
Register
SO
Command
Decode &
Control
SCK
CS
8Kbits
8Kbits
Logic
16Kbits
Reset
Timebase
RESET/RESET
Power-on and
Low Voltage
Reset
VCC
+
-
Generation
X5328 = RESET
X5329 = RESET
VTRIP
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2005. All Rights Reserved
1
All other trademarks mentioned are the property of their respective owners.
X5328, X5329
Ordering Information
PART NUMBER
PART NUMBER
RESET
RESET
PART
PART
V
CC RANGE
TEMP
(ACTIVE LOW)
MARKING
(ACTIVE HIGH)
MARKING
(V)
V
TRIP RANGE RANGE (°C)
PACKAGE
8 Ld PDIP
X5328P-4.5A
X5329P-4.5A
4.5-5.5
4.5-4.75
0 to 70
0 to 70
X5328PZ-4.5A (Note) X5328P Z AL X5329PZ-4.5A (Note) X5329P Z AL
X5328PI-4.5A X5329PI-4.5A
X5328PIZ-4.5A (Note) X5328P Z AM X5329PIZ-4.5A (Note) X5329P Z AM
X5328S8-4.5A X5328 AL X5329S8-4.5A
X5328S8Z-4.5A (Note) X5328 Z AL X5329S8Z-4.5A (Note) X5329 Z AL
8 Ld PDIP (Pb-free)
8 Ld PDIP
-40 to 85
-40 to 85
0 to 70
8 Ld PDIP (Pb-free)
8 Ld SOIC
0 to 70
8 Ld SOIC (Pb-free)
8 Ld SOIC
X5328S8I-4.5A
X5328 AM
X5329S8I-4.5A
-40 to 85
-40 to 85
X5328S8IZ-4.5A
(Note)
X5328 Z AM X5329S8IZ-4.5A
(Note)
X5329 Z AM
X5329V Z AL
X5329V Z AM
8 Ld SOIC (Pb-free)
X5328V14-4.5A
X5329V14-4.5A
0 to 70
0 to 70
14 Ld TSSOP
X5328V14Z-4.5A
(Note)
X5328V Z AL X5329V14Z-4.5A
(Note)
14 Ld TSSOP
(Pb-free)
X5328V14I-4.5A
X5329V14I-4.5A
-40 to 85
-40 to 85
14 Ld TSSOP
X5328V14IZ-4.5A
(Note)
X5328V Z AM X5329V14IZ-4.5A
(Note)
14 Ld TSSOP
(Pb-free)
X5328P
X5328P
X5329P
X5329P
4.5-5.5
4.25-4.5
0 to 70
0 to 70
8 Ld PDIP
X5328PZ (Note)
X5328PI
X5328P Z
X5328P I
X5328P Z I
X5328
X5329PZ (Note)
X5329PI
X5329P Z
X5329P I
X5329P Z I
8 Ld PDIP (Pb-free)
8 Ld PDIP
-40 to 85
-40 to 85
0 to 70
X5328PIZ (Note)
X5328S8*
X5329PIZ (Note)
X5329S8*
8 Ld PDIP (Pb-free)
8 Ld SOIC
X5328S8Z* (Note)
X5328S8I*
X5328 Z
X5328 I
X5329S8Z* (Note)
X5329S8I*
X5329 Z
0 to 70
8 Ld SOIC (Pb-free)
8 Ld SOIC
-40 to 85
-40 to 85
0 to 70
X5328S8IZ* (Note)
X5328V14*
X5328 Z I
X5328V
X5329S8IZ* (Note)
X5329V14*
X5329 Z I
X5329V Z
8 Ld SOIC (Pb-free)
14 Ld TSSOP
X5328V14Z* (Note)
X5328V Z
X5329V14Z* (Note)
0 to 70
14 Ld TSSOP
(Pb-free)
X5328V14I*
X5329V14I*
-40 to 85
-40 to 85
14 Ld TSSOP
X5328V14IZ* (Note)
X5328V Z I
X5329V14IZ* (Note)
X5329V Z I
14 Ld TSSOP
(Pb-free)
X5328P-2.7A
X5329P-2.7A
2.7-5.5
2.85-3.0
0 to 70
0 to 70
8 Ld PDIP
X5328PZ-2.7A (Note) X5328P Z AN X5329PZ-2.7A (Note) X5329P Z AN
X5328PI-2.7A X5329PI-2.7A
X5328PIZ-2.7A (Note) X5328P Z AP X5329PIZ-2.7A (Note) X5329P Z AP
X5328S8-2.7A X5328 AN X5329S8-2.7A
X5328S8Z-2.7A (Note) X5328 Z AN X5329S8Z-2.7A (Note) X5329 Z AN
8 Ld PDIP (Pb-free)
8 Ld PDIP
-40 to 85
-40 to 85
0 to 70
8 Ld PDIP (Pb-free)
8 Ld SOIC
0 to 70
8 Ld SOIC (Pb-free)
8 Ld SOIC
X5328S8I-2.7A
X5328 AP
X5329S8I-2.7A
-40 to 85
-40 to 85
X5328S8IZ-2.7A
(Note)
X5328 Z AP X5329S8IZ-2.7A
(Note)
X5329 Z AP
8 Ld SOIC (Pb-free)
X5328V14-2.7A
X5328V AN
X5329V14-2.7A
0 to 70
0 to 70
14 Ld TSSOP
X5328V14Z-2.7A
(Note)
X5328V Z AN X5329V14Z-2.7A
(Note)
X5329V Z AN
14 Ld TSSOP
(Pb-free)
FN8132.1
2
October 17, 2005
X5328, X5329
Ordering Information (Continued)
PART NUMBER
PART NUMBER
RESET
PART
RESET
PART
V
CC RANGE
TEMP
(ACTIVE LOW)
MARKING
(ACTIVE HIGH)
MARKING
(V)
V
TRIP RANGE RANGE (°C)
PACKAGE
X5328V14I-2.7A
X5329V14I-2.7A
2.7-5.5
2.7-5.5
2.85-3.0
-40 to 85
-40 to 85
14 Ld TSSOP
X5328V14IZ-2.7A
(Note)
X5328V Z AP X5329V14IZ-2.7A
(Note)
X5329V Z AP
14 Ld TSSOP
(Pb-free)
X5328P-2.7
X5328P F
X5328P Z F X5329PZ-2.7 (Note)
X5328P G X5329PI-2.7
X5329P-2.7
X5329P F
X5329P Z F
X5329P G
2.55-2.7
0 to 70
0 to 70
8 Ld PDIP
X5328PZ-2.7 (Note)
X5328PI-2.7
8 Ld PDIP (Pb-free)
8 Ld PDIP
-40 to 85
-40 to 85
0 to 70
X5328PIZ-2.7 (Note) X5328P Z G X5329PIZ-2.7 (Note) X5329P Z G
8 Ld PDIP (Pb-free)
8 Ld SOIC
X5328S8-2.7*
X5328S8Z-2.7* (Note) X5328 Z F
X5328S8I-2.7* X5328 G
X5328 F
X5329S8-2.7*
X5329S8Z-2.7* (Note) X5329 Z F
X5329S8I-2.7*
0 to 70
8 Ld SOIC (Pb-free)
8 Ld SOIC
-40 to 85
-40 to 85
0 to 70
X5328S8IZ-2.7* (Note) X5328 Z G
X5328V14-2.7*
X5329S8IZ-2.7* (Note) X5329 Z G
X5329V14-2.7*
8 Ld SOIC (Pb-free)
14 Ld TSSOP
X5328V14Z-2.7*
(Note)
X5328V Z F X5329V14Z-2.7*
X5329V Z F
0 to 70
14 Ld TSSOP
(Pb-free)
(Note)
X5328V14I-2.7*
X5329V14I-2.7*
-40 to 85
-40 to 85
14 Ld TSSOP
X5328V14IZ-2.7*
(Note)
X5328V Z G X5329V14IZ-2.7*
(Note)
X5329V Z G
14 Ld TSSOP
(Pb-free)
*Add "T1" suffix for tape and reel.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin
plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are
MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
FN8132.1
3
October 17, 2005
X5328, X5329
PIN DESCRIPTION
Pin
Pin
(SOIC/PDIP) TSSOP
Name
Function
1
1
CS
Chip Select Input. CS HIGH, deselects the device and the SO output pin is at
a high impedance state. Unless a nonvolatile write cycle is underway, the device
will be in the standby power mode. CS LOW enables the device, placing it in the
active power mode. Prior to the start of any operation after power-up, a HIGH to
LOW transition on CS is required.
2
5
2
8
SO
SI
Serial Output. SO is a push/pull serial data output pin. A read cycle shifts data out
on this pin. The falling edge of the serial clock (SCK) clocks the data out.
Serial Input. SI is a serial data input pin. Input all opcodes, byte addresses, and
memory data on this pin. The rising edge of the serial clock (SCK) latches the input
data. Send all opcodes (Table 1), addresses and data MSB first.
6
3
9
6
SCK
WP
Serial Clock. The Serial Clock controls the serial bus timing for data input and out-
put. The rising edge of SCK latches in the opcode, address, or data bits present on
the SI pin. The falling edge of SCK changes the data output on the SO pin.
Write Protect. The WP pin works in conjunction with a nonvolatile WPEN bit to
“lock” the setting of the Watchdog Timer control and the memory write protect bits.
4
8
7
7
VSS
VCC
Ground
14
13
Supply Voltage
RESET/ Reset Output. RESET/RESET is an active LOW/HIGH, open drain output
RESET
which goes active whenever VCC falls below the minimum VCC sense level. It
will remain active until VCC rises above the minimum VCC sense level for 200ms.
RESET/RESET goes active on power-up at about 1V and remains active for
200ms after the power supply stabilizes.
3-5,10-12
NC
No internal connections
PIN CONFIGURATION
14 Ld TSSOP
8 Ld SOIC/PDIP
1
2
3
4
5
6
7
14
13
12
11
10
9
VCC
CS
SO
NC
RESET/RESET
VCC
1
8
7
6
5
CS
SO
NC
NC
NC
SCK
SI
2
3
4
RESET/RESET
NC
NC
X5328/29
X5328/29
WP
SCK
SI
VCC
WP
VSS
8
FN8132.1
4
October 17, 2005
X5328, X5329
PRINCIPLES OF OPERATION
Power-On Reset
Figure 1. Set V
Voltage
TRIP
CS
Application of power to the X5328/X5329 activates a
Power-on Reset Circuit. This circuit goes active at
about 1V and pulls the RESET/RESET pin active. This
signal prevents the system microprocessor from start-
ing to operate with insufficient voltage or prior to stabi-
VP
SCK
VP
lization of the oscillator. When V exceeds the device
CC
SI
V
value for 200ms (nominal) the circuit releases
TRIP
RESET/RESET, allowing the processor to begin exe-
cuting code.
Resetting the V
Voltage
TRIP
Low Voltage Monitoring
This procedure sets the V
to a “native” voltage
TRIP
level. For example, if the current V
is 4.4V and the
During operation, the X5328/X5329 monitors the V
TRIP
CC
V
is reset, the new V
is something less than
level and asserts RESET/RESET if supply voltage
TRIP
TRIP
1.7V. This procedure must be used to set the voltage
to a lower value.
falls below
a
preset minimum
V
.
The
TRIP
RESET/RESET signal prevents the microprocessor
from operating in a power fail or brownout condition.
The RESET/RESET signal remains active until the
voltage drops below 1V. It also remains active until
To reset the V
voltage, apply a voltage between
TRIP
2.7 and 5.5V to the V
pin. Tie the CS pin, the WP
CC
pin, and the SCK pin HIGH. RESET/RESET and SO
pins are left unconnected. Then apply the program-
V
returns and exceeds V
for 200ms.
CC
TRIP
ming voltage V to the SI pin ONLY and pulse CS
P
V
Threshold Reset Procedure
CC
LOW then HIGH. Remove V and the sequence is
P
The X5328/X5329 has a standard V
(V
threshold
CC
complete.
) voltage. This value will not change over normal
TRIP
operating and storage conditions. However, in applica-
tions where the standard V is not exactly right, or
Figure 2. Reset V
Voltage
TRIP
TRIP
for higher precision in the
V
value, the
TRIP
X5328/X5329 threshold may be adjusted.
CS
Setting the V Voltage
TRIP
VCC
This procedure sets the V
to a higher voltage
SCK
TRIP
value. For example, if the current V
is 4.4V and
TRIP
the new V
is 4.6V, this procedure directly makes
VP
TRIP
the change. If the new setting is lower than the current
setting, then it is necessary to reset the trip point
before setting the new value.
SI
To set the new V
voltage, apply the desired V
TRIP
TRIP
threshold to the V pin and tie the CS pin and the WP
CC
pin HIGH. RESET/RESET and SO pins are left uncon-
nected. Then apply the programming voltage V to
P
both SCK and SI and pulse CS LOW then HIGH.
Remove V and the sequence is complete.
P
FN8132.1
5
October 17, 2005
X5328, X5329
Figure 3. V
Programming Sequence Flow Chart
TRIP
VTRIP Programming
Execute
Reset VTRIP
Sequence
Set VCC = VCC Applied =
Desired VTRIP
Execute
Set VTRIP
Sequence
New VCC Applied =
Old VCC Applied + Error
New VCC Applied =
Old VCC Applied - Error
Execute
Reset VTRIP
Sequence
Apply 5V to VCC
Decrement VCC
(VCC = VCC - 10mV)
NO
RESET pin
goes active?
YES
Error ≥ Emax
Error > Emax
Measured VTRIP
Desired VTRIP
-
Error < Emax
DONE
Emax = Maximum Desired Error
Figure 4. Sample V
Reset Circuit
TRIP
VP
4.7K
NC
NC
4.7K
RESET
1
2
3
4
8
7
6
5
NC
X5328/29
VTRIP
Adj.
+
Program
Reset VTRIP
Test VTRIP
Set VTRIP
10K
10K
FN8132.1
6
October 17, 2005
X5328, X5329
SPI SERIAL MEMORY
Write Enable Latch
The device contains a Write Enable Latch. This latch
must be SET before a Write Operation is initiated. The
WREN instruction will set the latch and the WRDI
instruction will reset the latch (Figure 3). This latch is
automatically reset upon a power-up condition and
after the completion of a valid Write Cycle.
The memory portion of the device is a CMOS Serial
EEPROM array with Intersil’s block lock protection. The
array is internally organized as x 8. The device features a
Serial Peripheral Interface (SPI) and software protocol
allowing operation on a simple four-wire bus.
™
The device utilizes Intersil’s proprietary Direct Write
cell, providing a minimum endurance of 100,000
cycles and a minimum data retention of 100 years.
Status Register
The RDSR instruction provides access to the Status
Register. The Status Register may be read at any
time, even during a Write Cycle. The Status Register
is formatted as follows:
The device is designed to interface directly with the
synchronous Serial Peripheral Interface (SPI) of many
popular microcontroller families. It contains an 8-bit
instruction register that is accessed via the SI input,
with data being clocked in on the rising edge of SCK.
CS must be LOW during the entire operation.
7
6
5
4
3
2
1
0
WPEN FLB
1*
1* BL1 BL0 WEL WIP
*Bits (5,4) should be written as ‘1’ only.
All instructions (Table 1), addresses and data are
transferred MSB first. Data input on the SI line is
latched on the first rising edge of SCK after CS goes
LOW. Data is output on the SO line by the falling edge
of SCK. SCK is static, allowing the user to stop the
clock and then start it again to resume operations
where left off.
The Write-In-Progress (WIP) bit is a volatile, read only
bit and indicates whether the device is busy with an
internal nonvolatile write operation. The WIP bit is read
using the RDSR instruction. When set to a “1”, a non-
volatile write operation is in progress. When set to a
“0”, no write is in progress.
Table 1. Instruction Set
Instruction Name Instruction Format*
Operation
WREN
SFLB
0000 0110
0000 0000
0000 0100
0000 0101
0000 0001
0000 0011
0000 0010
Set the Write Enable Latch (Enable Write Operations)
Set Flag Bit
WRDI/RFLB
RSDR
Reset the Write Enable Latch/Reset Flag Bit
Read Status Register
WRSR
Write Status Register (Block Lock, WPEN & Flag Bits)
Read Data from Memory Array Beginning at Selected Address
Write Data to Memory Array Beginning at Selected Address
READ
WRITE
Note: *Instructions are shown MSB in leftmost position. Instructions are transferred MSB first.
Table 2. Block Protect Matrix
WREN CMD Status Register Device Pin
Block
Block
Status Register
WPEN, BL0, BL1,
WD0, WD1
WEL
WPEN
WP#
Protected Block
Protected
Unprotected Block
Protected
0
1
1
1
X
1
0
X
X
0
X
1
Protected
Protected
Writable
Writable
Protected
Writable
Protected
Writable
Protected
Writable
FN8132.1
October 17, 2005
7
X5328, X5329
The Write Enable Latch (WEL) bit indicates the Status
function (Table 2). WP is LOW and WPEN bit pro-
grammed HIGH disables all Status Register Write
Operations.
of the Write Enable Latch. When WEL = 1, the latch is
set HIGH and when WEL = 0 the latch is reset LOW.
The WEL bit is a volatile, read only bit. It can be set by
the WREN instruction and can be reset by the WRDS
instruction.
In Circuit Programmable ROM Mode
This mechanism protects the block lock and Watchdog
bits from inadvertent corruption.
The block lock bits, BL0 and BL1, set the level of block
lock protection. These nonvolatile bits are pro-
grammed using the WRSR instruction and allow the
user to protect one quarter, one half, all or none of the
EEPROM array. Any portion of the array that is block
lock protected can be read but not written. It will
remain protected until the BL bits are altered to disable
block lock protection of that portion of memory.
In the locked state (Programmable ROM Mode) the WP
pin is LOW and the nonvolatile bit WPEN is “1”. This
mode disables nonvolatile writes to the device’s Status
Register.
Setting the WP pin LOW while WPEN is a “1” while an
internal write cycle to the Status Register is in progress
will not stop this write operation, but the operation dis-
ables subsequent write attempts to the Status Register.
Status Register Bits Array Addresses Protected
When WP is HIGH, all functions, including nonvolatile
writes to the Status Register operate normally.
BL1
BL0
X5328/X5329
None
0
0
1
1
0
1
0
1
Setting the WPEN bit in the Status Register to “0”
blocks the WP pin function, allowing writes to the Status
Register when WP is HIGH or LOW. Setting the WPEN
bit to “1” while the WP pin is LOW activates the Pro-
grammable ROM mode, thus requiring a change in the
WP pin prior to subsequent Status Register changes.
This allows manufacturing to install the device in a sys-
tem with WP pin grounded and still be able to program
the Status Register. Manufacturing can then load Con-
figuration data, manufacturing time and other parame-
ters into the EEPROM, then set the portion of memory
to be protected by setting the block lock bits, and finally
set the “OTP mode” by setting the WPEN bit. Data
changes now require a hardware change.
$0C00-$0FFF
$0800-$0FFF
$0000-$0FFF
The FLAG bit shows the status of a volatile latch that
can be set and reset by the system using the SFLB and
RFLB instructions. The Flag bit is automatically reset
upon power-up.
The nonvolatile WPEN bit is programmed using the
WRSR instruction. This bit works in conjunction with the
WP pin to provide an In-Circuit Programmable ROM
Figure 5. Read EEPROM Array Sequence
CS
0
1
2
3
4
5
6
7
8
9
10
20 21 22 23 24 25 26 27 28 29 30
SCK
SI
Instruction
16 Bit Address
15 14 13
3
2
1
0
Data Out
High Impedance
7
6
5
4
3
2
1
0
SO
MSB
FN8132.1
8
October 17, 2005
X5328, X5329
Read Sequence
For the Page Write Operation (byte or page write) to
be completed, CS can only be brought HIGH after bit 0
of the last data byte to be written is clocked in. If it is
brought HIGH at any other time, the write operation
will not be completed (Figure 4).
When reading from the EEPROM memory array, CS is
first pulled low to select the device. The 8-bit READ
instruction is transmitted to the device, followed by the
16-bit address. After the READ opcode and address
are sent, the data stored in the memory at the selected
address is shifted out on the SO line. The data stored
in memory at the next address can be read sequen-
tially by continuing to provide clock pulses. The
address is automatically incremented to the next
higher address after each byte of data is shifted out.
When the highest address is reached, the address
counter rolls over to address $0000 allowing the read
cycle to be continued indefinitely. The read operation
is terminated by taking CS high. Refer to the Read
EEPROM Array Sequence (Figure 1).
To write to the Status Register, the WRSR instruction
is followed by the data to be written (Figure 5). Data
bits 0 and 1 must be “0”.
While the write is in progress following a Status Regis-
ter or EEPROM Sequence, the Status Register may
be read to check the WIP bit. During this time the WIP
bit will be high.
OPERATIONAL NOTES
The device powers-up in the following state:
– The device is in the low power standby state.
To read the Status Register, the CS line is first pulled
low to select the device followed by the 8-bit RDSR
instruction. After the RDSR opcode is sent, the contents
of the Status Register are shifted out on the SO line.
Refer to the Read Status Register Sequence (Figure 2).
– A HIGH to LOW transition on CS is required to enter
an active state and receive an instruction.
– SO pin is high impedance.
– The Write Enable Latch is reset.
– The Flag Bit is reset.
Write Sequence
Prior to any attempt to write data into the device, the
“Write Enable” Latch (WEL) must first be set by issu-
ing the WREN instruction (Figure 3). CS is first taken
LOW, then the WREN instruction is clocked into the
device. After all eight bits of the instruction are trans-
mitted, CS must then be taken HIGH. If the user con-
tinues the Write Operation without taking CS HIGH
after issuing the WREN instruction, the Write Opera-
tion will be ignored.
– Reset Signal is active for t
.
PURST
Data Protection
The following circuitry has been included to prevent
inadvertent writes:
– A WREN instruction must be issued to set the Write
Enable Latch.
– CS must come HIGH at the proper clock count in
order to start a nonvolatile write cycle.
To write data to the EEPROM memory array, the user
then issues the WRITE instruction followed by the
16-bit address and then the data to be written. Any
unused address bits are specified to be “0’s”. The
WRITE operation minimally takes 32 clocks. CS must
go low and remain low for the duration of the opera-
tion. If the address counter reaches the end of a page
and the clock continues, the counter will roll back to
the first address of the page and overwrite any data
that may have been previously written.
FN8132.1
9
October 17, 2005
X5328, X5329
Figure 6. Read Status Register Sequence
CS
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14
SCK
Instruction
SI
Data Out
High Impedance
SO
7
6
5
4
3
2
1
0
MSB
Figure 7. Write Enable Latch Sequence
CS
0
1
2
3
4
5
6
7
SCK
SI
High Impedance
SO
Figure 8. Write Sequence
CS
0
1
2
3
4
5
6
7
8
9
10
20 21 22 23 24 25 26 27 28 29 30 31
SCK
Instruction
16 Bit Address
15 14 13
Data Byte 1
3
2
1
0
7
6
5
4
3
2
1
0
SI
CS
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
SCK
SI
Data Byte 2
Data Byte 3
Data Byte N
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
6
5
4
3
2
1
0
FN8132.1
10
October 17, 2005
X5328, X5329
Figure 9. Status Register Write Sequence
CS
0
1
2
3
4
5
6
7
8
7
9
6
10 11 12 13 14 15
SCK
Instruction
Data Byte
5
4
3
2
1
0
SI
High Impedance
SO
SYMBOL TABLE
WAVEFORM
INPUTS
OUTPUTS
Must be
steady
Will be
steady
May change
from LOW
to HIGH
Will change
from LOW
to HIGH
May change
from HIGH
to LOW
Will change
from HIGH
to LOW
Don’t Care:
Changes
Allowed
Changing:
State Not
Known
N/A
Center Line
is High
Impedance
FN8132.1
11
October 17, 2005
X5328, X5329
ABSOLUTE MAXIMUM RATINGS
COMMENT
Temperature under bias.................... -65°C to+135°C
Storage temperature ........................ -65°C to+150°C
Voltage on any pin with
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only; functional operation of the
device (at these or any other conditions above those
listed in the operational sections of this specification) is
not implied. Exposure to absolute maximum rating con-
ditions for extended periods may affect device reliability.
respect to V ...................................... -1.0V to +7V
SS
D.C. output current...............................................5mA
Lead temperature (soldering, 10s) .................... 300°C
RECOMMENDED OPERATING CONDITIONS
Temperature
Commercial
Industrial
Min.
0°C
Max.
70°C
Voltage Option
-2.7 or -2.7A
Supply Voltage
2.7V to 5.5V
4.5V-5.5V
-40°C
+85°C
BLank or -4.5A
D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.)
Limits
Symbol
Parameter
Min.
Typ.
Max.
Unit
Test Conditions
ICC1
VCC Write Current (Active)
5
mA SCK = VCC x 0.1/VCC x 0.9 @ 2MHz,
SO = Open
ICC2
ISB
VCC Read Current (Active)
VCC Standby Current
0.4
1
mA SCK = VCC x 0.1/VCC x 0.9 @ 2MHz,
SO = Open
µA
CS = VCC, VIN = VSS or VCC
VCC = 5.5V
,
ILI
Input Leakage Current
Output Leakage Current
Input LOW Voltage
0.1
0.1
10
10
µA
µA
V
VIN = VSS to VCC
ILO
VOUT = VSS to VCC
(1)
VIL
-0.5
VCC x 0.3
VCC + 0.5
0.4
(1)
VIH
Input HIGH Voltage
VCC x 0.7
V
VOL1
VOL2
VOL3
VOH1
VOH2
VOH3
VOLS
Output LOW Voltage
Output LOW Voltage
Output LOW Voltage
Output HIGH Voltage
Output HIGH Voltage
Output HIGH Voltage
Reset Output LOW Voltage
V
VCC > 3.3V, IOL = 2.1mA
0.4
V
2V < VCC ≤ 3.3V, IOL = 1mA
VCC ≤ 2V, IOL = 0.5mA
0.4
V
VCC - 0.8
VCC - 0.4
VCC - 0.2
V
VCC > 3.3V, IOH = -1.0mA
2V < VCC ≤ 3.3V, IOH = -0.4mA
VCC ≤ 2V, IOH = -0.25mA
V
V
0.4
V
IOL = 1mA
CAPACITANCE T = +25°C, f = 1MHz, V = 5V
A
CC
Symbol
Test
Max.
Unit
Conditions
VOUT = 0V
VIN = 0V
(2)
COUT
Output Capacitance (SO, RESET, RESET)
Input Capacitance (SCK, SI, CS, WP)
8
6
pF
pF
(2)
CIN
Notes: (1) VIL min. and VIH max. are for reference only and are not tested.
(2) This parameter is periodically sampled and not 100% tested.
FN8132.1
October 17, 2005
12
X5328, X5329
EQUIVALENT A.C. LOAD CIRCUIT AT 5V V
A.C. TEST CONDITIONS
CC
Input pulse levels
VCC x 0.1 to VCC x 0.9
10ns
5V
5V
Input rise and fall times
Input and output timing level
V
CC x0.5
4.6kΩ
2.06kΩ
Output
3.03kΩ
RESET/RESET
30pF
100pF
A.C. CHARACTERISTICS (Over recommended operating conditions, unless otherwise specified)
Serial Input Timing
2.7-5.5V
Symbol
fSCK
tCYC
tLEAD
tLAG
tWH
Parameter
Min.
0
Max.
Unit
MHz
ns
Clock Frequency
Cycle Time
2
500
250
250
200
250
50
CS Lead Time
CS Lag Time
ns
ns
Clock HIGH Time
Clock LOW Time
Data Setup Time
Data Hold Time
Input Rise Time
Input Fall Time
CS Deselect Time
Write Cycle Time
ns
tWL
ns
tSU
ns
tH
50
ns
(3)
tRI
100
100
ns
(3)
tFI
ns
tCS
500
ns
(4)
tWC
10
ms
FN8132.1
October 17, 2005
13
X5328, X5329
Serial Input Timing
tCS
CS
tLEAD
tLAG
SCK
tSU
tH
tRI
tFI
SI
MSB IN
LSB IN
High Impedance
SO
Serial Output Timing
Symbol
2.7-5.5V
Max.
Parameter
Min.
Unit
MHz
ns
fSCK
tDIS
tV
Clock Frequency
Output Disable Time
0
2
250
250
Output Valid from Clock Low
Output Hold Time
ns
tHO
0
ns
(3)
tRO
Output Rise Time
100
100
ns
(3)
tFO
Output Fall Time
ns
Notes: (3) This parameter is periodically sampled and not 100% tested.
(4) tWC is the time from the rising edge of CS after a valid write sequence has been sent to the end of the self-timed internal nonvolatile
write cycle.
Serial Output Timing
CS
SCK
SO
tCYC
tWH
tLAG
tV
tHO
tWL
tDIS
MSB Out
MSB–1 Out
LSB Out
ADDR
LSB IN
SI
FN8132.1
14
October 17, 2005
X5328, X5329
Power-Up and Power-Down Timing
VTRIP
VTRIP
VCC
tPURST
0 Volts
tF
tRPD
tPURST
tR
RESET (X5328)
RESET (X5329)
RESET Output Timing
Symbol
Parameter
Min.
Typ.
Max.
Unit
VTRIP
Reset Trip Point Voltage, X5328-4.5A, X5328-4.5A
Reset Trip Point Voltage, X5328, X5329
Reset Trip Point Voltage, X5328-2.7A, X5329-2.7A
Reset Trip Point Voltage, X5328-2.7, X5329-2.7
4.5
4.63
4.38
2.93
2.63
4.75
4.5
3.0
4.25
2.85
2.55
V
2.7
VTH
VTRIP Hysteresis (HIGH to LOW vs. LOW to HIGH VTRIP voltage)
Power-up Reset Time Out
VCC Detect to Reset/Output
VCC Fall Time
20
mV
ms
ns
µs
µs
V
tPURST
100
200
280
500
(5)
tRPD
(5)
tF
100
100
1
(5)
tR
VCC Rise Time
VRVALID
Reset Valid VCC
Note: (5) This parameter is periodically sampled and not 100% tested.
FN8132.1
15
October 17, 2005
X5328, X5329
V
Set Conditions
TRIP
tTHD
VCC
VTRIP
tTSU
tRP
tP
tVPH
tVPS
CS
tVPO
tVPH
tVPS
VP
SCK
SI
VP
tVPO
V
Reset Conditions
TRIP
VCC
*
tRP
tP
tVP1
tVPS
CS
tVPS
tVPO
tVPH
VCC
SCK
SI
VP
tVPO
*VCC > Programmed VTRIP
FN8132.1
16
October 17, 2005
X5328, X5329
V
Programming Specifications V = 1.7-5.5V; Temperature = 0°C to 70°C
CC
TRIP
Parameter
tVPS
tVPH
tP
Description
SCK VTRIP Program Voltage Setup time
Min. Max. Unit
1
1
µs
µs
µs
µs
ms
ms
ms
ms
V
SCK VTRIP Program Voltage Hold time
VTRIP Program Pulse Width
1
tTSU
tTHD
tWC
VTRIP Level Setup time
10
10
VTRIP Level Hold (stable) time
VTRIP Write Cycle Time
10
tRP
VTRIP Program Cycle Recovery Period (Between successive programming cycles)
SCK VTRIP Program Voltage Off time before next cycle
Programming Voltage
10
0
tVPO
VP
VTRAN
Vta1
15
1.7
18
VTRIP Programed Voltage Range
5.0
V
Initial VTRIP Program Voltage accuracy (VCC applied-VTRIP) (Programmed at 25°C.)
-0.1 +0.4
V
Vta2
Subsequent VTRIP Program Voltage accuracy [(VCC applied-Vta1)-VTRIP
(Programmed at 25°C.)
]
-25
-25
-25
+25
+25
+25
mV
Vtr
VTRIP Program Voltage repeatability (Successive program operations.) (programmed at
25°C)
mV
mV
Vtv
VTRIP Program variation after programming (0-75°C). (programmed at 25°C)
VTRIP programming parameters are periodically sampled and are not 100% tested.
FN8132.1
17
October 17, 2005
X5328, X5329
TYPICAL PERFORMANCE
Supply Current vs. Temperature (I
t
vs. Temperature
V
)
SB
PURST
CC
205
200
195
190
185
180
175
170
165
2
(VCC = 3V, 5V)
1
0
160
-40
25
Degrees °C
90
-40C
25C
Temp°C
90C
V
vs. Temperature (programmed at 25°C)
TRIP
5.025
V
V
TRIP = 5V
5.000
4.975
3.525
3.500
TRIP = 3.5V
3.475
2.525
2.500
2.475
VTRIP = 2.5V
0
25
85
Temperature
FN8132.1
October 17, 2005
18
X5328, X5329
PACKAGING INFORMATION
8-Lead Plastic Dual In-Line Package Type P
0.430 (10.92)
0.360 (9.14)
0.260 (6.60)
0.240 (6.10)
Pin 1 Index
Pin 1
0.060 (1.52)
0.020 (0.51)
0.300
(7.62) Ref.
Half Shoulder Width On
All End Pins Optional
0.145 (3.68)
0.128 (3.25)
Seating
Plane
0.025 (0.64)
0.015 (0.38)
0.065 (1.65)
0.150 (3.81)
0.125 (3.18)
0.045 (1.14)
0.110 (2.79)
0.090 (2.29)
0.020 (0.51)
0.016 (0.41)
0.325 (8.25)
0.300 (7.62)
.073 (1.84)
Max.
0°
Typ. 0.010 (0.25)
15°
NOTE:
1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
2. PACKAGE DIMENSIONS EXCLUDE MOLDING FLASH
FN8132.1
19
October 17, 2005
X5328, X5329
PACKAGING INFORMATION
8-Lead Plastic Small Outline Gull Wing Package Type S
0.150 (3.80) 0.228 (5.80)
0.158 (4.00) 0.244 (6.20)
Pin 1 Index
Pin 1
0.014 (0.35)
0.019 (0.49)
0.188 (4.78)
0.197 (5.00)
(4X) 7°
0.053 (1.35)
0.069 (1.75)
0.004 (0.19)
0.050 (1.27)
0.010 (0.25)
0.010 (0.25)
0.020 (0.50)
0.050" Typical
X 45°
0.050"
Typical
0° - 8°
0.0075 (0.19)
0.010 (0.25)
0.250"
0.016 (0.410)
0.037 (0.937)
0.030"
Typical
8 Places
FOOTPRINT
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
FN8132.1
20
October 17, 2005
X5328, X5329
PACKAGING INFORMATION
14-Lead Plastic Small Outline Gullwing Package Type S
0.150 (3.80) 0.228 (5.80)
0.158 (4.00) 0.244 (6.20)
Pin 1 Index
Pin 1
0.014 (0.35)
0.020 (0.51)
0.336 (8.55)
0.345 (8.75)
(4X) 7°
0.053 (1.35)
0.069 (1.75)
0.004 (0.10)
0.010 (0.25)
0.050 (1.27)
0.050"Typical
0.010 (0.25)
X 45°
0.020 (0.50)
0.050"Typical
0° - 8°
0.250"
0.0075 (0.19)
0.010 (0.25)
0.016 (0.410)
0.037 (0.937)
0.030"Typical
14 Places
FOOTPRINT
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN8132.1
21
October 17, 2005
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