X55621V20-4.5A [RENESAS]
IC,SERIAL EEPROM,32KX8,CMOS,TSSOP,20PIN,PLASTIC;
| 型号： | X55621V20-4.5A |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | IC,SERIAL EEPROM,32KX8,CMOS,TSSOP,20PIN,PLASTIC 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 光电二极管 内存集成电路 |
| 文件： | 总22页 (文件大小：129K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Preliminary Information
64K
X55061
Dual Voltage Monitor with Integrated System Battery Switch and EEPROM
FEATURES
DESCRIPTION
• Dual voltage monitoring
• System battery switch-over circuitry
This device combines power-on reset control, battery
switch circuit, watchdog timer, supply voltage supervi-
sion, secondary voltage supervision, block lock protect
and serial EEPROM in one package. This combination
lowers system cost, reduces board space require-
ments, and increases reliability.
• Early warning low V
fail indicator
CC
• Separate watchdog timer outputs
• Selectable watchdog timer
—(0.15s, 0.4s, 0.8s, off)
• Low V
reset assertion
—Four standard reset threshold voltages
—Re-program V1
(V1MON) and V2MON detection and
CC
Applying power to the device activates the power on
reset circuit which holds RESET active for a period of
time. This allows the power supply and oscillator to sta-
bilize before the processor can execute code.
and V2
reset threshold
TRIP
TRIP
voltage using special programming sequence
—Reset signal valid to V = 1V
A system battery switch circuit compares V
CC
CC
• Long battery life with low power consumption
—<50µA max standby current, watchdog on
—<30µA max standby current, watchdog off
—<1.5mA max active current during read
• 64Kbits of EEPROM
(V1MON) with V
whichever is higher. This provides voltage to external
SRAM or other circuits in the event of main power fail-
input and connect V
to
BATT
OUT
ure. The X55061 can drive 50mA from V
and 250µA
CC
from V
. The device switches to V
when V
BATT
BATT CC
• Built-in inadvertent write protection
—Power-up/power-down protection circuitry
—Protect 0, 1/4, 1/2 or all of EEPROM array with
programmable Block Lock™ protection
—In circuit programmable ROM mode
• 10MHz SPI interface modes (0,0 & 1,1)
• Minimize EEPROM programming time
—64 byte page write mode
drops below the low V voltage threshold and V
.
CC
BATT
The Watchdog Timer provides an independent protec-
tion mechanism for microcontrollers. When the micro-
controller fails to restart a timer within a selectable
time out interval, the device activates the WDO signal.
The user selects the interval from three preset values.
Once selected, the interval does not change, even
after cycling the power.
—Self-timed write cycle
—5ms write cycle time (typical)
• 2.7V to 5.5V power supply operation
• Available packages
The device’s low V
detection circuitry protects the
CC
user’s system from low voltage conditions, resetting the
system when V (V1MON) falls below the minimum
CC
—20-lead TSSOP
V
trip point (V
). RESET is asserted until V
CC
TRIP CC
returns to proper operating level and stabilizes. A sec-
ond voltage monitor circuit tracks the unregulated sup-
ply or monitors a second power supply voltage to
provide a power fail warning. Xicor’s unique circuits
allow the threshold for either voltage monitor to be
reprogrammed to meet special needs or to fine-tune the
threshold for applications requiring higher precision.
Characteristics subject to change without notice. 1 of 22
REV 1.1 3/5/01
www.xicor.com
X55061 – Preliminary Information
BLOCK DIAGRAM
V2FAIL
+
V2MON
V2
TRIP
V2 Monitor
Logic
-
Watchdog Transition
Detector
Watchdog
Timer Reset
WP
Protect Logic
WDO
Data
Register
SO
SI
Status
Register
Command
Decode, Test
& Control
Logic
Reset &
Watchdog
Timebase
EEPROM
Array
SCK
CS
512 X 512
RESET
\ MR
BATT-ON
System
Battery
Switch
V
OUT
Power On,
Manual and
Low Voltage
Reset
V
BATT
V
+
CC
V1
(V1MON)
TRIP
V
Monitor
-
CC
Generation
Logic
LOWLINE
PIN CONFIGURATION
20-Pin TSSOP
V
(V1MON)
1
20
CS/WDI
NC
CC
NC
2
3
19
18
SO
RESET/MR
BATT-ON
WDO
4
5
17
16
V
LOWLINE
V2FAIL
V2MON
WP
OUT
V
6
7
15
14
BATT
SCK
NC
NC
SI
8
9
13
12
NC
V
10
11
SS
Characteristics subject to change without notice. 2 of 22
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X55061 – Preliminary Information
PIN DESCRIPTION
Pin
Name
Function
1
CS/WDI
Chip Select Input. CS HIGH, deselects the device and the SO output pin is at a high impedance
state. Unless a nonvolatile write cycle is underway, the device will be in the standby power mode.
CS LOW enables the device, placing it in the active power mode. Prior to the start of any operation
after power up, a HIGH to LOW transition on CS is required.
Watchdog Input. A HIGH to LOW transition on the WDI pin restarts the Watchdog timer. The ab-
sence of a HIGH to LOW transition within the watchdog time out period results in RESET going active.
2
3
NC
SO
No internal connections
Serial Output. SO is a push/pull serial data output pin. A read cycle shifts data out on this pin.The
falling edge of the serial clock (SCK) clocks the data out.
4
5
6
WDO
Watchdog Output. WDO is an active Low, open drain output which goes active whenever the watch-
dog timer goes active.
LOWLINE Early Warning Low V Detect. This CMOS output signal goes LOW 800nsec before V
<
CC
CC
V
and returns HIGH when V > V
.
TRIP
CC
TRIP
V2FAIL
V2MON
V2 Voltage Fail Output. This open drain output goes LOW when V2MON is less than V2
and
TRIP
goes HIGH when V2MON exceeds V2
. There is no power up reset delay circuitry on this pin.
TRIP
This circuit works independently from the Low V reset and battery switch circuits.
CC
7
8
V2 Voltage Monitor Input. When the V2MON input is less than the V2
voltage, V2FAIL goes
TRIP
LOW. This input can monitor an unregulated power supply with an external resistor divider or can
monitor a second power supply with no external components. Connect V2MON to V or V
when not used.
SS
CC
WP
Write Protect. The WP pin works in conjunction with a nonvolatile WPEN bit to “lock” the setting
of the Watchdog Timer control and the memory write protect bits. This pin is also used as the test
mode enable pin where the high voltage will be applied. Thus the layout for the input is different to
allow for higher punch thru.
9
NC
No internal connections
Ground
10
11
V
SS
SI
Serial Input. SI is a serial data input pin. Input all opcodes, byte addresses, and memory data on this
pin.The rising edge of the serial clock (SCK) latches the input data. Send all opcodes (Table 1), ad-
dresses and data MSB first.
12
13
14
NC
NC
No internal connections
No internal connections
SCK
Serial Clock. The Serial Clock controls the serial bus timing for data input and output.The rising edge
of SCK latches in the opcode, address, or data bits present on the SI pin.The falling edge of SCK
changes the data output on the SO pin.
15
16
V
Battery Supply Voltage. This input provides a backup supply in the event of a failure of the pri-
BATT
mary V voltage. The V
voltage typically provides the supply voltage necessary to maintain
CC
BATT
the contents of SRAM and also powers the internal logic to “stay awake.”
V
Open Drain Output Voltage. V = V if V > V . IF V < V
, then V
= V if
OUT
OUT
CC
CC
VTRIP
CC
VTRIP
OUT CC
V
> V
+ 0.05, or V
= V
if V < V
- 0.05.
CC
BATT
OUT
BATT
CC
BATT
Note: There is hysteresis around V
0.05V point to avoid oscillation at or near the switchover
voltage. A capacitance of 0.1µF must be connected to Vout to ensure stability.
BATT
Characteristics subject to change without notice. 3 of 22
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X55061 – Preliminary Information
PIN DESCRIPTION (CONTINUED)
Pin
Name
Function
17
BATT-ON Battery On. This CMOS output goes HIGH when the V
switches to V
and goes LOW
OUT
BATT
when V
switches to V . It is used to drive an external PNP pass transistor when V = V
OUT
CC CC OUT
and current requirements are greater than 50mA.
The purpose of this output is to drive an external transistor to get higher operating currents when
the V supply is fully functional. In the event of a V failure, the battery voltage is applied to the
CC
OUT
CC
V
pin and the external transistor is turned off. In this “backup condition,” the battery only needs
to supply enough voltage and current to keep SRAM devices from losing their data-there is no
communication at this time.
18
RESET
/MR
RESET Output. This is an active LOW, open drain output which goes active whenever V falls be-
CC
low the minimum V sense level. Then communication to the device is interrupted. It will remainactive
CC
until V rises above the minimum V sense level for 150ms. RESET also goes active on power
CC
CC
up and remains active for 150ms after the power supply stabilizes.
19
20
NC
No internal connections
V
Supply Voltage
CC
(V1MON) V1 Voltage Monitor Input. When the V1MON input is less than the V1
voltage, RESET and
TRIP
RESET goes ACTIVE.
PRINCIPLES OF OPERATION
Power On Reset
Low V2MON Voltage Monitoring
The X55061 also monitors a second voltage level and
asserts V2FAIL if the voltage falls below a preset mini-
Application of power to the X55061 activates a Power
On Reset Circuit. This circuit goes active at about 1V
and pulls the RESET pin active. This signal prevents the
system microprocessor from starting to operate with
insufficient voltage or prior to stabilization of the oscilla-
mum V2
. The V2FAIL signal is either ORed with
TRIP
RESET to prevent the microprocessor from operating
in a power fail or brownout condition or used to inter-
rupt the microprocessor with notification of an impend-
ing power failure. The V2FAIL signal remains active
until the V2MON drops below 1V (V2MON falling). It
also remains active until V2MON returns and exceeds
tor. When Vcc exceeds the device V1
value for
TRIP
150ms (nominal) the circuit releases RESET, allowing
the processor to begin executing code.
V2
by 0.03V.
TRIP
The V2MON voltage sensor is completely separate
from the operation of the low V sense, and is inde-
Low V
(V1MON) Voltage Monitoring
CC
CC
During operation, the X55061 monitors the V
and asserts RESET if supply voltage falls below a pre-
set minimum V1 . During this time the communica-
level
CC
pendent of V supply.
CC
TRIP
tion to the device is interrupted. The RESET signal also
prevents the microprocessor from operating in a power
fail or brownout condition. The RESET signal remains
active until the voltage drops below 1V. These also
remain active until V
150ms.
returns and exceeds V1
for
CC
TRIP
Characteristics subject to change without notice. 4 of 22
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X55061 – Preliminary Information
Figure 1. Two Uses of Dual Voltage Monitoring
V
OUT
V
V2MON
OUT
X55061
X55061
Unregulated
Supply
Unregulated
Supply
5V
Reg
5V
V
CC
V
System
CC
Reg
RESET
RESET
Reset
R
R
V2MON
System
Interrupt
System
Reset
V2FAIL
V2MON
V2FAIL
5V
Reg
Resistors selected so 3V appears on V2MON when
Unregulated supply reaches 6V.
Notice: No external components required to monitor
two voltages.
Watchdog Timer
V
(V1MON), V2MON Threshold Reset Procedure
CC
The Watchdog Timer circuit monitors the microproces-
sor activity by monitoring the CS pin. The microproces-
sor must toggle the CS pin HIGH to LOW periodically
prior to the expiration of the watchdog time out period
to prevent the WDO signal going active. The state of
two nonvolatile control bits in the Status Register
determines the watchdog timer period. The micropro-
cessor can change these watchdog bits by writing to
the status register.
The X55061 is shipped with standard V
(V1MON)
CC
and V2MON threshold (V1
, V2
) voltages.These
TRIP
TRIP
values will not change over normal operating and stor-
age conditions. However, in applications where the stan-
dard thresholds are not exactly right, or if higher
precision is needed in the threshold value, the X55061
trip points may be adjusted. The procedure is described
below, and uses the application of a high voltage control
signal.
The Watchdog Timer oscillator stops when in battery
Setting the V
Voltage
TRIP
backup mode. It re-starts when V returns.
CC
This procedure is used to set the V1
or V2
to a
TRIP
TRIP
lower or higher voltage value. It is necessary to reset
the trip point before setting the new value.
System Battery Switch
As long as V
exceeds the low voltage detect thresh-
CC
old V1
, V
is connected to V through a 5 Ohm
To set the new voltage, apply the desired V
thresh-
TRIP OUT
CC
TRIP
(typical) switch. When the V
has fallen below V
,
old voltage to the V
pin or the V2
voltage to the
CC
TRIP
CC
TRIP
then V
is applied to V
if V
is or equal to or
V2MON pin (during V2MON V2
setting only, V
CC
OUT
CC
TRIP CC
greater than V
- 0.03V. When V
drops to less
should be same as V2MON), then tie the WP pin to the
BATT
CC
than V
- 0.03V, then V
is connected to V
programming voltage V . Then, send the WREN com-
BATT
OUT
BATT
P
through an 80 Ohm (typical) switch. V
typically
mand and write to address 01h or to address 0Bh to
OUT
supplies the system static RAM voltage, so the
switchover circuit operates to protect the contents of
the static RAM during a power failure. Typically, when
program V
or V2
, respectively (followed by
TRIP
TRIP
data byte 00h). The CS going high after a valid write
operation initiates the programming sequence. Bring
WP LOW to complete the operation. Note: this opera-
tion will not alter the contents of the EEPROM.
V
has failed, the SRAMs go into a lower power state
CC
and draw much less current than in their active mode.
When V returns, V switches back to V when
CC
OUT
CC
V
exceeds V
+0.03V. There is a 60mV hystere-
Manual Reset
CC
BATT
sis around this battery switch threshold to prevent
oscillations between supplies.
By connecting a push-button from MR to ground or
driven by logic, the designer adds manual system reset
capability. The RESET pins are asserted when the
While V
is connected to V
the BATT-ON pin is
CC
OUT
push-button is closed and remain asserted for t
PURST
pulled LOW. The signal can drive an external PNP
transistor to provide additional current to the external
circuits during normal operation.
after the push-button is released. This pin is debounced
so a push-button connected directly to the device will
have both clean falling and rising edges on MR. Also
has internal pull up thus the pin can left open if not used.
Characteristics subject to change without notice. 5 of 22
REV 1.1 3/5/01
www.xicor.com
X55061 – Preliminary Information
Figure 2. Example System Connection
Unregulated
Supply
5V
Reg
V
V
CC
BATT-ON
SRAM
V
OUT
BATT
V
V2MON
OUT
Address
Decode
V2MON
RESET
+
V2FAIL
Enable
Addr
NMI
LOWLINE
V
CC
RESET
RESET
µC
MR
SPI
CS, SCK
SI, SO
V
SS
Resetting the V
Voltage
voltage V . Then send the WREN command and write
P
TRIP
to address 03h or 0Dh to reset the V1
or V2
TRIP
TRIP
This procedure is used to set the V1
or the V
2TRIP
TRIP
respectively (followed by data byte 00h). The CS going
LOW to HIGH after a valid write operation initiates the
programming sequence. Bring WP LOW to complete
the operation.
to a “native” voltage level. For example, if the current
is 4.4V and the new V must be 4.0V, then
V
TRIP
TRIP
the V
must be reset. When the threshold is reset,
TRIP
the new level is something less than 1.7V. This proce-
dure must be used to set the voltage to a lower value.
Note: This operation does not change the contents of
the EEPROM array.
To reset the new V1
or V2
voltage, apply
TRIP
TRIP
greater than 3V to V
(V1MON) or V2MON pin,
CC
respectively, and tie the WP pin to the programming
Figure 3. Set V
Level Sequence (V
= desired V
)
TRIP
CC
TRIP
V
= 10-15V
P
WP
CS
0
1
2
3
4
5
6
7
0
1
2
3
4 5
6
7
8
9 10
20 21 22 23
SCK
SI
16 Bits
02h
WRITE
0001h/000Bh
ADDRESS
00h
DATA
06h
WREN
Addr 01h: Set V
(V1
)
TRIP
CC
Addr 0Bh: Set V2MON Trip
Characteristics subject to change without notice. 6 of 22
REV 1.1 3/5/01
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X55061 – Preliminary Information
Figure 4. Reset V
Level Sequence (V
> 3V. WP = 10-15V)
TRIP
CC
V
= 10-15V
P
WP
CS
0
1
2
3
4
5
6
7
0
1
2
3
4 5
6
7
8
9 10
20 21 22 23
SCK
SI
16 Bits
02h
WRITE
0003h/000Dh
ADDRESS
00h
DATA
06h
WREN
Addr 03h: Update V
(V1
)
TRIP
CC
Addr 0Dh: Update V2MON Trip
Figure 5. Sample V
Reset Circuit
TRIP
4.6K
X55061
V
RESET
µC
P
V
CS
SO
WP
CC
Adjust
Run
RESET
SCK
SCK
SI
V
TRIP
V
SI
Adj.
SS
SO
CS
Characteristics subject to change without notice. 7 of 22
REV 1.1 3/5/01
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X55061 – Preliminary Information
Figure 6. V
Programming Sequence Flow Chart
TRIP
V
Programming
Execute
TRIP
Reset V
Sequence
TRIP
Set V
= V
Applied =
TRIP
CC
CC
Desired V
Execute
Set V
TRIP
Sequence
Apply 5V to V
CC
Decrement V
= V
CC
(V
- 10mV)
CC
CC
NO
RESET pin
goes active?
YES
Error > Emax
Error ≥ Emax
Measured V
Desired V
-
TRIP
TRIP
Error < Emax
DONE
Execute
Reset V
New V
Applied =
Applied + Error
CC
TRIP
Old V
CC
Sequence
New V
Applied =
Applied - Error
CC
Emax = Maximum Desired Error
Old V
CC
SPI SERIAL MEMORY
The device is designed to interface directly with the
synchronous Serial Peripheral Interface (SPI) of many
popular microcontroller families. It contains an 8-bit
instruction register that is accessed via the SI input,
with data being clocked in on the rising edge of SCK.
CS must be LOW during the entire operation.
The memory portion of the device is a CMOS Serial
EEPROM array with Xicor’s block lock protection. The
array is internally organized as x 8. The device features
a Serial Peripheral Interface (SPI) and software protocol
allowing operation on a simple four-wire bus.
All instructions (Table 1), addresses and data are trans-
ferred MSB first. Data input on the SI line is latched on
the first rising edge of SCK after CS goes LOW. Data is
The device utilizes Xicor’s proprietary Direct Write™
cell, providing a minimum endurance of 1,000,000
cycles and a minimum data retention of 100 years.
Characteristics subject to change without notice. 8 of 22
REV 1.1 3/5/01
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X55061 – Preliminary Information
output on the SO line by the falling edge of SCK. SCK
is static, allowing the user to stop the clock and then
start it again to resume operations where left off.
Status Register
The RDSR instruction provides access to the Status
Register. The Status Register may be read at any time,
even during a Write Cycle. The Status Register is for-
matted as follows:
Write Enable Latch
The device contains a Write Enable Latch. This latch
must be SET before a Write Operation is initiated. The
WREN instruction will set the latch and the WRDI
instruction will reset the latch (Figure 3). This latch is
automatically reset upon a power-up condition and
after the completion of a valid Write Cycle.
7
6
5
4
3
2
1
0
WPEN WD1 WD0 BL2 BL1 BL0 WEL WIP
The Write-In-Progress (WIP) bit is a volatile, read only
bit and indicates whether the device is busy with an
internal nonvolatile write operation. The WIP bit is read
using the RDSR instruction. When set to a “1”, a non-
volatile write operation is in progress. When set to a
“0”, no write is in progress.
Table 1. Instruction Set
Instruction Name Instruction Format*
Operation
WREN
WRDI
0000 0110
0000 0100
0000 0101
0000 0001
0000 0011
0000 0010
Set the Write Enable Latch (Enable Write Operations)
Reset the Write Enable Latch
RSDR
WRSR
READ
WRITE
Read Status Register
Write Status Register (Watchdog, Block Lock, WPEN)
Read Data from Memory Array Beginning at Selected Address
Write Data to Memory Array Beginning at Selected Address
Note: *Instructions are shown MSB in leftmost position. Instructions are transferred MSB first.
Table 2. Block Protect Matrix
WREN CMD Status Register Device Pin
Block
Block
Status Register
WPEN, BL0, BL1,
BL2, WD0, WD1
WEL
WPEN
WP#
Protected Block Unprotected Block
0
1
1
1
X
1
0
X
X
0
X
1
Protected
Protected
Protected
Protected
Protected
Writable
Writable
Writable
Protected
Protected
Writable
Writable
The Write Enable Latch (WEL) bit indicates the Status
of the Write Enable Latch. When WEL=1, the latch is
set HIGH and when WEL=0 the latch is reset LOW.
The WEL bit is a volatile, read only bit. It can be set by
the WREN instruction and can be reset by the WRDS
instruction.
The block lock bits, BL0, BL1 and BL2, set the level of
block lock protection. These nonvolatile bits are pro-
grammed using the WRSR instruction and allow the
user to protect one quarter, one half, all or none of the
EEPROM array. Any portion of the array that is block
lock protected can be read but not written. It will remain
protected until the BL bits are altered to disable block
lock protection of that portion of memory.
Characteristics subject to change without notice. 9 of 22
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X55061 – Preliminary Information
The nonvolatile WPEN bit is programmed using the
WRSR instruction. This bit works in conjunction with
the WP pin to provide an In-Circuit Programmable
ROM function (Table 2). WP is LOW and WPEN bit pro-
grammed HIGH disables all Status Register Write
Operations.
Status Register Bits Array Addresses Protected
BL2
0
BL1
0
BL0
0
X55061
None
0
0
1
6000h–7FFFh
4000h–7FFFh
0000h–7FFFh
0000h–003Fh
0000h–007Fh
0000h–00FFh
0000h–01FFh
0
1
0
0
1
1
In Circuit Programmable ROM Mode
1
0
0
This mechanism protects the Block Lock and Watch-
dog bits from inadvertent corruption.
1
0
1
1
1
0
In the locked state (Programmable ROM Mode) the WP
pin is LOW and the nonvolatile bit WPEN is “1”. This
mode disables nonvolatile writes to the device’s Status
Register.
1
1
1
The Watchdog Timer bits, WD0 and WD1, select the
Watchdog Time Out Period. These nonvolatile bits are
programmed with the WRSR instruction.
Setting the WP pin LOW while WPEN is a “1” while an
internal write cycle to the Status Register is in progress
will not stop this write operation, but the operation dis-
ables subsequent write attempts to the Status Register.
Status Register Bits
Watchdog Time Out
WD1
WD0
(Typical)
800 milliseconds
400 milliseconds
150 milliseconds
disabled
0
0
1
1
0
1
0
1
Figure 7. Read EEPROM Array Sequence
CS
0
1
2
3
4
5
6
7
8
9
10
20 21 22 23 24 25 26 27 28 29 30
SCK
SI
Instruction
16 Bit Address
15 14 13
3
2
1
0
Data Out
High Impedance
7
6
5
4
3
2
1
0
SO
MSB
Characteristics subject to change without notice. 10 of 22
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X55061 – Preliminary Information
When WP is HIGH, all functions, including nonvolatile
writes to the Status Register operate normally. Setting
the WPEN bit in the Status Register to “0” blocks the
WP pin function, allowing writes to the Status Register
when WP is HIGH or LOW. Setting the WPEN bit to “1”
while the WP pin is LOW activates the Programmable
ROM mode, thus requiring a change in the WP pin
prior to subsequent Status Register changes. This
allows manufacturing to install the device in a system
with WP pin grounded and still be able to program the
Status Register. Manufacturing can then load Configu-
ration data, manufacturing time and other parameters
into the EEPROM, then set the portion of memory to
be protected by setting the block lock bits, and finally
set the “OTP mode” by setting the WPEN bit. Data
changes now require a hardware change.
To write data to the EEPROM memory array, the user
then issues the WRITE instruction followed by the 16
bit address and then the data to be written. Any
unused address bits are specified to be “0’s”. The
WRITE operation minimally takes 32 clocks. CS must
go low and remain low for the duration of the operation.
If the address counter reaches the end of a page and
the clock continues, the counter will roll back to the first
address of the page and overwrite any data that may
have been previously written.
For the Page Write Operation (byte or page write) to be
completed, CS can only be brought HIGH after bit 0 of
the last data byte to be written is clocked in. If it is
brought HIGH at any other time, the write operation will
not be completed (Figure 4).
To write to the Status Register, the WRSR instruction is
followed by the data to be written (Figure 5). Data bits
0 and 1 must be “0”.
Read Sequence
When reading from the EEPROM memory array, CS is
first pulled low to select the device. The 8-bit READ
instruction is transmitted to the device, followed by the
16-bit address. After the READ opcode and address
are sent, the data stored in the memory at the selected
address is shifted out on the SO line. The data stored
in memory at the next address can be read sequen-
tially by continuing to provide clock pulses. The
address is automatically incremented to the next
higher address after each byte of data is shifted out.
When the highest address is reached, the address
counter rolls over to address $0000 allowing the read
cycle to be continued indefinitely. The read operation is
terminated by taking CS high. Refer to the Read
EEPROM Array Sequence (Figure 1).
While the write is in progress following a Status Regis-
ter or EEPROM Sequence, the Status Register may be
read to check the WIP bit. During this time the WIP bit
will be high.
OPERATIONAL NOTES
The device powers-up in the following state:
– The device is in the low power standby state.
– A HIGH to LOW transition on CS is required to enter
an active state and receive an instruction.
– SO pin is high impedance.
– The Write Enable Latch is reset.
To read the Status Register, the CS line is first pulled
low to select the device followed by the 8-bit RDSR
instruction. After the RDSR opcode is sent, the contents
of the Status Register are shifted out on the SO line.
Refer to the Read Status Register Sequence (Figure 2).
– Reset Signal is active for t
.
PURST
Data Protection
The following circuitry has been included to prevent
inadvertent writes:
Write Sequence
– A WREN instruction must be issued to set the Write
Enable Latch.
Prior to any attempt to write data into the device, the
“Write Enable” Latch (WEL) must first be set by issuing
the WREN instruction (Figure 3). CS is first taken LOW,
then the WREN instruction is clocked into the device.
After all eight bits of the instruction are transmitted, CS
must then be taken HIGH. If the user continues the
Write Operation without taking CS HIGH after issuing
the WREN instruction, the Write Operation will be
ignored.
– CS must come HIGH at the proper clock count in
order to start a nonvolatile write cycle.
Characteristics subject to change without notice. 11 of 22
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X55061 – Preliminary Information
Figure 8. Read Status Register Sequence
CS
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14
SCK
Instruction
SI
Data Out
High Impedance
SO
7
6
5
4
3
2
1
0
MSB
Figure 9. Write Enable Latch Sequence
CS
0
1
2
3
4
5
6
7
SCK
SI
High Impedance
SO
Figure 10. Write Sequence
CS
0
1
2
3
4
5
6
7
8
9
10
20 21 22 23 24 25 26 27 28 29 30 31
SCK
Instruction
16 Bit Address
15 14 13
Data Byte 1
3
2
1
0
7
6
5
4
3
2
1
0
SI
CS
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
SCK
Data Byte 2
Data Byte 3
Data Byte N
SI
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
6
5
4
3
2
1
0
Characteristics subject to change without notice. 12 of 22
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X55061 – Preliminary Information
Figure 11. Status Register Write Sequence
CS
0
1
2
3
4
5
6
7
8
7
9
6
10 11 12 13 14 15
SCK
Instruction
Data Byte
5
4
3
2
1
0
SI
High Impedance
SO
SYMBOL TABLE
WAVEFORM
INPUTS
OUTPUTS
Must be
steady
Will be
steady
May change
from LOW
to HIGH
Will change
from LOW
to HIGH
May change
from HIGH
to LOW
Will change
from HIGH
to LOW
Don’t Care:
Changes
Allowed
Changing:
State Not
Known
N/A
Center Line
is High
Impedance
Characteristics subject to change without notice. 13 of 22
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X55061 – Preliminary Information
ABSOLUTE MAXIMUM RATINGS
COMMENT
Temperature under bias ...................–65°C to +135°C
Storage temperature ........................–65°C to +150°C
Voltage on any pin with
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only; functional operation of the
device (at these or any other conditions above those
listed in the operational sections of this specification) is
not implied. Exposure to absolute maximum rating con-
ditions for extended periods may affect device reliability.
respect to V ......................................–1.0V to +7V
SS
D.C. output current ............................................... 5mA
Lead temperature (soldering, 10 seconds).........300°C
RECOMMENDED OPERATING CONDITIONS
Temperature
Commercial
Industrial
Min.
0°C
Max.
70°C
Device Option
-2.7A
Supply Voltage
2.7V-5.5V
–40°C
+85°C
Blank
4.5V-5.5V
D.C. OPERATING CHARACTERISTICS
(Over recommended operating conditions unless otherwise specified.)
Limits
Symbol
Parameter
Min.
Typ.
Max.
Unit
Test Conditions
(1)
I
V
Supply Current (Active)
mA SCK = V x 0.1/V
CC CC
CC1
CC
x 0.9 @ 10MHz,
(Excludes I
(Excludes I
Memory
) Read Memory array
) Write nonvolatile
1.5
3.0
OUT
OUT
SO, V
, RESET,
OUT
LOWLINE = Open
(2)
(1)
I
V
Supply Current (Passive)
µA
µA
CS = V , V = V or
CC2
CC
CC IN
SS
V
, V
= Open
(Excludes I
(Excludes I
(Excludes I
) WDT on, 5V
) WDT on, 2.7V
) WDT off, 5V
50.0
40.0
30.0
90.0
60.0
50.0
CC OUT
OUT
OUT
OUT
I
V
Current (Battery Backup Mode)
1
V
V
= 0V, V
= 2.8V,
CC3
CC
CC
BATT
, RESET,
(Excludes I
)
OUT
OUT
LOWLINE = Open
(3)
I
V
V
Current (Excludes I
Current (Excludes I
)
)
1
µA
µA
V
= V
BATT1
BATT
OUT
OUT
CC
I
0.4
1.0
V
V
= V
= 2.8V, V
,
BATT
BATT2
BATT
OUT
OUT
(Battery Backup Mode)
,
BATT
OUT
RESET = Open
V
V
Output Voltage (V > V
CC
+ 0.03V
+ 0.03V
V
V
– 0.05
V
V
– 0.02
V
V
I
I
= -5mA
= -50mA
OUT1
BATT
CC
CC
OUT
OUT
or V > V
– 0.5
– 0.2
CC
TRIP
CC
CC
Output Voltage (V < V
V
– 0.2
V
V
I
= -250µA
OUT2
CC
BATT
BATT
OUT
and V < V
) {Battery Backup}
CC
TRIP
V
Output (BATT-ON) LOW Voltage
0.4
V
I
I
= 3.0mA (5V)
= 1.0mA (3V)
OLB
OL
OL
V
Output (BATT-ON) HIGH Voltage
Battery Switch Hysteresis
V
– 0.8
V
I
= -0.4mA (3V)
OHB
OUT
OH
V
50
-50
mV Power Up
mV Power Down
BSH
(V < V
)
CC
TRIP
RESET/MR/LOWLINE
(4)
V
Input (MR) LOW Voltage
Input (MR) HIGH Voltage
-0.5
x 0.7
V
x 0.3
ILM
IHM
CC
(4)
V
V
V
+ 0.5
CC
CC
Characteristics subject to change without notice. 14 of 22
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X55061 – Preliminary Information
D.C. OPERATING CHARACTERISTICS (CONTINUED)
(Over recommended operating conditions unless otherwise specified.)
Limits
Symbol
Parameter
Min.
Typ.
Max.
4.75
60
Unit
V
Test Conditions
V
V
Reset Trip Point Voltage
4.5
4.62
TRIP
CC
V
Low V RESET Hysteresis
CC
mV
V
LVRH
V
Output (RESET, WDO, LOWLINE)
LOW Voltage
0.4
I
I
= 3.0mA (5V)
= 1.0mA (3V)
OLR
OL
OL
V
Output (WDO, LOWLINE) HIGH
Voltage
V
– 0.8
V
I
= -0.4mA (5V)
OHR
OUT
OL
Second Supply Monitor
I
V2MON Current
15
30
3.05
60
µA
V
V2
V2
V2MON Reset Trip Point Voltage
V2MON Hysteresis
2.85
2.95
TRIP
V2H
V
mV
V
V
Output (V2FAIL) LOW Voltage
0.4
I
I
= 3.0mA (5V)
= 1.0mA (3V)
OLx
OL
OL
SPI Interface
(4)
V
Input (CS, SI, SCK, WP) LOW Voltage
Input (CS, SI, SCK, WP) HIGH Voltage
-0.5
V
x 0.3
V
V
ILx
CC
(4)
V
V
x 0.7
V
+ 0.5
10
IHx
CC
CC
I
Input Leakage Current (CS, SI, SCK,
WP)
µA
LIx
V
Output (SO) LOW Voltage
0.4
V
V
I
I
= 3.0mA (5V)
= 1.0mA (3V)
OLS
OHS
OL
OL
V
Output (SO) HIGH Voltage
V
– 0.8
I
= -1.0mA (5V)
OUT
OH
Notes: (1) The device enters the Active state after any start, and remains active until 9 clock cycles later if the Device Select Bits in the Slave
Address Byte are incorrect; 200ns after a stop ending a read operation; or t after a stop ending a write operation.
WC
(2) The device goes into Standby: 200ns after any Stop, except those that initiate a high voltage write cycle; t
after a stop that
WC
initiates a high voltage cycle; or 9 clock cycles after any start that is not followed by the correct Device Select Bits in the Slave
Address Byte.
(3) Negative number indicate charging current, Positive numbers indicate discharge current.
(4) V min. and V max. are for reference only and are not tested.
IL
IH
CAPACITANCE T = +25°C, f = 1MHz, V
= 5V
A
CC
Symbol
Test
Max.
8
Unit Conditions
(1)
C
Output Capacitance (SO, RESET, V2FAIL, WDO, LOWLINE, BATT-ON)
pF
V
= 0V
OUT
OUT
(1)
C
Input Capacitance (SCK, SI, CS, WP)
6
pF
V
= 0V
IN
IN
Note: (1) This parameter is periodically sampled and not 100% tested.
Characteristics subject to change without notice. 15 of 22
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X55061 – Preliminary Information
EQUIVALENT A.C. LOAD CIRCUIT AT 5V V
A.C. TEST CONDITIONS
CC
Input pulse levels
V
x 0.1 to V x 0.9
CC
V
CC
V
OUT
V2MON
OUT
Input rise and fall times
Input and output timing level
10ns
1.53KΩ
V
x0.5
1.53KΩ
CC
2.06KΩ
RESET
BATT-ON/LOWLINE
30pF
SO
V2FAIL
30pF
3.03KΩ
30pF
A.C. CHARACTERISTICS (Over recommended operating conditions, unless otherwise specified)
Serial Input Timing
2.7-5.5V
Symbol
Parameter
Clock Frequency
Min.
0
Max.
Unit
MHz
ns
f
10
SCK
CYC
t
Cycle Time
100
50
t
CS Lead Time
CS Lag Time
ns
LEAD
t
200
40
ns
LAG
t
Clock HIGH Time
Clock LOW Time
Data Setup Time
Data Hold Time
Input Rise Time
Input Fall Time
CS Deselect Time
Write Cycle Time
ns
WH
t
40
ns
WL
t
10
ns
SU
t
10
ns
H
(3)
t
t
20
20
ns
RI
(3)
ns
FI
t
50
ns
CS
(4)
t
10
ms
WC
Serial Input Timing
t
CS
CS
t
t
LAG
LEAD
SCK
t
t
t
t
FI
SU
H
RI
SI
MSB IN
LSB IN
High Impedance
SO
Characteristics subject to change without notice. 16 of 22
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X55061 – Preliminary Information
Serial Output Timing
2.7-5.5V
Symbol
Parameter
Clock Frequency
Min.
Max.
10
Unit
MHz
ns
f
0
SCK
t
Output Disable Time
Output Valid from Clock Low
Output Hold Time
50
DIS
t
40
ns
V
t
0
ns
HO
(3)
t
t
Output Rise Time
25
25
ns
RO
(3)
Output Fall Time
ns
FO
Notes: (3) This parameter is periodically sampled and not 100% tested.
(4) t is the time from the rising edge of CS after a valid write sequence has been sent to the end of the self-timed internal nonvolatile
WC
write cycle.
Serial Output Timing
CS
t
t
t
LAG
CYC
WH
SCK
SO
t
t
t
t
DIS
V
HO
WL
MSB Out
MSB–1 Out
LSB Out
ADDR
LSB IN
SI
Characteristics subject to change without notice. 17 of 22
REV 1.1 3/5/01
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X55061 – Preliminary Information
Power-Up and Power-Down Timing
V
TRIP
V
BATT
V
CC
0V
t
RPD
t
t
PURST
PURST
RESET
V
V
CC
BAT
V
OUT
0V
t
t
VB2
VB1
V
OUT
BATT-ON
V
to LOWLINE Timings
CC
V
V
TRIP
TRIP
V
CC
t
RPD
t
F
0V
t
RPD
t
R
V
OH
LOWLINE
V
OL
V
TRIP
V
BATT
0V
V2MON to V2FAIL Timings
V
TRIP
V2MON
0V
t
RPD2
t
t
RPD2
F
t
R
V2FAIL
Characteristics subject to change without notice. 18 of 22
REV 1.1 3/5/01
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X55061 – Preliminary Information
RESET Output Timing
Symbol
Parameter
Min.
Typ.
150
10
Max.
250
20
Unit
ms
µs
µs
ns
µs
µs
V
t
RESET Time Out Period
75
PURST
(5)
t
V
V
RESET (Power down only) V to LOWLINE
TRIP
RPD
TRIP
(5)
t
to V2FAIL
10
20
RPD2
TRIP
t
LOWLINE to RESET delay (Power down only)
100
1000
1000
1
250
800
LR
(6)
t
V
V
/V2MON Fall Time
/V2MON Rise Time
F
CC
(6)
t
R
CC
V
Reset Valid V
CC
RVALID
t
t
V
V
+ 0.03 v to BATT-ON (logical 0)
– 0.03 v to BATT-ON (logical 1)
20
20
µs
µs
VB1
VB2
BATT
BATT
Notes: (5) This parameter is not 100% tested.
(6) This measurement is from 10% to 90% of the supply voltage.
CS/WDI vs. RESET Timing
CS/WDI
t
CST
RESET
t
t
RST
t
t
RST
WDO
WDO
RESET Output Timing
Symbol
Parameter
Min.
Typ.
Max.
Unit
t
Watchdog Time Out Period,
WD1 = 1, WD0 = 0
WDO
75
200
500
150
400
800
250
600
1200
ms
ms
ms
WD1 = 0, WD0 = 1
WD1 = 0, WD0 = 0
t
CS Pulse Width to Reset the Watchdog
Reset Time Out
400
75
ns
CST
t
150
250
ms
RST
Characteristics subject to change without notice. 19 of 22
REV 1.1 3/5/01
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X55061 – Preliminary Information
V
Set/Reset Conditions
TRIP
V
/V2MON
CC
(V
/V
)
TRIP TRIP2
V
TRIP
t
t
THD
TSU
V
P
WP
t
t
t
VPH
VPS
VPO
t
PCS
CS
t
RP
SCK
SI
0001h or (Set)
0003h
06h
02h
000Bh or (Reset)
000Dh
V
Programming Specifications V
= 2.7-5.5V; Temperature = 25°C
CC
TRIP
Parameter
Description
Min. Max. Unit
t
WP V
WP V
Program Voltage Setup time
Program Voltage Hold time
10
10
10
10
10
µs
µs
µs
µs
ms
ms
ms
ms
V
VPS
VPH
TRIP
t
TRIP
t
V
V
V
V
V
Program Pulse Width
Level Setup time
P
TRIP
TRIP
TRIP
TRIP
TRIP
t
TSU
THD
t
Level Hold (stable) time
Write Cycle Time
t
10
WC
t
Program Cycle Recovery Period (Between successive programming cycles)
Program Voltage Off time before next cycle
TRIP
10
0
RP
t
WP V
VPO
V
Programming Voltage
Programed Voltage Range
10
2.5
15
P
V
V
5.0
V
TRAN
TRIP
V
Initial V
at 25°C.)
Program Voltage accuracy (V applied—V ) (Programmed
TRIP
-0.2 +0.4
V
ta1
TRIP
CC
V
Subsequent V
Program Voltage accuracy [(V applied—V )—V )
TRIP
-25
-25
-25
+25
+25
+25
mV
mV
mV
ta2
TRIP
CC
ta1
(Programmed at 25°C.)
V Program Voltage repeatability (Successive program operations.)
TRIP
(Programmed at 25°C.)
V
tr
V
V
TRIP
Program variation after programming (0–75°C). (Programmed at 25°C.)
tv
V
programming parameters are periodically sampled and are not 100% tested.
TRIP
Characteristics subject to change without notice. 20 of 22
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X55061 – Preliminary Information
PACKAGING INFORMATION
20-Lead Plastic, TSSOP, Package Type V
.025 (.65) BSC
.169 (4.3)
.177 (4.5)
.252 (6.4) BSC
.252 (6.4)
.300 (7.62)
.047 (1.20)
.0075 (.19)
.0118 (.30)
.002 (.05)
.006 (.15)
.010 (.25)
Gage Plane
0° - 8°
Seating Plane
.019 (.50)
.029 (.75)
Detail A (20X)
.031 (.80)
.041 (1.05)
See Detail “A”
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
Characteristics subject to change without notice. 21 of 22
REV 1.1 3/5/01
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X55061 – Preliminary Information
Ordering Information
Operating
V
Range
V1
Range
V2 Range
TRIP
Package
Temperature Range
Part Number
X55621V20-4.5A
X55621V20I-4.5A
X55621V20
CC
TRIP
4.5–5.5V
4.5–5.5V
2.7–5.5V
2.7–5.5V
4.5–4.75V
4.5–4.75V
2.85–3.0V
2.55–2.75V
2.55–2.7V
2.85–3.0V
4.5–4.75V
4.5–4.75V
20L TSSOP
0°C–70°C
-40°C–85°C
0°C–70°C
20L TSSOP
20L TSSOP
20L TSSOP
-40°C–85°C
0°C–70°C
X55621V20I
X55621V20-2.7A
X55621V20I-2.7A
X55621V20-2.7
X55621V20I-2.7
-40°C–85°C
0°C–70°C
-40°C–85°C
Part Mark Information
X55061
W
V20 = 20-Lead TSSOP
X
Blank = 5V 10%, 0°C to +70°C, V1
= 4.5–4.75, V2
= 2.55–2.7
TRIP
TRIP
AL = 5V 10%, 0°C to +70°C, V1
= 4.5–4.75, V2
= 2.85–3.0
TRIP
TRIP
I = 5V 10%, –40°C to +85°C, V1
= 4.5–4.75, V2
= 2.55–2.7
TRIP
TRIP
AM = 5V 10%, –40°C to +85°C, V1
= 4.5–4.75, V2
= 2.85–3.0
TRIP
TRIP
F = 2.7V to 5.5V, 0°C to +70°C, V1
= 2.85–3.0, V2
= 4.5–4.75
TRIP
TRIP
AN = 2.7V to 5.5V, 0°C to +70°C, V1
= 2.55–2.7, V2
= 4.5–4.75
TRIP
TRIP
G = 2.7V to 5.5V, –40°C to +85°C, V1
= 2.85–3.0, V2
= 4.5–4.75
TRIP
TRIP
AP = 2.7V to 5.5V, –40°C to +85°C, V1
= 2.55–2.7, V2
= 4.5–4.75
TRIP
TRIP
LIMITED WARRANTY
©Xicor, Inc. 2001 Patents Pending
Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty,
express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement.
Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and prices
at any time and without notice.
Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, or licenses are implied.
COPYRIGHTS ANDTRADEMARKS
Xicor, Inc., the Xicor logo, E2POT, XDCP, XBGA, AUTOSTORE, Direct Write cell, Concurrent Read-Write, PASS, MPS, PushPOT, Block Lock, IdentiPROM,
E2KEY, X24C16, SecureFlash, and SerialFlash are all trademarks or registered trademarks of Xicor, Inc. All other brand and product names mentioned herein are
used for identification purposes only, and are trademarks or registered trademarks of their respective holders.
U.S. PATENTS
Xicor products are covered by one or more of the following U.S. Patents: 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846;
4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829,482; 4,874,967; 4,883,976; 4,980,859; 5,012,132; 5,003,197; 5,023,694; 5,084,667; 5,153,880; 5,153,691;
5,161,137; 5,219,774; 5,270,927; 5,324,676; 5,434,396; 5,544,103; 5,587,573; 5,835,409; 5,977,585. Foreign patents and additional patents pending.
LIFE RELATED POLICY
In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detection
and correction, redundancy and back-up features to prevent such an occurrence.
Xicor’s products are not authorized for use in critical components in life support devices or systems.
1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to
perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user.
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or effectiveness.
Characteristics subject to change without notice. 22 of 22
REV 1.1 3/5/01
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