X84041V-3 [RENESAS]
512X8 I2C/2-WIRE SERIAL EEPROM, PDSO14, PLASTIC, TSSOP-14;
| 型号： | X84041V-3 |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | 512X8 I2C/2-WIRE SERIAL EEPROM, PDSO14, PLASTIC, TSSOP-14 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 光电二极管 内存集成电路 |
| 文件： | 总13页 (文件大小：138K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
4K
MPS™ EEPROM
X84041
Micro Port Saver EEPROM
DESCRIPTION
FEATURES
• Direct interface to micros
The X84041 Micro Port Saver is a 4096-bit CMOS
EEPROM designed for a direct interface to port limited
microcontroller or I/O limited microprocessor designs.
The X84041 provides all of the benefits of serial mem-
ories, such as low cost, low power, low voltage opera-
tion, and small package size, while featuring higher
data transfer rates and reduced interface code require-
ments—without the need for a dedicated serial bus.
The X84041 is organized as a 512 x 8, but is also suit-
able in 16-bit or 32-bit environments, due to the bit
serial nature of the interface.
—Eliminates I/O port requirements
—No interface glue logic required
—Eliminates need for parallel to serial converters
• 3.3Mbps data transfer rate
• Low power CMOS
—2.7V to 5.5V operation
—Standby current less than 50µA
—Active current less than 1mA
• 45ns read access time
• 8-byte page write mode
• Typical nonvolatile write cycle time: 5ms
• High reliability
—100,000 endurance cycles
—Guaranteed data retention: 100 years
• 8-lead PDIP, 8-lead SOIC, and 14-lead TSSOP
packages
The X84041 directly connects to the processor bus
and communicates over a single data line using a
sequence of standard bus read and write operations.
This eliminates the need for dedicated port pins, paral-
lel to serial converters, complicated ASIC implementa-
tions, or other glue logic, lowering system cost.
BLOCK DIAGRAM
WP
H.V. Generation
Timing & Control
CE
Command
EEPROM
Array
512 x 8
OE
Decode
and
X
DEC
WE
I/O
Control
Logic
Y Decode
Data Register
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X84041
PIN NAMES
Write Enable (WE)
The Write Enable input must be LOW to write either
data or command sequences to the X84041.
I/O
CE
Data Input/Output
Chip Enable Input
Output Enable Input
Write Enable Input
Write Protect Input
Supply Voltage
Ground
OE
WE
WP
VCC
VSS
NC
Data In/Data Out (I/O)
Data and command sequences are serially written to
or serially read from the X84041 through the I/O pin.
Write Protect (WP)
When the Write Protect input is LOW, nonvolatile writes
to the X84041 are disabled. When WP is HIGH, all
functions, including nonvolatile writes, operate nor-
mally. If a nonvolatile write cycle is in progress, WP
going LOW will have no effect on the cycle already
underway, but will inhibit any additional nonvolatile
write cycles.
No Connect
PIN CONFIGURATION
DIP/SOIC
1
8
CE
V
CC
I/O
2
7
6
5
NC
OE
WE
DEVICE OPERATION
X8401
WP
3
V
4
The X84041 is a serial 512 x 8 bit EEPROM designed
to interface directly with most microprocessor buses.
Standard CE, OE, and WE signals control the read and
write operations, and a single l/O line is used to send
and receive data and commands serially.
SS
TSSOP
X8401
1
CE
I/O
14
13
V
CC
2
3
NC
NC
NC
NC
OE
WE
12
11
10
9
NC
NC
NC
Data Timing
4
Data input on the l/O line is latched on the rising edge
of either WE or CE, whichever occurs first. Data output
on the l/O line is active whenever both OE and CE are
LOW. Care should be taken to ensure that WE and OE
are never both LOW while CE is LOW.
5
6
7
WP
V
SS
8
A Write Protect (WP) pin provides hardware protection
against inadvertent writes to the memory.
Read Sequence
A read sequence consists of sending a 16-bit address
followed by the reading of data serially. The address is
written by issuing 16 separate write cycles (WE and
CE LOW, OE HIGH) to the part without a read cycle
between the write cycles. The address is sent serially,
most significant bit first, over the I/O line. Note that this
sequence is fully static, with no special timing restric-
tions, and the processor is free to perform other tasks
on the bus whenever the X84041 CE pin is HIGH.
Once the 16 address bits are sent, a byte of data can
be read on the I/O line by issuing 8 separate read
cycles (OE and CE LOW, WE HIGH). At this point,
issuing a reset sequence will terminate the read
sequence, otherwise the X84041 will await further
reads in the sequential read mode.
Xicor EEPROMs are designed and tested for applica-
tions requiring extended endurance. Inherent data
retention is greater than 100 years.
PIN DESCRIPTIONS
Chip Enable (CE)
The Chip Enable input must be LOW to enable all read/
write operations. When CE is HIGH, the chip is dese-
lected, the I/O pin is in the high impedance state, and
unless a nonvolatile write operation is underway, the
X84041 is in the standby power mode.
Output Enable (OE)
The Output Enable input must be LOW to enable the
output buffer and to read data from the X84041 on the
I/O line.
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X84041
Sequential Read
the multiple read or write cycle sequences that are nor-
mally used when reading from or writing to the part.
This sequence can be used at any time to interrupt or
end a sequential read or page load. As soon as the
write “0” cycle is complete, the part is reset (unless a
nonvolatile write cycle is in progress). The second read
cycle in this sequence, and any further read cycles, will
read a HIGH on the l/O pin until a valid read sequence
is issued. The reset sequence must be issued at the
beginning of both read and write sequences to be sure
the X84041 initiates these operations properly.
The byte address is automatically incremented to the
next higher address after each byte of data is read.
The data stored in the memory at the next address can
be read sequentially by continuing to issue read
cycles. When the highest address is reached ($1FF),
the address counter rolls over to address $000 and
reading may be continued indefinitely.
Reset Sequence
The reset sequence resets the X84041 and sets an
internal write enable latch. A reset sequence can be
sent at any time by performing a read/write “0”/read
sequence (see Figs. 1 and 2). This sequence breaks
Figure 1. Read Sequence
CE
OE
WE
"0"
I/O (IN)
X
X
X
X
X
X
X A8 A7 A6 A5 A4 A3 A2 A1 A0
I/O (OUT)
D7
D6 D5 D4 D3 D2 D1 D0
RESET
Load Address
Read Data
Write Sequence
by issuing a special read/write “1”/read sequence. The
first read cycle ends the page load, then the write “1”
followed by a read starts the nonvolatile write cycle.
The X84041 recognizes 8-byte pages beginning at
addresses XXXXXX000. When sending data to the
part, attempts to exceed the upper address of the page
will result in the address counter “wrapping-around” to
the first address on the page, where data loading can
continue. For this reason, sending more than 64 con-
secutive data bits will result in overwriting previous
data. A nonvolatile write cycle will not start if a partial
or incomplete write sequence is issued. The internal
write enable latch is reset when the nonvolatile write
cycle is completed to prevent inadvertent writes. Note
that this sequence is fully static, with no special timing
A nonvolatile write sequence consists of sending a
reset sequence, a 16-bit address (the first 7 of which
are don’t cares), up to 8 bytes of data, and then a spe-
cial “start nonvolatile write cycle” command sequence.
The reset sequence is issued first (as described in the
Reset Sequence section) to set the internal write
enable latch. The address is written serially by issuing
16 separate write cycles (WE and CE LOW, OE HIGH)
to the part without any read cycles between the writes.
The address is sent serially, most significant bit first, on
the l/O pin. Up to eight bytes of data are written by
issuing either 8, 16, 24, 32, 40, 48, 56, or 64 separate
write cycles. Again, no read cycles are allowed
between writes. The nonvolatile write cycle is initiated
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X84041
restrictions. The processor is free to perform other
tasks on the bus whenever the chip enable pin (CE) is
HIGH.
are LOW and WE is HIGH. During a nonvolatile write
cycle the l/O pin is LOW. When the nonvolatile write
cycle is complete, the l/O pin goes HIGH. A reset
sequence can also be issued during a nonvolatile write
cycle with the same result: I/O is LOW as long as a
nonvolatile write cycle is in progress, and l/O is HIGH
when the nonvolatile write cycle is done.
Nonvolatile Write Status
The status of a nonvolatile write cycle can be deter-
mined at any time by simply reading the state of the l/O
pin on the X84041. This pin is read when OE and CE
Figure 2. Write Sequence
CE
OE
WE
"0"
I/O (IN)
X
X
X
X
X
X
X
A8 A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
"1"
"0"
I/O (OUT)
RESET
Load Address
Load Data
START
Nonvolatile
Write
Write Protection
SYMBOL TABLE
The following circuitry has been included to prevent
inadvertent nonvolatile writes:
WAVEFORM
INPUTS
OUTPUTS
– The internal Write Enable latch is reset upon power-up.
Must be
steady
Will be
steady
– A reset sequence must be issued to set the internal
write enable latch before starting a write sequence.
May change
from LOW to
HIGH
Will change
from LOW to
HIGH
– A special “start nonvolatile write” command sequence
is required to start a nonvolatile write cycle.
May change
Will change
from HIGH to from HIGH to
– The internal Write Enable latch is reset automatically
at the end of a nonvolatile write cycle.
LOW
LOW
Don’t Care:
Changes
Allowed
Changing:
State Not
Known
– The internal Write Enable latch is reset and remains
reset as long as the WP pin is LOW, which blocks all
nonvolatile write cycles.
N/A
Center Line
is High
Impedance
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X84041
ABSOLUTE MAXIMUM RATINGS
COMMENT
Temperature under bias ................... –65°C to +135°C
Storage temperature ........................ –65°C to +150°C
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only; the functional operation of the
device at these or any other conditions (above those indi-
cated in the operational sections of this specification) is
not implied. Exposure to absolute maximum rating condi-
tions for extended periods may affect device reliability.
Terminal voltage with respect to V ..........–1V to +7V
SS
DC output current................................................. 5mA
Lead temperature (soldering, 10 seconds)........ 300°C
RECOMMENDED OPERATING CONDITIONS
Temperature
Commercial
Industrial
Min.
0°C
Max.
+70°C
+85°C
Supply Voltage
X84041
Limits
5V ±10%
3V ±10%
2.7V to 5.5V
–40°C
X84041-3
X84041-2.7†
† Contact factory for availability
D.C. OPERATING CHARACTERISTICS (V = 5V ±10%)
CC
(Over the recommended operating conditions, unless otherwise specified.)
Limits
Symbol
Parameter
Min.
Max.
Unit
Test Conditions
I
V
V
V
supply current (read)
1
mA
OE = V , WE = V , I/O = Open, CE clocking
@ 2MHz
CC1
CC
CC
CC
IL
IH
I
supply current (write)
standby current
3
mA
µA
I
during nonvolatile write cycle all inputs at
CC
CC2
CMOS levels
I
50
CE = V , other inputs = V or V
CC CC SS
SB
V
V
V
= 5V ±10%
CC
I
Input leakage current
Output leakage current
Input LOW voltage
10
10
µA
µA
V
= V to V
SS CC
LI
IN
I
= V to V
SS CC
LO
OUT
(1)
lL
V
–1
V
x 0.3
CC
(1)
V
Input HIGH voltage
Output LOW voltage
Output HIGH voltage
V
V
x 0.7
V
+ 0.5
V
IH
CC
CC
V
0.4
V
I
I
= 2.1mA, V = 5V ±10%
OL CC
OL
V
– 0.8
V
= –1mA, V = 5V ±10%
OH CC
OH
CC
Note: (1) V min. and V max. are for reference only and are not tested.
IL
IH
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X84041
D.C. OPERATING CHARACTERISTICS (V
= 3V ±10%)
CC
(Over the recommended operating conditions, unless otherwise specified.)
Limits
Symbol
Parameter
Min.
Max.
Unit
Test Conditions
I
V
V
V
supply current (read)
250
µA
OE = V , WE = V , I/O = Open, CE clocking
@ 2MHz
CC1
CC
CC
CC
IL
IH
I
supply current (write)
standby current
1
mA
µA
I
during nonvolatile write cycle All inputs at
CC
CC2
CMOS levels
I
10
CE = V , Other inputs = V or V
,
SB1
CC
CC
SS
V
V
V
= 3V ±10%
CC
I
Input leakage current
Output leakage current
Input low voltage
10
10
µA
µA
V
= V to V
SS CC
LI
IN
I
= V to V
SS CC
LO
OUT
(1)
lL
V
–1
V
x 0.3
CC
(1)
V
Input high voltage
Output low voltage
Output high voltage
V
V
x 0.7
V
+ 0.5
V
IH
CC
CC
V
0.4
V
I = 1mA, V = 3V ±10%
OL CC
OL
V
– 0.4
V
I = –400µA, V = 3V ±10%
OH CC
OH
CC
Note: (1) V min. and V max. are for reference only and are not tested.
IL
IH
CAPACITANCE T = +25°C, f = 1MHz, V
= 5V
A
CC
Symbol
Parameter
Input/Output capacitance
Input capacitance
Max.
Unit
pF
Test Conditions
(2)
I/O
C
8
6
V
= 0V
= 0V
I/O
(2)
IN
C
pF
V
IN
POWER-UP TIMING
Symbol
Parameter
Power-up to read operation
Power-up to write operation
Max.
Unit
ms
(3)
PUR
t
2
5
(3)
PUW
t
ms
Note: (3) Time delays required from the time the V
is stable until the specific operation can be initiated. Periodically sampled, but not 100%
CC
tested.
A.C. CONDITIONS OF TEST
EQUIVALENT A.C. LOAD CIRCUITS
Input pulse levels
V
x 0.1 to V x 0.9
CC
CC
5V
3V
Input rise and fall times
Input and output timing levels
5ns
2.06KΩ
2.39KΩ
V
x 0.5
CC
Output
4.58KΩ
Output
3.03KΩ
30pF
30pF
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X84041
A.C. CHARACTERISTICS (Over the recommended operating conditions, unless otherwise specified.)
Read Cycle Limits—X84041
V
= 5V ±10%
Max.
V
= 3V ±10%
Max.
CC
CC
Symbol
Parameter
Read cycle time
Min.
Min.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
300
300
RC
t
CE access time
45
45
65
65
CE
t
OE access time
OE
t
CE LOW time
70
70
0
70
70
0
LOW
t
CE HIGH time
HIGH
(4)
t
CE LOW to output In low Z
CE HIGH to output In high Z
OE LOW to output In low Z
OE HIGH to output In high Z
Output hold from CE or OE HIGH
WE HIGH setup time
WE HIGH hold time
LZ
(4)
HZ
t
0
30
30
0
35
35
(4)
OLZ
t
0
0
(4)
OHZ
t
0
0
t
0
0
OH
t
25
25
25
25
WES
t
WEH
Note: (4) Periodically sampled, but not 100% tested. t
and t
are measured from the point where CE or OE goes HIGH (whichever
OHZ
HZ
occurs first) to the time when I/O is no longer being driven into a 5pF load.
Read Cycle
t
RC
t
t
HIGH
LOW
t
CE
CE
WE
OE
t
WES
t
OE
t
WEH
t
OHZ
I/O
HIGH Z
Data
t
OH
t
t
OLZ
LZ
t
HZ
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X84041
Write Cycle Limits—X84041
V
= 5V ±10%
Max.
V
= 3V ±10%
Max.
CC
CC
Symbol
Parameter
Min.
Min.
Unit
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
(5)
NVWC
t
Nonvolatile write cycle time
Write cycle time
10
10
t
300
30
200
0
300
30
200
0
WC
t
WE pulse width
WP
t
WE HIGH recovery time
Write setup time
WPH
t
CS
t
Write hold time
0
0
CH
t
CE pulse width
30
200
50
50
30
5
30
200
50
50
30
5
CP
t
CE HIGH recovery time
OE HIGH setup time
OE HIGH hold time
Data setup time
CPH
t
OES
t
OEH
(6)
t
DS
(6)
DH
t
Data hold time
(7)
(7)
(7)
t
WP HIGH before CE
WP HIGH after CE
WP HIGH before WE
WP HIGH after WE
500
500
500
500
WPCS
WPCH
t
t
500
500
WPWS
WPWH
(7)
t
500
500
Notes: (5) t
is the time from the falling edge of OE or CE (whichever occurs last) of the second read cycle in the “start nonvolatile write
NVWC
cycle” sequence until the self-timed, internal nonvolatile write cycle is completed.
(6) Data is latched into the X84041 on the rising edge of CE or WE, whichever occurs first.
(7) Periodically sampled, but not 100% tested.
CE Controlled Write Cycle
t
CPH
t
CP
CE
t
t
OEH
OES
OE
WE
WP
I/O
t
CS
t
CH
t
WP
t
WPH
t
t
WPCS
WPCH
Data
t
t
DS
DH
HIGH Z
t
WC
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X84041
WE Controlled Write Cycle
t
CPH
t
CP
CE
t
OES
t
OE
WE
WP
I/O
CS
t
CH
t
OEH
t
WPH
t
WP
t
WPWH
t
WPWS
t
t
DS
DH
HIGH Z
Data
t
WC
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X84041
PACKAGING INFORMATION
8-Lead Plastic Dual In-Line Package Type P
0.430 (10.92)
0.360 (9.14)
0.260 (6.60)
0.240 (6.10)
Pin 1 Index
Pin 1
0.060 (1.52)
0.020 (0.51)
0.300
(7.62) Ref.
Half Shoulder Width On
All End Pins Optional
0.145 (3.68)
0.128 (3.25)
Seating
Plane
0.025 (0.64)
0.015 (0.38)
0.065 (1.65)
0.150 (3.81)
0.125 (3.18)
0.045 (1.14)
0.110 (2.79)
0.090 (2.29)
0.020 (0.51)
0.016 (0.41)
0.325 (8.25)
0.300 (7.62)
.073 (1.84)
Max.
0°
Typ. 0.010 (0.25)
15°
NOTE:
1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
2. PACKAGE DIMENSIONS EXCLUDE MOLDING FLASH
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X84041
PACKAGING INFORMATION
8-Lead Plastic Small Outline Gull Wing Package Type S
0.150 (3.80) 0.228 (5.80)
0.158 (4.00) 0.244 (6.20)
Pin 1 Index
Pin 1
0.014 (0.35)
0.019 (0.49)
0.188 (4.78)
0.197 (5.00)
(4X) 7°
0.053 (1.35)
0.069 (1.75)
0.004 (0.19)
0.010 (0.25)
0.050 (1.27)
0.010 (0.25)
0.050" Typical
X 45°
0.020 (0.50)
0.050"
Typical
0° - 8°
0.0075 (0.19)
0.010 (0.25)
0.250"
0.016 (0.410)
0.037 (0.937)
0.030"
Typical
8 Places
FOOTPRINT
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
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X84041
PACKAGING INFORMATION
14-Lead Plastic, TSSOP, Package Type V
.025 (.65) BSC
.169 (4.3)
.177 (4.5)
.252 (6.4) BSC
.193 (4.9)
.200 (5.1)
.047 (1.20)
.0075 (.19)
.0118 (.30)
.002 (.05)
.006 (.15)
.010 (.25)
Gage Plane
0° - 8°
Seating Plane
.019 (.50)
.029 (.75)
Detail A (20X)
.031 (.80)
.041 (1.05)
See Detail “A”
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
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X84041
Ordering Information
X84041
X
X
-X
V
Range
Device
CC
Blank = 4.5V to 5.5V
3 = 2.7V to 3.3V
2.7 = 2.7V to 5.5V
Temperature Range
Blank = Commercial = 0°C to +70°C
I = Industrial = –40°C to +85°C
Package
P = 8-Lead plastic DIP
S = 8-Lead SOIC
V = 14-Lead TSSOP
Part Mark Convention
8-Lead TSSOP
84041
8-Lead SOIC
X84041
8-Lead PDIP
X84041P
EYWW
X
EYWW
X
MYYWWES X
Blank = 4.5V to 5.5V, 0°C to + 70°C
F= 2.7V to 5.5V, 0°C to + 70°C
D = 2.7V to 3.3V, 0°C to + 70°C
I = 4.5V to 5.5V, 40°C to + 85°C
G = 2.7V to 5.5V, 40°C to + 85°C
E = 2.7V to 3.3V, 40°C to + 85°C
Blank = 4.5V to 5.5V, 0°C to + 70°C
F = 2.7V to 5.5V, 0°C to + 70°C
D = 2.7V to 3.3V, 0°C to + 70°C
I = 4.5V to 5.5V, 40°C to + 85°C
G = 2.7V to 5.5V, 40°C to + 85°C
E = 2.7V to 3.3V, 40°C to + 85°C
Blank = 4.5V to 5.5V, 0°C to + 70°C
D = 2.7V to 3.3V, 0°C to + 70°C
I = 4.5V to 5.5V, 40°C to + 85°C
E = 2.7V to 3.3V, 40°C to + 85°C
©Xicor, Inc. 2000 Patents Pending
LIMITED WARRANTY
Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty,
express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement.
Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and prices
at any time and without notice.
Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, or licenses are implied.
TRADEMARK DISCLAIMER:
Xicor and the Xicor logo are registered trademarks of Xicor, Inc. AutoStore, Direct Write, Block Lock, SerialFlash, MPS, and XDCP are also trademarks of Xicor, Inc. All
others belong to their respective owners.
U.S. PATENTS
Xicor products are covered by one or more of the following U.S. Patents: 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846;
4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829,482; 4,874,967; 4,883,976; 4,980,859; 5,012,132; 5,003,197; 5,023,694; 5,084,667; 5,153,880; 5,153,691;
5,161,137; 5,219,774; 5,270,927; 5,324,676; 5,434,396; 5,544,103; 5,587,573; 5,835,409; 5,977,585. Foreign patents and additional patents pending.
LIFE RELATED POLICY
In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detection
and correction, redundancy and back-up features to prevent such an occurrence.
Xicor’s products are not authorized for use in critical components in life support devices or systems.
1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to
perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user.
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or effectiveness.
Characteristics subject to change without notice. 13 of 13
REV 1.0 6/29/00
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