X9111TV14IZ-2.7T1 [RENESAS]
Single Supply/Low Power/1024-Tap/SPI Bus/Single Digitally-Controlled (XDCP™) Potentiometer; TSSOP14; Temp Range: See Datasheet;
| 型号： | X9111TV14IZ-2.7T1 |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | Single Supply/Low Power/1024-Tap/SPI Bus/Single Digitally-Controlled (XDCP™) Potentiometer; TSSOP14; Temp Range: See Datasheet 光电二极管 转换器 电阻器 |
| 文件： | 总19页 (文件大小：416K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATASHEET
Single Supply/Low Power/1024-Tap/SPI Bus/Single
Digitally-Controlled (XDCP™) Potentiometer
X9111
The X9111 integrates a single, digitally controlled
Features
potentiometer (XDCP) on a monolithic CMOS integrated circuit.
• 1024 resistor taps – 10-bit resolution
The digital controlled potentiometer is implemented using
• SPI serial interface for write, read, and transfer operations of
the potentiometer
1023 resistive elements in a series array. Between each
element are tap points connected to the wiper terminal
through switches. The position of the wiper on the array is
controlled by the user through the SPI bus interface. The
potentiometer has associated with it a volatile Wiper Counter
Register (WCR) and four nonvolatile Data Registers that can be
directly written to and read by the user. The contents of the
WCR control the position of the wiper on the resistor array
through the switches. Power-up recalls the contents of the
default data register (DR0) to the WCR.
• Wiper resistance, 40Ω typical at 5V
• Four nonvolatile Data Registers
• Nonvolatile storage of multiple wiper positions
• Power-on recall, loads saved wiper position on power-up
• Standby current <3µA maximum
• V : 2.7V to 5.5V operation
CC
• 100kΩ end-to-end resistance
• 100-year data retention
The XDCP can be used as a 3-terminal potentiometer or as a
2-terminal variable resistor in a wide variety of applications
including control, parameter adjustments, and signal
processing.
• Endurance: 100,000 data changes per bit per register
• 14 Ld TSSOP
• Low-power CMOS
• Single supply version of the X9110
• Pb-Free (RoHS compliant)
V
R
H
CC
WRITE
READ
TRANSFER
ADDRESS
DATA
STATUS
POWER-ON RECALL
100kΩ
1024-taps
POT
WIPER COUNTER
REGISTER (WCR)
BUS
INTERFACE
AND
SPI
BUS
INTERFACE
WIPER
DATA REGISTERS
CONTROL
(DR0-DR3)
CONTROL
R
R
V
NC
W
L
SS
FIGURE 1. FUNCTIONAL DIAGRAM
October 13, 2016
FN8159.5
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2005, 2006, 2016. All Rights Reserved
Intersil (and design) and XDCP are trademarks owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
X9111
Circuit Level Applications
System Level Applications
• Vary the gain of a voltage amplifier
• Adjust the contrast in LCD displays
• Provide programmable DC reference voltages for comparators
and detectors
• Control the power level of LED transmitters in communication
systems
• Control the volume in audio circuits
• Set and regulate the DC biasing point in an RF power amplifier
in wireless systems
• Trim out the offset voltage error in a voltage amplifier circuit
• Set the output voltage of a voltage regulator
• Trim the resistance in Wheatstone bridge circuits
• Control the gain in audio and home entertainment systems
• Provide the variable DC bias for tuners in RF wireless systems
• Set the operating points in temperature control systems
• Control the operating point for sensors in industrial systems
• Trim offset and gain errors in artificial intelligent systems
• Control the gain, characteristic frequency, and Q-factor in filter
circuits
• Set the scale factor and zero point in sensor signal
conditioning circuits
• Vary the frequency and duty cycle of timer ICs
• Vary the DC biasing of a pin diode attenuator in RF circuits
• Provide a control variable (I, V, or R) in feedback circuits
Ordering Information
POTENTIOMETER
PART NUMBER
(Notes 2, 3)
PART
MARKING
ORGANIZATION
TEMP RANGE
(°C)
PACKAGE
(RoHS COMPLIANT)
PKG.
DWG. #
V
LIMITS (V)
(kΩ)
CC
X9111TV14IZ
X9111TV ZI
X9111TV Z
X9111TV ZF
5 ±10%
100
-40 to +85
0 to +70
14 Ld TSSOP (4.4mm)
14 Ld TSSOP (4.4mm)
14 Ld TSSOP (4.4mm)
14 Ld TSSOP (4.4mm)
M14.173
X9111TV14Z
M14.173
M14.173
M14.173
X9111TV14Z-2.7
2.7 to 5.5
0 to +70
X9111TV14IZ-2.7 (Note 1) X9111TV ZG
NOTES:
-40 to +85
1. Add “T1” suffix for 2.5k unit tape and reel option.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), see product information page for X9111. For more information on MSL, see tech brief TB363.
Detailed Functional Diagram
V
CC
POWER-ON
RECALL
HOLD
CS
SCK
SO
DR0 DR1
R
H
WIPER
COUNTER
REGISTER
(WCR)
INTERFACE
AND
CONTROL
CIRCUITRY
100kΩ
1024-taps
Data
SI
A0
A1
R
DR2 DR3
L
Control
R
W
WP
V
SS
FIGURE 2. DETAILED FUNCTIONAL DIAGRAM
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X9111
HOLD (HOLD)
Pin Configuration
HOLD is used in conjunction with the CS pin to select the device.
Once the part is selected and a serial sequence is underway,
HOLD may be used to pause the serial communication with the
controller without resetting the serial sequence. To pause, HOLD
must be brought LOW while SCK is LOW. To resume
communication, HOLD is brought HIGH, again while SCK is LOW.
If the pause feature is not used, HOLD should be held HIGH at all
times.
X9111
(14 LD TSSOP)
TOP VIEW
14
1
2
3
4
5
6
7
V
CC
SO
A0
R
R
R
13
12
11
10
L
NC
H
CS
SCK
SI
W
DEVICE ADDRESS (A , A )
0
1
HOLD
A1
The address inputs are used to set the 8-bit slave address. A
match in the slave address serial data stream must be made
with the address input (A1–A0) in order to initiate
communication with the X9111.
9
8
V
SS
WP
CHIP SELECT (CS)
When CS is HIGH, the X9111 is deselected and the SO pin is at
high impedance, and (unless an internal write cycle is underway)
the device will be in the standby state. CS LOW enables the
X9111, placing it in the active power mode. It should be noted
that after a power-up, a HIGH to LOW transition on CS is required
prior to the start of any operation.
Pin Descriptions
PIN
(TSSOP)
SYMBOL
SO
FUNCTION
1
2
Serial Data Output
A0
Device Address
HARDWARE WRITE PROTECT INPUT (WP)
3
NC
No Connect
The WP pin when LOW prevents nonvolatile writes to the Data
Registers.
4
CS
Chip Select
5
SCK
SI
Serial Clock
Potentiometer Pins
6
Serial Data Input
7
V
System Ground
R , R
SS
H
L
The R and R pins are equivalent to the terminal connections on a
mechanical potentiometer.
8
WP
A1
Hardware Write Protect
Device Address
H
L
9
R
W
10
11
12
13
14
HOLD
Device Select. Pause the Serial Bus
Wiper Terminal of the Potentiometer
High Terminal of the Potentiometer
Low Terminal of the Potentiometer
System Supply Voltage
The wiper pin is equivalent to the wiper terminal of a mechanical
potentiometer.
R
W
R
H
Bias Supply Pins
R
L
V
SYSTEM SUPPLY VOLTAGE (V ) AND SUPPLY
CC
GROUND (V
CC
)
SS
Bus Interface Pins
The V pin is the system supply voltage. The V pin is the
CC
SS
system ground.
SERIAL OUTPUT (SO)
SO is a serial data output pin. During a read cycle, data is shifted
out on this pin. Data is clocked out by the falling edge of the serial
clock.
Other Pins
NO CONNECT (NC)
Pin should be left open. This pin is used for Intersil
manufacturing and test purposes.
SERIAL INPUT (SI)
SI is the serial data input pin. All opcodes, byte addresses and data
to be written to the pots and pot registers are input on this pin.
Data is latched by the rising edge of the serial clock.
SERIAL CLOCK (SCK)
The SCK input is used to clock data into and out of the X9111.
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X9111
SERIAL DATA PATH
SERIAL
BUS
INPUT
R
H
FROM INTERFACE
CIRCUITRY
C
O
U
N
T
REGISTER 0
(DR0)
REGISTER 1
(DR1)
PARALLEL
BUS
10
10
E
R
INPUT
REGISTER 2
(DR2)
REGISTER 3
(DR3)
WIPER
D
E
C
O
D
E
COUNTER
REGISTER
(WCR)
If WCR = 000[HEX] then R = R
W
L
If WCR = 3FF[HEX] then R = R
W
H
R
R
L
W
FIGURE 3. DETAILED POTENTIOMETER BLOCK DIAGRAM
1. It may be written directly by the host via the write Wiper
Counter Register instruction (serial load).
Principles of Operation
Device Description
2. It may be written indirectly by transferring the contents of one
of four associated Data Registers via the XFR Data Register.
SERIAL INTERFACE
3. It is loaded with the contents of its Data Register zero (DR0)
upon power-up.
The X9111 supports the SPI interface hardware conventions. The
device is accessed via the SI input with data clocked-in on the rising
SCK. CS must be LOW and the HOLD and WP pins must be HIGH
during the entire operation.
The Wiper Counter Register is a volatile register, meaning its
contents are lost when the X9111 is powered-down. Although the
register is automatically loaded with the value in R0 upon
power-up, this may be different from the value present at power-
down. Power-up guidelines are recommended to ensure proper
loadings of the R0 value into the WCR.
The SO and SI pins can be connected together, since they have three
state outputs. This can help to reduce system pin count.
ARRAY DESCRIPTION
DATA REGISTERS (DR3 TO DR0)
The X9111 is comprised of a resistor array (see Figure 3). The
array contains the equivalent of 1,023 discrete resistive
segments that are connected in series. The physical ends of each
array are equivalent to the fixed terminals of a mechanical
The potentiometer has four 10-bit nonvolatile Data Registers.
These can be read or written directly by the host. Data can also
be transferred between any of the four Data Registers and the
Wiper Counter Register. All operations changing data in one of
the Data Registers is a nonvolatile operation and will take a
maximum of 10ms.
potentiometer (R and R inputs).
H
L
At both ends of each array and between each resistor segment is
a CMOS switch connected to the wiper (R ) output. Within the
individual array, only one switch may be turned on at a time.
W
If the application does not require storage of multiple settings for
the potentiometer, the Data Registers can be used as regular
memory locations for system parameters or user preference
data.
These switches are controlled by a Wiper Counter Register
(WCR). The 10-bits of the WCR (WCR[9:0]) are decoded to select,
and enable, one of 1024 switches.
A DR[9:0] is used to store one of the 1024 wiper positions (0
~1023). See Table 2 on page 5
WIPER COUNTER REGISTER (WCR)
The X9111 contains a Wiper Counter Register (see Table 1 on
page 5) for the XDCP potentiometer. The WCR is equivalent to a
serial-in, parallel-out register/counter with its outputs decoded to
select one of 1024 switches along its resistor array. The contents
of the WCR can be altered in one of three ways:
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X9111
The A1–A0 bits in the ID byte are the internal slave address. The
STATUS REGISTER (SR)
physical device address is defined by the state of the A1–A0
input pins. The slave address is externally specified by the user.
The X9111 compares the serial data stream with the address
input state; a successful compare of the address bits is required
for the X9111 to successfully continue the command sequence.
Only the device whose slave address matches the incoming
device address sent by the master executes the instruction. The
A1–A0 inputs can be actively driven by CMOS input signals or
This 1-bit status register is used to store the system status (see
Table 4).
WIP: Write In Progress status bit, read only.
• When WIP = 1, indicates that high-voltage write cycle is in
progress.
• When WIP = 0, indicates that no high-voltage write cycle is in
progress.
tied to V or V . The R/W bit is used to set the device to either
CC SS
read or write mode.
Device Instructions
Instruction Byte and Register Selection
The next byte sent to the X9111 contains the instruction and
register pointer information. The three most significant bits are
used provide the instruction opcode (I[2:0]). The RB and RA bits
point to one of the four registers. The format is shown in Table 5.
Identification Byte (ID and A)
The first byte sent to the X9111 from the host, following a CS
going HIGH to LOW, is called the Identification Byte. The most
significant four bits of the slave address are a device type
identifier. The ID[3:0] bits is the device ID for the X9111; this is
fixed as 0101[B] (refer to Table 5 on page 6).
TABLE 1. WIPER LATCH, WL (10-BIT), WCR9–WCR0: USED TO STORE THE CURRENT WIPER POSITION (VOLATILE, V)
WCR9
V
WCR8
V
WCR7
V
WCR6
V
WCR5
V
WCR4
V
WCR3
V
WCR2
V
WCR1
V
WCR0
V
(MSB)
(LSB)
TABLE 2. DATA REGISTER, DR (10-BIT), BIT 9–BIT 0: USED TO STORE WIPER POSITIONS OR DATA (NONVOLATILE, NV)
BIT 9
NV
BIT 8
NV
BIT 7
NV
BIT 6
NV
BIT 5
NV
BIT 4
NV
BIT 3
NV
BIT 2
NV
BIT 1
NV
BIT 0
NV
MSB
LSB
TABLE 3. STATUS REGISTER, SR (1-BIT)
WIP
(LSB)
TABLE 4. IDENTIFICATION BYTE FORMAT
INTERNAL SLAVE
ADDRESS
DEVICE TYPE
IDENTIFIER
READ OR
WRITE BIT
ID3
0
ID2
1
ID1
0
ID0
1
0
A1
A0
R/W
(MSB)
(LSB)
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X9111
TABLE 5. INSTRUCTION BYTE FORMAT
REGISTER
SELECTION
INSTRUCTION
OPCODE
I2
I1
I0
0
RB
RA
0
0
(MSB)
(LSB)
RB
RA
REGISTER
0
0
1
1
0
1
0
1
DR0
DR1
DR2
DR3
Five of the seven instructions are four bytes in length. These
instructions are:
Write in Process (WIP bit)
The contents of the Data Registers are saved to nonvolatile
memory when the CS pin goes from LOW to HIGH after a
complete write sequence is received by the device. The progress
of this internal write operation can be monitored by a Write In
Process bit (WIP). The WIP bit is read with a Read Status
command (see Figure 6 on page 7).
• Read Wiper Counter Register – read the current wiper position
of the selected pot.
• Write Wiper Counter Register – change current wiper position
of the selected pot.
• Read Data Register – read the contents of the selected data
register.
Power-Up and Power-Down Requirements
There are no restrictions on the power-up condition of V and
the voltages applied to the potentiometer pins provided that the
• Write Data Register – write a new value to the selected data
register.
CC
V
is always more positive than or equal to the voltages at R ,
CC
R , and R , i.e., V ≥ R , R , R . There are no restrictions on
H
• Read Status – This command returns the contents of the WIP
bit, which indicates if the internal write cycle is in progress.
L
W
CC
H
L
W
the power-down condition. However, the datasheet parameters
The basic sequence of the four byte instructions is illustrated in
Figure 5 on page 7. These four-byte instructions exchange data
between the WCR and one of the Data Registers. A transfer from
a Data Register to a WCR is essentially a write to a static RAM,
with the static RAM controlling the wiper position. The response
of the wiper to this action will be delayed by tWRL. A transfer
from the WCR (current wiper position), to a Data Register is a
write to nonvolatile memory and takes a minimum of tWR to
complete. The transfer can occur between the potentiometer and
one of its associated registers. The Read Status Register
instruction is the only unique format (see Figure 6 on page 7).
for the DCP do not apply until 1 millisecond after V reaches its
CC
final value.
Two instructions require a two-byte sequence to complete (see
Figure 4 on page 7). These instructions transfer data between
the host and the X9111, either between the host and one of the
Data Registers, or directly between the host and the Wiper
Counter Register. These instructions are:
• XFR Data Register to Wiper Counter Register – This transfers
the contents of one specified Data Register to the associated
Wiper Counter Register.
• XFR Wiper Counter Register to Data Register – This transfers
the contents of the specified Wiper Counter Register to the
specified associated Data Register.
See Instruction format for more details.
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X9111
CS
SCK
0
SI
0
0
0
0
0
0
1
0
1
I2
ID3 ID2 ID1 ID0
DEVICE ID
A1 A0 R/W
I1
I0
RB RA
0
INTERNAL
ADDRESS
INSTRUCTION
OPCODE
REGISTER
ADDRESS
FIGURE 4. TWO-BYTE INSTRUCTION SEQUENCE
CS
SCK
SI
0
0
1
0
1
0
0
X
X
0
X
0
X
X
X
X
X
A1
W W
W
C
R
7
W
C
R
6
W W W W W
W
C
R
0
A0
ID3 ID2 ID1 ID0 0
R/W I2 I1
0 RB RA 0 0
I0
C
R
9
C
R
8
C
R
5
C
R
4
C
R
3
C
R
2
C
R
1
INTERNAL INSTRUCTION REGISTER
ADDRESS
DEVICE ID
ADDRESS
OPCODE
WIPER
POSITION
FIGURE 5. FOUR-BYTE INSTRUCTION SEQUENCE (WRITE OR READ FOR WCR OR DATA REGISTERS)
CS
SCK
SI
1
X
0
1
0
1
0
0
X
X
0
0
0
0
0
0
0
0
X
0
X
X
X
X
0
0
X
X
I2 I1
I0
ID3 ID2ID1ID0
DEVICE ID
A1 A0 R/W
0 RB RA 0
WIP
INTERNAL
ADDRESS
INSTRUCTION REGISTER
ADDRESS
STATUS
BIT
OPCODE
FIGURE 6. FOUR-BYTE INSTRUCTION SEQUENCE (READ STATUS REGISTERS)
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X9111
TABLE 6. INSTRUCTION SET
INSTRUCTION SET
INSTRUCTION
R/W
1
I
I
I
1
0
0
RB
0
RA
0
0
0
0
0
OPERATION
3
2
Read Wiper Counter
Register
1
1
1
1
1
0
0
0
1
1
0
1
1
0
0
Read the contents of the Wiper Counter Register
Write Wiper Counter
Register
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Write new value to the Wiper Counter Register
Read Data Register
1/0
1/0
1/0
1/0
1/0
1/0
Read the contents of the Data Register pointed
to RB-RA
Write Data Register
Write new value to the Data Register pointed to
RB-RA
XFR Data Register to
Wiper Counter Register
Transfer the contents of the Data Register
pointed to by RB-RA to the Wiper Counter
Register
XFR Wiper Counter
Register to Data Register
0
1
1
0
1
1
1
0
0
0
1/0
0
1/0
0
0
0
0
1
Transfer the contents of the Wiper Counter
Register to the Data Register pointed to by RB-RA
Read Status (WIP Bit)
Read the status of the internal write cycle, by
checking the WIP bit (read status register).
NOTE: 1/0 = data is one or zero
Instruction Format
Read Wiper Counter Register (WCR)
CS
Falling
Edge
Device Type
Identifier
Device
Addresses
Instruction
Opcode
Register
Addresses
Wiper Position
(Sent by X9111 on SO)
Wiper Position
(sent by X9111 on SO)
CS
Rising
Edge
0
1
0
1
0
A1 A0
1
0
0
0
0
0
0
0
X
X
X
X
X
X
W
C
W
C
W
C
W
C
W
C
W
C
W
C
W
C
W
C
W
C
R
9
R
8
R
7
R
6
R
5
R
4
R
3
R
2
R
1
R
0
Write Wiper Counter Register (WCR)
CS
Falling
Edge
Device Type
Identifier
Device
Addresses
Instruction
Opcode
Register
Addresses
Wiper Position
(Sent by Master on SI)
Wiper Position
(Sent by Master on SI)
CS
Rising
Edge
0
1
0
1
0
A1 A0
1
0
1
0
0
0
0
0
X
X
X
X
X
X
W
C
W
C
W
C
W
C
W
C
W
C
W
C
W
C
W
C
W
C
R
9
R
8
R
7
R
6
R
5
R
4
R
3
R
2
R
1
R
0
Read Data Register (DR)
CS
Falling
Edge
Device
Type
Identifier
Device
Addresses
Instruction
Opcode
Register
Addresses
Wiper Position
(Sent by X9111 on SO)
Wiper Position
(sent by X9111 on SO)
CS
Rising
Edge
0
1
0
1
0
A1 A0
1
0
1
0
RB RA
0
0
X
X
X
X
X
X
W
C
R
9
W
W
W
W
C
R
5
W
C
R
4
W
C
R
3
W
C
R
2
W
C
R
1
W
C
R
0
C
R
8
C
R
7
C
R
6
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X9111
Write Data Register (DR)
CS
Falling
Edge
Device Type
Identifier
Device
Addresses
Instruction
Opcode
Register
Addresses
Wiper Position or Data
(Sent by Master on SI)
Wiper Position or Data
(Sent by Master on SI)
CS
Rising
Edge
0
1
0
1
0
A1 A0
1
1
0
0
RB RA
0
0
X
X
X
X
X
X
W
C
W W
W
C
W
C
W
C
W
C
W
C
W
C
W
C
R
0
C
R
8
C
R
7
R
9
R
6
R
5
R
4
R
3
R
2
R
1
Transfer Data Register (DR) to Wiper Counter Register (WCR)
CS
Falling
Edge
Device Type
Identifier
Device
Addresses
Instruction
Opcode
Register
Addresses
CS
Rising
Edge
0
1
0
1
0
A1 A0
1
1
0
0
RB RA
0
0
Transfer Wiper Counter Register (WCR) to Data Register (DR)
CS
Falling
Edge
Device Type
Identifier
Device
Addresses
Instruction
Opcode
Register Addresses
CS
Rising
Edge
HIGH-VOLTAGE
WRITE CYCLE
0
1
0
1
0
A1 A0
1
1
1
0
RB
RA
0
0
Read Status Register (SR)
CS
Falling
Edge
Device Type
Identifier
Device
Addresses
Instruction
Opcode
Register
Addresses
Status Data
(Sent by Slave on SO)
Status Data
(Sent by Slave on SO)
CS
Rising
Edge
0
1
0
1
0
A1 A0
0
1
0
0
0
0
0
1
X
X
X
X
X
X
X
X
0
0
0
0
0
0
0
WIP
NOTES:
4. “A0 and A1”: stand for the device address sent by the master.
5. WCRx refers to wiper position data in the Wiper Counter Register.
6. “X”: Don’t Care.
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X9111
Absolute Maximum Ratings
Recommended Operating Conditions
Temperature under bias . . . . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +135°C
Storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Voltage on SCK any address input
Temperature Range
Commercial. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C
Industrial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C
with respect to V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-1V to +7V
Supply Voltage (V ) Limits
SS
CC
V = | (VH–VL) |. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to V
CC
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see TB493
X9111 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5V ±10%
X9111-2.7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V to 5.5V
I
(10s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±6mA
W
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
Analog Characteristics Over recommended industrial operation conditions unless otherwise stated.
SYMBOL
R
PARAMETER
End to End Resistance
TEST CONDITIONS
MIN
TYP
100
MAX
UNIT
kΩ
%
TOTAL
End to End Resistance Tolerance
Power Rating
±20
50
+25°C, each pot
mW
mA
Ω
I
Wiper Current
±3
W
R
Wiper Resistance
Wiper Current = ±50µA,
= 5V
40
110
W
V
CC
Wiper Current = ±50µA,
150
300
Ω
V
V
= 3V
= 0V
CC
V
Voltage on any R or R Pin
V
V
CC
V
dBV
TERM
H
L
SS
SS
Noise
Ref: 1V
-120
1.6
Resolution
%
Absolute Linearity (Note 7)
Relative Linearity (Note 8)
Temperature Coefficient of R
R
-R
, where n = 8
(Note 10)
±1
MI (Note 9)
w(n)(actual) w(n)(expected)
to 1006
R
-R
w(n)(actual) w(n)(expected)
±1.5
±2.0
±0.5
MI (Note 9)
MI (Note 9)
R
1006
-[R
+ MI], where m = 8 to
w(m + 1)
w(m)
R
-[R
+ MI] (Note 10)
±0.5
±1.0
20
MI (Note 9)
ppm/°C
ppm/°C
pF
w(m + 1)
w(m)
±300
TOTAL
Ratiometric Temperature Coefficient
Potentiometer Capacitancies
C /C /C
See Macro model
10/10/25
H
L
W
NOTES:
7. Absolute linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used as a
potentiometer.
8. Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a
potentiometer. It is a measure of the error in step size.
9. MI = RTOT/1023 or (R – R )/1023, single pot
H
L
10. n = 0, 1, 2, …,1023; m =0, 1, 2, …, 1022.
11. ESD Rating on RH, RL, RW pins is 1.5kV (HBM, 1.0µA leakage maximum), ESD rating on all other pins is 2.0kV.
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X9111
DC Operating Characteristics Over the recommended operating conditions unless otherwise specified.
SYMBOL
PARAMETER
TEST CONDITIONS
MIN.
TYP.
MAX.
400
UNIT
µA
I
V
V
V
Supply Current (Active)
f
= 2.5 MHz, SO = Open, V = 5.5V
CC1
CC
CC
CC
SCK
Other inputs = V
CC
SS
I
Supply Current (Nonvolatile Write) f
= 2.5MHz, SO = Open, V = 5.5V
1
5
mA
CC2
SCK
Other inputs = V
CC
SS
I
I
Current (Standby)
SCK = SI = V , Address = V , CS = V = 5.5V
3
µA
µA
µA
V
SB
SS SS CC
I
Input Leakage Current
Output Leakage Current
Input HIGH Voltage
Input LOW Voltage
V
= V to V
SS CC
10
10
LI
IN
V
= V to V
SS CC
LO
OUT
V
V
x 0.7
V
+ 1
IH
CC
CC
V
-1
V
x 0.3
V
IL
CC
V
V
V
Output LOW Voltage
Output LOW Voltage
Output LOW Voltage
I
I
I
= 3mA
0.4
V
OL
OL
OL
OL
OH
OH
= -1mA, V ≥+3V
CC
V
V
- 0.8
V
CC
= -0.4mA, V ≤ +3V
- 0.4
V
CC
CC
Endurance And Data Retention
PARAMETER
Minimum Endurance
Data Retention
MIN
100,000
100
UNITS
Data changes per bit per register
Years
Capacitance
SYMBOL
TEST
TEST CONDITIONS
MAX
8
UNIT
C
(Note 12) Input/Output Capacitance (SI)
V
V
= 0V
= 0V
pF
pF
pF
IN/OUT
OUT
C
(Note 12) Output Capacitance (SO)
8
OUT
OUT
C
(Note 12)
Input Capacitance (A0, CS, WP, HOLD, and SCK)
V
= 0V
IN
6
IN
Power-Up Timing
SYMBOL
PARAMETER
MIN
0.2
MAX
50
1
UNIT
t V (Note 12)
V Power-Up Rate
CC
V/ms
ms
r
CC
t
(Note 13)
(Note 13)
Power-Up to Initiation of Read Operation
Power-Up to Initiation of Write Operation
PUR
t
50
ms
PUW
NOTES:
12. This parameter is not 100% tested.
13. t and t are the delays required from the time the (last) power supply (V -) is stable until the specific instruction can be issued. These
PUR PUW CC
parameters are not 100% tested.
AC Test Conditions
Input pulse levels
V
x 0.1 to V x 0.9
CC
CC
Input rise and fall times
Input and output timing level
10ns
V
x 0.5
CC
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X9111
Equivalent AC Load Circuit
3V
5V
SPICE MACROMODEL
1462Ω
1382Ω
R
TOTAL
C
R
L
R
H
SO pin
SO pin
C
C
L
W
L
10pF
10pF
1217Ω
2714Ω
100pF
100pF
25pF
R
W
AC Timing
SYMBOL
PARAMETER
MIN
MAX
UNIT
f
SSI/SPI Clock Frequency
SSI/SPI Clock Cycle Time
SSI/SPI Clock High Time
SSI/SPI Clock Low Time
Lead Time
2.5
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SCK
t
400
150
150
150
150
50
CYC
t
WH
t
WL
t
LEAD
t
Lag Time
LAG
t
SI, SCK, HOLD and CS Input Set-Up Time
SI, SCK, HOLD and CS Input Hold Time
SI, SCK, HOLD and CS Input Rise Time
SI, SCK, HOLD and CS Input Fall Time
SO Output Disable Time
SO Output Valid Time
SU
t
50
H
t
50
50
RI
t
FI
t
0
0
500
100
DIS
t
V
t
SO Output Hold Time
HO
RO
t
SO Output Rise Time
50
50
t
SO Output Fall Time
FO
t
HOLD Time
400
50
HOLD
t
HOLD Set-Up Time
HSU
t
HOLD Hold Time
50
HH
t
HOLD Low to Output in High-Z
HOLD High to Output in Low-Z
100
100
20
HZ
t
LZ
T
Noise Suppression Time Constant at
SI, SCK, HOLD and CS Inputs
I
t
CS Deselect Time
100
0
ns
ns
ns
CS
t
WP, A0, A1 Set-Up Time
WP, A0, A1 Hold Time
WPASU
t
0
WPAH
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12
X9111
High-Voltage Write Cycle Timing
SYMBOL
PARAMETER
TYP
5
MAX
10
UNIT
ms
t
High-Voltage Write Cycle Time (Store Instructions)
WR
XDCP Timing
SYMBOL
PARAMETER
MIN
5
MAX
10
UNIT
µs
t
Wiper Response Time after the Third (Last) Power Supply is Stable
Wiper Response Time after Instruction Issued (All Load Instructions)
WRPO
t
5
10
µs
WRL
Symbol Table
WAVEFORM
INPUTS
OUTPUTS
Must be
steady
Will be
steady
May change
from Low to
High
Will change
from Low to
High
May change
from High to
Low
Will change
from High to
Low
Don’t Care:
Changes
Allowed
Changing:
State Not
Known
N/A
Center Line
is High
Impedance
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X9111
Timing Diagrams
t
CS
CS
t
t
t
LAG
LEAD
CYC
SCK
...
t
t
t
RI
FI
t
t
t
WH
WL
SU
H
...
MSB
LSB
SI
High Impedance
SO
FIGURE 7. INPUT TIMING
CS
SCK
SO
...
...
t
t
t
DIS
V
HO
MSB
LSB
ADDR
SI
FIGURE 8. OUTPUT TIMING
CS
SCK
SO
t
t
HH
HSU
...
t
t
RO
FO
t
t
LZ
HZ
SI
t
HOLD
HOLD
FIGURE 9. HOLD TIMING
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X9111
Timing Diagrams(Continued)
CS
SCK
...
...
t
WRL
MSB
LSB
SI
R
W
High Impedance
SO
FIGURE 10. XDCP TIMING (FOR ALL LOAD INSTRUCTIONS)
(Any Instruction)
CS
t
t
WPAH
WPASU
WP
A0
A1
FIGURE 11. WRITE PROTECT AND DEVICE ADDRESS PINS TIMING
Applications information
Basic Configurations of Electronic Potentiometers
+V
R
V
R
RW
I
FIGURE 13. TWO-TERMINAL VARIABLE RESISTOR; VARIABLE
CURRENT
FIGURE 12. THREE-TERMINAL POTENTIOMETER; VARIABLE VOLTAGE
DIVIDER
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X9111
Application Circuits
V
+
–
S
V
V (REG)
O
317
V
IN
O
R
1
R
2
I
adj
R
R
1
2
V
(REG) = 1.25V (1+R /R )+I
R
adj 2
V
= (1+R /R )V
2 1 S
O
2
1
O
FIGURE 15. VOLTAGE REGULATOR
FIGURE 14. NONINVERTING AMPLIFIER
R
R
2
1
V
V
–
S
S
V
O
100kΩ
+
–
+
V
O
TL072
R
R
10kΩ
10kΩ
1
2
10kΩ
V
= {R /(R +R )} V (max)
1 1 2 O
UL
R
= {R /(R +R )} V (min)
LL
1 1 2 O
+12V
-12V
FIGURE 16. OFFSET VOLTAGE ADJUSTMENT
FIGURE 17. COMPARATOR WITH HYSTERISIS
C
V
+
–
S
V
R
O
R
R
2
1
3
–
+
R
V
O
V
S
R
2
R
4
R
= R = R = R = 10kΩ
2 3 4
1
R
1
GO = 1 + R /R
2
fc = 1/(2RC)
1
V
= G V
S
O
-1/2 ≤G ≤+1/2
FIGURE 19. FILTER
FIGURE 18. ATTENUATOR
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X9111
Application Circuits (Continued)
R
2
C
1
R
R
1
2
V
+
–
S
V
S
–
+
R
R
1
3
V
O
Z
IN
V
= G V
S
O
G = - R /R
2
1
Z
= R + s R (R + R ) C = R + s Leq
2 2 1 3 1 2
IN
(R + R ) >> R
1
3
2
FIGURE 20. INVERTING AMPLIFIER
FIGURE 21. EQUIVALENT L-R CIRCUIT
R
R
1
2
–
+
–
+
R
R
}
}
A
B
FREQUENCY R , R , C
1
2
B
AMPLITUDER , R
A
FIGURE 22. FUNCTION GENERATOR
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X9111
Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted.
Please visit our website to make sure you have the latest revision.
DATE
REVISION
FN8159.5
CHANGE
October 13, 2016
Updated entire datasheet applying Intersil’s new standards.
Updated the Ordering Information table on page 2.
Updated Notes 1 and 2. Added Note 3.
In “AC Timing” on page 12, changed f
maximum specification from “2.0” to “2.5”.
SCK
Added Revision History and About Intersil sections.
Updated Package Outline Drawing M14.173 to the latest revision changes are as follows:
-Updated drawing to remove table and added land pattern
About Intersil
Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products
address some of the largest markets within the industrial and infrastructure, mobile computing, and high-end consumer markets.
For the most updated datasheet, application notes, related documentation, and related parts, see the respective product information
page found at www.intersil.com.
You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask.
Reliability reports are also available from our website at www.intersil.com/support.
For additional products, see www.intersil.com/en/products.html
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
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X9111
For the most recent package outline drawing, see M14.173.
Package Outline Drawing
M14.173
14 LEAD THIN SHRINK SMALL OUTLINE PACKAGE (TSSOP)
Rev 3, 10/09
A
1
3
5.00 ±0.10
SEE
DETAIL "X"
14
8
6.40
PIN #1
I.D. MARK
4.40 ±0.10
2
3
1
7
0.20 C B A
B
0.65
0.09-0.20
TOP VIEW
END VIEW
1.00 REF
0.05
H
C
0.90 +0.15/-0.10
1.20 MAX
SEATING
PLANE
GAUGE
PLANE
0.25
5
0.25 +0.05/-0.06
0.10 CBA
0°-8°
0.60 ±0.15
0.05 MIN
0.15 MAX
0.10 C
SIDE VIEW
DETAIL "X"
(1.45)
NOTES:
1. Dimension does not include mold flash, protrusions or gate burrs.
Mold flash, protrusions or gate burrs shall not exceed 0.15 per side.
2. Dimension does not include interlead flash or protrusion. Interlead
flash or protrusion shall not exceed 0.25 per side.
(5.65)
3. Dimensions are measured at datum plane H.
4. Dimensioning and tolerancing per ASME Y14.5M-1994.
5. Dimension does not include dambar protrusion. Allowable protrusion
shall be 0.80mm total in excess of dimension at maximum material
condition. Minimum space between protrusion and adjacent lead is 0.07mm.
6. Dimension in ( ) are for reference only.
(0.65 TYP)
(0.35 TYP)
7. Conforms to JEDEC MO-153, variation AB-1.
TYPICAL RECOMMENDED LAND PATTERN
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19
相关型号：
X9116WM8-2.7T1
Digital Potentiometer, 1 Func, 10000ohm, Increment/decrement Control Interface, 16 Positions, PDSO8, MSOP-8
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X9116WM8-2.7T1C7975
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