X9251UV24Z-2.7T1 [RENESAS]
QUAD 50K DIGITAL POTENTIOMETER, INCREMENT/DECREMENT CONTROL INTERFACE, 256 POSITIONS, PDSO24, 4.40 MM, ROHS COMPLIANT, TSSOP-24;
| 型号： | X9251UV24Z-2.7T1 |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | QUAD 50K DIGITAL POTENTIOMETER, INCREMENT/DECREMENT CONTROL INTERFACE, 256 POSITIONS, PDSO24, 4.40 MM, ROHS COMPLIANT, TSSOP-24 光电二极管 |
| 文件： | 总20页 (文件大小：331K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
X9251
®
Single Supply/Low Power/256-Tap/SPI Bus
Data Sheet
April 13, 2007
FN8166.5
Quad Digitally-Controlled (XDCP™)
Potentiometer
Features
• Four potentiometers in one package
The X9251 integrates four digitally controlled potentio-
meters (XDCP) on a monolithic CMOS integrated circuit.
• 256 resistor taps–0.4% resolution
• SPI Serial Interface for write, read, and transfer operations
of the potentiometer
The digitally controlled potentiometers are imple-mented
with a combination of resistor elements and CMOS switches.
The position of the wipers are controlled by the user through
the SPI bus interface. Each potentiometer has associated
with it a volatile Wiper Counter Register (WCR) and four
non-volatile Data Registers that can be directly written to and
read by the user. The content of the WCR controls the
position of the wiper. At power-up, the device recalls the
content of the default Data Registers of each DCP (DR00,
DR10, DR20, and DR30) to the corresponding WCR.
• Wiper resistance: 100Ω typical @ V
CC
= 5V
• 4 Non-volatile data registers for each
potentiometer
• Non-volatile storage of multiple wiper positions
• Standby current <5µA max
• V : 2.7V to 5.5V Operation
CC
• 50kΩ, 100kΩ versions of total resistance
• 100 year data retention
The XDCP can be used as a three-terminal potentiometer or
as a two terminal variable resistor in a wide variety of
applications including control, parameter adjustments, and
signal processing.
• Single supply version of X9250
• Endurance: 100,000 data changes per bit per register
• 24 Ld SOIC, 24 Ld TSSOP
• Low power CMOS
• Pb-free plus anneal available (RoHS compliant)
Functional Diagram
R
R
H3
R
R
H2
V
H1
H0
CC
HOLD
DCP1
DCP3
DCP2
DCP0
WCR1
DR10
DR11
DR12
DR13
WCR3
DR30
DR31
DR32
DR33
WCR2
DR20
DR21
DR22
DR23
WCR0
DR00
DR01
DR02
DR03
A1
A0
SO
SI
SPI
Interface
POWER UP,
INTERFACE
CONTROL
AND
STATUS
SCK
CS
V
R
R
L3
R
SS
R
R
R
W3
R
WP
R
W0
L1
L2
L0
W1
W2
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
XDCP is a trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005-2007. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
X9251
Ordering Information
POTENTIOMENTER
ORGANIZATION
(kΩ)
PART
MARKING
V
LIMITS
(V)
TEMP RANGE
(°C)
PKG.
DWG. #
CC
PART NUMBER
X9251US24
PACKAGE
X9251US
5 ±10%
50
0 to +70
0 to +70
24 Ld SOIC (300 mil)
M24.3
X9251US24Z (Note)
X9251UV24
X9251US Z
X9251UV
24 Ld SOIC (300 mil) (Pb-free) M24.3
0 to +70
24 Ld TSSOP (4.4mm)
MDP0044
X9251UV24Z (Note)
X9251TS24
X9251UV Z
X9251TS
0 to +70
24 Ld TSSOP (4.4mm) (Pb-free) MDP0044
100
0 to +70
24 Ld SOIC (300 mil)
24 Ld SOIC (300 mil) (Pb-free) M24.3
24 Ld SOIC (300 mil) M24.3
24 Ld SOIC (300 mil) (Pb-free) M24.3
M24.3
X9251TS24Z (Note)
X9251TS24I
X9251TS Z
X9251TS I
X9251TS ZI
X9251TV I
X9251TV ZI
X9251US G
0 to +70
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
-40 to +85
0 to +70
X9251TS24IZ (Note)
X9251TV24I
24 Ld TSSOP (4.4mm)
MDP0044
X9251TV24IZ (Note)
X9251US24I-2.7
24 Ld TSSOP (4.4mm) (Pb-free) MDP0044
2.7 to 5.5
50
24 Ld SOIC (300 mil)
M24.3
X9251US24IZ-2.7 (Note) X9251US ZG
X9251UV24-2.7 X9251UV F
X9251UV24Z-2.7 (Note) X9251UV ZF
X9251UV24I-2.7 X9251UV G
X9251UV24IZ-2.7 (Note) X9251UV ZG
X9251TS24-2.7 X9251TS F
X9251TS24Z-2.7 (Note) X9251TS ZF
X9251TV24-2.7 X9251TV F
X9251TV24Z-2.7 (Note) X9251TV ZF
X9251TV24I-2.7 X9251TV G
24 Ld SOIC (300 mil) (Pb-free) M24.3
24 Ld TSSOP (4.4mm)
MDP0044
0 to +70
24 Ld TSSOP (4.4mm) (Pb-free) MDP0044
-40 to +85
-40 to +85
0 to +70
24 Ld TSSOP (4.4mm)
24 Ld TSSOP (4.4mm) (Pb-free) MDP0044
24 Ld SOIC (300 mil) M24.3
24 Ld SOIC (300 mil) (Pb-free) M24.3
MDP0044
100
0 to +70
0 to +70
24 Ld TSSOP (4.4mm)
MDP0044
0 to +70
24 Ld TSSOP (4.4mm) (Pb-free) MDP0044
-40 to +85
-40 to +85
24 Ld TSSOP (4.4mm)
MDP0044
X9251TV24IZ-2.7 (Note) X9251TV ZG
*Add "T1" suffix for tape and reel.
24 Ld TSSOP (4.4mm) (Pb-free) MDP0044
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
FN8166.5
April 13, 2007
2
X9251
Circuit Level Applications
Pinout
X9251
• Vary the gain of a voltage amplifier
(24 LD SOIC/TSSOP)
TOP VIEW
• Provide programmable dc reference voltages for
comparators and detectors
HOLD
SCK
SO
A0
1
24
• Control the volume in audio circuits
2
3
23
22
• Trim out the offset voltage error in a voltage amplifier
circuit
R
R
W3
L2
R
R
H3
4
5
21
20
H2
• Set the output voltage of a voltage regulator
R
R
L3
W2
• Trim the resistance in Wheatstone bridge circuits
NC
NC
6
7
19
18
X9251
V
V
• Control the gain, characteristic frequency and
Q-factor in filter circuits
CC
SS
R
R
8
9
17
16
W1
L0
R
R
H0
H1
• Set the scale factor and zero point in sensor signal
conditioning circuits
R
R
W0
10
15
14
L1
A1
SI
CS
11
12
• Vary the frequency and duty cycle of timer ICs
WP
13
• Vary the dc biasing of a pin diode attenuator in RF circuits
• Provide a control variable (I, V, or R) in feedback
circuits
Pin Assignments
System Level Applications
• Adjust the contrast in LCD displays
PIN
(SOIC)
SYMBOL
FUNCTION
1
2
SO
A0
Serial Data Output for SPI bus
Device Address for SPI bus. (See Note 1)
Wiper Terminal of DCP3
High Terminal of DCP3
• Control the power level of LED transmitters in
communication systems
3
R
• Set and regulate the DC biasing point in an RF power
amplifier in wireless systems
W3
4
R
H3
5
R
Low Terminal of DCP3
• Control the gain in audio and home entertainment systems
L3
7
V
System Supply Voltage
CC
• Provide the variable DC bias for tuners in RF wireless
systems
8
R
Low Terminal of DCP0
L0
H0
W0
9
R
High Terminal of DCP0
• Set the operating points in temperature control
systems
10
11
12
13
14
15
16
17
18
20
21
22
23
24
6, 19
R
Wiper Terminal of DCP0
SPI bus. Chip Select active low input
Hardware Write Protect - active low
Serial Data Input for SPI bus
Device Address for SPI bus. (See Note 1)
Low Terminal of DCP1
CS
WP
SI
• Control the operating point for sensors in industrial
systems
• Trim offset and gain errors in artificial intelligent
systems
A1
R
L1
H1
W1
R
High Terminal of DCP1
R
Wiper Terminal of DCP1
System Ground
V
SS
R
Wiper Terminal of DCP2
High Terminal of DCP2
W2
R
H2
R
Low Terminal of DCP2
L2
SCK
HOLD
NC
Serial Clock for SPI bus
Device select. Pauses the SPI serial bus.
No Connect
NOTE:
1. A0 and A1 device address pins must be tied to a logic level.
FN8166.5
April 13, 2007
3
X9251
Supply Pins
SYSTEM SUPPLY VOLTAGE (V ) AND SUPPLY
Pin Descriptions
Bus Interface Pins
SERIAL OUTPUT (SO)
CC
GROUND (V
)
SS
The V
CC
pin is the system supply voltage. The V pin is
SS
SO is a serial data output pin. During a read cycle, data is
shifted out on this pin. Data is clocked out by the falling edge
of the serial clock.
the system ground.
Other Pins
NO CONNECT
SERIAL INPUT (SI)
No connect pins should be left floating. This pins are
used for Intersil manufacturing and testing purposes.
SI is the serial data input pin. All opcodes, byte addresses
and data to be written to the device registers are input on
this pin. Data is latched by the rising edge of the serial clock.
HARDWARE WRITE PROTECT INPUT (WP)
SERIAL CLOCK (SCK)
The WP pin when LOW prevents non-volatile writes to the
Data Registers.
The SCK input is used to clock data into and out of the
X9251.
Principles of Operation
HOLD (HOLD)
The X9251 is an integrated circuit incorporating four DCPs
and their associated registers and counters, and a serial
interface providing direct communication between a host
and the potentiometers.
HOLD is used in conjunction with the CS pin to select the
device. Once the part is selected and a serial sequence is
underway, HOLD may be used to pause the serial
communication with the controller without resetting the serial
sequence. To pause, HOLD must be brought LOW while
SCK is LOW. To resume communication, HOLD is brought
HIGH, again while SCK is LOW. If the pause feature is not
used, HOLD should be held HIGH at all times.
DCP Description
Each DCP is implemented with a combination of resistor
elements and CMOS switches. The physical ends of each
DCP are equivalent to the fixed terminals of a mechanical
potentiometer (R and R pins). The RW pin is an
intermediate node, equivalent to the wiper terminal of a
mechanical potentiometer.
H
L
DEVICE ADDRESS (A1 AND A0)
The address inputs are used to set the two least significant
bits of the slave address. A match in the slave address serial
data stream must be made with the address input in order to
initiate communication with the X9251. Device pins A1 and
A0 must be tied to a logic level which specifies the internal
address of the device, see Figures 2, 3, 4, 5 and 6.
The position of the wiper terminal within the DCP is
controlled by an 8-bit volatile Wiper Counter Register
(WCR).
CHIP SELECT (CS)
When CS is HIGH, the X9251 is deselected and the SO pin
is at high impedance, and (unless an internal write cycle is
underway) the device is in the standby state. CS LOW
enables the X9251, placing it in the active power mode. It
should be noted that after a power-up, a HIGH to LOW
transition on CS is required prior to the start of any
operation.
Potentiometer Pins
R , R
H
L
The R and R pins are equivalent to the terminal
H
L
connections on a mechanical potentiometer. Since there are
4 potentiometers, there are 4 sets of R and R such that
H
L
R
and R are the terminals of DCP0 and so on.
L0
H0
R
W
The wiper pin are equivalent to the wiper terminal of a
mechanical potentiometer. Since there are 4 potentiometers,
there are 4 sets of R such that R
is the terminals of
W
W0
DCP0 and so on.
FN8166.5
April 13, 2007
4
X9251
One of Four Potentiometers
R
#: 0, 1, 2, or 3
H
SERIAL
BUS
INPUT
SERIAL DATA PATH
FROM INTERFACE
CIRCUITRY
DR#0
DR#2
DR#1
DR#3
8
8
PARALLEL
BUS
INPUT
COUNTER
- - -
DECODE
DCP
CORE
R
W
WIPER
COUNTER
REGISTER
(WCR#)
INC/DEC
LOGIC
IF WCR = 00[H] then R is closet to R
W
L
H
UP/DN
IF WCR = FF[H] then R is closet to R
UP/DN
CLK
W
MODIFIED SCK
R
L
FIGURE 1. DETAILED POTENTIOMETER BLOCK DIAGRAM
Power Up and Down Recommendations
There are no restrictions on the power-up or power-down
conditions of V and the voltages applied to the
Data Registers (DR)
Each of the four DCPs has four 8-bit non-volatile Data
Registers. These can be read or written directly by the host.
Data can also be transferred between any of the four Data
Registers and the associated Wiper Counter Register. All
operations changing data in one of the Data Registers is a
non-volatile operation and takes a maximum of 10ms.
CC
potentiometer pins provided that V
is always more
CC
positive than or equal to V , V , and V (i.e., V
≥ V , V ,
H
L
W
CC
H
L
V ). The V
CC
ramp rate specification is always in effect.
W
Wiper Counter Register (WCR)
If the application does not require storage of multiple
settings for the potentiometer, the Data Registers can be
used as regular memory locations for system parameters or
user preference data.
The X9251 contains four Wiper Counter Registers, one for
each potentiometer. The Wiper Counter Register can be
envisioned as a 8-bit parallel and serial load counter with its
outputs decoded to select one of 256 wiper positions along
its resistor array. The contents of the WCR can be altered in
four ways: it may be written directly by the host via the Write
Wiper Counter Register instruction (serial load); it may be
written indirectly by transferring the contents of one of four
associated data registers via the XFR Data Register
instruction (parallel load); it can be modified one step at a
time by the Increment/Decrement instruction (See
Instruction section for more details). Finally, it is loaded with
the contents of its Data Register zero (DR#0) upon
power-up. (See Figure 1)
Bits [7:0] are used to store one of the 256 wiper positions or
data (0 ~ 255).
Status Register (SR)
This 1-bit Status Register is used to store the system status.
WIP: Write In Progress status bit, read only.
• When WIP = 1, indicates that high-voltage write cycle is in
progress.
• When WIP = 0, indicates that no high-voltage write cycle is
in progress.
The wiper counter register is a volatile register; that is, its
contents are lost when the X9251 is powered-down.
Although the register is automatically loaded with the value
in DR#0 upon power-up, this may be different from the value
present at power-down. Power-up guidelines are
recommended to ensure proper loadings of the DR#0 value
into the WCR#.
FN8166.5
April 13, 2007
5
X9251
TABLE 1. WIPER COUNTER REGISTER, WCR (8-bit), WCR[7:0]: USED TO STORE THE CURRENT WIPER POSITION (VOLATILE)
WCR7
(MSB)
WCR6
WCR5
WCR4
WCR3
WCR2
WCR1
WCR0
(LSB)
TABLE 2. DATA REGISTER, DR (8-bit), DR[7:0]: USED TO STORE WIPER POSITIONS OR DATA (NON-VOLATILE)
Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1
Bit 7
Bit 0
(MSB)
(LSB)
The least significant four bits of the Identification Byte are the
Slave Address bits, AD[3:0]. For the X9251, A3 is 0, A2 is 0,
A1 is the logic value at the input pin A1, and A0 is the logic
value at the input pin A0. Only the device which Slave
Address matches the incoming bits sent by the master
executes the instruction. The A1 and A0 inputs can be actively
Serial Interface
The X9251 supports the SPI interface hardware conventions.
The device is accessed via the SI input with data clocked in,
on the rising SCK. CS must be LOW and the HOLD and WP
pins must be HIGH during the entire operation.
The SO and SI pins can be connected together, since they
have three state outputs. This can help to reduce system pin
count.
driven by CMOS input signals or tied to V
or V .
SS
CC
Instruction Byte
The next byte sent to the X9251 contains the instruction and
register pointer information. The four most significant bits are
used provide the instruction opcode (I[3:0]). The RB and RA
bits point to one of the four Data Registers of each associated
XDCP. The least two significant bits point to one of four Wiper
Counter Registers or DCPs.The format is shown below in
Table 4.
Identification Byte
The first byte sent to the X9251 from the host, following a CS
going HIGH to LOW, is called the Identification Byte. The
most significant four bits of the Identification Byte are a
Device Type Identifier, ID[3:0]. For the X9251, this is fixed as
0101 (refer to Table 3).
TABLE 3. IDENTIFICATION BYTE FORMAT
Device Type
Identifier
Slave Address
ID3
0
ID2
1
ID1
0
ID0
1
A3
0
A2
0
A1
A0
Pin A1
Pin A0
Logic Value
Logic Value
(MSB)
(LSB)
TABLE 4. INSTRUCTION BYTE FORMAT
Register
Selection
Instruction
Opcode
DCP Selection
(WCR Selection)
I3
I2
I1
I0
RB
RA
P1
P0
(LSB)
(MSB)
Data Register Selection
REGISTER
DR#0
RB
0
RA
0
DR#1
0
1
DR#2
1
0
DR#3
1
1
#: 0, 1, 2, or 3
FN8166.5
April 13, 2007
6
X9251
TABLE 5. INSTRUCTION SET
INSTRUCTION SET
INSTRUCTION
I3
I2
I1
I0
RB
RA
P1
P0
OPERATION
Read Wiper Counter Register
1
0
0
1
0
0
1/0
1/0 Read the contents of the Wiper Counter Register
pointed to by P1 - P0
Write Wiper Counter Register
Read Data Register
1
1
1
1
0
0
1
1
1
1
0
0
0
1
0
1
0
0
1/0
1/0
1/0
1/0
1/0 Write new value to the Wiper Counter
Register pointed to by P1 - P0
1/0
1/0
1/0
1/0
1/0
1/0
1/0 Read the contents of the Data Register pointed to
by P1 - P0 and RB - RA
Write Data Register
1/0 Write new value to the Data Register
pointed to by P1 - P0 and RB - RA
XFR Data Register to
Wiper Counter Register
1/0 Transfer the contents of the Data Register pointed to
by P1 - P0 and RB - RA to its
associated Wiper Counter Register
XFR Wiper Counter
Register to Data Register
1
0
1
0
1
0
0
0
1
0
0
1
0
1
0
0
1/0
1/0
1/0
0
1/0
1/0
1/0
0
1/0
0
1/0 Transfer the contents of the Wiper Counter Register
pointed to by P1 - P0 to the Data Register pointed
to by RB - RA
Global XFR Data Registers to
Wiper Counter Registers
0
Transfer the contents of the Data Registers pointed
to by RB - RA of all four pots to their respective
Wiper Counter Registers
Global XFR Wiper Counter
Registers to Data Register
0
0
Transfer the contents of both Wiper Counter
Registers to their respective data Registers pointed
to by RB - RA of all four pots
Increment/Decrement
Wiper Counter Register
1/0
1/0 Enable Increment/decrement of the Control Latch
pointed to by P1 - P0
NOTE: 1/0 = data is one or zero
DRs; or it may occur globally, where the transfer occurs
between all potentiometers and one associated register. The
Read Status Register instruction is the only unique format
(See Figure 5).
Instructions
Four of the nine instructions are three bytes in length. These
instructions are:
• Read Wiper Counter Register – read the current wiper
Four instructions require a two-byte sequence to complete.
These instructions transfer data between the host and the
X9251; either between the host and one of the data registers
or directly between the host and the Wiper Counter Register.
These instructions are:
position of the selected potentiometer,
• Write Wiper Counter Register – change current wiper
position of the selected potentiometer,
• Read Data Register – read the contents of the selected
Data Register,
• XFR Data Register to Wiper Counter Register – This
transfers the contents of one specified Data Register to
the associated Wiper Counter Register.
• Write Data Register – write a new value to the selected
Data Register,
• Read Status – this command returns the contents of the
WIP bit which indicates if the internal write cycle is in
progress.
• XFR Wiper Counter Register to Data Register – This
transfers the contents of the specified Wiper Counter
Register to the specified associated Data Register.
The basic sequence of the three byte instructions is
illustrated in Figure 3. These three-byte instructions
exchange data between the WCR and one of the Data
Registers. A transfer from a Data Register to a WCR is
essentially a write to a static RAM, with the static RAM
controlling the wiper position. The response of the wiper to
• Global XFR Data Register to Wiper Counter
Register – This transfers the contents of all specified Data
Registers to the associated Wiper Counter Registers.
• Global XFR Wiper Counter Register to Data
Register – This transfers the contents of all Wiper
Counter Registers to the specified associated Data
Registers.
this action is delayed by t
. A transfer from the WCR
WRL
(current wiper position), to a Data Register is a write to non-
volatile memory and takes a minimum of t to complete.
WR
The transfer can occur between one of the four
potentiometer’s WCR, and one of its associated registers,
FN8166.5
April 13, 2007
7
X9251
For each SCK clock pulse (t
selected wiper moves one wiper position towards the R
terminal. Similarly, for each SCK clock pulse while SI is
) while SI is HIGH, the
Increment/Decrement Command
HIGH
H
The final command is Increment/Decrement (See Figures 6
and 7). The Increment/Decrement command is different from
the other commands. Once the command is issued and the
X9251 has responded with an Acknowledge, the master can
clock the selected wiper up and/or down in one segment
steps; thereby, providing a fine tuning capability to the host.
LOW, the selected wiper moves one wiper position towards
the R terminal. A detailed illustration of the sequence and
L
timing for this operation are shown. See Instruction format
for more details.
CS
SCK
SI
0
0
0
0
0
1
0
1
A1 A0
ID3 ID2 ID1 ID0
DEVICE ID
RB RA
P0
I3
I2
I1
I0
P1
REGISTER
ADDRESS
INSTRUCTION
OPCODE
DCP/WCR
ADDRESS
INTERNAL
ADDRESS
FIGURE 2. TWO-BYTE INSTRUCTION SEQUENCE
CS
SCK
SI
0
0
0
0
0
1
0
1
ID3 ID2 ID1 ID0
P1
P0
A1 A0
RB RA
INSTRUCTION REGISTER
I3 I2
I0
D7 D6 D5 D4 D3 D2 D1 D0
DATA FOR WCR[7:0] OR DR[7:0]
I1
INTERNAL
ADDRESS
DCP/WCR
ADDRESS
DEVICE ID
ADDRESS
OPCODE
FIGURE 3. THREE-BYTE INSTRUCTION SEQUENCE SPI INTERFACE; WRITE CASE
CS
SCK
SI
0
0
0
0
0
1
0
1
X
X
X
X
X
X
X
X
ID3 ID2 ID1 ID0
DEVICE ID
A1 A0
I1
RB RA P1 P0
I2
I3
I0
DON’T CARE
INTERNAL
ADDRESS
DCP/WCR
ADDRESS
INSTRUCTION REGISTER
OPCODE ADDRESS
S0
D7 D6 D5 D4 D3 D2 D1 D0
WCR[7:0]
OR
DATA REGISTER BIT [7:0]
FIGURE 4. THREE-BYTE INSTRUCTION SEQUENCE SPI INTERFACE, READ CASE
FN8166.5
April 13, 2007
8
X9251
CS
SCK
SI
1
0
0
0
0
0
1
0
1
0
0
0
0
1
0
1
0
0
0
ID3 ID2 ID1 ID0
I3
A1 A0
I2
I1 I0
RB RA
P1 P0
WIP
INTERNAL
ADDRESS
INSTRUCTION
OPCODE
REGISTER
ADDRESS
POT/WCR
ADDRESS
STATUS
BIT
DEVICE ID
FIGURE 5. THREE-BYTE INSTRUCTION SEQUENCE (READ STATUS REGISTER)
CS
SCK
SI
0
0
0
0
0
1
0
1
ID3 ID2 ID1 ID0
DEVICE ID
I2
I3
I0
P1
RB RA P0
A1 A0
I1
I
N
C
I
N
C
D
E
C
I
D
E
C
n
N
C
n
INTERNAL
ADDRESS
INSTRUCTION
OPCODE
POT/WCR
ADDRESS
REGISTER
ADDRESS
1
2
1
FIGURE 6. INCREMENT/DECREMENT INSTRUCTION SEQUENCE
t
WRID
SCK
SI
VOLTAGE OUT
R
W
INC/DEC CMD ISSUED
FIGURE 7. INCREMENT/DECREMENT TIMING SPEC
FN8166.5
April 13, 2007
9
X9251
Instruction Format
Read Wiper Counter Register (WCR)
Device Type
Identifier
Device
Addresses
Instruction
Opcode
WCR
Addresses
Wiper Position
(Sent by X9251 on SO)
CS
Falling
Edge
CS
Rising
Edge
W
C
R
7
W
C
R
6
W
C
R
5
W
C
R
4
W
C
R
3
W
C
R
2
W
C
R
1
W
C
R
0
0
1
0
1
0
0
A1 A0
1
0
0
1
0
0
0
0
Write Wiper Counter Register (WCR)
Device Type
Identifier
Device
Addresses
Instruction
Opcode
WCR
Addresses
Data Byte
(Sent by Host on SI)
CS
Falling
Edge
CS
Rising
Edge
W
C
R
7
W
C
R
6
W
C
R
5
W
C
R
4
W
C
R
3
W
C
R
2
W
C
R
1
W
C
R
0
0
1
0
1
0
0
A1 A0
1
0
1
0
0
0
0
0
Read Data Register (DR)
Device Type
CS
Device
Addresses
Instruction
Opcode
DR and WCR
Addresses
Data Byte
(Sent by X9271 on SO)
CS
Rising
Edge
Identifier
Falling
Edge
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
0
1
0
1
0
0
A1 A0
1
0
1
1
RB RA P1 P0
Write Data Register (DR)
Device Type
Identifier
Device
Addresses
Instruction
Opcode
DR and WCR
Addresses
Data Byte
(Sent by Host on SI)
CS
Falling
Edge
CS
Rising
Edge
HIGH-VOLTAGE
WRITE CYCLE
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
0
1
0
1
0
0
A1 A0
1
1
0
0
RB RA P1 P0
Global Transfer Data Register (DR) to Wiper Counter Register (WCR)
Device Type
Identifier
Device
Addresses
Instruction
Opcode
DR
Addresses
CS
Falling
Edge
CS
Rising
Edge
0
1
0
1
0
0
A1 A0
0
0
0
1
RB RA
0
0
NOTES:
1. “A1 ~ A0”: stands for the device addresses sent by the master.
2. WPx refers to wiper position data in the Counter Register
3. “I”: stands for the increment operation, SI held HIGH during active SCK phase (high).
4. “D”: stands for the decrement operation, SI held LOW during active SCK phase (high).
FN8166.5
April 13, 2007
10
X9251
Global Transfer Wiper Counter Register (WCR) to Data Register (DR)
Device Type
Identifier
Device
Addresses
Instruction
Opcode
DR
Addresses
CS
Falling
Edge
CS
Rising
Edge
HIGH-VOLTAGE
WRITE CYCLE
0
1
0
1
0
0
A1 A0
1
0
0
0
RB RA
0
0
Transfer Wiper Counter Register (WCR) to Data Register (DR)
Device Type
Identifier
Device
Addresses
Instruction
Opcode
DR and WCR
Addresses
CS
Falling
Edge
CS
Rising
Edge
HIGH-VOLTAGE
WRITE CYCLE
0
1
0
1
0
0
A1 A0
1
1
1
0
RB RA
0
0
Transfer Data Register (DR) to Wiper Counter Register (WCR)
Device Type
Identifier
Device
Addresses
Instruction
Opcode
DR and WCR
Addresses
CS
Falling
Edge
CS
Rising
Edge
0
1
0
1
0
0
A1 A0
1
1
0
1
RB RA
0
0
Increment/Decrement Wiper Counter Register (WCR)
Device Type
Identifier
Device
Addresses
Instruction
Opcode
WCR
Addresses
Increment/Decrement
(Sent by Master on SI)
CS
Falling
Edge
CS
Rising
Edge
0
1
0
1
0
0
A1 A0
0
0
1
0
X
X
0
0
I/D I/D
.
.
.
.
I/D I/D
Read Status Register (SR)
Device Type
Identifier
Device
Addresses
Instruction
Opcode
WCR
Addresses
Data Byte
(Sent by X9251 on SO)
CS
Falling
Edge
CS
Rising
Edge
0
1
0
1
0
0
A1 A0
0
1
0
1
0
0
0
1
0
0
0
0
0
0
0
WIP
NOTES:
1. “A1 ~ A0”: stands for the device addresses sent by the master.
2. WPx refers to wiper position data in the Counter Register
3. “I”: stands for the increment operation, SI held HIGH during active SCK phase (high).
4. “D”: stands for the decrement operation, SI held LOW during active SCK phase (high).
FN8166.5
April 13, 2007
11
X9251
Absolute Maximum Ratings
Operating Conditions
Temperature Under Bias . . . . . . . . . . . . . . . . . . . . .-65°C to +135°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Commercial Temperature Range. . . . . . . . . . . . . . . . . 0°C to +70°C
Industrial Temperature Range . . . . . . . . . . . . . . . . . .-40°C to +85°C
Voltage on SCK, CS, SI, SO, WP, HOLD, V
Supply Voltage (V ) Limits (Note 4)
X9251. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5V ±10%
X9251-2.7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V to 5.5V
CC
. . . . . . . . . . . . . . . . . . . . . . . . . . . -1V to +7V
CC
with respect to V
SS
ΔV = | (V - VL) | . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5V
H
Lead Temperature (soldering, 10s) . . . . . . . . . . . . . . . . . . . .+300°C
I
(10s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±6mA
W
Wiper Current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±3mA
Power Rating (each pot) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50mW
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Analog Characteristics (Over the recommended operating conditions unless otherwise specified.)
LIMITS
SYMBOL
PARAMETER
End to End Resistance
TEST CONDITIONS
T version
MIN
TYP
MAX
UNITS
R
R
100
50
kΩ
kΩ
%
TOTAL
End to End Resistance
End to End Resistance Tolerance
Wiper Resistance
U version
TOTAL
±20
300
R
Ω
W
V(V
)
CC
I
I
=
@ V
@ V
= 3V
= 5V
W
W
CC
CC
R
TOTAL
220
Ω
V(V
)
CC
=
R
TOTAL
V
Voltage on any R or R Pin
V
= 0V
V
V
CC
V
TERM
H
L
SS
SS
Noise (Note 6)
Resolution
Ref: 1V
-120
0.4
dBV/√Hz
%
Absolute Linearity (Note 1)
Relative Linearity (Note 2)
Temperature Coefficient of R
R
R
- R
(Note 5)
w(n)(expected)
-1
+1
MI (Note 3)
w(n)(actual)
- [R
] (Note 5)
-0.6
+0.6
MI (Note 3)
w(n + 1)
w(n) + MI
(Note 6)
(Note 6)
±300
±20
ppm/°C
ppm/°C
pF
TOTAL
Ratiometric Temp. Coefficient
Potentiometer Capacitances
C /C /C
W
See Macro model, (Note 6)
10/10/25
H
L
NOTES:
1. Absolute linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used as a
potentiometer.
2. Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a
potentiometer. It is a measure of the error in step size.
3. MI = RTOT/255 or (R - R )/255, single pot
H
L
4. During power up V
> V , V , and V .
H L W
CC
5. n = 0, 1, 2, …,255; m = 0, 1, 2, …, 254.
FN8166.5
April 13, 2007
12
X9251
DC Operating Characteristics (Over the recommended operating conditions unless otherwise specified.)
LIMITS
TYP
SYMBOL
PARAMETER
TEST CONDITIONS
MIN.
MAX
UNITS
I
V
supply current
f
= 2.5 MHz, SO = Open, V
= 6V
400
μA
CC1
CC
SCK
Other Inputs = V
CC
(active)
SS
= 2.5MHz, SO = Open, V
I
V
supply current
f
= 6V
1
5
3
mA
CC2
CC
(non-volatile write)
SCK
Other Inputs = V
CC
SS
I
V
current (standby)
SCK = SI = V , Addr. = V ,
SS
CS = V
μA
SB
CC
SS
= 6V
CC
I
Input leakage current
Output leakage current
Input HIGH voltage
Input LOW voltage
V
V
= V to V
10
10
μA
μA
V
LI
IN
SS
CC
CC
I
= V to V
LO
OUT
SS
V
V
x 0.7
IH
CC
V
V
x 0.3
V
IL
CC
V
Output LOW voltage
Output HIGH voltage
Output HIGH voltage
I
I
I
= 3mA
0.4
V
OL
OH
OH
OL
OH
OH
V
V
= -1mA, V
≥ +3V
V
V
- 0.8
- 0.4
V
CC
CC
CC
= -0.4mA, V
≤ +3V
V
CC
Endurance and Data Retention
PARAMETER
MIN
100,000
100
UNITS
Minimum endurance
Data retention
Data changes per bit per register
years
Capacitance
SYMBOL
TEST
TEST CONDITIONS
TYP
UNITS
C
(Note 6) Input/Output capacitance (SI)
V
V
V
= 0V
= 0V
8
8
6
pF
pF
pF
IN/OUT
OUT
OUT
C
(Note 6)
Output capacitance (SO)
Input capacitance (A0, A1, CS, WP, HOLD, and SCK)
OUT
C
(Note 6)
= 0V
IN
IN
Power-Up Timing
SYMBOL
PARAMETER
MIN
MAX
UNITS
t V
(Note 6)
V Power-up rate
CC
0.2
V/ms
ms
r
CC
t
t
(Note 7)
(Note 7)
Power-up to initiation of read operation
Power-up to initiation of write operation
1
PUR
50
ms
PUW
A.C. Test Conditions
Input Pulse Levels
V
x 0.1 to V
x 0.5
x 0.9
CC
CC
Input rise and fall times
Input and output timing level
10ns
V
CC
NOTES:
6. This parameter is not 100% tested
7. t and t are the delays required from the time the (last) power supply (V -) is stable until the specific instruction can be issued. These
PUR
PUW
CC
parameters are periodically sampled and not 100% tested.
FN8166.5
April 13, 2007
13
X9251
Equivalent A.C. Load Circuit
V
CC
SPICE Macromodel
2kΩ
R
TOTAL
R
R
H
L
SO pin
C
C
W
C
L
L
10pF
2kΩ
10pF
25pF
10pF
R
W
AC TIMING
SYMBOL
PARAMETER
MIN
MAX
UNITS
MHz
ns
f
SPI clock frequency
SPI clock cycle rime
SPI clock high rime
SPI clock low time
Lead time
2
SCK
t
500
200
200
250
250
50
CYC
t
ns
WH
t
ns
WL
t
ns
LEAD
t
Lag time
ns
LAG
t
SI, SCK, HOLD and CS input setup time
SI, SCK, HOLD and CS input hold time
SI, SCK, HOLD and CS input rise time
SI, SCK, HOLD and CS input fall time
SO output disable time
ns
SU
t
50
ns
H
t
2
μs
μs
ns
RI
t
2
FI
t
0
0
250
200
DIS
t
SO output valid time
ns
V
t
SO output hold time
ns
HO
t
(Note 6) SO output rise time
(Note 6) SO output fall time
100
100
ns
RO
t
ns
FO
t
HOLD time
400
100
100
ns
HOLD
t
HOLD setup time
ns
HSU
t
HOLD hold time
ns
HH
t
HOLD low to output in high Z
HOLD high to output in low Z
100
100
10
ns
HZ
t
ns
LZ
T
Noise suppression time constant at SI, SCK, HOLD and CS inputs
ns
I
t
CS deselect time
WP, A0 setup time
WP, A0 hold time
2
0
0
μs
ns
CS
t
WPASU
t
ns
WPAH
High-Voltage Write Cycle Timing
SYMBOL
PARAMETER
TYP
MAX
UNITS
t
High-voltage write cycle time (store instructions)
5
10
ms
WR
XDCP Timing
SYMBOL
PARAMETER
MIN
5
MAX
10
UNITS
μs
t
(Note 6)
Wiper response time after the third (last) power supply is stable
WRPO
t
(Note 6)
Wiper response time after instruction issued (all load instructions)
5
10
μs
WRL
FN8166.5
April 13, 2007
14
X9251
Symbol Table
WAVEFORM
INPUTS
OUTPUTS
Must be
steady
Will be
steady
May change
from Low to
High
Will change
from Low to
High
May change
from High to
Low
Will change
from High to
Low
Don’t Care:
Changes
Allowed
Changing:
State Not
Known
N/A
Center Line
is High
Impedance
Timing Diagrams
Input Timing
t
CS
CS
t
t
t
LAG
LEAD
CYC
SCK
...
t
t
t
t
RI
FI
t
t
WL
SU
WH
H
...
MSB
LSB
SI
HIGH IMPEDANCE
SO
Output Timing
CS
SCK
SO
...
...
t
t
t
DIS
V
HO
MSB
LSB
ADDR
SI
FN8166.5
April 13, 2007
15
X9251
Hold Timing
CS
t
t
HH
HSU
SCK
...
t
RO
t
FO
SO
t
t
LZ
HZ
SI
t
HOLD
HOLD
XDCP Timing (for All Load Instructions)
CS
SCK
...
...
t
WRL
LSB
MSB
SI
VWx
HIGH IMPEDANCE
SO
Write Protect and Device Address Pins Timing
(ANY INSTRUCTION)
CS
t
t
WPAH
WPASU
WP
A0
A1
FN8166.5
April 13, 2007
16
X9251
Applications information
Basic Configurations of Electronic Potentiometers
+V
R
V
R
RW
I
Three terminal
Potentiometer;
Variable voltage divider
Two terminal Variable
Resistor;
Variable current
Application Circuits
NON INVERTING AMPLIFIER
VOLTAGE REGULATOR
V
+
–
S
V
V
V (REG)
O
317
O
IN
R
1
R
2
I
adj
R
R
1
2
V
= (1+R /R )V
V
(REG) = 1.25V (1+R /R )+I
R
adj 2
O
2
1
S
O
2
1
OFFSET VOLTAGE ADJUSTMENT
COMPARATOR WITH HYSTERESIS
R
R
2
1
V
–
+
S
V
V
S
O
100kΩ
–
+
V
O
TL072
R
R
1
2
10kΩ
10kΩ
+12V
V
= {R /(R +R )} V (max)
1 1 2 O
UL
RL = {R /(R +R )} V (min)
10kΩ
-12V
L
1
1
2
O
FN8166.5
April 13, 2007
17
X9251
Application Circuits (continued)
ATTENUATOR
FILTER
C
V
+
–
S
R
V
R
R
2
O
1
–
+
R
V
O
V
S
3
R
2
R
4
R
= R = R = R = 10kΩ
2 3 4
1
R
1
G
= 1 + R /R
2 1
V
= G V
S
O
O
fc = 1/(2πRC)
-1/2 ≤ G ≤ +1/2
INVERTING AMPLIFIER
EQUIVALENT L-R CIRCUIT
R
R
2
1
V
S
R
2
C
1
–
+
V
+
–
S
V
O
R
R
1
Z
IN
V
= G V
S
O
G = - R /R
2
1
3
Z
= R + s R (R + R ) C = R + s Leq
2 2 1 3 1 2
IN
(R + R ) >> R
1
3
2
FUNCTION GENERATOR
C
R
R
1
2
–
–
+
+
R
R
}
A
}
B
frequency ∝ R , R , C
1
2
amplitude ∝ R , R
A
B
FN8166.5
April 13, 2007
18
X9251
Small Outline Plastic Packages (SOIC)
M24.3 (JEDEC MS-013-AD ISSUE C)
N
24 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE
INDEX
AREA
0.25(0.010)
M
B M
H
INCHES
MILLIMETERS
E
SYMBOL
MIN
MAX
MIN
2.35
0.10
0.33
0.23
MAX
2.65
NOTES
-B-
A
A1
B
C
D
E
e
0.0926
0.0040
0.013
0.1043
0.0118
0.020
-
0.30
-
1
2
3
L
0.51
9
SEATING PLANE
A
0.0091
0.5985
0.2914
0.0125
0.32
-
-A-
0.6141 15.20
15.60
7.60
3
h x 45°
D
0.2992
7.40
4
-C-
0.05 BSC
1.27 BSC
-
α
H
h
0.394
0.010
0.016
0.419
0.029
0.050
10.00
0.25
0.40
10.65
0.75
1.27
-
e
A1
C
5
B
0.10(0.004)
L
6
0.25(0.010) M
C
A M B S
N
α
24
24
7
0°
8°
0°
8°
-
NOTES:
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
Rev. 1 4/06
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm
(0.006 inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Inter-
lead flash and protrusions shall not exceed 0.25mm (0.010 inch) per
side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch)
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact.
FN8166.5
April 13, 2007
19
X9251
Thin Shrink Small Outline Package Family (TSSOP)
MDP0044
THIN SHRINK SMALL OUTLINE PACKAGE FAMILY
0.25 M C A B
D
A
(N/2)+1
MILLIMETERS
N
SYMBOL 14 LD 16 LD 20 LD 24 LD 28 LD TOLERANCE
A
A1
A2
b
1.20
0.10
0.90
0.25
0.15
5.00
6.40
4.40
0.65
0.60
1.00
1.20
0.10
0.90
0.25
0.15
5.00
6.40
4.40
0.65
0.60
1.00
1.20
0.10
0.90
0.25
0.15
6.50
6.40
4.40
0.65
0.60
1.00
1.20
0.10
0.90
0.25
0.15
7.80
6.40
4.40
0.65
0.60
1.00
1.20
0.10
0.90
0.25
0.15
9.70
6.40
4.40
0.65
0.60
1.00
Max
±0.05
PIN #1 I.D.
E
E1
±0.05
+0.05/-0.06
+0.05/-0.06
±0.10
0.20 C B A
2X
1
(N/2)
c
N/2 LEAD TIPS
B
D
TOP VIEW
E
Basic
E1
e
±0.10
Basic
0.05
H
e
L
±0.15
C
L1
Reference
Rev. F 2/07
SEATING
PLANE
NOTES:
0.10 M C A B
b
1. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusions or gate burrs shall not exceed
0.15mm per side.
0.10 C
N LEADS
SIDE VIEW
2. Dimension “E1” does not include interlead flash or protrusions.
Interlead flash and protrusions shall not exceed 0.25mm per
side.
SEE DETAIL “X”
3. Dimensions “D” and “E1” are measured at dAtum Plane H.
4. Dimensioning and tolerancing per ASME Y14.5M-1994.
c
END VIEW
L1
A2
A
GAUGE
PLANE
0.25
L
A1
0° - 8°
DETAIL X
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN8166.5
April 13, 2007
20
相关型号：
X9251UV24ZT1
QUAD 50K DIGITAL POTENTIOMETER, INCREMENT/DECREMENT CONTROL INTERFACE, 256 POSITIONS, PDSO24, 4.40 MM, ROHS COMPLIANT, TSSOP-24
RENESAS
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