X9261TS24IZ-2.7T1 [RENESAS]
DUAL 100K DIGITAL POTENTIOMETER, 3-WIRE SERIAL CONTROL INTERFACE, 256 POSITIONS, PDSO24, 0.300 INCH, ROHS COMPLIANT, PLASTIC, MS-013AD, SOIC-24;
| 型号： | X9261TS24IZ-2.7T1 |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | DUAL 100K DIGITAL POTENTIOMETER, 3-WIRE SERIAL CONTROL INTERFACE, 256 POSITIONS, PDSO24, 0.300 INCH, ROHS COMPLIANT, PLASTIC, MS-013AD, SOIC-24 光电二极管 转换器 电阻器 |
| 文件： | 总20页 (文件大小：303K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
X9261
Single Supply/Low Power/256-Tap/SPI Bus
October 12, 2006
FN8171.4
DESCRIPTION
Dual Digitally-Controlled (XDCP™)
Potentiometers
The X9261 integrates
potentiometer (XDCP) on
integrated circuit.
2
digitally controlled
monolithic CMOS
a
FEATURES
• Dual–Two Separate Potentiometers
• 256 Resistor Taps/pot–0.4% Resolution
• SPI Serial Interface for Write, Read, and Transfer
Operations of the Potentiometer Single Supply
Device
The digital controlled potentiometer is implemented
using 255 resistive elements in a series array.
Between each element are tap points connected to the
wiper terminal through switches. The position of the
wiper on the array is controlled by the user through the
SPI bus interface. Each potentiometer has associated
with it a volatile Wiper Counter Register (WCR) and
four non-volatile Data Registers that can be directly
written to and read by the user. The contents of the
WCR controls the position of the wiper on the resistor
array though the switches. Powerup recalls the
contents of the default Data Register (DR0) to the
WCR.
• Wiper Resistance, 100 typical @ V
= 5V
CC
• 4 Nonvolatile Data Registers for Each
Potentiometer
• Nonvolatile Storage of Multiple Wiper Positions
• Power-on Recall Loads Saved Wiper Position on
Power-up.
• Standby Current < 5µA Max
• 50k, 100k Versions of End to End Resistance
• 100 yr. Data Retention
• Endurance: 100,000 Data Changes per Bit per
Register
• 24 Ld SOIC, 24 Ld TSSOP
The XDCP can be used as a three-terminal
potentiometer or as a two terminal variable resistor in
a wide variety of applications including control,
parameter adjustments, and signal processing.
• Low Power CMOS
• Power Supply V
= 5V ±10%
CC
• Pb-Free Plus Anneal Available (RoHS Compliant)
FUNCTIONAL DIAGRAM
V
R
R
H1
CC
H0
Write
Read
Address
Data
Status
Transfer
Inc/Dec
Power-on Recall
Bus
SPI
Bus
Interface
Wiper Counter
Register (WCR)
Interface
and Control
Data Registers
(DR0-DR3)
Control
V
R
R
R
R
L1
SS
W0
L0
W1
50k or 100k versions
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
XDCP is a trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005, 2006. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
1
X9261
Ordering Information
PART
MARKING
V
LIMITS
(V)
PKG.
DWG. #
CC
PART NUMBER
X9261US24
R
(k) TEMP RANGE (°C)
PACKAGE
24 Ld SOIC (300 mil)
TOTAL
X9261US
5 ±10%
50
0 to 70
0 to 70
0 to 70
0 to 70
M24.3
X9261US24Z (Note)
X9261UV24
X9261US Z
X9261UV
24 Ld SOIC (300 mil) (Pb-free)
24 Ld TSSOP (4.4mm)
M24.3
MDP0044
X9261UV24Z (Note)
X9261UV Z
24 Ld TSSOP (4.4mm) (Pb-free) MDP0044
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
DETAILED FUNCTIONAL DIAGRAM
R
R
R
H0
L0 W0
V
CC
Power-on
Recall
Pot 0
R
R
0
1
Wiper
Counter
Register
(WCR)
HOLD
CS
SCK
SO
INTERFACE
AND
R
R
2
3
CONTROL
CIRCUITRY
SI
A0
A1
50k
and 100k
256-taps
8
Power-on
Recall
Data
WP
R
R
0
1
Wiper
Counter
Register
(WCR)
Resistor
Array
Pot 1
R
R
2
3
V
R
R R
SS
L1 H1 W1
CIRCUIT LEVEL APPLICATIONS
• Vary the frequency and duty cycle of timer ICs
• Vary the dc biasing of a pin diode attenuator in RF
circuits
• Vary the gain of a voltage amplifier
• Provide programmable dc reference voltages for
comparators and detectors
• Provide a control variable (I, V, or R) in feedback
circuits
• Control the volume in audio circuits
• Trim out the offset voltage error in a voltage amplifier
circuit
• Set the output voltage of a voltage regulator
• Trim the resistance in Wheatstone bridge circuits
• Control the gain, characteristic frequency and
Q-factor in filter circuits
• Set the scale factor and zero point in sensor signal
conditioning circuits
FN8171.4
October 12, 2006
2
X9261
SYSTEM LEVEL APPLICATIONS
PIN ASSIGNMENTS
• Adjust the contrast in LCD displays
Pin
(SOIC/
TSSOP) Symbol
• Control the power level of LED transmitters in
communication systems
Function
1
2
SO
A0
Serial Data Output for SPI bus
Device Address for SPI bus.
No Connect.
• Set and regulate the DC biasing point in an RF
power amplifier in wireless systems
3
NC
NC
NC
NC
• Control the gain in audio and home entertainment
systems
4
No Connect.
5
No Connect.
• Provide the variable DC bias for tuners in RF wire-
less systems
6
No Connect.
7
V
System Supply Voltage
Low Terminal for Potentiometer 0.
High Terminal for Potentiometer 0.
Wiper Terminal for Potentiometer 0.
Device Address for SPI bus.
Hardware Write Protect
Serial Data Input for SPI bus
Device Address for SPI bus.
Low Terminal for Potentiometer 1.
High Terminal for Potentiometer 1.
Wiper Terminal for Potentiometer 1.
System Ground
CC
• Set the operating points in temperature control
systems
8
R
L0
H0
W0
9
R
• Control the operating point for sensors in industrial
systems
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
R
CS
WP
SI
• Trim offset and gain errors in artificial intelligent
systems
A1
PIN CONFIGURATION
R
L1
H1
W1
SOIC/TSSOP
R
R
HOLD
SCK
NC
SO
1
2
24
23
22
21
20
19
18
17
16
V
SS
A0
NC
NC
No Connect
NC
3
No Connect
NC
NC
NC
NC
4
NC
No Connect
NC
5
NC
NC
No Connect
6
X9261
V
V
SCK
Serial Clock for SPI bus
7
CC
SS
R
R
HOLD Device select. Pause the SPI serial bus.
8
W1
L0
R
R
H0
9
H1
R
PIN DESCRIPTIONS
Bus Interface Pins
SERIAL OUTPUT (SO)
R
W0
10
11
12
15
14
L1
A1
SI
CS
WP
13
SO is a serial data output pin. During a read cycle,
data is shifted out on this pin. Data is clocked out by
the falling edge of the serial clock.
SERIAL INPUT
SI is the serial data input pin. All opcodes, byte
addresses and data to be written to the pots and pot
registers are input on this pin. Data is latched by the
rising edge of the serial clock.
SERIAL CLOCK (SCK)
The SCK input is used to clock data into and out of the
X9261.
FN8171.4
October 12, 2006
3
X9261
HOLD (HOLD)
Other Pins
HOLD is used in conjunction with the CS pin to select
the device. Once the part is selected and a serial
sequence is underway, HOLD may be used to pause
the serial communication with the controller without
resetting the serial sequence. To pause, HOLD must
be brought LOW while SCK is LOW. To resume
communication, HOLD is brought HIGH, again while
SCK is LOW. If the pause feature is not used, HOLD
should be held HIGH at all times.
NO CONNECT
No connect pins should be left floating. This pins are
used for Intersil manufacturing and testing purposes.
HARDWARE WRITE PROTECT INPUT (WP)
The WP pin when LOW prevents nonvolatile writes to
the Data Registers.
PRINCIPLES OF OPERATION
Serial Interface
DEVICE ADDRESS (A1 - A0)
The address inputs are used to set the 4-bit slave
address. A match in the slave address serial data
stream must be made with the address input in order
to initiate communication with the X9261.
The X9261 supports the SPI interface hardware
conventions. The device is accessed via the SI input
with data clocked in on the rising SCK. CS must be
LOW and the HOLD and WP pins must be HIGH
during the entire operation.
CHIP SELECT (CS)
When CS is HIGH, the X9261 is deselected and the
SO pin is at high impedance, and (unless an internal
write cycle is underway) the device will be in the
standby state. CS LOW enables the X9261, placing it
in the active power mode. It should be noted that after
a power-up, a HIGH to LOW transition on CS is
required prior to the start of any operation.
The SO and SI pins can be connected together, since
they have three state outputs. This can help to reduce
system pin count.
Array Description
The X9261 is comprised of a resistor array (See
Figure 1). The array contains the equivalent of 255
discrete resistive segments that are connected in
series. The physical ends of each array are equivalent
to the fixed terminals of a mechanical potentiometer
Potentiometer Pins
R , R
H
L
(R and R inputs).
H
L
The R and R pins are equivalent to the terminal
H
L
At both ends of each array and between each resistor
segment is a CMOS switch connected to the wiper
connections on a mechanical potentiometer. Since
there are 2 potentiometers, there are 2 sets of R and
H
(R ) output. Within each individual array only one
W
R such that R and R are the terminals of POT 0
L
H0
L0
switch may be turned on at a time.
and so on.
These switches are controlled by a Wiper Counter
Register (WCR). The 8-bits of the WCR (WCR[7:0])
are decoded to select, and enable, one of 256
switches (See Table 1).
R
W
The wiper pin are equivalent to the wiper terminal of a
mechanical potentiometer. Since there are
2
potentiometers, there are 2 sets of R such that R
is the terminals of POT 0 and so on.
W
W0
Power-up and Down Requirements.
There are no restrictions on the power-up or power-
down conditions of V
and the voltages applied to
CC
Supply Pins
the potentiometer pins provided that V
is always
CC
more positive than or equal to V , V , and V , i.e.,
H
L
W
SYSTEM SUPPLY VOLTAGE (V ) AND SUPPLY
CC
V
, V , V , V . The V ramp rate specification is
CC CC
H
L
W
GROUND (V
)
SS
always in effect.
The V
pin is the system supply voltage. The V
CC
pin is the system ground.
SS
FN8171.4
October 12, 2006
4
X9261
Figure 1. Detailed Potentiometer Block Diagram
One of Two Potentiometers
SERIAL DATA PATH
SERIAL
BUS
INPUT
R
H
FROM INTERFACE
CIRCUITRY
C
O
U
N
T
REGISTER 1
(DR1)
REGISTER 0
(DR0)
8
8
PARALLEL
BUS
INPUT
E
R
REGISTER 2
(DR2)
REGISTER 3
(DR3)
D
E
C
O
D
E
WIPER
COUNTER
REGISTER
(WCR)
INC/DEC
LOGIC
IF WCR = 00[H] THEN R = R
W
L
UP/DN
IF WCR = FF[H] THEN R = R
UP/DN
CLK
W
H
R
L
MODIFIED SCK
R
W
DEVICE DESCRIPTION
Data Registers (DR)
Each potentiometer has four 8-bit nonvolatile Data
Registers. These can be read or written directly by the
host. Data can also be transferred between any of the
four Data Registers and the associated Wiper Counter
Register. All operations changing data in one of the
Data Registers is a nonvolatile operation and will take
a maximum of 10ms.
Wiper Counter Register (WCR)
The X9261 contains two Wiper Counter Registers, one
for each DCP potentiometer. The Wiper Counter
Register can be envisioned as a 8-bit parallel and
serial load counter with its outputs decoded to select
one of 256 switches along its resistor array. The
contents of the WCR can be altered in four ways: it
may be written directly by the host via the Write Wiper
Counter Register instruction (serial load); it may be
written indirectly by transferring the contents of one of
four associated data registers via the XFR Data
Register instruction (parallel load); it can be modified
one step at a time by the Increment/Decrement
instruction (See Instruction section for more details).
Finally, it is loaded with the contents of its Data
Register zero (DR0) upon power-up.
If the application does not require storage of multiple
settings for the potentiometer, the Data Registers can
be used as regular memory locations for system
parameters or user preference data.
Bits [7:0] are used to store one of the 256 wiper
positions or data (0~255).
Status Register (SR)
This 1-bit Status Register is used to store the system
status.
The Wiper Counter Register is a volatile register; that
is, its contents are lost when the X9261 is powered-
down. Although the register is automatically loaded
with the value in DR0 upon power-up, this may be
different from the value present at power-down.
Power-up guidelines are recommended to ensure
proper loadings of the DR0 value into the WCR.
WIP: Write In Progress status bit, read only.
– When WIP=1, indicates that high-voltage write cycle
is in progress.
– When WIP=0, indicates that no high-voltage write
cycle is in progress.
FN8171.4
October 12, 2006
5
X9261
Table 1. Wiper Counter Register, WCR (8-bit), WCR[7:0]: Used to store the current wiper position (Volatile, V).
WCR7
V
WCR6
V
WCR5
V
WCR4
V
WCR3
V
WCR2
V
WCR1
V
WCR0
V
(MSB)
(LSB)
Table 2. Data Register, DR (8-bit), Bit [7:0]: Used to store wiper positions or data (Nonvolatile, NV).
Bit 7
NV
Bit 6
NV
Bit 5
NV
Bit 4
NV
Bit 3
NV
Bit 2
NV
Bit 1
NV
Bit 0
NV
MSB
LSB
DEVICE DESCRIPTION
Instructions
input state; a successful compare of both address bits
is required for the X9261 to successfully continue the
command sequence. Only the device which slave
address matches the incoming device address sent
by the master executes the instruction. The A3-A0
inputs can be actively driven by CMOS input signals
IDENTIFICATION BYTE ( ID AND A )
The first byte sent to the X9261 from the host,
following a CS going HIGH to LOW, is called the
Identification Byte. The most significant four bits of the
slave address are a device type identifier. The ID[3:0]
bits is the device id for the X9261; this is fixed as
0101[B] (refer to Table 3).
or tied to V
or V
.
CC
SS
INSTRUCTION BYTE ( I[3:0] )
The next byte sent to the X9261 contains the instruction
and register pointer information. The three most
significant bits are used provide the instruction opcode
(I[3:0]). The RB and RA bits point to one of the four
Data Registers of each associated XDCP. The least
significant bit points to one of two Wiper Counter
Registers or Pots.The format is shown below in Table 4.
The AD[3:0] bits in the ID byte is the internal slave
address. The physical device address is defined by
the state of the A3 - A0 input pins. The slave address
is externally specified by the user. The X9261
compares the serial data stream with the address
Table 3. Identification Byte Format
Device Type
Identifier
Slave Address
ID3
0
ID2
1
ID1
0
ID0
1
A3
A2
A1
A0
(MSB)
(LSB)
Table 4. Instruction Byte Format
Data
Register
Pot Selection
(WCR Selection)
Instruction
Opcode
Selection
I3
I2
I1
I0
RB
RA
0
P0
(MSB)
(LSB)
FN8171.4
October 12, 2006
6
X9261
Register Selection
– XFR Data Register to Wiper Counter Register –
This transfers the contents of one specified Data
Register to the associated Wiper Counter Register.
Register Selected
RB
0
RA
0
DR0
DR1
DR2
DR3
– XFR Wiper Counter Register to Data Register –
This transfers the contents of the specified Wiper
Counter Register to the specified associated Data
Register.
0
1
1
0
1
1
– Global XFR Data Register to Wiper Counter
Register – This transfers the contents of all speci-
fied Data Registers to the associated Wiper Counter
Registers.
DEVICE DESCRIPTION
Instructions
Four of the ten instructions are three bytes in length.
These instructions are:
– Global XFR Wiper Counter Register to Data
Register – This transfers the contents of all Wiper
Counter Registers to the specified associated Data
Registers.
– Read Wiper Counter Register – read the current
wiper position of the selected potentiometer,
– Write Wiper Counter Register – change current
INCREMENT/DECREMENT COMMAND
wiper position of the selected potentiometer,
The final command is Increment/Decrement (See
Figures 6 and 7). The Increment/Decrement command
is different from the other commands. Once the
command is issued and the X9261 has responded
with an acknowledge, the master can clock the
selected wiper up and/or down in one segment steps;
thereby, providing a fine tuning capability to the host.
– Read Data Register – read the contents of the
selected Data Register;
– Write Data Register – write a new value to the
selected Data Register.
– Read Status - This command returns the contents
of the WIP bit which indicates if the internal write
cycle is in progress.
For each SCL clock pulse (t
) while SI is HIGH,
HIGH
the selected wiper will move one resistor segment
The basic sequence of the three byte instructions is
illustrated in Figure 3. These three-byte instructions
exchange data between the WCR and one of the Data
Registers. A transfer from a Data Register to a WCR is
essentially a write to a static RAM, with the static RAM
controlling the wiper position. The response of the
towards the R terminal. Similarly, for each SCL clock
pulse while SI is LOW, the selected wiper will move
H
one resistor segment towards the R terminal. A
L
detailed illustration of the sequence and timing for this
operation are shown. See Instruction format for more
details.
wiper to this action will be delayed by t
. A transfer
WRL
from the WCR (current wiper position), to a Data
Register is a write to nonvolatile memory and takes a
minimum of t
to complete. The transfer can occur
WR
between one of the two potentiometers and one of its
associated registers; or it may occur globally, where
the transfer occurs between all potentiometers and
one associated register. The Read Status Register
instruction is the only unique format (See Figure 5).
Four instructions require a two-byte sequence to
complete. These instructions transfer data between
the host and the X9261; either between the host and
one of the data registers or directly between the host
and the Wiper Counter Register. These instructions
are:
FN8171.4
October 12, 2006
7
X9261
Figure 2. Two-Byte Instruction Sequence
CS
SCK
SI
0
0
0
0
0
0
1
0
1
A1 A0
ID3 ID2 ID1 ID0
Device ID
RB RA
P0
I3
I2
I1 I0
Register
Address
Instruction
Opcode
Pot/WCR
Address
Internal
Address
Figure 3. Three-Byte Instruction Sequence (Write)
CS
SCL
SI
0
0
0
0
0
1
0
1
0
ID3 ID2 ID1 ID0
A1 A0
RB RA
P0
I3 I2
I0
D7 D6 D5 D4 D3 D2 D1 D0
I1
WCR[7:0]
or
Data Register Bit [7:0]
Internal
Address
Instruction
Opcode
Register
Address
Pot/WCR
Address
Device ID
Figure 4. Three-Byte Instruction Sequence (Read)
CS
SCL
SI
0
0
0
0
0
1
0
1
X
X
X
X
X
X
X
0
X
ID3 ID2 ID1 ID0
Device ID
A1 A0
I2 I1
RB RA
P0
I3
I0
Don’t Care
Internal
Address
Pot/WCR
Address
Instruction
Opcode
Register
Address
S0
D7 D6 D5 D4 D3 D2 D1 D0
WCR[7:0]
or
Data Register Bit [7:0]
FN8171.4
October 12, 2006
8
X9261
Figure 5. Three-Byte Instruction Sequence (Read Status Register)
CS
SCL
SI
1
0
0
0
0
0
0
1
0
1
0
0
0
0
1
0
1
0
0
0
ID3 ID2 ID1 ID0
I3
A1 A0
I2 I1 I0
RB RA
P0
WIP
Internal
Address
Instruction
Opcode
Register
Address
Pot/WCR
Address
Status
Bit
Device ID
Figure 6. Increment/Decrement Instruction Sequence
CS
SCL
SI
0
0
0
0
0
1
0
1
0
ID3 ID2 ID1 ID0
Device ID
I2 I3
I0
A1 A0
I1
RB RA
P0
I
I
D
E
C
1
I
D
E
C
n
N
C
1
N
C
2
N
C
n
Internal
Address
Instruction
Opcode
Pot/WCR
Address
Register
Address
Figure 7. Increment/Decrement Timing Limits
t
WRID
SCK
SI
VOLTAGE OUT
R
W
INC/DEC CMD ISSUED
FN8171.4
October 12, 2006
9
X9261
Table 5. Instruction Set
Instruction
Instruction Set
I0 RB RA
I3
I2
I1
0
P0
Operation
Read Wiper Counter
Register
1
0
0
1
0
1
0
1
0
0
0
1/0 Read the contents of the Wiper Counter
Register pointed to by P0
Write Wiper Counter
Register
1
1
1
1
0
0
1
1
1
1
0
0
0
0
0
0
0
0
1/0 Write new value to the Wiper Counter
Register pointed to by P0
Read Data Register
1/0 1/0
1/0 1/0
1/0 1/0
1/0 Read the contents of the Data Register
pointed to by P0 and RB - RA
Write Data Register
1/0 Write new value to the Data Register
pointed to by P0 and RB - RA
XFR Data Register to
Wiper Counter Register
1/0 Transfer the contents of the Data Register
pointed to by P0 and RB - RA to its
associated Wiper Counter Register
XFR Wiper Counter
Register to Data Register
1
0
1
0
1
0
0
0
1
0
0
1
0
1
0
0
1/0 1/0
1/0 1/0
1/0 1/0
0
0
0
0
1/0 Transfer the contents of the Wiper Counter
Register pointed to by P0 to the Data
Register pointed to by RB - RA
Global XFR Data Registers
to Wiper Counter Registers
0
Transfer the contents of the Data Registers
pointed to by RB - RA of all four pots to their
respective Wiper Counter Registers
Global XFR Wiper Counter
Registers to Data Register
0
Transfer the contents of both Wiper Counter
Registers to their respective data Registers
pointed to by RB - RA of all four pots
Increment/Decrement
Wiper Counter Register
0
0
1/0 Enable Increment/decrement of the Control
Latch pointed to by P0
Note: 1/0 = data is one or zero
INSTRUCTION FORMAT
Read Wiper Counter Register (WCR)
Device Type
Identifier
Device
Addresses
Instruction
Opcode
WCR
Addresses
Wiper Position
(Sent by X9261 on SO)
CS
Falling
Edge
CS
Rising
Edge
W
C
R
W
C
R
7
W W W W W W
C C C C C C
R R R R R R
0
1
0
1
0
0 A1 A0 1
0
0
1
0
0
0 P0
5
4
3
2
1
0
6
Write Wiper Counter Register (WCR)
Device Type
Identifier
Device
Addresses
Instruction
Opcode
WCR
Addresses
Data Byte
(Sent by Host on SI)
CS
Falling
Edge
CS
Rising
Edge
W
C
R
W
C
R
7
W W W W W W
C C C C C C
R R R R R R
0
1
0
1
0
0 A1 A0 1
0
1
0
0
0
0 P0
5
4 3 2 1 0
6
Read Data Register (DR)
Device Type
CS
Device
Addresses
Instruction
Opcode
DR and WCR
Addresses
Data Byte
(Sent by X9271 on SO)
CS
Rising
Edge
Identifier
Falling
Edge
D
D D D D D D D
0
1
0
1
0
0 A1 A0 1
0
1
1 RB RA
0
P0
6
5 4 3 2 1 0
7
FN8171.4
October 12, 2006
10
X9261
Write Data Register (DR)
Device Type
Identifier
Device
Addresses
Instruction
Opcode
DR and WCR
Addresses
Data Byte
(Sent by Host on SI)
CS
CS
Falling
Edge
Rising
Edge
D
7
D D D D D D D
6 5 4 3 2 1 0
0
1
0
1
0 0 A1 A0 1 1 0 0 RB RA
0
P0
Global Transfer Data Register (DR) to Wiper Counter Register (WCR)
Device Type
Identifier
Device
Addresses
Instruction
Opcode
DR
Addresses
CS
Falling
Edge
CS
Rising
Edge
0
1
0
1
0
0 A1 A0 0 0 0 1 RB RA 0 0
Global Transfer Wiper Counter Register (WCR) to Data Register (DR)
Device Type
Identifier
Device
Addresses
Instruction
Opcode
DR
Addresses
CS
Falling
Edge
CS
Rising
Edge
HIGH-VOLTAGE
WRITE CYCLE
0
1
0
1 0 0 A1 A0 1 0 0 0 RB RA 0 0
Transfer Wiper Counter Register (WCR) to Data Register (DR)
Device Type
Identifier
Device
Addresses
Instruction
Opcode
DR and WCR
Addresses
CS
Falling
Edge
CS
Rising
Edge
HIGH-VOLTAGE
WRITE CYCLE
0
1
0
1 0 0 A1 A0 1 1 1 0 RB RA 0 P0
Transfer Data Register (DR) to Wiper Counter Register (WCR)
Device Type
Identifier
Device
Addresses
Instruction
Opcode
DR and WCR
Addresses
CS
Falling
Edge
CS
Rising
Edge
0
1
0
1 0 0 A1 A0 1 1 0 1 RB RA 0 P0
Increment/Decrement Wiper Counter Register (WCR)
Device Type
Identifier
Device
Addresses
Instruction
Opcode
WCR
Addresses
Increment/Decrement
(Sent by Master on SDA)
CS
Falling
Edge
CS
Rising
Edge
0
1
0
1
0
0 A1 A0 0
0
1
0
X X 0 P0 I/D I/D
.
.
.
. I/D I/D
Read Status Register (SR)
Device Type
Identifier
Device
Addresses
0 A1 A0 0
Instruction
Opcode
WCR
Addresses
Data Byte
(Sent by X9261 on SO)
WIP
CS
Falling
Edge
CS
Rising
Edge
0
1
0
1
0
1
0
1
0
0
0
1
0
0
0
0
0
0
0
Notes: (1) “A1 ~ A0”: stands for the device addresses sent by the master.
(2) WPx refers to wiper position data in the Counter Register
(2) “I”: stands for the increment operation, SI held HIGH during active SCK phase (high).
(3) “D”: stands for the decrement operation, SI held LOW during active SCK phase (high).
FN8171.4
October 12, 2006
11
X9261
ABSOLUTE MAXIMUM RATINGS
COMMENT
Temperature under bias .................... -65C to +135C
Storage temperature.......................... -65C to +150C
Voltage on SCK any address input
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only; the functional operation of
the device (at these or any other conditions above
those listed in the operational sections of this
specification) is not implied. Exposure to absolute
maximum rating conditions for extended periods may
affect device reliability.
with respect to V ................................. -1V to +7V
SS
V = | (V - VL) |...................................................5.5V
H
Lead temperature (soldering, 10s) .................... 300C
I
(10s)..............................................................±6mA
W
RECOMMENDED OPERATING CONDITIONS
(4)
Temp
Min.
0C
-40C
Max.
+70C
+85C
Device
Supply Voltage (V
CC
)
Limits
Commercial
Industrial
X9261
5V 10%
POTENTIOMETER CHARACTERISTICS (Over recommended industrial operating conditions unless otherwise stated.)
Parameter
Limits
Symbol
Min.
Typ.
Max. Units
Test Conditions
T version
R
End to End Resistance
End to End Resistance
End to End Resistance Tolerance
Power Rating
100
50
k
k
TOTAL
TOTAL
R
U version
±20
50
%
mW
mA
25C, each pot
I
Wiper Current
±3
W
R
R
Wiper Resistance
300
150
I
I
= 3mA @ V+ = 3V
= 3mA @ V+ = 5V
W
W
W
Wiper Resistance
W
V
Voltage on any R or R Pin
V
V
V
V
= 0V
TERM
H
L
SS
CC
SS
Ref: 1V
Noise
-120
0.4
dBV
Resolution
%
(1)
(3)
MI
(5)
Absolute Linearity
±1
R
R
- R
w(n)(actual)
w(n)(expected)
(2)
(3)
MI
(5)
Relative Linearity
±0.6
- [R ]
w(n) + MI
w(n + 1)
Temperature Coefficient of R
300
ppm/C
ppm/°C
pF
TOTAL
Ratiometric Temp. Coefficient
Potentiometer Capacitances
20
C /C /C
W
10/10/25
0.1
See Macro model
Device in stand by.
H
L
I
R , R , R Leakage
10.0
µA
al
W
H
L
Vin = V to V
SS CC
Notes: (1) Absolute linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used as a
potentiometer.
(2) Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a
potentiometer. It is a measure of the error in step size.
(3) MI = RTOT / 255 or (R - R ) / 255, single pot
H
L
(4) During power-up V
> V , V , and V .
CC
H L W
(5) n = 0, 1, 2, …,255; m = 0, 1, 2, …, 254.
FN8171.4
October 12, 2006
12
X9261
D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.)
Limits
Symbol
Parameter
Min.
Typ.
Max.
Units
Test Conditions
I
I
I
V
supply current
400
A
f
= 2.5 MHz, SO = Open, V
= 6V
= 6V
CC1
CC2
SB
CC
SCK
CC
(active)
Other Inputs = V
SS
V
supply current
1
5
5
mA
f
= 2.5MHz, SO = Open, V
CC
(nonvolatile write)
SCK
Other Inputs = V
CC
SS
V
current (standby)
A
SCK = SI = V , Addr. = V
CS = V
,
SS
CC
SS
= 6V
CC
I
I
Input leakage current
Output leakage current
Input HIGH voltage
Input LOW voltage
10
10
A
A
V
V
V
= V to V
SS CC
LI
IN
= V to V
SS CC
LO
OUT
V
V
V
V
V
V
x 0.7
V
+ 1
IH
CC
-1
CC
x 0.3
V
V
IL
CC
0.4
Output LOW voltage
Output HIGH voltage
Output HIGH voltage
V
I
I
I
= 3mA
OL
OH
OH
OL
OH
OH
V
V
- 0.8
V
= -1mA, V
CC
+3V
+3V
CC
CC
- 0.4
V
= -0.4mA, V
CC
ENDURANCE AND DATA RETENTION
Parameter
Minimum endurance
Data retention
Min.
Units
100,000
100
Data changes per bit per register
years
CAPACITANCE
Symbol
Test
Max.
Units
pF
Test Conditions
(6)
C
Output capacitance (SO)
Input capacitance (A0, A1, SI, CS, WP, HOLD, and SCK)
8
6
V
V
= 0V
OUT
OUT
= 0V
(6)
C
pF
IN
IN
POWER-UP TIMING
Symbol
Parameter
Power-up rate
Min.
Max.
50
Units
(6)
t V
CC
V
0.2
V/ms
ms
r
CC
Power-up to initiation of read operation
(7)
t
1
PUR
POWER-UP AND DOWN REQUIREMENTS
The are no restrictions on the power-up or power-down conditions of V
and the voltages applied to the poten-
V , V , V . The
CC
is always more positive than or equal to V , V , and V , i.e., V
tiometer pins provided that V
CC
H
L
W
CC
H
L
W
V
power-up timing spec is always in effect.
CC
A.C. TEST CONDITIONS
Input Pulse Levels
V
x 0.1 to V x 0.9
CC
CC
Input rise and fall times
10ns
Input and output timing level
V
x 0.5
CC
Notes: (6) This parameter is not 100% tested
(7) t and t are the delays required from the time the (last) power supply (V -) is stable until the specific instruction can be issued.
PUR
PUW
CC
These parameters are periodically sampled and not 100% tested.
FN8171.4
October 12, 2006
13
X9261
EQUIVALENT A.C. LOAD CIRCUIT
5V
1462
3V
1382
SPICE Macromodel
R
TOTAL
R
R
L
H
SO pin
SO pin
C
C
W
C
L
L
10pF
2714
1217
100pF
100pF
25pF
10pF
R
W
AC TIMING
Symbol
Parameter
Min.
Max.
Units
MHz
ns
ns
ns
ns
ns
ns
ns
s
s
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
s
ns
f
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
SSI/SPI clock frequency
SSI/SPI clock cycle rime
SSI/SPI clock high rime
SSI/SPI clock low time
Lead time
2
SCK
CYC
WH
WL
LEAD
LAG
SU
500
200
200
250
250
50
Lag time
SI, SCK, HOLD and CS input setup time
SI, SCK, HOLD and CS input hold time
SI, SCK, HOLD and CS input rise time
SI, SCK, HOLD and CS input fall time
SO output disable time
50
H
2
RI
2
FI
0
0
250
200
DIS
V
SO output valid time
SO output hold time
HO
RO
FO
SO output rise time
100
100
SO output fall time
HOLD time
400
100
100
HOLD
HSU
HH
HZ
HOLD setup time
HOLD hold time
HOLD low to output in high Z
HOLD high to output in low Z
100
100
10
LZ
T
Noise suppression time constant at SI, SCK, HOLD and CS inputs
CS deselect time
I
t
t
t
2
0
0
CS
WP, A0, A1 setup time
WPASU
WPAH
WP, A0, A1 hold time
ns
FN8171.4
October 12, 2006
14
X9261
HIGH-VOLTAGE WRITE CYCLE TIMING
Symbol
Parameter
Typ.
Max.
Units
t
High-voltage write cycle time (store instructions)
5
10
ms
WR
XDCP TIMING
Symbol
Parameter
Min. Max. Units
t
t
Wiper response time after the third (last) power supply is stable
Wiper response time after instruction issued (all load instructions)
5
5
10
10
s
s
WRPO
WRL
SYMBOL TABLE
WAVEFORM
INPUTS
OUTPUTS
Must be
steady
Will be
steady
May change
from Low to
High
Will change
from Low to
High
May change
from High to
Low
Will change
from High to
Low
Don’t Care:
Changes
Allowed
Changing:
State Not
Known
N/A
Center Line
is High
Impedance
TIMING DIAGRAMS
Input Timing
t
CS
CS
t
t
t
LEAD
CYC
LAG
SCK
...
WH
t
t
t
RI
t
FI
t
t
WL
SU
H
...
MSB
LSB
SI
High Impedance
SO
FN8171.4
October 12, 2006
15
X9261
Output Timing
CS
SCK
SO
...
...
t
t
t
DIS
V
HO
MSB
LSB
ADDR
SI
Hold Timing
CS
t
t
HH
HSU
SCK
...
t
t
FO
RO
SO
t
t
LZ
HZ
SI
t
HOLD
HOLD
XDCP Timing (for All Load Instructions)
CS
SCK
...
...
t
WRL
LSB
MSB
SI
VWx
High Impedance
SO
Write Protect and Device Address Pins Timing
(Any Instruction)
CS
t
t
WPAH
WPASU
WP
A0
A1
FN8171.4
October 12, 2006
16
X9261
APPLICATIONS INFORMATION
Basic Configurations of Electronic Potentiometers
+V
R
V
R
RW
I
Three terminal Potentiometer;
Variable voltage divider
Two terminal Variable Resistor;
Variable current
Application Circuits
Noninverting Amplifier
Voltage Regulator
V
+
–
S
V
V
V (REG)
O
317
O
IN
R
1
R
2
I
adj
R
R
1
2
V
= (1+R /R )V
V
(REG) = 1.25V (1+R /R )+I
R
adj 2
O
2
1
S
O
2
1
Offset Voltage Adjustment
Comparator with Hysterisis
R
R
2
1
V
–
+
S
V
V
S
O
100k
–
+
V
O
TL072
R
R
1
2
10k
10k
+12V
V
V
= {R /(R +R )} V (max)
1 1 2 O
UL
LL
10k
-12V
= {R /(R +R )} V (min)
1 1 2 O
FN8171.4
October 12, 2006
17
X9261
Application Circuits (continued)
Attenuator
Filter
C
V
+
–
S
R
V
R
2
O
1
3
–
+
R
V
O
V
S
R
R
2
R
4
R = R = R = R = 10k
1
2
3
4
R
1
G
= 1 + R /R
2 1
V
= G V
S
O
O
fc = 1/(2RC)
-1/2 G +1/2
Inverting Amplifier
Equivalent L-R Circuit
R
R
2
1
V
S
R
2
C
1
–
+
V
+
–
S
V
O
R
R
1
Z
IN
V
= G V
S
O
G = - R /R
2
1
3
Z
= R + s R (R + R ) C = R + s Leq
2 2 1 3 1 2
IN
(R + R ) >> R
1
3
2
Function Generator
C
R
R
1
2
–
+
–
+
R
R
}
A
}
B
frequency R , R , C
1
2
amplitude R , R
A
B
FN8171.4
October 12, 2006
18
X9261
Small Outline Plastic Packages (SOIC)
M24.3 (JEDEC MS-013-AD ISSUE C)
N
24 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE
INDEX
AREA
0.25(0.010)
M
B M
H
INCHES
MILLIMETERS
E
SYMBOL
MIN
MAX
MIN
2.35
0.10
0.33
0.23
MAX
2.65
NOTES
-B-
A
A1
B
C
D
E
e
0.0926
0.0040
0.013
0.1043
0.0118
0.020
-
0.30
-
1
2
3
L
0.51
9
SEATING PLANE
A
0.0091
0.5985
0.2914
0.0125
0.32
-
-A-
0.6141 15.20
15.60
7.60
3
h x 45°
D
0.2992
7.40
4
-C-
0.05 BSC
1.27 BSC
-
H
h
0.394
0.010
0.016
0.419
0.029
0.050
10.00
0.25
0.40
10.65
0.75
1.27
-
e
A1
C
5
B
0.10(0.004)
L
6
0.25(0.010) M
C
A M B S
N
24
24
7
0°
8°
0°
8°
-
NOTES:
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
Rev. 1 4/06
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm
(0.006 inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Inter-
lead flash and protrusions shall not exceed 0.25mm (0.010 inch) per
side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch)
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact.
FN8171.4
October 12, 2006
19
X9261
Thin Shrink Small Outline Package Family (TSSOP)
MDP0044
0.25 M C A B
N
THIN SHRINK SMALL OUTLINE PACKAGE FAMILY
D
A
(N/2)+1
SYMBOL 14 LD 16 LD 20 LD 24 LD 28 LD TOLERANCE
A
A1
A2
b
1.20
0.10
0.90
0.25
0.15
5.00
6.40
4.40
0.65
0.60
1.00
1.20
0.10
0.90
0.25
0.15
5.00
6.40
4.40
0.65
0.60
1.00
1.20
0.10
0.90
0.25
0.15
6.50
6.40
4.40
0.65
0.60
1.00
1.20
0.10
0.90
0.25
0.15
7.80
6.40
4.40
0.65
0.60
1.00
1.20
0.10
0.90
0.25
0.15
9.70
6.40
4.40
0.65
0.60
1.00
Max
±0.05
PIN #1 I.D.
E
E1
±0.05
+0.05/-0.06
+0.05/-0.06
±0.10
c
0.20 C B A
2X
1
(N/2)
D
N/2 LEAD TIPS
B
E
Basic
TOP VIEW
E1
e
±0.10
Basic
L
±0.15
0.05
H
e
L1
Reference
Rev. E 12/02
C
NOTES:
SEATING
PLANE
1. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusions or gate burrs shall not exceed
0.15mm per side.
0.10 M C A B
b
0.10 C
N LEADS
SIDE VIEW
2. Dimension “E1” does not include interlead flash or protrusions.
Interlead flash and protrusions shall not exceed 0.25mm per
side.
3. Dimensions “D” and “E1” are measured at dAtum Plane H.
SEE DETAIL “X”
4. Dimensioning and tolerancing per ASME Y14.5M-1994.
c
END VIEW
L1
A2
A
GAUGE
PLANE
0.25
L
A1
0° - 8°
DETAIL X
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9001 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN8171.4
October 12, 2006
20
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