X9269TS24-2.7T1中文资料_数据手册_规格书

DATASHEET

X9269

FN8173

Rev.4.00

April 17, 2007

Single Supply/Low Power/256-Tap/2-Wire Bus Dual Digitally-Controlled (XDCP™)

Potentiometers

FEATURES

DESCRIPTION

• Dual–Two Separate Potentiometers

• 256 Resistor Taps/Pot–0.4% Resolution

• 2-Wire Serial Interface for Write, Read, and

Transfer Operations of the Potentiometer Single

Supply Device

The X9269 integrates

potentiometer (XDCP) on

integrated circuit.

2

digitally controlled

monolithic CMOS

a

The digital controlled potentiometer is implemented

using 255 resistive elements in a series array.

Between each element are tap points connected to the

wiper terminal through switches. The position of the

wiper on the array is controlled by the user through the

2-Wire bus interface. Each potentiometer has

associated with it a volatile Wiper Counter Register

(WCR) and a four nonvolatile Data Registers that can

be directly written to and read by the user. The

contents of the WCR controls the position of the wiper

on the resistor array though the switches. Powerup

recalls the contents of the default Data Register (DR0)

to the WCR.

• Wiper Resistance, 100 Typical V

= 5V

CC

• 4 Nonvolatile Data Registers for Each

Potentiometer

• Nonvolatile Storage of Multiple Wiper Positions

• Power-on Recall. Loads Saved Wiper Position on

Power-up.

• Standby Current < 5µA Max

• 50k, 100k Versions of End to End Pot

Resistance

• 100 yr. Data Retention

• Endurance: 100,000 Data Changes per Bit per

Register

• 24-Lead SOIC, 24-Lead TSSOP

• Low Power CMOS

The XDCP can be used as

a three-terminal

potentiometer or as a two terminal variable resistor in

a wide variety of applications including control,

parameter adjustments, and signal processing.

• Power Supply V

= 2.7V to 5.5V

CC

• Pb-Free Plus Anneal Available (RoHS Compliant)

FUNCTIONAL DIAGRAM

V

R

H1

CC

H0

Write

Read

Address

Data

Status

Transfer

Inc/Dec

Power-on Recall

Bus

2-Wire

Bus

Interface

Wiper Counter

Registers (WCR)

Interface

and Control

Data Registers

(DR0–DR3)

Control

V

R

SS

W0

L0

W1

L1

50k

or 100k versions

FN8173 Rev.4.00

April 17, 2007

Page 1 of 24

X9269

Ordering Information

POTENTIOMETER

ORGANIZATION

(k)

TEMP

RANGE

(°C)

PART

MARKING

V

LIMITS

(V)

PKG.

DWG. #

CC

PART NUMBER

PACKAGE

X9269TS24*

X9269TS

5 ±10%

100

0 to +70 24 Ld SOIC (300 mil)

-40 to +85 24 Ld SOIC (300 mil)

M24.3

X9269TS24I*

X9269TS I

X9269TS ZI

M24.3

X9269TS24IZ* (Note)

-40 to +85 24 Ld SOIC (300 mil)

(Pb-free)

X9269TS24Z* (Note)

X9269TS Z

0 to +70 24 Ld SOIC (300 mil)

(Pb-free)

M24.3

X9269TV24

X9269TV

0 to +70 24 Ld TSSOP (4.4mm)

0 to +70 24 Ld SOIC (300 mil)

-40 to +85 24 Ld SOIC (300 mil)

MDP0044

M24.3

X9269US24*

X9269US

X9269US I

X9269US ZI

50

X9269US24I*

M24.3

X9269US24IZ* (Note)

-40 to +85 24 Ld SOIC (300 mil)

(Pb-free)

M24.3

X9269US24Z* (Note)

X9269US Z

0 to +70 24 Ld SOIC (300 mil)

(Pb-free)

M24.3

X9269UV24*

X9269UV

0 to +70 24 Ld TSSOP (4.4mm)

-40 to +85 24 Ld TSSOP (4.4mm)

0 to +70 24 Ld SOIC (300 mil)

-40 to +85 24 Ld SOIC (300 mil)

MDP0044

M24.3

X9269UV24I

X9269UV I

X9269TS F

X9269TS G

X9269TS ZG

X9269TS24-2.7*

X9269TS24I-2.7*

X9269TS24IZ-2.7* (Note)

2.7 to 5.5

100

M24.3

-40 to +85 24 Ld SOIC (300 mil)

(Pb-free)

M24.3

X9269TS24Z-2.7* (Note)

X9269TS ZF

0 to +70 24 Ld SOIC (300 mil)

(Pb-free)

M24.3

X9269TV24I-2.7

X9269TV G

-40 to +85 24 Ld TSSOP (4.4mm)

MDP0044

X9269TV24IZ-2.7* (Note)

X9269TV ZG

-40 to +85 24 Ld TSSOP (4.4mm)

(Pb-free)

X9269US24-2.7*

X9269US F

X9269US G

X9269US ZG

50

0 to +70 24 Ld SOIC (300 mil)

-40 to +85 24 Ld SOIC (300 mil)

M24.3

X9269US24I-2.7*

X9269US24IZ-2.7* (Note)

-40 to +85 24 Ld SOIC (300 mil)

(Pb-free)

X9269US24Z-2.7* (Note)

X9269US ZF

0 to +70 24 Ld SOIC (300 mil)

(Pb-free)

M24.3

X9269UV24-2.7*

X9269UV24I-2.7*

X9269UV24IZ-2.7*

X9269UV F

X9269UV G

X9269UV ZG

0 to +70 24 Ld TSSOP (4.4mm)

-40 to +85 24 Ld TSSOP (4.4mm)

MDP0044

*Add "T1" suffix for tape and reel.

NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate

termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL

classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

FN8173 Rev.4.00

April 17, 2007

Page 2 of 24

X9269

DETAILED FUNCTIONAL DIAGRAM

R

H0

L0 W0

V

CC

Power-on

Recall

Pot 0

R

0

1

Wiper

Counter

Register

(WCR)

R

2

3

SCL

SDA

INTERFACE

AND

50k

 and 100k

A3

A2

A1

CONTROL

CIRCUITRY

256-taps

8

Power-on

Recall

A0

Data

WP

R

0

1

Wiper

Counter

Register

(WCR)

Resistor

Array

Pot 1

R

2

3

V

SS

R

L1 H1 W1

CIRCUIT LEVEL APPLICATIONS

SYSTEM LEVEL APPLICATIONS

• Vary the gain of a voltage amplifier

• Adjust the contrast in LCD displays

• Provide programmable dc reference voltages for com-

parators and detectors

• Control the power level of LED transmitters in

communication systems

• Control the volume in audio circuits

• Set and regulate the DC biasing point in an RF power

amplifier in wireless systems

• Trim out the offset voltage error in a voltage

amplifier circuit

• Control the gain in audio and home entertainment sys-

tems

• Set the output voltage of a voltage regulator

• Provide the variable DC bias for tuners in RF

wireless systems

• Trim the resistance in Wheatstone bridge circuits

• Control the gain, characteristic frequency and

Q-factor in filter circuits

• Set the operating points in temperature control

systems

• Set the scale factor and zero point in sensor signal

conditioning circuits

• Control the operating point for sensors in industrial

systems

• Vary the frequency and duty cycle of timer ICs

• Trim offset and gain errors in artificial intelligent

systems

• Vary the dc biasing of a pin diode attenuator in RF cir-

cuits

• Provide a control variable (I, V, or R) in feedback

circuits

FN8173 Rev.4.00

April 17, 2007

Page 3 of 24

X9269

PIN CONFIGURATION

SOIC/TSSOP

A3

NC

1

2

24

23

22

21

20

19

18

17

16

SCL

NC

A0

NC

3

NC

4

5

6

X9269

V

7

CC

SS

R

8

W1

L0

R

H0

9

H1

R

W0

A2

10

11

12

15

14

L1

A1

WP

13

SDA

PIN ASSIGNMENTS

(SOIC/TSSOP)

Symbol

NC

Function

1

2

No Connect

A0

Device Address for 2-Wire bus.

No Connect

3

NC

4

NC

No Connect

5

NC

No Connect

6

NC

No Connect

7

V

System Supply Voltage

Low Terminal for Potentiometer 0.

High Terminal for Potentiometer 0.

Wiper Terminal for Potentiometer 0.

Device Address for 2-Wire bus.

Hardware Write Protect

CC

8

R

L0

H0

W0

9

R

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

R

A2

WP

SDA

A1

Serial Data Input/Output for 2-Wire bus.

Device Address for 2-Wire bus.

Low Terminal for Potentiometer 1.

High Terminal for Potentiometer 1.

Wiper Terminal for Potentiometer 1.

System Ground

R

L1

H1

W1

R

V

SS

NC

SCL

A3

No Connect

Serial Clock for 2-Wire bus.

Device Address for 2-Wire bus.

FN8173 Rev.4.00

April 17, 2007

Page 4 of 24

X9269

PIN DESCRIPTIONS

Bus Interface Pins

SERIAL DATA INPUT/OUTPUT (SDA)

Potentiometer Pins

R , R

H

L

The R and R pins are equivalent to the terminal

H

L

connections on a mechanical potentiometer. Since there

are 2 potentiometers, there are 2 sets of R and R

The SDA is a bidirectional serial data input/output pin for

a 2-Wire slave device and is used to transfer data into

and out of the device. It receives device address,

opcode, wiper register address and data sent from an 2-

Wire master at the rising edge of the serial clock SCL,

and it shifts out data after each falling edge of the serial

clock SCL.

H

L

such that R

so on.

and R are the terminals of POT 0 and

H0

L0

R

W

The wiper pin are equivalent to the wiper terminal of a

mechanical potentiometer. Since there are

potentiometers, there are 2 sets of R such that R

4

is

It is an open drain output and may be wire-ORed with

any number of open drain or open collector outputs. An

open drain output requires the use of a pull-up resistor.

For selecting typical values, refer to the guidelines for

calculating typical values on the bus pull-up resistors

graph.

W

W0

the terminal of POT 0 and so on.

Bias Supply Pins

SYSTEM SUPPLY VOLTAGE (V ) AND SUPPLY

CC

GROUND (V

)

SS

SERIAL CLOCK (SCL)

The V

is the system ground.

pin is the system supply voltage. The V

SS

CC

This input is used by 2-Wire master to supply 2-Wire

serial clock to the X9269.

Other Pins

DEVICE ADDRESS (A3 - A0)

NO CONNECT

The address inputs are used to set the least significant 4

bits of the 8-bit slave address. A match in the slave

address serial data stream must be made with the

Address input in order to initiate communication with the

X9269. A maximum of 16 devices may occupy the 2-

Wire serial bus.

No connect pins should be left open. This pins are used

for Intersil manufacturing and testing purposes.

HARDWARE WRITE PROTECT INPUT (WP)

The WP pin when LOW prevents nonvolatile writes to

the Data Registers.

FN8173 Rev.4.00

April 17, 2007

Page 5 of 24

X9269

PRINCIPLES OF OPERATION

At both ends of each array and between each resistor

segment is a CMOS switch connected to the wiper (R )

output. Within each individual array only one switch may

be turned on at a time.

W

The X9269 is a integrated microcircuit incorporating four

resistor arrays and their associated registers and

counters and the serial interface logic providing direct

communication between the host and the digitally

controlled potentiometers. This section provides detail

description of the following:

These switches are controlled by a Wiper Counter

Register (WCR). The 8-bits of the WCR (WCR[7:0]) are

decoded to select, and enable, one of 256 switches (See

Table 1).

– Resistor Array Description

The WCR may be written directly. These Data Registers

can the WCR can be read and written by the host

system.

– Serial Interface Description

– Instruction and Register Description.

Array Description

Power-up and Down Requirements.

The X9269 is comprised of a resistor array (See Figure

1). Each array contains 255 discrete resistive segments

that are connected in series. The physical ends of each

array are equivalent to the fixed terminals of a mechanical

There are no restrictions on the power-up or power-

down conditions of V

potentiometer pins provided that V

and the voltages applied to the

is always more

positive than or equal to V , V , and V , i.e., V V ,

CC

W

H

L

CC

V , V . The V ramp rate specification is always in

CC

H

potentiometer (R and R inputs).

H

L

W

effect.

Figure 1. Detailed Potentiometer Block Diagram

One of Two Potentiometers

SERIAL DATA PATH

SERIAL

R

H

BUS

FROM INTERFACE

CIRCUITRY

INPUT

C

O

U

N

T

REGISTER 0

(DR0)

REGISTER 1

(DR1)

8

PARALLEL

BUS

INPUT

E

R

REGISTER 2

(DR2)

REGISTER 3

(DR3)

D

E

C

O

D

E

WIPER

COUNTER

REGISTER

(WCR)

INC/DEC

LOGIC

IF WCR = 00[H] THEN R = R

W

L

UP/DN

CLK

IF WCR = FF[H] THEN R = R

W

H

R

MODIFIED SCL

L

W

FN8173 Rev.4.00

April 17, 2007

Page 6 of 24

X9269

SERIAL INTERFACE DESCRIPTION

Serial Interface

Stop Condition

All communications must be terminated by a stop

condition, which is a LOW to HIGH transition of SDA

while SCL is HIGH. See Figure 2.

The X9269 supports a bidirectional bus oriented

protocol. The protocol defines any device that sends

data onto the bus as a transmitter and the receiving

device as the receiver. The device controlling the

transfer is a master and the device being controlled is

the slave. The master will always initiate data transfers

and provide the clock for both transmit and receive

operations. Therefore, the X9269 will be considered a

slave device in all applications.

Acknowledge

Acknowledge is a software convention used to provide a

positive handshake between the master and slave

devices on the bus to indicate the successful receipt of

data. The transmitting device, either the master or the

slave, will release the SDA bus after transmitting eight

bits. The master generates a ninth clock cycle and

during this period the receiver pulls the SDA line LOW to

acknowledge that it successfully received the eight bits

of data.

Clock and Data Conventions

Data states on the SDA line can change only during SCL

LOW periods. SDA state changes during SCL HIGH are

reserved for indicating start and stop conditions. See

Figure 2.

The X9269 will respond with an acknowledge after

recognition of a start condition and its slave address and

once again after successful receipt of the command

byte. If the command is followed by a data byte the

X9269 will respond with a final acknowledge. See Figure

2.

Start Condition

All commands to the X9269 are preceded by the start

condition, which is a HIGH to LOW transition of SDA

while SCL is HIGH. The X9269 continuously monitors

the SDA and SCL lines for the start condition and will not

respond to any command until this condition is met. See

Figure 2.

Figure 2. Acknowledge Response from Receiver

SCL FROM

MASTER

1

8

9

DATA

OUTPUT

FROM

TRANSMITTER

DATA

OUTPUT

FROM

RECEIVER

START

ACKNOWLEDGE

FN8173 Rev.4.00

April 17, 2007

Page 7 of 24

X9269

Acknowledge Polling

INSTRUCTION AND REGISTER DESCRIPTION

Instructions

The disabling of the inputs, during the internal

nonvolatile write operation, can be used to take

advantage of the typical 5ms EEPROM write cycle time.

Once the stop condition is issued to indicate the end of

the nonvolatile write command the X9269 initiates the

internal write cycle. ACK polling, Flow 1, can be initiated

immediately. This involves issuing the start condition

followed by the device slave address. If the X9269 is still

busy with the write operation no ACK will be returned. If

the X9269 has completed the write operation an ACK

will be returned and the master can then proceed with

the next operation.

DEVICE ADDRESSING: IDENTIFICATION BYTE (ID AND A)

The first byte sent to the X9269 from the host is called

the Identification Byte. The most significant four bits of

the slave address are a device type identifier. The

ID[3:0] bits is the device id for the X9269; this is fixed as

0101[B] (refer to Table 1).

The A[3:0] bits in the ID byte is the internal slave

address. The physical device address is defined by the

state of the A3-A0 input pins. The slave address is

externally specified by the user. The X9269 compares

the serial data stream with the address input state; a

successful compare of both address bits is required for

the X9269 to successfully continue the command

sequence. Only the device which slave address

matches the incoming device address sent by the

master executes the instruction. The A3 - A0 inputs can

FLOW 1: ACK Polling Sequence

Nonvolatile Write

Command Completed

EnterACK Polling

Issue

START

be actively driven by CMOS input signals or tied to V

CC

or V

.

SS

INSTRUCTION BYTE (I)

Issue Slave

Issue STOP

Address

The next byte sent to the X9269 contains the instruction

and register pointer information. The three most

significant bits are used provide the instruction opcode I

[3:0]. The RB and RA bits point to one of the four Data

Registers of each associated XDCP. The least

significant bit points to one of two Wiper Counter

Registers or Pots. The format is shown in Table 2.

ACK

Returned?

No

Yes

No

Further

Operation?

Register Selection

Yes

Register Selected

RB

0

RA

0

Issue

Instruction

DR0

DR1

DR2

DR3

Issue STOP

Proceed

0

1

0

Proceed

1

FN8173 Rev.4.00

April 17, 2007

Page 8 of 24

X9269

Table 1. Identification Byte Format

Device Type

Identifier

Slave Address

ID3

0

ID2

1

ID1

0

ID0

1

A3

A2

A1

A0

(MSB)

(LSB)

Table 2. Instruction Byte Format

Instruction

Opcode

Register

Selection

Pot Selection

(WCR Selection)

I3

I2

I1

I0

RB

RA

0

P0

(MSB)

(LSB)

Table 3. Instruction Set

Instruction

Instruction Set

I3 I2 I1 I0 RB RA

0

P0

Operation

Read Wiper Counter

Register

1

0

1

0

1

0

1

0

1

0

1

0

1/0 Read the contents of the Wiper Counter

Register pointed to by P0

Write Wiper Counter Register

0

1/0 Write new value to the Wiper Counter

Register pointed to by P0

Read Data Register

1/0 1/0

1/0 Read the contents of the Data Register

pointed to by P0 and RB - RA

Write Data Register

1/0 Write new value to the Data Register

pointed to by P0 and RB - RA

XFR Data Register to Wiper

Counter Register

1/0 Transfer the contents of the Data Register

pointed to by P0 and RB - RA to its

associated Wiper Counter Register

XFR Wiper Counter Register

to Data Register

1

0

1

0

1

0

1

0

1

0

1

0

1/0 1/0

0

1/0 Transfer the contents of the Wiper Counter

Register pointed to by P0 to the Data

Register pointed to by RB - RA

Global XFR Data Registers to

Wiper Counter Registers

0

Transfer the contents of the Data Registers

pointed to by RB - RA of all four pots to their

respective Wiper Counter Registers

Global XFR Wiper Counter

Registers to Data Register

0

Transfer the contents of both Wiper Counter

Registers to their respective data Registers

pointed to by RB - RA of all four pots

Increment/Decrement Wiper

Counter Register

0

1/0 Enable Increment/decrement of the Control

Latch pointed to by P0

Note: 1/0 = data is one or zero

FN8173 Rev.4.00

April 17, 2007

Page 9 of 24

X9269

DEVICE DESCRIPTION

Wiper Counter Register (WCR)

are recommended to ensure proper loadings of the DR0

value into the WCR (See Design Considerations

Section).

The X9269 contains two Wiper Counter Registers, one

for each DCP potentiometer. The Wiper Counter

Register can be envisioned as a 8-bit parallel and serial

load counter with its outputs decoded to select one of

256 switches along its resistor array. The contents of the

WCR can be altered in four ways: it may be written

directly by the host via the Write Wiper Counter Register

instruction (serial load); it may be written indirectly by

transferring the contents of one of four associated data

registers via the XFR Data Register instruction (parallel

load); it can be modified one step at a time by the

Increment/Decrement instruction (See Instruction

section for more details). Finally, it is loaded with the

contents of its Data Register zero (DR0) upon power-up.

Data Registers (DR)

Each potentiometer has four 8-bit nonvolatile Data

Registers. These can be read or written directly by the

host. Data can also be transferred between any of the

four Data Registers and the associated Wiper Counter

Register. All operations changing data in one of the data

registers is a nonvolatile operation and will take a

maximum of 10ms.

If the application does not require storage of multiple

settings for the potentiometer, the Data Registers can be

used as regular memory locations for system

parameters or user preference data.

Bit [7:0] are used to store one of the 256 wiper positions

(0~255).

The Wiper Counter Register is a volatile register; that is,

its contents are lost when the X9269 is powered-down.

Although the register is automatically loaded with the

value in DR0 upon power-up, this may be different from

the value present at power-down. Power-up guidelines

Table 4. Wiper counter Register, WCR (8-bit), WCR[7:0]: Used to store the current wiper position (Volatile, V).

WCR7

V

WCR6

V

WCR5

V

WCR4

V

WCR3

V

WCR2

V

WCR1

V

WCR0

V

(MSB)

(LSB)

Table 5. Data Register, DR (8-bit), Bit [7:0]: Used to store wiper positions or data (Nonvolatile, NV).

Bit 7

NV

Bit 6

NV

Bit 5

NV

Bit 4

NV

Bit 3

NV

Bit 2

NV

Bit 1

NV

Bit 0

NV

MSB

LSB

FN8173 Rev.4.00

April 17, 2007

Page 10 of 24

X9269

DEVICE DESCRIPTION

Instructions

– XFR Data Register to Wiper Counter Register –

This transfers the contents of one specified Data Reg-

ister to the associated Wiper Counter Register.

Four of the nine instructions are three bytes in length.

These instructions are:

– XFR Wiper Counter Register to Data Register –

This transfers the contents of the specified Wiper

Counter Register to the specified associated Data

Register.

– Read Wiper Counter Register – read the current

wiper position of the selected potentiometer,

– Global XFR Data Register to Wiper Counter

Register – This transfers the contents of all specified

Data Registers to the associated Wiper Counter Reg-

isters.

– Write Wiper Counter Register – change current

wiper position of the selected potentiometer,

– Read Data Register – read the contents of the

selected Data Register;

– Global XFR Wiper Counter Register to Data

Register – This transfers the contents of all Wiper

Counter Registers to the specified associated Data

Registers.

– Write Data Register – write a new value to the

selected Data Register.

The basic sequence of the three byte instructions is

illustrated in Figure 4. These three-byte instructions

exchange data between the WCR and one of the Data

Registers. A transfer from a Data Register to a WCR is

essentially a write to a static RAM, with the static RAM

controlling the wiper position. The response of the wiper

INCREMENT/DECREMENT COMMAND

The final command is Increment/Decrement (Figure 5

and 6). The Increment/Decrement command is different

from the other commands. Once the command is issued

and the X9269 has responded with an acknowledge, the

master can clock the selected wiper up and/or down in

one segment steps; thereby, providing a fine tuning

to this action will be delayed by t

. A transfer from the

WRL

WCR (current wiper position), to a Data Register is a

write to nonvolatile memory and takes a minimum of t

WR

to complete. The transfer can occur between one of the

four potentiometers and one of its associated registers;

or it may occur globally, where the transfer occurs

between all potentiometers and one associated register.

capability to the host. For each SCL clock pulse (t

)

HIGH

while SDA is HIGH, the selected wiper will move one

resistor segment towards the R terminal. Similarly, for

H

each SCL clock pulse while SDA is LOW, the selected

wiper will move one resistor segment towards the R

terminal.

Four instructions require a two-byte sequence to

complete. These instructions transfer data between the

host and the X9269; either between the host and one of

the data registers or directly between the host and the

Wiper Counter Register. These instructions are:

L

See Instruction format for more details.

FN8173 Rev.4.00

April 17, 2007

Page 11 of 24

X9269

Figure 3. Two-Byte Instruction Sequence

SCL

SDA

0

1

0

1

ID3 ID2 ID1 ID0

S

A2 A1 A0

S

T

A

R

T

A3

A I3 I2 I1

P0

I0

RB RA 0

A

C

K

C

K

T

O

P

External

Address

Instruction

Opcode

Register

Address

Pot/WCR

Address

Device ID

Figure 4. Three-Byte Instruction Sequence

SCL

SDA

0

1

0

1

0

S

T

A

R

T

I3

A

C

K

I1

P0

A

C

K

D7 D6 D5 D4 D3 D2 D1 D0

A

C

K

S

T

ID3 ID2

ID0

I2

I0 RB RA

ID1

A3 A2 A1 A0

O

P

External

Address

Device ID

WCR[7:0]

or

Data Register D[7:0]

Instruction

Opcode

Register

Address

Pot/WCR

Address

Figure 5. Increment/Decrement Instruction Sequence

SCL

0

1

0

1

SDA

0

ID3 ID2 ID1 ID0

Device ID

I1

A3 A2 A1 A0

I3

I2

I0

RB RA 0

P0

S

T

A

R

T

A

C

K

A

C

K

I

D

E

C

1

S

T

I

D

N

C

1

N

C

2

N

C

n

E

C

n

External

Address

Instruction

Opcode

Pot/WCR

Address

Register

Address

O

P

Figure 6. Increment/Decrement Timing Limits

INC/DEC

CMD

Issued

t

WRID

SCL

SDA

Voltage Out

R

W

FN8173 Rev.4.00

April 17, 2007

Page 12 of 24

X9269

INSTRUCTION FORMAT

Read Wiper Counter Register (WCR)

Device Type

Identifier

Device

Addresses

Instruction

Opcode

DR/WCR

Addresses

Wiper Position

(Sent by X9269 on SDA)

S

T

A

R

T

S

A

C

K

S

A

C

K

M S

A T

C O

K P

W

C

R

W

C

R

7

W W W W W W

C C C C C C

R R R R R R

0

1

0

1 A3 A2 A1 A0

1

0

1

0

P0

5

4 3 2 1 0

6

Write Wiper Counter Register (WCR)

Device Type

Identifier

Device

Addresses

Instruction

Opcode

DR/WCR

Addresses

Wiper Position

(Sent by Master on SDA)

S

T

A

R

T

S

A

C

K

S

A

C

K

S S

A T

C O

K P

W

C

W

C

R

7

W W W W W W

C C C C C C

R R R R R R

0

1

0

1 A3 A2 A1 A0

1

0

1

0

P0

R

5

4 3 2 1 0

6

Read Data Register (DR)

Device Type

Identifier

Device

Addresses

Instruction

Opcode

DR/WCR

Addresses

Wiper Position

(Sent by X9269 on SDA)

S

T

A

R

T

S

A

C

K

S

A

C

K

M S

A T

C O

K P

W

C

W

C

R

7

W W W W W W

C C C C C C

R R R R R R

0

1

0

1

A3 A2 A1 A0

1

0

1

1 RB RA

0

P0

R

5

4 3 2 1 0

6

Write Data Register (DR)

Device Type

Identifier

Device

Addresses

Instruction

Opcode

DR/WCR

Addresses

Wiper Position

(Sent by Master on SDA)

S

T

A

R

T

S

A

C

K

S

S S

A T

C O

K P

A

C

K

W

C

W

C

R

7

W W W W W W

C C C C C C

R R R R R R

0

1

0

1 A3 A2 A1 A0

1

0

0 RB RA

0

P0

R

5

4 3 2 1 0

6

Global XFR Data Register (DR) to Wiper Counter Register (WCR)

S

T

A

R

T

Device Type

Identifier

Device

Addresses

Instruction

Opcode

DR/WCR

Addresses

S

A

C

K

S S

A

T

C O

K P

0

1

0

1

A3 A2 A1 A0

0

1

RB RA

0

FN8173 Rev.4.00

April 17, 2007

Page 13 of 24

X9269

Global XFR Wiper Counter Register (WCR) to Data Register (DR)

S

T

A

R

T

Device Type

Identifier

Device

Addresses

Instruction

Opcode

DR/WCR

Addresses

S

A

C

K

S S

A T

C O

K P

HIGH-VOLTAGE

WRITE CYCLE

0

1

0

1

A3 A2 A1 A0

1

0

0 RB RA 0

0

Transfer Wiper Counter Register (WCR) to Data Register (DR)

S

T

A

R

T

Device Type

Identifier

Device

Addresses

Instruction

Opcode

DR/WCR

Addresses

S

A

C

K

S S

A T HIGH-VOLTAGE

C O WRITE CYCLE

P0

K P

0

1

0

1

A3 A2 A1 A0

1

0 RB RA

0

Transfer Data Register (DR) to Wiper Counter Register (WCR)

S

T

A

R

T

Device Type

Identifier

Device

Addresses

Instruction

Opcode

DR/WCR

Addresses

S

A

C

K

S S

A T

C O

K P

0

1

0

1

A3 A2 A1 A0

1

0

1 RB RA

0

P0

Increment/Decrement Wiper Counter Register (WCR)

S Device Type

Device

Addresses

Instruction

Opcode

DR/WCR

Addresses

Increment/Decrement

(Sent by Master on SDA)

S

A

C

K

S

A

C

K

S

T

O

P

T

A

R

T

Identifier

0

1

0

1 A3 A2 A1 A0

0

1

0

P0

I/D I/D

.

I/D I/D

Notes: (1) “MACK”/”SACK”: stands for the acknowledge sent by the master/slave.

(2) “A3 ~ A0”: stands for the device addresses sent by the master.

(3) “X”: indicates that it is a “0” for testing purpose but physically it is a “don’t care” condition.

(4) “I”: stands for the increment operation, SDA held high during active SCL phase (high).

(5) “D”: stands for the decrement operation, SDA held low during active SCL phase (high).

FN8173 Rev.4.00

April 17, 2007

Page 14 of 24

X9269

ABSOLUTE MAXIMUM RATINGS

COMMENT

Temperature under bias.................... -65C to +135C

Storage temperature ......................... -65C to +150C

Voltage on SCL, SDA any address input

Stresses above those listed under “Absolute Maximum

Ratings” may cause permanent damage to the device.

This is a stress rating only; the functional operation of

the device (at these or any other conditions above those

listed in the operational sections of this specification) is

not implied. Exposure to absolute maximum rating

conditions for extended periods may affect device

reliability.

with respect to V ................................. -1V to +7V

SS

V = | (V - V ) |...................................................5.5V

H

L

Lead temperature (soldering, 10 seconds)........ 300C

(10 seconds) .................................................±6mA

I

W

RECOMMENDED OPERATING CONDITIONS

(4)

Temp

Min.

0C

-40C

Max.

+70C

+85C

Device

X9261

Supply Voltage (V

CC

)

Limits

Commercial

Industrial

5V 10%

2.7V to 5.5V

X9261-2.7

POTENTIOMETER CHARACTERISTICS (Over recommended industrial (2.7V) operating conditions unless otherwise stated.)

Limits

Symbol

Parameter

End to End Resistance

Min.

Typ.

100

50

Max.

Units

k

Test Conditions

T version

R

TOTAL

R

k

U version

TOTAL

End to End Resistance

Tolerance

±20

%

Power Rating

50

±3

mW

mA



25C, each pot

I

Wiper Current

W

R

Wiper Resistance

300

150

I

=  3mA @ V

= 3V

= 5V

W

CC



W

V

Voltage on any R or R Pin

V

= 0V

TERM

H

L

SS

CC

SS

Ref: 1V

Noise

-120

0.4

dBV

%

Resolution

(1)

(2)

(3)

(5)

Absolute Linearity

Relative Linearity

±1

MI

R

- R

w(n)(actual)

- [R

w(n)(expected)

(5)

(3)

MI

±0.6

]

w(n) + MI

w(n + 1)

Temperature Coefficient of

300

ppm/C

R

TOTAL

Ratiometric Temp. Coefficient

Potentiometer Capacitances

20

ppm/°C

pF

C /C /C

W

10/10/25

0.1

See Macro model

Device in stand by.

H

L

I

R , R , R Leakage

10.0

µA

al

W

H

L

Vin = V to V

SS CC

Notes: (1) Absolute linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used as a

potentiometer.

(2) Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a

potentiometer. It is a measure of the error in step size.

(3) MI = RTOT / 255 or (R - R ) / 255, single pot

H

L

(4) During power-up V

> V , V , and V .

CC

(5) n = 0, 1, 2, …,255; m =0, 1, 2, …, 254.

H L W

FN8173 Rev.4.00

April 17, 2007

Page 15 of 24

X9269

D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.)

Limits

Symbol

Parameter

Min.

Typ.

Max.

Units

Test Conditions

= 400kHz; V = +6V;

SDA = Open; (for 2-Wire, Active, Read and

I

V

supply current

(active)

400

µA

f

SCL

CC1

CC2

SB

CC

Volatile Write States only)

V

supply current

1

5

mA

f

= 400kHz; V

= +6V;

CC

(nonvolatile write)

SCL

SDA = Open; (for 2-Wire, Active,

Nonvolatile Write State only)

V

current (standby)

A

V

= +6V; V = V or V ; SDA = V ;

IN SS CC CC

CC

(for 2-Wire, Standby State only)

I

Input leakage current

Output leakage cur-

Input HIGH voltage

Input LOW voltage

Output LOW voltage

Output HIGH voltage

10

A

V

= V to V

SS CC

LI

IN

= V to V

SS CC

LO

OUT

V

x 0.7

V

+ 1

IH

CC

-1

CC

x 0.3

V

IL

CC

0.4

V

I

= 3mA

OL

OH

OL

OH

V

- 0.8

V

= -1mA, V

CC

= -0.4mA, V

CC

+3V

 +3V

CC

- 0.4

V

ENDURANCE AND DATA RETENTION

Parameter

Minimum endurance

Data retention

Min.

Units

100,000

100

Data changes per bit per register

years

CAPACITANCE

Symbol

Test

Input / Output capacitance (SDA)

Input capacitance (SCL, WP, A3, A2, A1 and A0)

Max.

Units

pF

Test Conditions

= 0V

(6)

C

8

6

V

IN/OUT

(6)

OUT

V = 0V

IN

pF

IN

POWER-UP TIMING

Symbol

Parameter

Power-up rate

Min.

Max.

50

Units

V/ms

ms

(6)

t V

CC

V

0.2

r

CC

Power-up to initiation of read operation

(7)

t

1

PUR

POWER-UP AND DOWN REQUIREMENTS

The are no restrictions on the power-up or power-down conditions of V

and the voltages applied to the poten-

V , V , V . The

CC

is always more positive than or equal to V , V , and V , i.e., V

tiometer pins provided that V

CC

power-up timing spec is always in effect.

H

L

W

CC

H

L

W

V

CC

A.C. TEST CONDITIONS

Input Pulse Levels

V

x 0.1 to V x 0.9

CC

Input rise and fall times

Input and output timing level

10ns

V

x 0.5

CC

Notes: (6) This parameter is not 100% tested

(7) t and t are the delays required from the time the (last) power supply (V -) is stable until the specific instruction can be issued.

PUR

PUW

CC

These parameters are periodically sampled and not 100% tested.

FN8173 Rev.4.00

April 17, 2007

Page 16 of 24

X9269

EQUIVALENT A.C. LOAD CIRCUIT

5V

3V

867

SPICE Macromodel

1533



R

TOTAL

R

L

H

SDA pin

C

W

C

L

10pF

100pF

25pF

10pF

R

W

AC TIMING

Symbol

Parameter

Min.

Max.

Units

kHz

ns

f

t

Clock Frequency

400

SCL

Clock Cycle Time

2500

600

1300

600

100

30

CYC

Clock High Time

ns

HIGH

LOW

SU:STA

HD:STA

SU:STO

SU:DAT

HD:DAT

R

Clock Low Time

ns

Start Setup Time

ns

Start Hold Time

ns

Stop Setup Time

ns

SDA Data Input Setup Time

SDA Data Input Hold Time

SCL and SDA Rise Time

SCL and SDA Fall Time

ns

300

0.9

ns

F

SCL Low to SDA Data Output Valid Time

SDA Data Output Hold Time

s

ns

AA

0

50

1200

0

DH

T

Noise Suppression Time Constant at SCL and SDA inputs

Bus Free Time (Prior to Any Transmission)

A0, A1, A2, A3 Setup Time

ns

I

t

ns

BUF

ns

SU:WPA

HD:WPA

A0, A1, A2, A3 Hold Time

0

ns

FN8173 Rev.4.00

April 17, 2007

Page 17 of 24

X9269

HIGH-VOLTAGE WRITE CYCLE TIMING

Symbol

Parameter

Typ.

Max.

Units

t

High-voltage write cycle time (store instructions)

5

10

ms

WR

XDCP TIMING

Symbol

Parameter

Min. Max. Units

t

Wiper response time after the third (last) power supply is stable

Wiper response time after instruction issued (all load instructions)

5

10

s

WRPO

WRL

SYMBOL TABLE

WAVEFORM

INPUTS

OUTPUTS

Must be

steady

Will be

steady

May change

from Low to

High

Will change

from Low to

High

May change

from High to

Low

Will change

from High to

Low

Don’t Care:

Changes

Allowed

Changing:

State Not

Known

N/A

Center Line

is High

Impedance

FN8173 Rev.4.00

April 17, 2007

Page 18 of 24

X9269

TIMING DIAGRAMS

Start and Stop Timing

(START)

(STOP)

t

F

R

SCL

t

SU:STO

SU:STA

HD:STA

t

F

R

SDA

Input Timing

t

CYC

HIGH

SCL

SDA

t

LOW

t

BUF

SU:DAT

HD:DAT

Output Timing

SCL

SDA

t

DH

AA

FN8173 Rev.4.00

April 17, 2007

Page 19 of 24

X9269

XDCP Timing (for All Load Instructions)

(STOP)

SCL

SDA

VWx

LSB

t

WRL

Write Protect and Device Address Pins Timing

(START)

(STOP)

SCL

...

(Any Instruction)

...

SDA

...

t

SU:WPA

HD:WPA

WP

A0, A1

FN8173 Rev.4.00

April 17, 2007

Page 20 of 24

X9269

APPLICATIONS INFORMATION

Basic Configurations of Electronic Potentiometers

+V

R

V

R

RW

I

Three terminal Potentiometer;

Variable voltage divider

Two terminal Variable Resistor;

Variable current

Application Circuits

Noninverting Amplifier

Voltage Regulator

V

+

–

S

V

V (REG)

O

317

O

IN

R

1

R

2

I

adj

R

1

2

V

= (1+R /R )V

V

(REG) = 1.25V (1+R /R )+I

R

adj 2

O

2

1

S

O

2

1

Offset Voltage Adjustment

Comparator with Hysterisis

R

2

1

V

–

+

S

V

S

O

100k

–

+

V

O

TL072

10k

R

1

2

10k

+12V

V

CC

V

= {R /(R +R )} V (max)

1 1 2 O

UL

RL = {R /(R +R )} V (min)

10k

-12V

L

1

2

O

10k

FN8173 Rev.4.00

April 17, 2007

Page 21 of 24

X9269

Application Circuits (continued)

Attenuator

Filter

C

V

+

–

S

R

V

R

2

O

1

3

–

+

R

V

O

V

S

R

2

R

4

R = R = R = R = 10k

1

2

3

4

R

1

G

= 1 + R /R

2 1

V

= G V

S

O

fc = 1/(2RC)

-1/2  G  +1/2

Inverting Amplifier

Equivalent L-R Circuit

R

2

1

V

S

R

2

C

1

–

+

V

+

–

S

V

O

R

1

Z

IN

V

= G V

S

O

G = - R /R

2

1

3

Z

= R + s R (R + R ) C = R + s Leq

2 2 1 3 1 2

IN

(R + R ) >> R

1

3

2

Function Generator

C

R

1

2

–

+

–

+

R

}

A

}

B

frequency  R , R , C

1

2

amplitude  R , R

A

B

FN8173 Rev.4.00

April 17, 2007

Page 22 of 24

X9269

Small Outline Plastic Packages (SOIC)

M24.3 (JEDEC MS-013-AD ISSUE C)

N

24 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE

INDEX

AREA

0.25(0.010)

M

B M

H

INCHES

MILLIMETERS

E

SYMBOL

MIN

MAX

MIN

2.35

0.10

0.33

0.23

MAX

2.65

NOTES

-B-

A

A1

B

C

D

E

e

0.0926

0.0040

0.013

0.1043

0.0118

0.020

-

0.30

-

1

2

3

L

0.51

9

SEATING PLANE

A

0.0091

0.5985

0.2914

0.0125

0.32

-

-A-

0.6141 15.20

15.60

7.60

3

h x 45°

D

0.2992

7.40

4

-C-

0.05 BSC

1.27 BSC

-



H

h

0.394

0.010

0.016

0.419

0.029

0.050

10.00

0.25

0.40

10.65

0.75

1.27

-

e

A1

C

5

B

0.10(0.004)

L

6

0.25(0.010) M

C

A M B S

N



24

7

0°

8°

0°

8°

-

NOTES:

1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of

Publication Number 95.

Rev. 1 4/06

2. Dimensioning and tolerancing per ANSI Y14.5M-1982.

3. Dimension “D” does not include mold flash, protrusions or gate burrs.

Mold flash, protrusion and gate burrs shall not exceed 0.15mm

(0.006 inch) per side.

4. Dimension “E” does not include interlead flash or protrusions. Inter-

lead flash and protrusions shall not exceed 0.25mm (0.010 inch) per

side.

5. The chamfer on the body is optional. If it is not present, a visual index

feature must be located within the crosshatched area.

6. “L” is the length of terminal for soldering to a substrate.

7. “N” is the number of terminal positions.

8. Terminal numbers are shown for reference only.

9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater

above the seating plane, shall not exceed a maximum value of

0.61mm (0.024 inch)

10. Controlling dimension: MILLIMETER. Converted inch dimensions

are not necessarily exact.

FN8173 Rev.4.00

April 17, 2007

Page 23 of 24

X9269

Thin Shrink Small Outline Package Family (TSSOP)

MDP0044

0.25 M C A B

N

THIN SHRINK SMALL OUTLINE PACKAGE FAMILY

D

A

(N/2)+1

MILLIMETERS

SYMBOL 14 LD 16 LD 20 LD 24 LD 28 LD TOLERANCE

A

A1

A2

b

1.20

0.10

0.90

0.25

0.15

5.00

6.40

4.40

0.65

0.60

1.00

1.20

0.10

0.90

0.25

0.15

5.00

6.40

4.40

0.65

0.60

1.00

1.20

0.10

0.90

0.25

0.15

6.50

6.40

4.40

0.65

0.60

1.00

1.20

0.10

0.90

0.25

0.15

7.80

6.40

4.40

0.65

0.60

1.00

1.20

0.10

0.90

0.25

0.15

9.70

6.40

4.40

0.65

0.60

1.00

Max

±0.05

PIN #1 I.D.

E

E1

±0.05

+0.05/-0.06

±0.10

0.20 C B A

2X

1

(N/2)

c

N/2 LEAD TIPS

B

D

TOP VIEW

E

Basic

E1

e

±0.10

Basic

0.05

H

e

L

±0.15

C

L1

Reference

Rev. F 2/07

SEATING

PLANE

NOTES:

0.10 M C A B

b

1. Dimension “D” does not include mold flash, protrusions or gate

burrs. Mold flash, protrusions or gate burrs shall not exceed

0.15mm per side.

0.10 C

N LEADS

SIDE VIEW

2. Dimension “E1” does not include interlead flash or protrusions.

Interlead flash and protrusions shall not exceed 0.25mm per

side.

SEE DETAIL “X”

3. Dimensions “D” and “E1” are measured at dAtum Plane H.

4. Dimensioning and tolerancing per ASME Y14.5M-1994.

c

END VIEW

L1

A2

A

GAUGE

PLANE

0.25

L

A1

0° - 8°

DETAIL X

All trademarks and registered trademarks are the property of their respective owners.

For additional products, see www.intersil.com/en/products.html

Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted

in the quality certifications found at www.intersil.com/en/support/qualandreliability.html

Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such

modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are

current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its

subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or

otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

FN8173 Rev.4.00

April 17, 2007

Page 24 of 24

是否Rohs认证：	不符合	生命周期：	Obsolete
零件包装代码：	SOIC	包装说明：	0.300 INCH, PLASTIC, SOIC-24
针数：	24	Reach Compliance Code：	not_compliant
ECCN代码：	EAR99	HTS代码：	8542.39.00.01
风险等级：	5.76	其他特性：	NONVOLATILE MEMORY
控制接口：	2-WIRE SERIAL	转换器类型：	DIGITAL POTENTIOMETER
JESD-30 代码：	R-PDSO-G24	长度：	15.4 mm
功能数量：	2	位置数：	256
端子数量：	24	最高工作温度：	70 °C
最低工作温度：		封装主体材料：	PLASTIC/EPOXY
封装代码：	SOP	封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE	认证状态：	Not Qualified
电阻定律：	LINEAR	最大电阻容差：	20%
最大电阻器端电压：	3 V	最小电阻器端电压：
座面最大高度：	2.65 mm	标称供电电压：	3 V
表面贴装：	YES	技术：	CMOS
标称温度系数：	300 ppm/°C	温度等级：	COMMERCIAL
端子形式：	GULL WING	端子节距：	1.27 mm
端子位置：	DUAL	标称总电阻：	100000 Ω
宽度：	7.5 mm	Base Number Matches：	1

型号	制造商	描述	价格	文档
X9269TS24I	INTERSIL	Single Supply/Low Power/256-Tap/2-Wire Bus	获取价格
X9269TS24I	XICOR	Dual Digitally-Controlled Potentiometers	获取价格
X9269TS24I-2.7	INTERSIL	Single Supply/Low Power/256-Tap/2-Wire Bus	获取价格
X9269TS24I-2.7	XICOR	Dual Digitally-Controlled Potentiometers	获取价格
X9269TS24I-2.7T1	RENESAS	DUAL 100K DIGITAL POTENTIOMETER, 2-WIRE SERIAL CONTROL INTERFACE, 256 POSITIONS, PDSO24, 0.300 INCH, PLASTIC, SOIC-24	获取价格
X9269TS24IT1	XICOR	Digital Potentiometer, 2 Func, 100000ohm, 2-wire Serial Control Interface, 256 Positions, CMOS, PDSO24, PLASTIC, SOIC-24	获取价格
X9269TS24IZ	INTERSIL	Dual Digitally-Controlled Potentiometers	获取价格
X9269TS24IZ-2.7	INTERSIL	Dual Digitally-Controlled Potentiometers	获取价格
X9269TS24Z	INTERSIL	Dual Digitally-Controlled Potentiometers	获取价格
X9269TS24Z-2.7	INTERSIL	Dual Digitally-Controlled Potentiometers	获取价格

X9269TS24-2.7T1

X9269TS24-2.7T1 概述

X9269TS24-2.7T1 规格参数

X9269TS24-2.7T1 数据手册

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