X9279UV14-2.7T1 [RENESAS]
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| 型号： | X9279UV14-2.7T1 |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
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X9279
Single Supply/Low Power/256-Tap/2-Wire Bus
September 23, 2009
FN8175.4
Single Digitally-Controlled (XDCP™)
Potentiometer
Features
• 256 Resistor Taps
The X9279 integrates a single digitally controlled
potentiometer (XDCP) on a monolithic CMOS integrated
circuit.
• 2-Wire Serial Interface for Write, Read, and Transfer
Operations of the Potentiometer
• Wiper Resistance, 100 Typical @ 5V
The digital controlled potentiometer is implemented using
255 resistive elements in a series array. Between each
element are tap points connected to the wiper terminal
through switches. The position of the wiper on the array is
controlled by the user through the 2-Wire bus interface. The
potentiometer has associated with it a volatile Wiper Counter
Register (WCR) and a four non-volatile Data Registers that
can be directly written to and read by the user. The contents
of the WCR controls the position of the wiper on the resistor
array though the switches. Power-up recalls the contents of
the default data register (DR0) to the WCR.
• 16 Non-volatile Data Registers for Each Potentiometer
• Non-volatile Storage of Multiple Wiper Positions
• Power-on Recall. Loads Saved Wiper Position on
Power-up.
• Standby Current < 5µA Max
• V : 2.7V to 5.5V Operation
CC
• 50k, 100k Versions of End-to-End Resistance
• Endurance: 100,000 Data Changes per Bit per Register
• 100 yr. Data Retention
The XDCP can be used as a three-terminal potentiometer or
as a two terminal variable resistor in a wide variety of
applications including control, parameter adjustments, and
signal processing.
• 14 Ld TSSOP
• Low Power CMOS
• Pb-Free Available (RoHS Compliant)
Functional Diagram
V
R
H
CC
WRITE
READ
TRANSFER
INC/DEC
ADDRESS
DATA
STATUS
50k and 100k
256-TAPS
POT
POWER-ON RECALL
BUS
INTERFACE
AND
WIPER
WIPER COUNTER
REGISTER (WCR)
2-WIRE
BUS
INTERFACE
DATA REGISTERS
16 BYTES
CONTROL
CONTROL
V
R
R
L
SS
W
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
XDCP is a trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005, 2009. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
1
X9279
Ordering Information
POTENTIOMETER
ORGANIZATION
(k)
PART
NUMBER
PART
MARKING
V
LIMITS
(V)
TEMP RANGE
(°C)
PKG.
DWG. #
CC
PACKAGE
X9279TV14* (Note 2) X9279 TV
5 ±10%
100
0 to +70
0 to +70
14 Ld TSSOP (4.4mm)
M14.173
X9279TV14Z*
(Note 1)
X9279 TVZ
14 Ld TSSOP (4.4mm)
(Pb-free)
M14.173
X9279TV14I* (Note 2) X9279 TVI
-40 to +85
-40 to +85
14 Ld TSSOP (4.4mm)
M14.173
M14.173
X9279TV14IZ*
(Note 1)
X9279 TVZI
14 Ld TSSOP (4.4mm)
(Pb-free)
X9279UV14*
(Note 2)
X9279 UV
50
0 to +70
0 to +70
14 Ld TSSOP (4.4mm)
M14.173
M14.173
M14.173
M14.173
M14.173
M14.173
M14.173
M14.173
M14.173
M14.173
M14.173
M14.173
X9279UV14Z*
(Note 1)
X9279 UVZ
X9279 UVI
14 Ld TSSOP (4.4mm)
(Pb-free)
X9279UV14I*
(Note 2)
-40 to +85
-40 to +85
0 to +70
14 Ld TSSOP (4.4mm)
X9279UV14IZ*
(Note 1)
X9279 UVZI
X9279 TVF
X9279 TVZF
X9279 TVG
X9279 TVZG
X9279 UVF
X9279 UVZF
X9279 UVG
X9279 UVZG
14 Ld TSSOP (4.4mm)
(Pb-free)
X9279TV14-2.7*
(Note 2)
2.7 to 5.5
100
14 Ld TSSOP (4.4mm)
X9279TV14Z-2.7*
(Note 1)
0 to +70
14 Ld TSSOP (4.4mm)
(Pb-free)
X9279TV14I-2.7*
(Note 2)
-40 to +85
-40 to +85
0 to +70
14 Ld TSSOP (4.4mm)
X9279TV14IZ-2.7*
(Note 1)
14 Ld TSSOP (4.4mm)
(Pb-free)
X9279UV14-2.7*
(Note 2)
50
14 Ld TSSOP (4.4mm)
X9279UV14Z-2.7*
(Note 1)
0 to +70
14 Ld TSSOP (4.4mm)
(Pb-free)
X9279UV14I-2.7*
(Note 2)
-40 to +85
-40 to +85
14 Ld TSSOP (4.4mm)
X9279UV14IZ-2.7*
(Note 1)
14 Ld TSSOP (4.4mm)
(Pb-free)
*Add “-T” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
NOTES:
1. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100%
matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations).
Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC
J STD-020.
2. Not recommended for new designs.
FN8175.4
September 23, 2009
2
X9279
Detailed Functional Diagram
V
CC
BANK 0 POWER-ON RECALL
R
H
DR0 DR1
WIPER
50k and 100k
COUNTER
REGISTER
(WCR)
256-TAPS
R
R
L
SCL
SDA
DR2 DR3
INTERFACE
AND
CONTROL
CIRCUITRY
W
A3
A2
A1
A0
BANK 1
BANK 2
BANK 3
DATA
DR0
DR1 DR0 DR1
DR0 DR1
WP
DR2 DR3
DR2 DR3
DR2 DR3
CONTROL
12 ADDITIONAL NON-VOLATILE REGISTERS
3 BANKS OF 4 REGISTERS x 8-BITS
V
SS
Circuit Level Applications
System Level Applications
• Vary the gain of a voltage amplifier
• Adjust the contrast in LCD displays
• Provide programmable DC reference voltages for
comparators and detectors
• Control the power level of LED transmitters in
communication systems
• Control the volume in audio circuits
• Set and regulate the DC biasing point in an RF power
amplifier in wireless systems
• Trim out the offset voltage error in a voltage amplifier
circuit
• Control the gain in audio and home entertainment systems
• Set the output voltage of a voltage regulator
• Provide the variable DC bias for tuners in RF wireless
systems
• Trim the resistance in Wheatstone bridge circuits
• Set the operating points in temperature control systems
• Control the gain, characteristic frequency and Q-factor in
filter circuits
• Control the operating point for sensors in industrial
systems
• Set the scale factor and zero point in sensor signal
conditioning circuits
• Trim offset and gain errors in artificial intelligent systems
• Vary the frequency and duty cycle of timer ICs
• Vary the DC biasing of a pin diode attenuator in RF circuits
• Provide a control variable (I, V, or R) in feedback circuits
FN8175.4
September 23, 2009
3
X9279
connected to ground for proper operation. A match in the slave
address serial data stream must be made with the Address
input in order to initiate communication with the X9279. A
maximum of 8 devices may occupy the 2-Wire serial bus.
Pinout
X9279
(14 LD TSSOP)
TOP VIEW
Potentiometer Pins
NC
A0
14
13
12
11
10
9
1
2
3
4
5
6
7
V
CC
R
R
R
L
R , R
H
L
NC
H
W
The R and R pins are equivalent to the terminal
A2
H
L
connections on a mechanical potentiometer.
SCL
SDA
A3
A1
WP
R
W
V
8
SS
The wiper pin is equivalent to the wiper terminal of a
mechanical potentiometer.
Pin Functions
Bias Supply Pins
PIN
TSSOP SYMBOL
FUNCTION
SYSTEM SUPPLY VOLTAGE (V ) AND SUPPLY
CC
1
2
NC
A0
No Connect
GROUND (V
)
SS
pin is the system supply voltage. The V pin is
Device Address for 2-Wire bus
No Connect
The V
CC
the system ground.
SS
3
NC
4
A2
Device Address for 2-Wire bus
Serial Clock for 2-Wire bus
Serial Data Input/Output for 2-Wire bus
System Ground
Other Pins
5
SCL
SDA
NO CONNECT
6
7
V
No connect pins should be left open. This pins are used for
Intersil manufacturing and testing purposes.
SS
8
WP
A1
Hardware Write Protect
9
Device Address for 2-Wire bus
HARDWARE WRITE PROTECT INPUT (WP)
10
A3
Device Address for 2 wire-bus. Must be
connected to Ground
The WP pin when LOW prevents non-volatile writes to the
Data Registers.
11
12
13
14
R
Wiper Terminal of the Potentiometer
High Terminal of the Potentiometer
Low Terminal of the Potentiometer
System Supply Voltage
W
R
H
Principles Of Operation
R
L
The X9279 is a integrated microcircuit incorporating a
resistor array and associated registers and counter and the
serial interface logic providing direct communication
between the host and the digitally controlled potentiometers.
This section provides detail description of the following:
V
CC
Pin Descriptions
Bus Interface Pins
• Resistor Array Description
• Serial Interface Description
• Instruction and Register Description
Array Description
SERIAL DATA INPUT/OUTPUT (SDA)
The SDA is a bidirectional serial data input/output pin for a
2-Wire slave device and is used to transfer data into and out
of the device. It receives device address, opcode, wiper
register address and data sent from an 2-Wire master at the
rising edge of the serial clock SCL, and it shifts out data after
each falling edge of the serial clock SCL.
The X9279 is comprised of a resistor array (see Figure 1).
The array contains, in effect, 255 discrete resistive segments
that are connected in series. The physical ends of each array
are equivalent to the fixed terminals of a mechanical
It is an open drain output and may be wire-ORed with any
number of open drain or open collector outputs. An open
drain output requires the use of a pull-up resistor. For
selecting typical values, refer to the guidelines for calculating
typical values on the bus pull-up resistors graph.
potentiometer (R and R inputs).
H
L
At both ends of each array and between each resistor
segment is a CMOS switch connected to the wiper (R )
W
output. Within each individual array only one switch may be
turned on at a time.
SERIAL CLOCK (SCL)
This input is used by 2-Wire master to supply 2-Wire serial
clock to the X9279.
These switches are controlled by a Wiper Counter Register
(WCR). The 8-bits of the WCR (WCR[7:0]) are decoded to
select, and enable, one of 256 switches (see Table 1).
DEVICE ADDRESS (A3 - A0)
The Address inputs A2 - A0 are used to set the least significant
3 bits of the 8-bit slave address, address pin A3 must be
The WCR may be written directly. These Data Registers can
the WCR can be read and written by the host system.
FN8175.4
September 23, 2009
4
X9279
SERIAL
BUS
INPUT
SERIAL DATA PATH
R
H
FROM INTERFACE
CIRCUITRY
C
O
U
N
T
REGISTER 0
(DR0)
REGISTER 1
(DR1)
8
8
PARALLEL
BUS
INPUT
E
R
BANK_0 Only
REGISTER 2
(DR2)
REGISTER 3
(DR3)
D
E
C
O
D
WIPER
COUNTER
REGISTER
(WCR)
E
R
INC/DEC
LOGIC
IF WCR = 00[H] THEN R = R
W
L
UP/DN
UP/DN
CLK
IF WCR = FF[H] THEN R = R
W
H
R
MODIFIED SCK
L
R
W
FIGURE 1. DETAILED POTENTIOMETER BLOCK DIAGRAM
Start Condition
Power-up and Down Recommendations.
All commands to the X9279 are preceded by the start
condition, which is a HIGH to LOW transition of SDA while
SCL is HIGH. The X9279 continuously monitors the SDA
and SCL lines for the start condition and will not respond to
any command until this condition is met (see Figure 2).
There are no restrictions on the power-up or power-down
conditions of V
and the voltages applied to the
potentiometer pins provided that V is always more
CC
CC
positive than or equal to V , V , and V , i.e., V
V , V ,
H
L
W
CC
H
L
V . The V
CC
ramp rate specification is always in effect.
W
Stop Condition
Serial Interface Description
All communications must be terminated by a stop condition,
which is a LOW to HIGH transition of SDA while SCL is
HIGH (see Figure 2).
Serial Interface
The X9279 supports a bidirectional bus oriented protocol.
The protocol defines any device that sends data onto the
Acknowledge
bus as a transmitter and the receiving device as the receiver.
The device controlling the transfer is a master and the
device being controlled is the slave. The master will always
initiate data transfers and provide the clock for both transmit
and receive operations. Therefore, the X9279 will be
considered a slave device in all applications.
Acknowledge is a software convention used to provide a
positive handshake between the master and slave devices
on the bus to indicate the successful receipt of data. The
transmitting device, either the master or the slave, will
release the SDA bus after transmitting eight bits. The master
generates a ninth clock cycle and during this period the
receiver pulls the SDA line LOW to acknowledge that it
successfully received the eight bits of data.
Clock and Data Conventions
Data states on the SDA line can change only during SCL
LOW periods. SDA state changes during SCL HIGH are
reserved for indicating start and stop conditions (see
Figure 2.
The X9279 will respond with an acknowledge after
recognition of a start condition and its slave address and
once again after successful receipt of the command byte. If
the command is followed by a data byte the X9279 will
respond with a final acknowledge (see Figure 2).
FN8175.4
September 23, 2009
5
X9279
SCL FROM MASTER
1
8
9
DATA OUTPUT
FROM TRANSMITTER
DATA OUTPUT
FROM RECEIVER
START
ACKNOWLEDGE
FIGURE 2. ACKNOWLEGE RESPONSE FROM RECEIVER
Acknowledge Polling
Instruction and Register Description
The disabling of the inputs, during the internal non-volatile
write operation, can be used to take advantage of the typical
5ms EEPROM write cycle time. Once the stop condition is
issued to indicate the end of the non-volatile write command
the X9279 initiates the internal write cycle. ACK Polling
Sequence, Flow 1, can be initiated immediately. This
involves issuing the start condition followed by the device
slave address. If the X9279 is still busy with the write
operation no ACK will be returned. If the X9279 has
completed the write operation an ACK will be returned and
the master can then proceed with the next operation.
Device Addressing: Identification Byte (ID and A)
The first byte sent to the X9279 from the host, following a CS
going HIGH to LOW, is called the Identification byte. The
most significant four bits of the slave address are a device
type identifier. The ID[3:0] bits is the device ID for the X9279;
this is fixed as 0101[B] (refer to Table 3).
The A[2:0] bits in the ID byte is the internal slave address.
The physical device address is defined by the state of the
A2 - A0 input pins. The slave address is externally specified
by the user. The X9279 compares the serial data stream with
the address input state; a successful compare of both
address bits is required for the X9279 to successfully
continue the command sequence. Only the device which
slave address matches the incoming device address sent by
the master executes the instruction. The A2 - A0 inputs can
Flow 1: ACK Polling Sequence
Non-volatile Write
Command Completed
EnterACK Polling
Issue
START
be actively driven by CMOS input signals or tied to V
or
CC
V
.
SS
Issue Slave
Issue STOP
Address
Instruction Byte (I)
The next byte sent to the X9279 contains the instruction and
register pointer information. The three most significant bits
are used provide the instruction opcode I [2:0]. The RB and
RA bits point to one of the four Data Registers. P0 is the
POT selection; since the X9279 is single POT, the P0 = 0.
The format is shown in Table 4.
ACK
No
Returned?
Yes
Further
Operation?
No
Register Bank Selection (RB, RA, P1, P0)
Yes
There are 16 registers organized into four banks. Bank 0 is
the default bank of registers. Only Bank 0 registers can be
used for Data Register to Wiper Counter Register
operations.
Issue
Issue STOP
Proceed
Instruction
Proceed
Banks 1, 2, and 3 are additional banks of registers (12 total)
that can be used for 2-Wire write and read operations. The
Data Registers in Banks 1, 2, and 3 cannot be used for direct
read/write operations between the Wiper Counter Register.
FN8175.4
September 23, 2009
6
X9279
TABLE 1. REGISTER SELECTION (R0 TO R3)
REGISTER
TABLE 2. REGISTER BANK SELECTION (BANK 0 TO BANK 3)
BANK
RB
RA SELECTION
OPERATIONS
P1
P0 SELECTION
OPERATIONS
0
0
1
0
0
1
2
Data Register Read and Write; Wiper
Counter Register Operations
0
0
0
Data Register Read and Write; Wiper
Counter Register Operations
0
1
Data Register Read and Write; Wiper
Counter Register Operations
0
1
1
1
0
1
1
2
3
Data Register Read and Write Only
Data Register Read and Write Only
Data Register Read and Write Only
Data Register Read and Write; Wiper
Counter Register
Operations
1
1
3
Data Register Read and Write; Wiper
Counter Register
Operations
TABLE 3. IDENTIFICATION BYTE FORMAT
Device Type
Identifier
Internal Slave
Address
Set to 0
for proper operation
ID3
0
ID2
ID1
0
ID0
1
0
A2
A1
A0
1
(MSB)
(LSB)
TABLE 4. INSTRUCTION BYTE FORMAT
P1 and P0 are used also for register Bank Selection
for 2-Wire Register Write and Read operations
Register
Selection
Instruction Opcode
Register Selection
Register Selected
RB
0
RA
0
I3
(MSB)
I2
I1
I0
RB
RA
P1
P0
DR0
DR1
DR2
DR3
(LSB)
0
1
1
0
1
1
Pot Selection (Bank Selection)
Set to P0 = 0 for potentiometer operations
TABLE 5. INSTRUCTION SET
INSTRUCTION Set
INSTRUCTION
I3
I2
0
I1
0
I0
1
RB RA
P
P
OPERATION
1
0
Read Wiper Counter Register
1
1
0
0
0
0
0
0
Read the contents of the Wiper Counter Register
Write new value to the Wiper Counter Register
Write Wiper Counter
Register
0
1
0
0
1/0
1/0
0
0
Read Data Register
1
1
1
1
0
0
1
1
1
0
1
0
0
1
1
1
0
1
0
0
1/0 1/0
1/0 1/0
1/0 1/0
1/0 1/0
1/0 Read the contents of the Data Register pointed to by P1 - P0
and RB - RA
Write Data Register
1/0 Write new value to the Data Register pointed to by P1 - P0 and
RB - RA
XFR Data Register to
Wiper Counter Register
0
0
0
Transfer the contents of the Data Register pointed to by
RB-RA (Bank 0 only) to the Wiper Counter Register
XFR Wiper Counter
Register to Data Register
0
Transfer the contents of the Wiper Counter Register to the
Register pointed to by RB-RA (Bank 0 only)
Increment/Decrement
Wiper Counter Register
0
0
0
Enable Increment/decrement of the Wiper Counter Register
NOTE:
3. 1/0 = data is one or zero
FN8175.4
September 23, 2009
7
X9279
TABLE 6. WIPER COUNTER REGISTER, WCR (8-bit), WCR[7:0]: (Used to store the current wiper position (Volatile, V)
WCR7
V
WCR6
WCR5
WCR4
WCR3
WCR2
WCR1
WCR0
V
V
V
V
V
V
V
(MSB)
(LSB)
TABLE 7. DATA REGISTER, DR (8-BIT), BIT [7:0]: Used to store wiper positions or data (Non-volatile, NV)
Bit 7
NV
Bit 6
NV
Bit 5
NV
Bit 4
NV
Bit 3
NV
Bit 2
NV
Bit 1
NV
Bit 0
NV
MSB
LSB
• Write Wiper Counter Register – change current wiper
position of the potentiometer,
Device Description
Wiper Counter Register (WCR)
• Read Data Register – read the contents of the selected
The X9279 contains a Wiper Counter Register, for the DCP
potentiometer. The Wiper Counter Register can be envisioned
as a 8-bit parallel and serial load counter with its outputs
decoded to select one of 256 switches along its resistor array.
The contents of the WCR can be altered in four ways: it may be
written directly by the host via the Write Wiper Counter Register
instruction (serial load); it may be written indirectly by
transferring the contents of one of four associated data
registers via the XFR Data Register instruction (parallel load); it
can be modified one step at a time by the Increment/Decrement
instruction (see “Instruction Format” on page 10 for more
details). Finally, it is loaded with the contents of its Data
Register zero (DR0) upon power-up.
Data Register;
• Write Data Register – write a new value to the selected
Data Register.
The basic sequence of the three byte instructions is
illustrated in Figure 4. These three-byte instructions
exchange data between the WCR and one of the Data
Registers. A transfer from a Data Register to a WCR is
essentially a write to a static RAM, with the static RAM
controlling the wiper position. The response of the wiper to
this action will be delayed by t
(current wiper position), to a Data Register is a write to
non-volatile memory and takes a minimum of t to
. A transfer from the WCR
WRL
WR
complete. The transfer can occur between the potentiometer
and one of its four associated registers (Bank 0).
The Wiper Counter Register is a volatile register; that is, its
contents are lost when the X9279 is powered-down.
Although the register is automatically loaded with the value
in DR0 upon power-up, this may be different from the value
present at power-down. Power-up guidelines are
Two instructions require a two-byte sequence to complete.
These instructions transfer data between the host and the
X9279; either between the host and one of the data registers
or directly between the host and the Wiper Counter Register.
These instructions are:
recommended to ensure proper loadings of the DR0 value
into the WCR. The DR0 value of Bank 0 is the default value.
Data Registers (DR)
• XFR Data Register to Wiper Counter Register – This
transfers the contents of one specified Data Register to
the Wiper Counter Register.
The potentiometer has four 8-bit non-volatile Data Registers
(DR3-DR0). These can be read or written directly by the host.
Data can also be transferred between any of the four Data
Registers and the associated Wiper Counter Register. All
operations changing data in one of the Data Registers is a
non-volatile operation and will take a maximum of 10ms.
• XFR Wiper Counter Register to Data Register – This
transfers the contents of the Wiper Counter Register to the
specified Data Register.
The final command is Increment/Decrement (Figures 5
and 6). The Increment/Decrement command is different from
the other commands. Once the command is issued and the
X9279 has responded with an acknowledge, the master can
clock the selected wiper up and/or down in one segment
steps; thereby, providing a fine tuning capability to the host.
If the application does not require storage of multiple
settings for the potentiometer, the Data Registers can be
used as regular memory locations for system parameters or
user preference data.
Bit [7:0] are used to store one of the 256 wiper positions
(0~255).
For each SCL clock pulse (t
) while SDA is HIGH, the
HIGH
selected wiper will move one resistor segment towards the
terminal. Similarly, for each SCL clock pulse while SDA is
R
H
Instructions
LOW, the selected wiper will move one resistor segment
Four of the seven instructions are three bytes in length.
These instructions are:
towards the R terminal. See “Instruction Format” on
L
page 10 for more details.
• Read Wiper Counter Register – read the current wiper
position of the potentiometer,
FN8175.4
September 23, 2009
8
X9279
SCL
SDA
0
1
0
1
0
0
ID3 ID2 ID1 ID0
A2 A1 A0
S
T
A
R
T
0
A
C
K
RB RA P1
A
C
K
S
T
O
P
P0
I3
I2 I1 I0
Internal
Address
Device ID
Instruction
Opcode
Register
Address
Pot/Bank
Address
These commands only valid when P1 = P0 = 0
FIGURE 3. TWO-BYTE INSTRUCTION SEQUENCE
SCL
SDA
0
1
0
1
0
0
ID1
S
T
ID3 ID2
ID0
A
C
K
I3
RB RA P1 P0
A
C
K
D7 D6 D5 D4 D3 D2 D1 D0
A
C
K
S
T
O
P
I1
I2
I0
A2 A1 A0
A
External
Address
Pot/Bank
Register
WCR[7:0] valid only when P1 = P0 = 0;
or
R
Device ID
Instruction
Opcode
Address
T
Address
Data Register D[7:0] for all values of P1 and P0
FIGURE 4. THREE-BYTE INSTRUCTION SEQUENCE
SCL
SDA
0
1
0
1
0
0
A2 A1 A0
ID3 ID2 ID1 ID0
Device ID
I3
I2
I1 I0
RB RA P1 P0
A
C
K
I
I
N
C
D
E
C
S
T
O
I
D
A
C
K
S
T
A
R
T
N
C
1
N
C
n
E
C
n
External
Address
Pot/Bank
Register
Address
Instruction
Opcode
2
1
P
Address
FIGURE 5. INCREMENT/DECREMENT INSTRUCTION SEQUENCE
INC/DEC
CMD
ISSUED
t
WRID
SCL
SD A
VOLTAGE OUT
V
/R
W
W
FIGURE 6. INCREMENT/DECREMENT TIMING LIMITS
FN8175.4
September 23, 2009
9
X9279
Instruction Format
Read Wiper Counter Register (WCR)
S
T
A
R
T
Device Type
Identifier
Device
Addresses
Instruction
Opcode
DR/Bank
Addresses
Wiper Position
(Sent by X9279 on SDA)
S
A
C
K
S
A
C
K
M
A
C
K
S
T
O
P
0
1
0
1
0
A 2 A 1 A 0
1
0
0
1
0
0
0
0
WC WC WC WC WC WC WC WC
R7 R6 R5 R4 R3 R2 R1 R0
Write Wiper Counter Register (WCR)
S
T
A
R
T
Device Type
Identifier
Device
Addresses
Instruction
Opcode
DR/Bank
Addresses
Wiper Position
(Sent by Master on SDA)
S
S
S
A
C
K
S
T
O
P
A
C
K
A
C
K
0
1
0
1
0
A 2 A 1 A 0
1
0
1
0
0
0
0
0
WC WC WC WC WC WC WC WC
R7 R6 R5 R4 R3 R2 R1 R0
Read Data Register (DR)
S
T
A
R
T
Device Type
Identifier
Device
Addresses
Instruction
Opcode
DR/Bank
Addresses
Wiper Position
(Sent by X9279 on SDA)
S
S
M
S
T
O
P
A
C
K
A
C
K
A
C
K
0
1
0
1
0
A 2 A 1 A 0
1
0
1
1
RB RA P1 P0
WC WC WC WC WC WC WC WC
R7 R6 R5 R4 R3 R2 R1 R0
Write Data Register (DR)
Device Type
Identifier
Device
Addresses
Instruction
Opcode
DR/Bank
Addresses
S
Wiper Position
(Sent by Master on SDA)
S
T
A
R
T
S
A
C
K
S
A
C
K
S
T
O
P
0
1
0
1
0
A 2 A 1 A 0
1
1
0
0
RB RA P1 P0
WC WC WC WC WC WC WC WC
R7 R6 R5 R4 R3 R2 R1 R0
A
C
K
Transfer Wiper Counter Register (WCR) to Data Register (DR)
S
T
A
R
T
Device Type
Identifier
Device
Addresses
Instruction
Opcode
DR/Bank
Addresses
High-Voltage
Write Cycle
S
A
C
K
S
A
C
K
S
T
O
P
0
1
0
1
0
A 2
A 1
A 0
1
1
1
0
RB
RA
0
0
Transfer Data Register (DR) to Wiper Counter Register (WCR)
S
T
A
R
T
Device Type
Identifier
Device
Addresses
Instruction
Opcode
DR/Bank
Addresses
S
A
C
K
S
A
C
K
S
T
O
P
0
1
0
1
0
A 2
A 1
A 0
1
1
0
1
RB
RA
0
0
Increment/Decrement Wiper Counter Register (WCR)
S
T
A
R
T
Device Type
Identifier
Device
Addresses
Instruction
Opcode
DR/Bank
Addresses
Increment/Decrement
(Sent by Master on SDA)
S
A
C
K
S
A
C
K
S
T
O
P
0
1
0
1
0
A 2 A 1 A 0
0
0
1
0
0
0
0
0
I/D
I/D
.
.
.
.
I/D I/D
NOTES:
4. “MACK”/”SACK”: stands for the acknowledge sent by the master/slave.
5. “A3 ~ A0”: stands for the device addresses sent by the master.
6. “X”: indicates that it is a “0” for testing purpose but physically it is a “don’t care” condition.
7. “I”: stands for the increment operation, SDA held high during active SCL phase (high).
8. “D”: stands for the decrement operation, SDA held low during active SCL phase (high).
FN8175.4
September 23, 2009
10
X9279
Absolute Maximum Ratings
Thermal Information
Voltage on SCL, SDA any Address Input
with respect to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . -1V to +7V
DV = | (VH - VL) |. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5V
Thermal Resistance (Typical, Note 9)
(°C/W)
90
JA
14 Lead TSSOP. . . . . . . . . . . . . . . . . . . . . . . . . . . .
Temperature Under Bias . . . . . . . . . . . . . . . . . . . . .-65°C to +135°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
I
(10s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±6mA
W
Operating Conditions
Temperature Range
Commercial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to +70°C
Industrial. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C
Supply Voltage VCC Limits (Note 13)
X9279. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5V ± 10%
X9279-2.7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V to 5.5V
Wiper Max Current (I ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±3mA
W
Power Rating @ +25°C, each pot . . . . . . . . . . . . . . . . . . . . . .50mW
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTE:
9. is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
JA
Analog Characteristics Operating Conditions over recommended industrial (2.7V) unless otherwise specified.
SYMBOL
PARAMETER
End-to-End Resistance
TEST CONDITIONS
MIN
TYP
MAX
UNITS
R
R
T version
U version
100
50
k
TOTAL
End-to-End Resistance
k
TOTAL
End-to-End Resistance Tolerance
Wiper Resistance @ V = 3V
Wiper Resistance @ V = 5V
±20
300
150
%
R
R
I
I
= (V
= (V
- V )/R
RL TOTAL
W
W
RH
RH
- V )/R
RL TOTAL
W
W
V
Voltage on any R or R Pin
V
= 0V
V
V
CC
V
dBVHz
%
TERM
H
L
SS
SS
Noise
Ref: 1V
-120
0.4
Resolution
Absolute Linearity (Note 10)
Relative Linearity (Note 11)
Temperature Coefficient of R
R
R
- R
(Note 14)
w(n)(expected)
±1
MI
(Note 12)
w(n)(actual)
- [R
w(n) + MI
] (Note 14)
±0.2
MI
(Note 12)
w(n + 1)
±300
ppm/°C
TOTAL
Ratiometric Temp. Coefficient
Potentiometer Capacitances
±20
ppm/°C
pF
C /C /C
W
See Macro model
10/10/25
H
L
NOTES:
10. Absolute linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used as a
potentiometer.
11. Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a potentiometer. It is
a measure of the error in step size.
12. MI = RTOT / 255 or (R - R )/255, single pot
H
L
13. During power-up V
CC
> V , V , and V .
H L W
14. n = 0, 1, 2,....,255; m = 0, 1, 2,...., 254.
FN8175.4
September 23, 2009
11
X9279
DC Electrical Specifications Over the recommended Operating Conditions unless otherwise specified.
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
I
V
Supply Current (Active)
f
= 400kHz; V = +6V; SDA = Open;
3
mA
CC1
CC
SCL
CC
(for 2-Wire, Active, Read and Volatile Write States
only)
I
I
V
Supply Current
f
= 400kHz; V = +6V; SDA = Open
CC
5
5
mA
µA
CC2
SB
CC
SCL
(for 2-Wire, Active, Non-volatile Write State only)
(Non-volatile Write)
V
Current (Standby)
V
= +6V; V = V or V ; SDA = V
IN SS CC
CC
CC
(for 2-Wire, Standby State only)
CC
I
I
Input Leakage Current
Output Leakage Current
Input HIGH Voltage
Input LOW Voltage
V
V
= V to V
SS CC
10
10
µA
µA
V
LI
IN
= V to V
SS CC
LO
OUT
V
V
V
V
x 0.7
V
+ 1
IH
IL
CC
CC
-1
V
x 0.3
V
CC
0.4
Output LOW Voltage
I
= 3mA
V
OL
OL
Endurance and Data Retention
PARAMETER
MIN
UNITS
Minimum Endurance
Data Retention
100,000
100
Data changes per bit per register
years
Capacitance
SYMBOL
TEST
Input /Output capacitance (SDA)
TYP
8
UNITS
pF
TEST CONDITIONS
= 0V
C
C
V
OUT
IN/OUT
Input capacitance (SCL, WP, A2, A1 and A0)
6
pF
V
= 0V
IN
IN
Power-Up Timing
SYMBOL
PARAMETER
MIN
MAX
50
UNITS
V/ms
ms
t V
(Note 15)
V Power-up rate
CC
0.2
r
CC
t
t
(Note 16)
(Note 16)
Power-up to initiation of read operation
Power-up to initiation of write operation
1
PUR
50
ms
PUW
NOTES:
15. This parameter is not 100% tested.
16. t and t are the delays required from the time the (last) power supply (V -) is stable until the specific instruction can be issued. These
PUR
PUW
CC
parameters are periodically sampled and not 100% tested.
AC Test Conditions
Input Pulse Levels
V
x 0.1 to V
10ns
x 0.9
CC
CC
Input rise and fall times
Input and output timing level
V
x 0.5
CC
FN8175.4
September 23, 2009
12
X9279
Equivalent AC Load Circuit
SPICE MACROMODEL
5V
3V
1533
R
867
TOTAL
R
R
L
H
SDA PIN
SDA PIN
C
C
W
C
L
L
10pF
100pF
100pF
25pF
10pF
MIN
R
W
AC Timing
SYMBOL
PARAMETER
MAX
UNITS
kHz
ns
f
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Clock Frequency
400
SCL
Clock Cycle Time
2500
600
1300
600
600
600
100
30
CYC
Clock High Time
ns
HIGH
LOW
SU:STA
HD:STA
SU:STO
SU:DAT
HD:DAT
R
Clock Low Time
ns
Start Setup Time
ns
Start Hold Time
ns
Stop Setup Time
ns
SDA Data Input Setup Time
SDA Data Input Hold Time
SCL and SDA Rise Time
SCL and SDA Fall Time
ns
ns
300
300
0.9
ns
ns
F
SCL Low to SDA Data Output Valid Time
SDA Data Output Hold Time
µs
AA
0
50
1200
0
ns
DH
Noise Suppression Time Constant at SCL and SDA inputs
Bus Free Time (Prior to Any Transmission)
A0, A1 Setup Time
ns
I
ns
BUF
ns
SU:WPA
HD:WPA
A0, A1 Hold Time
0
ns
High Voltage Write Cycle Timing
SYMBOL
PARAMETER
TYP
MAX
UNITS
t
High-voltage write cycle time (store instructions)
5
10
ms
WR
XDCP Timing
SYMBOL
PARAMETER
MIN
5
MAX
UNITS
t
t
Wiper response time after the third (last) power supply is stable
Wiper response time after instruction issued (all load instructions)
10
10
µs
µs
WRPO
WRL
5
FN8175.4
September 23, 2009
13
X9279
Symbol Table
WAVEFORM
INPUTS
OUTPUTS
Must be
steady
Will be
steady
May change
from Low to
High
Will change
from Low to
High
May change
from High to
Low
Will change
from High to
Low
Don’t Care:
Changes
Allowed
Changing:
State Not
Known
N/A
Center Line
is High
Impedance
Timing Diagrams
Start and Stop Timing
(START)
(STOP)
t
t
F
R
SCL
t
t
t
SU:STO
SU:STA
HD:STA
t
t
F
R
SDA
Input Timing
t
t
CYC
HIGH
SCL
SDA
t
LOW
t
t
t
BUF
SU:DAT
HD:DAT
Output Timing
SCL
SDA
t
t
DH
AA
FN8175.4
September 23, 2009
14
X9279
XDCP Timing (for All Load Instructions)
(STOP)
SCL
SDA
VWx
LSB
t
WRL
Write Protect and Device Address Pins Timing
(START)
(STOP)
SCL
...
(ANY INSTRUCTION)
...
SDA
...
t
t
SU:WPA
HD:WPA
WP
A0, A1
Applications information
Basic Configurations of Electronic Potentiometers
+V
R
V
R
RW
I
Three terminal Potentiometer;
Variable voltage divider
Two terminal Variable Resistor;
Variable current
FN8175.4
September 23, 2009
15
X9279
Application Circuits
V
+
–
S
V
O
V
V
(REG)
317
IN
O
R
1
R
2
I
adj
R
1
R
2
V
= (1+R /R )V
2 1 S
O
V
(REG) = 1.25V (1+R /R )+I R
adj 2
O
2
1
VOLTAGE REGULATOR
NON-INVERTING AMPLIFIER
R
R
2
1
V
–
+
S
V
S
V
O
100k
–
+
V
O
TL072
R
R
2
1
10k
10k
V
= {R /(R +R )} V (max)
1 1 2 O
10k
UL
RL = {R /(R +R )} V (min)
L
1
1
2
O
+12V
-12V
COMPARATOR WITH HYSTERISIS
OFFSET VOLTAGE ADJUSTMENT
C
V
+
S
R
V
O
R
R
2
1
–
–
+
R
V
O
V
S
3
R
2
R
4
R
= R = R = R = 10k
2 3 4
1
R
1
G
= 1 + R /R
2 1
V
= G V
S
O
O
fc = 1/(2RC)
-1/2 G +1/2
FILTER
ATTENUATOR
FN8175.4
September 23, 2009
16
X9279
Application Circuits (Continued)
R
2
C
1
V
+
–
S
R
R
2
1
V
S
R
R
1
Z
IN
–
+
V
O
3
Z
= R + s R (R + R ) C = R + s Leq
2 2 1 3 1 2
V
= G V
S
IN
O
(R + R ) >> R
G = - R /R
1
3
2
2
1
EQUIVALENT L-R CIRCUIT
INVERTING AMPLIFIER
C
R
R
1
2
–
+
–
+
R
}
}
A
R
B
Frequency R , R , C
1
2
Amplitude R , R
A
B
FUNCTION GENERATOR
FN8175.4
September 23, 2009
17
X9279
Thin Shrink Small Outline Plastic Packages (TSSOP)
M14.173
N
14 LEAD THIN SHRINK SMALL OUTLINE PLASTIC
PACKAGE
INDEX
AREA
0.25(0.010)
M
B M
E
E1
-B-
INCHES
MIN
MILLIMETERS
GAUGE
PLANE
SYMBOL
MAX
0.047
0.006
0.041
0.0118
0.0079
0.199
0.177
MIN
-
MAX
1.20
0.15
1.05
0.30
0.20
5.05
4.50
NOTES
A
A1
A2
b
-
-
1
2
3
0.002
0.031
0.0075
0.0035
0.195
0.169
0.05
0.80
0.19
0.09
4.95
4.30
-
L
0.25
0.010
-
0.05(0.002)
SEATING PLANE
A
9
-A-
D
c
-
D
3
-C-
E1
e
4
A2
e
A1
0.026 BSC
0.65 BSC
-
c
b
0.10(0.004)
E
0.246
0.256
6.25
0.45
6.50
0.75
-
0.10(0.004) M
C
A M B S
L
0.0177
0.0295
6
N
14
14
7
NOTES:
o
o
o
o
0
8
0
8
-
1. These package dimensions are within allowable dimensions of
JEDEC MO-153-AC, Issue E.
Rev. 2 4/06
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm
(0.006 inch) per side.
4. Dimension “E1” does not include interlead flash or protrusions. Inter-
lead flash and protrusions shall not exceed 0.15mm (0.006 inch) per
side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “b” does not include dambar protrusion. Allowable dambar
protrusion shall be 0.08mm (0.003 inch) total in excess of “b” dimen-
sion at maximum material condition. Minimum space between protru-
sion and adjacent lead is 0.07mm (0.0027 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact. (Angles in degrees)
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9001 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN8175.4
18
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