X9314WMI-3T5C7886 [RENESAS]
10K DIGITAL POTENTIOMETER, INCREMENT/DECREMENT CONTROL INTERFACE, 32 POSITIONS, PDSO8, MSOP-8;
| 型号： | X9314WMI-3T5C7886 |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | 10K DIGITAL POTENTIOMETER, INCREMENT/DECREMENT CONTROL INTERFACE, 32 POSITIONS, PDSO8, MSOP-8 光电二极管 转换器 电阻器 |
| 文件： | 总9页 (文件大小：209K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
X9314
®
Terminal Voltages ±5V, 32 Taps, Log Taper
Data Sheet
September 5, 2006
FN8178.2
Single Digitally Controlled Potentiometer
(XDCP™)
Features
• Solid State Potentiometer
• 32 Taps
The Intersil X9314 is a solid state nonvolatile potentiometer and
is ideal for digitally controlled resistance trimming.
• 10kΩ End to End Resistance
• Three-Wire Up/Down Serial Interface
• Wiper Resistance, 40Ω Typical
The X9314 is a resistor array composed of 31 resistive
elements. Between each element and at either end are tap
points accessible to the wiper element. The position of the
wiper element is controlled by the CS, U/D, and INC inputs.
The position of the wiper can be stored in nonvolatile
memory and then be recalled upon a subsequent power-up
operation.
• Nonvolatile Storage and Recall on Power-up of Wiper
Position Standby Current < 500µA Max (Total Package)
• V
CC
= 3V to 5.5V Operation
• 100 Year Data Retention
The XDCP can be used as a three-terminal potentiometer or
as a two-terminal variable resistor in a wide variety of
applications including control, parameter adjustments, and
signal processing.
• Offered in 8 Ld MSOP, SOIC and PDIP Packages
• Pb-Free Plus Anneal Available (RoHS Compliant)
Block Diagram
U/D
INC
CS
31
30
29
28
5-Bit
Up/Down
Counter
V /R
H
H
5-Bit
Nonvolatile
Memory
One
of
Thirty-Two
Decoder
Transfer
Gates
Resistor
Array
2
1
0
Store and
Recall
Control
Circuitry
V
V /R
CC
L
L
V
SS
V
/R
W
W
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
XDCP is a trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005, 2006. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
1
X9314
Ordering Information
V
RANGE
(V)
R
TEMP RANGE
(°C)
PKG.
DWG. #
CC
TOTAL
(kΩ)
PART NUMBER
X9314WMI*
PART MARKING
PACKAGE
8 Ld MSOP
14WI
5 ±10%
10
-40 to +85
0 to +70
M8.118
X9314WP
X9314WP
X9314WP I
X9314W
X9314W I
X9314W ZI
X9314W Z
AAY
8 Ld PDIP
8 Ld PDIP
8 Ld SOIC
8 Ld SOIC
MDP0031
MDP0031
M8.15
X9314WPI
-40 to +85
0 to +70
X9314WS*
X9314WSI*
-40 to +85
-40 to +85
0 to +70
M8.15
X9314WSIZ (Note)
X9314WSZ* (Note)
X9314WMI-3*
X9314WMIZ-3* (Note)
X9314WS-3*
8 Ld SOIC (Pb-free) M8.15
8 Ld SOIC (Pb-free) M8.15
3 to 5.5
-40 to +85
-40 to +85
0 to +70
8 Ld MSOP
8 Ld MSOP (Pb-free) M8.118
8 Ld SOIC M8.15
8 Ld SOIC (Pb-free) M8.15
M8.118
DEX
X9314W D
X9314W ZD
X9314WSZ-3* (Note)
0 to +70
*Add "T1" suffix for tape and reel.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
Pin Descriptions
Pin Configuration
V /R and V /R
L
H
H
L
8 LD PDIP/SOIC
The high (V /R ) and low (V /R ) terminals of the X9314
H
H
L
L
V
are equivalent to the fixed terminals of a mechanical
potentiometer. The minimum voltage is –5V and the
maximum is +5V. It should be noted that the terminology of
INC
U/D
/R
1
8
7
6
5
CC
2
3
4
CS
X9314
V /R
L
V
L
H
H
V /R and V /R references the relative position of the
L
L
H
H
V
V /R
W W
SS
terminal in relation to wiper movement direction selected by
the U/D input and not the voltage potential on the terminal.
8 LD MSOP
X9314
V /R
W
W
V
/R
U/D
INC
H
H
1
8
V /R is the wiper terminal, equivalent to the movable
W
W
V
2
3
4
7
6
5
SS
terminal of a mechanical potentiometer. The position of the
wiper within the array is determined by the control inputs.
The wiper terminal series resistance is typically 40Ω.
V
CC
V
/R
W
W
CS
V /R
L
L
Up/Down (U/D)
The U/D input controls the direction of the wiper movement
and whether the counter is incremented or decremented.
Pin Names
Increment (INC)
SYMBOL
DESCRIPTION
High Terminal
Wiper Terminal
Low Terminal
Ground
The INC input is negative-edge triggered. Toggling INC will
move the wiper and either increment or decrement the
counter in the direction indicated by the logic level on the
U/D input.
V /R
H
H
W
L
V
/R
W
V /R
L
Chip Select (CS)
V
SS
The device is selected when the CS input is LOW. The
current counter value is stored in nonvolatile memory when
CS is returned HIGH while the INC input is also HIGH. After
the store operation is complete the X9314 will be placed in
the low power standby mode until the device is selected
once again.
V
Supply Voltage
Up/Down Input
Increment Input
Chip Select Input
CC
U/D
INC
CS
FN8178.2
September 5, 2006
2
X9314
Typical Attenuation Characteristics (dB)
0
-20
-40
-43.5
-60
0
31
28
24
20
16
8
4
12
Tap Position
Operation Notes
The system may select the X9314, move the wiper and
deselect the device without having to store the latest wiper
position in nonvolatile memory. The wiper
Principles of Operation
There are three sections of the X9314: the input control,
counter and decode section; the nonvolatile memory; and the
resistor array. The input control section operates just like an
up/down counter. The output of this counter is decoded to turn
on a single electronic switch connecting a point on the resistor
array to the wiper output. Under the proper conditions the
contents of the counter can be stored in nonvolatile memory
and retained for future use. The resistor array is comprised of
31 individual resistors connected in series. At either end of the
array and between each resistor is an electronic switch that
transfers the potential at that point to the wiper.
movement is performed as described above; once the new
position is reached, the system would keep the INC LOW
while taking CS HIGH. The new wiper position would be
maintained until changed by the system or until a power-
up/down cycle recalled the previously stored data.
This would allow the system to always power-up to a preset
value stored in nonvolatile memory; then during system
operation minor adjustments could be made. The
adjustments might be based on user preference, system
parameter changes due to temperature drift, etc.
The INC, U/D and CS inputs control the movement of the
wiper along the resistor array. With CS set LOW the X9314
is selected and enabled to respond to the
The state of U/D may be changed while CS remains LOW.
This allows the host system to enable the X9314 and then
move the wiper up and down until the proper trim is attained.
U/D and INC inputs. HIGH to LOW transitions on INC will
increment or decrement (depending on the state of the U/D
input) a five bit counter. The output of this counter is
decoded to select one of thirty-two wiper positions along the
resistive array.
t
/R
IW TOTAL
The electronic switches on the X9314 operate in a “make
before break” mode when the wiper changes tap positions. If
the wiper is moved several positions multiple taps are
The wiper, when at either fixed terminal, acts like its
mechanical equivalent and does not move beyond the last
position. That is, the counter does not wrap around when
clocked to either extreme.
connected to the wiper for t (INC to V change). The
IW
W
R
value for the device can temporarily be reduced by
TOTAL
a significant amount if the wiper is moved several positions.
The value of the counter is stored in nonvolatile memory
whenever CS transistions HIGH while the INC input is also
HIGH.
Power-up and Down Requirement
The are no restrictions on the sequencing of V
and the
CC
voltages applied to the potentiometer pins during power-up
or power-down conditions. During power-up, the data sheet
parameters for the DCP do not fully apply until 1 millisecond
When the X9314 is powered-down, the last counter position
stored will be maintained in the nonvolatile memory. When
power is restored, the contents of the memory are recalled
and the counter is reset to the value last stored.
after V
reaches its final value. The V
ramp rate spec is
CC
CC
always in effect.
FN8178.2
September 5, 2006
3
X9314
Absolute Maximum Ratings
Recommended Operating Conditions
Temperature under bias. . . . . . . . . . . . . . . . . . . . . .-65°C to +135°C
Storage temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Voltage on CS, INC, U/D, and
Temperature (Commercial) . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C
Temperature (Industrial). . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C
Supply Voltage (V ) Limits
CC
V
with respect to V
. . . . . . . . . . . . . . . . . . . . . . . -1V to +7V
SS
X9314. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5V ± 10%
X9314-2.7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3V to 5.5V
CC
Voltage on V /R and V /R referenced
H
H
L
L
to V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -8V to +8V
SS
∆V = |V /R - V /R | . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10V
H
H
L L
Lead temperature (soldering 10s) . . . . . . . . . . . . . . . . . . . . .+300°C
Wiper current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±1mA
I
(10s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .±8.8mA
W
CAUTION: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only; the functional
operation of the device (at these or any other conditions above those listed in the operational sections of this specification) is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
Potentiometer Characteristics (Over recommended operating conditions unless otherwise stated.)
LIMITS
SYMBOL
PARAMETER
TEST CONDITIONS/NOTES
MIN
TYP
MAX
±20
+5
UNITS
%
R
End to End Resistance Tolerance
TOTAL
V /R Terminal Voltage
-5
-5
V
H
H
V
V /R Terminal Voltage
+5
V
VL/RL
L
L
Power Rating
Wiper Resistance
Wiper Current
Noise
at +25°C
10
mW
Ω
R
I
= ±1mA, V = 5V
CC
40
100
±4.4
W
W
I
mA
dBV
W
Ref: 1kHz
log (R
-120
Relative variation. Error in step size
between taps.
) - log R
)
w(n - 1)
0.07-
0.003
0.07 + 0.003
w(n)
R
Temperature Coefficient
for -40°C to +85°C
See Circuit #3
±600
ppm/°C
ppm/°C
TOTAL
Ratiometric Temperature Coefficient
Potentiometer Capacitance
±20
pF
C /C /C
10/10/25
H
L
W
NOTE:
1. This parameter is periodically sampled and not 100% tested.
FN8178.2
September 5, 2006
4
X9314
DC Electrical Specifications (Over recommended operating conditions unless otherwise specified.)
LIMITS
(2)
SYMBOL
PARAMETER
Active Current
TEST CONDITIONS
MIN
TYP
MAX
UNITS
I
V
CS = V , U/D = V or V and
1
3
mA
CC
CC
IL IL IH
INC = 0.4V/2.4V @ max. t
CYC
I
Standby Supply Current
CS = V
- 0.3V, U/D and INC = V or
500
±10
µA
SB
CC
- 0.3V
SS
V
CC
I
CS, INC, U/D Input Leakage Current
CS, INC, U/D Input HIGH Voltage
CS, INC, U/D Input LOW Voltage
CS, INC, U/D Input Capacitance
V
= V to V
SS CC
µA
V
LI
IN
V
2
V
+ 1
IH
CC
0.8
10
V
-1
V
IL
(3)
C
V
= 5V, V = V , T = +25°C, f = 1MHz
pF
IN
CC
IN
SS
A
Standard Parts
PART NUMBER
MAXIMUM RESISTANCE
WIPER INCREMENTS
MINIMUM RESISTANCE
X9314W
10kΩ
Log Taper
40Ω
NOTES:
2. Typical values are for T = +25°C and nominal supply voltage.
A
3. This parameter is periodically sampled and not 100% tested.
Test Circuit #1
Test Circuit #2
Circuit #3 SPICE Macromodel
Macro Model
V
/R
H
H
V
/R
H
H
R
TOTAL
Test Point
R
R
L
H
C
L
C
H
C
Test Point
/R
W
V
/R
W
W
10pF
V
W
W
Force
Current
10pF
25pF
V /R
L
V /R
L
L
L
R
W
SYMBOL TABLE
A.C. Conditions of Test
WAVEFORM
INPUTS
OUTPUTS
INPUT PULSE LEVELS
Input rise and fall times
Input reference levels
0V to 3V
10ns
Must be
steady
Will be
steady
1.5V
May change
from Low to
High
Will change
from Low to
High
Mode Selection
May change
from High to
Low
Will change
from High to
Low
CS
INC
U/D
MODE
Don’t Care:
Changes
Allowed
Changing:
State Not
Known
L
H
Wiper up
L
L
Wiper down
N/A
Center Line
is High
Impedance
H
X
L
X
Store wiper position
Standby
H
X
X
No store, return to standby
FN8178.2
September 5, 2006
5
X9314
AC Electrical Specifications (Over recommended operating conditions unless otherwise specified)
LIMITS
(4)
SYMBOL
PARAMETER
MIN
100
100
2.9
1
TYP
MAX
UNITS
ns
t
CS to INC Setup
Cl
lD
DI
t
INC HIGH to U/D Change
U/D to INC Setup
ns
t
µs
t
INC LOW Period
µs
lL
lH
lC
t
t
INC HIGH Period
1
µs
INC Inactive to CS Inactive
CS Deselect Time
1
µs
t
t
20
ms
µs
CPH
t
INC to V Change
W
100
500
IW
CYC
INC Cycle Time
4
µs
(5)
t , t
INC Input Rise and Fall Time
Power-up to Wiper Stable
500
500
50
µs
R
F
(5)
PU
t
µs
t
V
V Power-up Rate
CC
0.2
mV/µs
R
CC
A.C. Timing
CS
t
CYC
t
IC
t
t
t
CPH
IL
IH
t
CI
90%
90%
10%
INC
U/D
t
t
DI
ID
t
t
R
F
t
IW
(6)
MI
V
W
NOTES:
4. Typical values are for T = +25°C and nominal supply voltage.
A
5. This parameter is periodically sampled and not 100% tested.
6. MI in the A.C. timing diagram refers to the minimum incremental change in the V output due to a change in the wiper position.
W
FN8178.2
September 5, 2006
6
X9314
Mini Small Outline Plastic Packages (MSOP)
N
M8.118 (JEDEC MO-187AA)
8 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE
INCHES
MILLIMETERS
E1
E
SYMBOL
MIN
MAX
MIN
0.94
0.05
0.75
0.25
0.09
2.95
2.95
MAX
1.10
0.15
0.95
0.36
0.20
3.05
3.05
NOTES
A
A1
A2
b
0.037
0.002
0.030
0.010
0.004
0.116
0.116
0.043
0.006
0.037
0.014
0.008
0.120
0.120
-
-B-
0.20 (0.008)
INDEX
AREA
1 2
A
B
C
-
-
TOP VIEW
4X θ
9
0.25
(0.010)
R1
c
-
R
GAUGE
PLANE
D
3
E1
e
4
SEATING
PLANE
L
0.026 BSC
0.65 BSC
-
-C-
4X θ
L1
A
A2
E
0.187
0.016
0.199
0.028
4.75
0.40
5.05
0.70
-
L
6
SEATING
PLANE
L1
N
0.037 REF
0.95 REF
-
0.10 (0.004)
-A-
C
C
b
8
8
7
-H-
A1
e
R
0.003
0.003
-
-
0.07
0.07
-
-
-
D
0.20 (0.008)
C
R1
0
-
o
o
o
o
5
15
5
15
-
a
SIDE VIEW
C
L
o
o
o
o
0
6
0
6
-
α
E
1
-B-
Rev. 2 01/03
0.20 (0.008)
C
D
END VIEW
NOTES:
1. These package dimensions are within allowable dimensions of
JEDEC MO-187BA.
2. Dimensioning and tolerancing per ANSI Y14.5M-1994.
3. Dimension “D” does not include mold flash, protrusions or gate
burrs and are measured at Datum Plane. Mold flash, protrusion
and gate burrs shall not exceed 0.15mm (0.006 inch) per side.
4. Dimension “E1” does not include interlead flash or protrusions
- H -
and are measured at Datum Plane.
Interlead flash and
protrusions shall not exceed 0.15mm (0.006 inch) per side.
5. Formed leads shall be planar with respect to one another within
0.10mm (0.004) at seating Plane.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “b” does not include dambar protrusion. Allowable
dambar protrusion shall be 0.08mm (0.003 inch) total in excess
of “b” dimension at maximum material condition. Minimum space
between protrusion and adjacent lead is 0.07mm (0.0027 inch).
- B -
to be determined at Datum plane
-A -
10. Datums
and
.
- H -
11. Controlling dimension: MILLIMETER. Converted inch dimen-
sions are for reference only.
FN8178.2
September 5, 2006
7
X9314
Small Outline Plastic Packages (SOIC)
M8.15 (JEDEC MS-012-AA ISSUE C)
N
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
INDEX
AREA
0.25(0.010)
M
B M
H
INCHES
MILLIMETERS
E
SYMBOL
MIN
MAX
MIN
1.35
0.10
0.33
0.19
4.80
3.80
MAX
1.75
0.25
0.51
0.25
5.00
4.00
NOTES
-B-
A
A1
B
C
D
E
e
0.0532
0.0040
0.013
0.0688
0.0098
0.020
-
-
1
2
3
L
9
SEATING PLANE
A
0.0075
0.1890
0.1497
0.0098
0.1968
0.1574
-
-A-
3
h x 45°
D
4
-C-
0.050 BSC
1.27 BSC
-
α
H
h
0.2284
0.0099
0.016
0.2440
0.0196
0.050
5.80
0.25
0.40
6.20
0.50
1.27
-
e
A1
C
5
B
0.10(0.004)
L
6
0.25(0.010) M
C
A M B S
N
α
8
8
7
NOTES:
0°
8°
0°
8°
-
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
Rev. 1 6/05
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Inter-
lead flash and protrusions shall not exceed 0.25mm (0.010 inch) per
side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact.
FN8178.2
September 5, 2006
8
X9314
Plastic Dual-In-Line Packages (PDIP)
E
N
1
D
PIN #1
INDEX
A2
A
E1
SEATING
PLANE
L
c
A1
NOTE 5
2
N/2
eA
eB
e
b
b2
MDP0031
PLASTIC DUAL-IN-LINE PACKAGE
SYMBOL
PDIP8
0.210
0.015
0.130
0.018
0.060
0.010
0.375
0.310
0.250
0.100
0.300
0.345
0.125
8
PDIP14
0.210
0.015
0.130
0.018
0.060
0.010
0.750
0.310
0.250
0.100
0.300
0.345
0.125
14
PDIP16
0.210
0.015
0.130
0.018
0.060
0.010
0.750
0.310
0.250
0.100
0.300
0.345
0.125
16
PDIP18
PDIP20
0.210
0.015
0.130
0.018
0.060
0.010
1.020
0.310
0.250
0.100
0.300
0.345
0.125
20
TOLERANCE
MAX
NOTES
A
A1
A2
b
0.210
0.015
0.130
0.018
0.060
0.010
0.890
0.310
0.250
0.100
0.300
0.345
0.125
18
MIN
±0.005
±0.002
b2
c
+0.010/-0.015
+0.004/-0.002
±0.010
D
1
2
E
+0.015/-0.010
±0.005
E1
e
Basic
eA
eB
L
Basic
±0.025
±0.010
N
Reference
Rev. B 2/99
NOTES:
1. Plastic or metal protrusions of 0.010” maximum per side are not included.
2. Plastic interlead protrusions of 0.010” maximum per side are not included.
3. Dimensions E and eA are measured with the leads constrained perpendicular to the seating plane.
4. Dimension eB is measured with the lead tips unconstrained.
5. 8 and 16 lead packages have half end-leads as shown.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN8178.2
September 5, 2006
9
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