X9315USZ-2.7T1 [RENESAS]
Low Noise, Low Power, 32 Taps Digitally Controlled Potentiometer (XDCPâ¢);
| 型号： | X9315USZ-2.7T1 |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | Low Noise, Low Power, 32 Taps Digitally Controlled Potentiometer (XDCPâ¢) 光电二极管 转换器 电阻器 |
| 文件： | 总16页 (文件大小：715K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATASHEET
X9315
FN8179
Rev.2.00
December 21, 2009
Low Noise, Low Power, 32 Taps Digitally Controlled Potentiometer
(XDCP™)
The Intersil X9315 is a digitally controlled potentiometer
(XDCP). The device consists of a resistor array, wiper
switches, a control section, and nonvolatile memory. The
wiper position is controlled by a 3-wire interface.
Features
• Solid-state potentiometer
• 3-wire serial interface
The potentiometer is implemented by a resistor array
composed of 31 resistive elements and a wiper switching
network. Between each element and at either end are tap
points accessible to the wiper terminal. The position of the
wiper element is controlled by the CS, U/D, and INC inputs.
The position of the wiper can be stored in nonvolatile
memory and then be recalled upon a subsequent power-up
operation.
• 32 wiper tap points
- Wiper position stored in nonvolatile memory and
recalled on power-up
• 31 resistive elements
- Temperature compensated
- End to end resistance range ± 20%
- Terminal voltage, 0 to V
CC
• Low power CMOS
The device can be used as a three-terminal potentiometer or
as a two-terminal variable resistor in a wide variety of
applications including:
- V
CC
= 2.7V or 5V
- Active current, 80/400µA max.
- Standby current, 5µA max.
• Control
• High reliability
• Parameter Adjustments
• Signal Processing
- Endurance, 100,000 data changes per bit
- Register data retention, 100 years
• R
TOTAL
values = 10k, 50k, 100k
• Packages
- 8 Ld SOIC, MSOP and PDIP
• Pb-free available (RoHS compliant)
Block Diagram
U/D
INC
CS
5-Bit
R /V
31
H
H
Up/Down
Counter
V
(Supply Voltage)
CC
30
29
28
R /V
H
H
Up/Down
(U/D)
5-Bit
Nonvolatile
Memory
Control
and
One
of
Increment
(INC)
R
/V
W
W
Memory
Transfer
Gates
Resistor
Array
Thirty
Device Select
(CS)
Two
R /V
Decoder
L
L
2
Store and
Recall
Control
Circuitry
V
(Ground)
SS
1
0
V
V
CC
SS
General
R /V
L
L
/V
R
W
W
Detailed
FN8179 Rev.2.00
December 21, 2009
Page 1 of 16
X9315
Ordering Information
V
LIMITS
(V)
R
TEMP RANGE
(°C)
PKG.
DWG. #
CC
TOTAL
(k)
PART NUMBER
X9315WMZ (Note 2)
X9315WMZT1 (Notes 1, 2)
X9315WMIT2 (Note 1)
X9315WMIZ (Note 2)
X9315WMIZT1 (Notes 1, 2)
X9315WP
PART MARKING
DDT
PACKAGE
5 ±10%
10
0 to 70
0 to 70
8 Ld MSOP (Pb-free) M8.118
8 Ld MSOP (Pb-free) M8.118
DDT
AAX
-40 to 85
-40 to 85
-40 to 85
0 to 70
8 Ld MSOP
M8.118
AKW
8 Ld MSOP (Pb-free) M8.118
8 Ld MSOP (Pb-free) M8.118
AKW
X9315WP
X9315W
X9315W Z
X9315W Z
X9315W I
X9315W I
X9315W ZI
X9315W ZI
DDS
8 Ld PDIP
8 Ld SOIC
MDP0031
M8.15E
X9315WST1 (Note 1)
X9315WSZ (Note 2)
0 to 70
0 to 70
8 Ld SOIC (Pb-free) M8.15
8 Ld SOIC (Pb-free) M8.15
X9315WSZT1 (Notes 1, 2)
X9315WSI
0 to 70
-40 to 85
-40 to 85
-40 to 85
-40 to 85
0 to 70
8 Ld SOIC
8 Ld SOIC
M8.15E
M8.15E
X9315WSIT1 (Note 1)
X9315WSIZ (Note 2)
X9315WSIZT1 (Notes 1, 2)
X9315UMZ (Note 2)
8 Ld SOIC (Pb-free) M8.15
8 Ld SOIC (Pb-free) M8.15
8 Ld MSOP (Pb-free) M8.118
8 Ld MSOP (Pb-free) M8.118
50
X9315UMZT1 (Notes 1, 2)
X9315UMI
DDS
0 to 70
AEB
-40 to 85
-40 to 85
-40 to 85
-40 to 85
0 to 70
8 Ld MSOP
8 Ld MSOP
M8.118
M8.118
X9315UMIT1 (Notes 1, 2)
X9315UMIZ (Note 2)
X9315UMIZT1 (Notes 1, 2)
X9315UST2 (Note 1)
X9315USZ (Note 2)
AEB
DDR
8 Ld MSOP (Pb-free) M8.118
8 Ld MSOP (Pb-free) M8.118
DDR
X9315U
X9315U Z
X9315U Z
X9315U ZI
X9315U ZI
DDN
8 Ld SOIC
M8.15E
0 to 70
8 Ld SOIC (Pb-free) M8.15
8 Ld SOIC (Pb-free) M8.15
8 Ld SOIC (Pb-free) M8.15
8 Ld SOIC (Pb-free) M8.15
8 Ld MSOP (Pb-free) M8.118
8 Ld MSOP (Pb-free) M8.118
8 Ld MSOP (Pb-free) M8.118
8 Ld MSOP (Pb-free) M8.118
8 Ld SOIC (Pb-free) M8.15
8 Ld SOIC (Pb-free) M8.15
8 Ld SOIC (Pb-free) M8.15
8 Ld SOIC (Pb-free) M8.15
8 Ld MSOP (Pb-free) M8.118
8 Ld MSOP (Pb-free) M8.118
X9315USZT1 (Notes 1, 2)
X9315USIZ (Note 2)
0 to 70
-40 to 85
-40 to 85
0 to 70
X9315USIZT1 (Notes 1, 2)
X9315TMZ (Note 2)
100
X9315TMZT1 (Notes 1, 2)
X9315TMIZ (Note 2)
DDN
0 to 70
DDL
-40 to 85
-40 to 85
0 to 70
X9315TMIZT1 (Notes 1, 2)
X9315TSZ (Note 2)
DDL
X9315T Z
X9315T Z
X9315T ZI
X9315T ZI
AOI
X9315TSZT1 (Notes 1, 2)
X9315TSIZ (Note 2)
0 to 70
-40 to 85
-40 to 85
0 to 70
X9315TSIZT1 (Notes 1, 2)
X9315WMZ-2.7 (Note 2)
X9315WMZ-2.7T1 (Notes 1, 2)
X9315WMI-2.7T2 (Note 1)
X9315WMIZ-2.7 (Note 2)
2.7 to 5.5
10
AOI
0 to 70
AAV
-40 to 85
-40 to 85
-40 to 85
0 to 70
8 Ld MSOP
M8.118
AKX
8 Ld MSOP (Pb-free) M8.118
8 Ld MSOP (Pb-free) M8.118
X9315WMIZ-2.7T1 (Notes 1, 2) AKX
X9315WS-2.7
X9315W F
8 Ld SOIC
M8.15E
FN8179 Rev.2.00
Page 2 of 16
December 21, 2009
X9315
Ordering Information (Continued)
V
LIMITS
(V)
R
TEMP RANGE
(°C)
PKG.
DWG. #
CC
TOTAL
(k)
PART NUMBER
X9315WS-2.7T1 (Note 1)
X9315WSZ-2.7 (Note 2)
X9315WSZ-2.7T1 (Notes 1, 2)
X9315WSI-2.7T1 (Note 1)
X9315WSIZ-2.7 (Note 2)
X9315WSIZ-2.7T1 (Notes 1, 2)
X9315UMZ-2.7 (Note 2)
X9315UMZ-2.7T1 (Notes 1, 2)
X9315UMIZ-2.7 (Note 2)
X9315UMIZ-2.7T1 (Notes 1, 2)
X9315US-2.7T2 (Note 1)
X9315USZ-2.7 (Note 2)
X9315USZ-2.7T1 (Notes 1, 2)
X9315USI-2.7
PART MARKING
PACKAGE
8 Ld SOIC
X9315W F
X9315W ZF
X9315W ZF
X9315W G
X9315W ZG
X9315W ZG
AKU
2.7 to 5.5
10
0 to 70
0 to 70
M8.15E
8 Ld SOIC (Pb-free) M8.15
8 Ld SOIC (Pb-free) M8.15
0 to 70
-40 to 85
-40 to 85
-40 to 85
0 to 70
8 Ld SOIC
M8.15E
8 Ld SOIC (Pb-free) M8.15
8 Ld SOIC (Pb-free) M8.15
8 Ld MSOP (Pb-free) M8.118
8 Ld MSOP (Pb-free) M8.118
8 Ld MSOP (Pb-free) M8.118
8 Ld MSOP (Pb-free) M8.118
50
AKU
0 to 70
AJG
-40 to 85
-40 to 85
0 to 70
AJG
X9315U F
X9315U ZF
X9315U ZF
X9315U G
X9315U ZG
X9315U ZG
DDP
8 Ld SOIC
M8.15E
0 to 70
8 Ld SOIC (Pb-free) M8.15
8 Ld SOIC (Pb-free) M8.15
0 to 70
-40 to 85
-40 to 85
-40 to 85
0 to 70
8 Ld SOIC
M8.15E
X9315USIZ-2.7 (Note 2)
X9315USIZ-2.7T1 (Notes 1, 2)
X9315TMZ-2.7 (Note 2)
X9315TMZ-2.7T1 (Notes 1, 2)
X9315TMI-2.7T1 (Note 1)
X9315TMIZ-2.7 (Note 2)
X9315TMIZ-2.7T1 (Notes 1, 2)
X9315TSZ-2.7 (Note 2)
X9315TSZ-2.7T1 (Notes 1, 2)
X9315TSIZ-2.7 (Note 2)
X9315TSIZ-2.7T1 (Notes 1, 2)
NOTES:
8 Ld SOIC (Pb-free) M8.15
8 Ld SOIC (Pb-free) M8.15
8 Ld MSOP (Pb-free) M8.118
8 Ld MSOP (Pb-free) M8.118
100
DDP
0 to 70
ADY
-40 to 85
-40 to 85
-40 to 85
0 to 70
8 Ld MSOP
M8.118
DDM
8 Ld MSOP (Pb-free) M8.118
8 Ld MSOP (Pb-free) M8.118
8 Ld SOIC (Pb-free) M8.15
8 Ld SOIC (Pb-free) M8.15
8 Ld SOIC (Pb-free) M8.15
8 Ld SOIC (Pb-free) M8.15
DDM
X9315T ZF
X9315T ZF
X9315T ZG
X9315T ZG
0 to 70
-40 to 85
-40 to 85
1. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-
020.
FN8179 Rev.2.00
Page 3 of 16
December 21, 2009
X9315
operation is complete the X9315 will be placed in the low
power standby mode until the device is selected once again.
Pin Configuration
X9315
(8 LD MSOP, SOIC, PDIP)
Principles of Operation
TOP VIEW
There are three sections of the X9315: the input control,
counter and decode section; the nonvolatile memory; and the
resistor array. The input control section operates just like an
up/down counter. The output of this counter is decoded to turn
on a single electronic switch connecting a point on the resistor
array to the wiper output. Under the proper conditions the
contents of the counter can be stored in nonvolatile memory
and retained for future use. The resistor array is comprised of
31 individual resistors connected in series. At either end of the
array and between each resistor is an electronic switch that
transfers the connection at that point to the wiper.
INC
U/D
1
2
3
4
8
7
6
5
V
CC
CS
X9315
R
/V
H
R /V
L
H
L
V
R
/V
W
SS
W
Pin Names
SYMBOL
DESCRIPTION
High terminal
Wiper terminal
Low terminal
Ground
R /V
H
H
W
L
The wiper, when at either fixed terminal, acts like its
mechanical equivalent and does not move beyond the last
position. That is, the counter does not wrap around when
clocked to either extreme.
R
/V
W
R /V
L
V
V
SS
Supply voltage
The electronic switches on the device operate in a “make
before break” mode when the wiper changes tap positions. If
the wiper is moved several positions, multiple taps are
CC
U/D
Up/Down control input
Increment control input
Chip Select control input
INC
CS
connected to the wiper for t (INC to V change). The
IW
W
R
value for the device can temporarily be reduced by a
TOTAL
significant amount if the wiper is moved several positions.
Pin Description
When the device is powered-down, the last wiper position
stored will be maintained in the nonvolatile memory. When
power is restored, the contents of the memory are recalled and
the wiper is set to the value last stored.
R /V and R /V
H
L
H
L
The high (R /V ) and low (R /V ) terminals of the X9315 are
H
L
H
L
equivalent to the fixed terminals of a mechanical
potentiometer. The minimum voltage is V and the maximum
SS
Instructions and Programming
is V . The terminology of R /V and R /V references the
CC
L
H
L
H
The INC, U/D and CS inputs control the movement of the wiper
along the resistor array. With CS set LOW the device is
selected and enabled to respond to the U/D and INC inputs.
HIGH to LOW transitions on INC will increment or decrement
(depending on the state of the U/D input) a five bit counter. The
output of this counter is decoded to select one of thirty two
wiper positions along the resistive array.
relative position of the terminal in relation to wiper movement
direction selected by the U/D input, and not the voltage
potential on the terminal.
RW/VW
R /V is the wiper terminal and is equivalent to the movable
W
w
terminal of a mechanical potentiometer. The position of the
wiper within the array is determined by the control inputs. The
The value of the counter is stored in nonvolatile memory
whenever CS transitions HIGH while the INC input is also
HIGH.
wiper terminal series resistance is typically 200 at V
= 5V.
CC
Up/Down (U/D)
The system may select the X9315, move the wiper and
deselect the device without having to store the latest wiper
position in nonvolatile memory. After the wiper movement is
performed as described above and once the new position is
reached, the system must keep INC LOW while taking CS
HIGH. The new wiper position will be maintained until changed
by the system or until a power-up/down cycle recalled the
previously stored data.
The U/D input controls the direction of the wiper movement
and whether the counter is incremented or decremented.
Increment (INC)
The INC input is negative-edge triggered. Toggling INC will
move the wiper and either increment or decrement the counter
in the direction indicated by the logic level on the U/D input.
Chip Select (CS)
This procedure allows the system to always power-up to a
preset value stored in nonvolatile memory; then during system
operation minor adjustments could be made. The adjustments
The device is selected when the CS input is LOW. The current
counter value is stored in nonvolatile memory when CS is
returned HIGH while the INC input is also HIGH. After the store
FN8179 Rev.2.00
Page 4 of 16
December 21, 2009
X9315
might be based on user preference, system parameter
changes due to temperature drift, etc...
Power-up and Down Requirements
There are no restrictions on the power-up or power-down
conditions of V
and the voltages applied to the
The state of U/D may be changed while CS remains LOW. This
allows the host system to enable the device and then move the
wiper up and down until the proper trim is attained.
CC
potentiometer pins provided that V
is always more positive
CC
than or equal to V , V , and V , i.e., V
V , V , V . The
H
L
W
CC
H
L
W
V
ramp rate spec is always in effect.
CC
Mode Selection
CS
INC
U/D
MODE
L
H
Wiper up
L
L
Wiper down
H
X
Store wiper position to nonvolatile
memory
H
X
L
L
L
X
X
H
L
Standby
No store, return to standby
Wiper Up (not recommended)
Wiper Down (not recommended)
FN8179 Rev.2.00
December 21, 2009
Page 5 of 16
X9315
Absolute Maximum Ratings
Thermal Information
Temperature under bias. . . . . . . . . . . . . . . . . . . . . .-65C to +135C
Storage temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Voltage on CS, INC, U/D, V , V and
Thermal Resistance (Typical, Notes 3, 4)
(°C/W)
(°C/W)
JC
JA
8 Ld SOIC . . . . . . . . . . . . . . . . . . . . . .
8 Ld MSOP. . . . . . . . . . . . . . . . . . . . . .
8 Ld PDIP. . . . . . . . . . . . . . . . . . . . . . .
Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
105
154
85
68
58
57
H
L
V
with respect to V
. . . . . . . . . . . . . . . . . . . . . . . -1V to +7V
SS
CC
V = |V –V | . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5V
H
L
I
(10 seconds). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .±7.5mA
W
Recommended Operating Conditions
Temperature (Commercial) . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C
Temperature (Industrial). . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C
Supply Voltage (V ) (Note 8) Limits
CC
X9315. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5V ± 10%
X9315-2.7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V to 5.5V
Max Wiper Current, I . . . . . . . . . . . . . . . . . . . . . . . . . . . . .±3.75mA
W
Max Power Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10mW
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTES:
3. is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
JA
4. For , the “case temp” location is taken at the package top center.
JC
Potentiometer Characteristics (Over recommended operating conditions unless otherwise stated.)
LIMITS
MIN
TYP
MAX
(Note 9) UNIT
(Note 9) (Note 8)
SYMBOL
PARAMETER
TEST CONDITIONS/NOTES
End to end resistance tolerance
-20
0
+20
%
V
V
V
V
terminal voltage
terminal voltage
V
V
VH
H
L
CC
CC
V
0
V
VL
R
Wiper resistance
Wiper resistance
Noise
I
I
= [V(R ) - V(R )]/ R
, V
= 5V
200
400
-120
3
400
W
W
W
W
H
L
TOTAL CC
R
= [V(R ) - V(R )]/ R
, V
TOTAL CC
= 2.7V
1000
H
L
Ref: 1kHz
dBV
%
Resolution
Absolute linearity (Note 5)
V
V
- V
±1
MI
(Note 7)
w(n)(actual)
w(n)(expected)
Relative linearity (Note 6)
- [V
]
w(n) + MI
±0.2
MI
w(n + 1)
(Note 7)
R
temperature coefficient
±300
±20
ppm/°C
ppm/°C
pF
TOTAL
Ratiometric temperature coefficient
Potentiometer capacitances
C /C /C
See circuit #3 on page 7
10/10/25
H
L
W
NOTES:
5. Absolute linearity is utilized to determine actual wiper voltage versus expected voltage = (V
(actual) - V
(expected)) = ±1 Ml Maximum.
w(n)
w(n)
6. Relative linearity is a measure of the error in step size between taps = R
- [R
+ Ml] = ±0.2 Ml.
w(n)
W(n+1)
7. 1 Ml = Minimum Increment = R
/31.
TOT
8. Typical values are for T = +25°C and nominal supply voltage.
A
9. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by
characterization and are not production tested.
FN8179 Rev.2.00
Page 6 of 16
December 21, 2009
X9315
DC Electrical Specifications (Over recommended operating conditions unless otherwise specified.
LIMITS
MIN
(Note 9)
TYP
(Note 8)
MAX
(Note 9)
SYMBOL
PARAMETER
Supply Voltage
TEST CONDITIONS
UNIT
V
V
X9315
4.5
2.7
5.5
5.5
80
CC
X9315-2.7
V
I
I
V
V
active current (Increment)
CS = V , U/D = V or V and INC = 0.4V
µA
CC1
CC2
CC
CC
IL
IL
IH
@ max. t
CYC
active current (Store) (EEPROM CS = V , U/D = V or V and INC = V
@
400
5
µA
µA
IH
IL
IH
IH
Store)
max. t
WR
I
Standby supply current
CS = V - 0.3V, U/D and INC = V or V
CC SS
SB
CC
- 0.3V
I
CS, INC, U/D input leakage current
CS, INC, U/D input HIGH voltage
CS, INC, U/D input LOW voltage
CS, INC, U/D input capacitance
V
= V to V
SS CC
-10
+10
µA
V
LI
IN
V
V
x 0.7
V
CC
+ 0.5
x 0.1
IH
CC
V
-0.5
V
V
IL
CC
C
V
= 5V, V = V , T = +25°C, f = 1MHz
10
pF
IN
CC
IN
SS
A
Endurance and Data Retention
PARAMETER
MIN
UNIT
Minimum endurance
Data retention
100,000
100
Data changes per bit
Years
Test Circuit #1
Test Circuit #2
Circuit #3 SPICE Macro Model
V
/R
V
/R
H
H
H
H
R
TOTAL
Test Point
R
R
L
H
C
L
C
W
C
V
H
S
Test Point
/R
10pF
V
/R
W
W
V
W
W
25pF
Force
Current
10pF
V /R
V /R
L
L
L
L
R
W
AC Conditions of Test
Input pulse levels
0V to 3V
10ns
Input rise and fall times
Input reference levels
1.5V
AC Electrical Specifications (Over recommended operating conditions unless otherwise specified)
LIMITS
MIN
(Note 9)
TYP
(Note 8)
MAX
(Note 9)
SYMBOL
PARAMETER
UNIT
ns
t
t
CS to INC setup
100
100
2.9
1
Cl
lD
DI
INC HIGH to U/D change
U/D to INC setup
ns
t
µs
t
INC LOW period
µs
lL
t
INC HIGH period
1
µs
lH
FN8179 Rev.2.00
Page 7 of 16
December 21, 2009
X9315
AC Electrical Specifications (Over recommended operating conditions unless otherwise specified) (Continued)
LIMITS
MIN
TYP
MAX
SYMBOL
PARAMETER
INC Inactive to CS inactive
(Note 9)
(Note 8)
(Note 9)
UNIT
µs
t
1
lC
t
t
CS Deselect time (NO STORE)
CS Deselect time (STORE)
INC to Vw change
100
10
ns
CPH
CPH
ms
µs
t
1
5
IW
t
INC cycle time
4
µs
CYC
t
t
INC input rise and fall time
500
5
µs
R, F
(Note 10)
t
Power-up to wiper stable
µs
V/ms
ms
PU
(Note 10)
t
V
V
power-up rate
0.2
50
10
R
CC
CC
(Note 10)
t
Store cycle
5
WR
NOTE:
10. This parameter is not 100% tested.
AC Timing
CS
t
CYC
(Store)
t
t
t
t
t
CI
IL
IH
IC
CPH
90%
90%
INC
U/D
10%
t
t
t
R
ID
DI
F
t
IW
(Note 9)
MI
V
W
NOTE:
11. MI in the A.C. timing diagram refers to the minimum incremental change in the V output due to a change in the wiper position.
W
FN8179 Rev.2.00
Page 8 of 16
December 21, 2009
X9315
Symbol Table
WAVEFORM
INPUTS
OUTPUTS
Must be
steady
Will be
steady
May change
from Low to
High
Will change
from Low to
High
May change
from High to
Low
Will change
from High to
Low
Don’t Care:
Changes
Allowed
Changing:
State Not
Known
N/A
Center Line
is High
Impedance
Performance Characteristics (Typical)
Typical Noise
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
0
10
20 30
40 50
60 70
80 90 100 110 120 130 140 150 160 170 180 190 200
Frequency (kHz)
FN8179 Rev.2.00
Page 9 of 16
December 21, 2009
X9315
Typical Rtotal vs. Temperature
10000
9800
9600
9400
9200
9000
8800
8600
8400
8200
8000
-55
-45 -35 -25 -15 -5
5
35 45
C°
75 85 95 105 115 125
15
25
55
Temperature65
Typical Total Resistance Temperature Coefficient
0
-50
-100
-150
PPM
-200
-250
-300
-350
-55 -45 -35 -25 -15
-5
5
15
25
35
45
55
65
75
85
95
105 115 125 °C
Temperature
Typical Wiper Resistance
800
700
600
500
400
300
200
100
0
0
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
V
= 2.7V
CC
Tap
FN8179 Rev.2.00
Page 10 of 16
December 21, 2009
X9315
Typical Absolute% Error per Tap Position
40.0%
30.0%
20.0%
10.0%
0.0%
-10.0%
-20.0%
-30.0%
-40.0%
0
3
6
9
12
15
18
21
24
27
30
Tap
Typical Relative% Error per Tap Position
20.0%
15.0%
10.0%
5.0%
0.0%
-5.0%
-10.0%
-15.0%
-20.0%
0
3
6
9
12
15
18
21
24
27
30
Tap
Applications Information
Electronic digitally controlled (XDCP) potentiometers provide
three powerful application advantages; (1) the variability and
reliability of a solid-state potentiometer, (2) the flexibility of
computer-based digital controls, and (3) the retentivity of
nonvolatile memory used for the storage of multiple
potentiometer settings or data.
FN8179 Rev.2.00
Page 11 of 16
December 21, 2009
X9315
Basic Configurations of Electronic Potentiometers
V
R
V
R
V
V
H
L
V
/R
W
W
I
Three terminal potentiometer;
variable voltage divider
Two terminal variable resistor;
variable current
Basic Circuits
Noninverting Amplifier
Buffered Reference Voltage
Cascading Techniques
R
+5V
1
+V
+V
LM308A
+V
V
+
–
S
+5V
V
O
V
OP-07
W
+
–
V
REF
-5V
X
V
OUT
R
/V
W
W
R
2
+V
-5V
= V /R
R
1
R
/V
W
V
W
OUT
W
W
(a)
(b)
V
= (1 + R /R )V
2 1 S
O
Voltage Regulator
Comparator with Hysteresis
V
V
(REG)
O
317
IN
LT311A
V
–
+
S
V
O
R
1
I
adj
R
2
R
R
1
2
V
V
= {R /(R + R )} V (max)
1 1 2 O
UL
LL
= {R /(R + R )} V (min)
1 1 2 O
V
(REG) = 1.25V (1 + R /R ) + I
R
adj 2
O
2
1
(for additional circuits see AN115)
FN8179 Rev.2.00
Page 12 of 16
December 21, 2009
X9315
Mini Small Outline Plastic Packages (MSOP)
N
M8.118 (JEDEC MO-187AA)
8 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE
INCHES
MILLIMETERS
E1
E
SYMBOL
MIN
MAX
MIN
0.94
0.05
0.75
0.25
0.09
2.95
2.95
MAX
1.10
0.15
0.95
0.36
0.20
3.05
3.05
NOTES
A
A1
A2
b
0.037
0.002
0.030
0.010
0.004
0.116
0.116
0.043
0.006
0.037
0.014
0.008
0.120
0.120
-
-B-
0.20 (0.008)
INDEX
AREA
1 2
A
B
C
-
-
TOP VIEW
4X
9
0.25
(0.010)
R1
c
-
R
GAUGE
PLANE
D
3
E1
e
4
SEATING
PLANE
L
0.026 BSC
0.65 BSC
-
-C-
4X
L1
A
A2
E
0.187
0.016
0.199
0.028
4.75
0.40
5.05
0.70
-
L
6
SEATING
PLANE
L1
N
0.037 REF
0.95 REF
-
0.10 (0.004)
-A-
C
C
b
8
8
7
-H-
A1
e
R
0.003
0.003
-
-
0.07
0.07
-
-
-
D
0.20 (0.008)
C
R1
0
-
o
o
o
o
5
15
5
15
-
a
SIDE VIEW
C
L
o
o
o
o
0
6
0
6
-
E
1
-B-
Rev. 2 01/03
0.20 (0.008)
C
D
END VIEW
NOTES:
1. These package dimensions are within allowable dimensions of
JEDEC MO-187BA.
2. Dimensioning and tolerancing per ANSI Y14.5M-1994.
3. Dimension “D” does not include mold flash, protrusions or gate
burrs and are measured at Datum Plane. Mold flash, protrusion
and gate burrs shall not exceed 0.15mm (0.006 inch) per side.
4. Dimension “E1” does not include interlead flash or protrusions
- H -
and are measured at Datum Plane.
Interlead flash and
protrusions shall not exceed 0.15mm (0.006 inch) per side.
5. Formed leads shall be planar with respect to one another within
0.10mm (0.004) at seating Plane.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “b” does not include dambar protrusion. Allowable
dambar protrusion shall be 0.08mm (0.003 inch) total in excess
of “b” dimension at maximum material condition. Minimum space
between protrusion and adjacent lead is 0.07mm (0.0027 inch).
- B -
to be determined at Datum plane
-A -
10. Datums
and
.
- H -
11. Controlling dimension: MILLIMETER. Converted inch dimen-
sions are for reference only.
FN8179 Rev.2.00
Page 13 of 16
December 21, 2009
X9315
Package Outline Drawing
M8.15E
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
Rev 0, 08/09
4
4.90 ± 0.10
A
DETAIL "A"
0.22 ± 0.03
B
6.0 ± 0.20
3.90 ± 0.10
4
PIN NO.1
ID MARK
5
(0.35) x 45°
4° ± 4°
0.43 ± 0.076
1.27
0.25 M C A B
SIDE VIEW “B”
TOP VIEW
1.75 MAX
1.45 ± 0.1
0.25
GAUGE PLANE
C
SEATING PLANE
0.175 ± 0.075
SIDE VIEW “A
0.10 C
0.63 ±0.23
DETAIL "A"
(0.60)
(1.27)
NOTES:
(1.50)
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3. Unless otherwise specified, tolerance : Decimal ± 0.05
(5.40)
4. Dimension does not include interlead flash or protrusions.
Interlead flash or protrusions shall not exceed 0.25mm per side.
The pin #1 identifier may be either a mold or mark feature.
Reference to JEDEC MS-012.
5.
6.
TYPICAL RECOMMENDED LAND PATTERN
FN8179 Rev.2.00
December 21, 2009
Page 14 of 16
X9315
Plastic Dual-In-Line Packages (PDIP)
E
N
1
D
PIN #1
INDEX
A2
A
E1
SEATING
PLANE
L
c
A1
NOTE 5
2
N/2
eA
eB
e
b
b2
MDP0031
PLASTIC DUAL-IN-LINE PACKAGE
SYMBOL
PDIP8
0.210
0.015
0.130
0.018
0.060
0.010
0.375
0.310
0.250
0.100
0.300
0.345
0.125
8
PDIP14
0.210
0.015
0.130
0.018
0.060
0.010
0.750
0.310
0.250
0.100
0.300
0.345
0.125
14
PDIP16
0.210
0.015
0.130
0.018
0.060
0.010
0.750
0.310
0.250
0.100
0.300
0.345
0.125
16
PDIP18
PDIP20
0.210
0.015
0.130
0.018
0.060
0.010
1.020
0.310
0.250
0.100
0.300
0.345
0.125
20
TOLERANCE
MAX
NOTES
A
A1
A2
b
0.210
0.015
0.130
0.018
0.060
0.010
0.890
0.310
0.250
0.100
0.300
0.345
0.125
18
MIN
±0.005
±0.002
b2
c
+0.010/-0.015
+0.004/-0.002
±0.010
D
1
2
E
+0.015/-0.010
±0.005
E1
e
Basic
eA
eB
L
Basic
±0.025
±0.010
N
Reference
Rev. B 2/99
NOTES:
1. Plastic or metal protrusions of 0.010” maximum per side are not included.
2. Plastic interlead protrusions of 0.010” maximum per side are not included.
3. Dimensions E and eA are measured with the leads constrained perpendicular to the seating plane.
4. Dimension eB is measured with the lead tips unconstrained.
5. 8 and 16 lead packages have half end-leads as shown.
FN8179 Rev.2.00
Page 15 of 16
December 21, 2009
X9315
Small Outline Plastic Packages (SOIC)
M8.15 (JEDEC MS-012-AA ISSUE C)
N
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
INDEX
AREA
0.25(0.010)
M
B M
H
INCHES
MILLIMETERS
E
SYMBOL
MIN
MAX
MIN
1.35
0.10
0.33
0.19
4.80
3.80
MAX
1.75
0.25
0.51
0.25
5.00
4.00
NOTES
-B-
A
A1
B
C
D
E
e
0.0532
0.0040
0.013
0.0688
0.0098
0.020
-
-
1
2
3
L
9
SEATING PLANE
A
0.0075
0.1890
0.1497
0.0098
0.1968
0.1574
-
-A-
3
h x 45°
D
4
-C-
0.050 BSC
1.27 BSC
-
H
h
0.2284
0.0099
0.016
0.2440
0.0196
0.050
5.80
0.25
0.40
6.20
0.50
1.27
-
e
A1
C
5
B
0.10(0.004)
L
6
0.25(0.010) M
C
A M B S
N
8
8
7
NOTES:
0°
8°
0°
8°
-
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
Rev. 1 6/05
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Inter-
lead flash and protrusions shall not exceed 0.25mm (0.010 inch) per
side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact.
© Copyright Intersil Americas LLC 2005-2009. All Rights Reserved.
All trademarks and registered trademarks are the property of their respective owners.
For additional products, see www.intersil.com/en/products.html
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such
modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are
current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its
subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN8179 Rev.2.00
Page 16 of 16
December 21, 2009
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