X9317TP-2.7T1 [RENESAS]
100K DIGITAL POTENTIOMETER, INCREMENT/DECREMENT CONTROL INTERFACE, 100 POSITIONS, PDIP8, PLASTIC, DIP-8;
| 型号： | X9317TP-2.7T1 |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | 100K DIGITAL POTENTIOMETER, INCREMENT/DECREMENT CONTROL INTERFACE, 100 POSITIONS, PDIP8, PLASTIC, DIP-8 光电二极管 转换器 电阻器 |
| 文件： | 总15页 (文件大小：299K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
X9317
®
Low Noise, Low Power, 100 Taps
Data Sheet
June 25, 2008
FN8183.4
Digitally Controlled Potentiometer
(XDCP™)
Features
• Solid-State Potentiometer
• 3-Wire Serial Up/Down Interface
• 100 Wiper Tap Points
The Intersil X9317 is a digitally controlled potentiometer
(XDCP™). The device consists of a resistor array, wiper
switches, a control section, and nonvolatile memory. The
wiper position is controlled by a 3-wire interface.
- Wiper Position Stored in Nonvolatile Memory and
Recalled on Power-up
The potentiometer is implemented by a resistor array
composed of 99 resistive elements and a wiper switching
network. Between each element and at either end are tap
points accessible to the wiper terminal. The position of the
wiper element is controlled by the CS, U/D, and INC inputs.
The position of the wiper can be stored in nonvolatile
memory and then be recalled upon a subsequent power-up
operation.
• 99 Resistive Elements
- Temperature Compensated
- End-to-end Resistance Range ±20%
• Low Power CMOS
- V
CC
= 2.7V to 5.5V, and 5V ±10%
- Standby Current <1µA
• High Reliability
The device can be used as a three-terminal potentiometer
for voltage control or as a two-terminal variable resistor for
current control in a wide variety of applications.
- Endurance, 100,000 Data Changes per Bit
- Register Data Retention, 100 years
• R
TOTAL
Values = 1kΩ, 10kΩ, 50kΩ, 100kΩ
Pinouts
• Packages
- 8 Ld SOIC, PDIP, TSSOP, and MSOP
X9317
(8 LD TSSOP)
TOP VIEW
• Pb-Free Available (RoHS Compliant)
Applications
R
CS
1
2
3
4
8
7
6
5
L
• LCD Bias Control
V
R
V
CC
INC
U/D
W
X9317
• DC Bias Adjustment
• Gain and Offset Trim
• Laser Diode Bias Control
• Voltage Regulator Output Control
SS
R
H
X9317
(8 LD PDIP, 8 LD SOIC, 8 LD MSOP)
TOP VIEW
V
INC
U/D
1
2
3
4
8
7
6
5
CC
CS
X9317
R
L
R
H
V
R
SS
W
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
XDCP is a trademark of Intersil Americas, Inc. Copyright Intersil Americas Inc. 2004-2005, 2008. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
1
X9317
Ordering Information
V
LIMITS
(V)
R
TEMPERATURE
RANGE (°C)
PKG.
DWG. #
CC
TOTAL
(kΩ)
PART NUMBER
X9317ZM8*
PART MARKING
AFG
PACKAGE
8 Ld MSOP
5 ±10%
1
0 to +70
0 to +70
M8.118
X9317ZM8Z* (Note)
X9317ZM8I*
DDA
8 Ld MSOP (Pb-free)
8 Ld MSOP
M8.118
AFI
-40 to +85
-40 to +85
0 to +70
M8.118
X9317ZM8IZ* (Note)
X9317ZP
DCY
8 Ld MSOP (Pb-free)
8 Ld PDIP
M8.118
X9317ZP
X9317Z
X9317Z Z
X9317Z I
X9317Z Z I
9317Z
MDP0031
MDP0027
MDP0027
MDP0027
MDP0027
M8.173
X9317ZS8*
0 to +70
8 Ld SOIC
X9317ZS8Z* (Note)
X9317ZS8I*
0 to +70
8 Ld SOIC (Pb-free)
8 Ld SOIC
-40 to +85
-40 to +85
0 to +70
X9317ZS8IZ* (Note)
X9317ZV8*
8 Ld SOIC (Pb-free)
8 Ld TSSOP
X9317ZV8Z* (Note)
X9317ZV8I*
9317Z Z
317Z I
0 to +70
8 Ld TSSOP (Pb-free) M8.173
8 Ld TSSOP M8.173
8 Ld TSSOP (Pb-free) M8.173
-40 to +85
-40 to +85
0 to +70
X9317ZV8IZ* (Note)
X9317WM8*
9317Z IZ
ABF
10
8 Ld MSOP
M8.118
X9317WM8Z* (Note)
X9317WM8I*
DCW
0 to +70
8 Ld MSOP (Pb-free)
8 Ld MSOP
M8.118
ADS
-40 to +85
-40 to +85
0 to +70
M8.118
X9317WM8IZ* (Note)
X9317WP
DCT
8 Ld MSOP (Pb-free)
8 Ld PDIP
M8.118
X9317WP
X9317WP I
X9317W
X9317W Z
X9317W I
X9317W ZI
9317W
MDP0031
MDP0031
MDP0027
MDP0027
MDP0027
MDP0027
M8.173
X9317WPI
-40 to +85
0 to +70
8 Ld PDIP
X9317WS8*
8 Ld SOIC
X9317WS8Z* (Note)
X9317WS8I*
0 to +70
8 Ld SOIC (Pb-free)
8 Ld SOIC
-40 to +85
-40 to +85
0 to +70
X9317WS8IZ* (Note)
X9317WV8*, **
X9317WV8Z* (Note)
X9317WV8I*
8 Ld SOIC (Pb-free)
8 Ld TSSOP
9317W Z
317W I
0 to +70
8 Ld TSSOP (Pb-free) M8.173
8 Ld TSSOP M8.173
8 Ld TSSOP (Pb-free) M8.173
-40 to +85
-40 to +85
0 to +70
X9317WV8IZ* (Note)
X9317UM8*
9317W IZ
AEC
50
8 Ld MSOP
M8.118
X9317UM8Z* (Note)
X9317UM8I*
DCS
0 to +70
8 Ld MSOP (Pb-free)
8 Ld MSOP
M8.118
AFE
-40 to +85
-40 to +85
0 to +70
M8.118
X9317UM8IZ* (Note)
X9317UP
DCR
8 Ld MSOP (Pb-free)
8 Ld PDIP
M8.118
X9317UP
X9317UP I
X9317U
X9317U Z
X9317U I
X9317U ZI
9317U
MDP0031
MDP0031
MDP0027
MDP0027
MDP0027
MDP0027
M8.173
X9317UPI
-40 to +85
0 to +70
8 Ld PDIP
X9317US8*
8 Ld SOIC
X9317US8Z* (Note)
X9317US8I*
0 to +70
8 Ld SOIC (Pb-free)
8 Ld SOIC
-40 to +85
-40 to +85
0 to +70
X9317US8IZ* (Note)
X9317UV8*
8 Ld SOIC (Pb-free)
8 Ld TSSOP
X9317UV8Z* (Note)
X9317UV8I*
9317U Z
317U I
0 to +70
8 Ld TSSOP (Pb-free) M8.173
8 Ld TSSOP M8.173
8 Ld TSSOP (Pb-free) M8.173
-40 to +85
-40 to +85
X9317UV8IZ* (Note)
9317U IZ
FN8183.4
June 25, 2008
2
X9317
Ordering Information (Continued)
V
LIMITS
(V)
R
TEMPERATURE
RANGE (°C)
PKG.
DWG. #
CC
TOTAL
(kΩ)
PART NUMBER
X9317TM8*, **
PART MARKING
AGD
PACKAGE
8 Ld MSOP
5 ±10%
100
0 to +70
0 to +70
M8.118
X9317TM8Z* (Note)
X9317TM8I*, **
DCN
8 Ld MSOP (Pb-free)
8 Ld MSOP
M8.118
AGF
-40 to +85
-40 to +85
0 to +70
M8.118
X9317TM8IZ* (Note)
X9317TP
DCL
8 Ld MSOP (Pb-free)
8 Ld PDIP
M8.118
X9317TP
X9317TP I
X9317T
X9317T Z
X9317T I
X9317T ZI
9317T
MDP0031
MDP0031
MDP0027
MDP0027
MDP0027
MDP0027
M8.173
X9317TPI
-40 to +85
0 to +70
8 Ld PDIP
X9317TS8
8 Ld SOIC
X9317TS8Z (Note)
X9317TS8I
0 to +70
8 Ld SOIC (Pb-free)
8 Ld SOIC
-40 to +85
-40 to +85
0 to +70
X9317TS8IZ (Note)
X9317TV8*, **
8 Ld SOIC (Pb-free)
8 Ld TSSOP
X9317TV8Z* (Note)
X9317TV8I*, **
9317T Z
317T I
0 to +70
8 Ld TSSOP (Pb-free) M8.173
8 Ld TSSOP M8.173
8 Ld TSSOP (Pb-free) M8.173
-40 to +85
-40 to +85
0 to +70
X9317TV8IZ* (Note)
X9317ZM8-2.7*
9317T IZ
AFH
2.7 to 5.5
1
8 Ld MSOP
M8.118
X9317ZM8Z-2.7* (Note)
X9317ZM8I-2.7*
AOA
0 to +70
8 Ld MSOP (Pb-free)
8 Ld MSOP
M8.118
AFJ
-40 to +85
-40 to +85
0 to +70
M8.118
X9317ZM8IZ-2.7* (Note)
X9317ZS8-2.7*
DCZ
8 Ld MSOP (Pb-free)
8 Ld SOIC
M8.118
X9317Z F
X9317Z ZF
X9317Z G
X9317Z ZG
317Z F
MDP0027
MDP0027
MDP0027
MDP0027
M8.173
X9317ZS8Z-2.7* (Note)
X9317ZS8I-2.7*
0 to +70
8 Ld SOIC (Pb-free)
8 Ld SOIC
-40 to +85
-40 to +85
0 to +70
X9317ZS8IZ-2.7* (Note)
X9317ZV8-2.7*
8 Ld SOIC (Pb-free)
8 Ld TSSOP
X9317ZV8Z-2.7* (Note)
X9317ZV8I-2.7*, **
X9317ZV8IZ-2.7* (Note)
X9317WM8-2.7*
9317Z FZ
317Z G
0 to +70
8 Ld TSSOP (Pb-free) M8.173
8 Ld TSSOP M8.173
8 Ld TSSOP (Pb-free) M8.173
-40 to +85
-40 to +85
0 to +70
9317Z GZ
ACZ
10
8 Ld MSOP
M8.118
X9317WM8Z-2.7* (Note)
X9317WM8I-2.7*
X9317WM8IZ-2.7*
X9317WP-2.7
DCX
0 to +70
8 Ld MSOP (Pb-free)
8 Ld MSOP
M8.118
ADT
-40 to +85
-40 to +85
0 to +70
M8.118
DCU
8 Ld MSOP (Pb-free)
8 Ld PDIP
M8.118
X9317WP F
X9317WP G
X9317W F
X9317W ZF
X9317W G
X9317W ZG
317W F
9317W FZ
317W G
AKZ
MDP0031
MDP0031
MDP0027
MDP0027
MDP0027
MDP0027
M8.173
X9317WPI-2.7
-40 to +85
0 to +70
8 Ld PDIP
X9317WS8-2.7*
8 Ld SOIC
X9317WS8Z-2.7* (Note)
X9317WS8I-2.7*, **
X9317WS8IZ-2.7* (Note)
X9317WV8-2.7*
0 to +70
8 Ld SOIC (Pb-free)
8 Ld SOIC
-40 to +85
-40 to +85
0 to +70
8 Ld SOIC (Pb-free)
8 Ld TSSOP
X9317WV8Z-2.7* (Note)
X9317WV8I-2.7*, **
X9317WV8IZ-2.7* (Note)
0 to +70
8 Ld TSSOP (Pb-free) M8.173
8 Ld TSSOP M8.173
8 Ld TSSOP (Pb-free) M8.173
-40 to +85
-40 to +85
FN8183.4
June 25, 2008
3
X9317
Ordering Information (Continued)
V
LIMITS
(V)
R
TEMPERATURE
RANGE (°C)
PKG.
DWG. #
CC
TOTAL
(kΩ)
PART NUMBER
X9317UM8-2.7*
PART MARKING
AED
PACKAGE
8 Ld MSOP
2.7 to 5.5
10
0 to +70
0 to +70
M8.118
X9317UM8Z-2.7* (Note)
X9317UM8I-2.7*, **
X9317UM8IZ-2.7* (Note)
X9317US8-2.7*
AOB
8 Ld MSOP (Pb-free)
8 Ld MSOP
M8.118
AFF
-40 to +85
-40 to +85
0 to +70
M8.118
AOH
8 Ld MSOP (Pb-free)
8 Ld SOIC
M8.118
X9317U F
X9317UP F
X9317UP G
X9317U ZF
X9317U G
X9317U ZG
317U F
50
MDP0027
MDP0031
MDP0031
MDP0027
MDP0027
MDP0027
M8.173
X9317UP-2.7
0 to +70
8 Ld PDIP
X9317UPI-2.7
-40 to +85
0 to +70
8 Ld PDIP
X9317US8Z-2.7* (Note)
X9317US8I-2.7*, **
X9317US8IZ-2.7* (Note)
X9317UV8-2.7*
8 Ld SOIC (Pb-free)
8 Ld SOIC
-40 to +85
-40 to +85
0 to +70
8 Ld SOIC (Pb-free)
8 Ld TSSOP
X9317UV8Z-2.7* (Note)
X9317UV8I-2.7*, **
X9317UV8IZ-2.7* (Note)
X9317TM8-2.7*, **
X9317TM8Z-2.7* (Note)
X9317TM8I-2.7*, **
X9317TM8IZ-2.7* (Note)
X9317TP-2.7
9317U FZ
317U G
0 to +70
8 Ld TSSOP (Pb-free) M8.173
8 Ld TSSOP M8.173
8 Ld TSSOP (Pb-free) M8.173
-40 to +85
-40 to +85
0 to +70
9317U GZ
AGE
100
8 Ld MSOP
M8.118
DCP
0 to +70
8 Ld MSOP (Pb-free)
8 Ld MSOP
M8.118
AGG
-40 to +85
-40 to +85
0 to +70
M8.118
DCM
8 Ld MSOP (Pb-free)
8 Ld PDIP
M8.118
X9317TP F
X9317TP G
X9317T F
X9317T ZF
X9317T G
X9317T ZG
317T F
MDP0031
MDP0031
MDP0027
MDP0027
MDP0027
MDP0027
M8.173
X9317TPI-2.7
-40 to +85
0 to +70
8 Ld PDIP
X9317TS8-2.7*, **
8 Ld SOIC
X9317TS8Z-2.7* (Note)
X9317TS8I-2.7*, **
X9317TS8IZ-2.7* (Note)
X9317TV8-2.7*, **
0 to +70
8 Ld SOIC (Pb-free)
8 Ld SOIC
-40 to +85
-40 to +85
0 to +70
8 Ld SOIC (Pb-free)
8 Ld TSSOP
X9317TV8Z-2.7* (Note)
X9317TV8I-2.7*, **
X9317TV8IZ-2.7* (Note)
9317T FZ
317T G
0 to +70
8 Ld TSSOP (Pb-free) M8.173
8 Ld TSSOP M8.173
8 Ld TSSOP (Pb-free) M8.173
-40 to +85
-40 to +85
9317T GZ
NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100%
matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
*Add "T1" suffix for tape and reel. Please refer to TB347 for details on reel specifications.
**Add "T2" suffix for tape and reel. Please refer to TB347 for details on reel specifications.
FN8183.4
June 25, 2008
4
X9317
Block Diagram
U/D
INC
CS
R
99
H
UP/DOWN
COUNTER
V
(SUPPLY VOLTAGE)
CC
98
97
96
R
R
UP/DOWN
(U/D)
H
7-BIT
NONVOLATILE
MEMORY
ONE
OF
ONE
CONTROL
AND
MEMORY
INCREMENT
W
(
INC)
WIPER
SWITCHES
RESISTOR
ARRAY
HUNDRED
DECODER
DEVICE SELECT
CS)
(
R
L
2
STORE AND
RECALL
CONTROL
CIRCUITRY
V
(GROUND)
1
0
SS
V
V
CC
SS
GENERAL
R
R
L
W
DETAILED
Pin Descriptions
PDIP/SOIC/MSOP
TSSOP
SYMBOL
INC
BRIEF DESCRIPTION
1
2
3
4
5
6
7
3
4
5
6
7
8
1
Increment. Toggling INC while CS is low moves the wiper either up or down.
Up/Down. The U/D input controls the direction of the wiper movement.
U/D
R
The high terminal is equivalent to one of the fixed terminals of a mechanical potentiometer.
Ground.
H
V
SS
R
The wiper terminal is equivalent to the movable terminal of a mechanical potentiometer.
The low terminal is equivalent to one of the fixed terminals of a mechanical potentiometer.
W
R
L
CS
Chip Select. The device is selected when the CS input is LOW, and de-selected when CS is
high.
8
2
V
Supply Voltage.
CC
FN8183.4
June 25, 2008
5
X9317
Absolute Maximum Ratings
Thermal Information
I
(10s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .±8.8mA
Junction Temperature Under Bias . . . . . . . . . . . . . .-65°C to +135°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
W
R , R , R to Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+6V
Voltage on CS, INC, U/D and V
H
W
L
CC
with Respect to V . . . . . . . . . . . . . . . . . . . . . . . . . . . -1V to +7V
SS
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
Potentiometer Specifications
V
= Full Range, T = Full Operating Temperature Range, unless otherwise stated.
CC A
MIN
TYP
MAX
SYMBOL
PARAMETER
TEST CONDITIONS/NOTES
(Note 8) (Note 4) (Note 8)
UNIT
R
End-to-end Resistance Tolerance
See “Ordering Information” beginning
on page 2 for values
-20 +20
%
TOTAL
V
/
R /R Terminal Voltage
V
= 0V
V
V
CC
V
mW
mW
Ω
RH RL
H
L
SS
SS
Power Rating
R
≥ 10kΩ
10
25
TOTAL
TOTAL
R
= 1kΩ
R
Wiper Resistance
I
I
= 1mA, V
= 1mA, V
= 5V
200
400
400
1000
+4.4
W
W
W
CC
CC
= 2.7V
Ω
I
Wiper Current (Note 5)
Noise (Note 7)
See “Test Circuit” on page 7
Ref: 1kHz
-4.4
mA
dBV
%
W
-120
1
Resolution
Absolute Linearity (Note 1)
V(R ) = V , V(R ) = 0V
CC
-1
+1
MI
H
L
(Note 3)
Relative Linearity (Note 2)
V(R ) = V , V(R ) = 0V
CC
-0.2
+0.2
MI
H
L
(Note 3)
R
Temperature Coefficient (Note 5)
V(R ) = V , V(R ) = 0V
CC
±300
ppm/°C
ppm/°C
TOTAL
H
L
Ratiometric Temperature Coefficient
(Notes 5, 6)
V(R ) = V , V(R ) = 0V
CC
-20
+20
H
L
C /C /C
W
Potentiometer Capacitances
See “Equivalent Circuit” on page 7
10/10/25
pF
H
L
(Note 5)
V
Supply Voltage
X9317
4.5
2.7
5.5
5.5
V
V
CC
X9317-2.7
DC Electrical Specifications
V
= 5V ±10%, T = Full Operating Temperature Range, unless otherwise stated.
CC A
MIN
TYP
MAX
SYMBOL
PARAMETER
TEST CONDITIONS
(Note 8) (Note 4) (Note 8) UNIT
I
V
V
Active Current (Increment)
CS = V , U/D = V or V and
50
µA
CC1
CC
IL
IL
IH
INC = V /V @ min. t
IL IH
CYC
R , R , R not connected
L
H
W
I
Active Current (Store)
CS = V , U/D = V or V and INC = V
IH IL IH
400
1
µA
µA
CC2
CC
IL
(non-volatile write)
or V . R , R , R not connected
IH
L
H
W
I
Standby Supply Current
CS ≥ V , U/D and INC = V
IH
SB
IL
R , R , R not connected
L
H
W
I
CS, INC, U/D Input Leakage Current
CS, INC, U/D Input HIGH Voltage
CS, INC, U/D Input LOW Voltage
V
= V to V
SS CC
-10
+10
µA
V
LI
IN
V
V
x 0.7
V
+ 0.5
CC
IH
CC
V
-0.5
V
x 0.1
V
IL
CC
C
(Note 5) CS, INC, U/D Input Capacitance
V
= 5V, V = V , T = +25°C,
IN SS
10
pF
IN
CC
A
f = 1MHz
FN8183.4
June 25, 2008
6
X9317
Endurance and Data Retention V = 5V ±10%, T = Full Operating Temperature Range.
CC
A
PARAMETER
Minimum Endurance
Data Retention
MIN
100,000
100
UNIT
Data changes per bit
Years
NOTES:
1. Absolute linearity is utilized to determine actual wiper voltage versus expected voltage = [V(R
)-V(R
)]/MI
W(n)(actual)
) - MI)]/MI.
W(n)(expected)
V(R
) = n(V(R )-V(R ))/99 + V(R ), with n from 0 to 99.
W(n)(expected)
H L L
2. Relative linearity is a measure of the error in step size between taps = [V(R
)-(V(R
W(n)
W(n+1)
3. 1 Ml = Minimum Increment = [V(R )-V(R )]/99.
H
L
4. Typical values are for T = +25°C and nominal supply voltage.
A
5. This parameter is not 100% tested.
6
6. Ratiometric temperature coefficient = (V(R
to 99.
)
-V(R
)
)/[V(R (T1-T2) x 10 ], with T1 and T2 being 2 temperatures, and n from 0
)
W T1(n)
W T2(n)
W T1(n)
7. Measured with wiper at tap position 99, R grounded, using test circuit.
L
8. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
Test Circuit
Equivalent Circuit
AC Conditions of Test
Input pulse levels
0V to 3V
10ns
R
TOTAL
TEST POINT
R
Input rise and fall times
Input reference levels
R
L
H
C
L
C
W
C
1.5V
H
10pF
R
W
FORCE
CURRENT
25pF
10pF
R
W
AC Electrical Specifications
V
= 5V ±10%, T = Full Operating Temperature Range, unless otherwise stated.
CC A
MIN
TYP
MAX
SYMBOL
PARAMETER
(Note 8)
(Note 4)
(Note 8)
UNIT
ns
t
CS to INC Setup
50
100
1
Cl
t
(Note 5)
(Note 5)
INC HIGH to U/D Change
U/D to INC Setup
ns
lD
t
µs
DI
t
INC LOW Period
960
960
1
ns
lL
t
t
INC HIGH Period
ns
lH
lC
INC Inactive to CS Inactive
CS Deselect Time (STORE)
CS Deselect Time (NO STORE)
µs
t
10
ms
ns
CPHS
t
100
CPHNS
(Note 5)
t
INC to R Change
W
1
5
µs
µs
µs
IW
t
INC Cycle Time
2
CYC
t
t
INC Input Rise and Fall Time
500
R, F
(Note 5)
t
(Note 5)
Power-up to Wiper Stable
5
µs
PU
t
V
V Power-up Rate
CC
0.2
50
V/ms
R
CC
(Note 5)
t
Store Cycle
5
10
ms
WR
FN8183.4
June 25, 2008
7
X9317
1ms after V
CC
reaches its final value. The V ramp spec is
CC
Power-up and Down Requirements
The recommended power-up sequence is to apply V /V
first, then the potentiometer voltages. During power-up, the
data sheet parameters for the DCP do not fully apply until
always in effect. In order to prevent unwanted tap position
changes, or an inadvertent store, bring the CS and INC high
before or concurrently with the V
CC
CC SS
pin on power-up.
AC Timing
CS
t
CYC
t
CPHNS
t
t
t
t
t
CPHS
CI
IL
IH
IC
90%
10%
90%
INC
U/D
t
t
t
t
R
ID
DI
F
t
IW
(3)
MI
R
W
Typical Performance Characteristic
0
-50
-100
-150
-200
-250
-300
-350
-55-45-35-25-15 -5
5
15 25 35 45 55 65 75 85 95 105115125
TEMPERATURE (°C)
FIGURE 1. TYPICAL TOTAL RESISTANCE TEMPERATURE COEFFICIENT
FN8183.4
June 25, 2008
8
X9317
Pin Descriptions
Pin Names
R
AND R
L
SYMBOL
DESCRIPTION
H
The high (R ) and low (R ) terminals of the X9317 are
H
L
R
High terminal
Wiper terminal
Low terminal
Ground
H
equivalent to the fixed terminals of a mechanical
potentiometer. The terminology of R and R references the
R
W
L
H
R
relative position of the terminal in relation to wiper movement
direction selected by the U/D input and not the voltage
potential on the terminal.
L
V
SS
CC
V
Supply voltage
RW
U/D
INC
CS
Up/Down control input
Increment control input
Chip select control input
R
is the wiper terminal and is equivalent to the movable
w
terminal of a mechanical potentiometer. The position of the
wiper within the array is determined by the control inputs.
The wiper terminal series resistance is typically 200Ω.
Principles of Operation
UP/DOWN (U/D)
There are three sections of the X9317: the control section,
the nonvolatile memory, and the resistor array. The control
section operates just like an up/down counter. The output of
this counter is decoded to turn on a single electronic switch
connecting a point on the resistor array to the wiper output.
The contents of the counter can be stored in nonvolatile
memory and retained for future use. The resistor array is
comprised of 99 individual resistors connected in series.
Electronic switches at either end of the array and between
each resistor provide an electrical connection to the wiper
The U/D input controls the direction of the wiper movement
and whether the counter is incremented or decremented.
INCREMENT (INC)
The INC input is negative-edge triggered. Toggling INC will
move the wiper and either increment or decrement the
counter in the direction indicated by the logic level on the
U/D input.
CHIP SELECT (CS)
pin, R .
W
The device is selected when the CS input is LOW. The
current counter value is stored in nonvolatile memory when
CS is returned HIGH while the INC input is also HIGH. After
the store operation is complete, the X9317 will be placed in
the low power standby mode until the device is selected
once again.
The wiper acts like its mechanical equivalent and does not
move beyond the first or last position. That is, the counter
does not wrap around when clocked to either extreme.
The electronic switches on the device operate in a “make
before break” mode when the wiper changes tap positions. If
the wiper is moved several positions, multiple taps are
Pin Configuration
connected to the wiper for t (INC to V change). The
IW
W
DIP/SOIC/MSOP
R
value for the device can temporarily be reduced by
TOTAL
a significant amount if the wiper is moved several positions.
V
INC
U/D
1
2
3
4
8
7
6
5
CC
CS
When the device is powered-down, the last wiper position
stored will be maintained in the nonvolatile memory. When
power is restored, the contents of the memory are recalled
and the wiper is set to the value last stored.
X9317
R
L
R
H
V
R
SS
W
Instructions and Programming
TSSOP
The INC, U/D and CS inputs control the movement of the
wiper along the resistor array. With CS set LOW, the device
is selected and enabled to respond to the U/D and INC
inputs. HIGH to LOW transitions on INC will increment or
decrement (depending on the state of the U/D input) a 7-bit
counter. The output of this counter is decoded to select one
of one hundred wiper positions along the resistive array.
R
CS
1
2
3
4
8
7
6
5
L
V
R
V
CC
W
X9317
INC
U/D
SS
R
H
The value of the counter is stored in nonvolatile memory
whenever CS transitions HIGH while the INC input is also
HIGH.
FN8183.4
June 25, 2008
9
X9317
The system may select the X9317, move the wiper and
deselect the device without having to store the latest wiper
position in nonvolatile memory. After the wiper movement is
performed as previously described and once the new
position is reached, the system must keep INC LOW while
taking CS HIGH. The new wiper position will be maintained
until changed by the system or until a power-up/down cycle
recalls the previously stored data.
Mode Selection
CS
INC
U/D
MODE
L
H
Wiper up
L
L
Wiper down
H
X
Store wiper position to nonvolatile
memory
H
X
L
L
L
X
X
H
L
Standby
This procedure allows the system to always power-up to a
preset value stored in nonvolatile memory; then during
system operation minor adjustments could be made. The
adjustments might be based on user preference, system
parameter changes due to temperature drift, etc.
No store, return to standby
Wiper Up (not recommended)
Wiper Down (not recommended)
The state of U/D may be changed while CS remains LOW.
This allows the host system to enable the device and then
move the wiper up and down until the proper trim is attained.
Applications Information
Electronic digitally controlled (XDCP) potentiometers provide
three powerful application advantages:
1. the variability and reliability of a solid-state potentiometer,
2. the flexibility of computer-based digital controls, and
3. the retentivity of nonvolatile memory used for the storage
of multiple potentiometer settings or data.
FN8183.4
June 25, 2008
10
X9317
Basic Configurations of Electronic Potentiometers
V
V
REF
REF
R
H
R
W
R
L
I
THREE TERMINAL POTENTIOMETER;
VARIABLE VOLTAGE DIVIDER
TWO TERMINAL VARIABLE RESISTOR;
VARIABLE CURRENT
Basic Circuits
SINGLE SUPPLY INVERTING AMPLIFIER
BUFFERED REFERENCE VOLTAGE
CASCADING TECHNIQUES
R
1
+V
+V
+5V
+V
R
R
2
1
+5V
V
S
R
LMC7101
V
W
+
-
V
REF
X
OUT
R
W
-
100k
V
O
+V
+
+5V
LMC7101
100k
R
V
= V /R
W W
W
OUT
(a)
(b)
V = (R2/R1)V
O S
VOLTAGE REGULATOR
317
OFFSET VOLTAGE ADJUSTMENT
COMPARATOR WITH HYSTERESIS
LT311A
R
R
2
1
V
V
(REG)
O
IN
V
V
-
S
S
V
O
+5V
R
1
100kΩ
+
-
V
O
+
I
adj
R
2
LMC7101
10kΩ
10kΩ
R
R
2
1
10kΩ
V
V
= {R /(R +R )} V (max)
1 1 2 O
UL
LL
V
(REG) = 1.25V (1+R /R )+I
R
adj 2
= {R /(R +R )} V (min)
O
2
1
1 1 2 O
+5V
FN8183.4
June 25, 2008
11
X9317
Mini Small Outline Plastic Packages (MSOP)
N
M8.118 (JEDEC MO-187AA)
8 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE
INCHES
MILLIMETERS
E1
E
SYMBOL
MIN
MAX
MIN
0.94
0.05
0.75
0.25
0.09
2.95
2.95
MAX
1.10
0.15
0.95
0.36
0.20
3.05
3.05
NOTES
A
A1
A2
b
0.037
0.002
0.030
0.010
0.004
0.116
0.116
0.043
0.006
0.037
0.014
0.008
0.120
0.120
-
-B-
0.20 (0.008)
INDEX
AREA
1 2
A
B
C
-
-
TOP VIEW
4X θ
9
0.25
(0.010)
R1
c
-
R
GAUGE
PLANE
D
3
E1
e
4
SEATING
PLANE
L
0.026 BSC
0.65 BSC
-
-C-
4X θ
L1
A
A2
E
0.187
0.016
0.199
0.028
4.75
0.40
5.05
0.70
-
L
6
SEATING
PLANE
L1
N
0.037 REF
0.95 REF
-
0.10 (0.004)
-A-
C
C
b
8
8
7
-H-
A1
e
R
0.003
0.003
-
-
0.07
0.07
-
-
-
D
0.20 (0.008)
C
R1
0
-
o
o
o
o
5
15
5
15
-
a
SIDE VIEW
C
L
o
o
o
o
0
6
0
6
-
α
E
1
-B-
Rev. 2 01/03
0.20 (0.008)
C
D
END VIEW
NOTES:
1. These package dimensions are within allowable dimensions of
JEDEC MO-187BA.
2. Dimensioning and tolerancing per ANSI Y14.5M-1994.
3. Dimension “D” does not include mold flash, protrusions or gate
burrs and are measured at Datum Plane. Mold flash, protrusion
and gate burrs shall not exceed 0.15mm (0.006 inch) per side.
4. Dimension “E1” does not include interlead flash or protrusions
- H -
and are measured at Datum Plane.
Interlead flash and
protrusions shall not exceed 0.15mm (0.006 inch) per side.
5. Formed leads shall be planar with respect to one another within
0.10mm (0.004) at seating Plane.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “b” does not include dambar protrusion. Allowable
dambar protrusion shall be 0.08mm (0.003 inch) total in excess
of “b” dimension at maximum material condition. Minimum space
between protrusion and adjacent lead is 0.07mm (0.0027 inch).
- B -
to be determined at Datum plane
-A -
10. Datums
and
.
- H -
11. Controlling dimension: MILLIMETER. Converted inch dimen-
sions are for reference only.
FN8183.4
June 25, 2008
12
X9317
Thin Shrink Small Outline Plastic Packages (TSSOP)
N
M8.173
INDEX
AREA
0.25(0.010)
M
B M
E
8 LEAD THIN SHRINK NARROW BODY SMALL OUTLINE
PLASTIC PACKAGE
E1
-B-
GAUGE
PLANE
INCHES
MIN
MILLIMETERS
SYMBOL
MAX
0.047
0.006
0.051
0.0118
0.0079
0.120
0.177
MIN
-
MAX
1.20
0.15
1.05
0.30
0.20
3.05
4.50
NOTES
1
2
3
A
A1
A2
b
-
-
L
0.002
0.031
0.0075
0.0035
0.116
0.169
0.05
0.80
0.19
0.09
2.95
4.30
-
0.25
0.010
0.05(0.002)
SEATING PLANE
A
-
-A-
D
9
c
-
-C-
α
D
3
A2
e
A1
E1
e
4
c
b
0.10(0.004)
0.026 BSC
0.65 BSC
-
0.10(0.004) M
C
A M B S
E
0.246
0.256
6.25
0.45
6.50
0.75
-
L
0.0177
0.0295
6
NOTES:
N
8
8
7
1. These package dimensions are within allowable dimensions of
JEDEC MO-153-AC, Issue E.
o
o
o
o
0
8
0
8
-
α
Rev. 1 12/00
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm
(0.006 inch) per side.
4. Dimension “E1” does not include interlead flash or protrusions. Inter-
lead flash and protrusions shall not exceed 0.15mm (0.006 inch) per
side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “b” does not include dambar protrusion. Allowable dambar
protrusion shall be 0.08mm (0.003 inch) total in excess of “b” dimen-
sion at maximum material condition. Minimum space between protru-
sion and adjacent lead is 0.07mm (0.0027 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact. (Angles in degrees)
FN8183.4
June 25, 2008
13
X9317
Small Outline Package Family (SO)
A
D
h X 45°
(N/2)+1
N
A
PIN #1
I.D. MARK
E1
E
c
SEE DETAIL “X”
1
(N/2)
B
L1
0.010 M
C A B
e
H
C
A2
A1
GAUGE
PLANE
SEATING
PLANE
0.010
L
4° ±4°
0.004 C
b
0.010 M
C
A
B
DETAIL X
MDP0027
SMALL OUTLINE PACKAGE FAMILY (SO)
INCHES
SO16
(0.150”)
SO16 (0.300”)
(SOL-16)
SO20
SO24
(SOL-24)
SO28
(SOL-28)
SYMBOL
SO-8
0.068
0.006
0.057
0.017
0.009
0.193
0.236
0.154
0.050
0.025
0.041
0.013
8
SO-14
0.068
0.006
0.057
0.017
0.009
0.341
0.236
0.154
0.050
0.025
0.041
0.013
14
(SOL-20)
0.104
0.007
0.092
0.017
0.011
0.504
0.406
0.295
0.050
0.030
0.056
0.020
20
TOLERANCE
MAX
NOTES
A
A1
A2
b
0.068
0.006
0.057
0.017
0.009
0.390
0.236
0.154
0.050
0.025
0.041
0.013
16
0.104
0.007
0.092
0.017
0.011
0.406
0.406
0.295
0.050
0.030
0.056
0.020
16
0.104
0.007
0.092
0.017
0.011
0.606
0.406
0.295
0.050
0.030
0.056
0.020
24
0.104
0.007
0.092
0.017
0.011
0.704
0.406
0.295
0.050
0.030
0.056
0.020
28
-
±0.003
±0.002
±0.003
±0.001
±0.004
±0.008
±0.004
Basic
-
-
-
c
-
D
1, 3
E
-
E1
e
2, 3
-
L
±0.009
Basic
-
L1
h
-
Reference
Reference
-
N
-
Rev. M 2/07
NOTES:
1. Plastic or metal protrusions of 0.006” maximum per side are not included.
2. Plastic interlead protrusions of 0.010” maximum per side are not included.
3. Dimensions “D” and “E1” are measured at Datum Plane “H”.
4. Dimensioning and tolerancing per ASME Y14.5M-1994
FN8183.4
June 25, 2008
14
X9317
Plastic Dual-In-Line Packages (PDIP)
E
N
1
D
PIN #1
INDEX
A2
A
E1
SEATING
PLANE
L
c
A1
NOTE 5
2
N/2
eA
eB
e
b
b2
MDP0031
PLASTIC DUAL-IN-LINE PACKAGE
INCHES
SYMBOL
PDIP8
0.210
0.015
0.130
0.018
0.060
0.010
0.375
0.310
0.250
0.100
0.300
0.345
0.125
8
PDIP14
0.210
0.015
0.130
0.018
0.060
0.010
0.750
0.310
0.250
0.100
0.300
0.345
0.125
14
PDIP16
0.210
0.015
0.130
0.018
0.060
0.010
0.750
0.310
0.250
0.100
0.300
0.345
0.125
16
PDIP18
PDIP20
0.210
0.015
0.130
0.018
0.060
0.010
1.020
0.310
0.250
0.100
0.300
0.345
0.125
20
TOLERANCE
MAX
NOTES
A
A1
A2
b
0.210
0.015
0.130
0.018
0.060
0.010
0.890
0.310
0.250
0.100
0.300
0.345
0.125
18
MIN
±0.005
±0.002
b2
c
+0.010/-0.015
+0.004/-0.002
±0.010
D
1
2
E
+0.015/-0.010
±0.005
E1
e
Basic
eA
eB
L
Basic
±0.025
±0.010
N
Reference
Rev. C 2/07
NOTES:
1. Plastic or metal protrusions of 0.010” maximum per side are not included.
2. Plastic interlead protrusions of 0.010” maximum per side are not included.
3. Dimensions E and eA are measured with the leads constrained perpendicular to the seating plane.
4. Dimension eB is measured with the lead tips unconstrained.
5. 8 and 16 lead packages have half end-leads as shown.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN8183.4
June 25, 2008
15
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