X9400YB24IT1 [RENESAS]
Digital Potentiometer, 4 Func, 2500ohm, 3-wire Serial Control Interface, 64 Positions, CMOS, BUMP, CSP-24;
| 型号： | X9400YB24IT1 |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | Digital Potentiometer, 4 Func, 2500ohm, 3-wire Serial Control Interface, 64 Positions, CMOS, BUMP, CSP-24 |
| 文件： | 总22页 (文件大小：555K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
APPLICATION NOTES
A V A I L A B L E
AN99 • AN115 • AN120 • AN124 • AN133 • AN134 • AN135
Low Noise/Low Power/SPI Bus
X9400
Quad Digitally Controlled Potentiometers (XDCP™)
FEATURES
DESCRIPTION
• Four potentiometers per package
• 64 resistor taps
The X9400 integrates four digitally controlled
potentiometers (XDCPs) on a monolithic CMOS
integrated circuit.
• SPI serial interface for write, read, and transfer
operations of the potentiometer
• Wiper resistance, 40Ω typical at 5V.
• Four non-volatile data registers for each
potentiometer
• Non-volatile storage of multiple wiper position
• Power on recall. Loads saved wiper position on
power up.
The digitally controlled potentiometer is implemented
using 63 resistive elements in a series array. Between
each element are tap points connected to the wiper
terminal through switches. The position of the wiper on
the array is controlled by the user through the SPI
serial bus interface. Each potentiometer has
associated with it a volatile Wiper Counter Register
(WCR) and four nonvolatile Data Registers (DR0-3)
that can be directly written to and read by the user.
The contents of the WCR controls the position of the
wiper on the resistor array through the switches.
Power up recalls the contents of DR0 to the WCR.
• Standby current < 1µA max
• System V : 2.7V to 5.5V operation
CC
• Analog V+/V–: -5V to +5V
• 10KΩ, 2.5KΩ End to end resistance
• 100 yr. data retention
• Endurance: 100,000 data changes per bit per
register
• Low power CMOS
The XDCP can be used as a three-terminal
potentiometer or as a two-terminal variable resistor in
a wide variety of applications including control,
parameter adjustments, and signal processing.
• 24-lead SOIC, 24-lead TSSOP, and 24-lead CSP
(Chip Scale Package) packages
BLOCK DIAGRAM
V
V
CC
SS
Pot 0
R0 R1
R2 R3
V
/R
R0 R1
R2 R3
H0 H0
V+
V-
Wiper
Counter
Register
(WCR)
Wiper
Counter
Register
(WCR)
V
/R
H2 H2
Resistor
Array
Pot 2
V
/R
L0 L0
HOLD
V
/R
L2 L2
CS
SCK
SO
SI
V
/R
W0 W0
V
/R
W2 W2
Interface
and
Control
8
Circuitry
A0
A1
V
/R
W1 W1
Data
V
V
/R
W3 W3
WP
R0 R1
R2 R3
R0 R1
R2 R3
V
/R
Wiper
Counter
Register
(WCR)
H1 H1
/R
Resistor
Array
Pot 1
Wiper
Counter
Register
(WCR)
H3 H3
Resistor
Array
Pot 3
V
/R
L1 L1
V
/R
L3 L3
Characteristics subject to change without notice. 1 of 22
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X9400
PIN DESCRIPTIONS
Host Interface Pins
Serial Output (SO)
resetting the serial sequence. To pause, HOLD must
be brought LOW while SCK is LOW. To resume
communication, HOLD is brought HIGH, again while
SCK is LOW. If the pause feature is not used, HOLD
should be held HIGH at all times.
SO is a push/pull serial data output pin. During a read
cycle, data is shifted out on this pin. Data is clocked
out by the falling edge of the serial clock.
Device Address (A –A )
0
1
The address inputs are used to set the least significant
2 bits of the 8-bit slave address. A match in the slave
address serial data stream must be made with the
address input in order to initiate communication with
the X9400. A maximum of 4 devices may occupy the
SPI serial bus.
Serial Input
SI is the serial data input pin. All opcodes, byte
addresses and data to be written to the pots and pot
registers are input on this pin. Data is latched by the
rising edge of the serial clock.
Potentiometer Pins
Serial Clock (SCK)
The SCK input is used to clock data into and out of the
X9400.
V /R (V /R –V /R ), V /R (V /R –V /R )
H H H0 H0 H3 H3 L L L0 L0 L3 L3
The V /R and V /R inputs are equivalent to the
H
H
L
L
terminal connections on either end of a mechanical
potentiometer.
Chip Select (CS)
When CS is HIGH, the X9400 is deselected and the
SO pin is at high impedance, and (unless an internal
write cycle is underway) the device will be in the
standby state. CS LOW enables the X9400, placing it
in the active power mode. It should be noted that after
a power-up, a HIGH to LOW transition on CS is
required prior to the start of any operation.
V /R (V /R –V /R )
W0 W0 W3 W3
The wiper outputs are equivalent to the wiper output of
a mechanical potentiometer.
W
W
Hardware Write Protect Input (WP)
The WP pin when LOW prevents nonvolatile writes to
the Data Registers.
Hold (HOLD)
HOLD is used in conjunction with the CS pin to select
the device. Once the part is selected and a serial
sequence is underway, HOLD may be used to pause
the serial communication with the controller without
Analog Supplies (V+, V-)
The analog Supplies V+, V- are the supply voltages for
the XDCP analog section.
PIN CONFIGURATION
SOIC
CSP
TSSOP
1
2
3
4
V+
V
V
WP
SI
1
2
24
23
22
21
20
19
18
17
16
15
1
2
24
23
22
21
20
19
18
17
16
15
CC
/R
V
/R
CS
V
A
L3 L3
L0 L0
1
V
/R
V
V
/R
A
CS
W0 W0
L1 L1
1
A
B
C
D
E
F
/R
V
V
A
/R
V
/R
3
V
/R
W0 W0
H3 H3
3
H0 H0
L1 L1
V /R
H1 H1
V
/R
/R
V
V
V
/R
/R
SI
WP
V
/R
L0 L0
W1 W1
4
H0 H0
W3 W3
4
W0 W0
CS
V
/R
W1 W1
/R
5
5
L0 L0
0
V
V
V
/R
V
V
/R
V
SS
CC
H0 H0
H1 H1
V
SO
SS
WP
6
6
CC
X9400
X9400
SI
V-
HOLD
SCK
7
V+
V
/R
/R
7
V+
V-
H3 H3 H2 H2
V
/R
A
1
/R
W2 W2
8
8
L3 L3
HOLD V /R
W2 W2
V
/R
SO
L3 L3
V
V
/R
V
/R
H2 H2
V
/R
9
V
V
/R
9
L2 L2
L1 L1
H3 H3
V
/R
/R
/R
10
L2 L2
H2 H2
10
V
/R
W3 W3
H1 H1
V
/R
A
SCK
V /R
L2 L2
W3 W3
0
V
/R
A
14
13
SCK
14
13
V
/R
W2 W2
11
12
0
11
12
W1 W1
V
HOLD
Top View–Bumps Down
V-
SS
SO
Characteristics subject to change without notice. 2 of 22
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X9400
PIN NAMES
These switches are controlled by a wiper counter
register (WCR). The six bits of the WCR are decoded
to select, and enable, one of sixty-four switches.
Symbol
Description
Serial Clock
SCK
Wiper Counter Register (WCR)
SI, SO
Serial Data
The X9400 contains four Wiper Counter Registers,
one for each XDCP potentiometer. The WCR is
equivalent to a serial-in, parallel-out register/counter
with its outputs decoded to select one of sixty-four
switches along its resistor array. The contents of the
WCR can be altered in four ways: it may be written
directly by the host via the write Wiper Counter
Register instruction (serial load); it may be written
indirectly by transferring the contents of one of four
associated data registers via the XFR Data Register or
global XFR data register instructions (parallel load); it
can be modified one step at a time by the increment/
decrement instruction. Finally, it is loaded with the
contents of its Data Register zero (DR0) upon power-
up.
A -A
Device Address
0
1
V
V
/R –V /R
,
Potentiometer Pins (terminal
equivalent)
H0 H0 H3 H3
/R –V /R
L0 L0 L3 L3
V
/R –V /R
Potentiometer Pins (wiper
equivalent)
W0 W0 W1 W1
WP
Hardware Write Protection
System Supply Voltage
System Ground
V
V
CC
SS
NC
No Connection
DEVICE DESCRIPTION
The X9400 is
a
highly integrated microcircuit
incorporating four resistor arrays and their associated
registers and counters and the serial interface logic
providing direct communication between the host and
the XDCP potentiometers.
The Wiper Counter Register is a volatile register; that
is, its contents are lost when the X9400 is powered-
down. Although the register is automatically loaded
with the value in DR0 upon power-up, this may be
different from the value present at power-down.
Serial Interface
The X9400 supports the SPI interface hardware
conventions. The device is accessed via the SI input
with data clocked in on the rising SCK. CS must be
LOW and the HOLD and WP pins must be HIGH
during the entire operation.
Data Registers
Each potentiometer has four 6-bit nonvolatile Data
Registers. These can be read or written directly by the
host. Data can also be transferred between any of the
four Data Registers and the associated Wiper Counter
Register. All operations changing data in one of the
data registers is a nonvolatile operation and will take a
maximum of 10ms.
The SO and SI pins can be connected together, since
they have three state outputs. This can help to reduce
system pin count.
Array Description
If the application does not require storage of multiple
settings for the potentiometer, the Data Registers can
be used as regular memory locations for system
parameters or user preference data.
The X9400 is comprised of four resistor arrays. Each
array contains 63 discrete resistive segments that are
connected in series. The physical ends of each array
are equivalent to the fixed terminals of a mechanical
Data Register Detail
potentiometer (V /R and V /R inputs).
H
H
L
L
(MSB)
D5
(LSB)
D0
At both ends of each array and between each resistor
segment is a CMOS switch connected to the wiper
D4
NV
D3
NV
D2
NV
D1
NV
(V /R ) output. Within each individual array only one
W
W
NV
NV
switch may be turned on at a time.
Characteristics subject to change without notice. 3 of 22
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X9400
Figure 1. Detailed Potentiometer Block Diagram
(One of Four Arrays)
Serial Data Path
Serial
Bus
Input
V /R
H H
From Interface
Circuitry
C
o
u
n
t
Register 0
Register 2
Register 1
8
6
Parallel
Bus
Input
e
r
Wiper
D
e
c
o
d
e
Register 3
Counter
Register
(WCR)
INC/DEC
Logic
If WCR = 00[H] then V /R = V /R
W
W
L
L
UP/DN
UP/DN
If WCR = 3F[H] then V /R = V /R
H
W
W
H
V /R
Modified SCL
L
L
CLK
V
/R
W
W
Write in Process
required for the X9400 to successfully continue the
command sequence. The A –A inputs can be actively
0
1
The contents of the Data Registers are saved to
nonvolatile memory when the CS pin goes from LOW
to HIGH after a complete write sequence is received by
the device. The progress of this internal write operation
can be monitored by a write in process bit (WIP). The
WIP bit is read with a read status command.
driven by CMOS input signals or tied to V or V
.
CC
SS
The remaining two bits in the slave byte must be set to 0.
Figure 2. Identification Byte Format
Device Type
Identifier
INSTRUCTIONS
Identification (ID) Byte
0
1
0
1
0
0
A1
A0
The first byte sent to the X9400 from the host, following
a CS going HIGH to LOW, is called the Identification
byte. The most significant four bits of the slave address
are a device type identifier, for the X9400 this is fixed
as 0101[B] (refer to Figure 2).
Device Address
Instruction Byte
The next byte sent to the X9400 contains the
instruction and register pointer information. The four
most significant bits are the instruction. The next four
bits point to one of the four pots and, when applicable,
they point to one of four associated registers. The
format is shown below in Figure 3.
The two least significant bits in the ID byte select one of
four devices on the bus. The physical device address is
defined by the state of the A -A input pins. The X9400
0
1
compares the serial data stream with the address input
state; a successful compare of both address bits is
Characteristics subject to change without notice. 4 of 22
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X9400
Figure 3. Instruction Byte Format
t
to complete.The transfer can occur between one of
WR
the four potentiometers and one of its associated
registers; or it may occur globally, where the transfer
occurs between all potentiometers and one associated
register.
Register
Select
I3
I2
I1
I0
R1 R0
P1
P0
Five instructions require a three-byte sequence to
complete. These instructions transfer data between the
host and the X9400; either between the host and one of
the data registers or directly between the host and the
Wiper Counter Register.These instructions are:
Pot Select
Instructions
The four high order bits of the instruction byte specify
the operation. The next two bits (R and R ) select one
1
0
– Read Wiper Counter Register—read the current
wiper position of the selected pot,
of the four registers that is to be acted upon when a
register oriented instruction is issued. The last two bits
(P1 and P ) selects which one of the four
potentiometers is to be affected by the instruction.
– Write Wiper Counter Register—change current wiper
position of the selected pot,
0
– Read Data Register—read the contents of the
selected data register;
Four of the ten instructions are two bytes in length and
end with the transmission of the instruction byte. These
instructions are:
– Write Data Register—write a new value to the
selected data register.
– XFR Data Register to Wiper Counter Register—This
transfers the contents of one specified Data Register
to the associated Wiper Counter Register.
– Read Status—This command returns the contents of
the WIP bit which indicates if the internal write cycle
is in progress.
– XFR Wiper Counter Register to Data Register —This
transfers the contents of the specified Wiper Counter
Register to the specified associated Data Register.
The sequence of these operations is shown in Figure 5
and Figure 6.
– Global XFR Data Register to Wiper Counter Register —
This transfers the contents of all specified Data
Registers to the associated Wiper Counter Registers.
The final command is Increment/Decrement. It is
different from the other commands, because it’s length is
indeterminate. Once the command is issued, the master
can clock the selected wiper up and/or down in one
resistor segment steps; thereby, providing a fine tuning
– Global XFR Wiper Counter Register to Data Register —
This transfers the contents of all Wiper Counter
Registers to the specified associated Data Registers.
capability to the host. For each SCK clock pulse (t
)
HIGH
while SI is HIGH, the selected wiper will move one
resistor segment towards the V /R terminal. Similarly,
The basic sequence of the two byte instructions is
illustrated in Figure 4. These two-byte instructions
exchange data between the WCR and one of the data
registers. A transfer from a Data Register to a WCR is
essentially a write to a static RAM, with the static RAM
controlling the wiper position.The response of the wiper
H
H
for each SCK clock pulse while SI is LOW, the selected
wiper will move one resistor segment towards the V /R
L
L
terminal. A detailed illustration of the sequence and
timing for this operation are shown in Figure 7 and Figure
8.
to this action will be delayed by t
. A transfer from
WRL
the WCR (current wiper position), to a data register is a
write to nonvolatile memory and takes a minimum of
Characteristics subject to change without notice. 5 of 22
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X9400
Figure 4. Two-Byte Instruction Sequence
CS
SCK
SI
0
1
0
1
0
0
A1 A0
I3 I2
I1 I0 R1 R0 P1 P0
Figure 5. Three-Byte Instruction Sequence (Write)
CS
SCK
SI
0
0
0
1
0
1
A1 A0
I3 I2
I1 I0 R1 R0 P1 P0
0
0
D5 D4 D3 D2 D1 D0
Figure 6. Three-Byte Instruction Sequence (Read)
CS
SCK
SI
Don’t Care
0
0
0
1
0
1
A1 A0
I3 I2
I1 I0 R1 R0 P1 P0
S0
0
0
D5 D4 D3 D2 D1 D0
Figure 7. Increment/Decrement Instruction Sequence
CS
SCK
SI
P1
0
1
0
1
0
0
A1 A0
I3 I2
I1 I0
0
0
P0
I
I
D
E
C
1
I
D
E
C
n
N
C
1
N
C
2
N
C
n
Characteristics subject to change without notice. 6 of 22
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X9400
Figure 8. Increment/Decrement Timing Limits
t
WRID
SCK
SI
Voltage Out
V
/R
W
W
INC/DEC CMD Issued
Table 1. Instruction Set
Instruction Set
Instruction
Read Wiper Counter Register
I
I
I
I
R
0
R
0
P
P
Operation
Read the contents of the Wiper Counter Register
pointed to by P -P
3
2
1
0
1
0
1
0
1
1
1
1
1
0
0
0
1
1
0
1
1
0
0
1
0
1
0
1
P
P
1
0
1
0
Write Wiper Counter Register
Read Data Register
0
0
P
P
P
P
P
P
P
P
Write new value to the Wiper Counter Register
pointed to by P -P
1
1
1
1
0
0
0
0
1
0
R
R
Read the contents of the Data Register pointed
to by P -P and R –R
1
1
1
0
0
0
1
0
1
0
Write Data Register
R
R
R
R
Write new value to the Data Register pointed to
by P -P and R –R
1
0
1
0
XFR Data Register to Wiper
Counter Register
Transfer the contents of the Data Register pointed
to by R –R to the Wiper Counter Register pointed
1
0
to by P -P
1
0
XFR Wiper Counter Register
to Data Register
1
0
1
1
0
0
1
0
0
0
1
0
R
R
R
R
R
R
P
P
Transfer the contents of the Wiper Counter
Register pointed to by P -P to the Register
1
1
1
0
0
0
1
0
1
0
pointed to by R –R
1
0
Global XFR Data Register to
Wiper Counter Register
0
0
Transfer the contents of the Data Registers
pointed to by R –R of all four pots to their
1
0
respective Wiper Counter Register
Global XFR Wiper Counter
Register to Data Register
0
0
Transfer the contents of all Wiper Counter
Registers to their respective data Registers
pointed to by R –R of all four pots
1
0
Increment/Decrement Wiper
Counter Register
0
0
0
1
1
0
0
1
0
0
P
P
Enable Increment/decrement of the Wiper
Counter Register pointed to by P -P
1
0
1
0
Read Status (WIP bit)
0
0
0
1
Read the status of the internal write cycle, by
checking the WIP bit.
Characteristics subject to change without notice. 7 of 22
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X9400
Instruction Format
Notes: (1) “A1 ~ A0”: stands for the device addresses sent by the master.
(2) WPx refers to wiper position data in the Counter Register
(3) “I”: stands for the increment operation, SI held HIGH during active SCK phase (high).
(4) “D”: stands for the decrement operation, SI held LOW during active SCK phase (high).
Read Wiper Counter Register (WCR)
device type
identifier
device
addresses
instruction
opcode
WCR
addresses
wiper position
(sent by X9400 on SO)
CS
CS
Falling
Edge
Rising
Edge
W W W W W W
0 P P P P P P
A A
P
1
P
0
0
1
0
1
0
0
1
0
0
1
0
0
0
0
1
0
5
4 3 2 1 0
Write Wiper Counter Register (WCR)
device type
identifier
device
addresses
instruction
opcode
WCR
addresses
Data Byte
(sent by Host on SI)
CS
Falling
Edge
CS
Rising
Edge
W W W W W W
0 P P P P P P
A A
P
1
P
0
0
1
0
1
0
0
1
0
1
0
0
0
1
0
5
4 3 2 1 0
Read Data Register (DR)
device type
identifier
device
addresses
instruction DR and WCR
opcode addresses
Data Byte
(sent by X9400 on SO)
CS
CS
Falling
Edge
Rising
Edge
W W W W W W
0 0 P P P P P P
A A
R
1
R
0
P
1
P
0
0
1
0
1
0
0
1
0
1
1
1
0
5
4 3 2 1 0
Write Data Register (DR)
device type
identifier
device
addresses
instruction DR and WCR
opcode addresses
Data Byte
(sent by host on SI)
CS
Falling
Edge
CS
Rising
Edge
HIGH-VOLTAGE
WRITE CYCLE
W W W W W W
0 P P P P P P
A A
1
R
1
R
0
P
1
P
0
0
1
0
1
0
0
1
1
0
0
0
0
5
4 3 2 1 0
Transfer Data Register (DR) to Wiper Counter Register (WCR)
device type
identifier
device
addresses
instruction DR and WCR
opcode addresses
CS
Falling
Edge
CS
Rising
Edge
A A
1
R
1
R
0
P
1
P
0
0
1
0
1
0
0
1 1 0 1
0
Transfer Wiper Counter Register (WCR) to Data Register (DR)
device type
identifier
device
addresses
instruction DR and WCR
opcode addresses
CS
Falling
Edge
CS
Rising
Edge
HIGH-VOLTAGE
WRITE CYCLE
A A
1
R
1
R
0
P
1
P
0
0
1
0
1
0
0
1 1 1 0
0
Characteristics subject to change without notice. 8 of 22
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X9400
Increment/Decrement Wiper Counter Register (WCR)
device type
identifier
device
addresses
instruction
opcode
WCR
increment/decrement
CS
Falling
Edge
CS
Rising
Edge
addresses (sent by master on SDA)
A A
1
P P I/ I/
1 0 D D
I/ I/
D D
0
1
0
1
0
0
0
0
1
0
X X
.
.
.
.
0
Global Transfer Data Register (DR) to Wiper Counter Register (WCR)
device type
identifier
device
addresses
instruction
opcode
DR
addresses
CS
Falling
Edge
CS
Rising
Edge
A A
1
R R
1 0
0
1
0
1
0
0
0
0
0
1
0 0
0
Global Transfer Wiper Counter Register (WCR) to Data Register (DR)
device type
identifier
device
addresses
instruction
opcode
DR
addresses
CS
Falling
Edge
CS
Rising
Edge
HIGH-VOLTAGE
WRITE CYCLE
A A
1
R R
1 0
0
1
0
1
0
0
1
0
0
0
0 0
0
Read Status
device type
identifier
device
addresses
instruction
opcode
wiper
addresses
Data Byte
(sent by X9400 on SO)
CS
CS
Falling
Edge
Rising
Edge
W
I
P
A A
0
1
0
1
0
0
0
1
0
1
0
0
0
1
0
0
0
0
0
0
0
1
0
Characteristics subject to change without notice. 9 of 22
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X9400
ABSOLUTE MAXIMUM RATINGS
COMMENT
Temperature under bias.................... –65°C to +135°C
Storage temperature......................... –65°C to +150°C
Voltage on SCK, SCL or any address
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only; functional operation of the
device (at these or any other conditions above those
listed in the operational sections of this specification) is
not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
input with respect to V ........................ –1V to +7V
SS
Voltage on V+ (referenced to V ).........................10V
SS
Voltage on V- (referenced to V ) ........................ -10V
SS
(V+) – (V-)..............................................................12V
Any V .....................................................................V+
H
Any V ......................................................................V-
L
Lead temperature (soldering, 10 seconds)........ 300°C
I
(10 seconds)................................................ 12mA
W
RECOMMENDED OPERATING CONDITIONS
Temperature
Commercial
Industrial
Min.
0°C
Max.
+70°C
+85°C
Device
X9400
Supply Voltage (V ) Limits
CC
5V 10%
–40°C
X9400-2.7
2.7V to 5.5V
ANALOG CHARACTERISTICS (Over recommended operating conditions unless otherwise stated.)
Limits
Symbol
R
Parameter
End to end resistance
Power rating
Min.
Typ.
Max.
20
Unit
%
Test Conditions
25°C, each pot
TOTAL
50
mW
mA
Ω
I
Wiper current
6
W
R
Wiper resistance
150
40
250
Wiper Current = 1mA,
= 3V
W
V
CC
100
Ω
Wiper Current = 1mA,
= 5V
V
CC
Vv+
Vv-
Voltage on V+ Pin
Voltage on V- Pin
X9400
+4.5
+2.7
-5.5
-5.5
V-
+5.5
+5.5
-4.5
-2.7
V+
V
X9400-2.7
X9400
V
X9400-2.7
V
Voltage on any V /R or V /R Pin
V
dBV
%
TERM
H
H
L
L
Noise
-120
1.6
Ref: 1kHz
R –R
Resolution
Absolute linearity (1)
Relative linearity (2)
-1
+1
MI(3)
MI(3)
ppm/°C
ppm/°C
pF
w(n)(actual) w(n)(expected)
-0.2
+0.2
R
–[R
]
w(n + 1)
w(n) + MI
Temperature coefficient of R
300
TOTAL
Ratiometric temp. coefficient
Potentiometer capacitances
20
10
C /C /C
10/10/25
0.1
See Spice Macromodel
= V to V . Device is in
H
L
W
I
R , R , R leakage current
µA
V
IN
AL
H
L
W
SS
CC
stand-by mode.
Notes: (1) Absolute linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when
used as a potentiometer.
(2) Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a
potentiometer. It is a measure of the error in step size.
(3) MI = RTOT/63 or (R –R )/63, single pot
H
L
Characteristics subject to change without notice. 10 of 22
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X9400
D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.)
Limits
Symbol
Parameter
Min.
Typ.
Max.
Units
Test Conditions
I
V
V
supply current (Active)
400
µA
f = 2MHz, SO = Open,
SCK
CC1
CC
Other Inputs = V
SS
I
supply current (Nonvol-
1
mA
f
= 2MHz, SO = Open,
CC2
CC
SCK
atile Write)
Other Inputs = V
SS
I
V
current (standby)
1
µA
µA
µA
V
SCK = SI = V , Addr. = V
SS SS
SB
CC
I
Input leakage current
Output leakage current
Input HIGH voltage
Input LOW voltage
Output LOW voltage
10
10
V
V
= V to V
SS CC
LI
IN
I
= V to V
SS CC
LO
OUT
V
V
x 0.7
V
+ 0.5
IH
CC
CC
V
–0.5
V
x 0.1
CC
V
IL
V
0.4
V
I
= 3mA
OL
OL
ENDURANCE AND DATA RETENTION
Parameter
Minimum endurance
Data retention
Min.
Unit
100,000
100
Data changes per bit per register
years
CAPACITANCE
Symbol
Test
Max.
Unit
pF
Test Conditions
= 0V
(4)
C
Output capacitance (SO)
8
6
V
OUT
OUT
(4)
C
Input capacitance (A0, A1, SI, and SCK)
pF
V
= 0V
IN
IN
POWER-UP TIMING
Symbol
Parameter
Min.
Max.
Unit
ms
(5)
t
Power-up to initiation of read operation
Power-up to initiation of write operation
1
5
PUR
(5)
t
ms
PUW
(4)
t V
V Power up ramp
CC
0.2
50
V/msec
R
CC
POWER UP REQUIREMENTS (Power Up sequencing
EQUIVALENT A.C. LOAD CIRCUIT
can affect correct recall of the wiper registers)
5V
The preferred power-on sequence is as follows: First
V
, then the potentiometer pins, R , R , and R .
CC
H L W
1533Ω
Voltage should not be applied to the potentiometer pins
before V+ or V- is applied. The V ramp rate specifi-
cation should be met, and any glitches or slope
changes in the V line should be held to <100mV if
CC
SDA Output
CC
100pF
possible. If V
powers down, it should be held below
CC
0.1V for more than 1 second before powering up again
in order for proper wiper register recall. Also, V
CC
should not reverse polarity by more than 0.5V. Recall of
wiper position will not be complete until V , V+ and V-
CC
reach their final value.
Characteristics subject to change without notice. 11 of 22
REV 1.1.8 3/31/04
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X9400
A.C. TEST CONDITIONS
SYMBOL TABLE
Input pulse levels
V
x 0.1 to V x 0.9
CC
CC
WAVEFORM
INPUTS
OUTPUTS
Input rise and fall times
Input and output timing level
10ns
Must be
steady
Will be
steady
V
x 0.5
CC
Notes: (4) This parameter is periodically sampled and not 100% tested
(5) t and t are the delays required from the time the
May change
from Low to
High
Will change
from Low to
High
PUR
PUW
third (last) power supply (V , V+ or V-) is stable until the
CC
specific instruction can be issued. These parameters are
periodically sampled and not 100% tested.
May change
from High to
Low
Will change
from High to
Low
SPICE Macro Model
Don’t Care:
Changes
Allowed
Changing:
State Not
Known
R
TOTAL
R
R
L
N/A
Center Line
is High
Impedance
H
C
L
C
H
C
W
10pF
10pF
25pF
R
W
AC TIMING
Symbol
Parameter
Min.
Max.
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
µs
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
ns
ns
f
SSI/SPI clock frequency
SSI/SPI clock cycle time
SSI/SPI clock high time
SSI/SPI clock low time
Lead time
2.0
SCK
t
500
200
200
250
250
50
CYC
t
WH
t
WL
t
LEAD
t
Lag time
LAG
t
SI, SCK, HOLD and CS input setup time
SI, SCK, HOLD and CS input hold time
SI, SCK, HOLD and CS input rise time
SI, SCK, HOLD and CS input fall time
SO output disable time
SU
t
50
H
t
2
RI
t
2
FI
t
0
0
500
100
DIS
t
SO output valid time
V
t
SO output hold time
HO
RO
t
SO output rise time
50
50
t
SO output fall time
FO
t
HOLD time
400
100
100
HOLD
t
HOLD setup time
HSU
t
HOLD hold time
HH
t
HOLD low to output in High Z
HOLD high to output in Low Z
100
100
20
HZ
t
LZ
T
Noise suppression time constant at SI, SCK, HOLD and CS inputs
CS deselect time
I
t
2
0
0
CS
t
WP, A0 and A1 setup time
WPASU
t
WP, A0 and A1 hold time
WPAH
REV 1.1.8 3/31/04
Characteristics subject to change without notice. 12 of 22
www.xicor.com
X9400
HIGH-VOLTAGE WRITE CYCLE TIMING
Symbol
Parameter
Typ.
Max.
Unit
t
High-voltage write cycle time (store instructions)
5
10
ms
WR
XDCP TIMING
Symbol
Parameter
Min. Max. Unit
t
Wiper response time after the third (last) power supply is stable
Wiper response time after instruction issued (all load instructions)
10
10
µs
µs
ns
WRPO
t
WRL
t
Wiper response time from an active SCL/SCK edge (increment/decrement instruction)
450
WRID
TIMING DIAGRAMS
Input Timing
t
CS
CS
t
t
t
LAG
LEAD
t
CYC
SCK
...
WH
t
t
FI
t
RI
t
t
WL
SU
H
...
MSB
LSB
SI
High Impedance
SO
Output Timing
CS
SCK
SO
...
...
t
t
t
DIS
V
HO
MSB
LSB
ADDR
SI
Characteristics subject to change without notice. 13 of 22
REV 1.1.8 3/31/04
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X9400
Hold Timing
CS
t
t
HH
HSU
SCK
SO
...
t
t
FO
RO
t
t
LZ
HZ
SI
t
HOLD
HOLD
XDCP Timing (for All Load Instructions)
CS
SCK
...
...
t
WRL
MSB
LSB
SI
V
/R
W
W
High Impedance
SO
XDCP Timing (for Increment/Decrement Instruction)
CS
SCK
...
t
WRID
...
V
/R
W
W
...
ADDR
Inc/Dec
SI
Inc/Dec
High Impedance
SO
Characteristics subject to change without notice. 14 of 22
REV 1.1.8 3/31/04
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X9400
Write Protect and Device Address Pins Timing
(Any Instruction)
CS
t
t
WPAH
WPASU
WP
A0
A1
Characteristics subject to change without notice. 15 of 22
REV 1.1.8 3/31/04
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X9400
APPLICATIONS INFORMATION
Basic Configurations of Electronic Potentiometers
+V
R
V
R
V
/R
W
W
I
Three terminal Potentiometer;
Variable voltage divider
Two terminal Variable Resistor;
Variable current
Application Circuits
Noninverting Amplifier
Voltage Regulator
V
+
–
S
V
V
V (REG)
O
317
O
IN
R
1
R
2
I
adj
R
R
1
2
V
= (1+R /R )V
V
(REG) = 1.25V (1+R /R )+I
R
adj
O
2
1
S
O
2
1
2
Offset Voltage Adjustment
Comparator with Hysteresis
R
R
2
1
V
–
+
S
V
V
S
O
100KΩ
–
+
V
O
TL072
R
R
1
2
10KΩ
10KΩ
+12V
V
V
= {R /(R +R )} V (max)
1 1 2 O
UL
LL
10KΩ
-12V
= {R /(R +R )} V (min)
1
1
2
O
Characteristics subject to change without notice. 16 of 22
REV 1.1.8 3/31/04
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X9400
Application Circuits (continued)
Attenuator
Filter
C
V
+
–
S
R
V
R
1
2
O
–
R
V
O
V
+
S
R
3
R
2
R
4
All R = 10kΩ
S
R
1
G
= 1 + R /R
2 1
V
= G V
S
O
O
fc = 1/(2pRC)
-1/2 ≤ G ≤ +1/2
Inverting Amplifier
Equivalent L-R Circuit
R
R
2
1
V
S
R
2
C
1
–
+
V
+
–
S
V
O
R
R
1
3
Z
IN
V = G V
O
S
G = - R /R
2
1
Z
= R + s R (R + R ) C = R + s Leq
2 2 1 3 1 2
IN
(R + R ) >> R
1
3
2
Function Generator
C
R
R
1
2
–
–
+
+
R
R
}
}
A
B
frequency ∝ R , R , C
1
2
amplitude ∝ R , R
A
B
Characteristics subject to change without notice. 17 of 22
REV 1.1.8 3/31/04
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X9400
PACKAGING INFORMATION
24-Lead Plastic Dual In-Line Package Type P
1.265 (32.13)
1.230 (31.24)
0.557 (14.15)
0.530 (13.46)
Pin 1 Index
Pin 1
0.080 (2.03)
0.065 (1.65)
1.100 (27.94)
Ref.
0.162 (4.11)
0.140 (3.56)
Seating
Plane
0.030 (0.76)
0.015 (0.38)
0.150 (3.81)
0.125 (3.18)
0.110 (2.79)
0.090 (2.29)
0.065 (1.65)
0.040 (1.02)
0.022 (0.56)
0.014 (0.36)
0.625 (15.87)
0.600 (15.24)
0°
15°
Typ. 0.010 (0.25)
NOTE:
1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
2. PACKAGE DIMENSIONS EXCLUDE MOLDING FLASH
Characteristics subject to change without notice. 18 of 22
REV 1.1.8 3/31/04
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X9400
PACKAGING INFORMATION
24-Lead Plastic Small Outline Gull Wing Package Type S
0.393 (10.00)
0.290 (7.37)
0.299 (7.60)
0.420 (10.65)
Pin 1 Index
Pin 1
0.014 (0.35)
0.020 (0.50)
0.598 (15.20)
0.610 (15.49)
(4X) 7°
0.092 (2.35)
0.105 (2.65)
0.003 (0.10)
0.012 (0.30)
0.050 (1.27)
0.050"Typical
0.010 (0.25)
0.020 (0.50)
X 45°
0.050"
Typical
0° – 8°
0.009 (0.22)
0.013 (0.33)
0.420"
0.015 (0.40)
0.050 (1.27)
0.030" Typical
24 Places
FOOTPRINT
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
Characteristics subject to change without notice. 19 of 22
REV 1.1.8 3/31/04
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X9400
PACKAGING INFORMATION
24-Lead Plastic, TSSOP Package Type V
.026 (.65) BSC
.169 (4.3)
.177 (4.5)
.252 (6.4) BSC
.303 (7.70)
.311 (7.90)
.047 (1.20)
.0075 (.19)
.0118 (.30)
.002 (.06)
.005 (.15)
.010 (.25)
Gage Plane
(7.72)
(4.16)
0°–8°
Seating Plane
.020 (.50)
.030 (.75)
(1.78)
(0.42)
Detail A (20X)
(0.65)
ALL MEASUREMENTS ARE TYPICAL
.031 (.80)
.041 (1.05)
See Detail “A”
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
Characteristics subject to change without notice. 20 of 22
REV 1.1.8 3/31/04
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X9400
PACKAGING INFORMATION
24-Bump Chip Scale Package (CSP B24)
Package Outline Drawing
a
d
f
A4
B4
C4
D4
E4
F4
A3
A2 A1
B2 B1
C2 C1
D2 D1
E2 E1
B3
C3
D3
E3
F3
j
b
F2 F1
k
m
e
l
Top View (Sample Marking)
Bottom View (Bumped Side)
Side View
e
c
Side View
Package Dimensions
Ball Matrix
Millimeters
Nominal
2.625
3.844
0.677
0.457
0.300
0.370
0.5
4
3
2
1
Symbol
Min
Max
A
B
C
D
E
F
RL1
RW1
VSS
V-
A1
CS
RW0
RL0
VCC
V+
Package Width
a
b
c
d
e
f
2.595
3.814
0.644
0.444
0.280
0.350
2.655
3.874
0.710
0.470
0.320
0.390
SI
WP
RH0
RH3
SO
Package Length
RH1
RH2
HOLD
SCK
Package Height
Body Thickness
RW2
RL2
RL3
RW3
Ball Height
A0
Ball Diameter
Ball Pitch – Width
Ball Pitch – Length
Ball to Edge Spacing – Width
Ball to Edge Spacing – Length
j
k
l
0.5
0.538
0.647
0.563
0.672
0.588
0.697
m
Characteristics subject to change without notice. 21 of 22
REV 1.1.8 3/31/04
www.xicor.com
X9400
Ordering Information
X9400
Y
P
T
V
V
Limits
CC
Device
Blank = 5V 10%
–2.7 = 2.7 to 5.5V
Temperature Range
Blank = Commercial = 0°C to +70°C
I = Industrial = –40°C to +85°C
Package
S24 = 24-Lead SOIC
V24 = 24-Lead TSSOP
B24 = 24-Lead CSP
(production quantity sold in tape and reel)
Potentiometer Organization
Pot 0 Pot 1 Pot 2 Pot 3
W =
Y =
10KΩ 10KΩ 10KΩ 10KΩ
2.5KΩ 2.5KΩ 2.5KΩ 2.5KΩ
©Xicor, Inc. 2003 Patents Pending
LIMITED WARRANTY
Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty,
express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement.
Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and prices
at any time and without notice.
Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, or licenses are implied.
TRADEMARK DISCLAIMER:
Xicor and the Xicor logo are registered trademarks of Xicor, Inc. AutoStore, Direct Write, Block Lock, SerialFlash, MPS, and XDCP are also trademarks of Xicor, Inc. All
others belong to their respective owners.
U.S. PATENTS
Xicor products are covered by one or more of the following U.S. Patents: 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846;
4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829,482; 4,874,967; 4,883,976; 4,980,859; 5,012,132; 5,003,197; 5,023,694; 5,084,667; 5,153,880; 5,153,691;
5,161,137; 5,219,774; 5,270,927; 5,324,676; 5,434,396; 5,544,103; 5,587,573; 5,835,409; 5,977,585. Foreign patents and additional patents pending.
LIFE RELATED POLICY
In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detection
and correction, redundancy and back-up features to prevent such an occurrence.
Xicor’s products are not authorized for use in critical components in life support devices or systems.
1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to
perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user.
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or effectiveness.
Characteristics subject to change without notice. 22 of 22
REV 1.1.8 3/31/04
www.xicor.com
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XICOR
X9400YS24I
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