X9420WS16Z-2.7 [RENESAS]
10K DIGITAL POTENTIOMETER, 3-WIRE SERIAL CONTROL INTERFACE, 64 POSITIONS, PDSO16, 0.300 INCH, ROHS COMPLIANT, PLASTIC, MS-013AA, SOIC-16;
| 型号： | X9420WS16Z-2.7 |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | 10K DIGITAL POTENTIOMETER, 3-WIRE SERIAL CONTROL INTERFACE, 64 POSITIONS, PDSO16, 0.300 INCH, ROHS COMPLIANT, PLASTIC, MS-013AA, SOIC-16 光电二极管 转换器 电阻器 |
| 文件： | 总19页 (文件大小：761K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATASHEET
NOT RECOMMENDED FOR NEW DESIGNS
POSSIBLE SUBSTITUTE PRODUCT
ISL22416, ISL22419, ISL95311, ISL95711
X9420
FN8195
Rev.1.00
April 26, 2006
Low Noise/Low Power/SPI Bus Single Digitally Controlled (XDCP™)
Potentiometer
FEATURES
DESCRIPTION
• Solid-State Potentiometer
• SPI Serial Interface
• Register Oriented Format
—Direct read/write/transfer wiper positions
—Store as many as four positions per
potentiometer
The X9420 integrates a single digitally controlled
potentiometers (XDCP) on a monolithic CMOS
integrated microcircuit.
The digitally controlled potentiometer is implemented
using 63 resistive elements in a series array. Between
each element are tap points connected to the wiper
terminal through switches. The position of the wiper on
the array is controlled by the user through the SPI bus
interface. The potentiometer has associated with it a
volatile Wiper Counter Register (WCR) and 4
nonvolatile Data Registers (DR0:DR3) that can be
directly written to and read by the user. The contents
of the WCR controls the position of the wiper on the
resistor array through the switches. Power-up recalls
the contents of DR0 to the WCR.
• Power Supplies
—V
= 2.7V to 5.5V
CC
—V+ = 2.7V to 5.5V
—V– = -2.7V to -5.5V
• Low Power CMOS
—Standby current < 1µA
• High Reliability
—Endurance–100,000 data changes per bit per
register
—Register data retention–100 years
• 8-bytes of Nonvolatile EEPROM Memory
• 10k or 2.5k Resistor Arrays
• Resolution: 64 Taps Each Pot
• 14 Ld TSSOP and 16 Ld SOIC Packages
• Pb-Free Plus Anneal Available (RoHS Compliant)
The XDCP can be used as
a three-terminal
potentiometer or as a two-terminal variable resistor in
a wide variety of applications including control,
parameter adjustments, and signal processing.
BLOCK DIAGRAM
HOLD
CS
SCK
R0 R1
V /R
H
H
Interface
and
Control
Circuitry
Wiper
Counter
Register
(WCR)
8
S0
Data
V /R
SI
A0
R2 R3
L
L
V
/R
W
W
FN8195 Rev.1.00
April 26, 2006
Page 1 of 19
X9420
Ordering Information
POTENTIOMETER
PART
ORGANIZATION TEMP. RANGE
PKG.
PART NUMBER
X9420WS16*
MARKING
X9420WS
X9420WS Z
X9420WS I
X9420WS ZI
X9420 W
V
LIMITS (V)
(k)
(°C)
PACKAGE
DWG. #
CC
5 ±10%
10
0 to +70
16 Ld SOIC (300 mil)
M16.3
M16.3
M16.3
M16.3
M14.173
X9420WS16Z* (Note)
X9420WS16I*
0 to +70
16 Ld SOIC (300 mil) (Pb-free)
16 Ld SOIC (300 mil)
-40 to +85
-40 to +85
0 to +70
X9420WS16IZ* (Note)
X9420WV14*
16 Ld SOIC (300 mil) (Pb-free)
14 Ld TSSOP (4.4mm)
X9420WV14Z* (Note)
X9420WV14I*
X9420 WZ
X9420 WI
X9420 WZI
X9420YS
0 to +70
14 Ld TSSOP (4.4mm) (Pb-free) M14.173
14 Ld TSSOP (4.4mm) M14.173
14 Ld TSSOP (4.4mm) (Pb-free) M14.173
-40 to +85
-40 to +85
0 to +70
X9420WV14IZ* (Note)
X9420YS16*
2.5
16 Ld SOIC (300 mil)
M16.3
M16.3
M16.3
M16.3
M14.173
X9420YS16Z* (Note)
X9420YS16I*
X9420YS Z
X9420YS I
X9420YS ZI
X9420 Y
0 to +70
16 Ld SOIC (300 mil) (Pb-free)
16 Ld SOIC (300 mil)
-40 to +85
-40 to +85
0 to +70
X9420YS16IZ* (Note)
X9420YV14*
16 Ld SOIC (300 mil) (Pb-free)
14 Ld TSSOP (4.4mm)
X9420YV14Z* (Note)
X9420YV14I*
X9420 YZ
X9420 YI
0 to +70
14 Ld TSSOP (4.4mm) (Pb-free) M14.173
14 Ld TSSOP (4.4mm) M14.173
14 Ld TSSOP (4.4mm) (Pb-free) M14.173
-40 to +85
-40 to +85
0 to +70
X9420YV14IZ* (Note)
X9420WS16-2.7*
X9420 YZI
X9420WS F
2.7 to 5.5
10
16 Ld SOIC (300 mil)
M16.3
M16.3
M16.3
M16.3
X9420WS16Z-2.7* (Note) X9420WS ZF
0 to +70
16 Ld SOIC (300 mil) (Pb-free)
16 Ld SOIC (300 mil)
X9420WS16I-2.7*
X9420WS G
-40 to +85
-40 to +85
X9420WS16IZ-2.7*
(Note)
X9420WS ZG
16 Ld SOIC (300 mil) (Pb-free)
X9420WV14-2.7*
X9420 WF
0 to +70
0 to +70
14 Ld TSSOP (4.4mm)
M14.173
X9420WV14Z-2.7* (Note) X9420 WZF
14 Ld TSSOP (4.4mm) (Pb-free) M14.173
14 Ld TSSOP (4.4mm) M14.173
14 Ld TSSOP (4.4mm) (Pb-free) M14.173
X9420WV14I-2.7*
X9420 WG
-40 to +85
-40 to +85
X9420WV14IZ-2.7*
(Note)
X9420 WZG
X9420YS16-2.7*
X9420YS F
2.7 to 5.5
2.5
0 to +70
0 to +70
16 Ld SOIC (300 mil)
M16.3
M16.3
M16.3
M16.3
M14.173
X9420YS16Z-2.7* (Note) X9420YS ZF
X9420YS16I-2.7* X9420YS G
X9420YS16IZ-2.7* (Note) X9420YS ZG
X9420YV14-2.7* X9420 YF
X9420YV14Z-2.7* (Note) X9420 YZF
X9420YV14I-2.7* X9420 YG
16 Ld SOIC (300 mil) (Pb-free)
16 Ld SOIC (300 mil)
-40 to +85
-40 to +85
0 to +70
16 Ld SOIC (300 mil) (Pb-free)
14 Ld TSSOP (4.4mm)
0 to +70
14 Ld TSSOP (4.4mm) (Pb-free) M14.173
14 Ld TSSOP (4.4mm) M14.173
14 Ld TSSOP (4.4mm) (Pb-free) M14.173
-40 to +85
-40 to +85
X9420YV14IZ-2.7* (Note) X9420 YZG
*Add "T1" suffix for tape and reel.
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
FN8195 Rev.1.00
April 26, 2006
Page 2 of 19
X9420
PIN DESCRIPTIONS
Potentiometer Pins
V /R , V /R
L
Host Interface Pins
H
H
L
The V /R and V /R input are equivalent to the terminal
connections on either end of a mechanical potentiometer.
H
H
L
L
Serial Output (SO)
SO is a push/pull serial data output pin. During a read
cycle, data is shifted out on this pin. Data is clocked out
by the falling edge of the serial clock.
V /R
W
W
The wiper output is equivalent to the wiper output of a
mechanical potentiometer.
Serial Input
Hardware Write Protect Input (WP)
SI is the serial data input pin. All opcodes, byte
addresses and data to be written to the potentiometer
and pot register are input on this pin. Data is latched by
the rising edge of the serial clock.
The WP pin when LOW prevents nonvolatile writes to
the Data Registers. Writing to the Wiper Counter
Register is not restricted.
Serial Clock (SCK)
Analog Supplies (V+, V-)
The SCK input is used to clock data into and out of the
X9420.
The analog supplies V+, V- are the supply voltages for
the XDCP analog section.
Chip Select (CS)
System/Digital Supply (V
)
CC
When CS is HIGH, the X9420 is deselected and the SO
pin is at high impedance, and (unless an internal write
cycle is underway) the device will be in the standby
state. CS LOW enables the X9420, placing it in the
active power mode. It should be noted that after a
power-up, a HIGH to LOW transition on CS is required
prior to the start of any operation.
V
V
is the supply voltage for the system/digital section.
is the system ground.
CC
SS
PIN CONFIGURATION
DIP/SOIC
V+
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
CC
CS
NC
A0
Hold (HOLD)
R /V
L
L
H
HOLD is used in conjunction with the CS pin to select
the device. Once the part is selected and a serial
sequence is underway, HOLD may be used to pause the
serial communication with the controller without resetting
the serial sequence. To pause, HOLD must be brought
LOW while SCK is LOW. To resume communication,
HOLD is brought HIGH, again while SCK is LOW. If the
pause feature is not used, HOLD should be held HIGH
at all times.
SO
HOLD
SCK
NC
V-
R /V
H
X9420
R
/V
W
W
SI
WP
V
SS
TSSOP
X9420
V
1
2
3
4
5
6
7
14
13
12
11
10
9
CC
V+
CS
Device Address (A )
0
R /V
L
L
H
The address inputs is used to set the least significant bit
of the 8-bit slave address. A match in the slave address
serial data stream must be made with the address input
in order to initiate communication with the X9420. A
maximum of 2 devices may occupy the SPI serial bus.
A0
R /V
H
SO
R
/V
W
W
SI
HOLD
SCK
V-
WP
8
V
SS
FN8195 Rev.1.00
April 26, 2006
Page 3 of 19
X9420
PIN NAMES
Wiper Counter Register (WCR)
The X9420 contains a Wiper Counter Register. The
WCR can be envisioned as a 6-bit parallel and serial
load counter with its outputs decoded to select one of
sixty-four switches along its resistor array. The contents
of the WCR can be altered in four ways: it may be written
directly by the host via the Write Wiper Counter Register
instruction (serial load); it may be written indirectly by
transferring the contents of one of four associated data
registers via the XFR Data Register instruction (parallel
load); it can be modified one step at a time by the
Increment/ Decrement instruction. Finally, it is loaded
with the contents of its data register zero (DR0) upon
power-up.
Symbol
SCK
Description
Serial Clock
Serial Data
SI, SO
A0
Device Address
V /R ,
Potentiometer Pins (terminal equivalent)
H
L
H
L
V /R
V /R
W
Potentiometer Pins (wiper equivalent)
Hardware Write Protection
Serial Communication Pause
Analog Supplies
W
WP
HOLD
V+,V-
V
System Supply Voltage
System Ground
CC
The Wiper Counter Register is a volatile register; that is,
its contents are lost when the X9420 is powered-down.
Although the register is automatically loaded with the
value in DR0 upon power-up, this may be different from
the value present at power-down.
V
SS
NC
No Connection
PRINCIPLES OF OPERATION
The X9420 is highly integrated microcircuit
incorporating a resistor array and associated registers
and counter and the serial interface logic providing direct
communication between the host and the XDCP
potentiometer.
a
Data Registers
The potentiometer has four 6-bit nonvolatile Data Registers.
These can be read or written directly by the host. Data can
also be transferred between any of the four Data Registers
and the WCR. It should be noted all operations changing
data in one of the Data Registers is a nonvolatile operation
and will take a maximum of 10ms.
Serial Interface
The X9420 supports the SPI interface hardware
conventions. The device is accessed via the SI input
with data clocked in on the rising SCK. CS must be LOW
and the HOLD and WP pins must be HIGH during the
entire operation.
If the application does not require storage of multiple
settings for the potentiometer, the Data Registers can be
used as regular memory locations for system
parameters or user preference data.
The SO and SI pins can be connected together, since
they have three state outputs. This can help to reduce
system pin count.
Register Descriptions
Table 1. Data Registers, (6-bit), Nonvolatile
0
0
D5
D4
D3
D2
D1
D0
Array Description
(MSB)
(LSB)
The X9420 is comprised of one resistor array containing
63 discrete resistive segments that are connected in
series. The physical ends of each array are equivalent to
the fixed terminals of a mechanical potentiometer
(V /R and V /R inputs).
There are four 6-bit Data Registers associated with the
potentiometer.
– {D5~D0}: These bits are for general purpose Nonvola-
tile data storage or for storage of up to four different
wiper values.
H
H
L
L
At both ends of the array and between each resistor
segment is a CMOS switch connected to the wiper
(V /R ) output. Within the individual array only one
Table 2. Wiper Counter Register, (6-bit), Volatile
W
W
switch may be turned on at a time.
0
0
WP5 WP4 WP3 WP2 WP1 WP0
(LSB)
These switches are controlled by a Wiper Counter Register
(WCR). The six bits of the WCR are decoded to select, and
enable, one of sixty-four switches. The block diagram of the
potentiometer is shown in Figure 1.
(MSB)
– {WP5~WP0}: These bits specify the wiper position of
the potentiometer.
FN8195 Rev.1.00
April 26, 2006
Page 4 of 19
X9420
Figure 1. Detailed Potentiometer Block Diagram
Serial Data Path
V
Serial
Bus
Input
H
From Interface
Circuitry
C
O
U
N
T
Register 0
Register 1
8
6
Parallel
Bus
Input
E
R
Wiper
D
E
C
O
D
E
REGISTER 2
REGISTER 3
Counter
Register
(WCR)
INC/DEC
Logic
IF WCR = 00[H] THEN V = V
W
L
H
UP/DN
IF WCR = 3F[H] THEN V = V
UP/DN
W
V
V
L
Modified SCK
CLK
W
Write in Process
Figure 2. Address/Identification Byte Format
The contents of the Data Registers are saved to
nonvolatile memory when the CS pin goes from LOW to
HIGH after a complete write sequence is received by the
device. The progress of this internal write operation can
be monitored by a Write In Process bit (WIP). The WIP bit
is read with a Read Status command.
Device Type
Identifier
0
1
0
1
1
1
0
A0
Device Address
INSTRUCTIONS
Instruction Byte
Address/Identification (ID) Byte
The next byte sent to the X9420 contains the instruction
and register pointer information. The four most
significant bits are the instruction. The next two bits point
to one of four data registers. The format is shown below
in Figure 3.
The first byte sent to the X9420 from the host, following
a CS going HIGH to LOW, is called the Address or
Identification byte. The most significant four bits of the
slave address are a device type identifier, for the X9420
this is fixed as 0101[B] (refer to Figure 2).
The least significant bit in the ID byte selects one of two
devices on the bus. The physical device address is
Figure 3. Instruction Byte Format
Register
Select
defined by the state of the A input pin. The X9420
0
compares the serial data stream with the address input
state; a successful compare of the address bit is
required for the X9420 to successfully continue the
I3
I2
I1
I0
R1 R0
0
0
command sequence. The A input can be actively driven
0
by a CMOS input signal or tied to V
or V
.
CC
SS
Instructions
The remaining three bits in the ID byte must be set to 110.
The four high order bits of the instruction byte specify the
register oriented instruction is issued. The last two bits
are defined as 0.
operation. The next two bits (R and R ) select one of
1
0
the four registers that is to be acted upon when a
FN8195 Rev.1.00
April 26, 2006
Page 5 of 19
X9420
Two of the eight instructions are two bytes in length and
end with the transmission of the instruction byte. These
instructions are:
Five instructions require a three-byte sequence to
complete. These instructions transfer data between the
host and the X9420; either between the host and one of
the Data Registers or directly between the host and the
WCR. These instructions are:
– XFR Data Register to Wiper Counter Register —This
instruction transfers the contents of one specified Data
Register to the Wiper Counter Register.
– Read Wiper Counter Register—read the current wiper
position of the pot,
– XFR Wiper Counter Register to Data Register—This
instruction transfers the contents of the Wiper Counter
Register to the specified associated Data Register.
– Write Wiper Counter Register—change current wiper
position of the pot,
The basic sequence of the two byte instructions is
illustrated in Figure 4. These two-byte instructions
exchange data between the WCR and one of the Data
Registers. A transfer from a Data Register to a WCR is
essentially a write to a static RAM, with the static RAM
controlling the wiper position. The response of the wiper
– Read Data Register—read the contents of the
selected data register;
– Write Data Register—write a new value to the selected
data register.
– Read Status—This command returns the contents of
the WIP bit which indicates if the internal write cycle is
in progress.
to this action will be delayed by t
. A transfer from the
WRL
WCR (current wiper position), to a Data Register is a write
to nonvolatile memory and takes a minimum of t to
The sequence of these operations is shown in Figure 5
and Figure 6.
WR
complete. The transfer can occur between the
potentiometer and one of its associated registers.
The final command is Increment/Decrement. It is
different from the other commands, because it’s length is
indeterminate. Once the command is issued, the master
can clock the wiper up and/or down in one resistor
segment steps; thereby, providing
a fine tuning
capability to the host. For each SCK clock pulse (t
)
HIGH
while SI is HIGH, the selected wiper will move one
resistor segment towards the V /R terminal. Similarly,
H
H
for each SCK clock pulse while SI is LOW, the selected
wiper will move one resistor segment towards the
V /R terminal. A detailed illustration of the sequence
L
L
and timing for this operation are shown in Figure 7 and
Figure 8.
Figure 4. Two-Byte Instruction Sequence
CS
SCK
SI
0
1
0
1
1
1
0
A0 I3 I2
I1 I0 R1 R0
0
0
FN8195 Rev.1.00
April 26, 2006
Page 6 of 19
X9420
Figure 5. Three-Byte Instruction Sequence (Write)
CS
SCL
SI
1
1
0
1
0
1
0
A0
I3 I2
I1 I0 R1 R0
0
0
0
0
D5 D4 D3 D2 D1 D0
Figure 6. Three-Byte Instruction Sequence (Read)
CS
SCL
SI
Don’t Care
1
1
0
1
0
1
0
A0
I3 I2
I1 I0 R1 R0
0
0
S0
0
0
D5 D4 D3 D2 D1 D0
Figure 7. Increment/Decrement Instruction Sequence
CS
SCK
SI
0
1
0
1
1
1
0
A0
I3 I2
I1 I0
0
0
0
0
I
I
D
E
C
1
I
D
E
C
n
N
C
1
N
C
2
N
C
n
Figure 8. Increment/Decrement Timing Limits
t
WRID
SCK
SI
Voltage Out
V
W
INC/DEC CMD Issued
FN8195 Rev.1.00
April 26, 2006
Page 7 of 19
X9420
Table 3. Instruction Set
Instruction Set
Instruction
I
I
I
I
R
R
0
Operation
3
2
1
0
1
Read Wiper Counter
Register
1
1
1
1
1
0
0
1
1
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
Read the contents of the Wiper Counter Register
Write Wiper Counter
Register
0
0
1
1
0
1
0
1
0
0
Write new value to the Wiper Counter Register
Read Data Register
R
R
Read the contents of the Data Register pointed to by
1
1
1
0
0
0
R - R
1
0
Write Data Register
R
R
R
R
Write new value to the Data Register pointed to by
R - R
1
0
XFR Data Register to
Wiper Counter
Register
Transfer the contents of the Data Register pointed to
by R - R to the Wiper Counter Register
1
0
XFR Wiper Counter
Register to Data
Register
1
0
0
1
0
1
1
1
0
0
0
1
R
R
0
0
0
0
0
1
Transfer the contents of the Wiper Counter
Register to the Data Register pointed to by R - R
1
0
1
0
Increment/Decrement
Wiper Counter
Register
0
0
Enable Increment/decrement of the Wiper Counter
Register
Read Status (WIP bit)
0
0
Read the status of the internal write cycle, by check-
ing the WIP bit.
FN8195 Rev.1.00
April 26, 2006
Page 8 of 19
X9420
Instruction Format
Notes: (1) “A1 ~ A0”: stands for the device addresses sent by the master.
(2) WPx refers to wiper position data in the Wiper Counter Register
“I”: stands for the increment operation, SI held HIGH during active SCK phase (high).
(3) “D”: stands for the decrement operation, SI held LOW during active SCK phase (high).
Read Wiper Counter Register (WCR)
device type
identifier
device
addresses
instruction
opcode
wiper position
(sent by X9420 on SO)
CS
CS
Falling
Edge
Rising
Edge
W W W W W W
0 0 P P P P P P
A
0
0
1
0
1
1
1
0
1
0
0
1
0
0
0
0
0
0
0
0
5
4 3 2 1 0
Write Wiper Counter Register (WCR)
device type
identifier
device
instruction
opcode
Data Byte
(sent by Host on SI)
addresses
CS
Falling
Edge
CS
Rising
Edge
W W W W W W
0 P P P P P P
A
0
0
1
0
1
1
1
0
1
0
1
0
0
5
4 3 2 1 0
Read Data Register (DR)
Read the contents of the Register pointed to by R1 - R0.
device type
identifier
device
addresses
instruction
opcode
register
addresses
Data Byte
(sent by X9420 on SO)
CS
CS
Falling
Edge
Rising
Edge
W W W W W W
0 0 0 0 P P P P P P
A
0
R R
0
1
0
1
1
1
0
1
0
1
1
1
0
5
4 3 2 1 0
Write Data Register (DR)
Write a new value to the Register pointed to by R1 - R0.
device type
identifier
device
addresses
instruction
opcode
register
addresses
Data Byte
(sent by host on SI)
W W W W W W
CS
Falling
Edge
CS
Rising
Edge
HIGH-VOLTAGE
WRITE CYCLE
A
0
R R
1 0
0 1 0 1 1 1 0
1 1 0 0
0 0 0 0 P P P P P P
5 4 3 2 1 0
Transfer Data Register (DR) to Wiper Counter Register (WCR)
Transfer the contents of the Register pointed to by R1 - R0 to the WCR.
device type
identifier
device
addresses
instruction
opcode
register
addresses
CS
Falling
Edge
CS
Rising
Edge
A
0
R R
0 0
1 0
0 1 0 1 1 1 0
1 1 0 1
FN8195 Rev.1.00
April 26, 2006
Page 9 of 19
X9420
Transfer Wiper Counter Register (WCR) to Data Register (DR)
device type
identifier
device
addresses
instruction
opcode
register
addresses
CS
Falling
Edge
CS
Rising
Edge
HIGH-VOLTAGE
WRITE CYCLE
A
0
R R
0
1
0 1
1
1
0
1
1
1 0
0 0
1
0
Increment/Decrement Wiper Counter Register (WCR)
device type
identifier
device
addresses
instruction
opcode
increment/decrement
(sent by master on SDA)
CS
Falling
Edge
CS
Rising
Edge
A
0
0
1
0
1
1
1
0
0
0
1
0
0
0
0
0 I/D I/D
.
.
.
.
I/D I/D
Read Status
device type
identifier
device
addresses
instruction
opcode
Data Byte
(sent by X9420 on SO)
CS
CS
Falling
Edge
Rising
Edge
W
I
P
A
0
0
1
0
1
1
1
0
0
1
0
1
0
0
0
1
0
0
0
0
0
0
0
FN8195 Rev.1.00
April 26, 2006
Page 10 of 19
X9420
ABSOLUTE MAXIMUM RATINGS
COMMENT
Temperature under bias.................... -65°C to +135°C
Storage temperature ......................... -65°C to +150°C
Voltage on SCK, SCL or any
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only; functional operation of the
device (at these or any other conditions above those
listed in the operational sections of this specification) is
not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
address input with respect to V ........... -1V to +7V
SS
Voltage on V+ (referenced to V )........................10V
SS
Voltage on V- (referenced to V )........................-10V
SS
(V+) - (V-) ..............................................................12V
Any V /R , V /R , V /R ........................... V- to V+
H
H
L
L
W
W
Lead temperature (soldering, 10s) .................... 300°C
(10s)..............................................................±6mA
I
W
RECOMMENDED OPERATING CONDITIONS
Temp
Min.
0C
-40C
Max.
+70C
+85C
Device
X9420
Supply Voltage (V ) Limits
CC
Commercial
Industrial
5V 10%
2.7V to 5.5V
X9420-2.7
ANALOG CHARACTERISTICS (Over recommended operating conditions unless otherwise stated.)
Limits
Symbol
R
Parameter
End to End Resistance
Power Rating
Min.
Typ.
Max. Units
Test Conditions
25°C, each pot
±20
50
%
mW
mA
TOTAL
I
Wiper Current
±3
W
R
Wiper Resistance
150
40
250
Wiper Current = 1mA,
V+/V- = ±3V
W
100
Wiper Current = 1mA,
V+/V- = ±5V
Vv+
Vv-
Voltage on V+ Pin
Voltage on V- Pin
X9420
+4.5
+2.7
-5.5
-5.5
V-
+5.5
+5.5
-4.5
-2.7
V+
V
X9420-2.7
X9420
V
X9420-2.7
V
Voltage on any V /R , V /R , V /R
V
dBV
%
TERM
H
H
L
L
W
W
Noise
-140
1.6
Ref: 1kHz
(4)
Resolution
See Note 5
(1)
(3)
Absolute Linearity
(2)
±1
MI
V
V
- V
w(n)(expected)
]
w(n) + MI
w(n)(actual)
- [V
(3)
MI
Relative Linearity
Temperature Coefficient of R
±0.2
w(n + 1)
300
ppm/°C See Note 5
20 ppm/°C See Note 5
TOTAL
Ratiometric Temperature Coefficient
Potentiometer Capacitances
Rh, RI, Rw leakage current
C /C /C
10/10/25
0.1
pF
µA
See Circuit #3
H
L
W
I
10
Vin = V- to V+. Device is in
stand-by mode.
AL
Notes: (1) Absolute Linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used as
a potentiometer.
(2) Relative Linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a potenti-
ometer. It is a measure of the error in step size.
(3) MI = RTOT/63 or (V - V )/63, single pot.
H
L
(4) Typical = Individual array resolution.
FN8195 Rev.1.00
April 26, 2006
Page 11 of 19
X9420
D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.)
Limits
Symbol
Parameter
Min.
Typ.
Max.
Units
Test Conditions
I
V
V
Supply Current (Active)
400
µA
f = 2MHz, SO = Open,
SCK
CC1
CC
Other Inputs = V
SS
I
Supply Current
1
mA
f
= 2MHz, SO = Open,
CC2
CC
SCK
Other Inputs = V
(Non-volatile Write)
SS
I
V
Current (Standby)
1
A
A
A
V
SCK = SI = V , Addr. = V
SS SS
SB
CC
I
Input Leakage Current
Output Leakage Current
Input HIGH Voltage
Input LOW Voltage
10
10
V
V
= V to V
SS CC
LI
IN
I
= V to V
SS CC
LO
OUT
V
V
x 0.7
V
+ 0.5
IH
CC
-0.5
CC
V
V
x 0.1
V
IL
CC
0.4
V
Output LOW Voltage
V
I
= 3mA
OL
OL
ENDURANCE AND DATA RETENTION
Parameter
Minimum Endurance
Data Retention
Min.
Units
100,000
100
Data Changes per Bit per Register
Years
CAPACITANCE
Symbol
Test
Output Capacitance (SO)
Max.
Units
pF
Test Conditions
= 0V
(5)
C
8
6
V
OUT
OUT
V = 0V
IN
(5)
C
Input Capacitance (A0, SI, and SCK)
pF
IN
POWER-UP TIMING
Symbol
Parameter
Max.
1
Max.
1
Units
ms
(6)
t
Power-up to Initiation of Read Operation
Power-up to Initiation of Write Operation
PUR
(6)
t
5
5
ms
PUW
t V
V
Power-up Ramp
0.2
50
V/msec
R CC
CC
POWER-UP REQUIREMENTS (Power-up sequencing can affect correct recall of the wiper registers)
The preferred power-on sequence is as follows: First V , then V+ and V-, and then the potentiometer pins, R , R ,
CC
and R . Voltage should not be applied to the potentiometer pins before V+ or V- is applied. The V
H
L
ramp rate
W
CC
line should be held to <100mV if possible.
specification should be met, and any glitches or slope changes in the V
CC
If V
powers down, it should be held below 0.1V for more than 1 second before powering up again in order for
CC
proper wiper register recall. Also, V
should not reverse polarity by more than 0.5V. Recall of wiper position will not
CC
be complete until V , V+ and V- reach their final value.
CC
Notes: (5) This parameter is periodically sampled and not 100% tested.
(6) t
and t
are the delays required from the time the third (last) power supply (V , V+ or V-) is stable until the specific instruction
PUR
can be issued. These parameters are periodically sampled and not 100% tested.
PUW CC
FN8195 Rev.1.00
April 26, 2006
Page 12 of 19
X9420
A.C. TEST CONDITIONS
EQUIVALENT A.C. LOAD CIRCUIT
Input pulse levels
V
x 0.1 to V
x 0.5
x 0.9
CC
CC
10ns
5V
Input rise and fall times
Input and output timing level
1533
V
CC
SDA Output
100pF
AC TIMING
Symbol
Parameter
Min.
Max.
Units
MHz
ns
ns
ns
ns
ns
ns
ns
µs
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
ns
ns
f
SSI/SPI Clock Frequency
SSI/SPI Clock Cycle Time
SSI/SPI Clock High Time
SSI/SPI Clock Low Time
Lead Time
2.0
SCK
t
500
200
200
250
250
50
CYC
t
WH
t
WL
t
LEAD
t
Lag Time
LAG
t
SI, SCK, HOLD and CS Input Setup Time
SI, SCK, HOLD and CS Input Hold Time
SI, SCK, HOLD and CS Input Rise Time
SI, SCK, HOLD and CS Input Fall Time
SO Output Disable Time
SU
t
50
H
t
2
RI
t
2
FI
t
0
0
500
100
DIS
t
SO Output Valid Time
V
t
SO Output Hold Time
HO
RO
t
SO Output Rise Time
50
50
t
SO Output Fall Time
FO
t
HOLD Time
400
100
100
HOLD
t
HOLD Setup Time
HSU
t
HOLD Hold Time
HH
t
HOLD Low to Output in High Z
HOLD High to Output in Low Z
100
100
20
HZ
t
LZ
T
Noise Suppression Time Constant at SI, SCK, HOLD and CS inputs
CS Deselect Time
I
t
2
0
0
CS
t
WP, A0 and A1 Setup Time
WPASU
t
WP, A0 and A1 Hold Time
WPAH
FN8195 Rev.1.00
April 26, 2006
Page 13 of 19
X9420
HIGH-VOLTAGE WRITE CYCLE TIMING
Symbol
Parameter
Typ.
Max.
Units
t
High-voltage Write Cycle Time (Store Instructions)
5
10
ms
WR
XDCP TIMING
Symbol
Parameter
Min. Max. Units
t
Wiper Response Time After The Third (Last) Power Supply Is Stable
Wiper Response Time After Instruction Issued (All Load Instructions)
10
10
µs
µs
ns
WRPO
t
WRL
t
Wiper Response Time From An Active SCL/SCK Edge (Increment/Decrement
Instruction)
450
WRID
SYMBOL TABLE
WAVEFORM
INPUTS
OUTPUTS
Must be
steady
Will be
steady
May change
from Low to
High
Will change
from Low to
High
May change
from High to
Low
Will change
from High to
Low
Don’t Care:
Changes
Allowed
Changing:
State Not
Known
N/A
Center Line
is High
Impedance
FN8195 Rev.1.00
April 26, 2006
Page 14 of 19
X9420
TIMING DIAGRAMS
Input Timing
t
CS
CS
t
t
t
LAG
LEAD
t
CYC
SCK
...
WH
t
t
FI
t
RI
t
t
WL
SU
H
...
MSB
LSB
SI
High Impedance
SO
Output Timing
CS
SCK
SO
...
...
t
t
t
DIS
V
HO
MSB
LSB
ADDR
SI
Hold Timing
CS
SCK
SO
t
t
HH
HSU
...
t
t
FO
RO
t
t
LZ
HZ
SI
t
HOLD
HOLD
FN8195 Rev.1.00
April 26, 2006
Page 15 of 19
X9420
XDCP Timing (for All Load Instructions)
CS
SCK
...
...
t
WRL
MSB
LSB
SI
V
W
High Impedance
SO
XDCP Timing (for Increment/Decrement Instruction)
CS
SCK
...
t
WRID
...
V
W
...
ADDR
Inc/Dec
SI
Inc/Dec
High Impedance
SO
Write Protect and Device Address Pins Timing
(Any Instruction)
CS
t
t
WPAH
WPASU
WP
A0
A1
FN8195 Rev.1.00
April 26, 2006
Page 16 of 19
X9420
APPLICATIONS INFORMATION
Electronic potentiometers provide three powerful application advantages: (1) the variability and reliability of a solid-
state potentiometer, (2) the flexibility of computer-based digital controls, and (3) the retentivity of nonvolatile memory
used for the storage of multiple potentiometer settings or data.
Basic Configurations of Electronic Potentiometers
V
R
V
R
V
H
V
W
V
L
I
Three terminal Potentiometer;
Variable voltage divider
Two terminal Variable Resistor;
Variable current
Basic Circuits
Buffered Reference Voltage
Cascading Techniques
Noninverting Amplifier
R
+5V
1
+V
+V
+V
LM308A
V
+
–
S
+5V
V
O
X
V
OP-07
W
+
–
V
-5V
W
V
= V
W
OUT
V
W
R
2
+V
-5V
R
1
V
W
V
= (1+R /R )V
2 1 S
(a)
(b)
O
Offset Voltage Adjustment
Comparator with Hysterisis
Voltage Regulator
R
R
2
1
V
–
+
S
V
V (REG)
O
317
IN
V
V
S
O
100k
R
1
–
+
V
O
I
adj
TL072
R
R
1
2
R
2
10k
10k
+12V
V
V
= {R /CR +R } V (max)
1 1 2 O
UL
LL
10k
-12V
= {R /CR +R } V (min)
V
(REG) = 1.25V (1+R /R )+I
R
adj 2
1
1
2
O
O
2
1
FN8195 Rev.1.00
April 26, 2006
Page 17 of 19
X9420
Thin Shrink Small Outline Plastic Packages (TSSOP)
M14.173
N
14 LEAD THIN SHRINK SMALL OUTLINE PLASTIC
PACKAGE
INDEX
AREA
0.25(0.010)
M
B M
E
E1
-B-
INCHES
MIN
MILLIMETERS
GAUGE
PLANE
SYMBOL
MAX
0.047
0.006
0.041
0.0118
0.0079
0.199
0.177
MIN
-
MAX
1.20
0.15
1.05
0.30
0.20
5.05
4.50
NOTES
A
A1
A2
b
-
-
1
2
3
0.002
0.031
0.0075
0.0035
0.195
0.169
0.05
0.80
0.19
0.09
4.95
4.30
-
L
0.25
0.010
-
0.05(0.002)
SEATING PLANE
A
9
-A-
D
c
-
D
3
-C-
E1
e
4
A2
e
A1
0.026 BSC
0.65 BSC
-
c
b
0.10(0.004)
E
0.246
0.256
6.25
0.45
6.50
0.75
-
0.10(0.004) M
C
A M B S
L
0.0177
0.0295
6
N
14
14
7
NOTES:
o
o
o
o
0
8
0
8
-
1. These package dimensions are within allowable dimensions of
JEDEC MO-153-AC, Issue E.
Rev. 2 4/06
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm
(0.006 inch) per side.
4. Dimension “E1” does not include interlead flash or protrusions. Inter-
lead flash and protrusions shall not exceed 0.15mm (0.006 inch) per
side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “b” does not include dambar protrusion. Allowable dambar
protrusion shall be 0.08mm (0.003 inch) total in excess of “b” dimen-
sion at maximum material condition. Minimum space between protru-
sion and adjacent lead is 0.07mm (0.0027 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact. (Angles in degrees)
FN8195 Rev.1.00
April 26, 2006
Page 18 of 19
X9420
Small Outline Plastic Packages (SOIC)
M16.3 (JEDEC MS-013-AA ISSUE C)
N
16 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE
INDEX
AREA
0.25(0.010)
M
B M
H
INCHES
MILLIMETERS
E
SYMBOL
MIN
MAX
MIN
2.35
0.10
0.33
0.23
10.10
7.40
MAX
2.65
NOTES
-B-
A
A1
B
C
D
E
e
0.0926
0.0040
0.013
0.1043
0.0118
0.0200
0.0125
0.4133
0.2992
-
0.30
-
1
2
3
L
0.51
9
SEATING PLANE
A
0.0091
0.3977
0.2914
0.32
-
-A-
10.50
7.60
3
h x 45°
D
4
-C-
0.050 BSC
1.27 BSC
-
H
h
0.394
0.010
0.016
0.419
0.029
0.050
10.00
0.25
0.40
10.65
0.75
1.27
-
e
A1
C
5
B
0.10(0.004)
L
6
0.25(0.010) M
C
A M B S
N
16
16
7
0°
8°
0°
8°
-
NOTES:
Rev. 1 6/05
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Interlead
flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above
the seating plane, shall not exceed a maximum value of 0.61mm (0.024
inch)
10. Controlling dimension: MILLIMETER. Converted inch dimensions are
not necessarily exact.
© Copyright Intersil Americas LLC 2005-2006. All Rights Reserved.
All trademarks and registered trademarks are the property of their respective owners.
For additional products, see www.intersil.com/en/products.html
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such
modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are
current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its
subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN8195 Rev.1.00
April 26, 2006
Page 19 of 19
相关型号：
X9420WS16Z-2.7T1
10K DIGITAL POTENTIOMETER, 3-WIRE SERIAL CONTROL INTERFACE, 64 POSITIONS, PDSO16, 0.300 INCH, ROHS COMPLIANT, PLASTIC, MS-013AA, SOIC-16
RENESAS
X9420WS16ZT1
10K DIGITAL POTENTIOMETER, 3-WIRE SERIAL CONTROL INTERFACE, 64 POSITIONS, PDSO16, 0.300 INCH, ROHS COMPLIANT, PLASTIC, MS-013AA, SOIC-16
RENESAS
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