X9421WV14I-2.7T1 [RENESAS]
10K DIGITAL POTENTIOMETER, 3-WIRE SERIAL CONTROL INTERFACE, 64 POSITIONS, PDSO14, 4.40 MM, PLASTIC, TSSOP-14;型号: | X9421WV14I-2.7T1 |
厂家: | RENESAS TECHNOLOGY CORP |
描述: | 10K DIGITAL POTENTIOMETER, 3-WIRE SERIAL CONTROL INTERFACE, 64 POSITIONS, PDSO14, 4.40 MM, PLASTIC, TSSOP-14 光电二极管 转换器 电阻器 |
文件: | 总20页 (文件大小:806K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
DATASHEET
NOT RECOMMENDED FOR NEW DESIGNS
POSSIBLE SUBSTITUTE PRODUCT
ISL22416, ISL22419
X9421
FN8196
Rev.1.00
January 14, 2009
Low Noise/Low Power/SPI Bus Single Digitally Controlled (XDCP™)
Potentiometer
Description
Features
The X9421 integrates a single digitally controlled
potentiometer (XDCP) on a monolithic CMOS integrated
circuit.
• Single Voltage Potentiometer
• 64 Resistor Taps
• SPI Serial Interface for Write, Read, and Transfer
Operations of the Potentiometer
The digital controlled potentiometer is implemented using 63
resistive elements in a series array. Between each element
are tap points connected to the wiper terminal through
switches. The position of the wiper on the array is controlled
by the user through the SPI bus interface. The potentiometer
has associated with it a volatile Wiper Counter Register
(WCR) and a four non-volatile Data Registers that can be
directly written to and read by the user. The contents of the
WCR controls the position of the wiper on the resistor array
though the switches. Power-up recalls the contents of the
default data register (DR0) to the WCR.
• Wiper Resistance, 150 Typical at 5V
• 4 Non-Volatile Data Registers
• Non-Volatile Storage of Multiple Wiper Positions
• Power-on Recall. Loads Saved Wiper Position on
Power-up.
• Standby Current < 5µA Max
• V
CC
: 2.7V to 5.5V Operation
• 2.5k, 10k End to End Resistance
• 100 yr. Data Retention
The XDCP can be used as a three-terminal potentiometer or
as a two terminal variable resistor in a wide variety of
applications including control, parameter adjustments, and
signal processing.
• Endurance: 100, 000 Data Changes per Bit per Register
• 14 Ld TSSOP, 16 Ld SOIC
• Low Power CMOS
• Pb-Free Available (RoHS Compliant)
Block Diagram
V
R /V
CC
H
H
WRITE
READ
TRANSFER
INC / DEC
10k
ADDRESS
DATA
POWER-ON RECALL
64-TAPS
STATUS
WIPER
WIPER COUNTER
REGISTER (WCR)
BUS
POT
SPI
BUS
INTERFACE
INTERFACE &
CONTROL
DATA REGISTERS
4 BYTES
CONTROL
R
/V
W
V
R /V
W
SS
L
L
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
FN8196 Rev.1.00
January 14, 2009
Page 1 of 20
XDCP is a trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005, 2008, 2009. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
X9421
Ordering Information
POTENTIOMETER
ORGANIZATION
(k)
PART
NUMBER
PART
MARKING
V
LIMITS
(V)
TEMP
RANGE (°C)
CC
PACKAGE
X9421YS16*
X9421YS
5 ±10%
2.5
0 to +70
0 to +70
16 Ld SOIC (300 mil)
X9421YS16Z* (Note)
X9421YS16I*
X9421YS Z
X9421YS I
X9421YS ZI
X9421 YV
16 Ld SOIC (300 mil) (Pb-Free)
16 Ld SOIC (300 mil)
-40 to +85
-40 to +85
0 to +70
X9421YS16IZ* (Note)
X9421YV14*
16 Ld SOIC (300 mil) (Pb-Free)
14 Ld TSSOP (4.4mm)
X9421YV14Z* (Note)
X9421YV14I*
X9421 YVZ
X9421 YV I
X9421 YVZI
X9421WS
0 to +70
14 Ld TSSOP (4.4mm) (Pb-Free)
14 Ld TSSOP (4.4mm)
-40 to +85
-40 to +85
0 to +70
X9421YV14IZ* (Note)
X9421WS16*
14 Ld TSSOP (4.4mm) (Pb-Free)
16 Ld SOIC (300 mil)
10
X9421WS16Z* (Note)
X9421WS16I*
X9421WS Z
X9421WS I
X9421WS ZI
X9421 WV
X9421 WV Z
X9421 WV I
X9421 WVZI
X9421YS F
X9421YS ZF
X9421 YS G
X9421 YS ZG
X9421 YVF
0 to +70
16 Ld SOIC (300 mil) (Pb-Free)
16 Ld SOIC (300 mil)
-40 to +85
-40 to +85
0 to +70
X9421WS16IZ* (Note)
X9421WV14*
16 Ld SOIC (300 mil) (Pb-Free)
14 Ld TSSOP (4.4mm)
X9421WV14Z* (Note)
X9421WV14I*
0 to +70
14 Ld TSSOP (4.4mm) (Pb-Free)
14 Ld TSSOP (4.4mm)
-40 to +85
-40 to +85
0 to +70
X9421WV14IZ* (Note)
X9421YS16-2.7*
X9421YS16Z-2.7* (Note)
X9421YS16I-2.7*
X9421YS16IZ-2.7* (Note)
X9421YV14-2.7*
14 Ld TSSOP (4.4mm) (Pb-Free)
16 Ld SOIC (300 mil)
2.7 to 5.5
2.5
0 to +70
16 Ld SOIC (300 mil) (Pb-Free)
16 Ld SOIC (300 mil)
-40 to +85
-40 to +85
0 to +70
16 Ld SOIC (300 mil) (Pb-Free)
14 Ld TSSOP (4.4mm)
X9421YV14Z-2.7* (Pb-free) X9421 YVZF
X9421YV14I-2.7* X9421 YVG
X9421YV14IZ-2.7* (Pb-free) X9421 YVZG
0 to +70
14 Ld TSSOP (4.4mm) (Pb-Free)
14 Ld TSSOP (4.4mm)
-40 to +85
-40 to +85
0 to +70
14 Ld TSSOP (4.4mm) (Pb-Free)
16 Ld SOIC (300 mil)
X9421WS16-2.7*
X9421WS F
X9421WS ZF
X9421WS G
X9421WS ZG
X9421 WVF
10
X9421WS16Z-2.7* (Note)
X9421WS16I-2.7*
0 to +70
16 Ld SOIC (300 mil) (Pb-Free)
16 Ld SOIC (300 mil)
-40 to +85
-40 to +85
0 to +70
X9421WS16IZ-2.7* (Note)
X9421WV14-2.7*
16 Ld SOIC (300 mil) (Pb-Free)
14 Ld TSSOP (4.4mm)
X9421WV14Z-2.7* (Pb-free) X9421 WVZF
X9421WV14I-2.7* X9421 WVG
X9421WV14IZ-2.7* (Pb-free) X9421 WVZG
*Add "T1" suffix for tape and reel. Please refer to TB347 for details on reel specifications.
0 to +70
14 Ld TSSOP (4.4mm) (Pb-Free)
14 Ld TSSOP (4.4mm)
-40 to +85
-40 to +85
14 Ld TSSOP (4.4mm) (Pb-Free)
NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100%
matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020
FN8196 Rev.1.00
January 14, 2009
Page 2 of 20
X9421
Detailed Functional Diagrams
V
CC
POWER-ON RECALL
WIPER
10k
DR0
64-taps
DR1
R /V
H
H
HOLD
COUNTER
REGISTER
(WCR)
CONTROL
CS
SCK
SO
DR2 DR3
R /V
L
L
INTERFACE
AND
CONTROL
CIRCUITRY
R
/V
W
W
SI
A0
DATA
WP
V
SS
Circuit Level Applications
System Level Applications
• Vary the Gain of a Voltage Amplifier
• Adjust the contrast in LCD displays
• Provide Programmable DC Reference Voltages for
Comparators and Detectors
• Control the Power Level of LED Transmitters in
Communication Systems
• Control the Volume in Audio Circuits
• Set and Regulate the DC Biasing Point in an RF Power
Amplifier in Wireless Systems
• Trim Out the Offset Voltage Error in a Voltage Amplifier
Circuit
• Control the Gain in Audio and Home Entertainment Systems
• Set the Output Voltage of a Voltage Regulator
• Trim the Resistance in Wheatstone Bridge Circuits
• Provide the Variable DC Bias for Tuners in RF Wireless
Systems
• Set the Operating Points in Temperature Control Systems
• Control the Gain, Characteristic Frequency and
Q-factor in Filter Circuits
• Control the Operating Point for Sensors in Industrial
Systems
• Set the Scale Factor and Zero Point in Sensor Signal
Conditioning Circuits
• Trim Offset and Gain Errors in Artificial Intelligent Systems
• Vary the Frequency and Duty Cycle of Timer ICs
• Vary the DC Biasing of a Pin Diode Attenuator in RF Circuits
• Provide a Control Variable (I, V, or R) in Feedback Circuits
FN8196 Rev.1.00
January 14, 2009
Page 3 of 20
X9421
X9421
X9421
(14 LD TSSOP)
TOP VIEW
(16 LD SOIC)
TOP VIEW
NC
SO
1
2
3
4
5
6
7
8
16 VCC
15 NC
S0
VCC
R /V
1
2
3
4
5
6
7
14
13
12
11
10
9
NC
L
L
NC
14 R /V
L L
R /V
H
NC
CS
H
CS
13 R /V
H H
R
/V
W
W
SCK
SI
12 R /V
W
W
SCK
SI
HOLD
A0
11 ISEN
10 AO
NC
VSS
8
WP
9
WP
VSS
Pin Assignments
TSSOP
SOIC
PIN NO.
PIN NO.
SYMBOL
SO
DESCRIPTION
1
2, 3
4
2
Serial Data Output
No Connect
3, 1, 7, 5
NC
4
5
CS
Chip Select
5
SCK
SI
Serial Clock
6
6
Serial Data Input
System Ground
Hardware Write Protect
Device Address
7
8
VSS
WP
8
9
9
10
A0
10
11
12
13
14
HOLD
Device select. Pause the serial bus.
Wiper Terminal of the Potentiometer.
High Terminal of the Potentiometer.
Low Terminal of the Potentiometer.
System Supply Voltage
12
13
14
16
R /V
W
W
H
L
R /V
H
R /V
L
VCC
underway) the device will be in the standby state. CS LOW
enables the X9421, placing it in the active power mode. It
should be noted that after a power-up, a HIGH to LOW
transition on CS is required prior to the start of any operation.
Pin Descriptions
Host Interface Pins
SERIAL OUTPUT (SO)
SO is a push/pull serial data output pin. During a read cycle,
data is shifted out on this pin. Data is clocked out by the falling
edge of the serial clock.
HOLD (HOLD)
HOLD is used in conjunction with the CS pin to select the
device. Once the part is selected and a serial sequence is
underway, HOLD may be used to pause the serial
SERIAL INPUT
communication with the controller without resetting the serial
sequence. To pause, HOLD must be brought LOW while SCK
is LOW. To resume communication, HOLD is brought HIGH,
again while SCK is LOW. If the pause feature is not used,
HOLD should be held HIGH at all times.
SI is the serial data input pin. All opcodes, byte addresses and
data to be written to the potentiometer and pot register are
input on this pin. Data is latched by the rising edge of the serial
clock.
SERIAL CLOCK (SCK)
DEVICE ADDRESS (A )
0
The SCK input is used to clock data into and out of the X9421.
The address input is used to set the least significant bit of the
8-bit slave address. A match in the slave address serial data
stream must be made with the address input in order to initiate
CHIP SELECT (CS)
When CS is HIGH, the X9421 is deselected and the SO pin is
at high impedance, and (unless an internal write cycle is
FN8196 Rev.1.00
January 14, 2009
Page 4 of 20
X9421
communication with the X9421. A maximum of two devices
may occupy the SPI serial bus.
ways: it may be written directly by the host via the Write Wiper
Counter Register instruction (serial load); it may be written
indirectly by transferring the contents of one of four associated
Data Registers via the XFR Data Register instruction (parallel
load); it can be modified one step at a time by the
Potentiometer Pins
V /R , V /R
L
H
H
L
Increment/Decrement instruction. Finally, it is loaded with the
contents of its data register zero (DR0) upon power-up.
The V /R and V /R inputs are equivalent to the terminal
connections on either end of a mechanical potentiometer.
H
H
L
L
The Wiper Counter Register is a volatile register; that is, its
contents are lost when the X9421 is powered-down. Although
the register is automatically loaded with the value in DR0 upon
power-up, this may be different from the value present at
power-down.
V /R
W
W
The wiper output is equivalent to the wiper output of a
mechanical potentiometer.
HARDWARE WRITE PROTECT INPUT (WP)
The WP pin when LOW prevents nonvolatile writes to the Data
Registers. Writing to the Wiper Counter Register is not
restricted.
Data Registers
The potentiometer has four 6-bit nonvolatile Data Registers.
These can be read or written directly by the host. Data can also
be transferred between any of the four Data Registers and the
WCR. It should be noted all operations changing data in one of
the Data Registers is a nonvolatile operation and will take a
maximum of 10ms.
SYSTEM/DIGITAL SUPPLY (V
)
CC
VCC is the supply voltage for the system/digital section. VSS is
the system ground.
Principles of Operation
If the application does not require storage of multiple settings
for the potentiometer, the Data Registers can be used as
regular memory locations for system parameters or user
preference data.
The X9421 is a highly integrated microcircuit incorporating a
resistor array and associated registers and counter and the
serial interface logic providing direct communication between
the host and the XDCP potentiometer.
Register Descriptions
Serial Interface
TABLE 1. DATA REGISTERS, (6-BIT), NONVOLATILE
The X9421 supports the SPI interface hardware conventions.
The device is accessed via the SI input with data clocked in on
the rising SCK. CS must be LOW and the HOLD and WP pins
must be HIGH during the entire operation.
0
0
D5
D4
D3
D2
D1
D0
(MSB)
(LSB)
There are four 6-bit Data Registers associated with the
potentiometer.
The SO and SI pins can be connected together, since they
have three state outputs. This can help to reduce system pin
count.
• {D5~D0}: These bits are for general purpose Nonvolatile
data storage or for storage of up to four different wiper
values.
Array Description
The X9421 is comprised of one resistor array containing 63
discrete resistive segments that are connected in series. The
physical ends of each array are equivalent to the fixed
TABLE 2. WIPER COUNTER REGISTER, (6-BIT), VOLATILE
0
0
WP5
WP4
WP3
WP2
WP1
WP0
(MSB)
(LSB)
terminals of a mechanical potentiometer (V /R and V /R
H
H
L
L
inputs).
At both ends of the array and between each resistor segment
is a CMOS switch connected to the wiper (V /R ) output.
• {WP5~WP0}: These bits specify the wiper position of the
potentiometer.
W
W
Within the individual array only one switch may be turned on at
a time.
These switches are controlled by a Wiper Counter Register
(WCR). The six bits of the WCR are decoded to select, and
enable, one of sixty-four switches. The block diagram of the
potentiometer is shown in Figure 1.
Wiper Counter Register (WCR)
The X9421 contains a Wiper Counter Register. The WCR can
be envisioned as a 6-bit parallel and serial load counter with its
outputs decoded to select one of sixty-four switches along its
resistor array. The contents of the WCR can be altered in four
FN8196 Rev.1.00
January 14, 2009
Page 5 of 20
X9421
SERIAL DATA PATH
V
SERIAL
BUS
INPUT
H
FROM INTERFACE
CIRCUITRY
C
O
U
N
T
REGISTER 0
REGISTER 1
8
6
PARALLEL
BUS
INPUT
E
R
WIPER
D
E
C
O
D
E
REGISTER 2
REGISTER 3
COUNTER
REGISTER
(WCR)
INC/DEC
LOGIC
IF WCR = 00[H] THEN V = V
W
L
H
UP/DN
IF WCR = 3F[H] THEN V = V
W
UP/DN
V
V
L
MODIFIED SCK
CLK
FIGURE 1. DETAILED POTENTIOMETER BLOCK DIAGRAM
W
Write In Process
DEVICE TYPE
IDENTIFIER
The contents of the Data Registers are saved to nonvolatile
memory when the CS pin goes from LOW to HIGH after a
complete write sequence is received by the device. The
progress of this internal write operation can be monitored by a
Write In Process bit (WIP). The WIP bit is read with a Read
Status command.
0
1
0
1
1
1
0
A0
DEVICE ADDRESS
FIGURE 2. ADDRESS/IDENTIFICATION BYTE FORMAT
Instructions
Instruction Byte
Address/Identification (ID) Byte
The next byte sent to the X9421 contains the instruction and
register pointer information. The four most significant bits are
the instruction. The next two bits point to one of four Data
Registers. The format is shown below in Figure 3.
The first byte sent to the X9421 from the host, following a CS
going HIGH to LOW, is called the Address or Identification
byte. The most significant four bits of the slave address are a
device type identifier, for the X9421 this is fixed as 0101[B]
(refer to Figure 2).
REGISTER
SELECT
The least significant bit in the ID byte selects one of two
devices on the bus. The physical device address is defined by
the state of the A input pin. The X9421 compares the serial
I3
I2
I1
I0
R1
R0
0
0
0
data stream with the address input state; a successful compare
of the address bit is required for the X9421 to successfully
INSTRUCTIONS
continue the command sequence. The A input can be actively
0
driven by a CMOS input signal or tied to V
CC
or V .
SS
FIGURE 3. INSTRUCTION BYTE FORMAT
The remaining three bits in the ID byte must be set to 110.
The four high order bits of the instruction byte specify the
operation. The next two bits (R and R ) select one of the four
1
0
registers that is to be acted upon when a register oriented
instruction is issued. The last two bits are defined as 0.
FN8196 Rev.1.00
January 14, 2009
Page 6 of 20
X9421
Two of the eight instructions are two bytes in length and end
with the transmission of the instruction byte. These instructions
are:
or directly between the host and the WCR. These instructions
are:
• Read Wiper Counter Register—read the current wiper
position of the pot,
• XFR Data Register to Wiper Counter Register —This
instruction transfers the contents of one specified Data
Register to the Wiper Counter Register.
• Write Wiper Counter Register—change current wiper
position of the pot,
• XFR Wiper Counter Register to Data Register—This
instruction transfers the contents of the Wiper Counter
Register to the specified associated Data Register.
• Read Data Register—read the contents of the selected data
register;
• Write Data Register—write a new value to the selected data
register.
The basic sequence of the two byte instructions is illustrated in
Figure 4. These two-byte instructions exchange data between
the WCR and one of the Data Registers. A transfer from a Data
Register to a WCR is essentially a write to a static RAM, with the
static RAM controlling the wiper position. The response of the
• Read Status—This command returns the contents of the
WIP bit which indicates if the internal write cycle is in
progress.
wiper to this action will be delayed by t
WCR (current wiper position), to a Data Register is a write to
nonvolatile memory and takes a minimum of t to complete.
The transfer can occur between the potentiometer and one of its
associated registers.
. A transfer from the
The sequence of these operations is shown in Figure 5 and
Figure 6.
WRL
WR
The final command is Increment/Decrement. It is different from
the other commands, because it’s length is indeterminate.
Once the command is issued, the master can clock the wiper
up and/or down in one resistor segment step; thereby,
providing a fine tuning capability to the host. For each SCK
Five instructions require a three-byte sequence to complete.
These instructions transfer data between the host and the
X9421; either between the host and one of the Data Registers
clock pulse (t
) while SI is HIGH, the selected wiper will
HIGH
move one resistor segment towards the V /R terminal.
H
H
Similarly, for each SCK clock pulse while SI is LOW, the
selected wiper will move one resistor segment towards
the V /R terminal. A detailed illustration of the sequence and
L
L
timing for this operation are shown in Figure 7 and 8.
CS
SCK
SI
0
1
0
1
1
1
0
A0 I3
I2
I1 I0
R1 R0
0
0
FIGURE 4. TWO-BYTE INSTRUCTION SEQUENCE
CS
SCL
SI
1
1
0
1
0
1
0
A0
I3 I2
I1 I0
R1 R0
0
0
0
0
D5 D4 D3 D2 D1 D0
FIGURE 5. THREE-BYTE INSTRUCTION SEQUENCE (WRITE)
FN8196 Rev.1.00
January 14, 2009
Page 7 of 20
X9421
CS
SCL
SI
DON’T CARE
1
1
0
1
0
1
0
A0
I3 I2
I1 I0
R1 R0
0
0
S0
0
0
D5 D4 D3 D2 D1 D0
FIGURE 6. THREE-BYTE INSTRUCTION SEQUENCE (READ)
CS
SCK
SI
0
1
0
1
1
1
0
A0
I3
I2
I1 I0
0
0
0
0
I
I
D
E
C
1
I
D
E
C
n
N
C
1
N
C
2
N
C
n
FIGURE 7. INCREMENT/DECREMENT INSTRUCTION SEQUENCE
t
WRID
SCK
SI
VOLTAGE OUT
V
W
INC/DEC CMD ISSUED
FIGURE 8. INCREMENT/DECREMENT TIMING LIMITS
FN8196 Rev.1.00
January 14, 2009
Page 8 of 20
X9421
TABLE 3. INSTRUCTION SET
INSTRUCTION SET
INSTRUCTION
I
I
I
I
R
R
0
OPERATION
3
2
1
0
1
Read Wiper Counter Register
Write Wiper Counter Register
Read Data Register
1
1
1
1
1
0
0
0
1
1
0
1
1
0
0
1
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
Read the contents of the Wiper Counter Register
Write new value to the Wiper Counter Register
0
0
1/0
1/0
1/0
1/0
1/0
1/0
Read the contents of the Data Register pointed to by R - R
1 0
Write Data Register
Write new value to the Data Register pointed to by R - R
1 0
XFR Data Register to Wiper
Counter Register
Transfer the contents of the Data Register pointed to by R -
1
R
to the Wiper Counter Register
0
XFR Wiper CounterRegisterto Data
Register
1
0
0
1
0
1
1
1
0
0
0
1
1/0
0
1/0
0
0
0
0
0
0
1
Transfer the contents of the Wiper Counter
Register to the Data Register pointed to by R - R
1
0
Increment/Decrement Wiper
Counter Register
Enable Increment/decrement of the Wiper Counter Register
Read Status (WIP bit)
0
0
Read the status of the internal write cycle, by checking the WIP
bit.
Instruction Format
NOTES:
1. “A0”: stands for the device addresses sent by the master.
2. WPx refers to wiper position data in the Wiper Counter Register“I”:
stands for the increment operation, SI held HIGH during active
SCK phase (high).
3. “D”: stands for the decrement operation, SI held LOW during active SCK phase (high).
Read Wiper Counter Register (WCR)
DEVICE
TYPE
IDENTIFIER
DEVICE
ADDRESSES
INSTRUCTION
OPCODE
WIPER POSITION
(SENT BY X9421 ON SO)
CS
FALLING
EDGE
CS
RISING
0
1
0
1
1
1
0
A0
1
0
0
1
0
0
0
0
0
0
WP5 WP4 WP3 WP2 WP1 WP0 EDGE
Write Wiper Counter Register (WCR)
DEVICE
TYPE
IDENTIFIER
DEVICE
ADDRESSES
INSTRUCTION
OPCODE
DATA BYTE
(SENT BY HOST ON SI)
CS
FALLING
EDGE
CS
RISING
EDGE
0
1
0
1
1
1
0
A0
1
0
1
0
0
0
0
0
0
0
WP5 WP4 WP3 WP2 WP1 WP0
Read Data Register (DR)
Read the contents of the Register pointed to by R1 - R0.
DEVICE
TYPE
IDENTIFIER
DEVICE
ADDRESSES
INSTRUCTION
OPCODE
REGISTER
ADDRESSES
DATA BYTE
(SENT BY X9421 ON SO)
CS
FALLING
EDGE
CS
RISING
0
1
0
1
1
1
0
A0
1
0
1
1
R1 R0
0
0
0
0
WP5 WP4 WP3 WP2 WP1 WP0 EDGE
Write Data Register (DR)
Write a new value to the Register pointed to by R1 - R0.
DEVICE
TYPE
DEVICE
INSTRUCTION
OPCODE
REGISTER
ADDRESSES
DATA BYTE
(SENT BY HOST ON SI)
IDENTIFIER ADDRESSES
CS
CS
FALLING
EDGE
0
1
0
1
1
1
0
A
0
1
1
0
0
R
1
R
0
0
0
0
0
WP WP WP WP WP WP RISING
EDGE
HIGH-VOLTAGE
WRITE CYCLE
5
4
3
2
1
0
FN8196 Rev.1.00
January 14, 2009
Page 9 of 20
X9421
Transfer Data Register (DR) to Wiper Counter Register (WCR)
Transfer the contents of the Register pointed to by R1 - R0 to the WCR.
DEVICE
TYPE
IDENTIFIER
DEVICE
ADDRESSES
INSTRUCTION
OPCODE
REGISTER
ADDRESSES
CS
FALLING
EDGE
CS
RISING
EDGE
0
1
0
1
1
1
0
A0
1
1
0
1
R1 R0
0
0
Transfer Wiper Counter Register (WCR) to Data Register (DR)
DEVICE
TYPE
IDENTIFIER
DEVICE
ADDRESSES
INSTRUCTION
OPCODE
REGISTER
ADDRESSES
CS
FALLIN
G EDGE
CS
RISING
EDGE
HIGH-VOLTAGE
WRITE CYCLE
0
1
0
1
1
1
0
A0
1
1
1
0
R1 R0
0
0
Increment/Decrement Wiper Counter Register (WCR)
DEVICE TYPE
IDENTIFIER
DEVICE
ADDRESSES
INSTRUCTION
OPCODE
INCREMENT/DECREMENT
(SENT BY MASTER ON SDA)
CS
FALLING
EDGE
CS
RISING
0
1
0
1
1
1
0
A0
0
0
1
0
0
0
0
0
I/D I/D
.
.
.
.
I/D I/D EDGE
Read Status
DEVICE
TYPE
IDENTIFIER
DEVICE
ADDRESSES
INSTRUCTION
OPCODE
DATA BYTE
(SENT BY X9421 ON SO)
CS
CS
FALLING
EDGE
0
1
0
1
1
1
0
A0
0
1
0
1
0
0
0
1
0
0
0
0
0
0
0
W
RISING
IP EDGE
FN8196 Rev.1.00
January 14, 2009
Page 10 of 20
X9421
Absolute Maximum Ratings
Thermal Information
Supply Voltage (V
Limits)
Thermal Resistance (Typical, Note 1)
(°C/W)
JA
CC
X9421. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5V ±10%
X9421-2.7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V to 5.5V
Voltage on SCK, SDA any address input
14 Lead TSSOP. . . . . . . . . . . . . . . . . . . . . . . . . . . .
16 Lead SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Temperature Under Bias . . . . . . . . . . . . . . . . . . . . .-65C to +135C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
92
82
with respect to V : . . . . . . . . . . . . . . . . . . . . . . . . . . . -1V to +7V
SS
V = | (V - V ) | . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5V
H
L
I
(10s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±6mA
W
Any VH/RH, VL/RL, VW/RW . . . . . . . . . . . . . . . . . . . . . VSS to VCC
Operating Conditions
Temperature Range
Commercial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C
Industrial. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTES:
1. is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details
JA
Analog Specifications (Over recommended operating conditions unless otherwise stated.)
LIMITS
MIN.
TYP.
MAX.
SYMBOL
PARAMETER
TEST CONDITIONS
(Note 5)
(Note 6)
(Note 5)
UNITS
Rtotal
End to End Resistance
Tolerance
-20
+20
%
Power Rating
+25°C, each pot
Wiper Current
50
mW
R
Wiper Resistance
150
400
250
W
Iw = (V - V )/R
, V
= 5V
= 3V
H
L
TOTAL CC
Wiper Current
1000
Iw = (V - V )/R
, V
H
L
TOTAL CC
V
Voltage on any V /R , V /R ,
V
= 0V
V
V
CC
V
TERM
H
H
L
L
SS
SS
V
/R
W
W
Noise
Resolution (Note 4)
Ref: 1kHz
(Note 5)
-120
1.6
dBV
%
Absolute Linearity (Note 1)
Relative Linearity (Note 2)
Temperature Coefficient of
V
V
- V
w(n)(expected)
-1
+1
MI (Note 3)
MI (Note 3)
ppm/°C
w(n)(actual)
- [V
]
w(n) + MI
-0.2
+0.2
w(n + 1)
(Note 5)
300
20
R
TOTAL
Ratio metric Temperature
Coefficient
(Note 5)
ppm/°C
pF
C /C /C
Potentiometer Capacitances See “Circuit #3 SPICE Macro Model” on
page 13
10/10/25
0.1
H
L
W
I
Rh, RI, Rw leakage current
VIN = VSS to VCC. Device is in stand-by
mode.
10
µA
AL
FN8196 Rev.1.00
January 14, 2009
Page 11 of 20
X9421
DC Electrical Specifications (Over the recommended operating conditions unless otherwise specified).
LIMITS
MIN
(Note 5)
TYP
(Note 6)
MAX
(Note 5)
SYMBOL
PARAMETER
TEST CONDITIONS
UNITS
I
V
Supply Current
f = 2MHz, SO = Open,
SCK
400
µA
CC1
CC
(Active)
Other Inputs = V
SS
I
V
Supply Current
f
= 2MHz, SO = Open,
3.5
mA
CC2
CC
(Nonvolatile Write)
SCK
Other Inputs = V
SS
I
V
Current (Standby)
CC
SCK = SI = V , Addr. = V
SS SS
3
µA
µA
µA
V
SB
I
Input Leakage Current
Output Leakage Current
Input HIGH Voltage
Input LOW Voltage
V
V
= V to V
SS CC
10
10
LI
IN
I
= V to V
SS CC
LO
OUT
V
V
x 0.7
V
CC
+ 0.3
x 0.1
IH
CC
V
-0.5
V
V
IL
CC
V
Output LOW Voltage
I
= 3mA
OL
0.4
V
OL
ENDURANCE AND DATA RETENTION
PARAMETER
Minimum Endurance
Data Retention
MIN
UNITS
100,000
100
Data Changes per Bit per Register
Years
CAPACITANCE
SYMBOL
(Note 5) Output Capacitance (SO)
TEST
TYP
8
UNITS
pF
TEST CONDITIONS
= 0V
C
V
OUT
OUT
V = 0V
IN
C
(Note 5)
Input Capacitance (A0, SI, and SCK)
6
pF
IN
POWER-UP TIMING
SYMBOL
PARAMETER
Power-up Ramp
CC
MIN
0.2
MAX
UNITS
t V (Note 5)
CC
V
50
V/msec
R
NOTES:
1. Absolute Linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used as a
potentiometer.
2. Relative Linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a
potentiometer. It is a measure of the error in step size.
3. MI = RTOT/63 or (V - V )/63, single pot
H
L
4. Typical = Individual array resolution.
5. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
6. Limits should be considered typical and are not production tested.
7. This parameter is not production tested. Parameter established by characterization.
more than 0.5V. Recall of wiper position will not be complete
until V reaches its final value.
Power-up Requirements
CC
(Power-up sequencing can affect correct recall of the wiper
registers) The preferred power-on sequence is as follows: First
V
and then the potentiometer pins, R , R , and R . Voltage
CC
H L W
should not be applied to the potentiometer pins before V
is
CC
ramp rate specification should be met, and
applied. The V
CC
any glitches or slope changes in the V
line should be held to
CC
should not reverse polarity by
<100mV if possible. Also, V
CC
FN8196 Rev.1.00
January 14, 2009
Page 12 of 20
X9421
AC Test Conditions
Input pulse levels
V
x 0.1 to V
x 0.5
x 0.9
CC
CC
Input rise and fall times
Input and output timing level
10ns
V
CC
Equivalent AC Load Circuit
5V
2.7V
1533
SDA Output
100pF
100pF
Circuit #3 SPICE Macro Model
R
TOTAL
R
R
L
H
C
L
C
H
C
W
10pF
10pF
25pF
R
W
FN8196 Rev.1.00
January 14, 2009
Page 13 of 20
X9421
AC Timing
SYMBOL
MIN
(Note 5)
TYP
(Note 6)
MAX
(Note 5)
PARAMETER
UNITS
MHz
ns
f
SSI/SPI Clock Frequency
SSI/SPI Clock Cycle Time
SSI/SPI Clock High Time
SSI/SPI Clock Low Time
Lead Time
2.0
SCK
CYC
t
500
200
200
250
250
50
t
ns
WH
t
ns
WL
t
ns
LEAD
t
Lag Time
ns
LAG
t
SI, SCK, HOLD and CS Input Setup Time
SI, SCK, HOLD and CS Input Hold Time
SI, SCK, HOLD and CS Input Rise Time
SI, SCK, HOLD and CS Input Fall Time
SO Output Disable Time
ns
SU
t
50
ns
H
(7)
t
t
2
µs
µs
ns
RI
(7)
FI
2
t
0
0
500
150
DIS
t
SO Output Valid Time
ns
V
t
SO Output Hold Time
ns
HO
RO
t
SO Output Rise Time
50
50
ns
t
SO Output Fall Time
ns
FO
t
HOLD Time
400
100
100
ns
HOLD
t
HOLD Setup Time
ns
HSU
t
HOLD Hold Time
ns
HH
t
HOLD Low to Output in High Z
HOLD High to Output in Low Z
Noise Suppression Time Constant at SI, SCK, HOLD and CS inputs
CS Deselect Time
100
100
20
ns
HZ
t
ns
LZ
T
ns
I
t
2
0
0
µs
ns
CS
t
WP, A0 and A1 Setup Time
WP, A0 and A1 Hold Time
WPASU
t
ns
WPAH
High-Voltage Write Cycle Timing
TYP
MAX
SYMBOL
PARAMETER
High-voltage Write Cycle Time (Store Instructions)
(NOTE 6)
(NOTE 5)
UNITS
t
5
10
ms
WR
XDCP Timing
MIN
MAX
SYMBOL
PARAMETER
(NOTE 5) (NOTE 5) UNITS
t
Wiper Response Time After The Power Supply Is Stable
10
10
10
µs
µs
µs
WRPO
t
Wiper Response Time After Instruction Issued (All Load Instructions)
WRL
t
Wiper Response Time From An Active SCL/SCK Edge (Increment/Decrement Instruction)
WRID
FN8196 Rev.1.00
January 14, 2009
Page 14 of 20
X9421
Symbol Table
WAVEFORM
INPUTS
OUTPUTS
MUST BE
STEADY
WILL BE
STEADY
MAY CHANGE
WILL CHANGE
FROM LOW TO FROM LWO TO
HIGH
HIGH
MAY CHANGE
WILL CHANGE
FROM HIGH TO FROM HIGH TO
LOW
LOW
DON’T CARE:
CHANGES
ALLOWED
CHANGING:
STATE NOT
KNOWN
N/A
CENTER LINE
IS HIGH
IMPEDANCE
Timing Diagrams
Input Timing
t
CS
CS
t
t
t
LAG
LEAD
CYC
SCK
...
t
t
t
RI
FI
t
t
WH
t
WL
SU
H
...
MSB
LSB
SI
HIGH IMPEDANCE
SO
Output Timing
CS
SCK
SO
SI
...
...
t
t
t
DIS
V
HO
MSB
LSB
ADDR
FN8196 Rev.1.00
January 14, 2009
Page 15 of 20
X9421
Hold Timing
CS
t
t
HH
HSU
SCK
SO
...
t
t
FO
RO
t
t
LZ
HZ
SI
t
HOLD
HOLD
XDCP Timing (for All Load Instructions)
CS
SCK
...
...
t
WRL
MSB
LSB
SI
V
W
HIGH IMPEDANCE
SO
XDCP Timing (for Increment/Decrement Instruction)
CS
SCK
...
t
WRID
...
V
W
...
ADDR
INC/DEC
SI
INC/DEC
HIGH IMPEDANCE
SO
FN8196 Rev.1.00
January 14, 2009
Page 16 of 20
X9421
Write Protect and Device Address Pins Timing
(ANY INSTRUCTION)
CS
t
t
WPAH
WPASU
WP
A0
A1
2. The flexibility of computer-based digital controls)
Applications information
1. Electronic potentiometers provide three powerful
application advantages: The variability and reliability of a
solid-state potentiometer,
3. the retentivity of nonvolatile memory used for the storage of
multiple potentiometer settings or data.
Basic Configurations of Electronic Potentiometers
V
R
V
R
V
H
V
W
V
L
I
THREE TERMINAL POTENTIOMETER;
VARIABLE VOLTAGE DIVIDER
TWO TERMINAL VARIABLE RESISTOR;
VARIABLE CURRENT
FN8196 Rev.1.00
January 14, 2009
Page 17 of 20
X9421
Application Circuits
BUFFERED REFERENCE VOLTAGE
CASCADING TECHNIQUES
NONINVERTING AMPLIFIER
R
+5V
1
+V
+V
+V
LM308A
V
+
–
S
+5V
-5V
V
O
X
V
W
OP-07
+
–
V
-5V
W
V
= V
W
OUT
V
W
R
2
+V
R
1
V
W
V
= (1+R /R )V
2 1 S
O
(a)
(b)
OFFSET VOLTAGE ADJUSTMENT
COMPARATOR WITH HYSTERITISIS
VOLTAGE REGULATOR
317
R
R
2
1
V
–
+
S
V
V (REG)
O
IN
V
V
S
O
100k
R
1
–
+
V
O
I
adj
TL072
R
R
1
2
R
2
10k
10k
V
V
= {R /CR +R } V (max)
1 1 2 O
UL
LL
10k
= {R /CR +R } V (min)
1
1
2
O
V
(REG) = 1.25V (1+R /R )+I R
adj 2
O
2
1
+12V
-12V
FN8196 Rev.1.00
January 14, 2009
Page 18 of 20
X9421
Thin Shrink Small Outline Plastic Packages (TSSOP)
N
M14.173
INDEX
AREA
0.25(0.010)
M
B M
E
14 LEAD THIN SHRINK SMALL OUTLINE PLASTIC PACKAGE
INCHES MILLIMETERS
MIN
E1
-B-
GAUGE
PLANE
SYMBOL
MAX
0.047
0.006
0.041
0.0118
0.0079
0.199
0.177
MIN
-
MAX
1.20
0.15
1.05
0.30
0.20
5.05
4.50
NOTES
A
A1
A2
b
-
-
1
2
3
0.002
0.031
0.0075
0.0035
0.195
0.169
0.05
0.80
0.19
0.09
4.95
4.30
-
L
0.25
0.010
-
0.05(0.002)
SEATING PLANE
A
9
-A-
D
c
-
D
3
-C-
E1
e
4
A2
e
A1
0.026 BSC
0.65 BSC
-
c
b
0.10(0.004)
E
0.246
0.256
6.25
0.45
6.50
0.75
-
0.10(0.004) M
C
A M B S
L
0.0177
0.0295
6
N
14
14
7
NOTES:
o
o
o
o
0
8
0
8
-
1. These package dimensions are within allowable dimensions of
JEDEC MO-153-AC, Issue E.
Rev. 2 4/06
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm
(0.006 inch) per side.
4. Dimension “E1” does not include interlead flash or protrusions. Inter-
lead flash and protrusions shall not exceed 0.15mm (0.006 inch) per
side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “b” does not include dambar protrusion. Allowable dambar
protrusion shall be 0.08mm (0.003 inch) total in excess of “b” dimen-
sion at maximum material condition. Minimum space between protru-
sion and adjacent lead is 0.07mm (0.0027 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact. (Angles in degrees)
FN8196 Rev.1.00
January 14, 2009
Page 19 of 20
X9421
Small Outline Plastic Packages (SOIC)
M16.3 (JEDEC MS-013-AA ISSUE C)
N
16 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE
INDEX
AREA
0.25(0.010)
M
B M
H
INCHES
MILLIMETERS
E
SYMBOL
MIN
MAX
MIN
2.35
0.10
0.33
0.23
10.10
7.40
MAX
2.65
NOTES
-B-
A
A1
B
C
D
E
e
0.0926
0.0040
0.013
0.1043
0.0118
0.0200
0.0125
0.4133
0.2992
-
0.30
-
1
2
3
L
0.51
9
SEATING PLANE
A
0.0091
0.3977
0.2914
0.32
-
-A-
10.50
7.60
3
h x 45°
D
4
-C-
0.050 BSC
1.27 BSC
-
H
h
0.394
0.010
0.016
0.419
0.029
0.050
10.00
0.25
0.40
10.65
0.75
1.27
-
e
A1
C
5
B
0.10(0.004)
L
6
0.25(0.010) M
C
A M B S
N
16
16
7
0°
8°
0°
8°
-
NOTES:
Rev. 1 6/05
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Interlead
flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above
the seating plane, shall not exceed a maximum value of 0.61mm (0.024
inch)
10. Controlling dimension: MILLIMETER. Converted inch dimensions are
not necessarily exact.
© Copyright Intersil Americas LLC 2005-2009. All Rights Reserved.
All trademarks and registered trademarks are the property of their respective owners.
For additional products, see www.intersil.com/en/products.html
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such
modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are
current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its
subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN8196 Rev.1.00
January 14, 2009
Page 20 of 20
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