X9429WV14IZ [RENESAS]
Single Digitally Controlled Potentiometer (XDCP™); SOIC16, TSSOP14; Temp Range: See Datasheet;
| 型号： | X9429WV14IZ |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | Single Digitally Controlled Potentiometer (XDCP™); SOIC16, TSSOP14; Temp Range: See Datasheet 光电二极管 转换器 电阻器 |
| 文件： | 总21页 (文件大小：827K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATASHEET
X9429
FN8248
Rev 4.00
October 16, 2015
Low Noise/Low Power/2-Wire Bus Single Digitally Controlled Potentiometer
(XDCP™)
The X9429 integrates a single digitally controlled
potentiometer (XDCP) on a monolithic CMOS integrated
Features
• Single Voltage Potentiometer
• 64 Resistor Taps
circuit.
The digital controlled potentiometer is implemented using 63
resistive elements in a series array. Between each element
are tap points connected to the wiper terminal through
switches. The position of the wiper on the array is controlled
by the user through the 2-wire bus interface. The
potentiometer has associated with it a volatile Wiper Counter
Register (WCR) and a four non-volatile Data Registers that
can be directly written to and read by the user. The contents
of the WCR controls the position of the wiper on the resistor
array though the switches. Power-up recalls the contents of
the default data register (DR0) to the WCR.
• 2-wire Serial Interface for Write, Read, and Transfer
Operations of the Potentiometer
• Wiper Resistance, 150W Typical at 5V
• Non-Volatile Storage of Multiple Wiper Positions
• Power-on Recall. Loads Saved Wiper Position on Power-up.
• Standby Current < 3µA Max
• VCC : 2.7V to 5.5V Operation
• 2.5kW, 10kW Total Pot Resistance
• Endurance: 100,000 Data Changes per Bit per Register
• 100 yr. Data Retention
The XDCP can be used as a three-terminal potentiometer or
as a two terminal variable resistor in a wide variety of
applications including control, parameter adjustments, and
signal processing.
• 14 Ld TSSOP, 16 Ld SOIC
• Low Power CMOS
• Pb-free available (RoHS compliant)
Block Diagram
V
V /R
H
CC
H
WRITE
READ
TRANSFER
INC/DEC
ADDRESS
DATA
STATUS
10k
64-TAPS
POT
POWER-ON RECALL
WIPER
BUS
INTERFACE
AND
WIPER COUNTER
REGISTER (WCR)
2-WIRE
BUS
INTERFACE
CONTROL
DATA REGISTERS
4 BYTES
CONTROL
V
V /R
V
/R
SS
L
L
W
W
FN8248 Rev 4.00
October 16, 2015
Page 1 of 21
X9429
Ordering Information
POTENTIOMETER
ORGANIZATION
(kΩ)
PART
NUMBER
PART
MARKING
VCC LIMITS
(V)
TEMP
RANGE (°C)
PACKAGE
(RoHS Compliant)
PKG
DWG. #
X9429WS16Z* (Note)
(No longer available,
recommended replacement:
X9429WS16IZT1)
X9429WS Z
5 ±10%
10
0 to +70
16 Ld SOIC (300 mil)
M16.3
X9429WS16IZ* (Note)
X9429WV14Z* (Note)
X9429WV14IZ* (Note)
X9429WS Z I
X9429 WV Z
X9429 WV Z I
X9429WS ZF
-40 to +85
0 to +70
16 Ld SOIC (300 mil)
M16.3
14 Ld TSSOP (4.4mm) M14.173
14 Ld TSSOP (4.4mm) M14.173
-40 to +85
0 to +70
X9429WS16Z-2.7* (Note)
(No longer available,
recommended replacement:
X9429WS16IZT1)
2.7 to 5.5
10
16 Ld SOIC (300 mil)
M16.3
X9429WS16IZ-2.7* (Note)
(No longer available,
recommended replacement:
X9429WS16IZT1)
X9429WS ZG
-40 to +85
16 Ld SOIC (300 mil)
M16.3
X9429WV14Z-2.7* (Note)
X9429WV14IZ-2.7* (Note)
X9429 WVZF
X9429 WVZ G
0 to +70
14 Ld TSSOP (4.4mm) M14.173
14 Ld TSSOP (4.4mm) M14.173
-40 to +85
*Add “T1” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100%
matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
FN8248 Rev 4.00
October 16, 2015
Page 2 of 21
X9429
Detailed Functional Diagram
V
CC
POWER-ON RECALL
DR0 DR1
10k
64--TAPS
R /V
H
H
WIPER
COUNTER
REGISTER
(WCR)
CONTROL
R /V
DR2 DR3
L
L
SCL
SDA
A3
INTERFACE
AND
CONTROL
CIRCUITRY
R
/V
W
W
A2
A0
DATA
WP
V
SS
Circuit Level Applications
System Level Applications
• Vary the Gain of a Voltage Amplifier
• Adjust the Contrast in LCD Displays
• Provide Programmable DC Reference Voltages for
Comparators and Detectors
• Control the Power Level of LED Transmitters in
Communication Systems
• Control the Volume in Audio Circuits
• Set and Regulate the DC Biasing Point in an RF Power
Amplifier in Wireless Systems
• Trim Out the Offset Voltage Error in a Voltage Amplifier
Circuit
• Control the Gain in Audio and Home Entertainment Systems
• Set the Output Voltage of a Voltage Regulator
• Trim the Resistance in Wheatstone Bridge Circuits
• Provide the Variable DC Bias for Tuners in RF Wireless
Systems
• Set the Operating Points in Temperature Control Systems
• Control the Gain, Characteristic Frequency and
Q-factor in Filter Circuits
• Control the Operating Point for Sensors in Industrial
Systems
• Set the Scale Factor and Zero Point in Sensor Signal
Conditioning Circuits
• Trim Offset and Gain Errors in Artificial Intelligent Systems
• Vary the Frequency and Duty Cycle of Timer ICs
• Vary the DC Biasing of a Pin Diode Attenuator in RF Circuits
• Provide a Control Variable (I, V, or R) in Feedback Circuits
FN8248 Rev 4.00
October 16, 2015
Page 3 of 21
X9429
Pinouts
X9429
X9429
(14 LD TSSOP)
TOP VIEW
(16 LD SOIC)
TOP VIEW
NC
NC
V
V
CC
14
13
12
11
10
9
1
2
3
4
5
6
7
CC
1
2
3
4
5
6
7
8
16
15
14
NC
NC
R /V
NC
R /V
L
L
NC
R /V
L
L
NC
H
H
R /V
H
A2
13
H
R
/V
W
A2
W
X9429
X9429
R
/V
W
SCL
SDA
NC
12
11
10
9
W
SCL
SDA
VSS
A3
A0
A3
A0
8
WP
VSS
WP
Pin Assignments
TSSOP PIN
SOIC PIN
12, 3, 7, 15
SYMBOL
NC
BRIEF DESCRIPTION
1, 2, 3
4
No Connect
4
5
A2
Device Address for 2-wire bus.
Serial Clock for 2-wire bus.
5
SCL
SDA
VSS
6
6
Serial Data Input/Output for 2-wire bus.
System Ground
7
8
8
9
WP
Hardware Write Protect
9
10
11
12
13
14
16
A0
Device Address for 2-wire bus.
Device Address for 2-wire bus.
Wiper Terminal of the Potentiometer.
High Terminal of the Potentiometer.
Low Terminal of the Potentiometer.
System Supply Voltage
10
11
12
13
14
A3
RW/VW
RH/VH
RL/VL
VCC
Potentiometer Pins
Pin Descriptions
Host Interface Pins
SERIAL CLOCK (SCL)
RH/VH, RL/VL
The RH/VH and RL/VL inputs are equivalent to the terminal
connections on either end of a mechanical potentiometer.
The SCL input is used to clock data into and out of the X9429.
RW/VW
SERIAL DATA (SDA)
The wiper outputs are equivalent to the wiper output of a
mechanical potentiometer.
SDA is a bidirectional pin used to transfer data into and out of
the device. It is an open drain output and may be wire-ORed
with any number of open drain or open collector outputs. An
open drain output requires the use of a pull-up resistor. For
selecting typical values, refer to the guidelines for calculating
typical values on the bus pull-up resistors graph.
HARDWARE WRITE PROTECT INPUT WP
The WP pin when low prevents nonvolatile writes to the Data
Registers.
Principals of Operation
DEVICE ADDRESS (A0, A2, A3)
The X9429 is a highly integrated microcircuit incorporating a
resistor array and its associated registers and counters and the
serial interface logic providing direct communication between
the host and the XDCP potentiometers.
The Address inputs are used to set the least significant 3 bits
of the 8-bit slave address. A match in the slave address serial
data stream must be made with the Address input in order to
initiate communication with the X9429. A maximum of 8
devices may occupy the 2-wire serial bus.
Serial Interface
The X9429 supports a bidirectional bus oriented protocol. The
protocol defines any device that sends data onto the bus as a
FN8248 Rev 4.00
October 16, 2015
Page 4 of 21
X9429
transmitter and the receiving device as the receiver. The
device controlling the transfer is a master and the device being
controlled is the slave. The master will always initiate data
transfers and provide the clock for both transmit and receive
operations. Therefore, the X9429 will be considered a slave
device in all applications.
Device Addressing
Following a start condition, the master must output the address
of the slave it is accessing. The most significant four bits of the
slave address are the device type identifier (refer to Figure 1).
For the X9429 this is fixed as 0101[B].
DEVICE TYPE
IDENTIFIER
Clock and Data Conventions
Data states on the SDA line can change only during SCL LOW
periods (tLOW). SDA state changes during SCL HIGH are
reserved for indicating start and stop conditions.
0
1
0
1
A3
A2
0
A0
Start Condition
DEVICE ADDRESS
All commands to the X9429 are preceded by the start
condition, which is a HIGH to LOW transition of SDA while SCL
is HIGH (tHIGH). The X9429 continuously monitors the SDA
and SCL lines for the start condition and will not respond to any
command until this condition is met.
FIGURE 1. SLAVE ADDRESS
The next four bits of the slave address are the device address.
The physical device address is defined by the state of the A0,
A2, and A3 inputs. The X9429 compares the serial data stream
with the address input state; a successful compare of all three
address bits is required for the X9429 to respond with an
acknowledge. The A0, A2, and A3 inputs can be actively driven
Stop Condition
All communications must be terminated by a stop condition,
which is a LOW-to-HIGH transition of SDA while SCL is HIGH.
Acknowledge
by CMOS input signals or tied to VCC or VSS
.
Acknowledge is a software convention used to provide a
positive handshake between the master and slave devices on
the bus to indicate the successful receipt of data. The
transmitting device, either the master or the slave, will release
the SDA bus after transmitting eight bits. The master generates
a ninth clock cycle and during this period, the receiver pulls the
SDA line LOW to acknowledge that it successfully received the
eight bits of data.
Acknowledge Polling
The disabling of the inputs, during the internal non-volatile
write operation, can be used to take advantage of the typical
5ms EEPROM write cycle time. Once the stop condition is
issued to indicate the end of the non-volatile write command,
the X9429 initiates the internal write cycle. ACK polling can be
initiated immediately. This involves issuing the start condition
followed by the device slave address. If the X9429 is still busy
with the write operation, no ACK will be returned. If the X9429
has completed the write operation, an ACK will be returned,
and the master can then proceed with the next operation.
The X9429 will respond with an acknowledge after recognition
of a start condition and its slave address and once again after
successful receipt of the command byte. If the command is
followed by a data byte the X9429 will respond with a final
acknowledge.
Instruction Structure
The next byte sent to the X9429 contains the instruction and
register pointer information. The four most significant bits are
the instruction. The next four bits point to one of four
associated registers. The format is shown in Figure 2.
Array Description
The X9429 is comprised of a resistor array. The array contains
63 discrete resistive segments that are connected in series.
The physical ends of the array are equivalent to the fixed
terminals of a mechanical potentiometer (VH/RH and VL/RL
inputs).
REGISTER
SELECT
At both ends of the array and between each resistor segment
is a CMOS switch connected to the wiper (VW/RW) output.
Within each individual array only one switch may be turned on
at a time. These switches are controlled by the Wiper Counter
Register (WCR). The six bits of the WCR are decoded to
select, and enable, one of sixty-four switches.
I3
I2
I1
I0
R1
R0
0
0
INSTRUCTIONS
FIGURE 2. INSTRUCTION BYTE FORMAT
The WCR may be written directly, or it can be changed by
transferring the contents of one of four associated Data
Registers into the WCR. These Data Registers and the WCR
can be read and written by the host system.
The four high order bits define the instruction. The next two bits
(R1 and R0) select one of the four registers that is to be acted
upon when a register oriented instruction is issued. Bits 0 and
1 are defined to be 0.
FN8248 Rev 4.00
October 16, 2015
Page 5 of 21
X9429
Four of the seven instructions end with the transmission of the
instruction byte. The basic sequence is illustrated in Figure 3.
These two-byte instructions exchange data between the Wiper
Counter Register and one of the Data Registers. A transfer
from a Data Register to a Wiper Counter Register is essentially
a write to a static RAM. The response of the wiper to this action
will be delayed tWRL. A transfer from the Wiper Counter
Register (current wiper position), to a Data Register is a write
to non-volatile memory and takes a minimum of tWR to
complete.
Flow 1. ACK Polling Sequence
NON-VOLATILE WRITE
COMMAND COMPLETED
ENTER ACK POLLING
ISSUE
START
Four instructions require a three-byte sequence to complete.
These instructions transfer data between the host and the
X9429; either between the host and one of the Data Registers or
directly between the host and the Wiper Counter Register.
These instructions are:
ISSUE SLAVE
ADDRESS
ISSUE STOP
ACK
NO
RETURNED?
YES
NO
FURTHER
OPERATION?
YES
ISSUE
INSTRUCTION
ISSUE STOP
PROCEED
PROCEED
SCL
SDA
S
T
A
R
T
0
1
0
1
A3 A2
0
A0
A
C
K
I3
I2
I1 I0
R1 R0
0
0
A
C
K
S
T
O
P
FIGURE 3. TWO-BYTE INSTRUCTION SEQUENCE
FN8248 Rev 4.00
October 16, 2015
Page 6 of 21
X9429
TABLE 1. INSTRUCTION SET
INSTRUCTION SET
INSTRUCTION
I3
1
1
1
1
1
I2
0
0
0
1
1
I1
0
1
1
0
0
I0
1
0
1
0
1
R1
0
R0
0
X1
0
X0
0
OPERATION
Read Wiper Counter Register
Write Wiper Counter Register
Read Data Register
Read the contents of the Wiper Counter Register
Write new value to the Wiper Counter Register
Read the contents of the Data Register pointed to by R1 - R0
Write new value to the Data Register pointed to by R1 - R0
0
0
0
0
1/0 1/0
1/0 1/0
1/0 1/0
0
0
Write Data Register
0
0
XFR Data Register to Wiper
Counter Register
0
0
Transfer the contents of the Data Register pointed to by R1 - R0
to its Wiper Counter Register
XFR Wiper Counter
Register to Data Register
1
0
1
0
1
1
0
0
1/0 1/0
0
0
0
0
Transfer the contents of the Wiper Counter Register to the Data
Register pointed to by R1 - R0
Increment/Decrement Wiper
Counter Register
0
0
Enable Increment/decrement of the Wiper Counter Register
Read Wiper Counter Register (read the current wiper position
of the selected pot), write Wiper Counter Register (change
current wiper position of the selected pot), read Data Register
(read the contents of the selected nonvolatile register) and
write Data Register (write a new value to the selected Data
Register). The sequence of operations is shown in Figure 4.
selected wiper up and/or down in one segment steps; thereby,
providing a fine tuning capability to the host. For each SCL
clock pulse (tHIGH) while SDA is HIGH, the selected wiper will
move one resistor segment towards the VH/RH terminal.
Similarly, for each SCL clock pulse while SDA is LOW, the
selected wiper will move one resistor segment towards the
VL/RL terminal. A detailed illustration of the sequence and
timing for this operation are shown in Figures 5 and 6
respectively.
The Increment/Decrement command is different from the other
commands. Once the command is issued and the X9429 has
responded with an acknowledge, the master can clock the
NOTE: (1)1/0 = data is one or zero
SCL
SDA
S
T
A
R
T
0
1
0
1
A3 A2
0
A0
A
C
K
I3 I2
I1 I0
R1 R0
0
0
A
C
K
0
0
D5 D4 D3 D2 D1 D0
A
C
K
S
T
O
P
FIGURE 4. THREE-BYTE INSTRUCTION SEQUENCE
SCL
SDA
S
T
A
R
T
0
1
0
1
A3 A2
0
A0
A
C
K
I3
I2
I1 I0
R1 R0
0
0
A
C
K
I
I
D
E
C
1
S
T
O
P
I
D
N
C
1
N
C
2
N
C
n
E
C
n
FIGURE 5. INCREMENT/DECREMENT INSTRUCTION SEQUENCE
FN8248 Rev 4.00
October 16, 2015
Page 7 of 21
X9429
INC/DEC
CMD
ISSUED
T
WRID
SCL
SDA
VOLTAGE OUT
V
/R
W
W
FIGURE 6. INCREMENT/DECREMENT TIMING LIMITS
SCL FROM
MASTER
1
8
9
DATA OUTPUT
FROM TRANSMITTER
DATA OUTPUT
FROM RECEIVER
START
ACKNOWLEDGE
FIGURE 7. ACKNOWLEDGE RESPONSE FROM RECEIVER
FN8248 Rev 4.00
October 16, 2015
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X9429
SERIAL DATA PATH
SERIAL
BUS
V /R
H H
FROM INTERFACE
CIRCUITRY
INPUT
C
O
U
N
T
REGISTER 0
REGISTER 1
8
6
PARALLEL
BUS
E
R
INPUT
WIPER
D
E
C
O
D
E
REGISTER 2
REGISTER 3
COUNTER
REGISTER
(WCR)
INC/DEC
LOGIC
IF WCR = 00[H] THEN V /R = V /R
L
W
W
L
UP/DN
UP/DN
IF WCR = 3F[H] THEN V /R = V /R
H
W
W
H
V /R
MODIFIED SCL
L
L
CLK
V
/R
W
W
FIGURE 8. DETAILED POTENTIOMETER BLOCK DIAGRAM
Wiper Counter Register. It should be noted all operations
changing data in one of these registers is a nonvolatile
operation and will take a maximum of 10ms.
Detailed Operation
The potentiometer has a Wiper Counter Register and four Data
Registers. A detailed discussion of the register organization
and array operation follows.
If the application does not require storage of multiple settings
for the potentiometer, these registers can be used as regular
memory locations that could possibly store system parameters
or user preference data.
Wiper Counter Register
The X9429 contains a Wiper Counter Register. The Wiper
Counter Register can be envisioned as a 6-bit parallel and
serial load counter with its outputs decoded to select one of
sixty-four switches along its resistor array. The contents of the
WCR can be altered in four ways: it may be written directly by
the host via the write Wiper Counter Register instruction (serial
load); it may be written indirectly by transferring the contents of
one of four associated Data Registers via the XFR Data
Register instruction (parallel load); it can be modified one step
at a time by the Increment/Decrement instruction. Finally, it is
loaded with the contents of its Data Register zero (DR0) upon
power-up.
Register Descriptions
DATA REGISTERS, (6-BIT), NON-VOLATILE
D5
NV
D4
D3
D2
D1
D0
NV
NV
NV
NV
NV
(MSB)
(LSB)
FOUR 6-BIT DATA REGISTERS FOR EACH XDCP.
{D5~D0}: These bits are for general purpose not volatile data
storage or for storage of up to four different wiper values. The
contents of Data Register 0 are automatically moved to the
Wiper Counter Register on power-up.
The WCR is a volatile register; that is, its contents are lost
when the X9429 is powered-down. Although the register is
automatically loaded with the value in DR0 upon power-up, it
should be noted this may be different from the value present at
power-down.
WIPER COUNTER REGISTER, (6-BIT), VOLATILE
WP5
V
WP4
WP3
WP2
WP1
WP0
V
V
V
V
V
Data Registers
(MSB)
(LSB)
The potentiometer has four nonvolatile Data Registers. These
can be read or written directly by the host and data can be
transferred between any of the four Data Registers and the
FN8248 Rev 4.00
October 16, 2015
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X9429
ONE 6-BIT WIPER COUNTER REGISTER FOR EACH XDCP.
power-up by the value in Data Register 0. The contents of the
WCR can be loaded from any of the other Data Register or
directly. The contents of the WCR can be saved in a DR.
{D5~D0}: These bits specify the wiper position of the
respective XDCP. The Wiper Counter Register is loaded on
Instruction Format
NOTES:
1. “MACK”/”SACK”: stands for the acknowledge sent by the master/slave.
2. A3 ~ A0”: stands for the device addresses sent by the master.
3. X”: indicates that it is a “0” for testing purpose but physically it is a “don’t care” condition.
4. “I”: stands for the increment operation, SDA held high during active
SCL phase (high).
5. “D”: stands for the decrement operation, SDA held low during active SCL phase (high).
Read Wiper Counter Register (WCR)
DEVICE
TYPE
DEVICE
INSTRUCTION
OPCODE
WIPER POSITION
(SENT BY SLAVE ON SDA)
S
T
A
R
T
IDENTIFIER ADDRESSES
S
A
C
K
S
A
C
K
M
A
C
K
S
T
O
P
0
1
0
1
A
3
A
2
0
A
0
1
0
0
1
0
0
0
0
0
0
W
P
5
W
P
4
W
P
3
W
P
2
W
P
1
W
P
0
Write Wiper Counter Register (WCR)
DEVICE
TYPE
DEVICE
INSTRUCTION
OPCODE
WIPER POSITION
(SENT BY MASTER ON SDA)
S
T
A
R
T
IDENTIFIER ADDRESSES
S
A
C
K
S
A
C
K
S
A
C
K
S
T
O
P
0
1
0
1
A
3
A
2
0
A
0
1
0
1
0
0
0
0
0
0
0
W
P
5
W
P
4
W
P
3
W
P
2
W
P
1
W
P
0
Read Data Register (DR)
DEVICE
TYPE
DEVICE
INSTRUCTION REGISTER
OPCODE ADDRESSES
WIPER POSITION/DATA
(SENT BY SLAVE ON SDA)
S
T
A
R
T
IDENTIFIER ADDRESSES
S
A
C
K
S
M
S
0
1
0
1
A
3
A
2
0
A
0
1
0
1
1
R
1
R
0
0
0
A
C
K
0
0
W
P
5
W
P
4
W
P
3
W
P
2
W
P
1
W
P
0
A
C
K
T
O
P
Write Data Register (DR)
DEVICE
TYPE
IDENTIFIER ADDRESSES
WIPER POSITION/DATA
(SENT BY MASTER ON
SDA)
HIGH-VOLTAGE
WRITE CYCLE
DEVICE
INSTRUCTION REGISTER
OPCODE ADDRESSES
S
T
A
R
T
S
A
C
K
S
A
C
K
S
S
0
1
0
1
A
3
A
2
0
A
0
1
1
0
0
R
1
R
0
0
0
0
0
W
P
5
W W
W
P
2
W
P
1
W
A
C
K
T
O
P
P
4
P
3
P
0
FN8248 Rev 4.00
October 16, 2015
Page 10 of 21
X9429
XFR Data Register (DR) to Wiper Counter Register (WCR)
DEVICE
TYPE
IDENTIFIER ADDRESSES
S
DEVICE
INSTRUCTION
OPCODE
REGISTER
ADDRESSES
T
A
R
T
S
A
C
K
S
A
C
K
S
T
O
P
0
1
0
1
A
3
A
2
0
A
0
1
1
0
1
R
1
R
0
0
0
XFR Wiper Counter Register (WCR) to Data Register (DR)
DEVICE
TYPE
IDENTIFIER ADDRESSES
HIGH-VOLTAGE
WRITE CYCLE
S
DEVICE
INSTRUCTION REGISTER
T
A
R
T
S
A
C
K
S
A
C
K
S
OPCODE
ADDRESSES
T
O
P
0
1
0
1
A
3
A
2
0
A
0
1
1
1
0
R
1
R
0
0
0
Increment/Decrement Wiper Counter Register (WCR)
S
T
A
R
T
DEVICE TYPE
IDENTIFIER
DEVICE
ADDRESSES
INSTRUCTION
OPCODE
INCREMENT/DECREMENT
(SENT BY MASTER ON SDA)
S
A
C
K
S
A
C
K
S
T
O
P
0
1
0
1
A3 A2
0
A0
0
0
1
0
0
0
0
0
I/ I/ I/ I/
.
.
.
.
D
D
D
D
Symbol Table
WAVEFORM
INPUTS
OUTPUTS
MUST BE
STEADY
WILL BE
STEADY
MAY CHANGE
WILL CHANGE
FROM LOW TO FROM LOW TO
HIGH
HIGH
MAY CHANGE
WILL CHANGE
FROM HIGH TO FROM HIGH TO
LOW
LOW
DON’T CARE:
CHANGES
ALLOWED
CHANGING:
STATE NOT
KNOWN
N/A
CENTER LINE
IS HIGH
IMPEDANCE
Guidelines for Calculating Typical Values of Bus
Pull-Up Resistors
120
VCC MAX
IOL MIN
RMIN
=
=1.8kW
100
80
TR
RMAX
=
CBUS
MAX.
60
40
20
0
RESISTANCE
MIN.
RESISTANCE
0
20 40 60 80 100 120
BUS CAPACITANCE (PF)
FN8248 Rev 4.00
October 16, 2015
Page 11 of 21
X9429
Absolute Maximum Ratings
Thermal Information
Supply Voltage (VCC Limits)
Thermal Resistance (Typical, Note 1)
JA (°C/W)
X9429. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5V ±10%
X9429-2.7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V to 5.5V
Voltage on SCL, SDA any address input
with respect to VSS: . . . . . . . . . . . . . . . . . . . . . . . . . . . -1V to +7V
V = | (VH - VL) | . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5V
14 Lead TSSOP. . . . . . . . . . . . . . . . . . . . . . . . . . . .
16 Lead SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Temperature Under Bias . . . . . . . . . . . . . . . . . . . . .-65C to +135C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
92
82
I
W (10 s). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±6mA
Operating Conditions
Temperature Range
Commercial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C
Industrial. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTES:
1. JA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details
Analog Specifications (Over recommended operating conditions unless otherwise stated.)
LIMITS
MIN.
MAX.
SYMBOL
PARAMETER
End-to-End Resistance Tolerance
Power Rating
TEST CONDITIONS
(Note 7)
TYP.
(Note 7)
UNIT
%
-20
+20
50
+25°C, each pot
mW
mA
IW
Wiper Current
±3
RW
Wiper Resistance
Wiper current = VCC/RTOTAL
CC = 5V
,
,
150
400
250
V
Wiper current = VCC/RTOTAL
CC = 3V
1000
VCC
V
VTERM
Voltage on Any VH/RH or VL/RL Pin
Noise
VSS = 0V
Ref: 1kHz
VSS
V
dBV
%
-120
1.6
Resolution (Note 4)
Absolute Linearity (Note 1)
Vw(n)(actual) - Vw(n)(expected)
±1
MI
(Note 3)
Relative Linearity (Note 2)
V
w(n + 1) - [Vw(n) + MI
]
±0.2
MI
(Note 3)
Temperature Coefficient of RTOTAL
Ratiometric Temperature Coefficient
Potentiometer Capacitances
300
±20
ppm/C
ppm/°C
pF
CH/CL/CW
See Circuit #3, Spice Macromodel
10/10/25
DC Electrical Specifications (Over the recommended operating conditions unless otherwise specified.)
LIMITS
MIN.
MAX.
SYMBOL
PARAMETER
VCC Supply Current
TEST CONDITIONS
(Note 7)
TYP
(Note 7)
UNIT
ICC1
fSCL = 400kHz, SDA = Open,
Other Inputs = VSS
3.5
mA
(nonvolatile write)
ICC2
VCC Supply Current
(move wiper, write, read)
fSCL = 400kHz, SDA = Open,
Other Inputs = VSS
170
µA
ISB
ILI
VCC Current (standby)
Input Leakage Current
SCL = SDA = VCC, Addr. = VSS
VIN = VSS to VCC
3
µA
µA
10
FN8248 Rev 4.00
October 16, 2015
Page 12 of 21
X9429
LIMITS
MIN.
MAX.
SYMBOL
PARAMETER
Output Leakage Current
Input HIGH Voltage
TEST CONDITIONS
VOUT = VSS to VCC
(Note 7)
TYP
(Note 7)
UNIT
µA
V
ILO
VIH
VIL
10
VCC x 0.7
-0.5
VCC x 0.5
VCC x 0.1
0.4
Input LOW Voltage
V
VOL
Output LOW voltage
IOL = 3mA
V
ENDURANCE AND DATA RETENTION
PARAMETER
Minimum Endurance
Data Retention
MIN.
100,000
100
UNIT
Data changes per bit per register
Years
CAPACITANCE
SYMBOL
CI/O (Note 5)
CIN (Note 5)
TEST
Input/output capacitance (SDA)
Input capacitance (A0, A2,and A3 and SCL)
TYP
8
UNIT
pF
TEST CONDITIONS
VI/O = 0V
6
pF
VIN = 0V
POWER-UP TIMING
SYMBOL
PARAMETER
VCC Power-up ramp rate
MIN
0.2
TYP
MAX
50
UNIT
tRVCC (Note 6)
NOTES:
V/ms
1. Absolute linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used as a
potentiometer.
2. Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a potentiometer. It is
a measure of the error in step size.
3. MI = RTOT/63 or (RH - RL)/63, single pot
4. Typical = individual array resolutions.
5. Limits established by characterization and are not production tested.
6. Sample tested only.
7. Parts are 100% tested at +25°C. Over temperature limits established by characterization and are not production tested.
Power-up and Power-down Requirements
AC Test Conditions
There are no restrictions on the power-up or power-down
Input pulse levels
VCC x 0.1 to VCC x 0.9
10ns
conditions of VCC and the voltage applied to the potentiometer
pins provided that VCC is always more positive than or equal to
VH, VL, and VW, i.e., VCC VH, VL, VW. The VCC ramp rate
spec is always in effect.
Input rise and fall times
Input and output timing level
VCC x 0.5
Equivalent AC Load Circuit
Circuit #3 SPICE Macro Model
5V
2.7V
R
TOTAL
1533
R
R
L
H
C
L
C
SDA OUTPUT
H
C
W
10pF
100pF
100pF
10pF
25pF
R
W
FN8248 Rev 4.00
October 16, 2015
Page 13 of 21
X9429
AC TIMING (Over recommended operating conditions)
MIN
MAX
SYMBOL
PARAMETER
(Note 7)
(Note 7)
UNIT
kHz
ns
fSCL
tCYC
Clock Frequency
400
Clock Cycle Time
2500
700
1300
600
600
600
100
30
tHIGH
tLOW
tSU:STA
tHD:STA
tSU:STO
tSU:DAT
tHD:DAT
tR
Clock High Time
ns
Clock Low Time
ns
Start Setup Time
ns
Start Hold Time
ns
Stop Setup Time
ns
SDA Data Input Setup Time
SDA Data Input Hold Time
SCL and SDA Rise Time
SCL and SDA Fall Time
ns
ns
300
300
900
ns
tF
ns
tAA
SCL low to SDA Data Output Valid Time
SDA Data Output Hold Hime
ns
tDH
50
50
ns
tI
Noise Suppression Time Constant at SCL and SDA Inputs
Bus Free Time (Prior to Any Transmission)
WP, A0, A2, A3 Setup Time
ns
tBUF
1300
0
ns
tSU:WPA
tHD:WPA
ns
WP, A0, A2, A3 Hold Time
0
ns
HIGH-VOLTAGE WRITE CYCLE TIMING
SYMBOL
PARAMETER
TYP
MAX
UNIT
tWR
High-Voltage Write Cycle Time (Store Instructions)
5
10
ms
XDCP TIMING
MIN
MAX
SYMBOL
PARAMETER
(Note 7) (Note 7)
UNIT
tWRPO
tWRL
Wiper Response Time After the Third (last) Power Supply is Stable
10
10
10
µs
µs
µs
Wiper Response Time After Instruction Issued (All Load Instructions)
Wiper Response Time From an Active SCL/SCK Edge (Increment/Decrement Instruction)
tWRID
FN8248 Rev 4.00
October 16, 2015
Page 14 of 21
X9429
Timing Diagrams
Start and Stop Timing
(START)
(STOP)
t
t
F
R
t
SCL
t
t
t
SU:STO
SU:STA
HD:STA
t
R
F
SDA
Input Timing
t
t
CYC
HIGH
SCL
SDA
t
LOW
t
t
t
BUF
SU:DAT
HD:DAT
Output Timing
SCL
SDA
t
t
DH
AA
XDCP Timing (for All Load Instructions)
(STOP)
SCL
SDA
LSB
t
WRL
V
/R
W
W
FN8248 Rev 4.00
October 16, 2015
Page 15 of 21
X9429
XDCP Timing (for Increment/Decrement Instruction)
SCL
WIPER REGISTER ADDRESS
INC/DEC
INC/DEC
SDA
t
WRID
V
/R
W
W
Write Protect and Device Address Pins Timing
(START)
(STOP)
SCL
...
(ANY INSTRUCTION)
...
SDA
...
t
t
SU:WPA
HD:WPA
WP
A0, A2, A3
Applications information
Basic Configurations of Electronic Potentiometers
+V
R
V
R
V
/R
W
W
I
THREE TERMINAL POTENTIOMETER;
VARIABLE VOLTAGE DIVIDER
TWO TERMINAL VARIABLE RESISTOR;
VARIABLE CURRENT
FN8248 Rev 4.00
October 16, 2015
Page 16 of 21
X9429
Application Circuits
NONINVERTING AMPLIFIER
VOLTAGE REGULATOR
317
V
+
–
S
V
V
V (REG)
O
O
IN
R
1
R
2
I
adj
R
R
1
2
V
= (1+R /R )V
V
(REG) = 1.25V (1+R /R )+I
R
adj 2
O
2
1
S
O
2
1
OFFSET VOLTAGE ADJUSTMENT
COMPARATOR WITH HYSTERESIS
R
R
2
1
V
V
–
+
S
S
V
O
–
+
100k
V
O
TL072
10k
10k
R
R
2
1
10k
V
V
= {R /(R +R )} V (max)
1 1 2 O
UL
LL
= {R /(R +R )} V (min)
1 1 2 O
+5V
FN8248 Rev 4.00
October 16, 2015
Page 17 of 21
X9429
Application Circuits (continued)
ATTENUATOR
FILTER
C
V
+
–
S
R
V
R
R
2
O
1
3
–
+
R
V
O
V
S
R
2
R
4
All R = 10k
S
R
1
G
= 1 + R /R
2
V
= G V
O
1
O
S
fc = 1/(2RC)
-1/2 G +1/2
INVERTING AMPLIFIER
EQUIVALENT L-R CIRCUIT
R
R
2
1
V
S
R
2
C
1
V
+
–
S
–
+
V
O
R
R
1
3
Z
IN
V
= G V
S
O
G = - R /R
2
1
Z
= R + s R (R + R ) C = R + s Leq
2 2 1 3 1 2
IN
(R + R ) >> R
1
3
2
FUNCTION GENERATOR
C
R
R
1
2
–
+
–
+
R
R
}
}
A
B
FREQUENCY µR , R , C
1
2
AMPLITUDE µR , R
A
B
FN8248 Rev 4.00
October 16, 2015
Page 18 of 21
X9429
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web to make sure that
you have the latest revision.
DATE
REVISION
CHANGE
October 16, 2015
FN8248.4
Updated the Ordering Information table on page 2.
Added Revision History and About Intersil sections.
Updated Package Outline Drawing M14.173 to the latest revision. Changes are as follows:
-Updated drawing to remove table and added land pattern.
About Intersil
Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products
address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets.
For the most updated datasheet, application notes, related documentation and related parts, please see the respective product
information page found at www.intersil.com.
You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask.
Reliability reports are also available from our website at www.intersil.com/support.
FN8248 Rev 4.00
October 16, 2015
Page 19 of 21
X9429
Package Outline Drawing
M14.173
14 LEAD THIN SHRINK SMALL OUTLINE PACKAGE (TSSOP)
Rev 3, 10/09
A
1
3
5.00 ±0.10
SEE
DETAIL "X"
14
8
6.40
PIN #1
I.D. MARK
4.40 ±0.10
2
3
1
7
0.20 C B A
B
0.65
0.09-0.20
TOP VIEW
END VIEW
1.00 REF
0.05
H
C
0.90 +0.15/-0.10
1.20 MAX
SEATING
PLANE
GAUGE
PLANE
0.25
5
0.25 +0.05/-0.06
0.10 CBA
0°-8°
0.60 ±0.15
0.05 MIN
0.15 MAX
0.10 C
SIDE VIEW
DETAIL "X"
(1.45)
NOTES:
1. Dimension does not include mold flash, protrusions or gate burrs.
Mold flash, protrusions or gate burrs shall not exceed 0.15 per side.
2. Dimension does not include interlead flash or protrusion. Interlead
flash or protrusion shall not exceed 0.25 per side.
(5.65)
3. Dimensions are measured at datum plane H.
4. Dimensioning and tolerancing per ASME Y14.5M-1994.
5. Dimension does not include dambar protrusion. Allowable protrusion
shall be 0.80mm total in excess of dimension at maximum material
condition. Minimum space between protrusion and adjacent lead is 0.07mm.
6. Dimension in ( ) are for reference only.
(0.65 TYP)
(0.35 TYP)
7. Conforms to JEDEC MO-153, variation AB-1.
TYPICAL RECOMMENDED LAND PATTERN
FN8248 Rev 4.00
October 16, 2015
Page 20 of 21
X9429
Small Outline Plastic Packages (SOIC)
M16.3 (JEDEC MS-013-AA ISSUE C)
N
16 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE
INDEX
AREA
0.25(0.010)
M
B M
H
INCHES
MILLIMETERS
E
SYMBOL
MIN
MAX
MIN
2.35
0.10
0.33
0.23
10.10
7.40
MAX
2.65
NOTES
-B-
A
A1
B
C
D
E
e
0.0926
0.0040
0.013
0.1043
0.0118
0.0200
0.0125
0.4133
0.2992
-
0.30
-
1
2
3
L
0.51
9
SEATING PLANE
A
0.0091
0.3977
0.2914
0.32
-
-A-
10.50
7.60
3
h x 45°
D
4
-C-
0.050 BSC
1.27 BSC
-
H
h
0.394
0.010
0.016
0.419
0.029
0.050
10.00
0.25
0.40
10.65
0.75
1.27
-
e
A1
C
5
B
0.10(0.004)
L
6
0.25(0.010) M
C
A M B S
N
16
16
7
0°
8°
0°
8°
-
NOTES:
Rev. 1 6/05
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Interlead
flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above
the seating plane, shall not exceed a maximum value of 0.61mm (0.024
inch)
10. Controlling dimension: MILLIMETER. Converted inch dimensions are
not necessarily exact.
© Copyright Intersil Americas LLC 2005-2015. All Rights Reserved.
All trademarks and registered trademarks are the property of their respective owners.
For additional products, see www.intersil.com/en/products.html
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such
modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are
current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its
subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN8248 Rev 4.00
October 16, 2015
Page 21 of 21
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