X9521B20I [RENESAS]
DUAL 100K DIGITAL POTENTIOMETER, 2-WIRE SERIAL CONTROL INTERFACE, 256 POSITIONS, PBGA20, XBGA-20;
| 型号： | X9521B20I |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | DUAL 100K DIGITAL POTENTIOMETER, 2-WIRE SERIAL CONTROL INTERFACE, 256 POSITIONS, PBGA20, XBGA-20 |
| 文件： | 总26页 (文件大小：433K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Hot Pluggable
Preliminary Information
X9521
Fiber Channel / Gigabit Ethernet Laser Diode Control for Fiber Optic Modules
Dual DCP, EEPROM Memory
FEATURES
DESCRIPTION
• Two Digitally Controlled Potentiometers (DCP’s)
—100 Tap - 10kΩ
The X9521 combines two Digitally Controlled Potentiome-
ters (DCP’s), and integrated EEPROM with Block LockTM
protection. All functions of the X9521 are accessed by an
industry standard 2-Wire serial interface.
—256 Tap - 100kΩ
—Non-Volatile
—Write Protect Function
• 2 kbit EEPROM Memory with Write Protect & Block
LockTM
• 2-Wire industry standard Serial Interface
—Complies to the Gigabit Interface Converter (GBIC)
specification
• Single Supply Operation
—2.7V to 5.5V
• Hot Pluggable
The DCP’s of the X9521 may be utilized to control the bias
and modulation currents of the laser diode in a Fiber Optic
module. The 2 kbit integrated EEPROM may be used to
store module definition data.
The features of the X9521 are ideally suited to simplifying
the design of fiber optic modules which comply to the Giga-
bit Interface Converter (GBIC) specification. The integration
of these functions into one package significantly reduces
board area, cost and increases reliability of laser diode
modules.
• Packages
—CSP (Chip Scale Package)
—20 Pin TSSOP
BLOCK DIAGRAM
R
R
R
H1
W1
L1
WIPER
COUNTER
REGISTER
8
7 - BIT
NONVOLATILE
MEMORY
WP
PROTECT LOGIC
R
R
R
H2
W2
L2
WIPER
COUNTER
REGISTER
CONSTAT
REGISTER
DATA
REGISTER
4
SDA
SCL
8 - BIT
NONVOLATILE
MEMORY
COMMAND
DECODE &
CONTROL
LOGIC
2 kbit
EEPROM
ARRAY
THRESHOLD
RESET LOGIC
©2000 Xicor Inc., Patents Pending
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Characteristics subject to change without notice. 1 of 26
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X9521 – Preliminary Information
PIN CONFIGURATION
NOT TO SCALE
CSP
20 Pin TSSOP
1
2
3
4
Vcc
NC
R
R
20
19
18
17
H2
1
2
3
4
W2
NC
NC
V1/Vcc
NC
R
R
L2
W2
A
B
C
D
E
R
NC
NC
NC
NC
NC
NC
L2
R
NC
H2
5
6
NC
16
15
14
13
12
11
NC
NC
NC
NC
WP
NC
R
SCL
WP
SCL
H1
7
8
NC
R
H1
R
V
R
SDA
W1
SS
L1
SDA
9
R
R
W1
L1
V
SS
10
Top View – Bumps Down
PIN ASSIGNMENT
Pin
1
CSP
B3
Name
Function
R
Connection to end of resistor array for (the 256 Tap) DCP 2.
H2
R
2
A3
Connection to terminal equivalent to the “Wiper” of a mechanical potentiometer for DCP 2.
Connection to other end of resistor array for (the 256 Tap) DCP2.
w2
R
3
A4
L2
Write Protect Control Pin. WP pin is a TTL level compatible input. When held HIGH, Write
Protection is enabled. In the enabled state, this pin prevents all nonvolatile “write” opera-
tions. Also, when the Write Protection is enabled, and the device Block Lock feature is active
(i.e. the Block Lock bits are NOT [0,0]), then no “write” (volatile or nonvolatile) operations
can be performed in the device (including the wiper position of any of the integrated Digitally
Controlled Potentiometers (DCPs).The WP pin uses an internal “pull-down” resistor, thus if
left floating the write protection feature is disabled.
7
C4
WP
Serial Clock.This is a TTL level compatible input pin used to control the serial bus timing for
data input and output.
8
9
D4
E4
SCL
Serial Data. SDA is a bidirectional TTL level compatible pin used to transfer data into and
out of the device. The SDA pin input buffer is always active (not gated). This pin requires
an external pull up resistor.
SDA
Vss
10
11
12
13
20
E1
E3
E2
D1
A2
Ground.
R
Connection to other end of resistor for (the 100 Tap) DCP 1.
Connection to terminal equivalent to the “Wiper” of a mechanical potentiometer for DCP 1
Connection to end of resistor array for (the 100 Tap) DCP 1.
Supply Voltage.
L1
R
w1
R
H1
Vcc
A1, B1,
B2, B4,
C1, C2,
C3, D2,
D3
4, 5, 6,
14, 15,
16, 17,
18, 19
NC
No Connect
Characteristics subject to change without notice. 2 of 26
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X9521 – Preliminary Information
SCL
SDA
Data Stable
Data Change
Data Stable
Figure 1. Valid Data Changes on the SDA Bus
Serial Stop Condition
PRINCIPLES OF OPERATION
SERIAL INTERFACE
All communications must be terminated by a STOP condi-
tion, which is a LOW to HIGH transition of SDA while SCL
is HIGH. The STOP condition is also used to place the
device into the Standby power mode after a read
sequence. A STOP condition can only be issued after the
transmitting device has released the bus. See Figure 2.
Serial Interface Conventions
The device supports a bidirectional bus oriented protocol.
The protocol defines any device that sends data onto the
bus as a transmitter, and the receiving device as the
receiver. The device controlling the transfer is called the
master and the device being controlled is called the slave.
The master always initiates data transfers, and provides
the clock for both transmit and receive operations. There-
fore, the X9521 operates as a slave in all applications.
Serial Acknowledge
An ACKNOWLEDGE (ACK) is a software convention
used to indicate a successful data transfer. The transmit-
ting device, either master or slave, will release the bus
after transmitting eight bits. During the ninth clock cycle,
the receiver will pull the SDA line LOW to ACKNOWL-
EDGE that it received the eight bits of data. Refer to Fig-
ure 3.
Serial Clock and Data
Data states on the SDA line can change only while SCL is
LOW. SDA state changes while SCL is HIGH are
reserved for indicating START and STOP conditions. See
Figure 1. On power up of the X9521, the SDA pin is in the
input mode.
The device will respond with an ACKNOWLEDGE after
recognition of a START condition if the correct Device
Identifier bits are contained in the Slave Address Byte. If a
write operation is selected, the device will respond with an
ACKNOWLEDGE after the receipt of each subsequent
eight bit word.
Serial Start Condition
All commands are preceded by the START condition,
which is a HIGH to LOW transition of SDA while SCL is
HIGH. The device continuously monitors the SDA and
SCL lines for the START condition and does not respond
to any command until this condition has been met. See
Figure 2.
In the read mode, the device will transmit eight bits of
data, release the SDA line, then monitor the line for an
ACKNOWLEDGE. If an ACKNOWLEDGE is detected
and no STOP condition is generated by the master, the
device will continue to transmit data.The device will termi-
SCL
SDA
Start
Stop
Figure 2. Valid Start and Stop Conditions
Characteristics subject to change without notice. 3 of 26
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X9521 – Preliminary Information
SCL
from
Master
1
8
9
Data Output
from
Transmitter
Data Output
from
Receiver
Start
Acknowledge
Figure 3. Acknowledge Response From Receiver
nate further data transmissions if an ACKNOWLEDGE is
not detected. The master must then issue a STOP condi-
tion to place the device into a known state.
—The next three bits (SA3 - SA1) are the Internal Device
Address bits. Setting these bits to 000 internally selects
the EEPROM array, while setting these bits to 111
selects the DCP structures in the X9521. The CON-
STAT Register may be selected using the Internal
Device Address 010.
DEVICE INTERNAL ADDRESSING
Addressing Protocol Overview
—The Least Significant Bit of the Slave Address (SA0)
Byte is the R/W bit. This bit defines the operation to be
performed on the device being addressed (as defined
in the bits SA3 - SA1). When the R/W bit is “1”, then a
READ operation is selected. A “0” selects a WRITE
operation (Refer to Figure 4.)
The user addressable internal components of the X9521
can be split up into three main parts:
—Two Digitally Controlled Potentiometers (DCPs)
—EEPROM array
—Control and Status (CONSTAT) Register
SA7 SA6
SA3 SA2
SA5 SA4
SA1
Depending upon the operation to be performed on each
of these individual parts, a 1, 2 or 3 Byte protocol is used.
All operations however must begin with the Slave Address
Byte being issued on the SDA pin. The Slave address
selects the part of the X9521 to be addressed, and speci-
fies if a Read or Write operation is to be performed.
SA0
R/W
1 0 1 0
READ /
WRITE
INTERNAL
DEVICE TYPE
IDENTIFIER
DEVICE
ADDRESS
It should be noted that in order to perform a write opera-
tion to either a DCP or the EEPROM array, the Write
Enable Latch (WEL) bit must first be set (See “BL1, BL0:
Block Lock protection bits - (Nonvolatile)” on page 12.)
Internally Addressed
Device
Internal Address
(SA3 - SA1)
EEPROM Array
CONSTAT Register
DCP
000
010
111
Slave Address Byte
Following a START condition, the master must output a
Slave Address Byte (Refer to Figure 4.). This byte con-
sists of three parts:
Bit SA0
Operation
WRITE
—The Device Type Identifier which consists of the most
significant four bits of the Slave Address (SA7 - SA4).
The Device Type Identifier must always be set to 1010
in order to select the X9521.
0
1
READ
Figure 4. Slave Address Format
Characteristics subject to change without notice. 4 of 26
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X9521 – Preliminary Information
Nonvolatile Write Acknowledge Polling
After a nonvolatile write command sequence (for either
the EEPROM array, the Non Volatile Memory of a DCP
(NVM), or the CONSTAT Register) has been correctly
issued (including the final STOP condition), the X9521 ini-
tiates an internal high voltage write cycle. This cycle typi-
cally requires 5 ms. During this time, no further Read or
Write commands can be issued to the device. Write
Acknowledge Polling is used to determine when this high
voltage write cycle has been completed.
R
N
Hx
WIPER
COUNTER
REGISTER
(WCR)
“WIPER”
FET
SWITCHES
RESISTOR
ARRAY
DECODER
To perform acknowledge polling, the master issues a
START condition followed by a Slave Address Byte. The
Slave Address issued must contain a valid Internal Device
Address. The LSB of the Slave Address (R/W) can be set
to either 1 or 0 in this case. If the device is still busy with
the high voltage cycle then no ACKNOWLEDGE will be
returned. If the device has completed the write operation,
an ACKNOWLEDGE will be returned and the host can
then proceed with a read or write operation. (Refer to Fig-
ure 5.).
2
1
0
NON
VOLATILE
MEMORY
(NVM)
R
R
Lx
Wx
Figure 6. DCP Internal Structure
DIGITALLY CONTROLLED POTENTIOMETERS
DCP Functionality
Byte load completed
by issuing STOP.
Enter ACK Polling
The X9521 includes two independent resistor arrays.
These arrays respectively contain 99 and 255 discrete
resistive segments that are connected in series. The
physical ends of each array are equivalent to the fixed
Issue START
terminals of a mechanical potentiometer (R and R
inputs - where x = 1,2).
Hx
Lx
Issue Slave Address
Byte (Read or Write)
Issue STOP
At both ends of each array and between each resistor
segment there is a CMOS switch connected to the wiper
NO
ACK
returned?
(R ) output.Within each individual array, only one switch
x
w
may be turned on at any one time. These switches are
controlled by the Wiper Counter Register (WCR) (See
Figure 6).The WCR is a volatile register.
YES
On power up of the X9521, wiper position data is auto-
matically loaded into the WCR from its associated Non
Volatile Memory (NVM) Register. The Table below shows
the Initial Values of the DCP WCR’s before the contents of
the NVM is loaded into the WCR.
High Voltage Cycle
complete. Continue
command sequence?
NO
Issue STOP
YES
DCP
R / 100 TAP
Initial Values Before Recall
V / TAP = 0
Continue normal
Read or Write
command sequence
1
L
R / 256 TAP
V / TAP = 255
H
2
PROCEED
The data in the WCR is then decoded to select and
enable one of the respective FET switches. A “make
Figure 5.
Acknowledge Polling Sequence
Characteristics subject to change without notice. 5 of 26
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X9521 – Preliminary Information
Vcc
Vcc (Max.)
V
TRIP
t
t
trans
pu
t
0
Maximum Wiper Recall time
Figure 7. DCP Power up
before break” sequence is used internally for the FET
switches when the wiper is moved from one tap position
to another.
remains unchanged. Therefore, when Vcc to the device is
powered down then back up, the “wiper position” reverts
to that last position written to the DCP using a nonvolatile
write operation.
Hot Pluggability
Both volatile and nonvolatile write operations are
executed using a three byte command sequence: (DCP)
Slave Address Byte, Instruction Byte, followed by a Data
Byte (See Figure 9)
Figure 7 shows a typical waveform that the X9521 might
experience in a Hot Pluggable situation. On power up,
Vcc applied to the X9521 may exhibit some amount of
ringing, before it settles to the required value.
A DCP Read operation allows the user to “read out” the
current “wiper position” of the DCP, as stored in the
associated WCR. This operation is executed using the
Random Address Read command sequence, consisting
of the (DCP) Slave Address Byte followed by an
Instruction Byte and the Slave Address Byte again (Refer
to Figure 10.).
The device is designed such that the wiper terminal (R
is recalled to the correct position (as per the last stored in
the DCP NVM), when the voltage applied to Vcc exceeds
)
Wx
V
for a time exceeding t .
pu
TRIP
Therefore, if t
is defined as the time taken for Vcc to
(Figure 7): then the desired wiper ter-
trans
settle above V
TRIP
minal position is recalled by (a maximum) time: t
+
trans
is determined by system
t . It should be noted that t
pu
trans
Instruction Byte
hot plug conditions.
While the Slave Address Byte is used to select the DCP
devices, an Instruction Byte is used to determine which
DCP is being addressed.
DCP Operations
In total there are three operations that can be performed
on any internal DCP structure:
The Instruction Byte (Figure 8) is valid only when the
Device Type Identifier and the Internal Device Address
bits of the Slave Address are set to 1010111. In this
case, the two Least Significant Bit’s (I1 - I0) of the
Instruction Byte are used to select the particular DCP (0
- 2). In the case of a Write to any of the DCPs (i.e. the LSB
of the Slave Address is 0), the Most Significant Bit of the
Instruction Byte (I7), determines the Write Type (WT) per-
formed.
—DCP Nonvolatile Write
—DCP Volatile Write
—DCP Read
A nonvolatile write to a DCP will change the “wiper
position” by simultaneously writing new data to the
associated WCR and NVM. Therefore, the new “wiper
position” setting is recalled into the WCR after Vcc of the
X9521 is powered down and then powered back up.
If WT is “1”, then a Nonvolatile Write to the DCP occurs. In
this case, the “wiper position” of the DCP is changed by
simultaneously writing new data to the associated WCR
A volatile write operation to a DCP however, changes the
“wiper position” by writing new data to the associated
WCR only. The contents of the associated NVM register
Characteristics subject to change without notice. 6 of 26
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X9521 – Preliminary Information
The Slave Address Byte 10101110 specifies that a Write
to a DCP is to be conducted. An ACKNOWLEDGE is
returned by the X9521 after the Slave Address, if it has
been received correctly.
I7
I6
0
I5
0
I4
0
I3
0
I2
0
I1
P1
I0
P0
WT
Next, an Instruction Byte is issued on SDA. Bits P1 and
P0 of the Instruction Byte determine which WCR is to be
written, while the WT bit determines if the Write is to be
volatile or nonvolatile. If the Instruction Byte format is
valid, another ACKNOWLEDGE is then returned by the
X9521.
WRITE TYPE
DCP SELECT
WT†
Description
Select a Volatile Write operation to be performed
on the DCP pointed to by bits P1 and P0
0
Select a Nonvolatile Write operation to be per-
formed on the DCP pointed to by bits P1 and P0
Following the Instruction Byte, a Data Byte is issued to the
X9521 over SDA. The Data Byte contents is latched into
the WCR of the DCP on the first rising edge of the clock
signal, after the LSB of the Data Byte (D0) has been
issued on SDA (See Figure 25).
1
†
This bit has no effect when a Read operation is being performed.
Figure 8. Instruction Byte Format
The Data Byte determines the “wiper position” (which
FET switch of the DCP resistive array is switched ON) of
the DCP. The maximum value for the Data Byte depends
upon which DCP is being addressed (see Table below).
and NVM. Therefore, the new “wiper position” setting is
recalled into the WCR after Vcc of the X9521 has been
powered down then powered back up
P1- P0
DCPx
# Taps
Reserved
Max. Data Byte
If WT is “0” then a DCP Volatile Write is performed. This
operation changes the DCP “wiper position” by writing
new data to the associated WCR only.The contents of the
associated NVM register remains unchanged. Therefore,
when Vcc to the device is powered down then back up,
the “wiper position” reverts to that last written to the DCP
using a nonvolatile write operation.
0
0
1
1
0
1
0
1
x=1
x=2
100
256
Refer to Appendix 1
FFh
Reserved
Using a Data Byte larger than the values specified above
results in the “wiper terminal” being set to the highest tap
position. The “wiper position” does NOT roll-over to the
lowest tap position.
DCP Write Operation
A write to DCPx (x=1,2) can be performed using the three
byte command sequence shown in Figure 9.
For DCP2 (256 Tap), the Data Byte maps one to one to
the “wiper position” of the DCP “wiper terminal”. There-
In order to perform a write operation on a particular DCP,
the Write Enable Latch (WEL) bit of the CONSTAT Regis-
ter must first be set (See “BL1, BL0: Block Lock protection
bits - (Nonvolatile)” on page 12.)
fore, the Data Byte 00001111 (15 ) corresponds to set-
10
ting the “wiper terminal” to tap position 15. Similarly, the
Data Byte 00011100 (28 ) corresponds to setting the
10
1
0
1
0
1
1
1
0
D7 D6 D5 D4 D3 D2 D1 D0
DATA BYTE
S
T
A
R
T
A
C
K
WT
0
0
0
0
0
P1 P0
A
C
K
A
C
K
S
T
O
P
SLAVE ADDRESS BYTE
INSTRUCTION BYTE
Figure 9. DCP Write Command Sequence
Characteristics subject to change without notice. 7 of 26
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X9521 – Preliminary Information
WRITE Operation
READ Operation
S
t
S
t
S
t
o
p
Signals from
the Master
Instruction
Byte
Slave
Slave
Address
a
r
a
r
Address
Data Byte
t
t
SDA Bus
P
0
10101110 W 00000 P1
10101111
T
A
C
K
A
C
K
A
C
K
Signals from
the Slave
DCPx
x = 1
x = 2
-
“Dummy” write
LSB
MSB
“-” = DON’T CARE
Figure 10. DCP Read Sequence
“wiper terminal” to tap position 28. The mapping of the
Data Byte to “wiper position” data for DCP1 (100 Tap), is
shown in “APPENDIX 1” . An example of a simple C lan-
guage function which “translates” between the tap posi-
tion (decimal) and the Data Byte (binary) for DCP1, is
given in “APPENDIX 2” .
DCP Read Operation
A read of DCPx (x=1,2) can be performed using the three
byte random read command sequence shown in Figure
10.
The master issues the START condition and the Slave
Address Byte 10101110 which specifies that a “dummy”
write” is to be conducted. This “dummy” write operation
sets which DCP is to be read (in the preceding Read
operation). An ACKNOWLEDGE is returned by the
X9521 after the Slave Address if received correctly. Next,
an Instruction Byte is issued on SDA. Bits P1-P0 of the
Instruction Byte determine which DCP “wiper position” is
to be read. In this case, the state of the WT bit is “don’t
care”. If the Instruction Byte format is valid, then another
ACKNOWLEDGE is returned by the X9521.
It should be noted that all writes to any DCP of the X9521
are random in nature.Therefore, the Data Byte of consec-
utive write operations to any DCP can differ by an arbi-
trary number of bits. Also, setting the bits (P1=0, P0=0) or
(P1=1, P0=1) are reserved sequences, and will result in
no ACKNOWLEDGE after sending an Instruction Byte on
SDA.
The factory default setting of all “wiper position” settings is
with 00h stored in the NVM of the DCPs. This corre-
sponds to having the “wiper teminal” R
(x=1,2) at the
WX
Following this ACKNOWLEDGE, the master immediately
issues another START condition and a valid Slave
address byte with the R/W bit set to 1. Then the X9521
issues an ACKNOWLEDGE followed by Data Byte, and
“lowest” tap position, Therefore, the resistance between
and R is a minimum (essentially only the Wiper
R
WX
LX
Resistance, R ).
W
S
t
WRITE Operation
S
t
o
p
a
r
Signals from
the Master
Address
Byte
Slave
Address
Data
Byte
t
SDA Bus
0 1
0 0
0
1
0 0
A
C
K
A
C
K
A
C
K
Internal
Signalsfrom
the Slave
Device
Address
Figure 11. EEPROM Byte Write Sequence
Characteristics subject to change without notice. 8 of 26
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X9521 – Preliminary Information
S
t
S
t
o
p
(2 < n < 16)
a
Signals from
the Master
r
t
Address
Byte
Slave
Address
Data
(1)
Data
(n)
SDA Bus
0 1
0 0
0
1
0 0
A
C
K
A
C
K
A
C
K
A
C
K
Signals from
the Slave
Figure 12. EEPROM Page Write Operation
finally, the master issues a STOP condition. The Data
Byte read in this operation, corresponds to the “wiper
position” (value of the WCR) of the DCP pointed to by bits
P1 and P0.
responds with an ACKNOWLEDGE. The master then
terminates the transfer by generating a STOP condition,
at which time the X9521 begins the internal write cycle to
the nonvolatile memory (See Figure 11). During this
internal write cycle, the X9521 inputs are disabled, so it
does not respond to any requests from the master. The
SDA output is at high impedance. A write to a region of
EEPROM memory which has been protected with the
Block-Lock feature (See “BL1, BL0: Block Lock protection
bits - (Nonvolatile)” on page 12.), suppresses the
ACKNOWLEDGE bit after the Address Byte.
It should be noted that when reading out the data byte for
DCP1 (100 Tap), the upper most significant bit is an
“unknown”. For DCP2 (256 Tap) however, all bits of the
data byte are relevant (See Figure 10).
2 kbit EEPROM ARRAY
Operations on the 2 kbit EEPROM Array, consist of either
1, 2 or 3 byte command sequences. All operations on the
EEPROM must begin with the Device Type Identifier of
the Slave Address set to 1010000. A Read or Write to the
EEPROM is selected by setting the LSB of the Slave
Address to the appropriate value R/W (Read = “1”,
Write=”0”).
EEPROM Page Write
In order to perform an EEPROM Page Write operation to
the EEPROM array, the Write Enable Latch (WEL) bit of
the CONSTAT Register must first be set (See “BL1, BL0:
Block Lock protection bits - (Nonvolatile)” on page 12.)
In some cases when performing a Read or Write to the
EEPROM, an Address Byte may also need to be speci-
fied. This Address Byte can contain the values 00h to
FFh.
The X9521 is capable of a page write operation. It is initi-
ated in the same manner as the byte write operation; but
instead of terminating the write cycle after the first data
byte is transferred, the master can transmit an unlimited
number of 8-bit bytes. After the receipt of each byte, the
X9521 responds with an ACKNOWLEDGE, and the
address is internally incremented by one. The page
address remains constant. When the counter reaches the
end of the page, it “rolls over” and goes back to ‘0’ on the
same page.
EEPROM Byte Write
In order to perform an EEPROM Byte Write operation to
the EEPROM array, the Write Enable Latch (WEL) bit of
the CONSTAT Register must first be set (See “BL1, BL0:
Block Lock protection bits - (Nonvolatile)” on page 12.)
For example, if the master writes 12 bytes to the page
starting at location 11 (decimal), the first 5 bytes are writ-
ten to locations 11 through 15, while the last 7 bytes are
written to locations 0 through 6. Afterwards, the address
counter would point to location 7. If the master supplies
more than 16 bytes of data, then new data overwrites the
previous data, one byte at a time (See Figure 13).
For a write operation, the X9521 requires the Slave
Address Byte and an Address Byte.This gives the master
access to any one of the words in the array. After receipt
of the Address Byte, the X9521 responds with an
ACKNOWLEDGE, and awaits the next eight bits of data.
After receiving the 8 bits of the Data Byte, it again
Characteristics subject to change without notice. 9 of 26
REV 1.1.9 1/30/03
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X9521 – Preliminary Information
S
Signals from
the Master
S
t
o
p
t
Slave
Address
a
r
t
SDA Bus
1
1
01 0 0 0 0
A
C
K
Signals from
the Slave
Data
Figure 14. Current EEPROM Address Read Sequence
The master terminates the Data Byte loading by issuing a
STOP condition, which causes the X9521 to begin the
nonvolatile write cycle. As with the byte write operation, all
inputs are disabled until completion of the internal write
cycle. See Figure 12 for the address, ACKNOWLEDGE,
and data transfer sequence.
Current EEPROM Address Read
Internally the device contains an address counter that
maintains the address of the last word read incremented
by one. Therefore, if the last read was to address n, the
next read operation would access data from address n+1.
On power up, the address of the address counter is unde-
fined, requiring a read or write operation for initialization.
Stops and EEPROM Write Modes
Upon receipt of the Slave Address Byte with the R/W bit
set to one, the device issues an ACKNOWLEDGE and
then transmits the eight bits of the Data Byte. The master
terminates the read operation when it does not respond
with an ACKNOWLEDGE during the ninth clock and then
issues a STOP condition (See Figure 14 for the address,
ACKNOWLEDGE, and data transfer sequence).
Stop conditions that terminate write operations must be
sent by the master after sending at least 1 full data byte
and receiving the subsequent ACKNOWLEDGE signal. If
the master issues a STOP within a Data Byte, or before
the X9521 issues a corresponding ACKNOWLEDGE, the
X9521 cancels the write operation. Therefore, the con-
tents of the EEPROM array does not change.
It should be noted that the ninth clock cycle of the read
operation is not a “don’t care.” To terminate a read opera-
tion, the master must either issue a STOP condition dur-
ing the ninth cycle or hold SDA HIGH during the ninth
clock cycle and then issue a STOP condition.
EEPROM Array Read Operations
Read operations are initiated in the same manner as write
operations with the exception that the R/W bit of the Slave
Address Byte is set to one. There are three basic read
operations: Current EEPROM Address Read, Random
EEPROM Read, and Sequential EEPROM Read.
Another important point to note regarding the “Current
EEPROM Address Read” , is that this operation is not
available if the last executed operation was an access to a
DCP or the CONSTAT Register (i.e.: an operation using
5 bytes
5 bytes
7 bytes
address
11
address
1510
address
= 610
10
address pointer
ends here
Addr = 710
Figure 13. Example:Writing 12 bytes to a 16-byte page starting at location 11.
Characteristics subject to change without notice. 10 of 26
REV 1.1.9 1/30/03
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X9521 – Preliminary Information
WRITE Operation
READ Operation
S
t
S
t
S
t
o
p
Signals from
the Master
Slave
Address
Address
Byte
Slave
Address
a
r
a
r
t
t
SDA Bus
0
1
1 0 1 0 0 0 0
10 1 0 0 0 0
A
C
K
A
C
K
A
C
K
Signals from
the Slave
Data
“Dummy”Write
Figure 15. Random EEPROM Address Read Sequence
the Device Type Identifier 1010111 or 1010010). Immedi-
ately after an operation to a DCP or CONSTAT Register is
performed, only a “Random EEPROM Read” is available.
Immediately following a “Random EEPROM Read” , a
“Current EEPROM Address Read” or “Sequential
EEPROM Read” is once again available (assuming that
no access to a DCP or CONSTAT Register occur in the
interim).
After the X9521 acknowledges the receipt of the Address
Byte, the master immediately issues another START con-
dition and the Slave Address Byte with the R/W bit set to
one. This is followed by an ACKNOWLEDGE from the
X9521 and then by the eight bit word. The master termi-
nates the read operation by not responding with an
ACKNOWLEDGE and instead issuing a STOP condition
(Refer to Figure 15.).
A similar operation called “Set Current Address” also
exists. This operation is performed if a STOP is issued
instead of the second START shown in Figure 15. In this
case, the device sets the address pointer to that of the
Address Byte, and then goes into standby mode after the
STOP bit. All bus activity will be ignored until another
START is detected.
Random EEPROM Read
Random read operation allows the master to access any
memory location in the array. Prior to issuing the Slave
Address Byte with the R/W bit set to one, the master must
first perform a “dummy” write operation. The master
issues the START condition and the Slave Address Byte,
receives an ACKNOWLEDGE, then issues an Address
Byte. This “dummy” Write operation sets the address
pointer to the address from which to begin the random
EEPROM read operation.
Sequential EEPROM Read
Sequential reads can be initiated as either a current
address read or random address read.The first Data Byte
is transmitted as with the other modes; however, the mas-
S
Slave
Address
A
C
K
A
C
K
A
C
K
Signals from
the Master
t
o
p
SDA Bus
1
0 0 0
A
C
K
Signals from
the Slave
Data
(2)
Data
(n-1)
Data
(1)
Data
(n)
(n is any integer greater than 1)
Figure 16. Sequential EEPROM Read Sequence
Characteristics subject to change without notice. 11 of 26
REV 1.1.9 1/30/03
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X9521 – Preliminary Information
WEL:Write Enable Latch (Volatile)
The WEL bit controls the Write Enable status of the entire
X9521 device. This bit must first be enabled before ANY
write operation (to DCPs, EEPROM memory array, or the
CONSTAT register). If the WEL bit is not first enabled,
then ANY proceeding (volatile or nonvolatile) write opera-
tion to DCPs, EEPROM array, as well as the CONSTAT
register, is aborted and no ACKNOWLEDGE is issued
after a Data Byte.
CS3
BL0
CS7 CS6
CS4
BL1
CS5
0
CS2 CS1 CS0
0
0
0
RWEL
WEL
NV
NV
Bit(s)
CS7 - CS5
BL1 - BL0
RWEL
Description
Always “0”(RESERVED)
Sets the Block Lock partition
Register Write Enable Latch bit
Write Enable Latch bit
The WEL bit is a volatile latch that powers up in the dis-
abled, LOW (0) state.The WEL bit is enabled / set by writ-
ing 00000010 to the CONSTAT register. Once enabled,
the WEL bit remains set to “1” until either it is reset to “0”
(by writing 00000000 to the CONSTAT register) or until
the X9521 powers down, and then up again.
WEL
CS0
Always “0” (RESERVED)
Writes to the WEL bit do not cause an internal high volt-
age write cycle. Therefore, the device is ready for another
operation immediately after a STOP condition is executed
in the CONSTAT Write command sequence (See Figure
18).
NOTE: Bits labelled NV are nonvolatile (See “CONTROL AND STATUS REGISTER”).
Figure 17. CONSTAT Register Format
ter now responds with an ACKNOWLEDGE, indicating it
requires additional data. The X9521 continues to output a
Data Byte for each ACKNOWLEDGE received. The mas-
ter terminates the read operation by not responding with
an ACKNOWLEDGE and instead issuing a STOP condi-
tion.
RWEL: Register Write Enable Latch (Volatile)
The RWEL bit controls the (CONSTAT) Register Write
Enable status of the X9521. Therefore, in order to write to
any of the bits of the CONSTAT Register (except WEL),
the RWEL bit must first be set to “1”. The RWEL bit is a
volatile bit that powers up in the disabled, LOW (“0”) state.
The data output is sequential, with the data from address
n followed by the data from address n + 1. The address
counter for read operations increments through the entire
memory contents to be serially read during one operation.
At the end of the address space the counter “rolls over” to
address 00h and the device continues to output data for
each ACKNOWLEDGE received (Refer to Figure 16.).
It must be noted that the RWEL bit can only be set, once
the WEL bit has first been enabled (See "CONSTAT Reg-
ister Write Operation").
The RWEL bit will reset itself to the default “0” state, in
one of three cases:
CONTROL AND STATUS REGISTER
—After a successful write operation to any bits of the
CONSTAT register has been completed (See Figure
18).
The Control and Status (CONSTAT) Register provides the
user with a mechanism for changing and reading the sta-
tus of various parameters of the X9521 (See Figure 17).
—When the X9521 is powered down.
The CONSTAT register is a combination of both volatile
and nonvolatile bits. The nonvolatile bits of the CONSTAT
register retain their stored values even when Vcc is pow-
ered down, then powered back up. The volatile bits how-
ever, will always power up to a known logic state “0”
(irrespective of their value at power down).
—When attempting to write to a Block Lock protected
region of the EEPROM memory (See "BL1, BL0: Block
Lock protection bits - (Nonvolatile)", below).
BL1, BL0: Block Lock protection bits - (Nonvolatile)
The Block Lock protection bits (BL1 and BL0) are used to:
A detailed description of the function of each of the CON-
STAT register bits follows:
—Inhibit a write operation from being performed to certain
addresses of the EEPROM memory array
—Inhibit a DCP write operation (changing the “wiper posi-
tion”).
Characteristics subject to change without notice. 12 of 26
REV 1.1.9 1/30/03
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X9521 – Preliminary Information
SCL
SDA
CS0
CS2CS1
1
CS7 CS6
S
T
A
R
T
1
0
1
0
0
1
0
R/W A
1
1
1
1
1
1
1
A
C
K
CS5 CS4 CS3
A
C
K
S
T
O
P
C
K
SLAVE ADDRESS BYTE
ADDRESS BYTE
CONSTAT REGISTER DATA IN
Figure 18. CONSTAT Register Write Command Sequence
The region of EEPROM memory which is protected /
locked is determined by the combination of the BL1 and
BL0 bits written to the CONSTAT register. It is possible to
lock the regions of EEPROM memory shown in the table
below:
Slave Address Byte, access to the CONSTAT register
requires an Address Byte which must be set to FFh. Only
one data byte is allowed to be written for each CONSTAT
register Write operation. The user must issue a STOP,
after sending this byte to the register, to initiate the nonvol-
atile cycle that stores the BP1and BP0 bits. The X9521
will not ACKNOWLEDGE any data bytes written after the
first byte is entered (Refer to Figure 18.).
Protected Addresses
(Size)
Partition of array
locked
BL1 BL0
0
0
1
1
0
1
0
1
None (Default)
None (Default)
Upper 1/4
Upper 1/2
All
When writing to the CONSTAT register, the bits CS7-CS5
and CS0 must all be set to “0”. Writing any other bit
sequence to bits CS7-CS5 and CS0 of the CONSTAT
register is reserved.
C0h - FFh (64 bytes)
80h - FFh (128 bytes)
00h - FFh (256 bytes)
If the user attempts to perform a write operation on a pro-
tected region of EEPROM memory, the operation is
aborted without changing any data in the array.
Prior to writing to the CONSTAT register, the WEL and
RWEL bits must be set using a two step process, with the
whole sequence requiring 3 steps
—Write a 02H to the CONSTAT Register to set the Write
Enable Latch (WEL). This is a volatile operation, so
there is no delay after the write. (Operation preceded by
a START and ended with a STOP).
When the Block Lock bits of the CONSTAT register are
set to something other than BL1=0 and BL0=0, then the
“wiper position” of the DCPs cannot be changed - i.e.
DCP write operations cannot be conducted:
—Write a 06H to the CONSTAT Register to set the Regis-
ter Write Enable Latch (RWEL) AND the WEL bit. This
is also a volatile cycle. The zeros in the data byte are
required. (Operation preceded by a START and ended
with a STOP).
BL1 BL0
DCP Write Operation Permissible
0
0
1
1
0
1
0
1
YES (Default)
NO
NO
NO
—Write a one byte value to the CONSTAT Register that
has all the bits set to the desired state. The CONSTAT
register can be represented as 000st010 in binary,
where st are the Block Lock Protection (BL1 and BL0)
bits. This operation is proceeded by a START and
ended with a STOP bit. Since this is a nonvolatile write
cycle, it will typically take 5ms to complete. The RWEL
bit is reset by this cycle and the sequence must be
repeated to change the nonvolatile bits again. If bit 2 is
set to ‘1’ in this third step (000s t110) then the RWEL bit
is set, but the BL1 and BL0 bits remain unchanged.
Writing a second byte to the control register is not
allowed. Doing so aborts the write operation and the
X9521 does not return an ACKNOWLEDGE.
The factory default setting for these bits are BL1 = 0, BL0
= 0.
IMPORTANT NOTE: If the Write Protect (WP) pin of the
X9521 is active (HIGH), then all nonvolatile write opera-
tions to both the EEPROM memory and DCPs are inhib-
ited, irrespective of the Block Lock bit settings (See "WP:
Write Protection Pin").
CONSTAT Register Write Operation
The CONSTAT register is accessed using the Slave
Address set to 1010010 (Refer to Figure 4.). Following the
Characteristics subject to change without notice. 13 of 26
REV 1.1.9 1/30/03
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X9521 – Preliminary Information
READ Operation
WRITE Operation
S
t
S
t
S
t
o
p
Signals from
the Master
Slave
Address
Address
Byte
Slave
Address
a
r
a
r
t
t
CS7 … CS0
SDA Bus
0
1
10 1 0 0 1 0
1 0 1 0 0 1 0
A
C
K
A
C
K
A
C
K
Signals from
the Slave
Data
“Dummy”Write
Figure 19. CONSTAT Register Read Command Sequence
For example, a sequence of writes to the device CON-
STAT register consisting of [02H, 06H, 02H] will reset the
BL0 and BL0 bits in the CONSTAT Register to “0”.
DATA PROTECTION
There are a number of levels of data protection features
designed into the X9521. Any write to the device first
requires setting of the WEL bit in the CONSTAT register.
A write to the CONSTAT register itself, further requires the
setting of the RWEL bit. Block Lock protection of the
device enables the user to inhibit writes to certain regions
of the EEPROM memory, as well as to all the DCPs. One
further level of data protection in the X9521, is incorpo-
rated in the form of the Write Protection pin.
It should be noted that a write to any nonvolatile bit of
CONSTAT register will be ignored if the Write Protect pin
of the X9521 is active (HIGH) (See "WP: Write Protection
Pin").
CONSTAT Register Read Operation
The contents of the CONSTAT Register can be read at
any time by performing a random read (See Figure 19).
Using the Slave Address Byte set to 10100101, and an
Address Byte of FFh. Only one byte is read by each regis-
ter read operation. The X9521 resets itself after the first
byte is read. The master should supply a STOP condition
to be consistent with the bus protocol.
WP:Write Protection Pin
When the Write Protection (WP) pin is active (HIGH), it
disables nonvolatile write operations to the X9521.
The table below (X9521 Write Permission Status) sum-
marizes the effect of the WP pin (and Block Lock), on the
write permission status of the device.
After setting the WEL and / or the RWEL bit(s) to a “1”, a
CONSTAT register read operation may occur, without
interrupting a proceeding CONSTAT register write opera-
tion.
Additional Data Protection Features
In addition to the preceding features, the X9521 also
incorporates the following data protection functionality:
When reading the contents of the CONSTAT register, the
bits CS7-CS5 and CS0 will always return “0”.
—The proper clock count and data bit sequence is
required prior to the STOP bit in order to start a nonvol-
atile write cycle.
X9521 Write Permission Status
BlockLock
Bits
Write to CONSTAT Register
Permitted
DCP Volatile Write
Permitted
DCP Nonvolatile
Write Permitted
Write to EEPROM
Permitted
Nonvolatile
Bits
BL0 BL1 WP
Volatile Bits
NO
x
1
0
x
1
0
1
x
0
1
x
0
1
1
1
0
0
0
NO
NO
NO
NO
NO
NO
NO
YES
NO
NO
NO
NO
NO
YES
NO
NO
NO
NO
Not in locked region
Not in locked region
Yes (All Array)
YES
YES
YES
YES
NO
YES
YES
YES
Characteristics subject to change without notice. 14 of 26
REV 1.1.9 1/30/03
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X9521 – Preliminary Information
ABSOLUTE MAXIMUM RATINGS
Parameter
Temperature under Bias
Min.
–65
–65
–1.0
–1.0
Max.
+135
+150
+15
+7
Units
°C
°C
V
Storage Temperature
Voltage on WP pin (With respect to Vss)
Voltage on other pins (With respect to Vss)
V
Vcc
5
V
| Voltage on R – Voltage on R | (x=1,2. Referenced to Vss)
D.C. Output Current (SDA)
Hx
Lx
0
mA
°C
V
Lead Temperature (Soldering, 10 seconds)
300
5.5
Supply Voltage Limits (Applied Vcc voltage, referenced to Vss)
2.7
RECOMMENDED OPERATING CONDITIONS
Temperature
Min.
Max.
Units
Industrial
–40
+85
°C
NOTE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
This is a stress rating only and the functional operation of the device at these or any other conditions above those listed
in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability
Figure 20. Equivalent A.C. Circuit
Vcc = 5V
2300Ω
SDA
100pF
Figure 21. DCP SPICE Macromodel
R
TOTAL
R
R
Hx
Lx
C
L
C
H
10pF
R
W
C
10pF
W
25pF
(x=1,2)
R
Wx
Characteristics subject to change without notice. 15 of 26
REV 1.1.9 1/30/03
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X9521 – Preliminary Information
TIMING DIAGRAMS
Figure 22. Bus Timing
t
t
t
t
F
HIGH
LOW
R
SCL
t
SU:DAT
t
t
t
SU:STO
SU:STA
HD:DAT
t
HD:STA
SDA IN
t
t
t
BUF
A
DH
SDA OUT
Figure 23. WP Pin Timing
START
SCL
Clk 1
Clk 9
SDA IN
WP
t
t
HD:WP
SU:WP
Figure 24. Write Cycle Timing
SCL
8th bit of last byte
ACK
SDA
t
WC
Stop
Condition
Start
Condition
Characteristics subject to change without notice. 16 of 26
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X9521 – Preliminary Information
Figure 25. DCP “Wiper Position”Timing
Rwx (x=1,2)
R
wx(n+1)
R
wx(n)
R
wx(n-1)
t
wr
Time
n = tap position
SCL
SDA
1
0
1
0
1
1
1
0
D7 D6 D5 D4 D3 D2 D1 D0
DATA BYTE
S
T
A
R
T
A
C
K
WT
0
0
0
0
0
P1 P0
A
C
K
A
C
K
S
T
O
P
SLAVE ADDRESS BYTE
INSTRUCTION BYTE
Characteristics subject to change without notice. 17 of 26
REV 1.1.9 1/30/03
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X9521 – Preliminary Information
D.C. OPERATING CHARACTERISTICS
Symbol
Parameter
Min Typ
Max
Unit
Test Conditions / Notes
Current into V Pin
CC
(X9521: Active)
Read memory array (3)
Write nonvolatile memory
f
= 400KHz
ICC1(1)
SCL
0.4
1.5
mA
V
= V
CC
Current into V Pin
SDA
CC
WP = Vss or Open/Floating
V =V (when no bus activity
SCL
(X9521:Standby)
With 2-Wire bus activity (3)
No 2-Wire bus activity
ICC2(2)
µA
50
50
CC
else f
= 400kHz)
SCL
VIN (4) = GND to V
CC.
Input Leakage Current (SCL, SDA)
Input Leakage Current (WP)
0.1
10
10
µA
µA
I
LI
V
= V to V with all other
CC
IN
SS
I
I
Analog Input Leakage
1
10
µA
ai
analog pins floating
VOUT (5) = GND to V
CC.
Output Leakage Current (SDA)
0.1
10
µA
LO
X9521 is in Standby(2)
V (6)
Input LOW Voltage (SCL, SDA, WP)
Input HIGH Voltage (SCL,SDA, WP)
SDA Output Low Voltage
-0.5
2.0
0.8
V
V
V
IL
V
CC
VIH (6)
+0.5
V
I
= 2.0mA
0.4
OLx
SINK
Notes: 1. The device enters the Active state after any START, and remains active until: 9 clock cycles later if the Device Select Bits in the
Slave Address Byte are incorrect; 200nS after a STOP ending a read operation; or t after a STOP ending a write operation.
WC
Notes: 2. The device goes into Standby: 200nS after any STOP, except those that initiate a high voltage write cycle; t
after a STOP that
WC
initiates a high voltage cycle; or 9 clock cycles after any START that is not followed by the correct Device Select Bits in the Slave
Address Byte.
Notes: 3. Current through external pull up resistor not included.
Notes: 4.
Notes: 5.
Notes: 6.
V
= Voltage applied to input pin.
IN
V
= Voltage applied to output pin.
OUT
Min. and V Max. are for reference only and are not tested
V
IL
IH
Characteristics subject to change without notice. 18 of 26
REV 1.1.9 1/30/03
www.xicor.com
X9521 – Preliminary Information
A.C. CHARACTERISTICS (See Figure 22, Figure 23, Figure 24)
400kHz
Symbol
Parameter
Min
0
Max
Units
KHz
ns
f
t
t
t
t
t
t
t
t
t
t
t
SCL Clock Frequency
400
SCL
IN (5)
Pulse width Suppression Time at inputs
SCL LOW to SDA Data Out Valid
Time the bus free before start of new transmission
Clock LOW Time
50
(5)
AA
0.1
1.3
1.3
0.6
0.6
0.6
100
0
0.9
µs
(5)
µs
BUF
µs
LOW
Clock HIGH Time
µs
HIGH
Start Condition Setup Time
Start Condition Hold Time
Data In Setup Time
µs
SU:STA
HD:STA
SU:DAT
HD:DAT
SU:STO
µs
ns
Data In Hold Time
µs
Stop Condition Setup Time
Data Output Hold Time
0.6
50
µs
(5)
DH
ns
t (5)
SDA and SCL Rise Time
300
300
ns
20 +.1Cb (2)
R
t (5)
SDA and SCL Fall Time
WP Setup Time
ns
µs
µs
pF
20 +.1Cb (2)
F
t
0.6
0
SU:WP
t
WP Hold Time
HD:WP
Cb
Capacitive load for each bus line
400
A.C.TEST CONDITIONS
Input Pulse Levels
0.1V
CC
to 0.9V
CC
Input Rise and Fall Times
Input and Output Timing Levels
Output Load
10ns
0.5V
CC
See Figure 20
NONVOLATILE WRITE CYCLE TIMING
Symbol
Parameter
Min.
Typ.(1)
Max.
10
Units
tWC(4)
Nonvolatile Write Cycle Time
5
ms
CAPACITANCE (T = 25˚C, F = 1.0 MHZ, V = 5V)
A
CC
Parameter
Symbol
Max
Units
Test Conditions
= 0V
V
C
OUT (5)
Output Capacitance (SDA, V1RO, V2RO, V3RO)
Input Capacitance (SCL, WP)
8
pF
pF
OUT
V
= 0V
C
IN (5)
6
IN
Notes: 1. Typical values are for T = 25˚C and V
Notes: 2. Cb = total capacitance of one bus line in pF.
= 5.0V
A
CC
Notes: 3. Over recommended operating conditions, unless otherwise specified
Notes: 4.
t
is the time from a valid STOP condition at the end of a write sequence to the end of the self-timed internal nonvolatile write
WC
cycle. It is the minimum cycle time to be allowed for any nonvolatile write by the user, unless Acknowledge Polling is used.
Notes: 5. This parameter is not 100% tested.
Characteristics subject to change without notice. 19 of 26
REV 1.1.9 1/30/03
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X9521 – Preliminary Information
POTENTIOMETER CHARACTERISTICS
Limits
Symbol
Parameter
Min.
–20
Vss
Vss
Typ.
Max.
Units
%
Test Conditions/Notes
R
End to End Resistance Tolerance
+20
TOL
V
R
Terminal Voltage (x=1,2)
V
V
RHx
H
CC
V
R Terminal Voltage (x=1,2)
L
V
V
RLx
CC
R
R
= 10 KΩ (DCP1)
10
5
mW
mW
TOTAL
P
R
Power Rating (1)(6)
= 100 KΩ (DCP2)
TOTAL
I
= 1mA, V = 5 V, V
RHx
=
W
CC
200
400
400
Ω
Vcc, V
= Vss (x=1,2).
RLx
R
DCP Wiper Resistance
W
I
= 1mA, V = 2.7 V, V
=
W
CC
RHx
1200
4.4
Ω
Vcc, V
= Vss (x=1,2)
RLx
I
Wiper Current (6)
Noise
mA
W
mV /
R
R
= 10 kΩ ( DCP1)
TOTAL
sqt(Hz)
mV /
sqt(Hz)
= 100 kΩ (DCP2)
TOTAL
MI(4)
MI(4)
R
R
R
R
– R
-1
-1
+1
+1
Absolute Linearity (2)
Relative Linearity (3)
w(n)(actual)
w(n)(expected)
]
w(n)+MI
– [R
w(n+1)
= 10 kΩ (DCP1)
= 100 kΩ (DCP2)
300
300
ppm/°C
ppm/°C
pF
TOTAL
TOTAL
R
Temperature Coefficient
TOTAL
C /C /
Potentiometer Capacitances
10/10/
25
H
L
See Figure 21.
See Figure 25.
C
W
t
Wiper Response time (6)
200
75
µs
V
wcr
V
Vcc power up DCP recall threshold
Vcc power up DCP recall delay time (6)
TRIP
t
25
50
ms
PU
Notes: 1. Power Rating between the wiper terminal R
and the end terminals R or R - for ANY tap position n, (x=1,2).
HX LX
WX(n)
Notes: 2. Absolute Linearity is utilized to determine actual wiper resistance versus, expected resistance
(expected)) = 1 Ml Maximum (x=1,2).
=
(R
(actual) –
wx(n)
R
wx(n)
Notes: 3. Relative Linearity is a measure of the error in step size between taps = R
– [R
+ Ml] = 1 Ml (x=0,1,2)
wx(n)
Wx(n+1)
Notes: 4. 1 Ml = Minimum Increment = R
/ (Number of taps in DCP - 1).
TOT
Notes: 5. Typical values are for T = 25°C and nominal supply voltage.
A
Notes: 6. This parameter is periodically sampled and not 100% tested.
Characteristics subject to change without notice. 20 of 26
REV 1.1.9 1/30/03
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X9521 – Preliminary Information
20-Bump Chip Scale Package (CSP B20)
Package Outline Drawing
a
d
f
A4
B4
C4
D4
E4
A3
B3
C3
D3
E3
A2
B2
C2
D2
E2
k
A1
B1
C1
D1
E1
b
j
m
l
e
Top View (Marking Side)
Bottom View (Bumped Side)
Side View
e
c
Side View
Package Dimensions
Ball Matrix:
4
3
2
1
Millimeters
Min Nominal Max
Inches
Min Nominal Max
Symbol
A
B
C
D
E
RL2 RW2
Vcc
NC
NC
NC
NC
RH1
Vss
Package Width
a
b
c
d
e
f
2.542
3.812
0.644
0.444
0.200
0.300
2.572
3.842
0.677
0.457
0.220
0.320
0.5
2.602
3.872
0.710
0.470
0.240
0.340
NC
WP
RH2
NC
Package Length
NC
Package Height
SCL
SDA
NC
NC
Body Thickness
RL1
RW1
Ball Height
Ball Diameter
Ball Pitch – Width
Ball Pitch – Length
Ball to Edge Spacing – Width
Ball to Edge Spacing – Length
j
k
l
0.5
0.511
0.896
0.536
0.921
0.561
0.946
m
Characteristics subject to change without notice. 21 of 26
REV 1.1.9 1/30/03
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X9521 – Preliminary Information
APPENDIX 1
DCP1 (100 Tap) Tap position to Data Byte translation Table
Data Byte
Tap
Position
Decimal
Binary
0
1
0
1
0000 0000
0000 0001
.
.
.
.
.
.
23
24
25
26
23
24
56
55
0001 0111
0001 1000
0011 1000
0011 0111
.
.
.
.
.
.
48
49
50
51
33
32
64
65
0010 0001
0010 0000
0100 0000
0100 0001
.
.
.
.
.
.
73
74
75
76
87
88
0101 0111
0101 1000
0111 1000
0111 0111
120
119
.
.
.
.
.
.
98
99
97
96
0110 0001
0110 0000
Characteristics subject to change without notice. 22 of 26
REV 1.1.9 1/30/03
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X9521 – Preliminary Information
APPENDIX 2
DCP1 (100 Tap) tap position to Data Byte translation algorithm example. (Example 1)
unsigned DCP1_TAP_Position(int tap_pos)
{
int block;
int i;
int offset;
int wcr_val;
offset= 0;
block = tap_pos / 25;
if (block < 0) return ((unsigned)0);
else if (block <= 3)
{
switch(block)
{ case (0): return ((unsigned)tap_pos) ;
case (1):
{
wcr_val = 56;
offset = tap_pos - 25;
for (i=0; i<= offset; i++) wcr_val-- ;
return ((unsigned)++wcr_val);
}
case (2):
{
wcr_val = 64;
offset = tap_pos - 50;
for (i=0; i<= offset; i++) wcr_val++ ;
return ((unsigned)--wcr_val);
}
case (3):
{
wcr_val = 120;
offset = tap_pos - 75;
for (i=0; i<= offset; i++) wcr_val-- ;
return ((unsigned)++wcr_val);
}
}
}
return((unsigned)01100000);
}
Characteristics subject to change without notice. 23 of 26
REV 1.1.9 1/30/03
www.xicor.com
X9521 – Preliminary Information
APPENDIX 2
DCP1 (100 Tap) tap position to Data Byte translation algorithm example. (Example 2)
unsigned DCP100_TAP_Position(int tap_pos)
{
/* optional range checking
*/ if (tap_pos < 0) return ((unsigned)0);
else if (tap_pos >99) return ((unsigned) 96);
/* set to min val */
/* set to max val */
/* 100 Tap DCP encoding formula */
if (tap_pos > 74)
return ((unsigned) (195 - tap_pos));
else if (tap_pos > 49)
return ((unsigned) (14 + tap_pos));
else if (tap_pos > 24)
return ((unsigned) (81 - tap_pos));
else return (tap_pos);
}
Characteristics subject to change without notice. 24 of 26
REV 1.1.9 1/30/03
www.xicor.com
X9521 – Preliminary Information
20-LEAD PLASTIC, TSSOP PACKAGE TYPE V
.025 (.65) BSC
.169 (4.3)
.177 (4.5)
.252 (6.4) BSC
.252 (6.4)
.260 (6.6)
.047 (1.20)
.0075 (.19)
.0118 (.30)
.002 (.05)
.006 (.15)
(7.72)
(4.16)
.010 (.25)
Gage Plane
0° – 8°
Seating Plane
(1.78)
(0.42)
.019 (.50)
.029 (.75)
DetailA (20X)
(0.65)
ALL MEASUREMENTS ARE TYPICAL
.031 (.80)
.041 (1.05)
See Detail “A”
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
Characteristics subject to change without notice. 25 of 26
REV 1.1.9 1/30/03
www.xicor.com
X9521 – Preliminary Information
ORDERING INFORMATION
X9521
P
T
Device
Temperature Range
I = Industrial –40°C to +85°C
Package
V20 = 20-Lead TSSOP
B20 = 20-Lead CSP
LIMITED WARRANTY
Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty,
express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement.
Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and
prices at any time and without notice.
Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, or licenses are implied.
TRADEMARK DISCLAIMER:
Xicor and the Xicor logo are registered trademarks of Xicor, Inc. AutoStore, Direct Write, Block Lock, SerialFlash, MPS, and XDCP are also trademarks of Xicor, Inc.
All others belong to their respective owners.
U.S. PATENTS
Xicor products are covered by one or more of the following U.S. Patents: 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461;
4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829,482; 4,874,967; 4,883,976; 4,980,859; 5,012,132; 5,003,197; 5,023,694; 5,084,667; 5,153,880;
5,153,691; 5,161,137; 5,219,774; 5,270,927; 5,324,676; 5,434,396; 5,544,103; 5,587,573; 5,835,409; 5,977,585. Foreign patents and additional patents
pending.
LIFE RELATED POLICY
In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error
detection and correction, redundancy and back-up features to prevent such an occurence.
Xicor’s products are not authorized for use in critical components in life support devices or systems.
1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure
to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the
user.
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or effectiveness.
Characteristics subject to change without notice. 26 of 26
REV 1.1.9 1/30/03
www.xicor.com
相关型号：
X9521V20IZ-B
DUAL 100K DIGITAL POTENTIOMETER, 2-WIRE SERIAL CONTROL INTERFACE, 256 POSITIONS, PDSO20, ROHS COMPLIANT, PLASTIC, TSSOP-20
RENESAS
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