ZSC31150GEB [RENESAS]
Fast Automotive Sensor Signal Conditioner;
| 型号： | ZSC31150GEB |
| 厂家： | 
RENESAS TECHNOLOGY CORP |
| 描述： | Fast Automotive Sensor Signal Conditioner |
| 文件： | 总27页 (文件大小：771K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ZSC31150
Fast Automotive Sensor Signal Conditioner
Datasheet
Brief Description
Benefits
The ZSC31150 is a CMOS integrated circuit for highly accurate
amplification and sensor-specific correction of bridge sensor
signals. Digital compensation of sensor offset, sensitivity,
temperature drift, and non-linearity is accomplished via an internal
16-bit RISC microcontroller running a correction algorithm, with
calibration coefficients stored in an EEPROM.
.
.
.
No external trimming components required
Only a few external protection devices needed
PC-controlled configuration and single pass calibration via
I2C or ZACwire™ interface: simple, cost efficient, quick, and
precise
.
.
End-of-line calibration via I2C or ZACwire™ interface
The ZSC31150 is adjustable to nearly all bridge sensor types.
Measured values are provided at the analog voltage output or at
the digital ZACwire™ and I2C interface. The digital interface can
be used for a simple PC-controlled calibration procedure in order
to program a set of calibration coefficients into an on-chip
EEPROM. A specific sensor and a ZSC31150 can be mated
digitally: fast, precise, and without the cost overhead associated
with trimming by external devices or a laser.
High accuracy (0.25% FSO at -25 to 85°C; 0.5% FSO
at -40°C to 125°C)
.
Excellent EMC/ESD robustness and AEC-Q100 qualification
Available Support
.
.
.
Evaluation Kits
Application Notes
Mass Calibration System
Features
.
Digital compensation of sensor offset, sensitivity,
temperature drift, and non-linearity
Physical Characteristics
.
.
.
Adjustable to nearly all bridge sensor types
Analog gain of up to 420
.
Supply voltage: 4.5V to 5.5V
Output options: ratiometric analog voltage output (5% to 95%
maximum, 12.4-bit resolution) or ZACwire™ (digital one-wire-
interface)
.
Operation temperature: -40°C to 125°C
(-40°C to +150°C extended temperature range)
.
Available as 14-DFN (5 4 mm; wettable flanks), SSOP14,
and die
.
Temperature compensation: internal or external diode, bridge
resistance, thermistor
.
.
.
.
.
.
Sensor biasing by voltage or constant current
Sample rate: up to 7.8kHz
ZSC31150 Application Circuit
High voltage protection up to 33V
Supply current: max. 5.5mA
Out / OWI
GND
Reverse polarity and short-circuit protection
C2
100nF
Wide operation temperature depending on part number: up to
-40°C to +150°C
8
7
6
5
4
3
2
1
VSSE
AOUT
VBN
VDDE
VDD
n.c.
VSUPP
+4.5V to +5.5V
C3
47nF
9
Sensor Bridge
.
.
Traceability by user-defined EEPROM entries
Safety and diagnostic functions
10
11
12
13
14
VBR_B
VBP
SCL
SCL
Serial Interface
SDA
SDA
VBR_T
IRTEMP
VSSA
VDDA
C4
C5
C1
100nF
Temperature Sensor
1
December 6, 2016
ZSC31150
Block Diagram
ZACwire™
Digital
Data I/O
RAM
EEPROM
I2C
Analog
Out
PGA
TS
ADC
CMC
DAC
BAMP
ROM
Analog Block
Digital Block
ZSC31150
Ordering Information
Sales Code
Description
Package
ZSC31150GE
ZSC31150 Die – Temperature range: -40°C to +150°C
Unsawn on Wafer: add “B” to sales code
Sawn on Wafer Frame: add “C”
Waffle Pack: add “D”
ZSC31150GEG2-R
ZSC31150GAG2-R
Tape and Reel
ZSC31150 14-DFN (5 4 mm; wettable flanks) – Temperature
range: -40°C to 150°C
Tape and Reel
ZSC31150 14-DFN (5 4 mm; wettable flanks) – Temperature
range: -40°C to 125°C
ZSC31150GAB
ZSC31150GAC
ZSC31150GEG1
ZSC31150GLG1
ZSC31150 Die – Temperature range: -40°C to +125°C
ZSC31150 Die – Temperature range: -40°C to +125°C
ZSC31150 14-SSOP – Temperature range: -40°C to +150°C
Unsawn on Wafer
Sawn on Wafer Frame
Tube: add “-T” to sales code
Tape & Reel: add “-R”
ZSC31150 14-SSOP – Temperature range: -40°C to +150°C
(Long life: 5000h @150°C)
ZSC31150GAG1
ZSC31150 14-SSOP – Temperature range: -40°C to +125°C
ZSC31150KITV1P2
ZSC31150 SSC Evaluation Kit V1.2: Three interconnecting boards, five ZSC31150 SSOP14 samples, USB cable
(software can be downloaded from product page at www.IDT.com/ZSC31150)
ZSC31150MCSV1P1
Modular Mass Calibration System (MSC) V1.1 for ZSC31150: MCS boards, cable, connectors (software can be
downloaded from product page)
2
December 6, 2016
Contents
1. Electrical Characteristics ..............................................................................................................................................................................5
1.1 Absolute Maximum Ratings.................................................................................................................................................................5
1.2 Operating Conditions...........................................................................................................................................................................5
1.3 Electrical Parameters ..........................................................................................................................................................................6
1.3.1
1.3.2
1.3.3
1.3.4
1.3.5
1.3.6
1.3.7
Supply Current and System Operation Conditions...............................................................................................................6
Analog Front-End (AFE) Characteristics ..............................................................................................................................6
Temperature Measurement [b]...............................................................................................................................................6
Analog-to-Digital Conversion (ADC).....................................................................................................................................7
Sensor Connection Check....................................................................................................................................................7
Digital-to-Analog Conversion (DAC) and Analog Output (AOUT Pin) ..................................................................................7
System Response ................................................................................................................................................................8
1.4 Interface Characteristics and EEPROM ..............................................................................................................................................8
1.4.1
1.4.2
1.4.3
I2C Interface [a] ......................................................................................................................................................................8
ZACwire™ One Wire Interface (OWI) ..................................................................................................................................9
EEPROM..............................................................................................................................................................................9
2. Circuit Description ......................................................................................................................................................................................10
2.1 Signal Flow........................................................................................................................................................................................10
2.2 Application Modes .............................................................................................................................................................................10
2.3 Analog Front End (AFE) ....................................................................................................................................................................11
2.3.1
2.3.2
2.3.3
2.3.4
Programmable Gain Amplifier (PGA) .................................................................................................................................11
Offset Compensation..........................................................................................................................................................11
Measurement Cycle............................................................................................................................................................12
Analog-to-Digital Converter ................................................................................................................................................13
2.4 Temperature Measurement...............................................................................................................................................................15
2.5 System Control and Conditioning Calculation ...................................................................................................................................15
2.5.1
2.5.2
2.5.3
Operation Modes................................................................................................................................................................15
Start Up Phase ...................................................................................................................................................................15
Conditioning Calculation.....................................................................................................................................................16
2.6 Analog Output AOUT.........................................................................................................................................................................16
2.7 Serial Digital Interface .......................................................................................................................................................................16
2.8 Failsafe Features, Watchdog and Error Detection.............................................................................................................................17
2.9 High Voltage, Reverse Polarity, and Short Circuit Protection............................................................................................................17
3. Application Circuit Examples......................................................................................................................................................................18
4. Pin Configuration, Latch-Up and ESD Protection.......................................................................................................................................20
4.1 Pin Configuration and Latch-up Conditions .......................................................................................................................................20
4.2 ESD Protection..................................................................................................................................................................................20
5. Package......................................................................................................................................................................................................21
5.1 SSOP14 Package..............................................................................................................................................................................21
5.2 14-DFNPackage................................................................................................................................................................................21
3
December 6, 2016
6. Quality and Reliability.................................................................................................................................................................................22
7. Customization.............................................................................................................................................................................................22
8. Ordering Information...................................................................................................................................................................................23
9. Related Documents and Tools ...................................................................................................................................................................23
10. Glossary .....................................................................................................................................................................................................24
11. Document Revision History ........................................................................................................................................................................25
List of Figures
Figure 2.1 Block Diagram of the ZSC31150.......................................................................................................................................................10
Figure 2.2 Measurement Cycle...........................................................................................................................................................................13
Figure 3.1 Bridge in Voltage Mode, External Diode Temperature Sensor..........................................................................................................18
Figure 3.2 Bridge in Voltage Mode, External Thermistor....................................................................................................................................19
Figure 3.3 Bridge in Current Mode, Temperature Measurement via Bridge TC .................................................................................................19
Figure 5.1 SSOP14 Pin Diagram........................................................................................................................................................................21
Figure 5.2 Outline Drawing for 14-DFN Package with Wettable Flanks .............................................................................................................22
List of Tables
Table 1.1 Absolute Maximum Ratings.................................................................................................................................................................5
Table 1.2 Operating Conditions...........................................................................................................................................................................5
Table 1.3 Electrical Parameters ..........................................................................................................................................................................6
Table 1.4 Interface and EEPROM Characteristics ..............................................................................................................................................8
Table 2.1 Adjustable Gains, Resulting Sensor Signal Spans, and Common Mode Ranges .............................................................................11
Table 2.2 Analog Zero Point Shift Ranges (XZC)..............................................................................................................................................12
Table 2.3 Analog Output Resolution versus Sample Rate ................................................................................................................................14
Table 3.1 Application Circuit Parameters ..........................................................................................................................................................18
Table 4.1 Pin Configuration and Latch-Up Conditions.......................................................................................................................................20
Table 5.1 14-DFN Package Dimensions ...........................................................................................................................................................22
4
December 6, 2016
1.
Electrical Characteristics
1.1 Absolute Maximum Ratings
The absolute maximum ratings are stress ratings only. The ZSC31150 might not function or be operable above the recommended operating
conditions. Stresses exceeding the absolute maximum ratings might also damage the device. In addition, extended exposure to stresses
above the recommended operating conditions might affect device reliability. IDT does not recommend designing to the “Absolute Maximum
Ratings.”
Parameters apply in operation temperature range and without time limitations.
Table 1.1 Absolute Maximum Ratings
No.
1.1.1
Parameter
Supply voltage [a]
Symbol
VDDE
Conditions
To VSSE.
Min
-33
-33
-0.3
Max
33
Unit
VDC
VDC
VDC
Potential at the AOUT pin [a]
Analog supply voltage [a]
VOUT
Relative to VSSE.
33
1.1.2
1.1.3
VDDA
Relative to VSSA.
6.5
VDDE - VDDA < 0.35V
1.1.4
1.1.5
Voltage at all analog and
digital IO pins
VA_IO
VD_IO
Relative to VSSA.
-0.3
-55
VDDA + 0.3
150
VDC
Storage temperature
TSTG
C
[a] Refer to the ZSC31150 Technical Note – High Voltage Protection for specification and detailed conditions for high voltage protection.
1.2 Operating Conditions
All voltages are related to VSSA. See important table notes at the end of the table.
Table 1.2 Operating Conditions
No.
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
TQE ambient temperature range
for part numbers ZSC31150xExx[a]
TAMB_TQE TQE
-40
150
C
TQA ambient temperature range
for part numbers
TAMB_TQA TQA
-40
-25
125
85
C
1.2.1
ZSC31150xAxx[b]
TQI ambient temperature range
for advanced performance[b]
TAMB_TQI TQI
VDDE
C
1.2.2
1.2.3
Supply voltage
4.5
2
5.0
5.5
25
VDC
Bridge resistance—Bridge Voltage RBR_V
Mode[b], [c]
k
1.2.4
Bridge resistance—Bridge Current RBR_C
Excitation Mode[b], [c]
See specification 1.2.6 for
IBR_MAX
10
k
Current reference resistor[b],[d]
RIBR
IBR = VDDA / (16 RIBR
)
0.07 RBR
*
1.2.5
1.2.6
k
*
Maximum bridge current
IBR_MAX
2
mA
5
December 6, 2016
No.
1.2.7
1.2.8
Parameter
Symbol
VBR_TOP
TC RIBR
Conditions
Min
Typ
Max
(15/16 VDDA) - 0.3
Unit
V
*
Maximum bridge top voltage
TC current reference resistor[b]
Behavior influences current
generated
50
ppm/K
[a] Refer to the temperature profile description in the ZSC31150 Technical Note – Die and Package Specifications for operation in temperature
range > 125°C.
[b] No measurement in mass production; parameter is guaranteed by design and/or quality observation.
[c] Symmetric behavior and identical electrical properties (especially with regard to the low pass characteristic) of both sensor inputs of the
ZSC31150 are required. Unsymmetrical conditions of the sensor and/or external components connected to the sensor input pins of ZSC31150
can generate a failure in signal operation.
[d] See application circuit components in Table 3.1.
1.3 Electrical Parameters
All parameter values are valid for operating conditions specified in section 1.2 except as noted. All voltages related to VSSA. See important
table notes at the end of the table.
Table 1.3 Electrical Parameters
No.
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
1.3.1 Supply Current and System Operation Conditions
1.3.1.1
1.3.1.2
Supply current
IS
Without bridge and load
5.5
mA
current; TAMB_TQA
;
fCLK 3MHz
Clock frequency [a]
fOSC
Guaranteed adjustment range
(see the ZSC31150 Functional
Description for details);
TAMB_TQA
2
3
4
MHz
1.3.2 Analog Front-End (AFE) Characteristics
1.3.2.1
1.3.2.2
Input span
VIN_SP
Analog gain: 420 to 2.8
1
275
300
mV/V
Analog offset compensation
range
Depends on gain adjust; refer
to section 2.3.1
-300
% VIN_SP
1.3.2.3
1.3.2.4
Parasitic differential input offset
current [a]
IIN_OFF
Within TAMB_TQE
Within TAMB_TQI
-10
-2
10
2
nA
nA
V
Common mode input range
VIN_CM
Depends on gain adjustment;
no XZC; see section 2.3.1
0.29
VDDA
0.65
*
VDDA
*
1.3.3 Temperature Measurement [b]
1.3.3.1
External temperature diode
channel gain
aTSED
300
6
1300
20
ppm FS
/ (mV/V)
1.3.3.2
External temperature diode bias ITSE
current
10
A
6
December 6, 2016
No.
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
1.3.3.3
External temperature diode
input range [a]
0
1.5
V
1.3.3.4
1.3.3.5
1.3.3.6
External temperature resistor
channel gain
aTSER
VTSER
STTSI
1200
0
3500
600
ppm FS
/ (mV/V)
External temperature resistor/
input voltage range [a]
mV/V
Internal temperature diode
sensitivity
Raw values – without
conditioning
700
2700
ppm FS
/ K
1.3.4 Analog-to-Digital Conversion (ADC)
ADC resolution [a]
rADC
13
16
Bit
1.3.4.1
1.3.4.2
ADC differential nonlinearity
(DNL) [a]
DNLADC
0.95
LSB
rADC =13-bit; fCLK=3MHz;
best fit, 2nd order; complete
AFE; with ADC input range
specified in 1.3.4.5
1.3.4.3
ADC integral nonlinearity (INL)
within TQA [a]
INLADC
4
LSB
1.3.4.4
1.3.4.5
ADC INL within TQE
ADC input range
INLADC
Range
5
LSB
10
90
%VDDA
1.3.5 Sensor Connection Check
1.3.5.1
Sensor connection loss
detection threshold
RSCC_min
100
k
1.3.5.2
1.3.5.3
Sensor input short check
RSSC_short
RSSC_pass
Short detection guaranteed
0
50
Sensor input no-short threshold
A short is not indicated above
this threshold
1000
1.3.6 Digital-to-Analog Conversion (DAC) and Analog Output (AOUT Pin)
1.3.6.1
1.3.6.2
DAC resolution
rDAC
Analog output, 10-90%
VOUT: 5-95%, RLOAD 2kΩ
VOUT: 10-90%, RLOAD 1kΩ
To VSSE or VDDE [c]
@ RLOAD 2k
12
Bit
mA
Output current sink and source
for VDDE=5V
ISRC/SINK_OUT
2.5
5
mA
1.3.6.3
1.3.6.4
Short circuit current
IOUT_max
VSR_OUT95
VSR_OUT90
SROUT
-25
0.05
0.1
25
mA
Addressable output signal
range
0.95
0.9
VDDE
VDDE
V/µs
@ RLOAD 1k
Output slew rate [a]
CLOAD < 50nF
0.1
1.3.6.5
1.3.6.6
Output resistance in diagnostic
mode
ROUT_DIA
Diagnostic Range:
<4|96>%, RLOAD 2k
<8|92>%, RLOAD 1k
82
Load capacitance [a]
DNL (DAC)
CLOAD
C3 (see section 3)
150
1.5
5
nF
1.3.6.7
1.3.6.8
1.3.6.9
DNLOUT
INLOUT
-1.5
-5
LSB
LSB
INL TQA (DAC) [a]
Best fit, rDAC =12-bit
7
December 6, 2016
No.
Parameter
INL TQE (DAC)
Output leak current @150°C
Symbol
INLOUT
Conditions
Best fit, rDAC =12-bit
power or ground loss
Min
-8
Typ
Max
8
Unit
LSB
µA
1.3.6.10
1.3.6.11
ILEAK_OUT
-25
25
1.3.7 System Response
Startup time [d]
tSTA
To 1st output; fCLK=3MHz;
no ROM check; ADC 14-bit
and 2nd order
5
ms
µs
1.3.7.1
1.3.7.2
Response time (100% jump)[a]
Bandwidth [a]
tRESP
fCLK=4MHz; 13-bit, 2nd order;
refer to Table 2.3
256
512
1.3.7.3
1.3.7.4
Comparable to analog SSCs
5
kHz
mV
Analog output noise
peak-to-peak [a]
VNOISE,PP
VNOISE,RMS
REOUT_5
Shorted inputs;
bandwidth 10kHz
10
3
Analog output noise RMS [a]
Shorted inputs;
bandwidth 10kHz
mV
1.3.7.5
1.3.7.6
1.3.7.7
Ratiometricity error
Maximum error of
VDDE=5V to 4.5/5.5V
1000
ppm
Overall failure (deviation from
ideal line including the INL,
gain, offset and temperature
errors) [e]
FALL TQI
FALL TQA
FALL TQE
13-bit, 2nd order ADC;
fCLK 3MHz; XZC=0
No sensor caused effects;
value in parentheses is the
digital readout.
0.25
(0.1)
% FS
% FS
% FS
0.5
(0.25)
1.0
(0.5)
[a] No measurement in mass production; parameter is guaranteed by design and/or quality observation.
[b] Refer to section 2.4.
[c] Minimum output voltage to VDDE or maximum output voltage to VSSE.
[d] Depends on resolution and configuration - start routine begins approximately 0.8ms after power on.
[e] XZC is active: additional overall failure of 25ppm/K for XZC=31 at maximum; failure decreases linearly for XZC adjustments lower than 31.
1.4 Interface Characteristics and EEPROM
Table 1.4 Interface and EEPROM Characteristics
No.
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
1.4.1 I2C Interface [a]
Input-high level [b]
Input-low level [b],
VI2C_IN_H
0.8
VDDA
VDDA
VDDA
pF
1.4.1.1
1.4.1.2
1.4.1.3
1.4.1.4
VI2C_IN_L
VI2C_OUT_L
CSDA
0.2
0.15
400
Output-low level [b]
SDA load capacitance [b]
Open Drain, IOL<2mA
8
December 6, 2016
No.
Parameter
Symbol
fSCL
RI2C
Conditions
Min
Typ
Max
400
100
Unit
kHz
k
SCL clock frequency [b]
Internal pull-up resistor [b]
1.4.1.5
1.4.1.6
25
1.4.2 ZACwire™ One Wire Interface (OWI)
Input-low level [b]
VOWI_IN_L
VOWI_IN_H
ROWI_PUP
COWI_LOAD
0.2
VDDA
VDDA
k
1.4.2.1
1.4.2.2
1.4.2.3
1.4.2.4
1.4.2.5
Input-high level [b]
0.75
0.3
Pull-up resistance master
OWI load capacitance
Start window [b]
3.3
Summarized OWI line load
Typ: @ fCLK=3MHz
50
nF
96
175
455
ms
1.4.3 EEPROM
1.4.3.1
Ambient temperature
TAMB_EEP
nWRI_EEP
-40
150
C
EEPROM programming [b]
Write cycles [b]
Write temperature: <=85°C
100k
100
1.4.3.2
Write temperature:
up to 150°C
Read cycles [b], [c]
nREAD_EEP
tRET_EEP
Read temperature:
<=175°C
8 * 108
15
1.4.3.3
1.4.3.4
Data retention [b], [d]
1300h at 175°C =100000h
at 55°C; 27000h at 125°C;
3000h at 150°C)
years
ms
Programming time [b]
tWRI_EEP
Per written word,
fCLK=3MHz
12
1.4.3.5
[a] Refer to the ZSC31150 Functional Description for timing details.
[b] No measurement in mass production; parameter is guaranteed by design and/or quality observation.
[c] Note that the package and temperature versions cause additional restrictions.
[d] Over lifetime; use calculation sheet SSC Temperature Profile Calculation Spreadsheet for temperature stress calculation; note additional restrictions are caused by
different package and temperature versions.
9
December 6, 2016
2.
Circuit Description
Note: This data sheet provides specifications and a general overview of ZSC31150 operation. For details of operation, including configuration
settings and related EEPROM registers, refer to the ZSC31150 Functional Description.
2.1 Signal Flow
The ZSC31150’s signal path includes both analog (shown in blue in Figure 2.1) and digital (pink) sections. The analog path is differential; i.e.,
the differential bridge sensor signal is handled internally via two signal lines that are symmetrical around a common mode potential (analog
ground = VDDA/2), which improves noise rejection.
Consequently, it is possible to amplify positive and negative input signals, which are located within the common mode range of the signal
input.
Figure 2.1 Block Diagram of the ZSC31150
ZACwire™
Digital
Data I/O
RAM
EEPROM
I2C
Analog
Out
PGA
TS
ADC
CMC
DAC
BAMP
ROM
Analog Block
Digital Block
ZSC31150
The differential signal from the bridge sensor is pre-amplified by the programmable gain amplifier (PGA). The multiplexer (MUX) transmits the
signals from either the bridge sensor, the external diode, or the separate temperature sensor to the analog-to-digital converter (ADC) in a
specific sequence (the internal pn-junction (TS) can be used instead of the external temperature diode). Next, the ADC converts these signals
into digital values.
The digital signal correction takes place in the calibration microcontroller (CMC). It is based on a correction formula located in the ROM and
sensor-specific coefficients stored in the EEPROM during calibration. Depending on the programmed output configuration, the corrected
sensor signal is output as an analog value or in a digital format (I2C or ZACwire™). The configuration data and the correction parameters can
be programmed into the EEPROM via the digital interfaces.
2.2 Application Modes
For each application, a configuration set must be established (generally prior to calibration) by programming the on-chip EEPROM regarding
to the following modes:
Sensor Channel
.
.
Sensor mode: ratiometric bridge excitation in voltage or current supply mode.
Input range: the gain adjustment of the AFE with respect to the maximum sensor signal span and the zero point of the ADC have to be
chosen.
.
.
An additional analog offset compensation, the Extended Zero-Point Compensation (XZC), must be enabled if required; e.g., if the sensor
offset voltage is close to or larger than the sensor span.
Resolution/response time: The ADC must be configured for resolution and conversion settings (1st or 2nd order). These settings influence
the sampling rate, signal integration time, and, as a result, the noise immunity.
Temperature
Temperature measurement: the source for the temperature correction must be chosen.
.
10
December 6, 2016
2.3 Analog Front End (AFE)
The analog front end (AFE) consists of the programmable gain amplifier (PGA), the multiplexer (MUX), and the analog-to-digital converter
(ADC).
2.3.1 Programmable Gain Amplifier (PGA)
Table 2.1 shows the adjustable gains, the sensor signal spans, and the allowed common mode range.
Table 2.1 Adjustable Gains, Resulting Sensor Signal Spans, and Common Mode Ranges
Input Common Mode Range
Max. Span
VIN_SP
[mV/V] [a]
VIN_CM as % of VDDA [b]
Overall Gain
aIN
Gain
Amp1
Gain
Amp2
Gain
Amp3
No.
1
XZC = Off
29 to 65
29 to 65
29 to 65
29 to 65
29 to 65
29 to 65
29 to 65
29 to 65
29 to 65
29 to 65
29 to 65
29 to 65
32 to 57
XZC = On
45 to 55
45 to 55
45 to 55
45 to 55
45 to 55
45 to 55
45 to 55
45 to 55
45 to 55
45 to 55
45 to 55
45 to 55
not applicable
420
280
210
140
105
70
1.8
2.7
30
30
15
15
7.5
7.5
3.75
3.75
3.75
1
7
4.66
7
2
2
2
2
2
2
2
2
2
2
2
2
2
2
3
3.6
4
5.4
4.66
7
5
7.1
6
10.7
14.3
21.4
28.5
53.75
80
4.66
7
7
52.5
35
8
4.66
3.5
7
9
26.3
14
10
11
12
13
9.3
7
1
4.66
3.5
1.4
107
267
1
2.8
1
[a] Recommended internal signal range maximum is 80% of the VDDA voltage. Span is calculated by the following formula:
Span = 80% / gain.
[b] Bridge in Voltage Mode with maximum input signal (with XZC = +300% Offset), 14-bit accuracy. Refer to the ZSC31150 Functional
Description for usable input signal/common mode range at bridge in current mode. See section 2.3.2 for an explanation of the extended
analog zero compensation (XZC).
2.3.2 Offset Compensation
The ZSC31150 supports two methods of sensor offset compensation (zero shift):
.
.
Digital offset correction
XZC: analog compensation for large offset values (up to a maximum of approximately 300% of the span, depending on the gain
adjustment)
The digital sensor offset correction will be processed during the digital signal correction/conditioning by the calibration microcontroller (CMC).
Analog sensor offset pre-compensation is needed for compensation of large offset values, which would overdrive the analog signal path by
uncompensated gaining. For analog sensor offset pre-compensation, a compensation voltage is added in the analog pre-gaining signal path
(coarse offset removal). The analog offset compensation in the AFE can be adjusted by 6 EEPROM bits (refer to the ZSC31150 Functional
Description for details).
11
December 6, 2016
Table 2.2 Analog Zero Point Shift Ranges (XZC)
PGA gain
aIN
Max. Span VIN_SP
[mV/V]
Offset shift per step
as % of full span
Approximate maximum
offset shift [mV/V]
Approximate maximum
shift [% VIN_SP] (at ± 31)
420
280
210
140
105
70
1.8
2.7
12.5%
7.6%
7.8
7.1
15.5
14.2
31
388%
237%
388%
237%
388%
237%
388%
237%
161%
388%
237%
161%
26%
3.6
12.5%
7.6%
5.4
7.1
12.5%
7.6%
10.7
14.3
21.4
28.5
53.75
80
28
52.5
35
12.5%
7.6%
32
57
26.3
14
5.2%
52
12.5%
7.6%
194
189
161
72
9.3
7
107
267
5.2%
2.8
0.83%
2.3.3 Measurement Cycle
The complete measurement cycle is controlled by the CMC. Depending on EEPROM settings, the multiplexer (MUX) selects the following
input signals in a defined sequence:
.
.
.
Temperature measured by external diode or thermistor, internal pn-junction, or bridge
Internal offset of the input channel (VOFF
Pre-amplified bridge sensor signal
)
The cycle diagram in Figure 2.2 shows the basic structure of the measurement cycle. The bridge sensor measurement count can be
configured in EEPROM for a value within n=<1,31>.
After power-on, the startup routine is processed, which performs all measurements needed to acquire an initial valid conditioned sensor
output. After the startup routine, the normal measurement cycle runs.
Note: The “CMV,” “SSC/SCC+” and “SSC/SCC-” measurements are always performed in every cycle independent of the EEPROM
configuration.
12
December 6, 2016
Figure 2.2 Measurement Cycle
Start Routine
1
n
1
n
1
n
1
n
1
n
1
n
Temperature auto-zero
Bridge sensor measurement
Temperature measurement
Bridge sensor measurement
Bridge sensor auto-zero
Bridge sensor measurement
CMV
Bridge sensor measurement
SSC/SCC+
Bridge sensor measurement
SSC/SCC-
Bridge sensor measurement
2.3.4 Analog-to-Digital Converter
The ADC is an integrating analog-to-digital converter in full differential switched capacitor technique.
Programmable ADC resolutions are rADC=<13, 14> or with segmentation, rADC=<15, 16> bit.
The ADC can be used as a first or second order converter. In the first order mode, it is inherently monotone and insensitive to short and
long-term instability of the clock frequency. The conversion cycle time depends on the desired resolution and can be roughly calculated by the
following equation where rADC is the ADC resolution and tADC_1 is the conversion cycle time in seconds in first-order mode:
2rADC
tADC_1
f
OSC
2
In the second order mode, two conversions are stacked with the advantage of a much shorter conversion cycle time but the drawback of a
lower noise immunity caused by the shorter signal integration period. The approximate conversion cycle time tADC_2 in second-order mode is
calculated by the following equation:
ADC 3) / 2
2(r
tADC_2
f
OSC
2
The calculation formulas for tADC give an overview of conversion time for one AD conversion. Refer to the ZSC31150 Bandwidth Calculation
Spreadsheet for detailed calculations for sampling time and bandwidth.
13
December 6, 2016
The result of the AD conversion is a relative counter result corresponding to the following equation (see the ZSC31150 Functional Description
for more detailed equations):
ZADC
rADC
Number of counts (result of the conversion)
Selected ADC resolution in bits
VADC_DIFF
r
ADC
ZADC 2
RSADC
VADC_REF
VADC_DIFF Differential input voltage of the ADC
VADC_REF Reference voltage of the ADC
1
1
1
1
RSADC Digital ADC range shift (RSADC = /16, /8, /4, /2, controlled by the
EEPROM setting)
The sensor input signal can be shifted to the optimal input range of the ADC with the RSADC value.
Table 2.3 Analog Output Resolution versus Sample Rate
ADC
Adjustment
Approximated Output
Resolution [a]
Sample Rate
Averaged
Bandwidth at fCLK
[b]
fCON
rADC
[Bit]
13
Digital
[Bit]
13
Analog
[Bit]
12
fCLK=3MHz
fCLK=4MHz
[Hz]
fCLK=3MHz
fCLK=4MHz
[Hz]
172
ADC Order
[Hz]
345
178
90
[Hz]
130
67
460
14
14
12
237
89
1
2
15
14
12
120
34
45
16
14
12
45
61
17
23
13
13
12
5859
3906
2930
1953
7813
5208
3906
2604
2203
1469
1101
734
2937
1958
1468
979
14
14
12
15
14
12
16
14
12
[a] The ADC resolution should be one bit higher than the required output resolution if the AFE gain is adjusted so that more than 50% of the input
range is used. Otherwise the ADC resolution should be more than one bit higher than the required output resolution.
[b] The sampling rate (A/D conversion time) is only a part of the whole cycle; refer to the ZSC31150 Bandwidth Calculation Spreadsheet for
detailed information.
Note: The ADC’s reference voltage ADCVREF is defined by the potential between <VBR_T> and <VBR_B> (or <VDDA> to <VSSA>, if
selected in EEPROM by the bit CFGAPP:BREF=1). Theoretically, the input range ADCRANGE_INP of the ADC is equivalent to the ADC’s
reference voltage.
In practice, the maximum ADC input range used should be from 10% to 90% of ADCRANGE_INP, which is a necessary condition for ensuring the
specified accuracy, stability, and nonlinearity parameters of the AFE. This condition is also valid for whole temperature range and all
applicable sensor tolerances. The ZSC31150 does not have an internal failsafe function that verifies that the input meets this condition.
14
December 6, 2016
2.4 Temperature Measurement
The ZSC31150 supports four different methods for acquiring the temperature data needed for calibration of the sensor signal in the specified
temperature range.
Temperature data can be acquired using one of these temperature sensors:
.
.
.
.
an internal pn-junction temperature sensor
an external pn-junction temperature sensor connected to sensor top potential (VBRTOP
an external resistive half bridge temperature sensor
)
the temperature coefficient of the sensor bridge at bridge current excitation
Refer to the ZSC31150 Functional Description for a detailed explanation of temperature sensor adaptation and adjustment.
2.5 System Control and Conditioning Calculation
The system control supports the following tasks/features:
.
.
Controlling the measurement cycle according to the EEPROM-stored configuration data
Performing the16-bit correction calculation for each measurement signal using the EEPROM-stored calibration coefficients and ROM-
based algorithms; i.e., the signal conditioning
.
.
.
Managing the start-up sequence and starting signal conditioning
Handling communication requests received by the digital interface
Managing failsafe tasks for the functions of the ZSC31150 and indicating detected errors with diagnostic states
Refer to the ZSC31150 Functional Description for a detailed description.
2.5.1 Operation Modes
The internal state machine has three main states:
.
.
.
The continuously running signal conditioning mode, which is called Normal Operation Mode (NOM)
The calibration mode with access to all internal registers and states, which is called Command Mode (CM)
The failure messaging mode, which is called Diagnostic Mode (DM)
2.5.2 Start Up Phase
The start-up phase* consists of following segments:
1. Internal supply voltage settling phase (i.e., the VDDA - VSSA potential), which is ended when the reset signal is disabled through
the power-on clear block (POR). Refer to the ZSC31150 Technical Note – High Voltage Protection document, section 4 for power
on/off thresholds.
Time (from beginning with VDDA-VSSA=0V): 500µs to 2000µs; AOUT is in tri-state
2. System start, EEPROM read out, and signature check (and ROM check if selected by setting EEPROM bit CFGAPP:CHKROM=1).
Time: ~200µs (~9000µs with ROM-check; i.e., 28180 clocks); AOUT is LOW (DM)
3. Processing the start routine for signal conditioning (all measurements and conditioning calculations).
Time: 5 x A/D conversion time; AOUT behavior depends on selected OWI mode (refer to section 2.6):
.
.
OWIANA & OWIDIS => AOUT is LOW (DM)
OWIWIN & OWIENA => AOUT is in tri-state
* All timings described are roughly estimated values and are affected by the internal clock frequency. Timings are estimated for fCLK=3MHz.
15
December 6, 2016
The analog output AOUT will be activated at the end of the start-up phase depending on the adjusted output and communication mode (refer
to section 2.6). If errors are detected, the Diagnostic Mode (DM) is activated and the diagnostic output signal is driven at the output.
After the start-up phase, the continuously running measurement and calibration cycle is started. Refer to ZSC31150 Bandwidth Calculation
Spreadsheet for detailed information about output update rate.
2.5.3 Conditioning Calculation
The digitalized value for the bridge sensor measurement (acquired raw data) is processed with the correction formula to remove offset and
temperature dependency and to compensate nonlinearity up to 3rd order. The result of the correction calculation is a non-negative 15-bit
value for the bridge sensor in the range [0; 1). This value P is clipped with programmed limitation coefficients and continuously written to the
output register of the digital serial interface and the output DAC.
Note: The conditioning includes up to third-order nonlinearity sensor input correction. The available adjustment ranges depend on the
specific calibration parameters; for a detailed description, refer to ZSC31150 Functional Description. Basically, offset compensation and linear
correction are only limited by the loss of resolution they will cause. The second-order correction is possible up to approximately 30% of the full
scale difference from a straight line; third order is possible up to approximately 20% (ADC resolution = 13-bit). The calibration principle used
is able to reduce existing nonlinearity errors of the sensor up to 90%. The temperature calibration includes first and second order correction
and should be fairly sufficient in all relevant cases. ADC resolution also influences calibration possibilities; e.g., 1 additional bit of resolution
reduces the calibration range by approximately 50%. The maximum calculation input data width is 14-bit. The 15 or 16 bit ADC resolution
mode uses only a 14-bit segment of the ADC range.
2.6 Analog Output AOUT
The analog output is used for outputting the analog signal conditioning result and for “end of line” communication via the ZACwireTM interface
one-wire communication interface (OWI). The ZSC31150 supports four different modes of the analog output in combination with the OWI
behavior:
. OWIENA:
. OWIDIS:
. OWIWIN:
Analog output is deactivated; OWI communication is enabled.
Analog output is active (~2ms after power-on); OWI communication is disabled.
Analog output will be activated after the time window;
OWI communication is enabled in a time window of ~500ms (maximum);
transmission of the “START_CM” command must be finished during the time window.
. OWIANA:
Analog output will be activated after a ~2ms power on time;
OWI communication is enabled in a time window of ~500ms (maximum);
transmission of the START_CM” command must be finished during time window;
to communicate, the internal driven potential at AOUT must be overwritten
by the external communication master (AOUT drive capability is current limited).
The analog output potential is driven by a unity gain output buffer for which the input signal is generated by a 12.4-bit resistor-string DAC. The
output buffer (BAMP), which is a rail-to-rail op amp, is offset compensated and current limited. Therefore, a short-circuit of the analog output
to ground or the power supply does not damage the ZSC31150.
2.7 Serial Digital Interface
The ZSC31150 includes a serial digital interface (SIF), which is used for communication with the circuit to calibrate the sensor module. The
serial interface is able to communicate with two communication protocols: I2C and the ZACwire™ one-wire communication interface (OWI).
The OWI can be used to for an “end of line” calibration via the analog output AOUT of the complete assembled sensor module.
Refer to the ZSC31150 Functional Description for a detailed description of the serial interfaces and communication protocols.
16
December 6, 2016
2.8 Failsafe Features, Watchdog and Error Detection
The ZSC31150 detects various possible errors. A detected error is indicated by a change in the internal status in Diagnostic Mode (DM). In
this case, the analog output is set to LOW (minimum possible output value; i.e., the lower diagnostic range LDR) and the output registers of
the digital serial interface are set to a significant error code.
A watchdog oversees the continuous operation of the CMC and the running measurement loop. The operation of the internal clock oscillator
is verified continuously by the oscillator failure detection.
A check of the sensor bridge for broken wires is done continuously by two comparators watching the input voltage of each input (sensor
connection and short check). Additionally, the common mode voltages of the sensor and sensor input short are watched continuously (sensor
aging).
Different functions and blocks in the digital section, e.g. the RAM, ROM, EEPROM, and register content, are watched continuously. Refer to
the ZSC31150 Functional Description for a detailed description of safety features and methods of error indication.
2.9 High Voltage, Reverse Polarity, and Short Circuit Protection
The ZSC31150 is designed for 5V power supply operation.
The ZSC31150 and the connected sensor are protected from overvoltage and reverse polarity damage by an internal supply voltage limiter.
The analog output AOUT can be connected with all potentials (short circuit, over-voltage, and reverse voltage) in the protection range under
all potential conditions at the VDDE and VSSE pins.
All external components (see section 3) are required to guarantee this operation. The protection is not time limited. Refer the ZSC31150
Technical Note – High Voltage Protection for a detailed description of protection cases and conditions.
17
December 6, 2016
3. Application Circuit Examples
The application circuits contain external components that are needed for over-voltage, reverse polarity, and short circuit protection.
Recommendation: Check the ZSC31150 product page www.IDT.com/ZSC31150 for other application examples given in application notes.
Note: Some application notes require a customer login—see section 9 for details.
Table 3.1 Application Circuit Parameters
Symbol
C1
Parameter
Min
100
100
4
Typ
Max
Unit
nF
Notes
C
C
C
470
C2
nF
C3 [a]
47
160
10
nF
The value of C3 is the sum of the load capacitor and
the cable capacitance.
C4, C5 [a]
R1
C
0
nF
kΩ
Ω
Recommended to increase EMC immunity.
10
RIBR
R
Refer to section 1.2.
[a] Higher values for C3, C4, and C5 increase EMC immunity.
Figure 3.1 Bridge in Voltage Mode, External Diode Temperature Sensor
Out / OWI
GND
VSUPP
C2
100nF
8
7
6
5
4
3
2
1
VSSE
AOUT
VBN
VDDE
VDD
n.c.
+4.5V to +5.5V
C3
47nF
9
Sensor Bridge
10
11
12
13
14
VBR_B
VBP
SCL
SCL
SDA
Serial Interface
SDA
VBR_T
IRTEMP
VSSA
VDDA
C4
C5
C1
100nF
Temperature Sensor
18
December 6, 2016
Figure 3.2 Bridge in Voltage Mode, External Thermistor
Out / OWI
GND
C2
100nF
8
7
6
5
4
3
2
1
VSSE
AOUT
VBN
VDDE
VDD
n.c.
VSUPP
+4.5V to +5.5V
C3
47nF
9
Sensor Bridge
10
11
12
13
14
VBR_B
VBP
SCL
SCL
SDA
Serial Interface
SDA
R1
VBR_T
IRTEMP
VSSA
VDDA
PT1000
C4
C5
C1
100nF
Temperature Sensor
Figure 3.3 Bridge in Current Mode, Temperature Measurement via Bridge TC
Out / OWI
GND
C2
100nF
8
7
6
5
4
3
2
1
VSSE
AOUT
VBN
VDDE
VDD
n.c.
VSUPP
+4.5V to +5.5V
C3
47nF
9
10
11
12
13
14
C4*
C5*
VBR_B
VBP
SCL
SCL
Serial Interface
SDA
SDA
* C4 and C5 must be connected
to VBR_B when using Current
Mode because VBR_B and
VSSA are not shorted in this
case.
VBR_T
IRTEMP
VSSA
VDDA
C1
100nF
Sensor Bridge
RIBR
19
December 6, 2016
4. Pin Configuration, Latch-Up and ESD Protection
4.1 Pin Configuration and Latch-up Conditions
Table 4.1 Pin Configuration and Latch-Up Conditions
Usage/
Latch-up Related Application Circuit
Restrictions and/or Notes
Pin
1
Name
VDDA
Description
Notes
Connection [a]
Required/-
Required/-
-/VDDA
Positive analog supply voltage
Analog IO
2
VSSA
SDA
Negative analog supply voltage Analog IO
3
I2C data IO
Digital IO,
pull-up
Trigger Current/Voltage to VDDA/VSSA:
+/-100mA or 8/-4V
4
SCL
I2C clock
Digital IN,
pull-up
-/VDDA
5
6
N.C.
VDD
No connection
Positive digital supply voltage
Analog IO
Supply
Ground
IO
Required or
open/-
Only capacitor to VSSA is allowed,
otherwise no application access
7
8
9
VDDE
VSSE
AOUT
Positive external supply
voltage
Required/-
Required/-
Required/-
Trigger Current/Voltage: -100mA/33V
Negative external supply
voltage
Analog output and one wire
IF IO
Trigger Current/Voltage: -100mA/33V
10
11
VBN
Negative input sensor bridge
Bridge bottom potential
Analog IN
Analog IO
Required/-
VBR_B
Required/VSSA
Depending on application circuit,
short to VDDA/VSSA possible
12
13
14
VBP
Positive input sensor bridge
Bridge top potential
Analog IN
Analog IO
Analog IO
Required/-
VBR_T
IRTEMP
Required / VDDA
- / VDDA, VSSA
Temp sensor and current
source resistor
Depending on application circuit
[a] Usage: If “Required” is specified, an electrical connection is necessary; refer to the application circuits in section 3.
Connection: To be connected to this potential if not used or if no application/configuration-related constraints are given.
4.2 ESD Protection
All pins have an ESD protection of > 2000V. Additionally, the pins VDDE, VSSE and AOUT have an ESD protection of >4000V.
ESD protection referenced to the Human Body Model is tested with devices during product qualification. The ESD test follows the Human
Body Model with 1.5kΩ/100pF based on MIL 883, Method 3015.7.
20
December 6, 2016
5. Package
5.1 SSOP14 Package
The standard packages of the ZSC31150 are the SSOP14 green package (5.3mm body width) with a lead pitch of 0.65mm and the DFN14
(4mmx5mm) package with a lead pitch of 0.5mm.
For the SSOP14 package markings shown in Figure 5.1, YYWW refers to the last two digits of the year (YY) and two digits for the work-week
designation (WW). XXXXXXXX refers to the lot number.
Figure 5.1 SSOP14 Pin Diagram
VSSE
AOUT
VBN
VDDE
VDD
N.C.
VBR_B
VBP
SCL
SDA
VBR_T
IRTEMP
VSSA
VDDA
5.2 14-DFNPackage
For the 14-DFN package, the pin assignment is the same as in SSOP14. Refer to the ZSC31150 Technical Note – Die and Package
Specifications for a description of package markings.
Figure 5.2 provides the dimensions for the 14-DFN package option, which are based on JEDEC MO-229. The 14-DFN package has wettable
flanks.
21
December 6, 2016
Figure 5.2 Outline Drawing for 14-DFN Package with Wettable Flanks
0,08
Exposed Pad
4.4 x 2.5 mm
14
8
8
14
Top View
Bottom View
1
7
7
1
H
E
e
b
Table 5.1 14-DFN Package Dimensions
Dimension
Minimum
Maximum
0.9
A
A1
b
0.8
0
0.05
0.2
0.3
e
0.5 nominal
HD
HE
L
3.9
4.9
0.3
4.1
5.1
0.5
6. Quality and Reliability
The ZSC31150 is qualified according to the AEC-Q100 standard, operating temperature grade 0. A fit rate < 5fit (temperature =55°C, S=60%)
is guaranteed. A typical fit rate of the C7D technology, which is used for ZSC31150, is 2.5fit.
7. Customization
For high-volume applications, which require an upgraded or downgraded functionality compared to the standard ZSC31150, IDT can
customize the circuit design by adding or removing certain functional blocks.
22
December 6, 2016
For this purpose, IDT has a considerable library of sensor-dedicated circuitry blocks. As a result, IDT can provide a custom solution quickly.
Please contact IDT for further information.
8. Ordering Information
Product Sales Code
ZSC31150GEB
Description
Package
Unsawn on Wafer
ZSC31150 Die — Temperature range: -40°C to +150°C
ZSC31150 Die — Temperature range: -40°C to +150°C
ZSC31150 Die — Temperature range: -40°C to +150°C
ZSC31150GEC
Sawn on Wafer Frame
Waffle Pack
ZSC31150GED
Tape & Reel
ZSC31150 14-DFN (5 4 mm with wettable flank—Temperature
ZSC31150GEG2-R
ZSC31150GAG2-R
range: -40°C to 150°C
Tape & Reel
ZSC31150 14-DFN (5 4 mm with wettable flank —Temperature
range: -40°C to 125°C
ZSC31150GAB
ZSC31150GAC
ZSC31150GEG1
ZSC31150 Die — Temperature range: -40°C to +125°C
ZSC31150 Die — Temperature range: -40°C to +125°C
ZSC31150 SSOP14—Temperature range: -40°C to +150°C
Unsawn on Wafer
Sawn on Wafer Frame
Tube: add “-T” to sales code
Tape & Reel: add “-R”
ZSC31150GLG1
ZSC31150GAG1
ZSC31150 SSOP14—Temperature range: -40°C to +150°C
(Long life: 5000h @150°C)
Tube: add “-T” to sales code
Tape & Reel: add “-R”
ZSC31150 SSOP14—Temperature range: -40°C to +125°C
Tube: add “-T” to sales code
Tape & Reel: add “-R”
ZSC31150KITV1P2
ZSC31150MCSV1P1
ZSC31150 SSC Evaluation Kit V1.2: three interconnecting boards, five ZSC31150 SSOP14 samples, USB
cable (software can be downloaded from product page at www.IDT.com/ZSC31150)
Modular Mass Calibration System (MSC) V1.1 for ZSC31150: MCS boards, cable, connectors
(software can be downloaded from product page at www.IDT.com/ZSC31150)
9. Related Documents and Tools
Visit the ZSC31150 product page www.IDT.com/ZSC31150 on the IDT website at www.IDT.com or contact your nearest sales office for the
latest version of this document and related documents.
23
December 6, 2016
10. Glossary
Term
Description
Analog-to-Digital Converter
Automotive Electronics Council
ADC
AEC
AFE
Analog Front End
AOUT
BAMP
CM
Analog Output
Buffer Amplifier
Command Mode
CMC
CMV
CMOS
DAC
DM
Calibration Microcontroller
Common Mode Voltage
Complementary Metal Oxide Semiconductor
Digital-to-Analog Converter
Diagnostic Mode
EEPROM
ESD
LDR
MUX
NOM
OWI
P
Electrically Erasable Programmable Read Only Memory
Electrostatic Device
Lower Diagnostic Range
Multiplexer
Normal Operation Mode
One Wire Interface
Bridge Sensor Measurement; e.g., Pressure Sensor
Programmable Gain Amplifier
Power on Clear
PGA
POC
RAM
RISC
RMS
ROM
SCC
SIF
Random-Access Memory
Reduced Instruction Set Computer
Root-Mean-Square
Read Only Memory
Sensor Connection Check
Serial Interface
SSC+
SSC-
TS
Positive-biased Sensor Short Check
Negative-biased Sensor Short Check
Temperature Sensor
XZC
eXtended Zero Compensation
24
December 6, 2016
11. Document Revision History
Date
Description
September 20, 2008
(Revision 1.01)
Section 6: fit rate added. Section 1.5.2: ROM check time revised/corrected.
Section 5.3.4.3: SC – no detection limit added.
September 20, 2009
(Revision 1.02)
Update to new ZMDI template.
October 2, 2009
(Revision 1.03)
Update to ZMDI denotation.
October 22, 2009
(Revision 1.04)
Formatting and linking issues solved.
February 26, 2010
(Revision 1.05)
Update for ZMDI template, including ZSC31150 Functional Description at page 2 and 3.
Added ordering codes for ZSC31150 and evaluation kits. Extended glossary.
Update for contact information.
July 29, 2010
Correct “Offset shift per step” and “Approx. maximum offset shift” in Table 2.2 for PGA gain = 105 and 52.5.
Moved 1.4.1.6 “Internal pull-up resistor” into section 1.4.1 in Table 1.2. Redrew of Sensor Bridge in Figure
3.1, Figure 3.2, and Figure 3.3.
(Revision 1.06)
Added comment for C4 and C5 in Figure 3.3. Renamed ZMD31150 as ZSC31150.
August 31, 2010
(Revision 1.07)
Connection of RIBR in Figure 3.3 corrected.
August 15, 2011
(Revision 1.08)
Update ordering information with “Long Life Automotive” in “Ordering Information” on page 3 and section 8.
December 15, 2012
(Revision 2.00)
Update for part numbers and IDT contact information. Minor edits.
March 31, 2014
(Revision 2.10)
Revision of specifications in section 1.4.2. Recommended internal signal range revised to 80%. OWI interface
parameters list extended. ADC formula corrected. DFN14 package added. Minor edits for clarity. Updated
contact information. Updated imagery for cover and headings.
April 30, 2014
(Revision 2.20)
Added notation that DFN14 package has wettable flanks.
Update for contact information and addition of CAD model files to section 9.
August 27, 2014
(Revision 2.30)
Minor edits on page 2.
Minor edits for die description in part code tables.
December 3, 2014
(Revision 2.40)
Corrected connection of temperature PTC sensor in Figure 3.2.
Update for contact information.
July 27, 2015
Update for order code for ZSC31150 SSC Evaluation Kit order code.
Update for contact information.
(Revision 2.41)
January 29, 2016
December 6, 2016
Changed to IDT branding. The document release date is now the revision reference.
Added ZSC31150GAB and ZSC31150GAC order codes.
Correction for order codes for kit and MCS.
Updates for formatting and minor edits.
25
December 6, 2016
1RWLFH
ꢄꢃ 'HVFULSWLRQVꢀRIꢀFLUFXLWVꢅꢀVRIWZDUHꢀDQGꢀRWKHUꢀUHODWHGꢀLQIRUPDWLRQꢀLQꢀWKLVꢀGRFXPHQWꢀDUHꢀSURYLGHGꢀRQO\ꢀWRꢀLOOXVWUDWHꢀWKHꢀRSHUDWLRQꢀRIꢀVHPLFRQGXFWRUꢀSURGXFWVꢀ
DQGꢀDSSOLFDWLRQꢀH[DPSOHVꢃꢀ<RXꢀDUHꢀIXOO\ꢀUHVSRQVLEOHꢀIRUꢀWKHꢀLQFRUSRUDWLRQꢀRUꢀDQ\ꢀRWKHUꢀXVHꢀRIꢀWKHꢀFLUFXLWVꢅꢀVRIWZDUHꢅꢀDQGꢀLQIRUPDWLRQꢀLQꢀWKHꢀGHVLJQꢀRIꢀ\RXUꢀ
SURGXFWꢀRUꢀV\VWHPꢃꢀ5HQHVDVꢀ(OHFWURQLFVꢀGLVFODLPVꢀDQ\ꢀDQGꢀDOOꢀOLDELOLW\ꢀIRUꢀDQ\ꢀORVVHVꢀDQGꢀGDPDJHVꢀLQFXUUHGꢀE\ꢀ\RXꢀRUꢀWKLUGꢀSDUWLHVꢀDULVLQJꢀIURPꢀWKHꢀXVHꢀRIꢀ
WKHVHꢀFLUFXLWVꢅꢀVRIWZDUHꢅꢀRUꢀLQIRUPDWLRQꢃ
ꢁꢃ 5HQHVDVꢀ(OHFWURQLFVꢀKHUHE\ꢀH[SUHVVO\ꢀGLVFODLPVꢀDQ\ꢀZDUUDQWLHVꢀDJDLQVWꢀDQGꢀOLDELOLW\ꢀIRUꢀLQIULQJHPHQWꢀRUꢀDQ\ꢀRWKHUꢀFODLPVꢀLQYROYLQJꢀSDWHQWVꢅꢀFRS\ULJKWVꢅꢀRUꢀ
RWKHUꢀLQWHOOHFWXDOꢀSURSHUW\ꢀULJKWVꢀRIꢀWKLUGꢀSDUWLHVꢅꢀE\ꢀRUꢀDULVLQJꢀIURPꢀWKHꢀXVHꢀRIꢀ5HQHVDVꢀ(OHFWURQLFVꢀSURGXFWVꢀRUꢀWHFKQLFDOꢀLQIRUPDWLRQꢀGHVFULEHGꢀLQꢀWKLVꢀ
GRFXPHQWꢅꢀLQFOXGLQJꢀEXWꢀQRWꢀOLPLWHGꢀWRꢅꢀWKHꢀSURGXFWꢀGDWDꢅꢀGUDZLQJVꢅꢀFKDUWVꢅꢀSURJUDPVꢅꢀDOJRULWKPVꢅꢀDQGꢀDSSOLFDWLRQꢀH[DPSOHVꢃꢀ
ꢆꢃ 1RꢀOLFHQVHꢅꢀH[SUHVVꢅꢀLPSOLHGꢀRUꢀRWKHUZLVHꢅꢀLVꢀJUDQWHGꢀKHUHE\ꢀXQGHUꢀDQ\ꢀSDWHQWVꢅꢀFRS\ULJKWVꢀRUꢀRWKHUꢀLQWHOOHFWXDOꢀSURSHUW\ꢀULJKWVꢀRIꢀ5HQHVDVꢀ(OHFWURQLFVꢀRUꢀ
RWKHUVꢃ
ꢇꢃ <RXꢀVKDOOꢀQRWꢀDOWHUꢅꢀPRGLI\ꢅꢀFRS\ꢅꢀRUꢀUHYHUVHꢀHQJLQHHUꢀDQ\ꢀ5HQHVDVꢀ(OHFWURQLFVꢀSURGXFWꢅꢀZKHWKHUꢀLQꢀZKROHꢀRUꢀLQꢀSDUWꢃꢀ5HQHVDVꢀ(OHFWURQLFVꢀGLVFODLPVꢀDQ\ꢀ
DQGꢀDOOꢀOLDELOLW\ꢀIRUꢀDQ\ꢀORVVHVꢀRUꢀGDPDJHVꢀLQFXUUHGꢀE\ꢀ\RXꢀRUꢀWKLUGꢀSDUWLHVꢀDULVLQJꢀIURPꢀVXFKꢀDOWHUDWLRQꢅꢀPRGLILFDWLRQꢅꢀFRS\LQJꢀRUꢀUHYHUVHꢀHQJLQHHULQJꢃ
ꢈꢃ 5HQHVDVꢀ(OHFWURQLFVꢀSURGXFWVꢀDUHꢀFODVVLILHGꢀDFFRUGLQJꢀWRꢀWKHꢀIROORZLQJꢀWZRꢀTXDOLW\ꢀJUDGHVꢉꢀꢊ6WDQGDUGꢊꢀDQGꢀꢊ+LJKꢀ4XDOLW\ꢊꢃꢀ7KHꢀLQWHQGHGꢀDSSOLFDWLRQVꢀIRUꢀ
HDFKꢀ5HQHVDVꢀ(OHFWURQLFVꢀSURGXFWꢀGHSHQGVꢀRQꢀWKHꢀSURGXFWꢋVꢀTXDOLW\ꢀJUDGHꢅꢀDVꢀLQGLFDWHGꢀEHORZꢃ
ꢊ6WDQGDUGꢊꢉ
&RPSXWHUVꢌꢀRIILFHꢀHTXLSPHQWꢌꢀFRPPXQLFDWLRQVꢀHTXLSPHQWꢌꢀWHVWꢀDQGꢀPHDVXUHPHQWꢀHTXLSPHQWꢌꢀDXGLRꢀDQGꢀYLVXDOꢀHTXLSPHQWꢌꢀKRPHꢀ
HOHFWURQLFꢀDSSOLDQFHVꢌꢀPDFKLQHꢀWRROVꢌꢀSHUVRQDOꢀHOHFWURQLFꢀHTXLSPHQWꢌꢀLQGXVWULDOꢀURERWVꢌꢀHWFꢃ
ꢊ+LJKꢀ4XDOLW\ꢊꢉ 7UDQVSRUWDWLRQꢀHTXLSPHQWꢀꢍDXWRPRELOHVꢅꢀWUDLQVꢅꢀVKLSVꢅꢀHWFꢃꢎꢌꢀWUDIILFꢀFRQWUROꢀꢍWUDIILFꢀOLJKWVꢎꢌꢀODUJHꢏVFDOHꢀFRPPXQLFDWLRQꢀHTXLSPHQWꢌꢀNH\ꢀ
ILQDQFLDOꢀWHUPLQDOꢀV\VWHPVꢌꢀVDIHW\ꢀFRQWUROꢀHTXLSPHQWꢌꢀHWFꢃ
8QOHVVꢀH[SUHVVO\ꢀGHVLJQDWHGꢀDVꢀDꢀKLJKꢀUHOLDELOLW\ꢀSURGXFWꢀRUꢀDꢀSURGXFWꢀIRUꢀKDUVKꢀHQYLURQPHQWVꢀLQꢀDꢀ5HQHVDVꢀ(OHFWURQLFVꢀGDWDꢀVKHHWꢀRUꢀRWKHUꢀ5HQHVDVꢀ
(OHFWURQLFVꢀGRFXPHQWꢅꢀ5HQHVDVꢀ(OHFWURQLFVꢀSURGXFWVꢀDUHꢀQRWꢀLQWHQGHGꢀRUꢀDXWKRUL]HGꢀIRUꢀXVHꢀLQꢀSURGXFWVꢀRUꢀV\VWHPVꢀWKDWꢀPD\ꢀSRVHꢀDꢀGLUHFWꢀWKUHDWꢀWRꢀ
KXPDQꢀOLIHꢀRUꢀERGLO\ꢀLQMXU\ꢀꢍDUWLILFLDOꢀOLIHꢀVXSSRUWꢀGHYLFHVꢀRUꢀV\VWHPVꢌꢀVXUJLFDOꢀLPSODQWDWLRQVꢌꢀHWFꢃꢎꢅꢀRUꢀPD\ꢀFDXVHꢀVHULRXVꢀSURSHUW\ꢀGDPDJHꢀꢍVSDFHꢀV\VWHPꢌꢀ
XQGHUVHDꢀUHSHDWHUVꢌꢀQXFOHDUꢀSRZHUꢀFRQWUROꢀV\VWHPVꢌꢀDLUFUDIWꢀFRQWUROꢀV\VWHPVꢌꢀNH\ꢀSODQWꢀV\VWHPVꢌꢀPLOLWDU\ꢀHTXLSPHQWꢌꢀHWFꢃꢎꢃꢀ5HQHVDVꢀ(OHFWURQLFVꢀGLVFODLPVꢀ
DQ\ꢀDQGꢀDOOꢀOLDELOLW\ꢀIRUꢀDQ\ꢀGDPDJHVꢀRUꢀORVVHVꢀLQFXUUHGꢀE\ꢀ\RXꢀRUꢀDQ\ꢀWKLUGꢀSDUWLHVꢀDULVLQJꢀIURPꢀWKHꢀXVHꢀRIꢀDQ\ꢀ5HQHVDVꢀ(OHFWURQLFVꢀSURGXFWꢀWKDWꢀLVꢀ
LQFRQVLVWHQWꢀZLWKꢀDQ\ꢀ5HQHVDVꢀ(OHFWURQLFVꢀGDWDꢀVKHHWꢅꢀXVHUꢋVꢀPDQXDOꢀRUꢀRWKHUꢀ5HQHVDVꢀ(OHFWURQLFVꢀGRFXPHQWꢃ
ꢐꢃ :KHQꢀXVLQJꢀ5HQHVDVꢀ(OHFWURQLFVꢀSURGXFWVꢅꢀUHIHUꢀWRꢀWKHꢀODWHVWꢀSURGXFWꢀLQIRUPDWLRQꢀꢍGDWDꢀVKHHWVꢅꢀXVHUꢋVꢀPDQXDOVꢅꢀDSSOLFDWLRQꢀQRWHVꢅꢀꢊ*HQHUDOꢀ1RWHVꢀIRUꢀ
+DQGOLQJꢀDQGꢀ8VLQJꢀ6HPLFRQGXFWRUꢀ'HYLFHVꢊꢀLQꢀWKHꢀUHOLDELOLW\ꢀKDQGERRNꢅꢀHWFꢃꢎꢅꢀDQGꢀHQVXUHꢀWKDWꢀXVDJHꢀFRQGLWLRQVꢀDUHꢀZLWKLQꢀWKHꢀUDQJHVꢀVSHFLILHGꢀE\ꢀ
5HQHVDVꢀ(OHFWURQLFVꢀZLWKꢀUHVSHFWꢀWRꢀPD[LPXPꢀUDWLQJVꢅꢀRSHUDWLQJꢀSRZHUꢀVXSSO\ꢀYROWDJHꢀUDQJHꢅꢀKHDWꢀGLVVLSDWLRQꢀFKDUDFWHULVWLFVꢅꢀLQVWDOODWLRQꢅꢀHWFꢃꢀ5HQHVDVꢀ
(OHFWURQLFVꢀGLVFODLPVꢀDQ\ꢀDQGꢀDOOꢀOLDELOLW\ꢀIRUꢀDQ\ꢀPDOIXQFWLRQVꢅꢀIDLOXUHꢀRUꢀDFFLGHQWꢀDULVLQJꢀRXWꢀRIꢀWKHꢀXVHꢀRIꢀ5HQHVDVꢀ(OHFWURQLFVꢀSURGXFWVꢀRXWVLGHꢀRIꢀVXFKꢀ
VSHFLILHGꢀUDQJHVꢃ
ꢑꢃ $OWKRXJKꢀ5HQHVDVꢀ(OHFWURQLFVꢀHQGHDYRUVꢀWRꢀLPSURYHꢀWKHꢀTXDOLW\ꢀDQGꢀUHOLDELOLW\ꢀRIꢀ5HQHVDVꢀ(OHFWURQLFVꢀSURGXFWVꢅꢀVHPLFRQGXFWRUꢀSURGXFWVꢀKDYHꢀVSHFLILFꢀ
FKDUDFWHULVWLFVꢅꢀVXFKꢀDVꢀWKHꢀRFFXUUHQFHꢀRIꢀIDLOXUHꢀDWꢀDꢀFHUWDLQꢀUDWHꢀDQGꢀPDOIXQFWLRQVꢀXQGHUꢀFHUWDLQꢀXVHꢀFRQGLWLRQVꢃꢀ8QOHVVꢀGHVLJQDWHGꢀDVꢀDꢀKLJKꢀUHOLDELOLW\ꢀ
SURGXFWꢀRUꢀDꢀSURGXFWꢀIRUꢀKDUVKꢀHQYLURQPHQWVꢀLQꢀDꢀ5HQHVDVꢀ(OHFWURQLFVꢀGDWDꢀVKHHWꢀRUꢀRWKHUꢀ5HQHVDVꢀ(OHFWURQLFVꢀGRFXPHQWꢅꢀ5HQHVDVꢀ(OHFWURQLFVꢀSURGXFWVꢀ
DUHꢀQRWꢀVXEMHFWꢀWRꢀUDGLDWLRQꢀUHVLVWDQFHꢀGHVLJQꢃꢀ<RXꢀDUHꢀUHVSRQVLEOHꢀIRUꢀLPSOHPHQWLQJꢀVDIHW\ꢀPHDVXUHVꢀWRꢀJXDUGꢀDJDLQVWꢀWKHꢀSRVVLELOLW\ꢀRIꢀERGLO\ꢀLQMXU\ꢅꢀ
LQMXU\ꢀRUꢀGDPDJHꢀFDXVHGꢀE\ꢀILUHꢅꢀDQGꢒRUꢀGDQJHUꢀWRꢀWKHꢀSXEOLFꢀLQꢀWKHꢀHYHQWꢀRIꢀDꢀIDLOXUHꢀRUꢀPDOIXQFWLRQꢀRIꢀ5HQHVDVꢀ(OHFWURQLFVꢀSURGXFWVꢅꢀVXFKꢀDVꢀVDIHW\ꢀ
GHVLJQꢀIRUꢀKDUGZDUHꢀDQGꢀVRIWZDUHꢅꢀLQFOXGLQJꢀEXWꢀQRWꢀOLPLWHGꢀWRꢀUHGXQGDQF\ꢅꢀILUHꢀFRQWUROꢀDQGꢀPDOIXQFWLRQꢀSUHYHQWLRQꢅꢀDSSURSULDWHꢀWUHDWPHQWꢀIRUꢀDJLQJꢀ
GHJUDGDWLRQꢀRUꢀDQ\ꢀRWKHUꢀDSSURSULDWHꢀPHDVXUHVꢃꢀ%HFDXVHꢀWKHꢀHYDOXDWLRQꢀRIꢀPLFURFRPSXWHUꢀVRIWZDUHꢀDORQHꢀLVꢀYHU\ꢀGLIILFXOWꢀDQGꢀLPSUDFWLFDOꢅꢀ\RXꢀDUHꢀ
UHVSRQVLEOHꢀIRUꢀHYDOXDWLQJꢀWKHꢀVDIHW\ꢀRIꢀWKHꢀILQDOꢀSURGXFWVꢀRUꢀV\VWHPVꢀPDQXIDFWXUHGꢀE\ꢀ\RXꢃ
ꢓꢃ 3OHDVHꢀFRQWDFWꢀDꢀ5HQHVDVꢀ(OHFWURQLFVꢀVDOHVꢀRIILFHꢀIRUꢀGHWDLOVꢀDVꢀWRꢀHQYLURQPHQWDOꢀPDWWHUVꢀVXFKꢀDVꢀWKHꢀHQYLURQPHQWDOꢀFRPSDWLELOLW\ꢀRIꢀHDFKꢀ5HQHVDVꢀ
(OHFWURQLFVꢀSURGXFWꢃꢀ<RXꢀDUHꢀUHVSRQVLEOHꢀIRUꢀFDUHIXOO\ꢀDQGꢀVXIILFLHQWO\ꢀLQYHVWLJDWLQJꢀDSSOLFDEOHꢀODZVꢀDQGꢀUHJXODWLRQVꢀWKDWꢀUHJXODWHꢀWKHꢀLQFOXVLRQꢀRUꢀXVHꢀRIꢀ
FRQWUROOHGꢀVXEVWDQFHVꢅꢀLQFOXGLQJꢀZLWKRXWꢀOLPLWDWLRQꢅꢀWKHꢀ(8ꢀ5R+6ꢀ'LUHFWLYHꢅꢀDQGꢀXVLQJꢀ5HQHVDVꢀ(OHFWURQLFVꢀSURGXFWVꢀLQꢀFRPSOLDQFHꢀZLWKꢀDOOꢀWKHVHꢀ
DSSOLFDEOHꢀODZVꢀDQGꢀUHJXODWLRQVꢃꢀ5HQHVDVꢀ(OHFWURQLFVꢀGLVFODLPVꢀDQ\ꢀDQGꢀDOOꢀOLDELOLW\ꢀIRUꢀGDPDJHVꢀRUꢀORVVHVꢀRFFXUULQJꢀDVꢀDꢀUHVXOWꢀRIꢀ\RXUꢀQRQFRPSOLDQFHꢀ
ZLWKꢀDSSOLFDEOHꢀODZVꢀDQGꢀUHJXODWLRQVꢃ
ꢔꢃ 5HQHVDVꢀ(OHFWURQLFVꢀSURGXFWVꢀDQGꢀWHFKQRORJLHVꢀVKDOOꢀQRWꢀEHꢀXVHGꢀIRUꢀRUꢀLQFRUSRUDWHGꢀLQWRꢀDQ\ꢀSURGXFWVꢀRUꢀV\VWHPVꢀZKRVHꢀPDQXIDFWXUHꢅꢀXVHꢅꢀRUꢀVDOHꢀLVꢀ
SURKLELWHGꢀXQGHUꢀDQ\ꢀDSSOLFDEOHꢀGRPHVWLFꢀRUꢀIRUHLJQꢀODZVꢀRUꢀUHJXODWLRQVꢃꢀ<RXꢀVKDOOꢀFRPSO\ꢀZLWKꢀDQ\ꢀDSSOLFDEOHꢀH[SRUWꢀFRQWUROꢀODZVꢀDQGꢀUHJXODWLRQVꢀ
SURPXOJDWHGꢀDQGꢀDGPLQLVWHUHGꢀE\ꢀWKHꢀJRYHUQPHQWVꢀRIꢀDQ\ꢀFRXQWULHVꢀDVVHUWLQJꢀMXULVGLFWLRQꢀRYHUꢀWKHꢀSDUWLHVꢀRUꢀWUDQVDFWLRQVꢃ
ꢄꢂꢃ ,WꢀLVꢀWKHꢀUHVSRQVLELOLW\ꢀRIꢀWKHꢀEX\HUꢀRUꢀGLVWULEXWRUꢀRIꢀ5HQHVDVꢀ(OHFWURQLFVꢀSURGXFWVꢅꢀRUꢀDQ\ꢀRWKHUꢀSDUW\ꢀZKRꢀGLVWULEXWHVꢅꢀGLVSRVHVꢀRIꢅꢀRUꢀRWKHUZLVHꢀVHOOVꢀRUꢀ
WUDQVIHUVꢀWKHꢀSURGXFWꢀWRꢀDꢀWKLUGꢀSDUW\ꢅꢀWRꢀQRWLI\ꢀVXFKꢀWKLUGꢀSDUW\ꢀLQꢀDGYDQFHꢀRIꢀWKHꢀFRQWHQWVꢀDQGꢀFRQGLWLRQVꢀVHWꢀIRUWKꢀLQꢀWKLVꢀGRFXPHQWꢃ
ꢄꢄꢃ 7KLVꢀGRFXPHQWꢀVKDOOꢀQRWꢀEHꢀUHSULQWHGꢅꢀUHSURGXFHGꢀRUꢀGXSOLFDWHGꢀLQꢀDQ\ꢀIRUPꢅꢀLQꢀZKROHꢀRUꢀLQꢀSDUWꢅꢀZLWKRXWꢀSULRUꢀZULWWHQꢀFRQVHQWꢀRIꢀ5HQHVDVꢀ(OHFWURQLFVꢃ
ꢄꢁꢃ 3OHDVHꢀFRQWDFWꢀDꢀ5HQHVDVꢀ(OHFWURQLFVꢀVDOHVꢀRIILFHꢀLIꢀ\RXꢀKDYHꢀDQ\ꢀTXHVWLRQVꢀUHJDUGLQJꢀWKHꢀLQIRUPDWLRQꢀFRQWDLQHGꢀLQꢀWKLVꢀGRFXPHQWꢀRUꢀ5HQHVDVꢀ
(OHFWURQLFVꢀSURGXFWVꢃ
ꢍ1RWHꢄꢎ ꢊ5HQHVDVꢀ(OHFWURQLFVꢊꢀDVꢀXVHGꢀLQꢀWKLVꢀGRFXPHQWꢀPHDQVꢀ5HQHVDVꢀ(OHFWURQLFVꢀ&RUSRUDWLRQꢀDQGꢀDOVRꢀLQFOXGHVꢀLWVꢀGLUHFWO\ꢀRUꢀLQGLUHFWO\ꢀFRQWUROOHGꢀ
VXEVLGLDULHVꢃ
ꢍ1RWHꢁꢎ ꢊ5HQHVDVꢀ(OHFWURQLFVꢀSURGXFWꢍVꢎꢊꢀPHDQVꢀDQ\ꢀSURGXFWꢀGHYHORSHGꢀRUꢀPDQXIDFWXUHGꢀE\ꢀRUꢀIRUꢀ5HQHVDVꢀ(OHFWURQLFVꢃ
ꢍ5HYꢃꢇꢃꢂꢏꢄꢀꢀ1RYHPEHUꢀꢁꢂꢄꢑꢎ
Corporate Headquarters
Contact Information
TOYOSU FORESIA, 3-2-24 Toyosu,
For further information on a product, technology, the most up-to-date version
of a document, or your nearest sales office, please visit:
Koto-ku, Tokyo 135-0061, Japan
www.renesas.com/contact/
www.renesas.com
Trademarks
Renesas and the Renesas logo are trademarks of Renesas Electronics
Corporation. All trademarks and registered trademarks are the property of
their respective owners.
ꢀꢁꢂ20ꢀ5HQHVDVꢀ(OHFWURQLFVꢀ&RUSRUDWLRQꢃꢀ$OOꢀULJKWVꢀUHVHUYHGꢃ
相关型号：
©2020 ICPDF网 联系我们和版权申明