ZSSC3240CC1B [RENESAS]

Sensor Signal Conditioner IC for Resistive Sensors;


型号：	ZSSC3240CC1B
厂家：	RENESAS TECHNOLOGY CORP
描述：	Sensor Signal Conditioner IC for Resistive Sensors
文件：	总64页 (文件大小：1714K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

Datasheet

ZSSC3240

Sensor Signal Conditioner IC for Resistive Sensors

Description

Features

The ZSSC3240 is a sensor signal conditioning IC

(SSC) for highly accurate amplification, digitization,

and sensor-specific correction of resistive sensor

signals. The ZSSC3240 is suitable for bridge and

half-bridge sensors, as well as external voltage-

source element and single-element sensors (e.g.,

Pt100 and external temperature sensor diodes)

compensation of the sensor offset, sensitivity,

temperature drift, and non-linearity is accomplished

via a 26-bit math core running a correction algorithm

with calibration coefficients stored in a non-volatile,

reprogrammable memory. The programmable,

integrated sensor front-end allows optimally applying

various sensors for a broad range of applications.

 Digital communication and calibration interfaces

o SPI up to 10MHz

o I2C (Standard, Fast, and High-Speed Mode)

o One-wire-interface (OWI), up to 100kBit/s

 Accommodates nearly all resistive bridge sensor

types (signal spans from 1mV/V up to 500mV/V)

 Supports different sensor element configurations:

o Resistive bridge or half-bridge

o Resistive divider string

o Voltage source

 On-chip temperature sensor

 External temperature sensing supported, e.g.

sensor-bridge as temperature detector, external

diode, etc.

The ZSSC3240 provides measurement value

readouts and programming capabilities via an I2C,

SPI, or one-wire interface (OWI). Three different

operation modes allow optimal development of

digital, digital-analog, and analog-output smart

sensor modules including wake-up on request,

continuous-on/fast-response, and automatic/cyclic

sensor measurement operations. Absolute and

ratiometric voltage, current-loop, or interrupt analog

outputs are supported by the ZSSC3240. The

analog output options and digital interface options

(for calibration and/or a digital application interface)

can be combined.

 Support for Pt100

 Programmable 16-bit digital-to-analog-converter and

output:

o (0V to 1V) or (0V to 5V) absolute voltage output

o V_DD-ratiometric voltage output

o 4mA to 20mA current-loop output supported

o 0V to 10V absolute-voltage output supported

 On-chip voltage regulators for sensor supply, and IC

operation

 Support for extra regulation by external transistor, for

example JFET

 Programmable 24-bit sensor-signal-conditioning

Basic Application Diagram

math core

Sensor

Element

 Reprogrammable, nonvolatile memory (NVM)

VDD

 Programmable measurement scheduler for

continuous sensing applications, with optimized

balance of

VSS

OUT_ANA

ZSSC3240

o Energy consumption

o Output update rate

o Sensor-signal-conditioning accuracy

o Self-diagnostic coverage and system safety

 On-chip diagnostics:

Optional Digital Master

(I2C, SPI, OWI)

o Sensor connection

o Broken-chip-check / chipping-check

o Memory integrity

Nov.27.20

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ZSSC3240

Datasheet

Physical Characteristics

Typical Applications

 Supply voltage, V_DD: 2.7V to 5.5V;

with external transistor, for example

JFET: 5V to 48V

 Calibrated, continuously operating sensors with

digital interface and/or analog output: (absolute or

ratiometric) voltage or current loop output

 Operating temperature: -40°C to 125°C

 Enables smart, digital sensors for energy-efficient

solutions

 Supported sensor elements: 0.5kΩ to 60kΩ

 Pressure, flow, and level sensing

 Available as die on wafers or 4  4 mm²24-QFN

with wettable flanks, allowing visual inspection of

QFN reflow quality

 Industrial applications; e.g. process/factory

automation

 Consumer / white goods, e.g. HVAC, weight scales

 Medical applications, e.g. blood pressure,

continuous smart health monitors

Block Diagram

Sensor Supply: voltage / ratiometric

LDOctrl

T_EXT

external

Transistor

Regulation

VDDA int

Internal

Voltage

Regulators

VDD

VSS

Internal

V_TP

V_TN

Sensor

Bias

AGND / CM

Generator

IC Bias Current

Generator

Temp.

Sensor

Element

VDDB

Sensor

Power Ctr.

Current

Ana

Dig

Sensor Supply:

current mode

ZSSC3240

AOUT /

OWI1

DAC

13-16Bit

RESQ

INP

VSSB

INN

12-24Bit

PGA

OWI2_in

OWI

Digitial Control and

Math Core

EOC

Analog

SCLK/SCL

MOSI/SDA

MISO

Clock

Generator

Sensor

Connection

Diagnostics

System

Control

Unit

SPI

Chipping

Check

Power-ON

Reset

NVM

Oscillator

I2C

Typical Application Examples

Digital Half-Bridge Sensor, e.g. PT100

Analog Sensor with Absolute Voltage Out

VDD

(2.7-5.5V)

V_DD

(2.7 to 5.5V

VDDB

VSS

VDDB

INP

VSS

PTC /

NTC

INP

VSSB

INN

AOUT / OWI1

ZSSC3240

OWI

VSSB

INN

AOUT / OWI1

V_{OUT, absolute}

(0 to 1V / 0 to 5V)

ZSSC3240

Sensor Half-

Bridge

Sensor Bridge

Digital Interface:

I2C or SPI or OWI

Sensor with Ratiometric Voltage Output and Digital Interface

Analog Sensor with Current Loop Output, OWI, and External JFET

V_DD

Loop+

(2.7 to 5.5V)

(7 to 48V)

5 to

5.5V

OWI

VDDB

VSS

INP

V_{OUT, ratiometric}

(2.5% to 97.5% of V_DD

AOUT

OWI1

VSSB

INN

VDDB

INP

VSS

ZSSC3240

Sensor Bridge

VSSB

INN

AOUT / OWI1

V_DD

(2.7 to

5.5V)

ZSSC3240

OWI2_in

Digital Interface:

I2C or SPI or OWI

Sensor Bridge

Loop-

4 to 20mA

R_sens

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ZSSC3240

Datasheet

Contents

1. Pin Assignments............................................................................................................................................ 6

2. Pin Descriptions ............................................................................................................................................ 7

3. Absolute Maximum Ratings.......................................................................................................................... 8

4. Recommended Operating Conditions ......................................................................................................... 8

5. Electrical Characteristics.............................................................................................................................. 8

6. Device Description ...................................................................................................................................... 11

6.1 Signal Flow .......................................................................................................................................... 12

6.2 Analog (Sensor) Front-End.................................................................................................................. 12

6.2.1.

6.2.2.

6.2.3.

6.2.4.

Programmable-Gain Amplifier (PGA).................................................................................... 13

Analog-to-Digital Converter (ADC)........................................................................................ 15

Internal Temperature Sensor ................................................................................................ 17

Supported Supplies for Sensor Elements and Additional, External Temperature Sensing.. 17

6.3 On-Chip Diagnostics............................................................................................................................ 22

6.4 Digital Interfaces.................................................................................................................................. 24

6.4.1.

6.4.2.

6.4.3.

SPI......................................................................................................................................... 24

I2C......................................................................................................................................... 27

One-Wire-Interface, OWI ...................................................................................................... 28

6.5 Measurement and Output Options ...................................................................................................... 32

6.5.1.

6.5.2.

6.5.3.

6.5.4.

Single Measurements, Digital Raw Results, and SSC Results ............................................ 32

Cyclic, Continuous, Repeated Measurements – Measurement Scheduler .......................... 34

Analog Outputs: Digital-to-Analog Converter (DAC)............................................................. 35

Output Interrupt Signaling ..................................................................................................... 38

6.6 System Setup and Control................................................................................................................... 40

6.6.1.

6.6.2.

6.6.3.

Digital Commands................................................................................................................. 40

Nonvolatile Memory (NVM)................................................................................................... 43

Digital Sensor-Signal-Conditioning Mathematics.................................................................. 55

6.7 External, Extra LDO (LDOctrl) for Applications for > 5.5V .................................................................. 58

7. Calibration .................................................................................................................................................... 59

8. Package Outline Drawings.......................................................................................................................... 59

9. Marking Diagram.......................................................................................................................................... 59

10. Ordering Information................................................................................................................................... 60

11. Glossary........................................................................................................................................................ 60

12. Revision History .......................................................................................................................................... 61

Nov.27.20

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ZSSC3240

Datasheet

Figures

Figure 1.

Figure 2.

Figure 3.

Figure 4.

Figure 5.

Figure 6.

Figure 7.

Figure 8.

Figure 9.

Figure 10.

Figure 11.

Figure 12.

Figure 13.

Figure 14.

Figure 15.

Figure 16.

Figure 17.

Figure 18.

Figure 19.

Figure 20.

Figure 21.

Figure 22.

Figure 23.

Figure 24.

Figure 25.

Pin Assignments for 4  4 mm²24-QFN Package – Top View.......................................................6

Pin (Pad) Assignments for Bare Die ...............................................................................................6

Main Operating Modes of the ZSSC3240.....................................................................................11

Analog Sensor Front-End Topology..............................................................................................13

SPI Configuration CPHA=0...........................................................................................................25

SPI Configuration CPHA=1...........................................................................................................25

SPI Command Request ................................................................................................................26

SPI Read Data ..............................................................................................................................26

SPI Read Status............................................................................................................................26

I2C Command Request ................................................................................................................27

I2C Read Data ..............................................................................................................................27

I2C Read Status............................................................................................................................27

General Block Schematic of the OWI Interface ............................................................................28

OWI Timing Diagram.....................................................................................................................29

OWI Extra (Activation) Pulse for Concurrent OWI and Analog Output Configuration ..................29

OWI Command Request...............................................................................................................30

OWI Response by ZSSC3240 ......................................................................................................31

Example Configuration for the Measurement Scheduling and Cyclic Mode Operation................34

Measurement Result Output Update in Cyclic Operation (with “Slow” Interface Polling).............35

DAC and Analog Output Topology................................................................................................35

Current Loop Configuration...........................................................................................................38

EOC-Behavior: Signalization of End-of-Conversion (INT_setup = 00_BIN).....................................38

EOC and Interrupt Thresholds......................................................................................................39

Digital IC Section Architecture ......................................................................................................40

LDOctrl Application Topology .......................................................................................................58

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ZSSC3240

Datasheet

Tables

Table 1.

Pin Descriptions ..............................................................................................................................7

Absolute Maximum Ratings ............................................................................................................8

Recommended Operating Conditions.............................................................................................8

Electrical Characteristics.................................................................................................................8

PGA Gain: Stage 1........................................................................................................................13

PGA Gain: Stage 2........................................................................................................................14

Absolute Offset Shift – Properties.................................................................................................14

Absolute Offset Shift – Differential Sensor Signal’s Offset Compensation...................................14

PGA Input Span Ranges...............................................................................................................15

Single Analog-to-Digital Conversion .............................................................................................16

ADC Offset Shift............................................................................................................................16

Sensor Supply Options .................................................................................................................17

Sensor Supply – Main Sensing.....................................................................................................18

Sensor Bias Currents – Sensor Sourcing in Current Mode ..........................................................19

Sensor Supply – Temperature Sensing........................................................................................19

Diagnostic Signalization Options with ZSSC3240 ........................................................................22

Information Assignment for CHECK_DIAG Command: Output Register diagnosticreg [15:0].....23

General Status Byte......................................................................................................................24

Mode Status..................................................................................................................................24

SPI Interface Parameter ...............................................................................................................26

I2C Interface Parameter................................................................................................................27

OWI Dimensioning Examples .......................................................................................................29

OWI Interface Parameters ............................................................................................................29

Data Format of Raw ADC Readings.............................................................................................32

Data Format of Corrected, SSC Results (S and T).......................................................................32

Typical Conversion Times for Complete SSC Sensor Measurements: SM, TM ..........................33

Typical Conversion Times and Noise Performance for Complete SSC Measurements ..............33

DAC Configurations ......................................................................................................................35

Direct Voltage Outputs..................................................................................................................36

Recommended Operating Conditions for Voltage Output ............................................................36

ZSSC3240 Current-Loop-Specific Properties...............................................................................37

Data Format of Interrupt Thresholds (TRSH1 and TRSH2)..........................................................39

Command List...............................................................................................................................40

Memory (NVM) Content Assignments ..........................................................................................44

Data Format of 24-bit SSC Coefficients........................................................................................55

Data Format of Corrected, SSC Results (S and T).......................................................................56

IC Supply, V_DDTarget Level Selection with External Voltage Regulation, External LDO.............58

External LDO Operating Conditions..............................................................................................58

Table 2.

Table 3.

Table 4.

Table 5.

Table 6.

Table 7.

Table 8.

Table 9.

Table 10.

Table 11.

Table 12.

Table 13.

Table 14.

Table 15.

Table 16.

Table 17.

Table 18.

Table 19.

Table 20.

Table 21.

Table 22.

Table 23.

Table 24.

Table 25.

Table 26.

Table 27.

Table 28.

Table 29.

Table 30.

Table 31.

Table 32.

Table 33.

Table 34.

Table 35.

Table 36.

Table 37.

Table 38.

Nov.27.20

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ZSSC3240

Datasheet

1. Pin Assignments

The ZSSC324x is available as 8-inch wafers and in a 24-QFN package. Detailed information about die and

wafers is available on request (see last page for contact information).

VDDB

INP

VSS

VSSB

INN

AOUT / OWI1

OWI2_in

EOC

ZSSC324x

IDT-Test

: QFN-bottom plate, Exposed PAD.

Figure 1. Pin Assignments for 4  4 mm²24-QFN Package – Top View

IC Core

Seal Ring

LDOctrl

VDD

VSS

T_ext

VDDB

INP

AOUT / OWI1

OWI2_in

VSSB

INN

EOC

IDT-Test

RESQ

MISO

MOSI / SDA

SCLK / SCL

IDT-Test

Figure 2. Pin (Pad) Assignments for Bare Die

Nov.27.20

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ZSSC3240

Datasheet

2. Pin Descriptions

Table 1.

Pin Number

Pin Descriptions

Name

Type

Description

Analog

Input/Output

Positive sensor (bridge) supply or sensor-signal input.

VDDB

INP

Analog Input

Positive sensor (bridge) signal.

VSSB

INN

Analog Input

Sensor (bridge) ground or sensor-signal input.

Negative sensor (bridge) signal.

Analog Input

IDT-test

RESQ

IDT-test

–

Renesas-internal use only. Connect to VSS or no connection; leave pin floating.

Digital IC reset (low active); internal pull-up.

–

Digital Input

–

Renesas-internal use only. Connect to VSS or no connection; leave pin floating.

Digital data input for SPI or bidirectional data I/O for I2C. Pull-up to VDD.

Digital

Input/Output

MOSI/SDA

n.c.

–

No connection. Leave pin floating.

SCLK/SCL

Digital Input

Clock input for SPI or I2C interface. Referenced to applied VDD level.

Data output from ZSSC3240 to master for SPI interface. Referenced to applied

VDD level.

MISO

Digital Output

Digital Input

Digital Output

Digital Input

Slave select (interface enable) for SPI. Referenced to applied VDD level.

End-of-conversion and output interrupt signal.

EOC

OWI2_in

Optional OWI interface input line for current-loop applications.

Analog smart-sensor output signal and/or OWI-interface input/output line.

Analog Output;

Digital

AOUT/OWI1

Input/Output

Current-loop application feedback output (level below VSS!). No connection if not

used.

Analog Output

VSS

V_DD

n.c.

Ground

Supply

–

Power supply ground.

Power supply.

No connection. Leave pin floating.

Current drive output for external temperature sensor and/or bridge in Current

Mode. A 1500Ω serial resistor is built in the IC internally for pad-protection

purposes.

T_EXT

Analog Output

n.c.

LDOctrl

–

No connection. Leave pin floating.

Control output (reference signal) for (optional) external regulator / supply control

loop.

Analog Output

n.c.

–

No connection. Leave pin floating.

QFN-bottom plate, i.e. Die-bottom/substrate. Leave pin floating (no electrical

connection), PAD to be used for heat dissipation only.

Exposed PAD

Nov.27.20

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ZSSC3240

Datasheet

3. Absolute Maximum Ratings

The absolute maximum ratings are stress ratings only. Stresses greater than those listed below can cause

permanent damage to the device. Functional operation of the ZSSC3240 at absolute maximum ratings is not

implied. Exposure to absolute maximum rating conditions might affect device reliability.

Table 2.

Absolute Maximum Ratings

Symbol

Parameter

Junction temperature

Conditions

Minimum

Maximum

135

Units

°C

T_J

T_S

Storage temperature

-45

150

ESD – Human Body Model

ESD – Charged Device Model

Latch-up

4000

750

-100

-0.3

+100

6.5

V_{DD_max}

V_{IF_max}

Maximum allowed for voltage supply

Voltage at digital interface pins

Referenced to VSS.

I2C pins: SDA, SCL

4mA to 20mA current loop

interface

5.5

V_{FB_max}

Voltage at FB pin

-2

4. Recommended Operating Conditions

Table 3.

Recommended Operating Conditions

Symbol

Parameter

Power supply voltage

Minimum

2.7

Typical

Maximum

5.5

Units

V_DD

T_A

–

Ambient temperature (depending on the part code)

-40

125

°C

External (parasitic) capacitance between VDD and VSS,

without external supply transistor regulation

100

6.8

–

120

C_VDD

External (parasitic) capacitance between VDD and VSS, with

(optional) external supply transistor regulation

Recommended, external capacitance between VDDB and

VSS for electro-magnetic immunity (EMI)

C_VDDB,EMC

Recommended, external capacitance between AOUT versus

VSS, and versus VDD for EMI ^[a]

Load current through external sensor element ^[b]

External temperature diode and RTD input range, drop over

external element referenced to T_EXTpin

C_AOUT,EMC

I_Sensor

V_DioDrop

V_{Sens_in}

0.5

–

0.02

-0.2

Absolute sensor signal input level, INN, INP pins

Minimum level at VDDB ^[b]

Maximum level at VSSB ^[b]

0.5

0.9

–

1.2

–

VDDB_{ratio_min}

VSSB_{ratio_max}

I_{max_AOUT_V}

0.7

–

Maximum current load at AOUT pin for voltage outputs

Recommended V_DDrise slew rate for power-on-reset (POR) ^[c]

V/ms

SR_{VDD_POR}

1.5

–

[a] For applications with OWI-interface or analog voltage-output.

[b] With ratiometric sensor supply configuration; e.g. a ratiometric bridge or bridge as temperature sensor with internal or external Rt.

[c] Per design, there is no (theoretical) minimum V_DDslew rate to trigger a clean POR. Nevertheless, a reasonable slew rate is

recommended.

5. Electrical Characteristics

All parameter values are valid only under specified operating conditions. All voltages are referenced to V_SS.

Table 4.

Electrical Characteristics

Note: See important notes at the end of this table.

Symbol

I_IC

Parameter

Conditions

Minimum

Typical

Maximum

Units

IC Supply

Excluding connected sensor elements

(with LDOctrl enabled)

Current consumption,

active IC

–

2.3

1.5

2.80

µA

Idle current consumption,

IC in Idle State

Typical value at 30°C, maximum value at

85°C (125°C)

I_IDLE

(22)

OWI and LDOctrl disabled

Nov.27.20

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ZSSC3240

Datasheet

Symbol

Parameter

Conditions

Minimum

Typical

Maximum

Units

Average current draw

Mean current consumption for one

complete SSC measurement cycle per

second at 16-bit digital-only output

–

3.5

µA

I_AVE

Target level regulation

range to generate V_DD

after external transistor,

for example JFET

Using LDOctrl and external transistor;

programmable setup: VDD_ldoctrl_target

(see section 6.7)

4.6

5.2

5.5

V_DD,LDOctrl

Sensor Supply

I_SUP

Sensor bias

-1

500

1.5

µA

In the case of a Current Mode sensor

supply; setup in temp_source and

sensor_sup (see section 6.2)

Relative sensor bias

current error ^[a]

-3.5

Err_TBIAS

Drop over sensor bias

current source

referenced VDDA_intfrom internal analog

regulator

–

200

230

V_TBIAS

Internally regulated

analog (bridge) sensor

front-end supply

In the case of a ratiometric sensor

supply, setup in temp_source and

sensor_sup

1.68

1.75

1.80

VDDB

(VDDA_int)

Attenuation of V_DDfluctuations in the

range of f_VDD= 0Hz to 10MHz

–

Power supply rejection

ratio^[b], only internal

regulator

PSRR_LOW

PSRR_HIGH

f_VDD> 10MHz

Analog-to-Digital Converter (ADC, A2D)

rADC

f_S,raw

Resolution

Bit

Single-conversion rate,

conversions per second

Single external sensor A2D conversion

(without auto-zero measurement AZ);

resolution dependent

0.21

(ADC:

24-bit)

3.39

(ADC:

16-bit)

13.00

(ADC:

12-bit)

kHz

Differential ADC input

common mode^[c]

With internal regulator supplying VDDB

pin, typical: VDDB/2 = 875mV (equals

PGA output common mode level)

–

0.5

–

VDDB

Bit

V_ADCmid

(AGND)

Effective number of bits,

3_Noisebased

For gain < 78, shorted input, rADC =

24-bit, no oversampling

15.8

18.1

–

ENOB ^[g]

Digital-to-Analog Converter (DAC) and Analog Output

r_DAC

Resolution

Bit

µs

Analog voltage output

settling time

Time from 30% steady state until 99% of

new DAC output (100% out) value is

reached; varies with level differences

150

t_DACsettle

Absolute output, Aout_setup = 010_BIN

(see section 6.5.3.1)

0.025

–

Addressable output

voltage at AOUT pin

V_DACout

Absolute output, V_DD> 5.01V,

Aout_setup = 011_BIN

Ratiometric output, Aout_setup = 001_BIN

0.1

–

100

%VDD

kHz

BW_DAC

SR_out

Output filter bandwidth

Output slew rate

Without external components

Resistive load > 2kΩ,

100

mV/µs

capacitive load < 20nF at Aout,

temperature = 25°C

Maximum output current

This current level must be overdriven

from an OWI-Master, if concurrent DAC-

output and OWI communication is

configured.

µA

I_OUTmax

Current loop driving

current

Aout_setup = 000_BIN; depends on

connected bipolar transistor for current

loop application

I_DRloop

–

100

160

Programmable-Gain Amplifier (PGA)

120 steps

G_amp

G_err

Gain

1.32

-2.5

–

540

2.5

V/V

Gain error

Referenced to nominal gain, T = 25°C

VDDA_int= 1.75V, valid for ratiometric and

current mode sensor supply

Supported input common

mode

V_CMin

0.70

0.85

1.00

Sensor Signal Conditioning Performance

Cyclic operation

0.07

1.45

1.20

2.91

kHz

SSC-corrected (S, T ) digital output rate,

ADC:16-bit (see section 6.5.1)

–

f_SSCout

Output (Update) rate ^[d]

Complete SSC cycle (S, T ) including

analog output update; ADC: 14-bit; DAC:

14-bit

1.35

1.45

1.60

kHz

Nov.27.20

Page 9

ZSSC3240

Datasheet

Symbol

Parameter

Conditions

Minimum

Typical

Maximum

Units

ZSSC3240 accuracy

error

Accuracy error with an ideally linear

sensor (in temperature and measurand)

Err_A,IC

–

0.01

% FSO

Correctable (in PGA),

absolute, differential input ±5% referenced to nominal setup

offset

Programmable in 1mV steps; accuracy:

V_ioffsc

-15

Correctable (in ADC),

relative, differential input

offset

Percentage of sensor signal offset

versus maximum sensor signal

Δ_ADC,c

–

Input

Absolute sensor input

Voltages at INP and INN pin; resulting

minimum/maximum differential voltages:

-700mV < V_INdiff< 700mV

V_INP, V_INN

0.5

–

1.20

1.25

External temperature

diode or RTD input range

At T_EXTpin

V_TEXT

VDDB = 1.75V

0.5

1.6

–

kΩ

External sensor (bridge)

resistance

R_SENSOR

For 4mA to 20mA current loop output

Differential input signal

range

Referenced to sensor supply (VDDA_int);

leading to full scale analog excitation

Diagnostics

|V_DIFFin

2.6

700

Sensor connection loss;

i.e., open threshold

INP vs. INN

R_open

R_short

–

kΩ

Ω

Sensor connection short

threshold

INP vs. INN; T_EXTvs. VDDB

–

100

Valid sensor input signal

Beyond V_s,valid,sensor connection checks

(such as in-range, etc.) signalize

Diagnostic FAULTs

V_s,valid

0.44

–

1.31

Power-Up

t_STA1

t_STA2

V_DDramp up to interface communication

V_DDramp up to analog operation

–

Start-up Time

Wake-up Time

2.5

Sleep to Active State interface

communication

t_WUP1

t_WUP2

–

µs

Sleep to Active State analog operation

–

Oscillator

Internal oscillator

frequency

f_CLK

5.9

6.0

–

6.1

–

MHz

Counts/K

kΩ

Temperature Sensor(s)

Setup: ADT_Tsens,int= 13-bit

Internal temperature

sensor resolution

Internal low TC^[f]

top/bottom resistance for

external temperature

r_Temp

Programmable with internal_rt and

extra_rt;

applied if temp_source є {010; 110} (see

section 6.2.4)

Rt, Rt'

1.34

Interface and Memory

f_C,SPI

f_C,I2C

SPI clock frequency

I2C clock frequency

OWI data rate

0.05

3.4

MHz

–

CD_OWI

t_PROG

0.33

–

kBit/s

NVM program time

NVM endurance

Data retention

Programming time per 16-bit word

Number of reprogramming cycles

10000

–

n_NVM

1000

–

Numeric

Years

t_RET,NVM

–

[a] Referenced to nominal value. Relative errors are typically < 1% for sensor bias current setups > 20µA.

[b] PSRR = 20·log₁₀(V_DD/V_DDB): will be improved when applying external filter elements at V_DDand/or also using an external JFET

regulator.

[c] This parameter must be taken into account if automatic common mode regulation in the PGA is switched off (pga_en_shift; see

section 6.2.1) and a non-symmetric sensor supply and input to the PGA ADC path have been configured.

[d] There are several setups and parameters that allow optimizing and maximizing the output update rate; e.g., ADC and DAC

resolutions, configurations for the measurement sequence, usage of the internal or an external temperature sensor.

[e] V_ioffscand Δ_ADC,ccan be arbitrarily set up and combined. They work independently on each other.

[f] Typical residual temperature variation of voltage across Rt, Rt': 10ppm/K; maximum deviation: 150ppm/K at

40kΩ and >100°C, all other setups and conditions < 60ppm/K.

[g] ENOB = log₂( 2^rADC/ 3_Noise) with, for example rADC[Bit] = 24.

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Datasheet

6. Device Description

The ZSSC3240 can be set up to for one of three main operating modes:

Sleep Mode

The Sleep Mode is recommended for smart sensors with purely digital output. The

ZSSC3240 automatically enters the idle state after command execution for minimum

current consumption, whereas the interface is still listening and accepts commands.

After receiving a valid command, the ZSSC3240 wakes up, executes the command,

provides the results at the digital interface, where the results must be read, and returns

to idle state after the data fetch. The results are only available once; repeated data fetch

is not supported. In Sleep Mode, sensor measurement results cannot be provided at the

analog output of ZSSC3240.

Command Mode

Cyclic Mode

The Command Mode is most appropriate for evaluation, test, and calibration purposes.

In this mode, all commands are available, both digital and analog outputs are supported

and all functionality is available. Command Mode can be used for applications requiring

re-occurring (or even continuous) digital interaction, potential analog output, and

minimum latency. Applications in Command Mode are only active on command request.

In Cyclic Mode, autonomous, cyclically repeated sensor measurements are performed

and related digital and/or analog output updates are provided. Cyclic Mode is

recommended for analog output applications. The cyclic sequence for measurements,

diagnostics, and hence the output update rate is configurable.

The ZSSC3240 always enters the programmed default_mode after power-on (reset). One of the three operating

modes can be set up as the default. After the ZSSC3240 is powered and has entered its default mode, changing

to one of the other operating modes is possible via the mode change and start commands: START_CM,

START_CYC, START_SLEEP (see section 6.6.1 for details).

Power-On (V_DD),

Reset

Initialization

(load fromconfigurations from NVM,

interfaces, default_mode, etc.)

10_BIN

default_mode

01_BIN

00_BIN

Sleep Mode

(wake up on command, automatic

sleep after command execution, no

Command Mode

(activity on command, digital and

analog output supported, fastest

Cyclic Mode

(autonomous measurements, digital

and analog output supported, limited

START_SLEEP

START_CM

START_CYC

START_CM

analog output)

response, all commands)

commands)

START_CYC

START_SLEEP

Figure 3. Main Operating Modes of the ZSSC3240

The ZSSC3240 supports three different types of digital interfaces: I2C, SPI, and OWI. All interface types allow

application and control of each of the main operating modes.

Exception: The combination of Sleep Mode as the default mode (see the default_mode bit in the SSF1 register in

Table 34) and the OWI interface is not supported. The OWI interface must be disabled (owi_off = 1, bit[13] in the

SSF1 register) for correct Sleep Mode operation.

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When using commands to change the operating mode, e.g. START_CM or START_SLEEP, validation of the

new operating mode is recommended; e.g., by reading an NVM register or simply retrieving the status byte.

Note: The ZSSC3240 always requires two or more interface command interactions after an operating mode

change prior to any additional changes in the mode.

6.1

Signal Flow

See the figures on page 2 for the ZSSC3240 block diagram and circuit diagrams for different input sensors. The

ZSSC3240 supports two sensor supplies: ratiometric voltage and current mode, i.e., sensor current bias. In the

ratiometric sensor-supply configuration, VDDB and the power supply for analog circuitry are provided by an on-

chip voltage regulator, which is optimized for power supply disturbance rejection (PSRR). To improve noise

suppression, the digital blocks are powered by a separate voltage regulator. A power supervision circuit monitors

all supply voltages and generates appropriate reset signals for initializing the digital blocks.

The System Control Unit controls the analog circuitry to perform the measurement types: external sensor,

external or internal temperature, and offset measurement. The multiplexer selects the signal input to the

amplifier, which can be the external signals from the input pins INP, INN, T_EXT, VDDB, and VSSB or the internal

temperature reference sensor signals. A full measurement request will trigger an automatic sequence of all

measurement types and all input signals. The basic sensor signal source configuration is set up in the SSF1

The programmable gain amplifier (PGA) consists of two stages with programmable gain values. The ZSSC3240

employs a programmable analog-to-digital converter (ADC) optimized for conversion speed and noise

suppression. The programmable resolution from 12 to 24 bits provides flexibility for adapting the conversion

characteristics. To improve power supply noise suppression, the ADC uses the external sensor supply voltage,

e.g., VDDB for the ratiometric supply of a connected full-bridge sensor element, as its reference voltage leading

to a ratiometric measurement topology. The remaining IC-internal offset and the sensor element offset, i.e., the

overall system offset for the amplifier and ADC, can be canceled via an offset and auto-zero measurement,

respectively.

The math core accomplishes the auto-zero, span, and 1^stand 2^ndorder temperature compensation of the

measured external sensor signal. The correction coefficients are stored in the non-volatile memory.

The ZSSC3240 supports SPI, OWI, and I2C interface communication for controlling the ZSSC3240,

configuration, and measurement result output. Analog output signals can be provided, which are proportional to

the sensor signal that has been compensated for nonlinearity and temperature. The ZSSC3240 can also check

and signalize numerous sensor and self-check diagnostic values.

6.2

Analog (Sensor) Front-End

The main blocks and functions of the analog sensor front-end of the ZSSC3240 are illustrated in Figure 4. As a

typical first setup, the type and supply of the connected (external) sensor element should be determined and

configured. The sensor_sup and temp_source bits in the SSF1 register (03_HEX; see Table 34) of the NVM must

be set up according to the connected sensor configuration.

Important: If using the current mode sensor biasing via the “Sensor Bias Current” block, which is configured with

the Tbiasout bit field (see section 6.2.4), ensure that the selection for bias current combined with the

dimensioning for the connected external sensor is within the input common mode constraints, V_CMin(typical

0.85V) as defined in Table 4.

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ZSSC3240

Datasheet

VDDA_int 1.75V

Sensor Supply: Voltage / Ratiometric

T_EXT

Internal

Temp.

Sensor

V_TP

V_TN

Sensor

Bias

Current

VDDB

Sensor Supply:

Current Mode

INP

VSSB

INN

PGA

adc_bits

gain_polarity

Gain_stage1

ioffsc Gain_stage2

adc_en_shift adc_offset

Tbiasout

sensor_sup

Figure 4. Analog Sensor Front-End Topology

6.2.1.

Programmable-Gain Amplifier (PGA)

The amplifier has a fully differential architecture and consists of two stages. The amplification of each stage and

the external sensor gain polarity are programmable via settings in the measurement configuration register:

 For the main sensor element: SM_config1 and SM_config2 (NVM addresses 14_HEXand 15_HEX; see Table 34)

 For an optional external temperature sensor: extTemp_config1 and extTemp_config2 (NVM addresses 16_HEX

and 17_HEX; see Table 34).

The first 7 bits of the *_config1 registers are the programmable gain settings Gain_stage1 and Gain_stage2. The

options for the programmable gain settings are listed in Table 5 and Table 6. The resulting analog gain is the

linear product of the stage 1 and stage 2 selection: Gain_PGA= Gain₁ Gain₂. With the programmable

Gain_polarity bit in the *_config1 registers, the sign of the effective PGA gain can be swapped; e.g., to invert the

sensor characteristic’s slope and invert signal processing of the differential signal between INP and INN.

Table 5.

PGA Gain: Stage 1

Gain_stage1[3:0]

Gain₁[V/V]

bit[3]

bit[2]

bit[1]

bit[0]

1.2

120

150

200

240

300

Not assigned

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ZSSC3240

Table 6.

Datasheet

PGA Gain: Stage 2

Gain_stage2[2:0]

Gain₂[V/V]

bit[2]

bit[1]

bit[0]

1.1

1.2

1.3

1.4

1.5

1.6

1.7

1.8

In addition to the amplification of the sensor input signals, the PGA’s first stage can perform an absolute offset

shifting of the differential sensor signal. This shift operation can be programmed in 1mV steps with the

configuration setup ioffsc bit field in the SM_config2 and extTemp_config2 registers. The effective voltage-shift

depends on the selected Gain₁, Gain_stage1. The V_IOFFSCvalues (in Table 8) correspond to the higher Gain₁

values, i.e. Gain₁> 100. The PGA-operation including shift effect for a differential input signal, V_DIFFincan be

described as:

(

)

− Gain₂

V_ADC,IN= Gain₂

∙

Gain₁

∙

V_DIFFin+ V

∙

Equation 1

IOFFSC

Table 7.

Symbol

Absolute Offset Shift – Properties

Parameter

Minimum

Typical

Maximum

Units

Relative accuracy of the effectively applied Offset Shift

referenced to the selected setup per ioffsc[4:0], IC-to-IC variation

_IOFFSC

0.89

0.98

1.07

1^storder temperature coefficient for the change of the effective

Offset Shift voltage for negative-voltage shift effects, i.e.

ioffsc[4]=0

TC_neg,IOFFSC

-0.25

-0.21

PPT/K

1^storder temperature coefficient for the change of the effective

Offset Shift voltage for positive-voltage shift effects, i.e.

ioffsc[4]=1

TC_pos,IOFFSC

0.21

0.25

PPT/K

Fluctuation of output offset signal (V_IOFFSC) versus nominal value

SNR_IOFFSC

–

at 25°C; 20·log10(V_IOFFSC/V_IOFFSC

)

The shifting can be configured independently for the main sensor and the optional, external temperature sensor.

If the absolute offset shifting is enabled, then the ZSSC3240 current consumption increases by 100µA. The

advantage of absolute offset shifting is an increase of analog dynamic range in the ZSSC3240’s sensor front-

end, which results in higher measurement result quality (less noise/fluctuations).

Table 8.

Absolute Offset Shift – Differential Sensor Signal’s Offset Compensation

ioffsc[4:0]

Shift Effect, V_IOFFSC

bit[4]

bit[3]

bit[2]

bit[1]

bit[0]

0mV, no shift

-1mV

-2mV

-3mV

-4mV

-5mV

-6mV

-7mV

-8mV

-9mV

-10mV

-11mV

-12mV

-13mV

-14mV

-15mV

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ZSSC3240

Datasheet

ioffsc[4:0]

Shift Effect, V_IOFFSC

bit[4]

bit[3]

bit[2]

bit[1]

bit[0]

0mV, no shift

1mV

2mV

3mV

4mV

5mV

6mV

7mV

8mV

9mV

10mV

11mV

12mV

13mV

14mV

15mV

The PGA can perform an automatic adjustment for the PGA input to ADC input common mode. This can be

enabled via the pga_en_shift bit in the *_config2 registers. The supportable input common mode range at the

PGA, i.e. at the sensor front-end input, is constant per IC because it is derived from the internally regulated

voltage VDDA_int.

Table 9.

PGA Input Span Ranges

Gain₁

Total Gain, G_AMPExamples

Gain₂

Max. Input Span, Differential Signal Range [mV]

540

420

330

280

220

144

103

300

200

120

1.8

1.4

1.1

1.4

1.1

1.2

1.3

1.1

1.2

1.5

1.2

1.3

1.5

1.6

1.1

1.7

1.3

1.5

1.1

5.0

6.4

8.1

9.6

12.2

18.5

25.9

30.5

37.5

19.2

13.2

10.2

5.2

140

204

264

519

900

1400

3.0

1.32 ^[a]

1.2

[a] There is a general PGA-input range constraint to support V_INdiffof ±700mV at maximum, which is especially dominating for G_AMP< 2.

6.2.2.

Analog-to-Digital Converter (ADC)

An analog-to-digital converter (ADC) is used to digitize the amplifier signal. To allow optimizing the trade-off

between conversion time and resolution, the resolution can be programmed from 12-bit to 24-bit (adc_bits bit

fields in the SM_config1, and extTemp_config1 registers; see section 6.6.2.1). The ADC processes differential

input signals around its input common mode level: V_ADCmid. Table 10 lists the ADC resolution, signal ranges,

conversion times for a single Analog-to-Digital conversion.

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Table 10. Single Analog-to-Digital Conversion

adc_bits[3:0]

ADC

Resolution

[Bits]

Ratiometric ADC

Input Range ^[a]

Absolute ADC

Conversion

Time, Typical

[µs]

Conversion

Rate, Typical

[kHz]

Input Range ^[b]

V_ADC,IN[V]

Bit[3] Bit[2] Bit[1]

Bit[0]

V_ADC,IN[V]

±1.42

±1.43

±1.41

±1.42

±1.41

±1.42

±1.41

±1.42

±1.41

±1.42

±1.41

±1.42

±1.40

–

±1.07

±1.08

±1.06

±1.07

±1.06

±1.07

±1.06

±1.07

±1.06

±1.07

±1.06

±1.07

±1.06

–

162

192

235

294

380

497

670

903

1245

1715

2400

3335

4705

–

6.1

5.2

4.2

3.4

2.6

2.0

1.4

1.1

0.8

0.5

0.4

0.3

0.2

–

Not assigned

–

[a] With the following settings: ratiometric reference, sel_ref* = 1, and no ADC-shift (adc_en_shift = 0) nor extra ADC-gain, i.e. Gain_ADC=1

[b] With the following settings: absolute reference, sel_ref* = 0, and no ADC-shift (adc_en_shift = 0) nor extra ADC-gain, i.e. Gain_ADC=1

The ADC can perform an additional offset shift (independent of the PGA shifting with ioffsc) in order to adapt

input signals with offsets to the ADC input range. The shift feature is enabled by setting adc_en_shift = 1 (bit[8]

in the SM_config2 or extTemp_config2 registers). As defined in Table 11, the respective analog offset shift can

be selected with bits [14:12], adc_offset in SM_config1 or extTemp_config1.

Note: Enabling the offset shift causes the ADC to perform an additional amplification of the ADC’s input signal by

factor 2. This must be considered for a correct analog sensor setup by means of the PGA’s gain, the absolute

offset shift in the PGA, the ADC offset shift, and the potential ADC gain.

The overall analog amplification Gain_TOTAL= Gain_PGA· Gain_ADCcan be determined for the following potential use

cases using Equation 2 or Equation 3 depending on the ADC offset setting:

If no ADC offset shift is selected, i.e., adc_en_shift = 0 and adc_offset = 000, then

Gain_TOTAL= Gain_PGA 1

Equation 2

If ADC offset shift is selected, i.e., adc_en_shift = 1 (adc_offset is configurable), then

Gain_TOTAL= Gain_PGA 2

Equation 3

Table 11. ADC Offset Shift

adc_offset[2:0]

Compensation of Percentage

Offset in Input Signal

ADC Input Signal

Range [V_ADC,IN]

bit[2]

bit[1]

bit[0]

-0.5 to 0.5

-0.44 to 0.56

-0.38 to 0.62

-0.31 to 0.69

-0.25 to 0.75

-0.19 to 0.81

-0.13 to 0.87

-0.06 to 0.94

-1 to +1

6.25%

12.50%

18.75%

25.00%

31.25%

37.50%

44.00%

ADC-offset shift disabled, adc_en_shift = 0

0% (compensation, 2-gain off)

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ZSSC3240

Datasheet

6.2.3.

Internal Temperature Sensor

The ZSSC3240 provides an internal temperature sensor measurement to allow compensation for temperature

effects. The temperature output signal is a differential voltage that is adapted by the amplifier (PGA) for the ADC

input, comparable to the external sensor’s signal. For ZSSC3240-internal temperature measurements, the

respective settings are defined and programmed in the NVM by Renesas.

6.2.4.

Supported Supplies for Sensor Elements and Additional, External Temperature Sensing

There are two options to supply and bias the external sensor element, which can be selected by the sensor_sup

bit field in the SSF1 register (03_HEX) in the NVM (see Table 34). The differential sensor signal (e.g., from a

sensor bridge) is fed into the ZSSC3240 at the INP pin for the positive and the INN pin for the negative signal

level.

Table 12. Sensor Supply Options

sensor_sup[1:0]

External Sensor Supply

bit[1]

bit[0]

Ratiometric voltage: VDDB to VSSB.^[a]

Bias current out of VDDB. ^[a]

No supply, INN internally connected to AGND, absolute voltage-source measurement (e.g., thermopile

between INP and INN).

Not assigned.

[a] The combination of settings temp_source = 100 and sensor_sup=01 returns the sensor to be supplied by a ratiometric voltage.

There are multiple possible combinations of an external main sensing supply and the SSC-input signal

generation with different sensing elements and approaches for generating a temperature signal for temperature-

dependency compensation. Table 13 illustrates the possible sensor connections, application circuits, and

ZSSC3240 configurations.

Note: The applications circuits S1 to S3 and T1 to T5 highlight the supply paths in blue and the input signal paths

in red for the main sensing element connection and supply in Table 13 and for the supporting, external

temperature sensing in Table 15.

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Datasheet

Table 13. Sensor Supply – Main Sensing

Application

Front-End Configuration, Sensor Application, and Connection Circuit

Setup and Remarks

General sensor front-end overview for

main and supporting temperature

sensor connection and setup

T_EXT

Internal

Temp.

Sensor

Bias

Current

V_TP

V_TN

VDDB

R_t

INP

VSSB

INN

PGA

extra_rt

R_t´

Ratiometric bridge-type sensor setup:

 Sensor element supplied through an

ZSSC3240-internal, regulated

voltage

Regulated Voltage,

VDDA

T_EXT

Internal

Temp.

Sensor

Bias

Current

Sensor

Element

VDDB

Sensor

 sensor_sup = 00_BIN

 Could also be combined with the

internal temperature sensor or any

external temperature sensor

configuration using a ratiometric

supply

V_sup

INP

VSSB

INN

PGA

Note: if temp_source = 100_BIN

(temperature application T3.2) is also

set up, the sensor_sup = 01_BINmust be

configured in order to get the S1

application functionality.

Current Mode bridge-type sensor

setup:

 Sensor element biased through an

ZSSC3240-internal current source

via VDDB pad

Regulated Voltage,

VDDA

Internal

Temp.

Sensor

T_EXT

I_sup

Sensor

Bias

Current

Sensor

VDDB

Element

 sensor_sup = 01_BIN

 Could also be combined with the

internal temperature sensor or any

external temperature sensor

configuration using the Current

Mode supply

INP

VSSB

INN

PGA

Absolute-voltage sensor setup:

 Sensor element not supplied

 sensor_sup = 10_BIN

Regulated Voltage,

VDDA

T_EXT

Internal

Temp.

Sensor

Bias

Current

VDDB

 Could also be combined with the

internal temperature sensor

Sensor

(temp_source = 000_BIN) or an

external single-diode temperature

sensor configuration in Current

Sensor

Element

Mode (temp_source = 100_BIN

)

INP

VSSB

INN

Voltage

Source

Note: Only up to a maximum of 50% of

the input dynamic range is useable in

this configuration

PGA

AGND

For a ratiometric sensor supply, the VDDA_intvoltage from the ZSSC3240-internal regulator is used. As defined in

Table 14, the alternative sensor bias current source generates a bias current that is programmable with the

Tbiasout in bit field in the *_config2 registers (see Table 34).

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ZSSC3240

Datasheet

Table 14. Sensor Bias Currents – Sensor Sourcing in Current Mode

Tbiasout

Nominal Sensor

bit[2]

bit[1]

bit[0]

Bias Current [µA]

157

196

494

The ZSSC3240 supports internal and external temperature sensing for sensor-signal conditioning (SSC)

purposes; i.e. an extra, separate temperature measurement in order to compensate temperature effects in the

measurand signal from the main sensing element; e.g., a pressure sensor. The respective setup must be

configured via the temp_source bit field in the SSF1 register.

If the main sensing element itself with its inherent temperature sensitivity is used to generate the temperature

information for SSC correction, then the internal_rt and extra_rt bit fields in the SFF1 register must be

programmed. Table 15 provides an overview for the some of the supported temperature measurement options.

The internal resistors Rt and Rt’ have been designed for flat, almost zero-sensitivity to temperature, such that the

resulting temperature sensor measurements’ characteristic is mainly dominated only by the (typically spurious)

temperature characteristic of the main sensor element itself. The use of the bottom resistance Rt’, selectable by

extra_rt, is recommended for most related applications in order to have a bridge-resistance-related, symmetric

temperature excitation, and not to introduce further differential signal offset when using the bridge-sensor

element as the temperature sensor.

In any configuration, the constraints for the minimum/maximum absolute and differential input signal dynamics

must be considered.

Table 15. Sensor Supply – Temperature Sensing

Application

Front-End Configuration, Temperature Sensor Application, and Connection Circuit

Setup and Comments

Bridge as the temperature

sensor with the internal Rt in

Current Mode

 Sensor element supplied

through the ZSSC3240-

internal bias; i.e., the

current source

Regulated Voltage,

T_EXT

VDDA

I_sup

Internal

Temp.

V_TP

V_TN

Sensor

Bias

Current

Sensor

Element

VDDB

Sensor

R_t

 temp_source = 001_BIN

 internal_rt = User selected

 extra_rt = 0_BIN

R_sens

INP

VSSB

INN

Note: Only combine this T1

application with

sensor_sup = 01_BIN(i.e.,

main sensing application S2

in Table 13)

PGA

R_t´

extra_rt

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ZSSC3240

Datasheet

Application

Front-End Configuration, Temperature Sensor Application, and Connection Circuit

Setup and Comments

Bridge as temperature

sensor with an external Rt in

Current Mode:

 Sensor element supplied

through the ZSSC3240-

internal bias, i.e. the

current source

I_sup

Regulated Voltage,

Sensor

Element

T_EXT

VDDA

Internal

Temp.

V_TP

V_TN

Sensor

Bias

Current

VDDB

Sensor

R_t,external

R_t

 temp_source = 010_BIN

 internal_rt = value close to

R_t,external

R_sens

INP

VSSB

INN

 extra_rt = 0_BIN

PGA

Note: Only combine this T2

application with

sensor_sup = 01_BIN(i.e.,

main sensing application S2

in Table 13)

R_t´

extra_rt

Separate diode / PTC-

resistor as temperature

sensor in Current Mode:

 Sensor element supplied

through the ZSSC3240-

internal bias, i.e. the

I_sup

Regulated Voltage,

VDDA

T_EXT

Internal

Sensor

Bias

Current

Temp.

Sensor

VDDB

Sensor

Element

current source

 temp_source = 100_BIN

 internal_rt = any

INP

AGND

 extra_rt = 0_BINand

sensor_sup = 10_BIN(no Rt‘

and absolute voltage

sensor, i.e. main sensing

application S3)

T3.1

PGA

VSSB

INN

extra_rt

R_t´

 sel_ref2 = 0_BINmust be

selected

Note: The voltage at T_EXT

must fulfill input conditions

and must be in the range of

0.5V to 1.25V

Separate diode / PTC-

resistor as temperature

sensor in Current Mode:

 Sensor element supplied

through the ZSSC3240-

internal bias, i.e. the

I_sup

Sensor Element

Regulated Voltage,

VDDA

Internal

Temp.

Sensor

T_EXT

Sensor

Bias

Current

V_TP

V_TN

VDDB

R_t

current source

R_sens

 temp_source = 100_BIN

 internal_rt = any

INP

VSSB

INN

AGND

PGA

 extra_rt = 0_BINand

sensor_sup = 01_BIN

(different from other

application cases, Rt‘ is

connected here and the

Main Sensor Bridge is

supplied ratiometrically,

i.e. main sensing

R_t´

extra_rt

T3.2

application S1)

 sel_ref2 = 0_BINmust be

selected

Note: The voltage at T_EXT

must fulfill input conditions

and must be in the range of

0.5V to 1.25V

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ZSSC3240

Datasheet

Application

Front-End Configuration, Temperature Sensor Application, and Connection Circuit

Setup and Comments

Temperature sensor with

internal Rt with ratiometric

supply

 Sensor element supplied

through the ZSSC3240-

internal regulated voltage

VDDA, i.e. radiometric

supply

Regulated Voltage,

T_EXT

VDDA

Internal

V_TP

V_TN

Sensor

Bias

Current

Sensor

Element

Temp.

Sensor

VDDB

R_t

R_sens

 temp_source = 101_BIN

 internal_rt = User selected

 extra_rt = 0_BIN

INP

VSSB

INN

V_sup

PGA

Note: Only combine this T4

application with

sensor_sup = 00_BIN(i.e.,

main sensing application S1

in Table 13)

R_t´

extra_rt

Temperature Sensor with

external Rt with ratiometric

supply

 Sensor element supplied

through the ZSSC3240-

internal regulated voltage

VDDA; i.e., the

Regulated Voltage,

VDDA

Internal

Temp.

Sensor

Element

T_EXT

Sensor

Bias

Current

V_TP

V_TN

VDDB

R_t,external

R_t

radiometric supply

R_sens

 temp_source = 110_BIN

INP

VSSB

INN

 internal_rt = any value

close to the external Rt

value

PGA

R_t´

 extra_rt = 0_BIN

extra_rt

Note: Only combine this T5

application with

sensor_sup = 00_BINonly (i.e.,

main sensing application S1

in Table 13)

When using scenario T1, “Bridge as the temperature sensor with the internal Rt in Current Mode” in Table 15,

the setup for bias current (I_sup) and internal Rt must fulfill the requirements given in Equation 4 and Equation 5:

Equation 4

(0.5  R_sens+ Rt)  I_sup= 0.85V ±125mV

Where R_sensis the nominal resistance of the sensor element; i.e. the typical, effective resistance

generating the differential sensor signal as input to the INP and INN pads.

Important: Take into consideration the maximum specifications for the PGA common mode input

level, V_Cmin(see Table 4).

Equation 5

(MAX[R_sens] – MIN[R_sens])  I_sup< 700mV

Important: Take into consideration the maximum specifications for the input signal, MAX[V_DIFFin

]

(see Table 4).

The best method for deriving the respective values for Rt and I_supis to choose an Rt value close to but greater

than R_sensand to calculate I_supaccordingly.

When using scenario T4, “Temperature sensor with internal Rt with ratiometric supply,” in Table 15 the setup for

bias current (I_sup) and internal Rt must fulfill Equation 6:

Important: Take into consideration the maximum specifications for the PGA common mode input

level, V_Cmin, which is automatically ensured if Rt and the extra Rt’ are selected.

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Equation 6

(MAX[R_sens] – MIN[R_sens]) / (R_sens+ 2  Rt)  VDDB_typ< 700mV

Important: Take into consideration the maximum specifications for the input signal, MAX[V_DIFFin

]

with VDDB_typ= 1.85V.

In most cases, a low Rt value will suffice for ratiometrically supplied configurations. The lower the applied Rt

value, the less the noise-level effect onto the temperature measurement signal.

Sensor-bridge elements, which already contain a top resistor for temperature sensing purposes, can use the

internal extra Rt’.

6.3

On-Chip Diagnostics

The ZSSC3240 offers analog and digital self-test and sensor-diagnostic features to ensure robust system

operation. If the part is programmed and operated with analog output (cont_ANAoutn = 0_BINin the SSF2 register;

see Table 34), then diagnostic states are indicated by upper and lower levels at the AOUT pin; see Table 16.

With the SPI, I2C, and OWI digital interfaces, the default status byte contains fault-diagnostics information. If

further detailed diagnostic information is required, the CHECK_DIAG command B0_HEXmust be issued to retrieve

the detailed diagnostics’ results in the diagnosticreg output register. The content of diagnosticreg (see Table 17)

is updated each time new respective diagnostic information becomes available. This is also the case with the

default ZSSC3240 initialization after power-on-reset (POR) or if specific commands are triggered in order to

perform diagnostic checks or influence diagnosticreg:

RESET_DIAG, B1_HEX

UPDATE_DIAG, B2_HEX

Resets the contents of diagnosticreg.

Performs all enabled diagnostic checks (selected via the select_checks bit field

[9:0] in register 21_HEXin NVM; see Table 34) and default diagnostic checks

including checksum validation of the NVM; results in complete update of

diagnosticreg.

Connection Checks

These are scheduled connection checks in the Cyclic Mode setup. All enabled

checks (as selected with select_checks) are performed, and diagnosticreg is

updated accordingly.

The analog signalization of diagnostic states at the AOUT pin for the different analog output options can be

enabled/disabled via the diagouten bit in the SSF2 register 04_HEXin the NVM (see Table 34). In Cyclic Mode, the

analog signalization of a diagnostic state is present with the SSC Calculation and Output Update phase of the

same measurement slot; see section 6.5.2. In Command Mode (with enabled analog output at AOUT pin), the

diagnostic state at AOUT will be present with completion of the next SSC-conversion command, i.e. AA_HEXor

AC_HEXto AF_HEX; see Table 33).

Table 16. Diagnostic Signalization Options with ZSSC3240

Analog Ratiometric

Analog Absolute Diagnostic OWI, SPI, I2C Status

Detected Fault

No Error / Fault

Memory Error

Comments

Diagnostic Level, AOUT ^[a]

Level, AOUT ^[a]

Byte [7:0]

0.125 to 4.875 V ^[b]

0.025 to 0.975 V ^[c]

0 to 0.125 V ^[b]

Status after “reset.”

2.5% to 97.5%

Lower

01XXX000_BIN

Checksum failure of

NVM.

0XXXX1XX_BIN

0 to 0.025 V ^[c]

Loss of INP

Connection, INP

Open ^[d]

4.875 V to VDD^[b]

0.975 to 1.0 V ^[c]

Upper

A detailed, digital

decoding of the

respective connection

check fault can be

fetched using the B0_HEX

CHECK_DIAG

command, which returns

the diagnosticreg register

content.

Loss of INN

Connection, INN

Open ^[d]

4.875 V to VDD^[b]

0.975 to 1.0 V ^[c]

0XXXXX1X_BIN

4.875 V to VDD^[b]

0.975 to 1.0 V ^[c]

4.875 V to VDD^[b]

0.975 to 1.0 V ^[c]

0 to 0.125 V ^[b]

INN or INP Signals

Out of Range

Upper

Lower

Bridge/Sensor

Short (INN=INP) ^[d]

T_ext Pin Open

0 to 0.025 V ^[c]

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Analog Ratiometric

Analog Absolute Diagnostic OWI, SPI, I2C Status

Detected Fault

Comments

Diagnostic Level, AOUT ^[a]

Level, AOUT ^[a]

0 to 0.125 V ^[b]

Byte [7:0]

T_ext Pin Out of

Range

Lower

0 to 0.025 V ^[c]

0 to 0.125 V ^[b]

0 to 0.025 V ^[c]

0 to 0.125 V ^[b]

0 to 0.025 V ^[c]

0 to 0.125 V ^[b]

0 to 0.025 V ^[c]

4.875 V to VDD^[b]

0.975 to 1.0 V ^[c]

T_ext Pin Short to

INP

T_ext Pin Short to

INN

Lower

Die Crack /

Chipping Check

Lower

SSC Calculation

Unit Saturation

Upper (extra)

0XXX XXX1_BIN

[a] Only signalized if diagouten = 1_BIN

[b] With VDD = 5V ±10%, for 0 to 5V absolute analog out.

[c] With any VDD, for 0 to 1V absolute analog out.

[d] Do not enable if the IC is connected to an absolute voltage source sensor, for example, Thermopile (sensor_sup = 10_BIN) with

typical internal resistances >60kΩ.

If multiple failures are detected leading to analog outputs that would be contradictory to each other, the high

signal is always provided. The effective absolute, analog diagnostic-output level is constant for lower and upper

diagnostic signal output. This absolute level may vary from IC to IC slightly. Hence, the effective lower and upper

level for the absolute AOUT signal in the event of a valid diagnostic and failure event, respectively, are not

influenced by any diagnostic-related setup in NVM nor by calibration coefficients, etc., per the Aout_setup bit

field in register 04_HEXin NVM (see Table 34). However, the threshold (i.e., the sensor-signal-valid maximum for

the upper and minimum for the lower diagnostic band) can be programmed and adjusted via proper calibration

and the diagouten bit in register 04_HEX

Table 17. Information Assignment for CHECK_DIAG Command: Output Register diagnosticreg [15:0]

Bit-Number

Connection Check

Content

DAC

Meaning

No Error / Fault

Output^[a]15 14 13 12 11 10

Yes

From SSC

Fault information improved since

last status information

–

Loss of sensor positive

connection, INP

2dacres – 7

Yes

Loss of sensor negative

connection, INN

Signal at INP pin out of range

(leaking / short to VSS or VDDB)

Signal at INN pin out of range

(leaking / short to VSS or VDDB)

Sensor short (INN = INP)

TEXT pin open

Yes

2dacres – 7

0007_HEX

Signal at TEXT pin out of range

(leaking / short to VSS or VDDB)

0007_HEX

Yes

TEXT pin short to INN

Yes

0007_HEX

SSC Calculation Unit saturation

2dacres – 7

0007_HEX

Memory error, checksum-check

failure

TEXT pin short to INP

Yes

0007_HEX

Die crack / chipping check failure

[a] The effective low limit for the DAC and resulting AOUT output signaling scales with the set up DAC resolution and is 16-bit =

0007_HEX, 15-bit = 000E_HEX, 14-bit = 0015_HEX, or 13-bit = 001C_HEX.

If a bit reset, i.e. a change from 1_BIN(FAULT) back to 0_BIN(NO-FAULT), for any bit occurs, diagnosticreg[0] is set

in order to signal an improvement of fault states during the ZSSC3240 operation. This is especially relevant for

Cyclic Mode and Continuous Analog-Output Mode operation.

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The select_checks bit field in NVM register 21_HEX¹can be programed to select which (analog) checks are

executed and/or signalized when the UPDATE_DIAG command is triggered or when a connection check is

performed during Cyclic Mode operation. Checks that are not selected do not result in diagnosticreg register

updates and are not signalized at the DAC and AOUT output.

6.4

Digital Interfaces

The ZSSC3240 supports three different digital interface protocols: SPI, I2C, and OWI. The implementation of the

interfaces is such that the available commands (section 6.6.1) and request codes for the ZSSC3240 are the

same regardless on the interface type used.

The selection of whether the ZSSC3240 operates with SPI, I2C, or OWI interface is determined in the start-up

phase after power-on. Initially all interface relevant parameters are loaded from address 02_HEXin the NVM (slave

address, SPI configuration). If the first command after power-on is a valid and properly formatted I2C request

including the correct slave address, the interface is fixed as an I2C slave. If, instead, there is an active signal at

the SS pin as the first valid activity, then the IC is fixed as an SPI slave. Alternatively, a valid OWI start (within

the start-up window) will fix the interface as OWI. Once, the interface is established and fixed, a change of the

interface can only be done by means of a power-on-reset. The status byte defined in Table 18 is common for all

supported interface types, and it is part of the ZSSC3240’s digital response to read requests.

Table 18. General Status Byte

Bit-Number

Meaning

Connection

Check

Fault?

Memory

Error?

Math

Saturation

Powered?

Busy?

Mode

Table 19. Mode Status

Status[4:3]

Mode

Command Mode

Cyclic Mode

Sleep Mode

Renesas reserved

6.4.1.

SPI

The SPI interface mode is available if the first interface activity after ZSSC3240 power-up is an active signal at

the SS pin. The polarity and phase of the SPI clock are programmable via the CKP_CKE setting in bits [11:10] in

address 02_HEXas described in Table 34. CKP_CKE is two bits: CPHA (bit 10), which selects which edge of

SCLK latches data, and CPOL (bit 11), which indicates whether SCLK is high or low when it is idle. The polarity

of the SS signal and pin are programmable via the SS_polarity setting (bit 9).

The different combinations of polarity and phase are illustrated in Figure 5 and Figure 6. See Table 20 for the

timing parameters.

Recommendation for current loop applications: To minimize the effect of varying current draw in current loop applications, do not perform

short-connection checks (sens_short_check, text_inn_short_check, text_inp_short_check).

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CPHA=0

SCLK (CPOL=0)

SCLK (CPOL=1)

MOSI

MSB

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

LSB

MISO

/SS

SAMPLE

t_ssd

t_ssa

Figure 5. SPI Configuration CPHA=0

CPHA=1

SCLK (CPOL=0)

SCLK (CPOL=1)

MOSI

MSB

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

LSB

MISO

MSB

Bit1

LSB

/SS

SAMPLE

t_ssa

t_ssd

Figure 6. SPI Configuration CPHA=1

In SPI Mode, each command except NOP is started as shown in Figure 7. After the execution of a command

(busy = 0), the expected data can be read as illustrated in Figure 8 or if no data are returned by the command,

the next command can be sent. The status can be read at any time with the NOP command (see Figure 9).

Note: If SS and SCLK do not end after one complete read-response cycle, but continue for any reason, the

ZSSC3240 will start repeating; e.g. the measurement result data would repeat in the following sequence

(comparable to the OWI response shown in Figure 17):

Status  SensorData [23:16]  SensorData [15:8]  SensorData [7:0]  TempData[23:16]  TempData[15:8]

 TempData[7:0]  SensorData [23:16]  SensorData [15:8] ...

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Command Request

Command

otherthan

NOP

CmdDat

<15:8>

CmdDat

<7:0>

MOSI

MISO

Status

Data

Note: A command request always consists of 3 bytes. If the command is shorter, then

it must be completed with 0ꢀs. The data on MISO depend on the preceding command.

Figure 7. SPI Command Request

Read Data

(a) Example: after the completion of a Memory Read command

Command

= NOP

MOSI

MISO

00_HEX

MemData MemData

<15:8> <7:0>

Status

(b) Example: after the completion of a Measure command (AA_HEX

)

Command

= NOP

MOSI

MISO

00_HEX

SensorData SensorData SensorData TempData TempData TempData

<23:16> <15:8> <7:0> <23:16> <15:8> <7:0>

Status

Figure 8. SPI Read Data

Read Status

Command

MOSI

= NOP

MISO

Status

Figure 9. SPI Read Status

Table 20. SPI Interface Parameter

Note: See important table notes at the end of the table.

Symbol

Parameter

Conditions

Minimum

Typical

Maximum

Units

f_SCLK

D_SPI

Interface clock

Duty cycle

0.05

–

MHz

V_high,SPI

Input high level voltage

Input low level voltage

Referenced to external

supply voltage V_DD

(maximum 5.5V)

0.7

1.0

V_DD

V_low,SPI

SR_SPI

0.0

–

0.3

V_DD

Input rising and falling edge slew rate

0.26

V/ns

Delay time^[a]between SS-activation

edge and first edge of SLCK, MOSI or

MISO

Delay time ^[a]between SS-deactivation

edge and last edge of SLCK, MOSI or

MISO

t_ssa

–

“Typical” is for f_SCLK≤ 3MHz

operation

t_ssd

Delay between SS-deactivation edge of

last command and of SS-activation edge

for next command

t_ss

–

µs

I_MISO

Driving current of SPI output (peak)

–

180

[a] Typical: For conditions with no clocks prior and after the command and data bytes, the maximum values for t_ssaand t_ssdare not

relevant; under conditions with clocks prior to and after command and data, there is a maximum for t_ssaand t_ssd= 0.3/f_SCLK

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6.4.2.

I2C

I2C Mode is selected if the first interface activity after the ZSSC3240 power-up is an I2C command with valid

slave address. In I2C Mode, each command is started as shown in Figure 10. Only the number of bytes that are

needed for the command must be sent. An exception is the I2C High Speed Mode where 3 bytes must always

be sent as in SPI Mode. After the execution of a command (busy = 0), the expected data can be read as

illustrated in Figure 11 or if no data are returned by the command, the next command can be sent. The status

can be read at any time as described in Figure 12.

Command Request (IC Write)

From master to slave

From slave to master

START condition

STOP condition

Acknowledge

SlaveAddr 0 A Command A P

write

CmdData

<15:8>

CmdData

<7:0>

SlaveAddr 0 A Command

write

A P

Not acknowledge

Figure 10. I2C Command Request

Read Data (I2C Read)

(a) Example: after the completion of a Memory Read command

MemData

<15:8>

MemData

<7:0>

SlaveAddr 1 A

read

Status

N P

(b) Example: after the completion of a Measure command (AA_HEX

)

SensorData

<23:16>

SensorData

<15:8>

SensorData

TempData

<23:16>

TempData

<15:8>

TempData

<7:0>

SlaveAddr 1 A

read

Status

N P

<7:0>

Figure 11. I2C Read Data

Read Status (I2C Read)

SlaveAddr 1 A

Status

N P

read

Figure 12. I2C Read Status

Table 21. I2C Interface Parameter

Symbol

f_SCL

Parameter

Interface clock

Duty cycle

Conditions

Minimum

Typical

Maximum

Units

MHz

0.1

–

3.4

D_SPI

Input high level

voltage

Referenced to external supply

voltage V_DD.

V_high,I2C

V_low,I2C

0.7

0.0

–

1.0

0.3

V_DD

Input low level

voltage

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ZSSC3240

Datasheet

Symbol

Parameter

Conditions

Minimum

Typical

Maximum

Units

Capacitive load at

input pin, SDA

100pF: maximum for Standard and

Fast Mode; in HS Mode

f_SCL,max= 3.4MHz

C_SDA

–

100

400

400pF: only in HS Mode;

f_SCL,max= 1.7MHz

Low level output

current

V_SDA=0.4V; Standard and Fast

Mode with 400kHz; 400pF load

I_OL

Details for timing and protocol of the ZSSC3240-supported I2C communication in Standard Mode, Fast Mode,

and High-Speed Mode are given in I2C-Bus Specification, Rev.6, UM10204.

6.4.3.

One-Wire-Interface, OWI

The ZSSC3240 employs a one-wire digital interface concept (OWI). It combines a simple and easy protocol

adaptation with a cost-saving pin sharing. The communication principle of the OWI interface is derived from the

I2C protocol.

OWI-Slave

OWI-Master

Dynamic Driving,

switch-on only

during OWI-Slave-

Output phases

ZSSC3240

5µA

R_OWI,PULLUP

AOUT

VSS

R_OWI,LINE

C_OWI,LINE

Figure 13. General Block Schematic of the OWI Interface

Both the analog output signal and the digital OWI interface use the same pin, AOUT. An advantage of the OWI is

that it enables “end of line” calibration – no additional pins are required to digitally calibrate a finished assembly.

Although the OWI is integrated mainly for calibration, it can also be used to read out the calibrated sensor signal

continuously or retrieve diagnostic detail information.

The OWI protocol is defined as follows:

 Idle State: During inactivity of the bus, the OWI line is pulled up to the supply voltage V_DDby an external

resistor.

 Start Condition: When the OWI line is in idle mode, a low pulse with a minimum width of t_OWI,START≥ 10μs and

then a return to high indicates a start condition. Every request must be initiated by a start condition sent by a

master. A master can generate a start condition only when the OWI line is in idle mode.

 Valid Data: Data is transmitted in bytes (8 bits) starting with the most significant bit (MSB). Transmitted bits

are recognized after a start condition at every transition from low to high at the OWI line. The value of the

transmitted bit depends on the duty ratio between the high phase and high/low period (bit period, t_OWI,BITin

Figure 14). A duty ratio greater than 1/8 and less than 3/8 is detected as 0; a duty ratio greater than 5/8 and

less than 7/8 is detected as 1. The bit period of consecutive bits must not increase to more than 1.5 times the

previous bit period or decrease to less than half of the previous bit period because a stop condition is detected

in this case.

The length of the OWI-line and the size of R_OWI,PULL(if it is statically connected to AOUT), and consequently the

resistive and capacitive load influence the maximum possible interface speed and minimum Bit period,

respectively. Further, it can be beneficial for harsh EMC conditions to intentionally add capacitance to the OWI1

(AOUT) line in order to improve RF disturbance robustness. Table 22 shows some practical OWI-interface

dimensioning examples and the resulting maximum signal frequencies (minimum possible Bit periods). The

complete ZSSC3240’s OWI interface properties and timing capabilities are given in Table 23.

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Table 22. OWI Dimensioning Examples

R_OWI,PULL

(+ R_OWI,LOAD

)

1.8 kΩ

2.5 kΩ

3.3 kΩ

5.5 kΩ

10.0 kΩ

[a]

C_OWI,LOAD

20µs

113µs

249µs

373µs

497µs

576µs

20µs

157µs

345µs

518µs

691µs

801µs

21µs

207µs

456µs

684µs

912µs

1057µs

35µs

63µs

1nF

345µs

628µs

10nF

22nF

33nF

44nF

51nF

760µs

1381µs

2070µs

2762µs

3205µs

1140µs

1520µs

1760µs

[a] Examples are shown with statically connected R_OWI,PULL, and with minimum bit period: t_OWI,BIT

OWI protocol timing and parameters are specified in Figure 14, Figure 15, and Table 23.

Start

Stop Start

t_OWI,STOP

t_OWI,IDLE

t_OWI,START

t_OWI,BIT

t_OWI,0

t_OWI,1

Figure 14. OWI Timing Diagram

Note: Configuration for SSF1 register 03_HEXin NVM (see Table 34) to allow continuous OWI and concurrent

analog output: owi_off = 0, cont_ANAoutn = 0, owi_su_case = 1.

Start

t_OWIextraH

t_OWIextraL

t_OWI,START

t_OWI,BIT

Figure 15. OWI Extra (Activation) Pulse for Concurrent OWI and Analog Output Configuration

Table 23. OWI Interface Parameters

Symbol

Parameter

Conditions

Minimum

Typical

Maximum

Units

Programmable window length , see

owi_su_length, bit[2] in SSF1

OWI start-up “listening”

window

t_SUlength

–

For Cyclic and Command Mode

operation

Bus free time between

START and STOP

condition

t_OWI,IDLE

–

µs

Minimum in ZSSC3240 Sleep Mode

operation

Hold time for START

condition

0.5 ×

t_{OWI_BIT}

t_OWI,START

20µs

–

µs

Robust operation with:

t_OWI,BIT≥ 10  R_OWI,PULL C_OWI,LOAD

t_OWI,BIT

t_OWI,0

t_OWI,1

Bit period, bit time

3000

Duty ratio bit ‘0’

Duty ratio bit ‘1’

0.125

0.625

0.25

0.75

0.375

0.875

t_{OWI_BIT}

t_{OWI_BIT_L}is the bit period of the last

valid bit

t_OWI,STOP

Hold time STOP condition

1.5

t_{OWI_BIT_L}

Duration of most recent bit versus

previous bit duration

t_{OWI_BIT_DEV}

t_OWIextraL

Bit time deviation

0.55

43.5

1.0

–

1.45

49.5

–

t_{OWI_BIT}

µs

Length of extra pulse ^[a]

Duration of HIGH after

Aout-to-OWI extra pulse

OWI configuration to allow

continuous OWI and concurrent

analog output; see Figure 15.

t_OWIextraH

–

µs

Minimize C_OWI,LOADif ratiometric

DAC-output, Aout_setup = 001_BINis

configured for AOUT/OWI1

Capacitive load at OWI

line

C_OWI,LOAD

0.05

2.2

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Symbol

Parameter

Conditions

Minimum

Typical

Maximum

Units

If R_OWI,PULLvalues greater than

3.3kΩ were applied, the shortest

t_OWI,BITtimes cannot be achieved

anymore.

Pull-up resistance –

master ^[b]

R_OWI,PULL

1.8

2.5

3.3

kΩ

If R_OWI,LOAD>35Ω, OWI-timing

parameter (t_OWI,*) low-limits, i.e.

highest speeds are not guaranteed.

0.01 x

R_OWI,PULL

R_OWI,LOAD

Resistive OWI line load

–

V_OWI,inL

V_OWI,inH

Voltage level LOW

Voltage level HIGH

–

0.1

0.9

0.25

VDD

0.80

–

Open drain output at AOUT pin,

max. allowed current draw 5mA,

otherwise: V_OWI-S,LOW>0.1*VDD

V_OWI-S,LOW

Slave output level LOW

–

0.1

VDD

[a] To switch from analog output to “OWI listen” at AOUT pin.

[b] For the selection of R_OWI,PULL, the minimum current limit of the AOUT buffer and maximal VDD supply must take into account if

OWI and analog output voltage mode are set up to work concurrently; that is owi_off = 0, cont_ANAoutn = 0, and owi_su_case = 1.

If the current limitation condition (I_OUTmax, see Table 4) is exceeded, it is recommended to use the Dynamic Driving Approach for

R_OWI,PULLat the OWI-master, and only switch the R_OWI,PULLto AOUT when the OWI-master starts communication. This setting is

specifically recommended for the phases when the OWI-master listens to the AOUT-line, and the OWI-slave (the ZSSC3240) has

to respond, respectively.

The effective OWI properties depend on the load conditions at the OWI1 pin. Additional to Table 22, some

further applicable configurations are as follows:

 For maximum operation speed (50kHz) of OWI1, the capacitive load, C_OWI,LOADcan be up to 1nF and the

maximum R_OWI,PULLis 2.5kΩ.

 For high operation speed (10kHz) of OWI1, the capacitive load, C_OWI,LOADcan be up to 4.7nF and R_OWI,PULL

must be ≤ 3.3kΩ.

 For an equivalent frequency of 1kHz of OWI1, it should be ensured that C_OWI,LOAD≤ 22nF and R_OWI,PULL≤ 7kΩ,

or for example that C_OWI,LOAD≤ 66nF combined with R_OWI,PULL≤ 4.5kΩ.

Example 1: OWI Request, 1 Command Byte, 1 Data Word:

Optional

S 6 5 4 3 2 1 0 W 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 S

Slave Address [6:0]

Data Byte

Command Byte [7:0]

Data Word [15:0]

Example 2: OWI Request, 1 Command Byte, no Data:

S 6 5 4 3 2 1 0 W 7 6 5 4 3 2 1 0 S

S Start condition S Stop

condition

Read/write bit

(write = 0)

Data bit

(example: Bit 2)

Slave Address [6:0]

Data Byte

Slave address

(example: Bit 5)

Command Byte [7:0]

Sent by

Master

Figure 16. OWI Command Request

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Example: OWI Read Operation, Status Byte (+n) Data Bytes*:

Response data is sent in a loop, i.e. repeated until master generates stop condition

Optional

...

7 6 5 4 3 2 1 0 S

0 R 7

Slave Address [6:0]

Status Byte [7:0]

Data Byte [7:0]

...n^thData Byte

* n data bytes could be:

NVM read: 2 bytes,

Measure: 6 bytes,

Get_Raw: 3 bytes

Sent by

Master

Slave

Master

Read/write bit

(read = 1)

Slave address

(example: Bit 5)

Data bit

(example: Bit 2)

Stop condition

Start condition

Figure 17. OWI Response by ZSSC3240

The ZSSC3240 allows utilization of the OWI interface in different application configurations:

 OWI Disable: The OWI interface can be deactivated by owi_off = 1 (bit[13] in SSF1 register 03_HEX). For

example, this could be applied in cases when an analog-output smart sensor is configured and calibrated

using the OWI interface and the OWI will not be available after calibration and final setup/programming.

 OWI Only (no analog output): With the NVM configuration owi_off = 0 and cont_ANAoutn = 1, the AOUT will

not provide any analog outputs and is only used as the OWI pin. There is no startup window limitation

(owi_su_length is ignored by the ZSSC3240). If the first (valid) digital interface activity is the Startup OWI

(D2_HEX) command, the ZSSC3240’s interface type will be fixed as OWI communication (SPI and I2C will be

disabled/ignored).

 OWI with Startup Window and Analog Output: The OWI startup window followed by subsequent activation

of the analog output is possible with owi_off = 0, cont_ANAoutn = 0, and owi_su_case = 0. AOUT works as a

(listening) OWI signal pin after power-up until the selected startup window (owi_su_length) has elapsed. If the

Startup OWI (D2_HEX) command is received within the startup window, AOUT persists as the OWI

communication pin until a power-on reset occurs. If the ZSSC3240 does not receive the

Startup OWI command (D2_HEX) during the startup window, the OWI interface will be disabled and AOUT starts

functioning as an analog output.

 Continuous OWI and Analog Output: The configuration owi_off = 0, cont_ANAoutn = 0, and

owi_su_case = 1 results in AOUT providing analog output levels as soon as they are available after power-up

(in Cyclic Mode). Concurrently, the OWI listens to the AOUT ¹pin in order to check for valid OWI commands.

The OWI still needs to be enabled by means of the Startup OWI command. The physical protocol in this

configuration requires an extra pulse (see Figure 15) prior the Startup OWI command. After the release of the

extra OWI initialization pulse, the analog output is switched off ²and AOUT becomes the OWI I/O pin until the

OWI startup window (according to owi_su_length) has elapsed.

The OWI-master implements Dynamic Driving to avoid dynamic currents (due to DAC-output level changes)

causing unwanted pull-up signal generation (via R_OWI,PULL). When Dynamic Driving Approach is not applied in

this configuration, set the constantly connected OWI-master pull-up resistances (R_OWI,PULL) to ≥5.5kΩ to

prevent erroneous OWI-start detections that can be triggered by changing DAC-output levels. Limit the

interface speed to slower values with the proper setting, such as longer bit period.

Dependent on Aout_setup, OWI2 is the alternative input pin, e.g., in the case of the current loop setup, i.e. the Aout_setup bit field = 000 in

The DAC switch-off time point is variable and depends on the activity status in the measurement cycle, measurement execution, etc. It can

be anytime between the extra-pulse and a received, completed Startup OWI command.

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6.5

Measurement and Output Options

Sensor or diagnostic measurement results of the ZSSC3240 can be provided in both domains, digital and

analog. Any of the supported digital interfaces and output options can be used as the only active interaction

path, or it can be combined with any of the analog output configurations. For digital communication, only one

interface type can be active and supported (see section 6.4).

Digital communication via SPI and I2C are fully independent of the configuration and application of the

ZSSC3240’s analog outputs. For digital OWI communication combined with analog output, special application

circuits and constraints might have to be considered, as the OWI interface and the analog outputs use the same

pin, AOUT.

6.5.1.

Single Measurements, Digital Raw Results, and SSC Results

The IC generates digital raw values, which are processed by the ZSSC3240-internal math core generating the

SSC-corrected (linearized, temperature-compensated) output signal. See section 6.6.3 for details about the SSC

math, etc. In addition to the SSC-corrected digital measurement results, the ZSSC3240 can provide raw values

without SSC correction for evaluation and/or calibration purposes. The respective results are provided at the

digital interface as a 24-bit wide data word. Raw values and SSC results are MSB-aligned. Raw values are

formatted as two’s-complement, whereas SSC results are formatted as unsigned absolute value.

Table 24. Data Format of Raw ADC Readings

Bit-Number

…

Meaning,

Weighting

-2⁰

2^-1

2^-2

2^-3

…

2^-21

2^-22

2^-23

Table 25. Data Format of Corrected, SSC Results (S and T)

Bit-Number

…

Meaning,

Weighting

2⁰

2^-1

2^-2

2^-3

…

2^-21

2^-22

2^-23

The ZSSC3240 can process and digitize the following signals:

 SM: Direct sensor signal inputs; i.e., perform sensor measurements

 AZS: Auto-zero signals for the sensor channel

 TM: Direct temperature signal inputs, i.e. perform temperature measurements

 AZT: Auto-zero signals for the temperature channel

The internal sequence (in time) of A2D-conversions with both auto-zero measurements enabled is: first is AZS,

second is SM, third is AZT, and forth is TM. The utilization of auto-zero measurements allows further

optimization and reduction of the noise level for the sensor signal in combination with the inherent compensation

of the residual offsets of the analog sensor front-end. If an auto-zero measurement is enabled, then the sensor

signal remains the input for the auto-zero measurement with the gain and ADC set up as for the original signal

measurement, but with swapped inputs and offset configurations of the PGA and ADC such that the following

holds for the resulting raw value:

 Sensor raw value with auto-zero: S_raw = 0.5  (SM – AZS)

 Temperature raw value with auto-zero: T_raw = 0.5  (TM – AZT)

The application benefits with enabled auto-zero measurements are

 ZSSC3240 front-end offset cancellation – residual signal degradation¹or drift for the application is eliminated

 Improvement of the signal-to-noise ratio for the raw or SSC-corrected output signal

¹Worst-case IC-offset drift is < 2ppm/day at 125°C.

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On the other hand, the default application benefit without auto-zero measurements is an approximately 50%

faster output update rate compared to an equivalent configuration with enabled auto-zero measurements.

Recommendations: For applications where a faster update rate is the priority, disable and not apply the auto-

zero measurements. For applications where a better signal-to-noise level and maximum signal quality are the

priority, enable and apply the auto-zero measurements.

The NVM configuration and measurement-request commands can be used to select which measurements are

performed, processed, and provided at the digital interface. See Table 33 for command details.

Examples of options for a single measurement request and output:

 SSC-corrected sensor readings (requested by the Measure command AA_HEX) generating an output of SSC-

corrected, 24-bit sensor data followed by SSC-corrected, 24-bit temperature data.

 Raw sensor measurement with or without auto-zero correction (requested by the Raw Sensor Measure

command A2_HEX) generating an output of raw 24-bit sensor data.

 Raw temperature measurement with or without auto-zero correction (requested by the Raw Temperature

Measure command, A4_HEX) generating an output of raw 24-bit temperature data.

The auto-zero measurements can be disabled/enabled via the AZMs_on and AZMt_on bits in NVM registers

04_HEX(see Table 34).

Table 26 and Table 27 provide some exemplary, typical conversion times and noise performance values for the

ZSSC3240’s Front-End (PGA and ADC) in order provide some guidance for understanding effects and signal-

quality-related consequences while defining an application setup.

Table 26. Typical Conversion Times for Complete SSC Sensor Measurements: SM, TM

ADC Resolution (Main) Sensor

ADC Resolution Temperature Sensor

Typical Measurement Duration [ms] ^[a]

12 (external temperature sensor)

13 (internal temperature sensor)

14 (external temperature sensor)

16 (external temperature sensor)

18 (external temperature sensor)

24 (external temperature sensor)

0.38

0.47

0.53

0.67

0.82

1.40

9.47

[a] The time from the end of the SSC-measurement command request AA_HEXto signalization for the end-of-conversion at the EOC pin

with the ZSSC3240 in Command Mode; INT_setup bit field = 00_BINin register 02_HEX(see Table 34); 25°C; V_DD=5V; AZMs_on = 0_BIN

and AZMt_on = 0_BIN

;

The data is shown with ZSSC3240 default NVM configuration.

Table 27. Typical Conversion Times and Noise Performance for Complete SSC Measurements

ADC Resolution:

External Sensor [Bits]

Reference Source for External

Typical 3-sigma Noise for SSC-

Corrected (Digital) Output ^[b],S, T

Typical Measurement^[a]

Duration ^[c][ms]

Sensor (sel_ref1)

Absolute, sel_ref1=0

Ratiometric, sel_ref1=1

Absolute, sel_ref1=0

Ratiometric, sel_ref1=1

Absolute, sel_ref1=0

Ratiometric, sel_ref1=1

Absolute, sel_ref1=0

Ratiometric, sel_ref1=1

5 LSB_12Bit

7 LSB_12Bit

0.8

1.2

2.9

9.8

26 LSB_16Bit

51 LSB_16Bit

182 LSB_20Bit

270 LSB_20Bit

1122 LSB_24Bit

1354 LSB_24Bit

[a] Measurements including AZS, SM, AZT, TM with internal temperature measurement.

[b] Reference noise values normalized to the respective external sensor’s ADC resolution, obtained with the following setup:

10kΩ sensor bridge, 25°C, Gain=28, VDD=3.3V, ioffsc=00000 for sel_ref1=1, ioffsc=01111 for sel_ref1=0, adc_en_shift=0,

pga_en_shift=0, sensor_sup=00, cp_off=0.

[c] The time from the end of the SSC-measurement command request AA_HEXto signalization for the end-of-conversion at the EOC pin

with the ZSSC3240 in Command Mode; INT_setup bit field = 00_BINin register 02_HEX(see Table 34).

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6.5.2.

Cyclic, Continuous, Repeated Measurements – Measurement Scheduler

In addition to single measurement requests, such as AA_HEX, or the Oversample-x Measure requests (AC_HEXto

AF_HEX; see Table 33), the ZSSC3240 can be configured for cyclic measurement sequences. The continuously

running measurement sequence consists of individual measurement slots in which all or a selectable subset of

measurements and checks can be scheduled and allocated including sensor measurement (S), auto-zero

measurement for the sensor (AZS), temperature measurement (T), auto-zero measurement for temperature

(AZT), and diagnostic checks (see section 6.3). If AZS is enabled (AZMs_on = 1_BINin register 04_HEX

;

see Table 34 for details for registers), the sensor measurement (S) and auto-zero measurement for the sensor

(AZS) must be scheduled to always occur together for correct signal processing; i.e., these settings are required:

slots_S = slots_AZS in register 1F_HEXand startS_wfirstn = startAZS_wfirstn in register 1E_HEX. If AZT is enabled

(AZMt_on = 1_BINin register 04_HEX), the temperature measurement (T) and auto-zero measurement for

temperature (AZT) must be scheduled to always occur together for correct signal processing; i.e., these settings

are required: slots_T = slots_AZT and startT_wfirstn = startAZT_wfirstn (see registers 1E_HEXand 1F_HEX). For

applications where obtaining the fastest possible update rate is the highest priority, disabling the auto-zero

measurements is recommended, i.e., AZM*_on = 0_BIN, for which slot scheduling is user programmable without

constraints.

The automatically, continuously running measurement sequence is executed in Cyclic Mode, which is either

entered as the default main operating mode after power-on or entered by means of the START_CYC command,

AB_HEX

Figure 18 shows an example of the measurement sequence configurability. During the pauses in the sequence,

the ZSSC3240 signals that it is not busy (i.e., the Busy? bit = 0_BINin the general status byte; see Table 18). The

available measurement results are updated at the end of each SSC calculation and output operation and are

kept valid at the digital interface or DAC output until the next SSC calculation and output operation.

The configuration of the measurement scheduler is done in the NVM registers 1E_HEXto 20_HEX

Measurement example with the following requirements:

S every slot, start with first

No AZS (AZMs_on = 0_BIN

)

T every 7 slots, start with first

AZT every 7 slots, start with first

Sensor Connection Check every 10 slots, no start with first slot

Individual Measurement Slot Numbers

...

Time

Figure 18. Example Configuration for the Measurement Scheduling and Cyclic Mode Operation

A slot denotes all measurements that are conducted and updated before the next SSC calculation. There can be

pauses from one slot to the start of the next slot. The first slot has the slot number 0.

If the digital interface clock speed is too slow or contains long no-read pauses related to the SSC output update

rate in Cyclic Mode, intermediate results can be lost, and the respective read result can be outdated compared

to the related, read-concurrent, physical situation at the sensor (especially for very long pauses between two

interface read operations). This digital interface behavior is valid for all options: SPI, I2C, OWI.

In Cyclic Mode, the present data word (measurement result) at the interface output always follows the last data

(result) that was read at the interface. See Figure 19 for relatively slow interface polling compared to the internal

measurement data update rate in Cyclic Mode.

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result not output at interface ó ꢁLost

Informationꢂ

time

IC-internal operation

ꢀmeasurement result

ADC/SSC: measure

data 3

ADC/SSC: measure

data 5

ADC/SSC: measure

data 6

data 1

data 2

data 4

generation

data 1 to interface

for external read

data 4 to interface

for external fetch

data 2 to interface

for external read

interface

interface released to

get IC-internal data update

(next available data: data 2)

Data availability at Digital

Interface

ꢀfor result data polling

released to get IC-

internal data update

(next avail. data:

data 4)

result read at dig.

interface: data1

result read at dig.

interface: data 2

result fetch at I2C

interface: data 4

time between 2 subsequent reads longer than

time to get next ADC/SSC result update ó

most recent data lost

Figure 19. Measurement Result Output Update in Cyclic Operation (with “Slow” Interface Polling)

6.5.3.

Analog Outputs: Digital-to-Analog Converter (DAC)

The integrated, programmable digital-to-analog converter (DAC) generates an IC-internal analog signal that can

be output at AOUT as an absolute voltage, V_DD-ratiometric voltage, or control signal for an externally connected

current loop circuit. The analog output must be configured by Aout_setup in the SSF2 register, 04_HEX

13-16 bit

Alternative input by

DAC-Diagnostic, B3_HEX

Aout_setup

ADC Raw Results

bit[0]

bit[8]

bit[15]

AOUT

DAC-Input Register

Digitial Control and

Math Core

...

Truncated

T or S

SSC-Result Register

bit[23]

bit[0]

Figure 20. DAC and Analog Output Topology

The ZSSC3240 provides only analog outputs for signals that have been processed by the SSC calculation unit

(see section 6.6.3), or that are directly transferred (via the digital command, DAC-Diagnostic, B3_HEX; see Table

33) as input to the DAC; e.g., for test or calibration purposes. The setup parameter dacouttype, bit[3] of the

SSF2 register, 04_HEXdefines if either the SSC-corrected sensor value, S, or the SSC-corrected temperature

value, T, is provided at AOUT; see Figure 20.

Table 28. DAC Configurations

dacres

Applied DAC Resolution

Maximum DAC Output Voltage t_DACsettleSettling Time ^[a]

bit[1]

bit[0]

13-Bit

14-Bit

15-Bit

16-Bit

150µs

160µs

180µs

200µs

[a] t_DACsettleis the step-response time for the DAC and analog output stage (only); i.e., the time to reach 99% of the new analog output

level after a DAC input change. For analog-output smart-sensor step-response time, the time for generating a new SSC-result as

input to the DAC must also be considered.

For the suppression of spuriously emitted tones in the analog output signal, dithering within the DAC operation

can be enabled/disabled via the dither_off bit in the SSF2 register. If spurious tone emission is irrelevant in the

application, dithering can be switched off in order to improve the analog output signal’s noise level.

For analog diagnostic level signalization, enabled by the diagouten bit = 1_BINin the SSF2 register (see Table 16),

the ZSSC3240 directly ties the analog output signal to 0% or 100% with the selected output stage, supported by

digital pre-scaling to reserve approximately 1.5%-wide signal bands for diagnostic outputs. Strong

recommendation: If the ZSSC3240 provides diagnostic levels, activate analog signalization of diagnostic levels

before sensor calibration.

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6.5.3.1. Voltage Outputs

The ZSSC3240 can provide one of three direct voltage outputs at the AOUT pin. The Aout_setup bit field in the

SSF2 register (bits [7:5]; see Table 34) is used to configure the ZSSC3240 and select the analog voltage output

stage as defined in Table 29. It is also possible to set up the analog voltage output for 0V to 10V systems using

additional external components.

Table 29. Direct Voltage Outputs

Aout_setup

Voltage Output (Range/Type) ^[a]

Comments

bit[2]

bit[1]

bit[0]

–

Current loop; see section 6.5.3.3

Typical 0 to 5V; with V_DD> 5V, rail-to-rail output

Any (valid) V_DD

0 to V_DD, ratiometric

0 to 1V, absolute

0 to 5V, absolute

–

Requires V_DD> 5.01V

Not assigned

0 to V_DD, ratiometric

Typical 0 to 5V; with V_DD> 5V, rail-to-rail output,

OWI2_inenabled as OWI input pin

0 to 1V, absolute

0 to 5V, absolute

Any (valid) V_DD,OWI2_inenabled as OWI input

Requires V_DD> 5.01V, OWI2_inenabled as OWI

input

[a] The voltage outputs listed are directly supported, requiring minimal (for ratiometric output) or no (for absolute voltage output)

additional external devices.

Table 30. Recommended Operating Conditions for Voltage Output

Symbol

R_Lout

Parameter

Typical Value

Unit

kΩ

Comments

External, resistive load at AOUT

External, capacitive load at AOUT

For 1kHz to 5kHz output bandwidth, as RC low-

pass filter configuration.

C_Lout

6.5.3.2. Accuracy and Calibration of the DAC-Output

The 16-bit-DAC of ZSSC3240 is optimized from design prospective for high stability. Low drift over operational

conditions can be achieved with minimal additional effort during the calibration phase, by compensating absolute

errors/mismatches with mathematical adaptation of sensor calibration coefficients.

The functional, analog main-components of the ZSSC3240’s DAC come with some residual level of IC-to-IC

variation for DAC-characteristic’s offset and gain. It is recommended to calibrate the DAC-characteristic and

consider the linearity IC-to-IC-variation of the DAC at the IC’s calibration, especially for applications with high

requirements for absolute accuracy of the output voltage. For analog output configurations, the SSC coefficients

can be derived such that the digital SSC-results and hence the DAC’s digital input (S or T) is pre-shaped in order

to compensate the residual DAC’s (non-)linearity variation.

To avoid taking analog measurement values during the smart sensors’ calibration procedure, the ZSSC3240

provides two high-precision DAC-calibration point measurement results in the NVM, DAC10RM5V and

DAC90RM5V in the NVM registers 22_HEXand 23_HEX, see Table 34. Using these two high-precision DAC

calibration points for the determination of the SSC-coefficients, the ZSSC3240 achieves a low residual, absolute

DAC-output error of less than ±0.15% over the device specified temperature range, and over the DAC output

swinging from 1% to 100% of the specified range . This approach can be also interpreted as mapping of the

digital SSC-outputs (S or T) to an IC-to-IC-varying best fit straight line characteristic of the DAC. The residual

DAC-error is typically higher in the signal range 0% to 1%, as the ZSSC3240’s does not provide exactly 0V for

zero-value digital DAC-inputs, S or T.

If more than two DAC-calibration points is considered, absolute accuracies below ±0.15% become possible,

down to the analog output (AOUT) line’s noise-and-distortion level.

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6.5.3.3. Current Loop Output

The analog current loop is a typical output signal configuration, especially for industrial sensors. Using only two

wires, the sensor is supplied with power and transmits its output signal to the processing unit. With

Aout_setup = 000_BIN(bits [7:5] in the SSF2 register; see Table 34), the ZSSC3240 will generate a SSC-corrected

sensor-signal-proportional control signal at AOUT that allows generating a related loop current according the

application in Figure 21.

Table 31. ZSSC3240 Current-Loop-Specific Properties

Symbol

Parameter

Typical Value

Unit

Comments

Combined with external R_SENS, defines the

current-loop gain: R₁/R_SENS

Control feedback resistor,

internal

R₁

120

kΩ

R₁-process-variation in the range of ±20%

Using a low-TC resistor is recommended to

minimize spurious temperature influence

R_SENS

β _TLOOP

BW_L

External loop-sensing resistor

100

Ω

Current gain of external-loop

bipolar transistor, T_LOOP

Numeric

kHz

Transfer bandwidth of internal

current loop op amp.

With a ratiometric supply and resistances that

are too low, the overall current consumption

(I_Sensor+ I_IC) at V_DDcould exceed the 4mA low-

limit for typical current loops (see Table 3 for

I_Sensorspecifications, and see Table 4 for I_IC

specifications)

External sensor element’s

minimum resistance

R_SENSOR,MIN

1.6

kΩ

Loop-response current for

logical-1; OWI over current-loop

Effective current modulation when ZSSC3240 is

OWI slave modulating the slave-to-master

response via the loop current (controlled by

AOUT/OWI1)

I_Loop,high

I_Loop,low

14…18

4…6

Loop-response current for

logical-0; OWI over current-loop

Strong recommendation: Use the Zener diode between FB and VDD to protect the V_DDline from positive over-

voltage conditions and protect the FB input from negative over-voltages. The 100nF capacitor performs a low-

pass-filter function for short/fast changes in the total current consumption for the sensor element plus the

ZSSC3240 (I_SENS+ I_IC), such that current consumption changes do not lead to short-term fluctuations of AOUT

and the loop current.

An equivalent effect of slight loop current fluctuations might be observable if a sensor-connection check is

sometimes executed between the normal sensor measurements. Here, the connected sensor element, e.g., a

resistive bridge, will be unsupplied briefly in order to determine the electrical connection properties; whereas an

overall load change (sensor measurements  sensor-connection check  sensor-measurement) at V_DDand

hence in the current loop will be present. Therefore, diagnostic features should be carefully enabled and

selected for current loop applications that have strong requirements for output signal quality under any

circumstances.

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I_SENSOR+ I_IC< 4mA !

VDD (V_DD~5V)

JFET

Loop+

7 to 48V

LDO Control /

Regulation

LDOctrl

detect

I_loop

13-16 bit

100n

I_DAC

T_loop

V_loop

AOUT

VSS

I_SENSOR+ I_IC

Rsens

I_Loop

Loop-

4..20mA

Figure 21. Current Loop Configuration

Output Interrupt Signaling

6.5.4.

The EOC pin can be programmed to operate either as a simple “measurement busy” and end-of-conversion

transducer or as a configurable interrupt transducer, which is configured using the INT_setup[1:0] bits in NVM

TRSH2 (Interrupt Level Setup registers 18_HEX, 19_HEXand 1A_HEXin NVM; see Table 34). Depending on the

INT_setup selection, the EOC pin provides a logic 1 or logic 0 (also dependent on the respective interface setup;

e.g., SPI with either logic 0 = V_DDor logic 0 = V_SS, etc.) according to the SSC-corrected measurement result. The

respective thresholds must be programmed left-aligned in the memory with the threshold’s MSB in the memory

the ADC resolution as selected with adc_bits (see Table 10).

With INT_setup = 00_BIN, only the effective end-of-conversion is signalized. The EOC signal is a pulse of

approximately 5µs (see Figure 22). The next command will be executed only after this EOC signaling period.

ZSSC3240 internal activity

configured ADC-

measurements: SM,

TM, AZS, AZT

configured ADC-

measurements: SM,

TM, AZS, AZT

configured ADC-

measurements: SM,

TM, AZS, AZT

SSC-Measurement Result

Time

EOC

5µs

Time

Note: timing relations are not to scale, they are qualitative illustrations only

Figure 22. EOC-Behavior: Signalization of End-of-Conversion (INT_setup = 00_BIN

)

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Datasheet

The interrupt functionality is only available for digital values from the SSC-calculation unit. The interrupt feature

cannot monitor raw values. The encoding and data format of the interrupt thresholds is the same as for SSC-

corrected measurement results (see Table 32).

Table 32. Data Format of Interrupt Thresholds (TRSH1 and TRSH2)

Bit-Number

…

Meaning,

Weighting

2⁰

2^-1

2^-2

2^-3

…

2^-21

2^-22

2^-23

INT_setup = 01_BIN

INT_setup = 10_BIN

Measurement

Result

Measurement

Result

max.

threshold 1

Time

EOC

Time

INT_setup = 11_BIN

Case A:

threshold1 > threshold2

Case B:

threshold1 < threshold2

Measurement

Result

Measurement

Result

max.

threshold 1

threshold 2

threshold 1

Time

EOC

Figure 23. EOC and Interrupt Thresholds

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6.6

System Setup and Control

The digital blocks of the ZSSC3240 are organized functionally as shown in Figure 24. In addition to the central

blocks, which are the “Interfaces,” “Digital Main Core,” and “Memory (NVM)” blocks, there is also the Shadow

Registers block, which in most cases, is a direct copy of the NVM registers. The shadow registers are loaded

from NVM during the power-up sequence and allow acceleration of command processing and NVM-independent

configuration adaptability; e.g., during adaptive sensor setup, evaluation, or smart sensor test. For the main

function of the ZSSC3240 to conduct a sensor measurement and ADC-conversion, the setups (for main Sensor

or Temperature) are loaded or activated from the corresponding Shadow Registers in order to set all IC-internal

configuration switches for sensor supply, PGA gain, offset compensation, reference voltage sources, etc. After a

settling time for the analog signals and levels, the A2D conversion takes place. This course of activities is

(re-)done for each individual measurement, i.e. once for SM, AZS, TM, AZT, with setups for SM and AZS

according the Shadow Registers for SM_config1 and SM_config2, and for TM, AZT from registers

extTemp_config1 and extTemp_config2. If the internal temperature sensor was selected as signal source for TM,

AZT, the setups are loaded from a Renesas-preprogrammed register different to extTemp_config1 and

extTemp_config2.

Analog Front-End

Analog Output

. Internal Temp. Sensor

. PGA

. DAC

. AOUT driver stages

ADC

inMUX

MUXout

Shadow Registers

Interfaces

Select

Digital Main Core

(De)activate

OWI

IC Control

Command Interpreter

SSC Math

Overwrite

Shadow

Digital Request,

Response

...

Read

SPI

I2C

Load Shadow from NVM

Memory (NVM)

Read/Write NVM

...

Dashed line indicates control line

...

Green line indicates data transfer line

Figure 24. Digital IC Section Architecture

6.6.1.

Digital Commands

The availability of commands depends on the active main operating mode: Command, Sleep, or Cyclic Mode.

Table 33. Command List

Note: See important table notes as the end of this table.

Command Code

(Byte)

Available in

Sleep Mode Command Mode Cyclic Mode

Available in

Return

Description

00_HEXto 3F _HEX

16-bit data

Memory Read address 00_HEXto 3F_HEX

Yes

40_HEXto 75_HEX

followed by data

(0000_HEXto

Memory Write addresses 00_HEXto 35_HEX(NVM

NVM is locked, write requests are not acknow-

ledged or are ignored

–

FFFF_HEX

)

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Command Code

(Byte)

Available in

Sleep Mode Command Mode Cyclic Mode

Available in

Return

Description

Calculate NVM Checksum and write it to the

memory

90_HEX

–

Yes

Raw Sensor Measurement^[a]– Configuration is

loaded in the controlling shadow registers from

the SM_config1 and SM_config2 registers in

NVM

A2_HEX

24-bit raw data

Yes

Note: auto-zero sensor measurement is

performed if set up in the AZMs_on bit in the

SSF2 register

Raw Temperature Measurement^[a]

–

Configuration is loaded in the controlling shadow

registers from the extTemp_Config1/2 or

T_config1/2 registers in NVM as well as the

SSF1/2 registers

Note: Auto-zero correction will be performed if

set up via the AZMt_on bit in the SSF2 register

Note: If a raw data measurement with an external

setup (different from the NVM content) will be

performed, then pre-load the measurement

configuration via the Overwrite SSF1/2 Register

and Overwrite T_config1/2 Shadow Register

commands.

A4_HEX

24-bit raw data

Yes

Note: The internal or external temperature

measurement will be performed if set up via the

temp_source bit field in the SSF1 register

START_SLEEP – Exit Command Mode or Cyclic

Mode and transition to Sleep Mode

Note: The response to Start_Sleep is only the

status byte

A8_HEX

A9_HEX

–

Yes

START_CM – Exit Sleep Mode or Cyclic Mode

and transition to Command Mode

Yes

24-bit SSC-

corrected

Measure – Trigger a full measurement (auto-

zero-sensor, sensor, auto-zero-temperature,

sensor data and temperature) and perform SSC correction

AA_HEX

AB_HEX

AC_HEX

24-bit SSC-

corrected

temperature

data

Yes

Note: Auto-zero correction is performed with this

command if set up in the AZMs_on and AZMt_on

bits in the SSF2 register

START_CYC – Enter the Cyclic Mode:

continuous measurement cycles, SSC

corrections, and automatic, continuous digital

and/or analog output updates

Oversample-2 Measure ^[b]– Mean value

generation; 2 full measurements (triggered

similar to AA_HEX, not cyclic) are performed and

the resulting mean value is provided as output

Note: Auto-zero correction is performed with this

command if set up in the AZMs_on and AZMt_on

bits in the SSF2 register

–

Oversample-4 Measure ^[b]– Mean value

generation; 4 full measurements (triggered

similar to AA_HEX, not cyclic) are performed and

the resulting mean value is provided as output

Note: Auto-zero correction is performed with this

command if set up in the AZMs_on and AZMt_on

bits in the SSF2 register

Oversample-8 Measure ^[b]– Mean value

generation; 8 full measurements (triggered

similar to AA_HEX, not cyclic) are performed and

the resulting mean value is provided as output

Note: Auto-zero correction is performed with this

command if set up in the AZMs_on and AZMt_on

bits in the SSF2 register

24-bit SSC-

corrected

sensor data and

24-bit SSC-

corrected

AD_HEX

Yes

temperature

data

AE_HEX

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Command Code

(Byte)

Available in

Sleep Mode Command Mode Cyclic Mode

Available in

Return

Description

Oversample-16 Measure ^[b]– Mean value

generation; 16 full measurements (triggered

similar to AA_HEX, not cyclic) are performed and

the resulting mean value is provided as output

Note: Auto-zero correction is performed with this

command if set up in the AZMs_on and AZMt_on

bits in the SSF2 register

AF_HEX

Yes

16-bit

diagnostic

result data

CHECK_DIAG – The ZSSC3240 responds with

the detailed fault-result status in the

diagnosticreg register

B0_HEX

B1_HEX

Yes

RESET_DIAG – Resets the contents of

diagnosticreg to 00_HEX

–

Update_DIAG – Causes a complete diagnostics

check cycle including memory CRC calculation,

etc., and results in a reset and update of

diagnosticreg

B2_HEX

–

Yes

Note: If a measurement cycle is running concur-

rently, the diagnostic update happens after

completion of the measurement cycle and SSC

calculations (and might delay the next cyclic

measurement cycle)

DAC Diagnostic – Set the DAC output register

with the data in the command and enable/output

the respective analog signal through AOUT

(according to the AOUT_setup)

B3_HEXfollowed by

data (0000_HEXto

–

Yes

FFFF_HEX

)

Note: The DAC output can be switched off by the

RESQ pin, POR, or a change in the main

operating mode

Self-Diagnostic Measure – The ADC performs a

raw measurement with the setup from the

SM_config registers, and the PGA input is

disconnected from the external sensor and

internally shorted (INN = INP = AGND). The

ZSSC3240-internal setup, which is configured

according to the ioffsc bit field in the SM_config2

the command). The respective pseudo-offset

signal becomes the input test signal to the PGA-

ADC-path.

B4_HEXfollowed by

00XX_HEX

24-bit raw data

Yes

The original ioffsc and SM_config2 contents are

restored after the self-diagnostic measurement

completion.

Note: alternatively, also a changed setup (PGA,

ADC) could be used by applying Overwrite

commands prior to the self-diagnostic

measurement.

Set Post-Calibration Offset – Set recent SSC-

output to expected value XXXX_HEXin command

by means of offset adjustment with coefficient

SENS_shift

D1_HEXfollowed by

XXXX_HEX

–

Yes

Startup OWI – Initialization command to enter

OWI interface operation; only valid for OWI (see

section 6.4.3)

D2_HEX

Overwrite SM_config1 shadow register –

Content (originally from NVM register 14_HEX) in

the digital shadow register for SM_config1 is

directly overwritten with the command data ^[c]

D6_HEXfollowed by

data (0000_HEXto

FFFF_HEX

)

Overwrite SM_config2 shadow register –

Content (originally from NVM register 15_HEX) in

the digital shadow register for SM_config2 is

directly overwritten with the command data ^[c]

D7_HEXfollowed by

data (0000_HEXto

–

Yes

FFFF_HEX

)

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Command Code

(Byte)

Available in

Sleep Mode Command Mode Cyclic Mode

Available in

Return

Description

Overwrite T_config1 shadow register –

Content (originally from NVM register 16_HEXor

3C_HEX) in the digital shadow register for the

temperature measurement is directly overwritten

with the command data ^[c]

D8_HEXfollowed by

data (0000_HEXto

–

Yes

FFFF_HEX

)

Overwrite T_config2 shadow register –

Content (originally from NVM register 17_HEXor

3D_HEX) in the digital shadow register for the

temperature measurement is directly overwritten

with the command data ^[c]

D9_HEXfollowed by

data (0000_HEXto

–

FFFF_HEX

)

Overwrite SSF1 shadow register – Content

(originally from NVM register 03_HEX) n the digital

shadow register for SSF1 is directly overwritten

with the command data ^[c]

Note: transferred bits[1:0] and bits[15:13] are

ignored; i.e., are not overwritten in the shadow

DA_HEXfollowed

by data (0000_HEX

Yes

to FFFF_HEX

)

Overwrite SSF2 shadow register – Content

(originally from NVM register 04_HEX) the digital

shadow register for SSF2 is directly overwritten

with the command data ^[c]

DB_HEXfollowed

by data (0000_HEX

Yes

to FFFF_HEX

)

Status followed NOP – Output of read results; only valid for SPI

FX_HEX

by last 24-bit

data

(see section 6.4.1)

Yes

[a] These commands can be used to conduct a measurement without an SSC correction; e.g., during the smart sensor calibration

procedure. No digital correction is performed on the measurement result. The setup and configuration for the raw measurement is

the content in the shadow registers that can be pre-loaded (automatically loaded during power-on) from the NVM or by means of

the Overwrite commands, D6_HEXto DB_HEX

[b] Use Oversample measurements to obtain noise-minimized measurement results in Sleep or Command Mode. With higher

oversampling factors, the command execution time increases proportionally.

[c] Overwrite commands can be used to optimize evaluation and test routine execution time for analog front-end setup or to configure

self-diagnostic measurement setups without needing to change the ZSSC3240’s NVM content. The content and effects from

Overwrite commands are cleared and reset with the ZSSC3240 reset via the RESQ pin or POR.

6.6.2.

Nonvolatile Memory (NVM)

In the ZSSC3240, the memory is organized in 16-bit wide registers and can be programmed multiple times

(approximately 10000). There are 54  16-bit registers available for customer use. Each register can be re-

programmed.

Basically, there are two NVM content sectors:

 Customer Use: Accessible via regular write operations: 40_HEXto 75_HEX. This sector contains the customer ID,

interface setup data, measurement setup information, calibration coefficients, analog output configuration, etc.

 Renesas Use: Only accessible for write operations by Renesas. This sector (36_HEXto 3F_HEX) contains

specific trim information and is programmed during manufacturing test by Renesas, e.g. setups for the internal

temperature sensor are stored there.

The whole NVM can be locked by programming lock = 1_BINin the SSF1 register, NVM address 03_HEX, bit[14]. No

change of the NVM content is possible once the NVM lock has been activated.

Recommendations when using the NVM lock:

 Write all required setups, configurations, and SSC coefficients to the NVM first.

 Then write the SSF1 register content with the lock bit set.

 Then trigger the generation and writing of the CRC via the Calculate NVM Checksum command, 90_HEX

The NVM lock will be effective after a ZSSC3240 reset with POR or RESQ.

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6.6.2.1. Memory Contents

Table 34. Memory (NVM) Content Assignments

NVM Address

Word/Bit Range Default Setting

Description

Notes/Explanations

Customer ID byte 0 (combines with memory word 01_HEXto

form customer ID)^[a]

00_HEX

15:0

0000_HEX

Cust_ID0

Customer ID byte 1 (combines with memory word 00_HEXto

form customer ID).

01_HEX

Cust_ID1

Interface Configuration

I2C and OWI slave address; valid range: 00_HEXto 7F_HEX

(default: 00_HEX).

6:0

000 0000_BIN

Slave_Addr

Note: address codes 04_HEXto 07_HEXare reserved for entering

the I2C High Speed Mode.

Interrupt configuration, EOC pin functionality:

00 = End-of-conversion signal

01 = 0 to 1 transition if threshold1 (TRSH1) is exceeded

and 1 to 0 transition if threshold1 is underrun again

10 = 0 to 1 transition if threshold1 is underrun and 1 to 0

transition if threshold1 is exceeded again

11 = EOC is determined by threshold settings (see section

6.5.4):

8:7

00_BIN

INT_setup

 If (TRSH1 > TRSH2) then EOC/INT (interrupt

level) = 0 if (TRSH1 > MEAS ≥ TRSH2) where

MEAS is the conditioned measurement result.

Otherwise EOC/INT = 1.

 If (TRSH1 ≤ TRSH2) then EOC = 1 if (TRSH1 ≤

MEAS < TRSH2). Otherwise EOC = 0.

Determines the polarity of the Slave Select pin (SS) for SPI

operation:

0 = Slave Select is active low (SPI and ZSSC3240 are

active if SS==0)

0_BIN

SS_polarity

1 = Slave Select is active high (SPI and ZSSC3240 are

active if SS==1)

02_HEX

Clock polarity and clock-edge select. CKP_CKE determines

polarity and phase of SPI interface clock with the following

modes:

00 = SCLK is low in idle state; data latch with rising edge

and data output with falling edge

01 = SCLK is low in idle state; data latch with falling

edge and data output with rising edge

11:10

00_BIN

CKP_CKE

10 = SCLK is high in idle state; data latch with falling

edge and data output with rising edge

11 = SCLK is high in idle state; data latch with rising

edge and data output with falling edge

Update period in cyclic operation:

000 = 0.0ms

001 = 0.1ms

010 = 1.0ms

011 = 2.5ms

100 = 5.0ms

101 = 10ms

110 = 50ms

111 = 87.5ms

14:12

000_BIN

CYC_period

SOT_curve

Note: A slower measurement rate, i.e., a higher CYC_period,

can improve the analog output signal quality due to lower

system bandwidth.

Type/shape of second-order curve correction for the sensor

signal:

0_BIN

0 = Parabolic curve

1 = S-shaped curve

Smart Sensor Feature Configuration Register 1 (SSF1)

Defines the default operating mode that is automatically

entered after power-on:

00 = Command Mode

01 = Cyclic Mode

03_HEX

1:0

00_BIN

default_mode

10 = Sleep Mode

11 = Not assigned

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NVM Address

Word/Bit Range Default Setting

Description

Notes/Explanations

Defines the length of the OWI startup window, during which

the OWI interface can be activated if analog output through

the AOUT pin is also set up via cont_ANAoutn = 0_BIN(see

0_BIN

owi_su_length

OWI_ListenTime:

0 = 50ms

1 = 3ms

Defines the activation level for the analog output at AOUT

with or without concurrent OWI1 I/O behavior (see section

6.4.3 for OWI application cases):

0_BIN

owi_su_case

0 = Regular, separate Startup Window for OWI first, then

switch over to AOUT behavior

1 = Direct start with output of analog signal at AOUT

Selection of utilized temperature sensor source:

000 = Integrated PTAT temperature sensor (no extra

setup required)

001 = Bridge as temperature sensor with internal Rt in

Current Mode^[b]

010 = Current Mode through T_EXT^[b]for one of the

following:

 Bridge as the temperature sensor with external

Rt at T_EXT

 Single diode/resistor at T_EXT

6:4

000_BIN

temp_source

011 = Not assigned

100 = Current Mode operation for diode or PTC between

T_EXTand VSSB ^[b]

101 = Ratiometric supply for the sensor (bridge) as the

temperature sensor with the internal Rt ^[b]

110 = Ratiometric supply for sensor (bridge) as the

temperature sensor with the external Rt between

sensor (bridge) top and T_EXTpin^[b]

111 = Not assigned

Front-end operation and supply setup for main measurand

sensor measurements:

00 = Ratiometric supply at VDDB

01 = Current Mode out of VDDB from Tbias

(see section 6.2)

8:7

00_BIN

sensor_sup

10 = Absolute voltage (Thermopile)

11 = Not assigned

Note: if temp_source = 100 (temperature application T3.2) is

also set up, sensor_sup = 01 must be configured in order to

get ratiometric main sensor supply at VDDB.

Top resistance set up for “Bridge as temperature sensor”

configuration (see Table 15).

Selection of resistance value (internal Rt) for re-using the

sensor (bridge) as the temperature sensor with internal Rt

(temp_source = 001 or 101).

Selected Rt value is as follows:

11:9

000_BIN

internal_rt

000 = 1.34kΩ

001 = 4kΩ

010 = 8kΩ

011 = 10kΩ

100 = 15kΩ

101 = 20kΩ

110 = 30kΩ

111 = 40kΩ

Note: the same value is selected for the bottom Rt’, if

extra_rt = 1_BINis selected

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NVM Address

Word/Bit Range Default Setting

Description

Notes/Explanations

Bottom resistance set up for the “Bridge as temperature

sensor” configuration.

If temp_source = 110 or 010 (or 100 combined with

sensor_sup = 01), then extra_rt defines whether an internal

bottom resistor Rt’ equivalent to the internal_rt selection is

placed between VSSB and PGA negative input:

0 =Use internal Rt’ (no extra external Rt’)

0_BIN

extra_rt

1 =Extra external Rt’ (do not apply internal Rt’)

Note: with temp_source = 100 AND sensor_sup = 10, the

meaning of extra_rt bit is swapped (that is extra_rt = 0

means internal Rt’ is not enabled)

Setup bit to disable OWI interface:

0 =OWI is enabled and usable

0_BIN

owi_off

lock

1 = OWI is disabled and cannot be used

Note: This setting has no effect on SPI or I2C operation

Lock bit: no further NVM writing is possible if this bit is set.

0 =NVM write allowed

0_BIN

1 = NVM locked

Note: Once this bit is set to 1, the lock becomes effective

after the next IC reset.

Switch off the charge pump for the internal regulators:

0 = Charge pump on (recommended setting for better

PSRR, or when external VDD<4.3V)

1 = Charge pump off (less current consumption and

lower distortion risks, e.g. coupling to VSS); this

might be needed to ensure the 4mA low-limit in

current loop applications (default setting for pre-

configured Current-Loop application products, for

example, ZSSC3240CL1B and ZSSC3240CL3R)

0_BIN

cp_off

Note: Switch off the charge pump only if V_DD> 4.3V is

ensured

Smart Sensor Feature Configuration Register 2 (SSF2):

Setup of DAC output resolution:

00 = 13-bit

01 = 14-bit

1:0

00_BIN

dacres

10 = 15-bit

11 = 16-bit

Switch on/off the dithering function for the DAC:

1_BIN

dither_off

0 =

1 =

Dither is applied for DAC outputs

Dither is switched off

Defines if the SSC-corrected sensor(bridge) signal S or the

temperature signal T is the output at the DAC:

0 =Sensor signal S is output at the DAC

0_BIN

dacouttype

04_HEX

1 =Temperature signal T is output at DAC

Selects whether the ZSSC3240 provides analog output in

general:

0 = Analog (DAC) output is enabled

0_BIN

cont_ANAoutn

1 = No analog output (cyclic operation with digital

outputs is still possible)

Note: If cont_ANAoutn is set to 1, then Aout_setup is ignored;

there is no analog output in Sleep Mode in general

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NVM Address

Word/Bit Range Default Setting

Description

Notes/Explanations

Definition of the basic AOUT pin behavior:

000 = Current loop enabled, output through error

amplifier for current loop^[c], OWI listens to both

the OWI2_inand OWI1 pins concurrently

(default setting for pre-configured Current-Loop

application products, for example,

ZSSC3240CL1B and ZSSC3240CL3R )

001 = External V_DD-ratiometric, rail-to-rail out

010 = 0V to 1.0V absolute output

011 = 0V to 5V absolute output

100 = not assigned

7:5

001_BIN

Aout_setup

101 = External V_DD-ratiometric, rail-to-rail out (OWI2_in

enabled)

110 = 0V to 1.0V absolute output (OWI2_inenabled)

111 = 0V to 5V absolute output (OWI2_inenabled)

Enable diagnostic level output mode: The lower and upper

analog output range levels are reserved for diagnostic

signaling according to Table 16. The ZSSC3240 performs an

automatic DAC-output scaling (if already digitally calibrated)

to reserve the lower and upper 1.56% band or absolute

voltage levels:

0_BIN

diagouten

0 =

1 =

No analog signalization

Analog diagnostic signaling is enabled

Switch off the internal output regulator circuit running the

LDOctrl pin if no external supply transistor (such as JFET) is

used; this reduces current consumption, etc.

0 =

1 =

LDOctrl output is switched/kept on

LDOctrl output switched off

0_BIN

disable_ldoctrl

Note: If enabled (= 0), then the charge-pump can be off (the

cp_off bit = 1 in register 03_HEX

)

Set point for regulated V_DDusing external supply transistor

JFET or depletion MOSFET:

00 = V_DD= 4.8V

VDD_ldoctrl

_target

11:10

10_BIN

01 = V_DD= 5.0V

10 = V_DD= 5.2V

11 = V_DD= 5.4V

Enable/disable for auto-zero measurement for (bridge)

sensor measurement:

0 = No auto-zero measurements for sensor signal

0_BIN

AZMs_on

AZMt_on

1 = Auto-zero measurement of sensor bridge is

performed and processed

Note: This setup is ignored for raw data measurements with

setup via the interface, i.e. command A2_HEX

Enable/disable for auto-zero measurement for temperature

measurement:

0 = No auto-zero measurements for temperature signal

0_BIN

1 = Auto-zero measurement for temperature signal

performed and processed

Selection for applied digital oversampling in Cyclic Mode

operation:

00 = No oversampling

01 = Oversample-4: Results of 4 SSC cycles per last

meas_scheduler sequence

15:14

00_BIN

oversamp_cyc

10 = Oversample-8: Results of 8 SSC cycles per last

meas_scheduler sequence

11 = Oversample-16: Results of 16 SSC cycles per last

meas_scheduler sequence

Note: This setup is ignored for any measurement in

Command and Sleep Mode

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NVM Address

Word/Bit Range Default Setting

Description

Notes/Explanations

Signal Conditioning Parameters

Bits [15:0] of the 24-bit-wide sensor offset correction

05_HEX

06_HEX

15:0

0000_HEX

Offset_S[15:0] coefficient Offset_S. The MSBs including sign are

Offset_S[23:16], which is [15:8] in register 0F_HEX

Bits [15:0] of the 24-bit-wide value of the sensor gain

Gain_S[15:0]

Tcg[15:0]

coefficient Gain_S. The MSBs including sign are

Gain_S[23:16], which is [7:0] in register 0F_HEX

Bits [15:0] of the 24-bit-wide coefficient Tcg for the

temperature correction of the sensor gain. The MSBs

including sign are Tcg[23:16], which is bits [15:8] in

07_HEX

15:0

0000_HEX

Bits [15:0] of the 24-bit-wide coefficient Tco for temperature

08_HEX

09_HEX

0A_HEX

15:0

0000_HEX

Tco[15:0]

correction of the sensor offset. The MSBs with sign are

Tco[23:16], which is bits [7:0] in register 10_HEX

Bits [15:0] of the 24-bit-wide 2^ndorder term SOT_tco applied

SOT_tco[15:0] to Tco. The MSBs of this term including sign are

SOT_tco[23:16], which is bits [15:8] in register 11_HEX

Bits [15:0] of the 24-bit-wide 2^ndorder term SOT_tcg applied

SOT_tcg[15:0] to Tcg. The MSBs of this term including sign are

SOT_tcg[23:16], which is bits[7:0] in register 11_HEX

Bits [15:0] of the 24-bit-wide 2^ndorder term SOT_sens

applied to the sensor readout. The MSBs of this term

including sign are SOT_sens[23:16], which is bits[15:8] in

0B_HEX

15:0

0000_HEX

SOT_sens[15:0]

Bits [15:0] of the 24-bit-wide temperature offset correction

Offset_T[15:0] coefficient Offset_T. The MSBs of this coefficient including

0C_HEX

0D_HEX

0E_HEX

15:0

7:0

0000_HEX

20_HEX

sign are Offset_T[23:16], which is bits[7:0] in register 12_HEX

Bits [15:0] of the 24-bit-wide absolute value of the

Gain_T[15:0]

SOT_T[15:0]

temperature gain coefficient Gain_T. The MSBs including

sign are Gain_T[23:16], which is bits[15:8] in register 13_HEX

Bits [15:0] of the 24-bit-wide 2^nd-order term SOT_T applied to

the temperature reading. The MSBs including sign are

SOT_T[23:16], which is bit[7:0] in register 13_HEX

Bits [23:16] including sign for the 24-bit-wide sensor gain

Gain_S[23:16] correction coefficient Gain_S. The LSBs of this coefficient are

Gain_S[15:0] in register 06_HEX

0F_HEX

10_HEX

11_HEX

12_HEX

13_HEX

Bits [23:16] including sign for the 24-bit-wide sensor offset

Offset_S[23:16] correction coefficient Offset_S. The LSBs are Offset_S[15:0]

15:8

7:0

00_HEX

in register 05_HEX

Bits [23:16] including sign for the 24-bit-wide coefficient Tco

for temperature correction for the sensor offset. The LSBs are

00_HEX

Tco[23:16]

Tcg[23:16]

Tco[15:0] in register 08_HEX

Bits [23:16] including sign for the 24-bit-wide coefficient Tcg

for the temperature correction of the sensor gain. The LSBs

15:8

7:0

00_HEX

are Tcg[15:0] in register 07_HEX

Bits [23:16] including sign for the 24-bit-wide 2^ndorder term

SOT_tcg[23:16] SOT_tcg applied to Tcg. The LSBs are SOT_tcg[15:0] in

00_HEX

Bits [23:16] including sign for the 24-bit-wide 2^ndorder term

15:8

7:0

00_HEX

SOT_tco[23:16] SOT_tco applied to Tco. The LSBs are SOT_tco[15:0] in

Bits [23:16] including sign for the 24-bit-wide temperature

Offset_T[23:16] offset correction coefficient Offset_T. The LSBs are

00_HEX

Offset_T[15:0] in register 0C_HEX

Bits [23:16] including sign for the 24-bit-wide 2^ndorder term

15:8

7:0

00_HEX

SOT_sens[23:16] SOT_sens applied to the sensor readout. The LSBs are

SOT_sens[15:0] in register 0B_HEX

Bits [23:16] including sign for the 24-bit-wide 2^nd-order term

00_HEX

SOT_T[23:16]

SOT_T applied to the temperature reading. The LSBs are

SOT_T[15:0] in register 0E_HEX

Bits [23:16] including sign for the 24-bit-wide absolute value

Gain_T[23:16] of the temperature gain coefficient Gain_T. The LSBs are

Gain_T[15:0] in register 0D_HEX

15:8

20_HEX

Nov.27.20

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Datasheet

NVM Address

Word/Bit Range Default Setting

Measurement Configuration Register 1 (SM_config1)

Gain setting for the 1^stPGA stage with Gain_stage1[3:0]:

Description

Notes/Explanations

Parameters are valid for

Gain_PGA≤ 192:

Parameters are limited for

Gain_PGA> 192:

0000 = 1.2

0001 = 2

0010 = 4

0011 = 6

0100 = 12

0101 = 20

0110 = 30 1011 = 150

0111 = 40 1100 = 200

3:0

0000_BIN

Gain_stage1

1000 = 60 1101 = 240

1001 = 80 1110 = 300

1010 = 120 1111 = Not assigned

Gain setting for the 2^ndPGA stage with Gain_stage2[1:0]:

000 = 1.1

001 = 1.2

010 = 1.3

011 = 1.4

100 = 1.5

101 = 1.6

110 = 1.7

111 = 1.8

6:4

000_BIN

Gain_stage2

Gain_polarity

Set up the polarity of the sensor bridge’s gain

(invert chopper 1):

0_BIN

0 =

1 =

positive (no polarity change)

negative (180° polarity change)

Resolution, i.e. absolute number of bits for the ADC with

adc_bits[3:0]:

14_HEX

0000 = 12

0111 = 19

0001 = 13

1000 = 20

0010 = 14

1001 = 21

11:8

0100_BIN

adc_bits

0011 = 15

1010 = 22

0100 = 16 (default)

0101 = 17

1011 = 23

1100 = 24

0110 = 18

1101 to 1111 = Not assigned

Differential signal’s offset shift in the ADC including gain x2;

compensation of x% signal offset:

000 = 0%, no offset compensation 100 = 25.00% offset

14:12

000_BIN

adc_offset

sel_ref1

001 = 6.25% offset

010 = 12.50% offset

011 = 18.75% offset

101 = 31.25% offset

110 = 37.50% offset

111 = 44.00% offset

Reference source for main sensor measurement:

0 = Absolute (internal) bandgap is the reference

0_BIN

1 = Ratiometric reference; recommended for

ratiometrically supplied sensors

Measurement Configuration Register 2 (SM_config2)

Absolute voltage input shift for input signals to the PG, e.g.

INP-INN

The input signal is shifted by the following voltages:

00000 =

00001 =

00010 =

00011 =

…

0mV, no shift

-1mV

-2mV

-3mV

15_HEX

4:0

0 0000_BIN

ioffsc

01110 =

01111 =

10000 =

10001 =

10010 =

…

-14mV

-15mV

0mV, no shift

+1mV

+2mV

11110 =

11111 =

+14mV

+15mV

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Datasheet

NVM Address

Word/Bit Range Default Setting

Description

Notes/Explanations

Current Mode sensor bias selection; nominal sensor supply

current I_sup

(if sensor_sup = 01 ):

000 =

001 =

010 =

011 =

100 =

5µA

10µA

20µA

39µA

79µA

7:5

000_BIN

Tbiasout

101 = 157µA

110 = 196µA

111 = 494µA

General disable/enable of the ADC feature to apply the extra

gain x2 and signal offset compensation adc_offset in register

14_HEX

0_BIN

adc_en_shift

0 =Gain: 2 and signal offset compensation off

1 =Gain: 2 and signal offset compensation on

Automatic common mode adjust feature, which allows

automatically, optimally adapting the sensor-input common

mode to AGND at the PGA output.^[d]

0_BIN

pga_en_shift

0 =Automatic common mode adjustment off

1 =Automatic common mode adjustment on

15:10

00 0000_BIN

–

Not assigned

External Temperature Measurement Configuration Register 1 (extTemp_config1)

Gain setting for the 1^stPGA stage with Gain_stage1[3:0] for

external temperature measurements:

Parameters are valid for Gain_PGA≤ 192:

0000 = 1.2

0001 = 2

0010 = 4

0011 = 6

0100 = 12

0101 = 20

0110 = 30

0111 = 40

1000 = 60

1001 = 80

1010 = 120

3:0

0000_BIN

Gain_stage1

Parameters are limited for Gain_PGA> 192:

1011 = 150

1100 = 200

1101 = 240

1110 = 300

1111 = Not assigned

Gain setting for the 2^ndPGA stage with Gain_stage2[1:0] for

external temperature measurements:

16_HEX

000 = 1.1

001 = 1.2

010 = 1.3

011 = 1.4

100 = 1.5

101 = 1.6

110 = 1.7

111 = 1.8

6:4

000_BIN

Gain_stage2

Gain_polarity

Set up the polarity of the temperature sensor gain (invert

input) with:

0 = Positive (no polarity change)

1 = Negative (180° polarity change)

0_BIN

Resolution, i.e. absolute number of bits for the ADC for

external temperature measurements with adc_bits[3:0]:

0000 = 12

0111 = 19

0001 = 13

1000 = 20

0010 = 14

1001 = 21

11:8

0100_BIN

adc_bits

0011 = 15

1010 = 22

0100 = 16 (default)

0101 = 17

1011 = 23

1100 = 24

0110 = 18

1101 to 1111 = Not assigned

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Datasheet

NVM Address

Word/Bit Range Default Setting

Description

Notes/Explanations

Differential signal’s offset shift in ADC including gain x2 for

external temperature measurements; compensation of x%

signal offset:

000 = 0%, no offset compensation

001 = 6.25% offset

010 = 12.50% offset

14:12

000_BIN

adc_offset

011 = 18.75% offset

100 = 25.00% offset

101 = 31.25% offset

110 = 37.50% offset

111 = 44.00% offset

Reference source for external temperature sensing and

conversion:

0 = Absolute (internal) bandgap is reference

0_BIN

sel_ref2

1 = Ratiometric reference; recommended for

ratiometrically supplied sensors

External Temperature Measurement Configuration Register 2 (extTemp_config2)

Absolute voltage input shift for input signals for external

temperature measurements to the PG, e.g. INP-INN

The input signal is shifted by the following voltages:

00000 = 0mV, no shift

00001 = -1mV

00010 = -2mV

00011 = -3mV

…

4:0

0 0000_BIN

ioffsc

01110 = -14mV

01111 = -15mV

10000 = 0mV, no shift

10001 = +1mV

10010 = +2mV

…

11110 = +14mV

11111 = +15mV

Current Mode sensor bias selection for external temperature

measurements; nominal sensor supply current

(if temp_source є {001_BIN, 010_BIN, 011 _BIN, 100 _BIN}):

17_HEX

000 = 5µA

001 = 10µA

010 = 20µA

011 = 39µA

100 = 79µA

101 = 157µA

110 = 196µA

111 = 494µA

7:5

000_BIN

Tbiasout

General disenable/enable of the ADC feature for external

temperature measurements to apply the extra gain x2 and

signal offset compensation adc_offset in register 16_HEX

0 = Gain: x2 and signal offset compensation off

1 = Gain: x2 and signal offset compensation on

0_BIN

adc_en_shift

Automatic common mode adjust feature, which allows

automatically, optimally adapting the sensor-input common

mode to AGND at the PGA output for external temperature

measurements.^[d]

0_BIN

pga_en_shift

0 = Automatic common mode adjustment off

1 = Automatic common mode adjustment on

15:10

15:0

00 0000_BIN

–

Not assigned

Interrupt Level Setup and Post-Calibration (Digital) Offset Calibration

Bits [15:0] of the 24-bit-wide interrupt threshold1, TRSH1.

18_HEX

0000_HEX

TRSH1[15:0]

(The MSBs for this threshold are TRSH1[23:16], which is bits

[7:0] of register 1A_HEX.)

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ZSSC3240

Datasheet

NVM Address

Word/Bit Range Default Setting

Description

Notes/Explanations

Bits [15:0] of the 24-bit-wide interrupt threshold2, TRSH2.

(The MSBs for this threshold are TRSH2[23:16], which is

bits[15:8] of register 1A_HEX.)

19_HEX

15:0

7:0

0000_HEX

00_HEX

TRSH2[15:0]

Bits [23:16] of the 24-bit-wide interrupt threshold1, TRSH1.

TRSH1[23:16] (The LSBs for this threshold are TRSH1[15:0], which is

bits[15:0] of register 18_HEX.)

1A_HEX

Bits [23:16] of the 24-bit-wide interrupt threshold2, TRSH2.

TRSH2[23:16] (The LSBs for this threshold are TRSH2[15:0], which is

bits[15:0] of register 19_HEX.)

15:8

15:0

7:0

00_HEX

Bits [15:0] of the post-calibration sensor offset shift coefficient

SENS_Shift[15:0] SENS_Shift.

1B_HEX

1C_HEX

0000_HEX

00_HEX

(The MSBs of SENS_Shift are bits [15:8] of register 1D_HEX.)

Bits [15:0] of the post-calibration temperature offset shift

coefficient T_Shift.

(The MSBs of T_Shift are bits [7:0] of register 1D_HEX.)

T_Shift[15:0]

Bits [23:16] of the post-calibration temperature offset shift

T_Shift[23:16] coefficient T_Shift. (The LSBs of T_Shift are in register

1C_HEX.)

1D_HEX

Bits [23:16] of the post-calibration sensor offset shift

SENS_Shift[23:16] coefficient SENS_Shift. (The LSBs of SENS_Shift are in

15:8

00_HEX

Measurement Scheduler (Cyclic Operation Sequence)

Cyclic measurement operation is performed with/including

the sensor measurement:

0 = Sensor measurement is performed

0_BIN

cycwsn

cycwtn

1 = Sensor measurement is not performed

Note: Whether AZS is to be performed in the cyclic

measurement sequence is set up with AZMs_on (see register

04_HEX

)

Cyclic measurement operation is performed with the

temperature measurement:

0 = Temperature measurement is performed

1 = Temperature measurement is not performed

Note: whether AZT is to be performed in the cyclic

measurement sequence is set up with AZMt_on (see register

1E_HEX

0_BIN

04_HEX

)

0_BIN

Not assigned

Cyclic measurement operation is performed with/including

the sensor-connection check:

0_BIN

cycwscn

0 = Sensor connection check is performed

1 = Sensor connection check is not performed

The bits [9:4] in the 1E_HEXregister define whether the cycle measurement sequence performs the respective

measurement type in the first slot or only after respective slots_X have been completed for the first time.

Note: The SSC and analog output will only become valid after the sensor, temperature, and related auto-zero

measurements have already been conducted for the first time. The first output signals maybe invalid until this condition

is reached.

0 = Perform the sensor measurement in the first slot

1 = Do not perform the sensor measurement in the first slot

0_BIN

startS_wfirstn

0 = Perform the auto-zero sensor measurement in the

first slot

1E_HEX

(continued)

1 = Do not perform the auto-zero sensor measurement

in the first slot

0_BIN

startAZS_wfirstn

Note: The startAZS_wfirstn bit is ignored for the cyclic

operation if the AZMs_on = 0 = “off.”

0 = Perform the temperature measurement in the first

slot

0_BIN

startT_wfirstn

1 = Do not perform the temperature measurement in the

first slot

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Datasheet

NVM Address

Word/Bit Range Default Setting

Description

Notes/Explanations

0 = Perform the auto-zero temperature measurement in

the first slot

1 = Do not perform the auto-zero temperature

measurement in the first slot

0_BIN

startAZT_wfirstn

Note: The startAZT_wfirstn bit is ignored for the cyclic

operation if the AZMt_on = 0 = “off.”

0_BIN

–

Not assigned

Diagnostics: sensor connection checks:

0 = Perform sensor connection checks in the first slot

0_BIN

startSC_wfirstn

1 = Do not perform sensor connection checks in the first

slot

Defines the number of pause slots between two subsequent

temperature measurements:

0 =

No pause, measure temperature at each

slot

15:10

00 0000_BIN

slots_T

1_DECto 63_DEC

Pause slots after the slot with the

temperature measurement

Note: Set slots_T = slots_AZT for correct Cyclic

Operation.

Defines the number of pause slots between two subsequent

auto-zero temperature (AZT) measurements:

0 =

No pause, measure AZT at each slot

5:0

00 0000_BIN

slots_AZT

1 to 63_DEC= Number of pause slots after the slot with the

AZT measurement

Note: If AZMt_on = 0, no auto-zero temperature

measurement will be performed.

Defines the number of pause slots between two subsequent

sensor/bridge measurements:

0 =

No pause, measure sensor at each slot

9:6

0000_BIN

slots_S

1_DECto 15_DEC

Number of pause slots after the slot with

the sensor measurement

1F_HEX

Note: Set slots_S = slots_AZS for correct Cyclic

Operation.

Defines the number of pause slots between two subsequent

auto-zero-sensor (AZS) measurements:

0 =

No pause, measure AZS at each slot

13:10

0000_BIN

slots_AZS

1_DECto 15_DEC

Number of pause-slots after the slot with

sensor measurement

Note: If AZMs_on = 0, no auto-zero-sensor measurement is

performed.

15:14

5:0

00_BIN

–

These bits must be 00_BINto ensure proper Cyclic Operation

00 0000_BIN

Not assigned.

Defines the number of pause slots between two subsequent

sensor connection check runs:

0 =

No pause, always check sensor

connection

20_HEX

15:6

00 0000 0000_BIN

slots_SC

1_DECto 1023_DEC

Number of pause-slots after slot with

Sensor-Connection check

Selection of (Sensor) Connection Checks to be Conducted

The first 10 bits of register 21_HEXare the select_checks[9:0] bit field:

Loss of sensor positive connection, INP ^[f]

0_BIN

inp_check

0 = Check is not performed; result is not signalized

1 = Check is performed; result is signalized

Loss of bridge/sensor negative connection, INN ^[f]

0 = Check is not performed; result is not signalized

1 = Check is performed; result is signalized

21_HEX

0_BIN

inn_check

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Datasheet

NVM Address

Word/Bit Range Default Setting

Description

Notes/Explanations

Signal at pin INP out of range (leaking/short to VSS or

VDDB)

0_BIN

inp_range_check

0 = Check is not performed; result is not signalized

1 = Check is performed; result is signalized

Signal at pin INN out of range (leaking/short to VSS or

VDDB)

0_BIN

inn_range_check

0 = Check is not performed; result is not signalized

1 = Check is performed; result is signalized

Sensor short (INN = INP) ^[f]

sens_short

_check

0_BIN

0 = Check is not performed; result is not signalized

1 = Check is performed; result is signalized

T_EXTpin open

0_BIN

text_open_check 0 = Check is not performed; result is not signalized

1 = Check is performed; result is signalized

Signal at pin T_EXTout of range (leaking / short to VSS or

VDDB)

0_BIN

text_range_check

0 = Check is not performed; result is not signalized

1 = Check is performed; result is signalized

T_EXTpin short to INN

text_inn_short

0_BIN

0 = Check is not performed; result is not signalized

_check

1 = Check is performed; result is signalized

T_EXTpin short to INP

text_inp_short

0_BIN

0 = Check is not performed; result is not signalized

_check

1 = Check is performed; result is signalized

Broken-chip check / chipping check

0_BIN

crack_check

0 = Check is not performed; result is not signalized

1 = Check is performed; result is signalized

Not assigned

15:10

00 0000_BIN

–

DAC (Output Calibration Data)

Encoded, 16bit-quantized measurement value of DAC-output

at V_DD=5V with 10%-DAC-excitation, digital code (199A_HEX).

Programmed at Renesas’ device test. The measured DAC-

voltage ^[e]can be derived as: V_DAC10,AOUT[V] :=

22_HEX

15:0

XXXX_HEX

DAC10RM5V

DAC90RM5V

DAC10RM5V[dec] / 296000 + 0.39

Encoded, 16bit-quantized measurement value of DAC-output

at V_DD=5V with 90%-DAC-excitation, digital code (E666_HEX).

Programmed at Renesas’ device test. The measured DAC-

voltage ^[e]can be derived as: V_DAC90,AOUT[V] :=

23_HEX

15:0

DAC90RM5V[dec] / 284000 + 4.45

Free Memory (Available for Customer Use)

Not assigned (e.g., can be used for Cust_IDx customer

identification number)

24_HEX

…

0000_HEX

–

Not assigned (e.g., can be used for Cust_IDx customer

identification number)

Not assigned (e.g., can be used for Cust_IDx customer

identification number)

34_HEX

15:0

0000_HEX

Generated (checksum) for the entire memory through a linear

feedback shift register (LFSR); signature is checked on

power-up to ensure memory content integrity

35_HEX

Checksum

[a] For I3C operation, this should contain the Legacy Virtual Register (LVR) information: 1X_HEXto Index 0. Fast-Mode is supported.

[b] Use the extTemp_config1 and extTemp_config2 registers for temperature sensor related front-end configuration.

[c] In Current Loop Operation Mode, it must be ensured that a sufficient external V_DD-level > 4.8V is present (e.g., with external supply

transistor, such as JFET or depletion MOSFET, and extra LDO-control option).

[d] If pga_en_shift is enabled, the ZSSC3240 current consumption increases by approximately 100µA. Usage is recommended for

optimizing the analog front-end setup.

[e] The IC provides the originally measured DAC-output voltage V_DAC*0,AOUT[V] with V_DD=5V, Aout_setup=(001_BINor 101_BIN) as reaction on

B3_HEXcommand, see Table 33.

[f] Do not enable (that is, set to 0_BIN) if the IC is connected to an absolute voltage source sensor, for example, Thermopile

(sensor_sup = 10_BIN).

Nov.27.20

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ZSSC3240

Datasheet

The NVM-consistence checksum is calculated (internally by the ZSSC3240 for the whole NVM) using the

polynomial: x¹⁶+ x¹⁵+ x²+ 1. The checksum verification is only realized directly after V_DDpower-on. If the

checksum is successfully verified, then the “Memory Error” status bit is set to 0_BIN

6.6.3. Digital Sensor-Signal-Conditioning Mathematics

The saturation check (signalized by SSC Calculation Unit Saturation, see Table 16) in the ZSSC3240 detects

saturation effects of the internal calculation steps, allowing the final correction output to be determined despite

the saturation. It is possible to get potentially useful signal conditioning results that have had an intermediate

saturation during the calculations. These cases are detectable; e.g., by observing the status bit[0] for each

measurement result. Details about the saturation limits and the valid ranges for values are provided in the

equations in the following sections.

The calibration math description assumes a calculation with integer numbers. The description is numerically

correct concerning values, dynamic range, and resolution.

6.6.3.1. Sensor Signal Correction

The configuration parameter SOT_curve in NVM register 02_HEXselects whether second-order equations

compensate for sensor nonlinearity with a parabolic or S-shaped curve. The parabolic compensation is

recommended for most sensor types.

The following equations describe the available SSC capabilities. The equation terms are as follows:

Corrected sensor reading output via I2C, OWI, or SPI; range [0_HEXto FFFFFF_HEX

S_Raw Raw sensor reading from ADC (after AZ correction, if selected); range [-7FFFFF_HEXto

7FFFFF_HEX

Gain_S Sensor gain term; range [-7FFFFF_HEXto 7FFFFF_HEX

Offset_SSensor offset term; range [-7FFFFF_HEXto 7FFFFF_HEX

]

Tcg

Tco

Temperature coefficient gain term; range [-7FFFFF_HEXto 7FFFFF_HEX

]

Temperature coefficient offset term; range [-7FFFFF_HEXto 7FFFFF_HEX

]

T_Raw Raw temperature reading (after AZ correction); range [-7FFFFF_HEXto 7FFFFF_HEX

]

SOT_tcgSecond-order term for Tcg non-linearity; range [-7FFFFF_HEXto 7FFFFF_HEX

]

SOT_tcoSecond-order term for Tco non-linearity; range [-7FFFFF_HEXto 7FFFFF_HEX

SOT_sens Second-order term for sensor non-linearity; range [-7FFFFF_HEXto 7FFFFF_HEX

]

SENS_shift Post-calibration, post-assembly offset shift; range [-7FFFFF_HEXto 7FFFFF_HEX

]



Absolute value

Bound/saturation number range from ll to ul, overflow/underflow is reported as saturation in the





status byte

The correction formula for the differential signal reading is represented as a two-step process depending on the

SOT_curve setting.

Table 35. Data Format of 24-bit SSC Coefficients

Bit-Number:

…

0 = positive

1 = negative

Meaning, Weighting

2¹

2⁰

2^-1

…

2^-19

2^-20

2^-21

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Datasheet

Table 36. Data Format of Corrected, SSC Results (S and T)

Bit-Number:

…

Meaning, Weighting

2⁰

2^-1

2^-2

2^-3

…

2^-21

2^-22

2^-23

Equations for the parabolic SOT_curve setting (SOT_curve = 0):

Simplified:

T_Raw

2²³

SOT_tcg

2²³

∙

K₁= 2²³

∙

ꢀ

∙

T_Raw+ 4 Tcgꢁ

Equation 7

Equation 8

∙

T_Raw

2²³

SOT_tco

2²³

∙

K = 4 Offset_S + S_raw +

ꢀ

Raw

+ 4 Tcoꢁ

∙

Gain_S

+ 2²³(delimited to positive number range)

∙

Equation 9

Z_SP

∙ ∙

SOT_sens

ꢂ⁴

∙

_SP+ 2²³ꢃ + SENS_shift

(delimited to positive number range)

Equation 10

S =

∙

Complete:

-1

^-1ꢋ

ꢊ

ꢅ

ꢄ

[

^-1

ꢋ

ꢊ

ꢅ

ꢄ

[

-1

T_Raw

2²³

SOT_tcg

ꢆꢇ

Equation 11

Equation 12

K₁= 2²³

Raw

]

+ 4 Tcgꢈ

∙

ꢊ

ꢉ_-2

2²¹

ꢊ

ꢉ_-2

-2

-1

^-1

ꢋ

ꢊ

ꢅ

ꢄ

^-1

ꢋ

ꢊ

ꢅ

ꢄ

ꢅ

ꢄ

[

^-1

ꢋ

ꢊ

-1

T_Raw

2²³

SOT_tco

2²¹

ꢄ

ꢊ

K = 4 Offset_S + S_raw +

ꢆꢇ

]

Raw

+ 4 Tcoꢈ

∙

ꢊ

ꢄ

[

-2

ꢉ_-2

-1

ꢅ

ꢄ

[

ꢋ

Gain_S

2²¹

K₁

2²³

Equation 13

Equation 14

²³

ꢊ

Z_SP

ꢆ

ꢇ

K ]

ꢈ

+ 2

∙

-2

ꢉ₀

-1

ꢅ

ꢄ

[

ꢋ

ꢊ

Z_SP

SOT_sens

2²¹

S =

ꢆꢇ

]

-2

+ 2²³

ꢈ

+ SENS_shift

∙

-2

ꢉ₀

Equations for the S-shaped SOT_curve setting (SOT_curve = 1):

Simplified:

Gain_S

∙

Equation 15

Equation 16

Z_SS

(K₁and K₂according to Equation 7 and Equation 8)

∙ ∙

SOT_sens

S =^Z

ꢂ⁴

Z_SS+ 2²³ꢃ + 2²³+ SENS_shift

(delimited to positive number range)

∙

Complete:

-1

^-1

ꢋ

ꢊ

-1

ꢅ

Gain_S

2²¹

K₁

2²³

Equation 17

ꢄ

[

Z_SS

ꢆ

ꢇ

K ]

ꢈ

∙

ꢊ

ꢉ_-2

-2

Nov.27.20

Page 56

ZSSC3240

Datasheet

Equation 18

-1

^-1

ꢋ

ꢊ

ꢅ

ꢄ

[

ꢋ

ꢊ

-1

SOT_sens

2²¹

ꢄ

[

S =

ꢆꢇ

+ 2²³

ꢈ

+ 2²³+ SENS_shift

Z_SS

]

∙

ꢊ

-2

ꢉ_-2

ꢉ₀

6.6.3.2. Temperature Signal Correction

Temperature is measured either internally by the ZSSC3240 or through an additional external element or by

means of a combination of ZSSC3240-internal and external temperature sensing capabilities; see sections 6.2.3

and 6.2.4. Temperature correction contains both linear gain and offset terms as well as a second-order term to

correct for any nonlinearities. For temperature, second-order compensation for nonlinearity is always parabolic.

The correction equation terms are as follows:

Corrected temperature sensor reading output via digital interface; range [0_HEXto FFFFFF_HEX

Gain_T Gain coefficient for temperature; range [-7FFFFF_HEXto 7FFFFF_HEX

T_Raw Raw temperature reading after AZ correction; range [-7FFFFF_HEXto 7FFFFF_HEX

Offset_TOffset coefficient for temperature; range [-7FFFFF_HEXto 0x7FFFFF_HEX

SOT_T Second-order term for temperature source nonlinearity; range [-7FFFFF_HEXto 7FFFFF_HEX

]

T_Shift Shift for post-calibration/post-assembly offset compensation [-7FFFFF_HEXto 7FFFFF_HEX

The correction formula is best represented as a two-step process as follows:

Simplified:

]

Gain_T

∙

Equation 19

(

)

Z_T=

T_Raw + 4 Offset_T + 2

(delimited to positive number range)

∙

T = ^Z

ꢂ^{4 × SOT_T}Z + 2²³ꢃ + T_shift (delimited to positive number range)

Equation 20

∙

Complete:

-1

Gain_T

2²¹

+ 2²³

ꢈ

-1

Equation 21

Equation 22

ꢌ

ꢍ²

-2

Z_T= ꢆꢇ

T_Raw + 4 Offset_T

]

-2

∙

-1

ꢅ

ꢋ

ꢊ

Z_T

SOT_T

2²¹

T =

ꢆꢇ

Z ]

+ 2²³

ꢈ

+ T_shift

ꢄ

[

∙

-2

ꢉ₀

Nov.27.20

Page 57

ZSSC3240

Datasheet

6.7

External, Extra LDO (LDOctrl) for Applications for > 5.5V

The ZSSC3240 has integrated voltage regulators that generate separate analog and digital ZSSC3240-internal

voltages for any valid external supply voltage, V_DD(2.7V to 5.5V). For proper ZSSC3240 function, the directly

applied supply voltage should not exceed the maximum V_DDlimit.

The ZSSC3240 also supports applications with higher application-inherent supply voltages greater than 5.5V.

The ZSSC3240 provides a voltage regulation signal at the LDOctrl pin and a programmable IC supply, i.e. V_DD

level regulation target level, VDD_ldoctrl_target in the SSF2 register. The use of an additional external regulator

transistor (by means of, for example JFET, depletion MOSFET, or comparable) further improves the power-

supply rejection ratio (PSRR); i.e., it reduces effects from the external supply voltage onto the sensor

measurement results in addition to the ZSSC3240-internal regulator properties. If the external extra supply

regulation is not used or needed, the respective feature should be disabled by disable_ldoctrl = 1_BIN

Table 37. IC Supply, V_DDTarget Level Selection with External Voltage Regulation, External LDO

VDD_ldoctrl_target

V_DDTarget Level

Notes

Bit[1]

Bit[0]

4.8V

5.0V

5.2V

5.4V

Recommended, typical settings.

Recommendation: Use the clamping diode at V_DD(to FB for current-loop output configurations or to VSS in all

other cases with external LDO as shown by gray dashed line in Figure 24) to ensure over-voltage protection at

the initial application power-on. The external transistor, depicted as JFET¹can be a real JFET type, or, for

example, depletion MOSFET and comparable. It must be selected such that the drain-source voltage can be at

least V_DDext– 5V.

JFET

I_SENSOR+ I_IC

Application Supply

V_DDext> 5.5V

VDD

IC-Internal

Regulators

LDO Control /

Regulation

VDDA

VDDD

LDOctrl

AOUT

Analog Front-End

Digital Core

C_VDD

- Internal Temp.Sensor

- PGA

- ADC

- IC Control

- Memory

- SSC Math

- inMUX

Analog Output

VSS

- DAC

- AOUT Driver Stages

- MUXout

ZSSC3240

LDO control circuitry

Figure 25. LDOctrl Application Topology

Table 38. External LDO Operating Conditions

Symbol

Parameter

Minimum

Typical

Maximum

Units

C_ctrl

Allowed parasitic capacitance at LDOctrl pin

Buffer/filter capacitance between V_DDand VSS

–

150

100

500

120

C_VDD

Depending on the V_DDext>5.5V application main supply, different external transistors can be applied, for example BSS169 (Infineon),

DN3545N8 (Microchip-Supertex), MMBF4392LT1G (Fairchild), etc.

Nov.27.20

Page 58

ZSSC3240

Datasheet

7. Calibration

Calibration essentially involves collecting raw signal and temperature data from the sensor-ZSSC3240 system

for different known sensor-element values (i.e., for a resistive bridge or an absolute voltage source) and

temperatures. This raw data can then be processed by the calibration master (assumed to be the user’s

computer), and the calculated calibration coefficients can then be written to on-chip memory.

Brief overview of the three mains steps involved in calibrating the ZSSC3240:

1. Assigning a unique identification to the ZSSC3240. This identification is written to shadow RAM and

programmed in NVM. This unique identification can be stored in the two 16-bit registers dedicated to the

customer ID. It can be used as an index into a database stored on the calibration PC. This database will

contain all the raw values of the connected sensor-element readings and temperature readings for that part,

as well as the known sensor-element measurand conditions and temperature to which the sensor-element

was exposed.

2. Data collection. Data collection involves getting uncorrected (raw) data from the external sensor at different

known measurand values and temperatures. Then this data is stored on the calibration master using the

unique identification of the device as the index to the database.

3. Coefficient calculation and storage in NVM. After enough data points have been collected to calculate all the

desired coefficients, the coefficients can be calculated by the calibration master. Then the coefficients can be

programmed to the memory.

4. Result. The sensor signal and the characteristic temperature effect on output will be linearized according to

the setup-dependent maximum output range.

It is essential to perform the calibration with a fixed programming setup during the data collection phase.

Strong recommendation: To prevent any accidental misprocessing, keep the sensor front-end NVM setup

(registers SSF1, SSF2, SM_config1, SM_config2, extTemp_config1, extTemp_config2) stable during the entire

calibration process as well as in the subsequent operation.

Note: A ZSSC3240 calibration only fits the setup used during its calibration. Changes of functional parameters

after a successful calibration can decrease the precision and accuracy performance of the ZSSC3240 as well as

of the entire application.

8. Package Outline Drawings

The package outline drawings are appended at the end of this document and are accessible from the link below.

The package information is the most current data available.

https://www.idt.com/document/psc/24-vfqfpn-package-outline-drawing-40-x-40-x-085-mm-body05mm-pitch-

epad-25-x-25-wettable-flank-side

9. Marking Diagram

1. Line 1 is the truncated part number.

3240C

YYWW

2. Line 2 – “YYWW” are the last two digits of the year and

week that the part was assembled.

XXXXX

3. Line 3 – “XXXXX” denotes assembly lot number.

Nov.27.20

Page 59

ZSSC3240

Datasheet

10. Ordering Information

Orderable Part Number Description and Package

MSL Rating

Carrier Type

Wafer Box

13 inch Reel

Wafer Box

13 inch Reel

7 inch Reel

Temperature

-40 to 85°C

-40 to 125°C

ZSSC3240CC1B

ZSSC3240CC2B

ZSSC3240CC5B

ZSSC3240CC6B

ZSSC3240CC3R

ZSSC3240CI1B

ZSSC3240CI2B

ZSSC3240CI5B

ZSSC3240CI6B

ZSSC3240CI3R

ZSSC3240CI3W

DICE on 304µm wafer no inking

DICE on 725µm wafer no inking

DICE on 304µm wafer with inking

DICE on 725µm wafer with inking

4  4 mm²24-QFN

MSL1

DICE on 304µm wafer no inking

DICE on 725µm wafer no inking

DICE on 304µm wafer with inking

DICE on 725µm wafer with inking

4  4 mm²24-QFN

MSL1

4  4 mm²24-QFN

DICE on 304µm wafer no inking, pre-configured for

Current-Loop

ZSSC3240CL1B

ZSSC3240CL3R

ZSSC3240KIT

Wafer Box

-40 to 125°C

4  4 mm²24-QFN, pre-configured for Current-Loop

MSL1

13 inch Reel

Modular ZSSC3240 SSC Evaluation Kit including three interconnecting boards, five ZSSC3240 24-VFPQFN

samples, and cable. Software is available for download on www.IDT.com/ZSSC3240.

11. Glossary

Term

Description

A2D

ACK

ADC

AGND

Analog-to-Digital

Acknowledge (interface’s protocol indicator for successful data/command transfer)

Analog-to-Digital Converter or Conversion

Analog-Ground, ZSSC3240-internal … VDDA_int/2

Auto-Zero (unspecific)

AZS

AZT

CLK

DAC

EMC

EMI

Auto-Zero Measurement for (External) Sensor Path

Auto-Zero Measurement for (External or Internal) Temperature Path

Clock

Digital-to-Analog Converter or Conversion

Electromagnetic Compatibility

Electromagnetic Immision (Immunity), i.e. immunity on spuriously coupled high-frequency disturbances

End of Conversion

EOC

FSO

LFSR

LSB

MSB

MSL

NACK

NVM

Op amp

PGA

POR

PPT

PSRR

PTC

Full Scale Output (value in percent relative to the ADC maximum output code; resolution dependent)

Linear Feedback Shift Register

Least Significant Bit

Most Significant Bit

Moisture Sensitivity Level

Not Acknowledge (interface’s protocol indicator for unsuccessful data/command transfer)

Nonvolatile Memory

Operating Amplifier

Programmable Gain Amplifier

Power-On Reset

Parts-per-Thousand, 1PPT=1/1000

Power Supply (Disturbance) Rejection Ratio

Positive Temperature Coefficient (sensing element)

SSC-corrected Sensor Readout / Result

Sensor Measurement

SOT

SSF

Second Order Term

Smart-Sensor Function (specific NVM registers)

SSC-corrected (extra) Temperature Readout / Result

Temperature Coefficient

Nov.27.20

Page 60

ZSSC3240

Datasheet

12. Revision History

Revision Date

Description of Change

Nov.27.20

 Explanations for EOC

 New product version ZSSC3240CL* pre-configured NVM for current-loop applications

 Correction of Marking Diagram corrected for “3240C”

 slots_S corrected to be up to 15_DEC, slots_AZS definition updated

 Added note, not to apply sensor-open/short diagnostic checks together with Thermopile sensors

 Corrected Equation 1

 Reduced conversion time for internal temp. sensor and typ. SSC-conversion time

 Added figure and explanation for digital output behavior in cyclic mode

Mar.13.20

Initial release

Nov.27.20

Page 61

24-VFQFPN, Package Outline Drawing

4.0 x 4.0 x 0.85 mm Body,0.50mm Pitch,Epad 2.50 x 2.50 mm Wettable Flank (Side Plate)

NLG24S1, PSC-4192-04, Rev 02, Page 1

24-VFQFPN, Package Outline Drawing

4.0 x 4.0 x 0.85 mm Body,0.50mm Pitch,Epad 2.50 x 2.50 mm Wettable Flank (Side Plate)

NLG24S1, PSC-4192-04, Rev 02, Page 2

Package Revision History

Description

Rev 02 New Format, Add Land Pattern, Change EPC Code

Update Title

Date Created Rev No.

Nov 5, 2018

Jul 5, 2017

Rev 01

1RWLFH

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