RF2054 [RFMD]
LOW POWER PLL AND VCO WITH INTEGRATED MIXERS;
| 型号： | RF2054 |
| 厂家： | 
RF MICRO DEVICES |
| 描述： | LOW POWER PLL AND VCO WITH INTEGRATED MIXERS |
| 文件： | 总39页 (文件大小：2767K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
RF2054Low
Power PLL and
VCO with Inte-
grated Mixers
RF2054
LOW POWER PLL AND VCO WITH INTEGRATED
MIXERS
Package: QFN, 32-Pin, 5mm x 5mm
VCO
Features
Fractional-N Synthesizer
LO
divider
Very Fine Frequency Resolution
1.5Hz for 26MHz Reference
Sw
Synth
Frac-N
LO Frequency Range 940MHz to
1000MHz
N
sequence
divider
generator
LO
divider
Low Phase Noise VCO
Integrated LO Buffers
Two Wideband RF Mixers
Phase /
freq
detector
Charge
pump
Ref
divider
Mixer Frequency Range 30MHz
to 2500MHz
Mixer Input IP3 +12dBm
Functional Block Diagram
Mixer Bias Adjustable for Low
Power Operation
Product Description
The RF2054 is a low power, high performance, frequency conversion chip with inte-
grated local oscillator (LO) and a pair of RF mixers. The synthesizer includes an inte-
grated fractional-N phase locked loop that can control the VCO to produce a low
phase noise and low spurious LO signal with very fine frequency resolution. The
VCO output can then be divided by one, two, or four in the LO divider, the output of
which drives the mixer, which converts the signal into the required frequency band.
The LO generation block has been optimized to operate with the VCO covering the
frequency range from 940MHz to 1000MHz, set by the value of the external induc-
tor used. The mixers are broadband and can operate from 30MHz to 2500MHz at
the input and output, enabling both up and down conversion. An external reference
source of between 10MHz and 26MHz can be used with the RF2054.
2.1V to 2.3V Power Supply
Low Current Consumption
45mA typ. at 2.2V
3-Wire Serial Interface
Applications
Band Shifters
Super-Heterodyne Radios
Diversity Receivers
Wireless Telemetry
All on-chip registers are controlled through a simple three-wire serial interface. The
RF2054 has been characterized for 2.2V operation and low power consumption. It
is available in a plastic 32-pin, 5mm x 5mm QFN package.
Optimum Technology Matching® Applied
GaAs HBT
GaAs MESFET
InGaP HBT
SiGe BiCMOS
Si BiCMOS
SiGe HBT
GaAs pHEMT
Si CMOS
Si BJT
GaN HEMT
BiFET HBT
LDMOS
RF MICRO DEVICES®, RFMD®, Optimum Technology Matching®, Enabling Wireless Connectivity™, PowerStar®, POLARIS™ TOTAL RADIO™ and UltimateBlue™ are trademarks of RFMD, LLC. BLUETOOTH is a trade-
mark owned by Bluetooth SIG, Inc., U.S.A. and licensed for use by RFMD. All other trade names, trademarks and registered trademarks are the property of their respective owners. ©2012, RF Micro Devices, Inc.
7628 Thorndike Road, Greensboro, NC 27409-9421 · For sales or technical
support, contact RFMD at (+1) 336-678-5570 or customerservice@rfmd.com.
DS120320
1 of 39
RF2054
Absolute Maximum Ratings
Parameter
Caution! ESD sensitive device.
Rating
-0.5 to +3.6
Unit
V
Exceeding any one or a combination of the Absolute Maximum Rating conditions may
cause permanent damage to the device. Extended application of Absolute Maximum
Rating conditions to the device may reduce device reliability. Specified typical perfor-
mance or functional operation of the device under Absolute Maximum Rating condi-
tions is not implied.
Supply Voltage (V
)
DD
Input Voltage (V ), any Pin
-0.3 to V +0.3
V
IN
DD
The information in this publication is believed to be accurate and reliable. However, no
responsibility is assumed by RF Micro Devices, Inc. ("RFMD") for its use, nor for any
infringement of patents, or other rights of third parties, resulting from its use. No
license is granted by implication or otherwise under any patent or patent rights of
RFMD. RFMD reserves the right to change component circuitry, recommended appli-
cation circuitry and specifications at any time without prior notice.
RF/IF Mixer Input Power
+15
dBm
°C
Operating Temperature Range
Storage Temperature Range
-40 to +85
-65 to +150
°C
RFMD Green: RoHS compliant per EU Directive 2002/95/EC, halogen free
per IEC 61249-2-21, < 1000ppm each of antimony trioxide in polymeric
materials and red phosphorus as a flame retardant, and <2% antimony in
solder.
Specification
Parameter
Unit
Condition
Min.
Typ.
Max.
ESD Requirements
Human Body Model
General
2000
1000
V
V
RF Pins
Machine Model
General
200
100
V
V
RF Pins
Operating Conditions
Supply Voltage (V
)
2.1
-20
2.2
2.3
V
DD
Temperature (T
)
+75
°C
OP
V
= Supply to DIG_VDD pin
Logic Inputs/Outputs
Input Low Voltage
DD
-0.3
1.5
+0.5
V
V
Input High Voltage
V
DD
Input Low Current
Input High Current
-10
-10
+10
+10
uA
uA
Input = 0V
Input = V
DD
Output Low Voltage
Output High Voltage
0
0.2 * V
V
V
DD
0.8 * V
V
DD
DD
Load Resistance
Load Capacitance
Static
10
k
20
48
pF
V
= +2.2V, MIX_IDD = 001
DD
Supply Current (I
)
DD
One Mixer Enabled
Both Mixers Enabled
42
-6
45
57
3
mA
mA
mA
A
FULLD = 0
FULLD = 1
Standby
Reference oscillator and bandgap only.
ENBL = 0 and REF_STBY = 0
Mixer output driving 4:1 balun, MIX_IDD = 001
Power Down Current
Mixer
140
Gain (DUT Only)
Gain
-3.5
-6.5
-2
dB
dB
Not including balun losses.
Including balun losses, 1GHz to 2GHz conver-
sion.
Noise Figure
11
dB
IIP
+12
dBm
3
Pin1dB
+1
dBm
MHz
dB
RF and IF Port Frequency Range
Mixer Input Return Loss
30
2500
10
100 differential
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2 of 39
DS120320
RF2054
Specification
Typ.
Parameter
Unit
Condition
Min.
Max.
3.3nH (*2) VCO Inductor
Voltage Controlled Oscillator
VCO Frequency Range
900
1150
MHz
Open Loop Phase-Noise at 1MHz
Offset
960MHz LO Frequency
VCO Tuning Gain
-134
15
dBc/Hz
MHz/V
MHz
960MHz LO Frequency
Reference Oscillator
External Reference Frequency
Reference Divider Ratio
External Reference Input Level
10
1
21
26
7
500
800
1200
mV
AC-coupled
P-P
3.3nH (*2) VCO Inductor
Local Oscillator
Synthesizer Output Frequency
Phase Detector Frequency
940
1000
26
MHz
MHz
Closed Loop Phase-Noise at
960MHz LO
21MHz phase detector frequency
10kHz Offset
100kHz Offset
1MHz Offset
-90
dBc/Hz
dBc/Hz
dBc/Hz
-100
-130
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support, contact RFMD at (+1) 336-678-5570 or customerservice@rfmd.com.
DS120320
3 of 39
RF2054
Detailed Functional Block Diagram
IP1
ANA_VDD
DIG_VDD
RFIP1N
ENBL
MODE
CONTROL
1:1
RFIP1P
RESETB
ANA_DEC
ANA_VDD
SDATA
SCLK
ENX
RFOP1P
RFOP1N
SERIAL
BUS
OP1
Analog
Regulator
Digital
Regulator
Serial Data Interface,
Control and Biasing
4:1
Mixer 1
REXT
LO Divider 1
/1, /2, or /4
INDN
Voltage Controlled Oscillator
LO Buffer 1
INDP
Vtune
LFILT3
Mux
Synthesizer
Vref
LFILT2
LFILT1
Frac-N
Sequence
Generator
N Divider
LO Buffer 2
Phase /
Freq
Detector
-
+
Charge
Pump
LO Divider 2
/1, /2, or /4
ANA_VDD
Mixer 2
RFOP2P
RFOP2N
REFERENCE
CLOCK
OP2
XTALIPP
XTALIPN
Reference Divider
/1 to /7
Reference Oscillator
Circuitry
4:1
RFIP2P
RFIP2N
IP2
1:1
Pin Out
32 31 30 29 28 27 26 25
ENBL
INDP
1
2
3
4
5
6
7
8
24 RFIP2P
23 RFIP2N
INDN
22 ANA_VDD
21 NC
REXT
EP
ANA_DEC
LFILT1
LFILT2
LFILT3
20 NC
19 DIG_VDD
18 RFOP1P
17 RFOP1N
9
10 11 12 13 14 15 16
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4 of 39
DS120320
RF2054
Pin Names and Descriptions
Pin
1
Name
ENBL
Description
Ensure that the ENBL high voltage level is not greater than V . An RC low-pass filter could be used to reduce
DD
digital noise.
VCO 3 differential inductor. Connect to ground for DC bias.
2
3
4
INDP
INDN
REXT
VCO 3 differential inductor. Connect to ground for DC bias.
External bandgap bias resistor. Connect a 51k resistor from this pin to ground to set the bandgap reference
bias current. This could be a sensitive low frequency noise injection point.
Analog supply decoupling capacitor. Connect to analog supply and decouple as close to the pin as possible.
Phase detector output. Low-frequency noise-sensitive node.
Loop filter op-amp output. Low-frequency noise-sensitive node.
VCO control input. Low-frequency noise-sensitive node.
5
6
7
8
ANA_DEC
LFILT1
LFILT2
LFILT3
MODE
XTALIPP
XTALIPN
GND
Mode select pin. An RC low-pass filter can be used to reduce digital noise.
Reference oscillator input. Should be AC-coupled if an external reference is used. See note 3.
Reference oscillator input. Should be AC-coupled to ground if an external reference is used. See note 3.
Connect to ground.
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
EP
Differential input 1. See note 1.
RFIP1P
RFIP1N
NC
Differential input 1. See note 1.
NC
Differential output 1. See note 2.
RFOP1N
RFOP1P
DIG_VDD
NC
Differential output 1. See note 2.
Digital supply. Should be decoupled as close to the pin as possible.
NC
Analog supply. Should be decoupled as close to the pin as possible.
Differential input 2. See note 1.
ANA_VDD
RFIP2N
RFIP2P
NC
Differential input 2. See note 1.
NC
Differential output 2. See note 2.
RFOP2N
RFOP2P
RESETB
ENX
SCLK
SDATA
Exposed pad
Differential output 2. See note 2.
Chip reset (active low). Connect to DIG_VDD if external reset is not required.
Serial interface select (active low). An RC low-pass filter could be used to reduce digital noise.
Serial interface clock. An RC low-pass filter could be used to reduce digital noise.
Serial interface data. An RC low-pass filter could be used to reduce digital noise.
Connect to ground. This is the ground reference for the circuit. All decoupling should be connected here through
low impedance paths.
Note 1: The signal should be connected to this pin such that DC current cannot flow into or out of the chip, either by using AC
coupling capacitors or by use of a transformer (see evaluation board schematic).
Note 2: DC current needs to flow from ANA_VDD into this pin, either through an RF inductor, or transformer (see evaluation
board schematic).
Note 3: Alternatively an external reference can be AC-coupled to pin 11 XTALIPN, and pin 10 XTALIPP decoupled to ground. This
may make PCB routing simpler.
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support, contact RFMD at (+1) 336-678-5570 or customerservice@rfmd.com.
DS120320
5 of 39
RF2054
Typical Performance Characteristics: PLL and VCO
V
= +2.2V, T = +25°C unless stated, as measured on RF2054 evaluation board.
DD
A
See schematic page 36.
Synthesizer Phase Noise versus Frequency
Synthesizer Phase Noise versus Temperature
LO = 960MHz, 21MHz Reference and +2.2V Supply
21MHz Reference and +2.2V Supply
-60.0
-60.0
-80.0
-80.0
-100.0
-120.0
-140.0
-160.0
-100.0
-120.0
-140.0
-160.0
-20ꢀC
0ꢀC
940MHz
960MHz
980MHz
1000MHz
+25ꢀC
+50ꢀC
+75ꢀC
1.0
10.0
100.0
1000.0
10000.0
1.0
10.0
100.0
1000.0
10000.0
Offset Frequency (kHz)
Offset Frequency (kHz)
VCO Phase Noise versus Frequency
+2.2V Supply
VCO Phase Noise versus Temperature
VCO Frequency 960MHz, +2.2V Supply
-20.0
-40.0
-20.0
-40.0
-20ꢀC
0ꢀC
940MHz
960MHz
980MHz
1000MHz
+25ꢀC
+50ꢀC
+75ꢀC
-60.0
-60.0
-80.0
-80.0
-100.0
-120.0
-140.0
-160.0
-100.0
-120.0
-140.0
-160.0
1.0
10.0
100.0
1000.0
10000.0
1.0
10.0
100.0
1000.0
10000.0
Offset Frequency (kHz)
Offset Frequency (kHz)
VCO Coarse Tuning versus Frequency
3.3nH VCO Inductors and +2.2V Supply
VCO Frequency versus Tuning Voltage and Temperature
For the Same Coarse Tune Setting, +2.2V Supply
970
125.0
965
960
955
950
945
940
100.0
75.0
50.0
25.0
0.0
-20ꢀC
0ꢀC
-20ꢀC
0ꢀC
+25ꢀC
+50ꢀC
+75ꢀC
+25ꢀC
+50ꢀC
+75ꢀC
800
900
1000
1100
1200
1300
0.0
0.5
1.0
1.5
2.0
VCO Frequency (MHz)
Tuning Voltage (Volts)
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DS120320
RF2054
Typical Performance Characteristics: RF Mixer 1, Downconversion
V
= +2.2V, T = +25°C, unless stated, as measured on RF2054 evaluation board.
DD
A
See schematic page 36.
Mixer 1 Conversion Gain versus Temp and Voltage
Total Supply Current versus Temp and Voltage
RF Input = 2000MHz, IF Output = 1040MHz
Mixer 1 Enabled, LO Frequency = 960MHz
-2.0
-3.0
-4.0
-5.0
-6.0
-7.0
-8.0
-9.0
-10.0
48.0
47.0
46.0
45.0
44.0
43.0
42.0
41.0
40.0
-20ꢀC
0ꢀC
+25ꢀC
+50ꢀC
+75ꢀC
-20ꢀC
0ꢀC
+25ꢀC
+50ꢀC
+75ꢀC
2.05
2.10
2.15
2.20
2.25
2.30
2.35
2.05
2.10
2.15
2.20
2.25
2.30
2.35
Supply Voltage
Supply Voltage
Mixer 1 Input IP3 versus Temp and Voltage
RF Input = 2000MHz, IF Output = 1040MHz
Mixer 1 Linearity versus Voltage
Downconversion, IF Output = 1040MHz
16.0
14.0
12.0
10.0
8.0
14.0
14.0
12.0
10.0
8.0
12.0
10.0
8.0
IIP3, +2.1V
IIP3, +2.2V
IIP3, +2.3V
6.0
6.0
6.0
-20° C
0° C
Pin 1dB, +2.1V
Pin 1dB, +2.2V
Pin 1dB, +2.3V
4.0
4.0
4.0
+25° C
+50° C
+75° C
2.0
2.0
2.0
0.0
2.05
0.0
1970
0.0
2030
2.10
2.15
2.20
2.25
2.30
2.35
1980
1990
2000
2010
2020
Supply Voltage
RF Input Frequency (MHz)
Mixer 1 Noise Figure versus Temp and Voltage
RF Input = 2000MHz, IF Output = 1040MHz
Mixer 1 LO Leakage versus Temp and Voltage
LO Frequency 960MHz
14.0
13.0
12.0
11.0
10.0
9.0
-40.0
-42.0
-44.0
-46.0
-48.0
-50.0
-52.0
-54.0
-56.0
-58.0
-60.0
-20ꢀC
0ꢀC
-20ꢀC
0ꢀC
8.0
+25ꢀC
+50ꢀC
+75ꢀC
+25ꢀC
+50ꢀC
+75ꢀC
7.0
6.0
2.05
2.10
2.15
2.20
2.25
2.30
2.35
2.05
2.10
2.15
2.20
2.25
2.30
2.35
Supply Voltage
Supply Voltage
7628 Thorndike Road, Greensboro, NC 27409-9421 · For sales or technical
support, contact RFMD at (+1) 336-678-5570 or customerservice@rfmd.com.
DS120320
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RF2054
Typical Performance Characteristics: RF Mixer 2, Upconversion
V
= +2.2V, T = +25°C unless stated, as measured on RF2054 evaluation board.
DD
A
See schematic page 36.
Mixer 2 Conversion Gain versus Temp and Voltage
Total Supply Current versus Temp and Voltage
IF Input = 1040MHz, RF Output = 2000MHz
Mixer 2 Enabled, LO Frequency = 960MHz
-2.0
-3.0
-4.0
-5.0
-6.0
-7.0
-8.0
-9.0
-10.0
48.0
47.0
46.0
45.0
44.0
43.0
42.0
41.0
40.0
-20ꢀC
0ꢀC
+25ꢀC
+50ꢀC
+75ꢀC
-20ꢀC
0ꢀC
+25ꢀC
+50ꢀC
+75ꢀC
2.05
2.10
2.15
2.20
2.25
2.30
2.35
2.35
2.35
2.05
2.10
2.15
2.20
2.25
2.30
2.35
Supply Voltage
Supply Voltage
Mixer 2 Input IP3 versus Temp and Voltage
IF input = 1040MHz, RF Output = 2000MHz
Mixer 2 Linearity versus Voltage
Upconversion, IF Input = 1040MHz
16.0
14.0
12.0
10.0
8.0
14.0
12.0
10.0
8.0
14.0
12.0
10.0
8.0
IIP3, +2.1V
IIP3, +2.2V
IIP3, +2.3V
Pin 1dB, +2.1V
Pin 1dB, +2.2V
Pin 1dB, +2.3V
6.0
6.0
6.0
4.0
4.0
-20ꢀC
0ꢀC
4.0
2.0
2.0
+25ꢀC
+50ꢀC
+75ꢀC
2.0
0.0
0.0
0.0
2.05
-2.0
-2.0
2.10
2.15
2.20
2.25
2.30
1970
1980
1990
2000
2010
2020
2030
Supply Voltage
RF Input Frequency (MHz)
Mixer 2 Noise Figure versus Temp and Voltage
IF Input = 1040MHz, RF Output = 2000MHz
Mixer 2 LO Leakage versus Temp and Voltage
LO Frequency 960MHz
14.0
13.0
12.0
11.0
10.0
9.0
-40.0
-42.0
-44.0
-46.0
-48.0
-50.0
-52.0
-54.0
-56.0
-58.0
-60.0
-20ꢀC
0ꢀC
+25ꢀC
+50ꢀC
+75ꢀC
-20ꢀC
0ꢀC
8.0
+25ꢀC
+50ꢀC
+75ꢀC
7.0
6.0
2.05
2.10
2.15
2.20
2.25
2.30
2.05
2.10
2.15
2.20
2.25
2.30
2.35
Supply Voltage
Supply Voltage
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support, contact RFMD at (+1) 336-678-5570 or customerservice@rfmd.com.
8 of 39
DS120320
RF2054
Typical Performance Characteristics: RF Mixers
V
= +2.2V, T = +25°C unless stated, as measured on RF2054 evaluation board.
DD
A
See schematic page 36.
Typical Mixer Conversion Gain
+25°C and +2.2V Supply, RF = IF + LO
Typical LO Leakage at Mixer Output
+25°C and +2.2V Supply
-2.0
-3.0
-4.0
-5.0
-6.0
-7.0
-8.0
-9.0
-10.0
0.0
-10.0
-20.0
-30.0
-40.0
-50.0
-60.0
Mixer 1, RF in = 2000MHz
Mixer 2, IF in = 1050MHz
Mixer 1
Mixer 2
880
900
920
940
960
980
1000
880
900
920
940
960
980
1000
LO Frequency (MHz)
LO Frequency (MHz)
Total Supply Current versus Temp and Voltage
Full Duplex Mode, LO Frequency = 960MHz
60.0
59.0
58.0
57.0
56.0
55.0
54.0
53.0
52.0
51.0
50.0
-20ꢀC
0ꢀC
+25ꢀC
+50ꢀC
+75ꢀC
2.05
2.10
2.15
2.20
2.25
2.30
2.35
Supply Voltage
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support, contact RFMD at (+1) 336-678-5570 or customerservice@rfmd.com.
DS120320
9 of 39
RF2054
Detailed Description
The RF2054 is a frequency converter chip that includes a fractional-N phase locked loop, a low noise VCO core, an LO signal
multiplexer, two LO buffer circuits, and two RF mixers. Synthesizer programming, device configuration, and control are
achieved through a mixture of hardware and software controls. All on-chip registers are programmed through a simple three-
wire serial interface.
VCO
The VCO core in the RF2054 consists of one VCO which covers a frequency range dependant on the value of the external
inductor used. The RF2054 has been characterized with 3.3nH inductors, so the VCO covers from 940MHz to 1000MHz. Note
that the VCO inductor is differential so the value given is the inductance on each device pin, and the total differential induc-
tance will be twice this value.
VCO3 must be selected using the PLL1x0:P1_VCOSEL and PLL2x0:P2_VCOSEL control word and setting 10 for VCO3. The VCO
has 128 overlapping bands to achieve an acceptable VCO gain (MHz/V) and hence a good phase noise performance across
the whole tuning range. The chip automatically selects the correct VCO band (VCO coarse tuning) to generate the desired fre-
quency based on the values programmed into the PLL1 and PLL2 register banks. For information on how to program the
desired LO frequency into the PLL1 and PLL2 banks, refer to the next section. The automatic VCO band selection is triggered
every time the ENBL pin is taken high. Once the band has been selected, the PLL will lock onto the correct frequency. During
the band selection process, fixed capacitance elements are progressively connected to the VCO resonant circuit until the VCO
is oscillating at approximately the correct frequency. The output of this band selection is made available in the RB1:CT_CAL
read-back register. A value of 127 or 0 in this register indicates that the selection was unsuccessful; this is usually due to the
wrong VCO being selected so the user is trying to program a frequency that is outside of the VCO operating range. A value
between one and 126 indicates a successful calibration, the actual value being dependent on the desired frequency, as well
as process variation. The band selection takes approximately 25s with a 21MHz clock. The band select process will center
the VCO tuning voltage at about 1.0V, compensating for manufacturing tolerances and process variation, as well as environ-
mental factors, including temperature. For applications where the synthesizer is always on and the LO frequency is fixed, the
synthesizer will maintain lock over the whole temperature range of -20°C to +75°C. However, it is recommended to re-initiate
an automatic band selection for every 30 degrees of temperature change in order to maintain optimal synthesizer perfor-
mance. This assumes an active loop filter. If start-up time is a critical parameter and the user is always programming the same
frequency for the PLL, the calibration result may be read back from the RB1:CT_CAL register and written to PLL1x2:P1_CT_DEF
or PLL2x2:P2_CT_DEF registers (depending on the desired PLL register bank). The calibration function must then be disabled
by setting the PLL1x0:P1_CT_EN and/or PLL2x0:P2_CT_EN control words to 0. For further information, please refer to the
RF205x Calibration User Guide.
The LO divide ratio is set by the PLL1x0:P1_LODIV and PLL2x0:P2_LODIV control words. The LO is routed to mixer1, mixer2, or
both, depending on the state of the MODE pin and the value of CFG1:FULLD.
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RF2054
VCO External Inductor Selection
The RF2054 VCO resonator circuit can be simplified to the schematic shown below:
L1
0.5nH
Pin 2
INDP
RF2054
VCO
L3
CORE
3.3nH
C1
2.5pF to 5.5pF
L2
0.5nH
L4
L5
3.3nH
Pin 3
INDN
Variable (coarse tune) capacitance plus varactor and stray capacitance.
Bondwire inductance of 0.5nH on each pin.
C1
L1 and L2
L3 and L4
L5
External inductors that form a differential inductor and provide a DC ground path to bias VCO.
Inductance of ground via (not part of differential inductor).
The following equation can be used to calculate the VCO frequency range:
1
Fo = ------------------
2 LC
where C is the total differential capacitance C1, 2.5pF to 5.5pF, and L is the total differential inductance:
L = L3 + L4 + 1nH = 7.6nH
For L3 and L4 of 3.3nH, this equation gives total VCO frequency range of about 800MHz to 1150MHz.
Some margin must be left at the top and bottom of the VCO frequency range to allow for process, assembly and environmental
variations. A CT_CAL margin of 25 bits is recommended at both the top and bottom, about 0.6pF of capacitance.
The VCO resonator will have the highest Q and lowest phase noise at the lower end of the coarse tuning curve. For applications
where the LO frequency is fixed, or only tunes over a few MHz, it is recommended to design for CT_CAL of about 40 using C1 =
4.7pF.
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RF2054
Fractional-N PLL
The RF2054 contains a charge-pump based fractional-N phase locked loop (PLL) for controlling the VCO. The PLL includes
automatic calibration systems to counteract the effects of process and environmental variations, ensuring repeatable lock
time and noise performance. The PLL is intended to use a reference frequency signal of 10MHz to 26MHz. The reference path
features a divider, but typically for best phase noise this is bypassed. The reference divider bypass is controlled by bit CLK
DIV_BYP, set low to enable the reference divider and set high for divider bypass (divide by 1). The remaining three bits CLK DIV
<15:13> set the reference divider value, divide by 2 (010) to 7 (111) when the reference divider is enabled.
Two PLL programming banks are provided, the first bank is preceded by the label PLL1, and the second bank is preceded by
the label PLL2. For the RF2054, these banks are used to program mixer 1 and mixer 2 respectively, and are selected automat-
ically as the mixer is selected (using the MODE pin).
The PLL will lock the VCO to the frequency FVCO according to:
FVCO = NEFF*FOSC/R
where NEFF is the programmed fractional-N divider value, FOSC is the reference input frequency, and R is the programmed R
divider value (1 to 7).
The N divider is a fractional divider, containing a dual-modulus prescaler and a digitally spur-compensated fractional sequence
generator to allow fine frequency steps. The N divider is programmed using the N and NUM bits as follows:
First determine the desired, effective N divider value, NEFF
:
NEFF = FVCO*R/FOSC
N(9:0) should be set to the integer part of NEFF. NUM should be set to the fractional part of NEFF multiplied by 224 = 16777216.
Example: VCO3 operating at 960MHz, 21MHz reference frequency, the desired effective divider value is:
NEFF = FVCO *R / FOSC = 960 *1 / 21 = 45.714285714285.
The N value is set to 45, equal to the integer part of NEFF, and the NUM value is set to the fractional portion of NEFF multiplied
by 224
:
NUM = 0.714285714285 * 224 = 11983726.
Converting N and NUM into binary results in the following:
N = 0001 0110 1
NUM = 1011 0110 1101 1011 0110 1110
So the registers would be programmed:
P1_N (or P2_N) = 0001 0110 1
P1_NUM_MSB (or P2_NUM_MSB) = 1011 0110 1101 1011
P1_NUM_LSB (or P2_NUM_LSB) = 0110 1110
The maximum NEFF is 511, and the minimum NEFF is 15, when in fractional mode.
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DS120320
RF2054
PLL Lock Detect
The lock detect function is a window detector, indicating an out of lock condition when the VCO tuning voltage is outside of a
certain voltage range. When out of lock then the LOCK bit will be high, bit 1 in the read back register RB1. It is possible that
when an out of lock is indicated the PLL is still locked, but the tuning voltage has drifted outside of the window.
There are two windows for the lock detector set by LD_LEV, bit 14 in register CFG1. The following are the typical tuning voltage
ranges for the lock detect circuit measured with +2.2V supply voltage to the RF2054:
LD_LEV = 0: 0.55V to 1.55V (narrow window)
LD_LEV = 1: 0.35V to 1.75V (wide window)
Phase Detector and Charge Pump
The chip provides a current output to drive an external loop filter. An on-chip operational amplifier can be used to design an
active loop filter or a passive design can be implemented. The maximum charge pump output current is set by the value con-
tained in the P1_CP_DEF/P2_CP_DEF field and CP_LO_I.
In the default state (P1_CP_DEF/P2_CP_DEF = 31 and CP_LO_I = 0) the charge pump current (ICPset) is 120A. If CP_LO_I is
set to 1 this current is reduced to 30A.
The charge pump current can be altered by changing the value of P1_CP_DEF/P2_CP_DEF. The charge pump current is
defined as:
ICP= ICPset*CP_DEF / 31
If automatic loop bandwidth correction is enabled the charge pump current is set by the calibration algorithm based upon the
VCO gain. For more information on the VCO gain calibration, which is disabled by default, please refer to the RF205x Calibra-
tion User Guide.
The phase detector will operate with a maximum input frequency of 26MHz.
Loop Filter
The PLL may be designed to use an active or a passive loop filter as required. The internal configuration of the chip is shown
below. If the CFG1:LF_ACT bit is asserted high, the op-amp will be enabled. If the CFG1:LF_ACT bit is asserted low, the internal
op-amp is disabled and a high impedance is presented to the LFILT1 pin. The RF205x Programming Tool software can assist
with loop filter designs. Because the op-amp is used in an inverting configuration in active mode, when the passive loop filter
mode is selected the phase-detector polarity should be inverted. For active mode, CFG1:PDP = 1, for passive mode, CFG1:PDP
= 0.
LF_ACT=TRUE
+1.1V
To VCO Tuning
+
-
LFILT1
LFILT2
LFILT3
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RF2054
The charge pump output voltage compliance range is typically +0.7V to +1.5V. For applications using a passive loop filter VCO
coarse tuning must be performed regularly enough to ensure that the VCO tuning voltage falls within this compliance range at
all temperatures. The active loop filter maintains the charge pump output voltage in the center of the compliance range, and
the op-amp provides a wider VCO tuning voltage range, typical 0V to +2.1V.
Reference Input
The RF2054 requires an external reference source. The external source (such as a TCXO) should be AC-coupled into one of the
XO inputs, and the other input should be AC-coupled to ground.
The bias circuits in the reference path (XO) take approximately 200sec to settle, and so for applications requiring rapid pulsed
operation of the PLL (such as a TDMA system, or Rx/Tx half-duplex system) it is necessary to keep the XO running between
bursts. However, when the PLL is used less frequently, it is desirable to turn off the XO to minimize current draw. The REFSTBY
register is provided to allow for either mode of operation. If REFSTBY is programmed high, the XO will continue to run even
when ENBL is asserted low. Thus the XO will be stable and a clock is immediately available when ENBL is asserted high, allow-
ing the chip to assume normal operation. On cold start, or if REFSTBY is programmed low, the XO will need a warm-up period
before it can provide a stable clock. It is recommended to program REFSTBY high at least 200 users before asserting ENBL
high.
Wideband Mixer
The RF2054 includes two wideband, double-balanced Gilbert cell mixers. Each mixer has an input port and an output port that
can be used for either IF or RF, i.e. for up conversion or down conversion. The mixer current can be programmed to between
5mA and 25mA in 5mA steps depending on linearity requirements, using the MIX1_IDD<3:0> word for mixer 1 and the
MIX2_IDD<3:0> word for mixer 2, both of which are in the CFG2 register. The majority of the mixer current is sourced through
the output pins via either a centre-tapped balun or an RF choke in the external matching circuitry to the supply. The RF2054
has been characterized for lowest current operation, so MIX1 _IDD and MIX2_IDD set to 001.
Mixer 1 of the RF2054 has been characterized for down conversion from approximately 2 GHz input to 1040MHz IF output.
Mixer 2 of the RF2054 has been characterized for upconversion from IF input of 1040MHz to approximately 2GHz output.
The RF mixer input and output ports are differential and require simple matching circuits optimized to the specific application
frequencies. A conversion gain of approximately -3dB is achieved with 100 differential input impedance, and the outputs
driving 200 differential load impedance. Increasing the mixer output load increases the conversion gain.
The mixer has a broadband common gate input. The input impedance is dominated by the resistance set by the mixer 1/gm
term, which is inversely proportional to the mixer current setting. The resistance will be approximately 135 at the mixer low
current setting (001). There is also some shunt capacitance at the mixer input.
The mixer output is high impedance, consisting of a resistance of approximately 2k in parallel with some capacitance. The
mixer output does not need to be matched as such, just to see a resistive load. A higher resistance load will give higher output
voltage and gain. A shunt inductor can be used to resonate with the mixer output capacitance at the frequency of interest. This
inductor may not be required at lower frequencies where the impedance of the output capacitance is less significant. For the
RF2054 mixer 1 IF output a 33nH inductor is used (1040MHz) and for the mixer 2 RF output a 8.2nH inductor is used (2GHz).
For more information about the mixer port impedances and matching, please refer to the RF205x Family Application Note on
Matching Circuits and Baluns.
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DS120320
RF2054
The mixer layout and pin placement has been optimized for high mixer-to-mixer isolation of over 60dB. The mixers can be set
up to operate in half-duplex mode (1 mixer active) or full duplex mode (both mixers active). The mode selection is done via
hardware control of the MODE pin and by setting the FULLD bit in the CFG1 register as shown in the table below. When in full-
duplex mode, one can either use PLL register bank 1 or 2, the LO signal is routed to both mixers.
Mode Pin
Low
FULLD Bit
Active PLL Register Bank
Active Mixer
0
0
1
1
1
2
1
2
1
High
2
Low
Both
Both
High
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RF2054
General Programming Information
Serial Interface
All on-chip registers in the RF2054 are programmed using a 3-wire serial bus which supports both write and read operations.
Synthesizer programming, device configuration and control are achieved through a mixture of hardware and software controls.
Certain functions and operations require the use of hardware controls via the ENBL, MODE, and RESETB pins in addition to
programming via the serial bus.
3‐wire bus
ENX
SCLK
SDATA
MCU
RF2054
ENBL
RESETB
MODE
Hardware
Controls
Serial Data Timing Characteristics
RESETB
ENX
t1
t3
t5
SCLK
SDATA
ENBL
t2
t6
t4
t7
t8
t9
X
X
X
X
X
X
X
X
Reset
chip
Initial programming of device
Programming
updates
Parameter
Description
Reset delay
Time
>5ns
>5ns
>5ns
>5ns
>5ns
>5ns
>5ns
>0ns
>0ns
t1
t2
t3
t4
t5
t6
t7
t8
t9
Programming setup time
Programming hold time
ENX setup time
ENX hold time
Data setup time
Data hold time
ENBL setup time
ENBL hold time
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DS120320
RF2054
Write
ENX
SCLK
X
A6
A5
A4
A3
A2
A1
A0
D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
SDATA
Initially ENX is high and SDATA is high impedance. The write operation begins with the controller starting SCLK. On the first fall-
ing edge of SCLK the baseband asserts ENX low. The second rising edge of SCLK is reserved to allow the SDI to initialize, and
the third rising edge is used to define whether the operation will be a write or a read operation. In write mode the baseband will
drive SDATA for the entire telegram. RF2054 will read the data bit on the rising edge of SCLK.
The next 7 data bits are the register address, MSB first. This is followed by the payload of 16 data bits for a total write mode
transfer of 24 bits. Data is latched into RF2054 on the last rising edge of SCLK (after ENX is asserted high).
For more information, please refer to the timing diagram on page 16.
The maximum clock speed for a register write is 19.2MHz. A register write therefore takes approximately 1.3s. The data is
latched on the rising edge of the clock. The datagram consists of a single start bit followed by a ‘0’ (to indicate a write opera-
tion). This is then followed by a seven bit address and a sixteen bit data word.
Note that since the serial bus does not require the presence of the reference clock, it is necessary to insert an additional rising
clock edge before the ENX line is set low to ensure the address/data are read correctly.
Read
ENX
SCLK
X
A6
A5
A4
A3
A2
A1
A0
D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
SDATA
Initially ENX is high and SDATA is high impedance. The read operation begins with the controller starting SCLK. The controller is
in control of the SDATA line during the address write operation. On the first falling edge of SCLK the baseband asserts ENX low.
The second rising edge of SCLK is reserved to allow the SDI to initialize, and the third rising edge is used to define whether the
operation will be a write or a read operation. In read mode the baseband will drive SDATA for the address portion of the tele-
gram, and then control will be handed over to RF2054 for the data portion. RF2054 will read the data bits of the address on
the rising edge of SCLK. After the address has been written, control of the SDATA line is handed over to RF2054. One and a half
clocks are reserved for turn-around, and then the data bits are presented by RF2054. The data is set up on the rising edge of
SCLK, and the controller latches the data on the falling edge of SCLK. At the end of the data transmission, RF2054 will release
control of the SDATA line, and the controller asserts ENX high. The SDATA port on RF2054 transitions from high impedance to
low impedance on the first rising edge of the data portion of the transaction (for example, 3 rising edges after the last address
bit has been read), so the controller chip should be presenting a high impedance by that time.
For more information, please refer to the timing diagram on page 16.
The maximum clock speed for a register read is 19.2MHz. A register read therefore takes approximately 1.4s. The address is
latched on the rising edge of the clock and the data output on the falling edge. The datagram consists of a single start bit fol-
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RF2054
lowed by a ‘1’ (to indicate a read operation), followed by a seven bit address. A 1.5 bit delay is introduced before the sixteen bit
data word representing the register content is presented to the receiver.
Note that since the serial bus does not require the presence of the reference clock, it is necessary to insert an additional rising
clock edge before the ENX line is set low to ensure the address is read correctly.
Hardware Control
Three hardware control pins are provided: ENBL, MODE, and RESETB.
ENBL Pin
The ENBL pin has two functions: to enable the analog circuits in the chip and to trigger the VCO band selection as described in
the VCO section on page 10.
ENBL Pin
Low
REFSTBY Bit
XO and Bias Block
Analogue Block
Digital Block
0
1
0
1
Off
On
On
On
Off
Off
On
On
On
On
On
On
Low
High
High
As outlined in the VCO section the chip has a built-in automatic VCO band selection to tune the selected VCO to the desired fre-
quency. The band selection is initiated when the ENBL pin is taken high. Every time the frequency of the synthesizer is re-pro-
grammed, the ENBL has to be inserted high to initiate the automatic VCO band selection (VCO coarse tune).
ENBL
t1
MODE
t2
Parameter
Description
MODE setup time
MODE hold time
Time
>5ns
>5ns
t1
t2
RESETB Pin
The RESETB pin is a hardware reset control that will reset all digital circuits to their start-up state when asserted low. The
device includes a power-on-reset function, so this pin should not normally be required, in which case it should be connected to
the positive supply.
MODE Pin
The MODE pin controls which mixer(s) and PLL programming register bank is active. See the PLL and Mixer description sec-
tions for details.
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DS120320
RF2054
Programming the RF2054
The figure below shows an overview of the device programming.
Device off
Apply power to the device.
Apply power
Reset device
Ensure the device is set into a known and correct
state.
1
2
3
4
Set-up device
operation
To use the device it will be necessary to program the
registers with the desired contents to achieve the
required operating characteristics.
Set calibration
mode
See following sections for details.
Set operating
frequencies
When programming is complete the device can be
enabled.
ENABLE device
Note: The set-up processes 1 to 2, 2 to 3, and 3 to 4 are explained further below.
Additional information on device use and programming can be found on the RF205X family page of the RFMD web site
(http://www.rfmd.com/rf205x). The following documents may be particularly helpful:
• RF205x Frequency Synthesizer User Guide
• RF205x Calibration User Guide
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RF2054
Start-up
When starting up and following device reset then REFSTBY=0, REFSTBY should be asserted high at least 200s before ENBL is
taken high. This is to allow the XO bias circuits to settle. The various calibration routines will also take some time depending on
whether they are enabled or not. Coarse tuning calibration takes about 50s and VCO tuning gain compensation takes about
100s. Additionally, time for the PLL to settle will be required. All of these timings will be dependant upon application specific
factors such as loop filter bandwidth, reference clock frequency, and so on. The fastest turn-on and lock time will be obtained
by leaving REFSTBY asserted high, disabling all calibration routines, minimizing all calibration times, and setting the PLL loop
bandwidth as wide as possible.
The device can be reset into its initial state (default settings) at any time by performing a hard reset. This is achieved by setting
the RESETB pin low for at least 100ns.
Setting Up Device Operation
The device offers a number of operating modes which need to be set up in the device before it will work as intended. This is
achieved as follows.
Set-up device
operation
1
When setting up the device it is necessary to decide if
an active or passive loop filter will be used in the
Disable active
loop filter?
LF_ACT
Set to 0
phase locked loop. The LF_ACT bit is located in the
CFG1 register and is active by default. Set the phase
detector polarity bit in CFG1since the active filter
inverts the loop filter voltage.
Yes
Yes
Default
The user must then activate the full duplex mode of
operation if fast frequency switching is required or it is
necessary to have both mixers operating
simultaneously. This bit is also located in the CFG1
register and is inactive by default.
Full duplex
operation?
FULLD
Set to 1
Default
The mixer linearity setting is then selected. The default
value is 4 with 1 being the lowest setting and 5 the
highest. The MIX1_IDD and MIX2_IDD bits are located
in the CFG2 register.
Mixer
linearity
Program
MIX1_IDD and
MIX2_IDD
Internal
capacitors
used to set
Xtal load
The internal crystal loading capacitors are also
programmed to present the correct load to the crystal.
The capacitance internal to the chip can be varied
from 8-16pF in 0.25pF steps (default=10pF). The
reference divider must also be set to determine the
phase detector frequency (default=1). These bits are
located in the CFG4 register.
Program XO_CT,
XO_CR_S and
CLK_DIV
Set-up complete
2
Three registers need to be written, taking 3.9s at the maximum clock speed. If the device is used with an active filter in sim-
plex operation it will not be necessary to program CFG1 reducing the programming time to 2.6s.
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DS120320
RF2054
Setting Up VCO Coarse Tuning and Loop Filter Calibration
If the user wishes to disable the VCO coarse tune calibration or enable the loop filter calibration then the following program-
ming operation will need to take place.
Set calibration
2
mode
When setting up the device it is necessary to decide
P1_CT_EN,
P2_CT_EN
Set to 00
whether to deactivate the devices' internal VCO
calibration or provide the calibration information
directly. These bits are located in the PLL1x0 and
PLL2x0 registers and are active by default.
Disable VCO
coarse tune?
Yes
Yes
Default
It is also necessary to decide whether to activate the
loop filter calibration mode, only necessary when
operating the device over very wide band of
frequencies. These bits are also located in the PLL1x0
and PLL2x0 registers. The default setting assumes an
active loop filter is used.
Enable loop filter
cal?
Loop filter
calibration
Default
Operating mode set
3
Two registers need to be written taking 2.6s at maximum clock speed if the course tuning is deactivated or the loop filter cal-
ibration activated. Since it is necessary to program these registers when setting the operating frequency (see next section) this
operation usually carries no overhead.
The coarse tune calibration takes approximately 26s when using a 21MHz reference clock (it will take proportionally longer if
a slower clock is used, and vice versa). This follows a VCO warm-up period also dependent on the reference clock, typically
10s to 15s.
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RF2054
Setting The Operating Frequency
Setting the operating frequency of the device requires a number of registers to be programmed.
Set operating
frequencies
3
Program
P1_VCOSEL,
P2_VCOSEL,
P1_LODIV,
When programming the operating frequency it is
necessary to select the appropriate VCO and LODIV
values. The P1_VCOSEL and P1_LODIV bits are
located in the PLL1x0 register and the corresponding
P2 bits in the PLL2x0 register. P1_VCOSEL and
P2_VCOSEL should always be set to 10 for VCO3.
FLL_Fact (CFG3) should be set to 00 if N<28.
P2_LODIV, and FLL
Fact
The integer part of the PLL division ratio is
programmed into the PLL1x3 and PLL2x3 registers
according to the required synthesizer path.
Program
P1_N, P2_N
Program
P1_NUM_MSB,
P2_NUM_MSB
The MSB of the fractional part of the synthesizer PLL
divider value is programmed into the PLL1x1 and
PLL2x1 registers.
The LSB of the fractional part of the synthesizer PLL
divider value is programmed into the PLL1x2 and
PLL2x2 registers together with the CT_CAL bits if fast
frequency switching is required.
(Depending on required frequency resolution and
coarse tune settings this may not be required.)
Program
P1_NUM_LSB,
P2_NUM_LSB,
P1_CT_DEF,
P2_CT_DEF
Frequency
programmed
4
A total of five registers must be programmed to set the device operating frequency for each path within the device. This will
take 6.5s for each path at maximum clock speed.
To change the frequency of the VCO it will be necessary to repeat these operations. However, it may not be necessary to repro-
gram the LODIV bits reducing the register writes to three per path.
For an example on how to determine the integer and fractional parts of the synthesizer PLL division ratio please refer to the
detailed description of the PLL.
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DS120320
RF2054
Programming Registers
Register Map Diagram
Data
Reg.
R/W
Add
Name
CFG1
CFG2
CFG3
CFG4
CFG5
CFG6
PLL1x0
15
14
13 12 11 10
TVCO
9
8
7
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
00
01
02
03
04
05
08
LD_EN LD_LEV
MIX1_IDD
TKV1
PDP LF_ACT
CPL
Res
Res
CT_POL Res EXT_VCO FULLD CP_LO_I
MIX1_VB MIX2_IDD
TKV2
MIX2_VB
KV_RNG NBR_CT_AVG NBR_KV_AVG
FLL_FACT CT_CPOLREFSTBY
CLK_DIV_BYPASS
LO1_I
XO_CT
XO_I2 XO_I1 XO_CR_S
TCT
T_PH_ALGN
Res
LO2_I
SU_WAIT
P1_VCOSEL P1_CT_E P1_KV_E P1_LODI
Res
P1_CP_DEF
N
N
V
PLL1x1
PLL1x2
PLL1x3
PLL1x4
PLL1x5
PLL2x0
R/W
R/W
R/W
R/W
R/W
R/W
09
0A
0B
0C
0D
10
P1_NUM_MSB
P1_NUM_LSB
P1_N
P1_CT_DEF
Res
Res
Res
P1_CT_GAIN
Res
P1_VCOI
P1_KV_GAIN
P1_CT_V
P2_CP_DEF
P1_DN
P1_N_PHS_ADJ
P2_VCOSEL P2_CT_E P2_KV__ P2_LODI
Res
N
EN
V
PLL2x1
PLL2x2
PLL2x3
PLL2x4
PLL2x5
GPO
R/W
R/W
R/W
R/W
R/W
R/W
11
12
13
14
15
18
P2_NUM_MSB
P2_NUM_LSB
P2_N
P2_CT_DEF
Res
Res
Res
P2_VCOI
P2_DN
P2_N_PHS_ADJ
P2_CT_GAIN
Res
P2_KV_GAIN
P2_CT_V
Res P1_GPO Res P1_ P1_
Res
P2_GP Res
O1
P2_GPO P2_
Res
1
GPO GPO
3
GPO
4
3
4
CHIPREV
RB1
R
R
R
R
R
19
1C
1D
1E
1F
PARTNO
REVNO
LOCK
TEN
CT_CAL
V0_CAL
RSM_STATE
TMUX
CP_CAL
Res
RB2
V1_CAL
Res
DACTEST
RB3
TEST
CPU CPD FNZ LDO TSEL Res
Res
_BY
P
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RF2054
CFG1 (OOh) - Operational Configuration Parameters
#
15
14
13
12
11
10
9
Bit Name
LD_EN
Default
Function
1
0
0
0
0
0
0
1
1
1
0
0
0
0
0
9
Enable lock detector circuitry
LD_LEV
Modify lock range for lock detector
TVCO(4:0)
VCO warm-up time = (TVCO*32)/F
REF
1
C
0
8
PDP
Phase detector polarity: 0 = positive, 1 = negative
Active loop filter enable, 1 = Active 0 = Passive
7
LF_ACT
CPL(1:0)
6
Charge pump leakage current: 00 = no leakage, 01 = low leakage, 10 = mid leakage, 11 =
high leakage
5
4
CT_POL
Polarity of VCO coarse-tune word: 0 = positive, 1 = negative
3
2
EXT_VCO
FULLD
0 = Normal operation 1 = external VCO
1
0 = Half duplex, mixer is enabled according to MODE pin, 1 = Full duplex, both mixers
enabled
0
CP_LO_I
0
0 = High charge pump current, 1 = low charge pump current
CFG2 (O1h) - Mixer Bias and PLL Calibration
#
15
14
13
12
11
10
9
Bit Name
MIX1_IDD
Default
Function
1
0
0
0
1
1
0
0
0
1
0
1
1
0
0
0
8
Mixer 1 current setting: 000 = 0mA to 101 = 25mA in 5mA steps. 110 and 111 unused.
RF2054 characterized with setting 001 for lowest current.
MIX1_VB
Mixer 1 voltage bias.
C
5
8
MIX2_IDD
Mixer 2 current setting: 000 = 0mA to 101 = 25mA in 5mA steps. 110 and 111 unused.
RF2054 characterized with setting 001 for lowest current.
8
7
MIX2_VB
Mixer 2 voltage bias
6
5
4
KV_RNG
Sets accuracy of voltage measurement during KV calibration: 0 = 8bits, 1 = 9bits
Number of averages during CT cal
3
NBR_CT_AVG
2
1
NBR_KV_AVG
Number of averages during KV cal
0
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DS120320
RF2054
CFG3 (O2h) - PLL Calibration
#
15
14
13
12
11
10
9
Bit Name
TKV1
Default
Function
0
0
0
0
0
1
0
0
0
0
0
0
0
1
0
0
0
Settling time for first measurement in LO KV compensation
TKV2
4
0
4
Settling time for second measurement in LO KV compensation
8
7
6
5
4
3
FLL_FACT
Default setting 01. Needs to be set to 00 for N<28.
2
1
CT_CPOL
REFSTBY
0
Reference oscillator standby mode 0=XO is off in standby mode, 1=XO is on in standby mode
CFG4 (O3h) - Crystal Oscillator and Reference Divider
#
15
14
13
12
11
10
9
Bit Name
CLK_DIV
Default
Function
0
0
0
1
1
0
0
0
0
0
0
0
1
1
1
1
1
Reference divider, divide by 2 (010) to 7 (111) when reference divider is enabled
CLK_DIV_BYPASS
XO_CT
Reference divider enabled = 0, divider bypass (divide by 1) = 1
8
0
F
Crystal oscillator coarse tune (approximately 0.5pF steps from 8pF to 16pF)
8
7
XO_I2
XO_I1
XO_CR_S
TCT
Crystal oscillator current setting
6
5
Crystal oscillator additional fixed capacitance (approximately 0.25pF)
Duration of coarse tune acquisition
4
3
2
1
0
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RF2054
CFG5 (O4h) - LO Bias
#
15
14
13
12
11
10
9
Bit Name
LO1_I
Default
Function
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
Local oscillator Path1 current setting
Local oscillator Path2 current setting
Phase alignment timer
LO2_I
0
0
4
8
7
T_PH_ALGN
6
5
4
3
2
1
0
CFG6 (O5h) - Start-up Timer
#
15
14
13
12
11
10
9
Bit Name
SU_WAIT
Default
Function
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
Crystal oscillator settling timer.
1
0
0
8
7
6
5
4
3
2
1
0
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DS120320
RF2054
PLL1x0 (08h) - VCO, LO Divider and Calibration Select
#
15
14
13
12
11
10
9
Bit Name
P1_VCOSEL
Default
Function
0
1
1
1
0
0
0
1
0
0
0
1
1
1
1
1
7
Always set to 10 = VCO3.
P1_CT_EN
P1_KV_EN
P1_LODIV
Path 1 VCO coarse tune: 00 = disabled, 11 = enabled
1
1
F
Path 1 VCO tuning gain calibration: 00 = disabled, 11 = enabled
Path 1 local oscillator divider: 00 = divide by 1, 01 = divide by 2, 10 = divide by 4, 11 =
reserved
8
7
6
5
P1_CP_DEF
Charge pump current setting
If P1_KV_EN = 11 this value sets charge pump current during KV compensation only
4
3
2
1
0
PLL1x1 (09h) - MSB of Fractional Divider Ratio
#
15
14
13
12
11
10
9
Bit Name
P1_NUM_MSB
Default
Function
0
1
1
0
0
0
1
0
0
1
1
1
0
1
1
0
6
Path 1 VCO divider numerator value, most significant 16 bits
2
7
6
8
7
6
5
4
3
2
1
0
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RF2054
PLL1x2 (0Ah) - LSB of Fractional Divider Ratio and CT Default
#
15
14
13
12
11
10
9
Bit Name
P1_NUM_LSB
Default
Function
0
0
1
0
0
1
1
1
0
1
1
1
1
1
1
0
2
Path 1 VCO divider numerator value, least significant 8 bits
7
7
E
8
7
P1_CT_DEF
Path 1 VCO coarse tuning value, used when P1_CT_EN = 00
6
5
4
3
2
1
0
PLL1x3 (0Bh) - Integer Divider Ratio and VCO Current
#
15
14
13
12
11
10
9
Bit Name
P1_N
Default
Function
0
0
1
0
0
0
1
1
0
0
0
0
0
0
1
0
2
Path 1 VCO divider integer value
3
0
2
8
7
6
5
4
3
2
P1_VCOI
Path 1 VCO bias setting: 000 = minimum value, 111 = maximum value. RF2054 character-
ized with 000.
1
0
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DS120320
RF2054
PLL1x4 (0Ch) - Calibration Settings
#
15
14
13
12
11
10
9
Bit Name
P1_DN
Default
Function
0
0
0
1
0
1
1
1
1
1
1
0
0
1
0
0
1
Path 1 frequency step size used in VCO tuning gain calibration
7
E
4
8
7
6
P1_CT_GAIN
P1_KV_GAIN
Path 1 coarse tuning calibration gain
Path 1 VCO tuning gain calibration gain
5
4
3
2
1
0
PLL1x5 (0Dh) - More Calibration Settings
#
15
14
13
12
11
10
9
Bit Name
P1_N_PHS_ADJ
Default
Function
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
Path 1 frequency step size used in VCO tuning gain calibration
0
1
0
8
7
6
5
4
P1_CT_V
Path 1 course tuning voltage setting when performing course tuning calibration. Default
value is 16.
3
2
1
0
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RF2054
PLL2x0 (10h) - VCO, LO Divider and Calibration Select
#
15
14
13
12
11
10
9
Bit Name
P2_VCOSEL
Default
Function
0
1
1
1
0
0
0
1
7
Always set to 10 = VCO3.
P2_CT_EN
P2_KV_EN
P2_LODIV
Path 2 VCO coarse tune: 00 = disabled, 11 = enabled
1
1
F
Path 2 VCO tuning gain calibration: 00 = disabled, 11 = enabled
Path 2 local oscillator divider: 00 = divide by 1, 01 = divide by 2, 10 = divide by 4, 11 =
reserved
8
7
6
5
P2_CP_DEF
0
1
1
1
1
1
Charge pump current setting.
If P2_KV_EN = 11 this value sets charge pump current during KV compensation only
4
3
2
1
0
PLL2x1 (11h) - MSB of Fractional Divider Ratio
#
15
14
13
12
11
10
9
Bit Name
P2_NUM_MSB
Default
Function
0
1
1
0
0
0
1
0
0
1
1
1
0
1
1
0
6
Path 2 VCO divider numerator value, most significant 16 bits
2
7
6
8
7
6
5
4
3
2
1
0
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DS120320
RF2054
PLL2x2 (12h) - LSB of Fractional Divider Ratio and CT Default
#
15
14
13
12
11
10
9
Bit Name
P2_NUM_LSB
Default
Function
0
0
1
0
0
1
1
1
0
1
1
1
1
1
1
0
2
Path 2 VCO divider numerator value, least significant 8 bits.
7
7
E
8
7
P2_CT_DEF
Path 2 VCO coarse tuning value, used when P2_CT_EN = 00
6
5
4
3
2
1
0
PLL2x3 (13h) - Integer Divider Ratio and VCO Current
#
15
14
13
12
11
10
9
Bit Name
P2_N
Default
Function
0
0
1
0
0
0
1
1
0
0
0
0
0
0
1
0
2
Path 2 VCO divider integer value
3
0
2
8
7
6
5
4
3
2
P2_VCOI
Path 2 VCO bias setting: 000 = minimum value, 111 = maximum value. RF2054 character-
ized with 000.
1
0
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RF2054
PLL2x4 (14h) - Calibration Settings
#
15
14
13
12
11
10
9
Bit Name
P2_DN
Default
Function
0
0
0
1
0
1
1
1
1
1
1
0
0
1
0
0
1
Path 2 frequency step size used in VCO tuning gain calibration
7
E
4
8
7
6
P2_CT_GAIN
P2_KV_GAIN
Path 2 coarse tuning calibration gain
Path 2 VCO tuning gain calibration gain
5
4
3
2
1
0
PLL2x5 (15h) - More Calibration Settings
#
15
14
13
12
11
10
9
Bit Name
P2_N_PHS_ADJ
Default
Function
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
Path 2 synthesizer phase adjustment
0
1
0
8
7
6
5
4
P2_CT_V
Path 2 course tuning voltage setting when performing course tuning calibration. Default
value is 16.
3
2
1
0
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32 of 39
DS120320
RF2054
GPO (18h) - Internal Control Output Settings
#
15
14
13
12
11
10
9
Bit Name
Default
Function
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
P1_GPO1
Setting of GPO1 when path 1 is active, used internally only
P1_GPO3
P1_GPO4
Setting of GPO3 when path 1 is active, used internally only
Setting of GPO4 when path 1 is active, used internally only
0
0
0
8
7
6
P2_GPO1
Setting of GPO1 when path 2 is active, used internally only
5
4
P2_GPO3
P2_GPO4
Setting of GPO3 when path 2 is active, used internally only
Setting of GPO4 when path 2 is active, used internally only
3
2
1
0
CHIPREV (19h) - Chip Revision Information
#
15
14
13
12
11
10
9
Bit Name
PARTNO
Default
Function
0
0
0
0
0
0
0
0
X
X
X
X
X
X
X
X
0
RFMD Part number for device
0
X
X
8
7
REVNO
Part revision number
6
5
4
3
2
1
0
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RF2054
RB1 (1Ch) - PLL Lock and Calibration Results Read-back
#
15
14
13
12
11
10
9
Bit Name
LOCK
Default
Function
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
0
X
PLL lock detector, 0 = PLL locked, 1 = PLL unlocked
CT_CAL
CT setting (either result of course tune calibration, or CT_DEF, depending on state of CT_EN).
Also depends on the MODE of the device
X
X
X
8
7
CP_CAL
CP setting (either result of KV cal, or CP_DEF, depending on state of KV_EN).
Also depends on the MODE of the device
6
5
4
3
2
1
0
RB2 (1Dh) - Calibration Results Read-Back
#
15
14
13
12
11
10
9
Bit Name
VO_CAL
Default
Function
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
The VCO voltage measured at the start of a VCO gain calibration
X
X
X
8
7
V1_CAL
The VCO voltage measured at the end of a VCO gain calibration
6
5
4
3
2
1
0
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DS120320
RF2054
RB3 (1Eh) - PLL state Read-Back
#
15
14
13
12
11
10
9
Bit Name
RSM_STATE
Default
Function
X
X
X
X
X
X
0
0
0
0
0
0
0
0
0
0
X
State of the radio state machine
X
0
0
8
7
6
5
4
3
2
1
0
TEST (1Fh) - Test Modes
#
15
14
13
12
11
10
9
Bit Name
TEN
Default
Function
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Enables test mode
TMUX
Sets test multiplexer state
CPU
0
0
0
Set charge pump to pump up, 0 = normal operation 1 = pump down
Set charge pump to pump down, 0 = normal operation 1 = pump down
0 = normal operation, 1 = fractional divider modulator disabled
On chip low drop out regulator bypassed
CPD
FNZ
8
LDO_BYP
TSEL
7
6
5
4
DACTEST
DAC test
3
2
1
0
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support, contact RFMD at (+1) 336-678-5570 or customerservice@rfmd.com.
DS120320
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RF2054
Evaluation Board Schematic
2
2
2
2
N C
N C
D
D
G N
N C
N C
2 5
2 6
2 7
2 8
2 9
3 0
3 1
3 2
3 3
1 6
1 5
P 2 N R F O
R F O P 2
T B S E R E
E N
S C L
T A S D A
R F I P 1 N
1 4
P
R F I P 1 P
1 3
G N
1 2
1 1
1 0
X
I P L N A T X
I P L P A T X
O D M E
K
9
2
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DS120320
RF2054
Evaluation Board Layout (RF2056)
Board Size 2.5” x 2.5”
Board Thickness 0.040”, Board Material FR-4
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support, contact RFMD at (+1) 336-678-5570 or customerservice@rfmd.com.
DS120320
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RF2054
Note: The RF2054 was evaluated and characterized on a standard RF2056 evaluation board, but with component changes as
defined in the schematic on page 36.
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support, contact RFMD at (+1) 336-678-5570 or customerservice@rfmd.com.
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DS120320
RF2054
Package Drawing
QFN, 32-Pin, 5mm x 5mm
0.85±0.10
0.1
C A B
M
1
3.70±0.10
0.1
C
1
SEE DETAIL ‘D’
5.00
0.25 Typ.
0.50 Typ.
0.35±0.05
32x
-B-
0.23±0.05
32x
0.1
C A B
M
5.000
-A-
See Detail ‘D’
Dimensions in mm.
Shaded area indicates pin 1.
0.1
C
0.85±0.10
0.08
-C-
C
SEATING
PLANE
0.00
0.05
Detail ‘D’
Rotated CW
Support and Applications Information
Application notes and support material can be downloaded from the product web page: www.rfmd.com/rf205x.
Ordering Information
Part Number
RF2054
RF2054SB
RF2054SR
RF2054TR7
RF2054TR13
Package
32-Pin QFN
32-Pin QFN
32-Pin QFN
32-Pin QFN
32-Pin QFN
Quantity
25-Piece sample bag
5-Piece sample bag
100-Piece reel
750-Piece reel
2500-Piece reel
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support, contact RFMD at (+1) 336-678-5570 or customerservice@rfmd.com.
DS120320
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