RF2705 [RFMD]
LOW NOISE, MULTI-MODE, QUAD-BAND, QUADRATURE MODULATOR AND PA DRIVER; 低噪音，多模四频，正交调制器和PA驱动器
| 型号： | RF2705 |
| 厂家： | 
RF MICRO DEVICES |
| 描述： | LOW NOISE, MULTI-MODE, QUAD-BAND, QUADRATURE MODULATOR AND PA DRIVER |
| 文件： | 总24页 (文件大小：379K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
RF2705
LOW NOISE, MULTI-MODE, QUAD-BAND,
QUADRATURE MODULATOR AND PA DRIVER
0
Typical Applications
• EDGE/GSM (GSM850/900) Handsets
• EDGE/GSM (DCS/PCS) Handsets
• W-CDMA Handsets/Data Cards
• W-CDMA/GSM/EDGE Multimode Handsets
and Data Cards
Product Description
-A-
1.00
0.80
4.00
-B-
The RF2705 is a low noise, multi-mode, quad-band direct
I/Q to RF modulator and PA driver designed for handset
applications where multiple modes of operation are
required. Frequency doublers, dividers and LO buffers
are included to support a variety of LO generation
options. Dynamic power control is supported through a
single analog input giving 90dB of power control range for
the W-CDMA mode and 40dB of power control in the
other two modes. Three sets of RF outputs are provided:
high band and low band low noise EDGE/GMSK outputs,
as well as one wideband W-CDMA output. The device is
designed for 2.7V to 3.3V operation, and is assembled in
a plastic, 24-pin, 4mmx4mm QFN.
0.10 C
4.00
0.10 C
0.10 C
0.10 C
-C-
+0.10
-0.10
2.45
SEATING
PLANE
Shaded lead is pin 1.
0.50 TYP
Dimensions in mm.
Scale: None
0.05
0.00
0.10 C
+0.10
-0.10
2.45
0.08 C
0.30
0.18
0.10 M C A B
0.50
TYP
0.30
TYP
Optimum Technology Matching® Applied
Package Style: QFN, 24-Pin, 4x4
Si BJT
GaAs HBT
SiGe HBT
GaN HEMT
GaAs MESFET
Si Bi-CMOS
InGaP/HBT
Si CMOS
Features
SiGe Bi-CMOS
9
• W-CDMA High/Mid/Low Power Modes
• Quad-Band Direct Quadrature Modulator
• Variable Gain PA Drivers
24
23
22
21
20
19
RF OUT
WB P
VCC2
1
2
18
17
16
15
14
13
• GMSK Bypass Amplifiers
Note: The die flag is the
chip's main ground.
RF OUT
WB N
LO HB P
• LO Frequency Doubler and Divider
• Baseband Filtering
DIV
2
+45°
-45°
RF OUT
HB P
LO HB N
3
Σ
RF OUT
HB N
+45°
-45°
Flo
x2
LO LB P
LO LB N
4
5
RF OUT
LB P
Ordering Information
Mode Control
and Biasing
Power
Control
RF2705
Low Noise, Multi-Mode, Quad-Band, Quadrature
Modulator and PA Driver
RF OUT
LB N
MODE C
6
RF2705PCBA-41XFully Assembled Evaluation Board
7
8
9
10
11
12
RF Micro Devices, Inc.
Tel (336) 664 1233
7628 Thorndike Road
Greensboro, NC 27409, USA
Fax (336) 664 0454
http://www.rfmd.com
Functional Block Diagram
Rev A4 041026
5-113
RF2705
Absolute Maximum Ratings
Parameter
Rating
Unit
V
°C
°C
V
dBm
Caution! ESD sensitive device.
Supply Voltage
-0.5 to 3.6
-40 to +150
-40 to +85
-0.5 to +3.6
+5
Storage Temperature
Operating Ambient Temperature
Input Voltage, any pin
Input Power, any pin
RF Micro Devices believes the furnished information is correct and accurate
at the time of this printing. However, RF Micro Devices reserves the right to
make changes to its products without notice. RF Micro Devices does not
assume responsibility for the use of the described product(s).
Specification
Typ.
Parameter
Unit
Condition
Min.
Max.
Output Performance with Modulated Baseband Inputs
Low Band EDGE 8PSK Mode (GSM850/GSM900)
Mode=Low Band F x1 (see Control Logic Truth Table for Mode Control Settings)
LO
V
=2.7V, T=+25°C
Output Power
CC
Maximum Output Power with
8PSK Modulated Signal*
Maximum VGC
Minimum VGC
Gain Range
0
+2.5
-39
42
dBm
dBm
dB
While meeting spectral mask
While meeting spectral mask
Difference between output power at
GC=2.0V and GC=0.2V.
-37
Out-of-Band Emission
Spectrum Emission Mask*
Frequency Spacing
200kHz
250kHz
400kHz
-36
-43
-67
-73
-73
-73
-75
TBD
TBD
TBD
dBc
dBc
dBc
dBc
dBc
dBc
dBc
30kHz BW
30kHz BW
30kHz BW
30kHz BW
100kHz BW
100kHz BW
100kHz BW
8PSK Modulation
600kHz to 1800kHz
1800kHz to 3000kHz
3000kHz to 6000kHz
>6000kHz
Error Vector Magnitude
RMS*
2
-40
4
3
-34
9
%
dB
%
Origin Offset*
Peak*
Output Noise
At F ±20MHz*
C
Relative Noise at:
Maximum Gain
-156
-152
dBc/Hz
dBc/Hz
GC=2.0V, IQ=1.2V
GC=2.0V to 1.4V
8PSK
P-P
Absolute Noise at:
Maximum Gain
-156
-154
dBm
dBm
GC=2.0V, IQ=0V
P-P
All Gain Settings
IQ=1.2V
8PSK
P-P
General Conditions
Local Oscillator
LO LB Input Frequency
RF LB Output Frequency
Input Power
824
824
-6.0
915
915
+3.0
MHz
MHz
dBm
0.0
1.2
IQ Baseband Inputs
8PSK
IQ Level
V
Input IQ signal driven differentially and in
quadrature.
P-P
IQ Common Mode
Input Bandwidth
Baseband Filter Attenuation
* Not tested in Production
1.2
1.0
V
MHz
dB
0.7
20
At 20MHz offset
5-114
Rev A4 041026
RF2705
Specification
Typ.
Parameter
Unit
Condition
Min.
Max.
Output Performance with Modulated Baseband Inputs
High Band EDGE 8PSK Mode (DCS1800/PCS1900)
Mode=High Band F x1 (see Control Logic Truth Table for Mode Control Settings)
LO
V
=2.7V, T=+25°C
Output Power
CC
Maximum Output Power with
8PSK Modulated Signal*
Maximum VGC
Minimum VGC
Gain Range
-1
+1.5
-40
42
dBm
dBm
dB
While meeting spectral mask
While meeting spectral mask
Difference between output power at
GC=2.0V and GC=0.2V.
-38
Out-of-Band Emission
Spectrum Emission Mask*
Frequency Spacing
200kHz
250kHz
400kHz
-36
-43
-67
-73
-73
-73
-75
TBD
TBD
TBD
dBc
dBc
dBc
dBc
dBc
dBc
dBc
30kHz BW
30kHz BW
30kHz BW
30kHz BW
100kHz BW
100kHz BW
100kHz BW
8PSK Modulation
600kHz to 1800kHz
1800kHz to 3000kHz
3000kHz to 6000kHz
>6000kHz
Error Vector Magnitude
RMS*
1.3
-37
3
3
-30
11
%
dB
%
Origin Offset*
Peak*
Output Noise
At F ±20MHz*
C
Relative Noise at:
Maximum Gain
-154
-150
dBc/Hz
dBc/Hz
GC=2.0V, IQ=1.2V
GC=2.0V to 1.4V
8PSK
P-P
Absolute Noise at:
Maximum Gain
-153
-151
dBm
dBm
GC=2.0V, IQ=0V
P-P
All Gain Settings
IQ=1.2V
8PSK
P-P
General Conditions
Local Oscillator
LO HB Input Frequency
RF HB Output Frequency
Input Power
1710
1710
-6.0
1910
1910
+3.0
MHz
MHz
dBm
0.0
1.2
IQ Baseband Inputs
8PSK
IQ Level
V
Input IQ signal driven differentially and in
quadrature.
P-P
IQ Common Mode
Input Bandwidth
Baseband Filter Attenuation
* Not tested in Production
1.2
1.0
V
MHz
dB
0.7
20
At 20MHz offset
Rev A4 041026
5-115
RF2705
Specification
Typ.
Parameter
Unit
Condition
Min.
Max.
Output Performance with Modulated Baseband Inputs
W-CDMA Mode
Mode=Wideband F x2 (see Control Logic Truth Table for Mode Control Settings)
LO
V
=2.7V, T=+25°C, while meeting 48dBc
CC
Output Power
ALCR
Maximum Output Power with
W-CDMA Modulated Signal*
High Power Mode
Medium Power Mode
3
-4
6
-1
dBm
dBm
GC=2.0V
GC=1.5V
Difference between output power at
GC=2.0V and GC=0.2V.
Gain Range
High Power Mode
90
dB
Gain step when switching between power
modes in either direction.
GC=1.4V
Gain Step
High Power to Medium Power
Medium Power to Low Power
Out-of-Band Emission
±0.5
TBD
dB
dB
GC=TBD
Adjacent Channel Leakage
Power Ratio (ALCR)*
Channel Spacing
±5MHz
50
65
dBc
dBc
3.84MHz relative to channel power
3.84MHz relative to channel power
±10MHz
Error Vector Magnitude
RMS*
1.4
%rms
3GPP W-CDMA
Output Noise
At F ±40MHz*
-152
-146
-146
dBc/Hz
dBc/Hz
GC=2.0V
C
GC=2.0V to 1.5V
General Conditions
Local Oscillator
LO LB Input Frequency
RF WB Output Frequency
Input Power
960
1920
-10.0
990
1980
+3.0
MHz
MHz
dBm
0.0
0.8
IQ Baseband Inputs
3GPP W-CDMA
HQPSK, 1DPCCH+1DPDCH
Input IQ signal driven differentially and in
quadrature.
IQ Level
V
P-P
IQ Common Mode
Input Bandwidth
Baseband Filter Attenuation
* Not tested in Production
1.2
11
V
MHz
dB
8
10
At 40MHz offset
5-116
Rev A4 041026
RF2705
Specification
Typ.
Parameter
Unit
Condition
Min.
Max.
Output Performance with CW Baseband Inputs
Wideband Mode
Mode=Wideband F x2 (see Control Logic Truth Table for Mode Control Settings)
LO
V
=2.7V, T=+25°C, LO=975MHz to
CC
990MHz at -10dBm, IQ=540mV ** at
VGA and PA Driver
P-P
100kHz, unless otherwise noted
Output Power W-CDMA Modu-
lated*
Output Power CW
Gain Control Voltage Range
Gain Control Range
5
5
dBm
GC=2.0V, IQ=0.8V
at HQPSK
P-P
2
0.2
8
2.0
dBm
V
dB
GC=2.0V
92
73
Difference between output power at
GC=2.0V and GC=0.2V
Calculated between GC=1.0V and 0.5V
Gain Control Slope
dB/V
Modulator
Sideband Suppression
-48
-50
-50
-50
-42
-41
-38
-23
-55
-30
-30
-30
-30
-30
-30
-30
-10
-50
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
GC=2.0V, No I/Q adjustment
GC=1.5V, No I/Q adjustment
GC=1.0V, No I/Q adjustment
GC=0.5V, No I/Q adjustment
GC=2.0V, No I/Q adjustment
GC=1.5V, No I/Q adjustment
GC=1.0V, No I/Q adjustment
GC=0.5V, No I/Q adjustment
GC=2.0V
*
*
*
Carrier Suppression
3rd Harmonic of Modulation
Suppression at F -3x300kHz
C
Spurious Outputs
Spurious Output at Integer Multi-
ples of FLO LB*
FLO LB
GC=2.0V, I/Q=540mV
at 100kHz
P-P
-60.0
-14.0
-47.0
dBm
dBm
dBm
FLO LB leakage
Second harmonic of carrier
Third harmonic of carrier
4xFLO LB
6xFLO LB
0
0
Output Compression
Output P1dB*
+11.5
+20
dBm
dBm
I/Q=100kHz
Intermodulation
Output IP3*
GC=2.0V. Extrapolated from IM3 with two
baseband tones at 90kHz and 110kHz
applied differentially, in quadrature, at both I
and Q inputs, each tone 400mV
.
P-P
Intermodulation IM3 tone at
-37
dBc
GC=2.0V
F +70kHz and F +130kHz
C
C
relative to tones at
F +90kHz and F +110kHz
C
C
-40
dBc
GC=1.5V
* Not tested in Production
** Provides the same output power as modulated signal with associated crest factor.
Rev A4 041026
5-117
RF2705
Specification
Typ.
Parameter
Unit
Condition
Min.
Max.
Output Performance with CW Baseband Inputs
Low Band Mode (GSM850/GSM900)
Mode=Low Band F x1 (see Control Logic Truth Table for Mode Control Settings)
LO
V
=2.7V, T=+25°C,
CC
LO=824MHz to 915MHz at 0dBm,
VGA and PA Driver
IQ=800mV ** at 100kHz,
P-P
unless otherwise noted
Output Power 8PSK Modulated*
Output Power CW
+2.5
2.2
dBm
dBm
dBm
dBm
dBm
dBm
GC=2.0V, IQ=1.2V
8PSK
P-P
0
+5
GC=2.0V, IQ=800mV
GC=1.5V, IQ=800mV
GC=1.0V, IQ=800mV
GC=0.5V, IQ=800mV
GC=0.2V, IQ=800mV
at 100kHz
P-P
P-P
P-P
P-P
P-P
-1.2
-13.5
-30
at 100kHz
at 100kHz
at 100kHz
at 100kHz
*
-44
0.2
-40
-37
2.0
Gain Control Voltage Range
Gain Control Range
V
dB
42
28
Difference between output power at
GC=2.0V and GC=0.2V
Calculated between GC=0.5V and 1.5V
Gain Control Slope
dB/V
Modulator
Sideband Suppression
-36
-36
-36
-36
-36
-44
-44
-44
-44
-40
-30
-30
-30
-30
-30
-34
-34
-34
-34
-34
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
GC=2.0V, No I/Q adjustment
GC=1.5V, No I/Q adjustment
GC=1.0V, No I/Q adjustment
GC=0.5V, No I/Q adjustment
GC=0.2V, No I/Q adjustment
GC=2.0V, No I/Q adjustment
GC=1.5V, No I/Q adjustment
GC=1.0V, No I/Q adjustment
GC=0.5V, No I/Q adjustment
GC=0.2V, No I/Q adjustment
*
*
*
*
Carrier Suppression
*
3rd Harmonic of Modulation
Suppression at F -3x300kHz
-49
-40
dBc
GC=2.0V
C
F
/2 Mode
Spurious Outputs
LO
Spurious Outputs at Integer
Harmonics of 1/2xFLOHB*
FLO HB
GC=2.0V, I/Q=800mV
at 100kHz
P-P
-62.0
-19.0
dBm
dBm
Second harmonic of carrier and LO leakage
Third harmonic of carrier
(3/2)xFLO LB
Output Compression
Output P1dB*
+7.0
dBm
I/Q=100kHz
* Not tested in Production
** Provides the same output power as modulated signal with associated crest factor.
5-118
Rev A4 041026
RF2705
Specification
Typ.
Parameter
Unit
Condition
Min.
Max.
Output Performance with CW Baseband Inputs
Low Band Mode (GSM850/GSM900), cont’d
Mode=Low Band F x1 (see Control Logic Truth Table for Mode Control Settings)
LO
Intermodulation
Output IP3*
+20.0
dBm
GC=2.0V. Extrapolated from IM3 with two
baseband tones at 90kHz and 110kHz
applied differentially, in quadrature, at both I
and Q inputs, each tone 400mV
.
P-P
Intermodulation IM3 tone at
F +70kHz and F +130kHz
C
C
relative to tones at
F +90kHz and F +110kHz
-48
dBc
GC=2.0V
C
C
Low Band Bypass Mode (GSM850/GSM900)
Mode=Low Band Bypass (see Control Logic Truth Table for Mode Control Settings)
V
=2.7V
PA Driver
CC
GMSK Input Power*
GMSK Output Power
Output Impedance*
-3
5.0
0
7.5
50
+3
10.0
dBm
dBm
Ω
At LO LB input from a 50Ω source.
At RF LB output
Output Noise
At F ±20MHz*
-161
-159
dBc/Hz
AM+PM noise, LO=0dBm
C
* Not tested in Production
Rev A4 041026
5-119
RF2705
Specification
Typ.
Parameter
Unit
Condition
Min.
Max.
Output Performance with CW Baseband Inputs
High Band Mode (DCS1800/PCS1900)
Mode=High Band F x1 (see Control Logic Truth Table for Mode Control Settings)
LO
V
=2.7V, T=+25°C,
CC
LO=1710MHz to 1910MHz at 0dBm,
VGA and PA Driver
IQ=800mV ** at 100kHz,
P-P
unless otherwise noted
Output Power 8PSK Modulated*
Output Power CW
0
0
2.2
2
dBm
dBm
dBm
dBm
dBm
dBm
GC=2.0V, IQ=1.2V
8PSK
P-P
+6.0
GC=2.0V, IQ=800mV
GC=1.5V, IQ=800mV
GC=1.0V, IQ=800mV
GC=0.5V, IQ=800mV
GC=0.2V, IQ=800mV
at 100kHz
P-P
P-P
P-P
P-P
P-P
-1.6
-17.6
-30
-40
at 100kHz
at 100kHz
at 100kHz
at 100kHz
*
-44
0.2
-37
2.0
Gain Control Voltage Range
Gain Control Range
V
dB
42
28
Difference between output power at
GC=2.0V and GC=0.2V
Calculated between GC=0.5V and 1.5V
Gain Control Slope
dB/V
Modulator
Sideband Suppression
-45
-45
-45
-45
-45
-40
-40
-40
-39
-37
-30
-30
-30
-30
-30
-34
-34
-33
-30
-30
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
GC=2.0V, No I/Q adjustment
GC=1.5V, No I/Q adjustment
GC=1.0V, No I/Q adjustment
GC=0.5V, No I/Q adjustment
GC=0.2V, No I/Q adjustment
GC=2.0V, No I/Q adjustment
GC=1.5V, No I/Q adjustment
GC=1.0V, No I/Q adjustment
GC=0.5V, No I/Q adjustment
GC=0.2V, No I/Q adjustment
*
*
*
*
Carrier Suppression
*
3rd Harmonic of Modulation
Suppression at F -3x300kHz
-50
-40
dBc
GC=2.0V
C
F
x2 Mode
Spurious Outputs
LO
Spurious Outputs at Integer
Harmonics of 1/2xFLOHB
FLO LB
GC=2.0V, I/Q=800mV
at 100kHz
P-P
-70.0
-25.0
-40.0
dBm
dBm
dBm
FLO LB leakage
Second harmonic of carrier
Third harmonic of carrier
4xFLO LB
6xFLO LB
Output Compression
Output P1dB*
+8.0
dBm
I/Q=100kHz
* Not tested in Production
** Provides the same output power as modulated signal with associated crest factor.
5-120
Rev A4 041026
RF2705
Specification
Typ.
Parameter
Unit
Condition
Min.
Max.
Output Performance with CW Baseband Inputs
High Band Mode (DCS1800/PCS1900), cont’d
Mode=High Band F x1 (see Control Logic Truth Table for Mode Control Settings)
LO
Intermodulation
Output IP3*
+20
dBm
dBc
GC=2.0V. Extrapolated from IM3 with two
baseband tones at 90kHz and 110kHz
applied differentially, in quadrature, at both I
and Q inputs, each tone 400mV
.
P-P
Intermodulation IM3 tone at
F +70kHz and F +130kHz
C
C
relative to tones at
F +90kHz and F +110kHz
-53
-42
GC=2.0V
C
C
Output Performance with CW Baseband Inputs
Wideband Mode
Mode=Wideband F x2 (see Control Logic Truth Table for Mode Control Settings)
LO
V
=2.7V, T=+25°C, LO=975MHz to
CC
990MHz at -10dBm, IQ=540mV ** at
VGA and PA Driver
P-P
100kHz, unless otherwise noted
Output Power W-CDMA Modu-
lated*
Output Power CW
Gain Control Voltage Range
Gain Control Range
5
5
dBm
GC=2.0V, IQ=0.8V
at HQPSK
P-P
2
0.2
8
2.0
dBm
V
dB
GC=2.0V
92
73
Difference between output power at
GC=2.0V and GC=0.2V
Calculated between GC=1.0V and 0.5V
Gain Control Slope
dB/V
Modulator
Sideband Suppression
-48
-50
-50
-50
-42
-41
-38
-23
-55
-30
-30
-30
-30
-30
-30
-30
-10
-50
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
GC=2.0V, No I/Q adjustment
GC=1.5V, No I/Q adjustment
GC=1.0V, No I/Q adjustment
GC=0.5V, No I/Q adjustment
GC=2.0V, No I/Q adjustment
GC=1.5V, No I/Q adjustment
GC=1.0V, No I/Q adjustment
GC=0.5V, No I/Q adjustment
GC=2.0V
*
*
*
Carrier Suppression
3rd Harmonic of Modulation
Suppression at F -3x300kHz
C
Spurious Outputs
Spurious Output at Integer Multi-
ples of FLO LB*
FLO LB
GC=2.0V, I/Q=540mV
at 100kHz
P-P
-60.0
-14.0
-47.0
dBm
dBm
dBm
FLO LB leakage
Second harmonic of carrier
Third harmonic of carrier
4xFLO LB
6xFLO LB
0
0
Output Compression
Output P1dB*
+11.5
+20
dBm
dBm
I/Q=100kHz
Intermodulation
Output IP3*
GC=2.0V. Extrapolated from IM3 with two
baseband tones at 90kHz and 110kHz
applied differentially, in quadrature, at both I
and Q inputs, each tone 400mV
.
P-P
Intermodulation IM3 tone at
-37
dBc
GC=2.0V
F +70kHz and F +130kHz
C
C
relative to tones at
F +90kHz and F +110kHz
C
C
-40
dBc
GC=1.5V
* Not tested in Production
** Provides the same output power as modulated signal with associated crest factor.
Rev A4 041026
5-121
RF2705
Specification
Typ.
Parameter
Unit
Condition
Min.
Max.
High Band Bypass Mode (DCS1800/PCS1900)
Mode=High Band Bypass (see Control Logic Truth Table for Mode Control Settings)
V
=2.7V
PA Driver
CC
GMSK Input Power*
GMSK Output Power
Output Impedance*
-3
4.0
0
6.8
50
+3
9.0
dBm
dBm
Ω
At LO LB input from a 50Ω source.
At RF LB output
Output Noise
At F ±20MHz*
-161
-159
dBc/Hz
AM+PM noise, LO=0dBm
C
* Not tested in Production
5-122
Rev A4 041026
RF2705
Specification
Typ.
Parameter
Unit
Condition
Min.
Max.
General Specifications
Operating Range
Supply Voltage
Temperature
2.7
-40
3.3
+85
V
°C
Refer to Logic Control Truth Table for Mode
Control Pin Voltages.
Current Consumption
Sleep
<1
10
µA
Wideband F x1 (high power)
114
mA
GC=2.0V
LO
*
85
89
54
63
42
mA
mA
mA
mA
mA
mA
GC=0.2V
GC=2.0V
GC=0.2V
GC=2.0V. See Note 1.
GC=0.2V. See Note 1.
GC=2.0V
(medium power)
*
(low power)
*
Wideband F x2 (high power)
110
LO
84
80
53
54
41
72
mA
mA
mA
mA
mA
mA
GC=0.2V
GC=2.0V
GC=0.2V
GC=2.0V. See Note 1.
GC=0.2V. See Note 1.
GC=2.0V
(medium power)
(low power)
High Band F x2
LO
Low Band F /2
82
mA
GC=2.0V
LO
High Band Bypass
Low Band Bypass
23
22
76
mA
mA
mA
High Band F x1
GC=2.0V
GC=2.0V
LO
Low Band F x1
74
mA
LO
Logic Levels
Input Logic 0
Input Logic 1
0
1.4
0.4
V
CC
V
V
Logic Pins Input Current
LO Input Ports
LO LB Input Frequency Range
LO HB Input Frequency Range
Input Impedance
<1.0
50
µA
CMOS inputs
800
1600
1000
2000
MHz
MHz
Ω
Externally matched
I/Q Baseband Inputs
Baseband Input Voltage
Baseband Input Level
1.15
1.25
1.0
V
Common mode voltage
EDGE
1.2
0.8
V
V
V
Differential
P-P
P-P
P-P
W-CDMA
GMSK
1DPCCH+1DPDCH. See Note 1.
Differential
Baseband Input Impedance
Input Bandwidth
100k||1pF
Ω
Measured at 100kHz
EDGE
W-CDMA
0.7
8.0
1.0
11.0
MHz
MHz
Baseband Filter Attenuation
EDGE
W-CDMA
Baseband Input DC Current
20
10
-10
dB
dB
µA
At 20MHz
At 40MHz
0
10
Gain Control
Gain Control Voltage
Gain Control Impedance
0.2
2.2
V
kΩ
10
Note 1: In low power mode it is recommended that the IQ level be reduced to 0.4V . If IQ level is >0.4V , this mode should be used
P-P
P-P
for W-CDMA TX power levels below -20dBm (measured at antenna).
Rev A4 041026
5-123
RF2705
Pin
Function Description
Interface Schematic
Supply for LO buffers, frequency doubler and dividers.
1
VCC2
VCC2
Modulator and
VGA
High band local oscillator input (1800MHz).
2
LO HB P
In “low band F /2” modes the signal (LOHBP-LOHBN) undergoes a
LO
frequency division of 2 to provide the low band LO signal for the modu-
lator.
VCC
In “high band F x1” modes the signal (LOHBP-LOHBN) is used as
LO
the high band LO signal for the modulator.
In “high band bypass” a modulated DCS1800/PCS1900 signal
(LOHBP-LOHBN) is switched into the RF signal path. The modulator
is disabled and the signal is routed to the RFOutHb outputs through a
differential PA driver amplifier.
The LOHBP input is AC-coupled internally.
LO HB P
LO HB N
The noise performance, carrier suppression at low output powers and
sideband suppression all vary with LO power. The optimum LO power
is between -3dBm and +3dBm. The device will work with LO powers as
low as -20dBm however this is at the expense of higher phase noise in
the LO circuitry and poorer sideband suppression.
The input impedance should be externally matched to 50Ω. The port
can be driven either differentially or single ended. The port impedance
does not vary significantly between active and power down modes.
The RF2705 is intended for use with the RF6002. This performs the
GSM GMSK modulation within a Frac-N synthesizer loop. The 8PSK
EDGE and W-CDMA signal modulations are performed in the RF2705
and uses the RF6002’s synthesizers to generate the LO signals. The
LO signal for EDGE900 mode is derived by frequency division by 2 of
the RF6002’s DCS1800 VCO. This helps protect the system against PA
pulling.
The complementary LO input for both LOHBP LO signals.
In any of the modes the LOHB input may be driven either single ended
or differentially. If the LO is driven single ended then the PCB board
designer can ground this pin.
See pin 2.
3
LO HB N
It is recommended that if this pin is grounded that it is kept isolated
from the GND1 pin and the die flag ground. All connections to any other
ground should be made through a ground plane. Poor routing of this
ground signal can significantly degrade the LO leakage performance.
5-124
Rev A4 041026
RF2705
Pin
4
Function Description
Interface Schematic
Low band local oscillator input (900MHz).
In “wideband F x2” and “high band F x2” modes the signal
LO LB P
LO
LO
(LOLBP-LOLBN) is doubled in frequency to provide the LO signal for
the modulator.
In “Low band F x1” modes the signal (LOLBP-LOLBN) is used as
the LO signal for the modulator.
LO
VCC
In “Low band Bypass” a modulated GSM900 signal (LOLBP-LOLBN)
is switched into the RF signal path. The modulator is disabled and the
signal is routed to the RFOutLb outputs through a differential PA driver
amplifier.
This LOLBP input is AC-coupled internally.
The noise performance, carrier suppression at low output powers and
sideband suppression performance are functions of LO power. The
optimum LO power is between -3dBm and +3dBm. The device will
work with LO powers as low as -20dBm however this is at the expense
of higher noise performance at high output powers and poorer side-
band suppression.
LO LB P
LO LB N
The input impedance should be externally matched to 50Ω. The port
impedance does not vary significantly between active and powered
modes.
The RF2705 is intended for use with the RF6002 which performs the
GSM GMSK modulation within a Frac-N synthesizer loop. The 8PSK
EDGE and W-CDMA signal modulations are performed in the RF2705
and uses the RF6002’s synthesizers to generate the LO signals. The
LO signal for DCS1800 mode is derived by frequency doubling
RF6002’s GSM900 VCO. This helps protect the system against PA pull-
ing.
The complementary LO input for both LOLBP LO signals.
In any of the modes the LOLB input may be driven either single ended
or differentially. If the LO is driven single ended then the PCB board
designer can ground this pin.
It is recommended that if this pin is grounded that it is kept isolated
from the GND1 pin and the die flag ground. All connections to any other
ground should be made through a ground plane. Poor routing of this
GndLO signal can significantly degrade the LO leakage performance.
See pin 4.
5
6
LO LB N
MODE C
Chip enable control pin. See the Logic Truth table.
VCC2
CMOS Logic inputs: Logic 0=0V to 0.4V; Logic 1=1.4V to V
.
CC
Mode control pin. See the Logic Truth table.
CMOS Logic inputs: Logic 0=0V to 0.4V; Logic 1=1.4V to V
See pin 6.
7
MODE D
.
CC
Rev A4 041026
5-125
RF2705
Pin
Function Description
Interface Schematic
Quadrature Q channel negative baseband input port.
Best performance is achieved when the QSIGP and QSIGN are driven
differentially with a 1.2V common mode DC voltage. The recom-
8
Q SIG N
mended differential drive level (V
-V
) is 1.2V
for EDGE,
QSIGP QSIGN
P-P
0.8V
for W-CDMA modulation and 1.0V
for GMSK modulation.
P-P
P-P
This input should be DC-biased at 1.2V. In sleep mode an internal FET
switch is opened, the input goes high impedance and the modulator is
de-biased.
VCC2
Phase or amplitude errors between the QSIGP and QSIGN signals will
result in a common-mode signal which may result in an increase in the
even order distortion of the modulation in the output spectrum.
DC offsets between the QSIGP and QSIGN signals will result in
increased carrier leakage. Small DC offsets may be deliberately
applied between the ISIGP/ISIGN and QSIGP/QSIGN inputs to can-
cel out the LO leakage. The optimum corrective DC offsets will change
with mode, frequency and gain control.
x1
Common-mode noise on the QSIGP and QSIGN should be kept low
as it may degrade the noise performance of the modulator.
Phase offsets from quadrature between the I and Q baseband signals
results in degraded sideband suppression.
Quadrature Q channel negative baseband input port. See pin 8.
See pin 8.
9
10
Q SIG P
VREF
Voltage reference decouple.
External 10nF decoupling capacitor to ground.
VCC2
The voltage on this pin is typically 1.67V when the chip is enabled. The
voltage is 0V when the chip is powered down.
4 kΩ
-
The purpose of this decoupling capacitor is to filter out low frequency
noise (20MHz) on the gain control lines.
+
Poor positioning of the VREF decoupling capacitor can cause a degra-
dation in LO leakage.
A voltage of around 2.5V on this pin indicates that the die flag under
the chip is not grounded and the chip is not biased correctly.
Gain control voltage decouple with an external 1nF decoupling capaci-
tor to ground.
11
GC DEC
VCC2
The voltage on this pin is a function of gain control (GC) voltage when
the chip is enabled. The voltage is 0V when the chip is powered down.
The purpose of this decoupling capacitor is to filter out low frequency
noise (20MHz) on the gain control lines. The size capacitor on the GC
DEC line will effect the settling time response to a step in gain control
voltage. A 1nF capacitor equates to around 200ns settling time and a
0.5nF capacitor equates to a 100ns settling time. There is a trade-off
between settling time and noise contributions by the gain control cir-
cuitry as gain control is applied.
4 kΩ
-
+
Poor positioning of the VREF decoupling capacitor can cause a degra-
dation in LO leakage.
Gain control voltage. Maximum output power at 2.0V. Minimum output
power at 0V. When the chip is enabled the input impedance is 10kΩ to
12
GC
VCC2
1.67V . When the chip is powered down a FET switch is opened and
DC
4 kΩ
the input goes high impedance.
10 kΩ
-
1.7 V
+
5-126
Rev A4 041026
RF2705
Pin
13
Function Description
Interface Schematic
Differential low band PA driver amplifier output.
RF OUT
LB N
VCC VCC
This output is intended for low band (GSM850/900) operation and
drives a differential SAW.
A bypass mode allows the low band PA driver amplifier’s input to be
switched between the signal from the modulator and the signal applied
at LOLB. This enables a GMSK-modulated signal on the LOLB input to
be switched into the RF signal path.
VCC
The output is an open collector. The outputs are matched off-chip.
RF OUT LB P
RF OUT LB N
Complementary differential low band PA driver amplifier output.
See pin 13.
See pin 13.
14
15
RF OUT
LB P
RF OUT
HB N
Differential high band PA Driver amplifier output.
VCC VCC
This output is intended for DCS1800/PCS1900 band operation.
A bypass mode allows the high band PA driver amplifier’s input to be
switched between the signal from the modulator and the signal applied
at LOHB. This enables a GMSK-modulated DCS1800/PCS1900 signal
on the LOHB input to be switched into the RF signal path.
The output is an open collector. The outputs are matched off-chip.
VCC
RF OUT HB P
RF OUT HB N
Complementary differential high band PA driver amplifier output.
See pin 15.
See pin 15.
16
17
RF OUT
HB P
RF OUT
WB N
Differential high band PA driver amplifier output.
This output is intended for wide band (W-CDMA) applications.
The output is an open collector. The output are matched off-chip.
VCC VCC
VCC
RF OUT WB P
RF OUT WB N
Complementary differential wideband PA driver amplifier output.
See pin 17.
See pin 17.
18
RF OUT
WB P
Ground.
19
20
GND
MODE A
Mode control pin. See the Logic Truth table.
CMOS Logic inputs: Logic 0=0V to 0.4V; Logic 1=1.4V to V
See pin 6.
.
CC
Supply for modulator, VGA and PA driver amplifiers.
21
VCC1
VCC1
LO Quadrature
Generator and
Buffers
GND1
Rev A4 041026
5-127
RF2705
Pin
Function Description
Interface Schematic
In-phase I channel positive baseband input port.
Best performance is achieved when the ISIGP and ISIGN are driven
differentially with a 1.2V common mode DC voltage. The recom-
22
I SIG P
mended differential drive level (V
-V
) is 1.2V
for EDGE,
ISIGP ISIGN
P-P
0.8V
W-CDMA modulation and 1.0V
for GMSK modulation.
P-P
P-P
This input should be DC-biased at 1.2V. In sleep mode an internal FET
switch is opened, the input goes high impedance and the modulator is
de-biased.
VCC2
Phase or amplitude errors between the ISIGP and ISIGN signals will
result in a common-mode signal which may result in an increase in the
even order distortion of the modulation in the output spectrum.
DC offsets between the ISIGP and ISIGN signals will result in
increased carrier leakage. Small DC offsets may be deliberately
applied between the ISIGP/ISIGN and QSIGP/QSIGN inputs to can-
cel out the LO leakage. The optimum corrective DC offsets will change
with mode, frequency and gain control.
x1
Common-mode noise on the ISIGP and ISIGN should be kept low as it
may degrade the noise performance of the modulator.
Phase offsets from quadrature between the I and Q baseband signals
results in degrades sideband suppression.
In-phase I channel negative baseband input port. See pin 22.
See pin 22.
See pin 6.
23
24
I SIG N
MODE B
Mode control pin. See the Logic Truth table.
CMOS Logic inputs: Logic 0=0V to 0.4V; Logic 1=1.4V to V
.
CC
Ground for LO section, modular, biasing, variable gain amplifier, and
substrate.
Pkg
Base
DIE FLAG
5-128
Rev A4 041026
RF2705
LO Frequency Planning Options for European 3GPP W-CDMA/EDGE
Recommended Frequency Plan: Frequency Doubler/Divide by 2/GMSK Modulator Bypass Modes
Modulation
Format
Output Frequency Band
LO Port
LO Frequency Range
Lower Limit Upper Limit
Comments
Band
Lower Limit Upper Limit
GSM850
GSM850
GSM900
GSM900
DCS1800
DCS1800
PCS1900
PCS1900
824MHz
824MHz
880MHz
880MHz
1710MHz
1710MHz
1850MHz
1850MHz
849MHz
849MHz
915MHz
915MHz
1785MHz
1785MHz
1910MHz
1910MHz
EDGE 8PSK
GSM GMSK
EDGE 8PSK
GSM GMSK
EDGE 8PSK
GSM GMSK
EDGE 8PSK
GSM GMSK
LOHB
LOLB
LOHB
LOLB
LOLB
LOHB
LOLB
LOHB
LOLB
1648MHz
824MHz
1760MHz
880MHz
855MHz
1710MHz
925MHz
1850MHz
960MHz
1698MHz
849MHz
1830MHz
915MHz
892.5MHz
1785MHz
955MHz
1910MHz
990MHz
F
/2
LO
Divide by 2
_bypass Bypass,
F
LO
GMSK-modulated LO
/2
F
LO
Divide by 2
_bypass Bypass,
F
LO
GMSK-modulated LO
x2
F
LO
Frequency Doubler
_bypass Bypass,
F
LO
GMSK-modulated LO
x2
F
LO
Frequency Doubler
_bypass Bypass,
F
LO
GMSK-modulated LO
F x2
LO
W-CDMA1950 1920MHz
1980MHz 3GPP W-CDMA
Frequency Doubler
On Frequency LO with GMSK Modulator Bypass Modes
Modulation
Output Frequency Band
Format
LO Port
LO Frequency Range
Lower Limit Upper Limit
Comments
Band
Lower Limit Upper Limit
GSM850
824MHz
824MHz
880MHz
880MHz
1710MHz
1710MHz
1850MHz
1850MHz
849MHz
849MHz
915MHz
915MHz
1785MHz
1785MHz
1910MHz
1910MHz
EDGE 8PSK
GSM GMSK
EDGE 8PSK
GSM GMSK
EDGE 8PSK
GSM GMSK
EDGE 8PSK
GSM GMSK
LOLB
LOLB
LOLB
LOLB
LOHB
LOHB
LOHB
LOHB
LOHB
824MHz
824MHz
880MHz
880MHz
1710MHz
1710MHz
1850MHz
1850MHz
1920MHz
849MHz
849MHz
915MHz
915MHz
1785MHz
1785MHz
1910MHz
1910MHz
1980MHz
F
x1
LO
On Frequency
F _bypass Bypass,
LO
GSM850
GSM900
GSM900
DCS1800
DCS1800
PCS1900
PCS1900
GMSK-modulated LO
x1
F
LO
On Frequency
_bypass Bypass,
F
LO
GMSK-modulated LO
x1
F
LO
On Frequency
_bypass Bypass,
F
LO
GMSK-modulated LO
x1
F
LO
On Frequency
_bypass Bypass,
F
LO
GMSK-modulated LO
x1
W-CDMA1950 1920MHz
1980MHz 3GPP W-CDMA
F
LO
On Frequency
Rev A4 041026
5-129
RF2705
Control Logic Truth Table
ActiveRF
I/Os
Input Logic
Comment
Mode Description
Expected Mode of
Operation
Mode A Mode B Mode C Mode D
Sleep Mode
X
0
0
0
Sleep
Sleep
Frequency Doubler/Divide by 2 Options
Wideband F x2 (High Power)
1
1
1
1
1
0
0
0
1
1
1
1
0
1
0
0
1
1
1
1
LoLbP LoLbN Bands: 1920MHz to 1980MHz
RFOutWb P Modulation: 3GPP W-CDMA
RFOutWb N
LO
Modulator and frequency doubler
enabled
Wideband F x2 (Medium Power)
LoLbP LoLbN Bands: 1920MHz to 1980MHz
RFOutWb P Modulation: 3GPP W-CDMA
RFOutWb N
LO
Modulator and frequency doubler
enabled
Wideband F x2 (Low Power)
LoLbP LoLbN Bands: 1920MHz to 1980MHz
RFOutWb P Modulation: 3GPP W-CDMA
RFOutWb N
LO
Modulator and frequency doubler
enabled
High Band F x2
LoLbP LoLbN Bands: DCS1800 or PCS1900
RFOutHb P Modulation: GMSK, TDMA and
LO
Modulator and frequency doubler
enabled
RFOutHb N
8PSK EDGE
Low Band F /2
LoHbP LoHbN Bands: GSM900 or GSM850
RFOutLb P Modulation: GMSK, TDMA and
LO
Modulator and divide by 2 enabled
RFOutLb N
8PSK EDGE
GMSK Modulator Bypass Options
Low Band Bypass
X
X
1
0
0
LoLbP LoLbN Bands: GSM850 or GSM900
RFOutLb P Modulation: GMSK
RFOutLb N
LoHbP LoHbN Bands: DCS1800 or PCS1900
RFOutHb P Modulation: GMSK
RFOutHb N
Modulator bypass enabled
High Band Bypass
1
1
0
Modulator bypass enabled
On-Frequency LO Options
Wideband F x1 (High Power)
0
0
0
0
0
0
0
0
1
1
1
1
0
1
0
0
1
1
1
1
LoHbP LoHbN Bands: 1920MHz to 1980MHz
RFOutWb P Modulation: 3GPP W-CDMA
RFOutWb N
LO
Modulator and on-frequency LO
enabled
Wideband F x1 (Medium Power)
LoHbP LoHbN Bands: 1920MHz to 1980MHz
RFOutWb P Modulation: 3GPP W-CDMA
RFOutWb N
LO
Modulator and on-frequency LO
enabled
Wideband F x1 (Low Power)
LoHbP LoHbN Bands: 1920MHz to 1980MHz
RFOutWb P Modulation: 3GPP W-CDMA
RFOutWb N
LO
Modulator and on-frequency LO
enabled
High Band F x1
LoHbP LoHbN Bands: DCS1800 or PCS1900
RFOutHb P Modulation: GMSK, TDMA and
LO
Modulator and on-frequency LO
enabled
RFOutHb N
8PSK EDGE
Low Band F x1
LoLbP LoLbN Bands: GSM900 to GSM850
RFOutLb P Modulation: GMSK, TDMA and
LO
Modulator and on-frequency LO
enabled
RFOutLb N
8PSK EDGE
5-130
Rev A4 041026
RF2705
Application Information
The baseband inputs of the RF2705 must be driven with balanced signals. Amplitude and phase matching <0.5dB and
<0.5 degrees are recommended. Phase or gain imbalances between the complementary input signals will cause addi-
tional distortion including some second order baseband distortion.
The RF2705 is designed to be driven with either single-ended or differential LO signals. Driving the chip differentially is
beneficial in improving the LO leakage performance. Decreasing the LO drive level will also improve LO leakage, but the
output noise performance will be degraded. Driving the LO level too high will degrade linearity.
The ground lines for the LO sections are brought out of the chip independently from the ground to the RF and modulator
sections. This is intended to give the board design the independence of isolating the LO signals from the RF output sec-
tions.
The RF2705 includes frequency doubler and divider modes that allow the LO to operate at half or twice the frequency
depending on the application. This provides some flexibility in improving VCO isolation and LO leakage through fre-
quency translation.
The RF outputs use open collector architecture and may be biased at voltages higher than VCC. In practice, biasing at a
higher voltage may improve the intermodulation performance. The load resistors are selected to provide sufficient output
power while maintaining good linearity.
The GC DEC and VREF output pins should be decoupled to ground. A 10nF capacitor on VREF and a 1nF capacitor on
GC CEC are recommended. The purpose of these capacitors is to filter out low frequency noise (20MHz) in the gain
control lines that may cause noise on the RF signal. The capacitor on the GC DEC line will effect the settling time of the
step response in power control voltage. A 1nF capacitor equates to around a 200ns settling time; a 0.5nF capacitor
equates to a 100ns settling time. There is a trade-off between setting time and phase noise as gain control is applied.
As with any RF circuit, the RF2705 is sensitive to PC board layout. The suggested schematic and board layout is
included as a guideline. Proper grounding of the die flag under the chip is essential in achieving acceptable RF perfor-
mance. A symmetric output structure will maintain signal balance while keeping the RF lines short will reduce losses.
Proper routing and bypassing of the supply lines will improve stability and performance, especially under low gain control
settings where carrier suppression becomes crucial. The location and value of the bypass capacitor on pin 1 is critical in
promoting good carrier suppression and is designated to resonate out the series wire bond and PC board inductance.
Rev A4 041026
5-131
RF2705
Application Schematic
VCC
MODE A
VCC
2.2 nH
4.3 pF
T1
RF OUT WB
I SIG P
1 kΩ
1 pF
4.3 pF
2.2 nH
I SIG N
1 nF
MODE B
2:1
VCC
VCC
5.6 pF
24
23
22
21
20
19
VCC
1
2
3
18
17
16
15
14
13
3.9 nH
1.8 pF
Note: The die flag is the
chip's main ground.
LO HB
430 Ω
4.3 nH
T2
RF OUT HB
1.6 pF
1.6 pF
+45°
-45°
DIV
2
Σ
2:1
22.0 nH
3 pF
LO LB
430 Ω
4.3 nH
VCC
VCC
+45°
-45°
Flo
x2
4
Mode Control
and Biasing
Power
Control
5
6
12 nH
1 kΩ
3.3 pF
3.3 pF
MODE C
T3
RF OUT LB
7
8
9
10
11
12
0.5 pF
MODE D
Q SIG N
Q SIG P
2:1
10 nF
1 nF
12 nH
VCC
GC
5-132
Rev A4 041026
RF2705
Evaluation Board Schematic
VCC
MODE A
VCC
C7
12 pF
J2
I SIG P
50 Ω µstrip
J4
50 Ω µstrip
50 Ω µstrip
WB RF OUT
J1
I SIG N
L2
2.2 nH
L3
2.2 nH
C12
1.3 pF
T1
C1
1 nF
Murata
LDB211G9020C-001
MODE B
C2
4.3 pF
C3
4.3 pF
R1
1 kΩ
C6
5.6 pF
24
23
22
21
20
19
VCC
1
2
3
18
17
16
15
14
13
C11
22 pF
Note: The die flag is the
chip's main ground.
50 Ω µstrip
L1
3.9 nH
J5
HB RF OUT
J3
HB LO
50 Ω µstrip
50 Ω µstrip
C4
1.8 pF
R2
430 Ω
L4
4.3 nH
L5
4.3 nH
C5
DNI
T2
Murata
DIV
2
+45°
-45°
LDB211G8020C-001
C9
1.6 pF
R3
430 Ω
C10
1.6 pF
Σ
L6
22 nH
J6
LB LO
+45°
-45°
Flo
x2
4
C13
3 pF
VCC
Mode Control
and Biasing
Power
Control
5
6
C8
100 pF
50 Ω µstrip
J7
LB RF OUT
MODE C
MODE D
7
8
9
10
11
12
L7
12 nH
L8
12 nH
C18
0.5 pF
T3
Murata
LDB21906M20C-001
C14
10 nF
C15
1 nF
50 Ω µstrip
50 Ω µstrip
J8
Q SIG N
C17
3.3 pF
C16
3.3 pF
R4
1 kΩ
J9
Q SIG P
P2
1
P1
GC
1
2
3
P2-1
VCC
MODE D
MODE C
MODE B
MODE A
P1-1
P2-2
GND
2
P2-3
GC
P1-3
3
P2-4
4
CON3
CON4
Rev A4 041026
5-133
RF2705
Evaluation Board Layout
Board Size 2.250” x 2.250”
Board Thickness 0.032”, Board Material FR-4, Multi-Layer
Assembly
Top
Mid
Back
5-134
Rev A4 041026
RF2705
PCB Design Requirements
PCB Surface Finish
The PCB surface finish used for RFMD’s qualification process is Electroless Nickel, immersion Gold. Typical thickness is
3µinch to 8µinch Gold over 180µinch Nickel.
PCB Land Pattern Recommendation
PCB land patterns are based on IPC-SM-782 standards when possible. The pad pattern shown has been developed and
tested for optimized assembly at RFMD; however, it may require some modifications to address company specific
assembly processes. The PCB land pattern has been developed to accommodate lead and package tolerances.
PCB Metal Land Pattern
A = 0.69 x 0.28 (mm) Typ.
B = 0.28 x 0.69 (mm) Typ.
C = 2.50 (mm) Sq.
2.50 (mm)
Typ.
0.50 (mm) Typ.
Pin 24
B
B
B
B
B
B
Pin 18
Pin 1
A
A
A
A
A
A
A
A
A
A
A
A
0.50 (mm) Typ.
1.25 (mm)
Typ.
2.50 (mm)
Typ.
C
0.57 (mm) Typ.
0.57 (mm) Typ.
B
B
B
B
B
B
Pin 12
1.25 (mm)
Typ.
Figure 1. PCB Metal Land Pattern (Top View)
Rev A4 041026
5-135
RF2705
PCB Solder Mask Pattern
Liquid Photo-Imageable (LPI) solder mask is recommended. The solder mask footprint will match what is shown for the
PCB Metal Land Pattern with a 2mil to 3mil expansion to accommodate solder mask registration clearance around all
pads. The center-grounding pad shall also have a solder mask clearance. Expansion of the pads to create solder mask
clearance can be provided in the master data or requested from the PCB fabrication supplier.
A = 0.79 x 0.38 (mm) Typ.
B = 0.38 x 0.79 (mm) Typ.
C = 2.60 (mm) Sq.
2.50 (mm)
Typ.
0.50 (mm) Typ.
Pin 24
B
B
B
B
B
B
Pin 18
Pin 1
A
A
A
A
A
A
A
A
A
A
A
A
0.50 (mm) Typ.
1.25 (mm)
Typ.
2.50 (mm)
Typ.
C
0.57 (mm) Typ.
0.57 (mm) Typ.
B
B
B
B
B
B
Pin 12
1.25 (mm)
Typ.
Figure 2. PCB Solder Mask Pattern (Top View)
Thermal Pad and Via Design
The PCB land pattern has been designed with a thermal pad that matches the exposed die paddle size on the bottom of
the device.
Thermal vias are required in the PCB layout to effectively conduct heat away from the package. The via pattern shown
has been designed to address thermal, power dissipation and electrical requirements of the device as well as accommo-
dating routing strategies.
The via pattern used for the RFMD qualification is based on thru-hole vias with 0.203mm to 0.330mm finished hole size
on a 0.5mm to 1.2mm grid pattern with 0.025mm plating on via walls. If micro vias are used in a design, it is suggested
that the quantity of vias be increased by a 4:1 ratio to achieve similar results.
5-136
Rev A4 041026
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