RFFC5062SQ [RFMD]
WIDEBAND SYNTHESIZER/VCO WITH INTEGRATED 6GHz MIXER;
| 型号： | RFFC5062SQ |
| 厂家： | 
RF MICRO DEVICES |
| 描述： | WIDEBAND SYNTHESIZER/VCO WITH INTEGRATED 6GHz MIXER |
| 文件： | 总25页 (文件大小：4260K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
RFFC5061/62
Wideband Syn-
thesizer/VCO
withIntegrated
6GHz Mixer
RFFC5061/62
WIDEBAND SYNTHESIZER/VCO WITH
INTEGRATED 6GHz MIXER
Package: QFN, 32-Pin, 5mmx5mm
RFFC5061
RFFC5062
Features
85MHz to 4200MHz LO
Frequency Range
Phase
det.
Phase
det.
Fractional-N Synthesizer with
Very Low Spurious Levels
Synth
Synth
Typical Step Size 1.5Hz
Ref.
divider
Ref.
divider
On-Chip Crystal-Sustaining
Circuit with Programmable
Loading Capacitors
Fully Integrated Low Phase Noise
VCO and LO Buffers
Integrated Phase Noise
• Typ. 0.3° rms at 1 GHz
• Typ. 0.8° rms at 3GHz
Functional Block Diagram
High Linearity RF Mixer(s)
Product Description
30MHz to 6000MHz Mixer
Frequency Range
The RFFC5061 and RFFC5062 are re-configurable frequency conversion devices
with integrated fractional-N phased locked loop (PLL) synthesizer, voltage con-
trolled oscillator (VCO) and either one or two high linearity mixers. The fractional-N
synthesizer takes advantage of an advanced sigma-delta modulator that delivers
ultra-fine step sizes and low spurious products. The RFFC5061 and RFFC5062
have been designed to use an external crystal, typically 26MHz, and have inte-
grated programmable loading capacitors. The PLL/VCO engine combined with an
external loop filter allows the user to generate local oscillator (LO) signals from
85MHz to 4200MHz. The LO signal is buffered and routed to the integrated RF mix-
ers which are used to up/down-convert frequencies ranging from 30MHz to
6000MHz. The mixer bias current is programmable and can be reduced for applica-
tions requiring lower power consumption. Both devices can be configured to work
as signal sources by bypassing the integrated mixers. Device programming is
achieved via a simple 3-wire serial interface. In addition, a unique programming
mode allows up to four devices to be controlled from a common serial bus. This
eliminates the need for separate chip-select control lines between each device and
the host controller. Up to six general purpose outputs are provided, which can be
used to access internal signals (e.g. the LOCK signal) or to control front end compo-
nents. Both devices operate with a 2.7V to 3.3V power supply.
Input IP3 +23dBm
Mixer Bias Adjustable for Low
Power Operation
Full Duplex Mode (RFFC5061)
2.7V to 3.3V Power Supply
Low Current Consumption
3- or 4-Wire Serial Interface
Applications
Frequency Band Shifters
Wideband Radios
Diversity Receivers
Software Defined Radios
Optimum Technology Matching® Applied
GaAs HBT
GaAs MESFET
InGaP HBT
SiGe BiCMOS
Si BiCMOS
SiGe HBT
GaAs pHEMT
Si CMOS
Si BJT
GaN HEMT
BiFET HBT
LDMOS
RF MICRO DEVICES®, RFMD®, Optimum Technology Matching®, Enabling Wireless Connectivity™, PowerStar®, POLARIS™ TOTAL RADIO™ and UltimateBlue™ are trademarks of RFMD, LLC. BLUETOOTH is a trade-
mark owned by Bluetooth SIG, Inc., U.S.A. and licensed for use by RFMD. All other trade names, trademarks and registered trademarks are the property of their respective owners. ©2010, RF Micro Devices, Inc.
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Absolute Maximum Ratings
Parameter
Caution! ESD sensitive device.
Rating
-0.5 to +3.6
Unit
V
Exceeding any one or a combination of the Absolute Maximum Rating conditions may
cause permanent damage to the device. Extended application of Absolute Maximum
Rating conditions to the device may reduce device reliability. Specified typical perfor-
mance or functional operation of the device under Absolute Maximum Rating condi-
tions is not implied.
Supply Voltage (V
)
DD
Input Voltage (V ) any pin
-0.3 to V +0.3
DD
V
IN
The information in this publication is believed to be accurate and reliable. However, no
responsibility is assumed by RF Micro Devices, Inc. ("RFMD") for its use, nor for any
infringement of patents, or other rights of third parties, resulting from its use. No
license is granted by implication or otherwise under any patent or patent rights of
RFMD. RFMD reserves the right to change component circuitry, recommended appli-
cation circuitry and specifications at any time without prior notice.
RF/IF mixer input power
+15
dBm
°C
Operating Temperature Range
Storage Temperature Range
-40 to +85
-40 to +150
°C
RFMD Green: RoHS compliant per EU Directive 2002/95/EC, halogen free
per IEC 61249-2-21, < 1000ppm each of antimony trioxide in polymeric
materials and red phosphorus as a flame retardant, and <2% antimony in
solder.
Specification
Parameter
Unit
Condition
Min.
Typ.
Max.
ESD Requirements
Human Body Model
2000
1500
500
V
V
V
DC Pins
All Pins
All Pins
Charge Device Model
Operating Conditions
Supply voltage (V
)
2.7
-40
3.0
3.3
V
DD
Temperature (T
)
+85
°C
OP
Logic Inputs/Outputs (VDD=Supply to DIG_VDD pin)
Input low voltage
Input high voltage
-0.3
1.5
+0.5
V
V
V
DD
Input low current
Input high current
-10
-10
+10
+10
A
A
Input=0V
Input=V
DD
Output low voltage
Output high voltage
0
0.2*V
V
V
DD
DD
0.8*V
10
V
DD
Load resistance
Load capacitance
GPO Drive Capability
Sink Current
kΩ
20
pF
20
20
25
mA
mA
Ω
At V = +0.6V
OL
Source Current
Output Impedance
Static
At V = +2.4V
OL
Supply Current (I ) with 1GHz LO
DD
100
125
mA
mA
mA
A
Low current, MIX_IDD=1, one mixer enabled.
High linearity, MIX_IDD=6, one mixer enabled.
Reference oscillator and bandgap only.
ENBL=0 and REF_STBY=0
Standby
4
300
Power Down Current
Mixer 1/2 (Mixer output driving 4:1 balun)
Gain
-2
10
dB
dB
Not including balun losses
Low current setting
High linearity setting
Low current setting
High linearity setting
Low current setting
High linearity setting
Noise Figure <3000MHz
13
dB
Noise Figure <4000MHz
IIP3
11
dB
15
dB
+10
+23
dBm
dBm
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Specification
Typ.
Parameter
Unit
Condition
Min.
Max.
Mixer 1/2 (Mixer output driving 4:1 balun) (continued)
Input Port Frequency range
Mixer input return loss
30
6000
4500
6000
MHz
dB
10
100Ω differential
Output port frequency range
30
MHz
Mixer 1/2 (Mixer output driving 1:1 balun)
Output Port Frequency Range
Gain
30
MHz
dB
-7
Not including balun losses
Reference Oscillator
Crystal frequency
10
1
26
26
7
MHz
Reference divider ratio
Synthesizer (PLL Closed Loop, 26MHz Crystal)
Synthesizer Output Frequency
Phase detector frequency
Phase noise (LO=1GHz)
85
4200
26
MHz
MHz
-102
-103
-130
0.30
-96
dBc/Hz 10kHz offset
dBc/Hz 100kHz offset
dBc/Hz 1MHz offset
0.40
0.60
1.00
1.10
°
RMS integrated from 1kHz to 40MHz
Phase noise (LO=2GHz)
Phase noise (LO=3GHz)
Phase noise (LO=4GHz)
dBc/Hz 10kHz offset
dBc/Hz 100kHz offset
dBc/Hz 1MHz offset
-97
-124
0.45
-91
°
RMS integrated from 1kHz to 40MHz
dBc/Hz 10kHz offset
dBc/Hz 100kHz offset
dBc/Hz 1MHz offset
-93
-120
0.80
-90
°
RMS integrated from 1kHz to 40MHz
dBc/Hz 10kHz offset
dBc/Hz 100kHz offset
dBc/Hz 1MHz offset
-91
-118
0.85
-210
°
RMS integrated from 1kHz to 40MHz
Normalized phase noise floor
Voltage Controlled Oscillator
Open loop phase noise at 1MHz offset
2.5GHz LO frequency
dBc/Hz Measured at 20kHz to 30kHz offset
-134
-135
-136
dBc/Hz VCO3, LO Divide by 2
dBc/Hz VCO2, LO Divide by 2
dBc/Hz VCO1, LO Divide by 2
2.0GHz LO frequency
1.5GHz LO frequency
Open loop phase noise at 10MHz offset
2.5GHz LO frequency
-149
-150
-151
dBc/Hz VCO3, LO Divide by 2
dBc/Hz VCO2, LO Divide by 2
dBc/Hz VCO1, LO Divide by 2
2.0GHz LO frequency
1.5GHz LO frequency
External LO Input
LO Input Frequency Range
LO Input Frequency Range
External LO Input Level
85
85
4200
5400
MHz
MHz
dBm
LO Divide by 1
LO Divide by 2
0
Driven from 50 Source Via a 1:1 Balun
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RFFC5061/62
Pin
1
2
Function
ENBL/GPO5
EXT_LO
Description
Device Enable pin (see note 1 and 2).
External local oscillator input (See note 4).
Decoupling pin for external local oscillator (See note 4).
External bandgap bias resistor (See note 3).
3
4
EXT_LO_DEC
REXT
Analog supply. Use good RF decoupling.
5
6
7
8
ANA_VDD1
LFILT1
LFILT2
LFILT3
MODE/GPO6
XTALP
Phase detector output. Low-frequency noise-sensitive node.
Loop filter op-amp output. Low-frequency noise-sensitive node.
VCO control input. Low-frequency noise-sensitive node.
Mode select pin (See note 1 and 2).
9
Reference crystal input.
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
Reference crystal input.
XTALN
TM
Connect to ground.
Differential input 1 (see note 4). On RFFC5062 this pin is NC.
Differential input 1 (see note 4). On RFFC5062 this pin is NC.
General purpose output / MultiSlice address bit.
General purpose output / MultiSlice address bit.
Differential output 1 (see note 5). On RFFC5062 this pin is NC.
Differential output 1 (see note 5). On RFFC5062 this pin is NC.
Digital supply. Should be decoupled as close to the pin as possible.
MIX1_IPN
MIX1_IPP
GPO1/ADD1
GPO2/ADD2
MIX1_OPN
MIX1_OPP
DIG_VDD
NC
NC
Analog supply. Use good RF decoupling.
ANA_VDD2
MIX2_IPP
MIX2_IPN
GPO3/FM
GPO4/LD/DO
MIX2_OPN
MIX2_OPP
RESETX
Differential input 2 (see note 4).
Differential input 2 (see note 4).
General purpose output / frequency control input.
General purpose output / Lock detect output / serial data out.
Differential output 2. (see note 5).
Differential output 2. (see note 5).
Chip reset (active low). Connect to DIG_VDD if asynchronous reset is not required.
Serial interface select (active low) (See note 1).
Serial interface clock (see note 1).
ENX
SCLK
SDATA
Serial interface data (see note 1).
Ground reference, should be connected to PCB ground through a low impedance path.
Exposed paddle
Note 1: An RC low-pass filter could be used on this line to reduce digital noise.
Note 2: If the device is under software control this input can be configured as a general purpose output (GPO).
Note 3: Connect a 51K resistor from this pin to ground. This pin is sensitive to low frequency noise injection.
Note 4: DC voltage should not be applied to this pin. Use either an AC coupling capacitor as part of lumped element matching
network or a transformer (see application schematic).
Note 5: This pin must be connected to ANA_VDD2 using an RF choke or transformer (see application schematic).
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Theory of Operation
The RFFC5061 and RFFC5062 are wideband RF frequency converter chips which include a fractional-N synthesizer and a low
noise VCO core. The RFFC5061 has an LO signal multiplexer, two LO buffer circuits, and two RF mixers. The RFFC5062 has a
single LO buffer circuit and one RF mixer. Both devices have an integrated voltage reference and low drop out regulators sup-
plying critical circuit blocks such as the VCOs and synthesizer. Synthesizer programming, device configuration and control are
achieved through a mixture of hardware and software controls. All on-chip registers are programmed through a simple 3-wire
serial interface.
VCO
The VCO core in the RFFC5061 and RFFC5062 consists of three VCOs which, in conjunction with the integrated LO dividers of
/2 to /32, cover the LO range of 85MHz to 4200MHz. Each VCO has 128 overlapping bands which are used to achieve low
VCO gain and optimal phase noise performance across the whole tuning range. The chip automatically selects the correct VCO
(VCO auto-select) and VCO band (VCO coarse tuning) to generate the desired LO frequency based on the values programmed
into the PLL1 and PLL2 registers banks.
The VCO auto-select and VCO coarse tuning are triggered every time ENBL is taken high, or if the PLL re-lock self clearing bit is
programmed high. Once the correct VCO and band have been selected the PLL will lock onto the correct frequency. During the
band selection process, fixed capacitance elements are progressively connected to the VCO resonant circuit until the VCO is
oscillating approximately at the correct frequency. The output of this band selection, CT_CAL, is made available in the read-
back register. A value of 127 or 0 in this register indicates that the coarse tuning was unsuccessful, and this will also be indi-
cated by the CT_FAILED flag also available in the read-back register. A CT_CAL value between 1 and 126 indicates a success-
ful calibration, the actual value being dependent on the desired frequency as well as process variation for a particular device.
The band select process will center the VCO tuning voltage at about 1.0V, compensating for manufacturing tolerances and pro-
cess variation as well as environmental factors including temperature. In applications where the device is left enabled at the
same LO frequency for some time, it is recommended that automatic band selection be performed for every 30°C change in
temperature. This assumes an active loop filter.
The RFFC5061 and RFFC5062 feature a differential LO input to allow the mixer to be driven from an external LO source. The
fractional-N PLL can be used with an external VCO driven into this LO input, which may be useful to reduce phase noise in
some applications. This may also require an external op-amp, dependant on the tuning voltage required by the external VCO.
In the RFFC5061 the LO signal is routed to mixer 1, mixer 2, or both mixers depending on the state of the MODE pin (or MODE
bit if under software control) and the value of the FULLD bit. Setting FULLD high puts the device into Full Duplex mode and both
mixers are enabled.
Fractional-N PLL
The RFFC5061 and RFFC5062 contain a charge pump-based fractional-N phase locked loop (PLL) for controlling the three
VCOs. The PLL has been designed to use a standard crystal of between 10MHz and 26MHz. The PLL includes automatic cali-
bration systems to counteract the effects of process and environmental variations, ensuring repeatable loop response and
phase noise performance. As well as the VCO auto-select and coarse tuning, there is a loop filter calibration mechanism which
can be enabled if required. This operates by adjusting the charge pump current to maintain loop bandwidth. This can be useful
for applications where the LO is tuned over a wide frequency range.
Two PLL programming banks are provided, the first bank is preceded by the label PLL1 and the second bank is preceded by the
label PLL2. For the RFFC5061 these banks are used to program mixer 1 and mixer 2 respectively, and are selected automati-
cally as the mixer is selected using MODE. For the RFFC5062 mixer 2 and register bank PLL2 are normally used.
The VCO outputs are first divided down in a high frequency prescalar. The output of this high frequency prescalar then enters
the N divider, which is a fractional divider containing a dual-modulus prescaler and a digitally spur-compensated fractional
sequence generator. This allows very fine frequency steps and minimizes fractional spurs. The fractional energy is randomized
and appears as fractional noise at frequency offsets above 100kHz which will be attenuated by the loop filter. An external loop
filter is used, giving flexibility in setting loop bandwidth for optimizing phase noise and lock time, for example.
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RFFC5061/62
The synthesizer step size is typically 1.5Hz when using a 26MHz reference frequency. The exact step size for any reference
and LO frequency can be calculated using the following formula:
(FREF * P) / (R * 224 * LO_DIV)
Where FREF is the reference frequency, R is the reference division ratio, P is the prescalar division ratio, and LO_DIV is the LO
divider value.
Pin 26 (GPO4) can be configured as a lock detect pin. The lock status is also available in the read-back register. The lock detect
function is a window detector on the VCO tuning voltage. The lock flag will be high to show PLL lock which corresponds to the
VCO tuning voltage being within the specified range, typically 0.30V to 1.25V.
Phase Detector and Charge Pump
The phase detector provides a current output to drive an active loop filter. The charge pump output current is set by the value
contained in the P1_CP_DEF and P2_CP_DEF fields in the loop filter configuration register. The charge pump current is given
by approximately 3uA/bit, and the fields are 6 bits long. This gives default value (31) of 93uA and maximum value (63) of
189uA.
If the automatic loop bandwidth calibration is enabled the charge pump current is set by the calibration algorithm based upon
the VCO gain.
The phase detector will operate with a maximum input frequency of 26MHz.
Loop Filter
The active loop filter is implemented using the on-chip low noise op-amp with external resistors and capacitors. The internal
configuration of the chip is shown below with the recommended active loop filter. The op-amp gives a tuning voltage range of
typically +0.1V to +2.4V. The recommended loop filter shown is designed to give the lowest integrated phase noise for refer-
ence frequency of 26MHz. The external loop filter gives the flexibility to optimize the loop response for any particular applica-
tion and combination of reference and VCO frequencies.
8p2
LFILT1
22K
180p
LFILT2
470R
470R
LFILT3
330p
330p
+1.1V
Crystal Oscillator
The RFFC5061 and RFFC5062 have been designed to use a standard, low cost, external crystal of typically 26MHz. The crystal
oscillator circuit contains internal loading capacitors. No external loading capacitors are required, assuming crystal load speci-
fication of between 8pF and 10pF.
The internal loading capacitors are a combination of fixed capacitance, and an array of switched capacitors. The switched
capacitors can be used to tune the crystal oscillator onto the required center frequency and minimize frequency error. The
capacitance steps are approximately 0.25pF (fine) and 0.55pF (coarse) and the total differential capacitance range is from
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about 2pF to 12pF. The PCB stray capacitance and oscillator input and output capacitance will also contribute to the crystal's
total load capacitance.
When the PLL is not in use, it may be desirable to turn off the internal reference circuits, by setting the REFSTBY bit low, to min-
imize current draw while in standby mode. On cold start, or if REFSTBY is programmed low, the reference circuits will need a
warm-up period. A crystal oscillator typically takes many milliseconds to settle. This time is set by the SU_WAIT bits. This will
allow the clock to be stable and immediately available when the ENBL bit is asserted high, allowing the PLL to assume normal
operation. If the current consumption of the reference circuits in standby mode, typically 4mA, is not critical, then the REFSTBY
bit can be set high. This allows the fastest startup and lock time after ENBL is taken high.
Wideband Mixer
The mixers are wideband, double-balanced Gilbert cells. They support RF/IF frequencies from 30MHz up to 6000MHz. Each
mixer has an input port and an output port that can be used for either IF or RF (in other words, for up- or down-conversion). The
mixer current can be programmed to between about 15mA and 45mA depending on linearity requirements. The majority of the
mixer current is sourced through the output pins via either a center-tapped balun or an RF choke in the external matching cir-
cuitry to the supply.
The RF mixer input and output ports are differential and require baluns and simple matching circuits optimized to the specific
application frequencies. A conversion gain of approximately -2dB (not including balun losses) is achieved with 100 differen-
tial input impedance, and the outputs driving 200 differential load impedance. Increasing the mixer output load increases
the conversion gain.
The mixer has a broadband common gate input. The input impedance is dominated by the resistance set by the mixer 1/gm
term, which is inversely proportional to the mixer current setting. The resistance will be approximately 85 at the default mixer
current setting (100). There is also some shunt capacitance at the mixer input, and the inductance of the bond wires (about
0.5nH on each pin) to consider at higher frequencies. The following diagram is a simple model of the mixer input impedance:
0.5nH
RFFC506x
Mixer Input
Rin
Typ 85
0.5pF
0.5nH
The mixer output is high impedance, consisting of approximately 2k resistance in parallel with some capacitance, approxi-
mately 1pF dependent on PCB layout. The mixer output does not require a conjugate matching network. It is a constant current
output which will drive a real differential load of between 50ꢀ and 500ꢀ, typically 200ꢀ. Since the mixer output is a constant
current source, a higher resistance load will give higher output voltage and gain. A shunt inductor can be used to resonate with
the mixer output capacitance at the frequency of interest. This inductor may not be required at lower frequencies where the
impedance of the output capacitance is less significant. At higher output frequencies the inductance of the bond wires (about
0.5nH on each pin) becomes more significant. Above about 4500MHz, it is beneficial to lower the output load to 50 to mini-
mize the effect of the ouput capacitance. The following diagram is a simple model of the mixer output:
0.5nH
1K
RFFC506x
Mixer Output
1pF
1K
0.5nH
The RFFC5061 mixer layout and pin placement has been optimized for high mixer-to-mixer isolation of greater than 60dB. The
mixers can be set up to operate in half duplex mode (1 mixer active) or full duplex mode (both mixers active). This selection is
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done via control of MODE and by setting the FULLD bit. When in full duplex mode, either PLL register bank can be used, the LO
signal is routed to both mixers.
Mode FULLD Active PLL
Active
Register Bank Mixer
LOW
HIGH
LOW
HIGH
0
0
1
1
1
2
1
2
1
2
1 and 2
1 and 2
Serial Interface
All on-chip registers in the RFFC5061 and RFFC5062 are programmed using a proprietary 3-wire serial bus which supports
both write and read operations. Synthesizer programming, device configuration, and control are achieved through a mixture of
hardware and software controls. Certain functions and operations require the use of hardware controls via the ENBL, MODE,
and RESETB pins in addition to programming via the serial bus. Alternatively there is the option to control the chip completely
via the serial bus.
The serial data interface can be configured for 4-wire operation by setting the 4wire bit in the SDI_CTRL register high. Then pin
26 is used as the data out pin, and pin 32 is the serial data in pin.
Hardware Control
Three hardware control pins are provided: ENBL, MODE, and RESETB.
The ENBL pin has two functions: to enable the analog circuits in the chip and to trigger the VCO auto-selection and coarse tun-
ing mechanisms. The VCO auto-selection and coarse tuning is initiated when the ENBL pin is taken high. Every time the fre-
quency of the synthesizer is reprogrammed, ENBL has to be asserted high to initiate these mechanisms and then to initiate the
PLL locking. Alternatively following the programming of a new frequency the PLL re-lock self clearing bit could be used.
If the device is left in the enabled state for long periods, it is recommended that VCO auto-selection and coarse tuning (band
selection) is performed for every 30°C change in temperature. The lock detect flag can be used to indicate when to perform
the VCO calibration, it shows that the VCO tuning voltage has drifted significantly with changing temperature.
The RESETB pin is a hardware reset control that will reset all digital circuits to their startup state when asserted low. The device
includes a power-on-reset function, so this pin should not normally be required, in which case it should be connected to the
positive supply.
The MODE pin controls which mixer(s) and PLL programming register bank is active.
Serial Data Interface Control
The normal mode of operation uses the 3-wire serial data interface to program the device registers, and three extra hardware
control lines: MODE, ENBL and RESETB.
When the device is under software control, achieved by setting the SIPIN bit in the SDI_CTRL register high, then the hardware
can be controlled via the SDI_CTRL register. When this is the case, the three hardware control lines are not required. If the
device is under software control, pins 1 and 9 can be configured as general purpose outputs (GPO).
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Multi-Slice Mode
ENX
SDATA
SCLK
Slice2
(0)
Slice2
(1)
Slice2
(2)
Slice2
(3)
A1 A2
A1 A2
A1 A2
A1 A2
Vdd
Vdd
Vdd
Vdd
The Multi-Slice mode of operation allows up to four chips to be controlled from a common serial bus. The device address pins
A0 and A1 are used to set the address of each part.
On power up, and after a reset, the devices ignore the address pins (A1 and A2, pins 15 and 16) and any data presented to the
serial bus will be programmed into all the devices. However, once the sipin bit in the SDI_CTRL register is set, each device then
adopts an address according to the state of the address pins on the device.
General Purpose Outputs
The general purpose outputs (GPOs) can be controlled via the GPO register and will depend on the state of MODE since they
can be set in different states corresponding to either mixer path 1 or 2. For example, the GPOs can be used to drive LEDs or to
control external circuitry such as switches or low power LNAs.
Each GPO pin can supply approximately 20mA load current. The output voltage of the GPO high state will drop with increased
current drive by approximately 25mV/mA. Similarly the output voltage of the GPO low state will rise with increased current,
again by approximately 25mV/mA.
External Modulation
The RFFC5061 and RFFC5062 fractional-N synthesizer can be used to modulate the frequency of the VCO. There are two ded-
icated registers, EXT_MOD and FMOD, which can be used to configure the device as a modulator. It is possible to modulate the
VCO in two ways:
1.Binary FSK
The MODSETUP bits in the EXT_MOD register are set to 11. GPO3 is then configured as an input and used to control the signal
frequency. The frequency deviation is set by the MODSTEP and MODULATION bits in the EXT_MOD and FMOD registers respec-
tively.
The modulation frequency is calculated according to the following formula:
FMOD = 2MODSTEP FPD MODULATION 216
Where MODULATION is a 2's complement number and FPD is the phase detector frequency.
2.Continuous Modulation
The MODSETUP bits in the EXT_MOD register are set to 01. The frequency deviation is set by the MODSTEP and MODULATION
bits in the EXT_MOD and FMOD registers respectively. The VCO frequency is then changed by writing a new value into the MOD-
ULATION bits, the VCO frequency is instantly updated. An arbitrary frequency modulation can then be performed dependant
only on the rate at which values are written into the FMOD register.
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RFFC5061/62
The modulation frequency is calculated according to the following formula:
FMOD = 2MODSTEP FPD MODULATION 216
Where MODULATION is a 2's complement number and FPD is the phase detector frequency.
Programming Information
The RFFC5061 and RFFC5062 share a common serial interface and control block. Please refer to the Register Maps and Pro-
gramming Guide which are available for download from http://rfmd.com/products/IntSynthMixer/.
Evaluation Boards
Evaluation boards for RFFC5061 and RFFC5062 are provided as part of a design kit, along with the necessary cables and pro-
gramming software tool to enable full evaluation of the device. Design kits can be ordered from www.rfmd.com or from local
RFMD sales offices and authorized sales channels. For ordering codes please see “Ordering Information” on page 25.
For further details on how to set up the design kits go to http://rfmd.com/products/IntSynthMixer/.
The standard evaluation boards are configured with 3.7GHz ceramic baluns on the RF ports and wideband transformers on
the IF ports. On the RFFC5061 evaluation board, mixer 1 is configured for down-conversion and mixer 2 is configured for up-
conversion. On the RFFC5062 evaluation board, mixer 2 is configured for down conversion.
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DS110614
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Detailed Functional Block Diagram
+3V
OP2
RFXF8553
4:1 Balun
RFXF9503
1:1 Balun
Ext LO
IP2
Mixer 2
Pre-
scaler
Loop
Filter
+3V
Sequence
generator
N
/2n
[n=0..5]
divider
51K
Phase
detector
+3V
Reference
divider
MODE
ENBL
Control
Lines
OP1
Mixer 1
RESET
ENX
3-Wire
Serial
Bus
Xtal oscillator
& tuning
SDATA
SCLK
GPO
RFXF8553
4:1 Balun
Lock
Flag
IP1
RFXF9503
1:1 Balun
RFFC5061 Only
Note: Wideband transmission line transformer baluns shown above for operation to ~2.5GHz. Substitute baluns for higher fre-
quency applications as required.
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RFFC5061/62
RFFC5061 Pin Out
ENBL/GPO5
EXT_LO
1
2
3
4
5
6
7
8
24 MIX2_IPN
23 MIX2_IPP
22 ANA_VDD2
21 NC
EXT_LO_DEC
REXT
Exposed
paddle
ANA_VDD1
LFILT1
20 NC
19 DIG_VDD
18 MIX1_OPP
17 MIX1_OPN
LFILT2
LFILT3
RFFC5062 Pin Out
ENBL/GPO5
EXT_LO
1
2
3
4
5
6
7
8
24 MIX_IPN
23 MIX_IPP
22 ANA_VDD2
21 NC
EXT_LO_DEC
REXT
Exposed
paddle
ANA_VDD1
LFILT1
20 NC
19 DIG_VDD
18 NC
LFILT2
LFILT3
17 NC
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DS110614
RFFC5061/62
Wideband Application Schematic (<2.5GHz)
2
2
2
2
3
4
I O P G
I O P G
G N D
2 5
2 6
2 7
2 8
2 9
3 0
3 1
3 2
3 3
1 6
1 5
O 2 G P I
O 1 G P I
4
I O P G
P 1 O I _ 2 X M I
N 1 O I _ 2 X M I
E S T X R E
M I X 1 _ I O 1 P
1 4
M I X 1 _ I O 1 N
1 3
T M
1 2
X
E N
L K S C
A T S D
N
P
A L X T
1 1
A L X T
1 0
A
M O D E
9
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RFFC5061/62
Narrowband 3.7GHz Application Schematic
2
2
2
2
1
2
3
6
5
4
1
2
3
6
5
4
3
I O P G
I O P G
G N D
2 5
2 6
2 7
2 8
2 9
3 0
3 1
3 2
3 3
1 6
1 5
2 O G P I
1 O G P I
4
4
I O P G
P 1
X I 2 _ M I O
M I X 1 _ I O 1 P
1 4
N 1 O I _ 2 X M I
E S T X R E
M I X 1 _ I O 1 N
1 3
T M
1 2
X
E N
L K S C
A T S D
N
P
A L X T
1 1
A L X T
1 0
A
M O D E
9
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DS110614
RFFC5061/62
Typical Performance Characteristics: Synthesizer and VCO
VDD=+3V and TA=+27°C unless stated.
Synthesizer Phase Noise
VCO Phase Noise
With LO Divide by 1
3000MHz VCO Frequency, 26MHz Crystal
-60.0
-70.0
-60.0
-70.0
3000MHz
1500MHz
750MHz
4000MHz VCO2
3500MHz VCO2
3000MHz VCO1
-80.0
-80.0
-90.0
-90.0
375MHz
187.5MHz
93.75MHz
-100.0
-110.0
-120.0
-130.0
-140.0
-150.0
-160.0
-100.0
-110.0
-120.0
-130.0
-140.0
-150.0
-160.0
1
1
1
10
100
1000
10000
100000
100000
100000
10.0
100.0
1000.0
10000.0
100000.0
Offset Frequency (KHz)
Offset Frequency (KHz)
Synthesizer Phase Noise
4000MHz VCO Frequency, 26MHz Crystal
VCO Phase Noise
With LO Divide by 2
-60.0
-70.0
-60.0
-70.0
2500MHz VCO3
2000MHz VCO2
1500MHz VCO1
4000MHz
2000MHz
1000MHz
500MHz
250MHz
125MHz
-80.0
-80.0
-90.0
-90.0
-100.0
-110.0
-120.0
-130.0
-140.0
-150.0
-160.0
-100.0
-110.0
-120.0
-130.0
-140.0
-150.0
-160.0
10
100
1000
10000
10.0
100.0
1000.0
10000.0
100000.0
Offset Frequency (KHz)
Offset Frequency (KHz)
Synthesiser RMS Integrated Phase Noise
Integration Bandwidth 1KHz to 40MHz
Synthesizer Phase Noise
5200MHz VCO Frequency, 26MHz Crystal
-60.0
-70.0
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
2600MHz
1300MHz
650MHz
325MHz
162.5MHz
-80.0
-90.0
-100.0
-110.0
-120.0
-130.0
-140.0
-150.0
-160.0
10
100
1000
10000
0
600
1200 1800 2400 3000 3600 4200
LO Frequency (MHz)
Offset Frequency (KHz)
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RFFC5061/62
Typical Performance Characteristics: VCO
VDD=+3V and TA=+27°C unless stated.
VCO1 Frequency versus Kvco
VCO1 Frequency versus CT_CAL
VCO1 with LO Divide by 2
LO Divide by 2
25
20
15
10
5
1800
1700
1600
1500
1400
1300
1200
-40 Deg C
+27 Deg C
+85 Deg C
VCO1
0
1200
1300
1400
1500
1600
1700
1800
0
0
0
20
40
60
80
100
120
120
120
VCO Frequency /2 (MHz)
CT_CAL Word
VCO2 Frequency versus Kvco
LO Divide by 2
VCO2 Frequency versus CT_CAL
VCO2 with LO Divide by 2
30
2300
2200
2100
2000
1900
1800
1700
1600
25
20
15
10
5
-40 Deg C
+27 Deg C
+85 Deg C
VCO2
0
1600 1700 1800 1900 2000 2100 2200 2300
VCO Frequency /2 (MHz)
20
40
60
80
100
CT_CAL Word
VCO3 Frequency versus Kvco
LO Divide by 2
VCO3 Frequency versus CT_CAL
VCO3 with LO Divide by 2
30
2900
2800
2700
2600
2500
2400
2300
2200
2100
25
20
15
10
5
-40 Deg C
+27 Deg C
+85 Deg C
VCO3
0
2200 2300 2400 2500 2600 2700 2800 2900
VCO Frequency /2 (MHz)
20
40
60
80
100
CT_CAL Word
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DS110614
RFFC5061/62
Typical Performance Characteristics: VCO
VDD=+3V and TA=+27°C unless stated.
VCO1 Frequency versus Tuning Voltage
For the same coarse tune setting, LO divide by two
VCO2 Frequency versus Tuning Voltage
For the same coarse tune setting, LO divide by two
1505
1500
1495
1490
1485
1480
1475
2020
2015
2010
2005
2000
1995
1990
1985
1980
-40 Deg C
+27 Deg C
+85 Deg C
-40 Deg C
+27 Deg C
+85 Deg C
0.0
0.5
1.0
1.5
0.0
0.5
1.0
1.5
Tuning Voltage (Volts)
Tuning Voltage (Volts)
VCO3 Frequency versus Tuning Voltage
For the same coarse tune setting, LO divide by two
2515
2510
2505
2500
2495
2490
2485
2480
2475
2470
2465
-40 Deg C
+27 Deg C
+85 Deg C
0.0
0.5
1.0
1.5
Tuning Voltage (Volts)
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RFFC5061/62
Typical Performance Characteristics: Supply Current
VDD=+3V and TA=+27°C unless stated.Typical Performance Characteristics: RFMixer 2, RFFC5061 and RFFC5062
Total Supply Current versus Mixer Bias Setting
One Mixer Enabled, LO Frequency = 3500MHz
160.0
Total Supply Current versus Mixer Bias Setting
One Mixer Enabled, LO Frequency = 1000MHz
140.0
150.0
140.0
130.0
120.0
110.0
100.0
90.0
130.0
120.0
110.0
100.0
90.0
-40 Deg C, +2.7V
-40 Deg C, +3.0V
-40 Deg C, +3.3V
+27 Deg C, +2.7V
+27 Deg C, +3.0V
+27 Deg C, +3.3V
+85 Deg C, +2.7V
+85 Deg C, +3.0V
+85 Deg C, +3.3V
-40 Deg C, +2.7V
-40 Deg C, +3.0V
-40 Deg C, +3.3V
+27 Deg C, +2.7V
+27 Deg C, +3.0V
+27 Deg C, +3.3V
+85 Deg C, +2.7V
+85 Deg C, +3.0V
+85 Deg C, +3.3V
80.0
1
2
3
4
5
6
7
1
2
3
4
5
6
7
Mixer Bias Current Setting (MIX_IDD)
Mixer Bias Current Setting (MIX_IDD)
RFFC5061 Typical Operating Current in mA
in Full Duplex Mode (both mixers enabled) with +3V supply.
Total Supply Current versus LO Frequency
One Mixer Enabled, +3.0V Supply Voltage
160.0
150.0
140.0
130.0
120.0
110.0
100.0
90.0
MIX2_IDD
MIX1_IDD
4
1
2
3
5
6
7
121
126
131
136
141
146
151
126
131
136
141
146
151
156
131
136
141
147
152
156
161
136
142
147
152
157
162
167
171
146
151
156
162
167
171
176
151
156
161
167
172
176
181
1
2
3
4
5
6
7
141
147
MIX_IDD = 1
MIX_IDD = 2
MIX_IDD = 3
MIX_IDD = 4
MIX_IDD = 5
MIX_IDD = 6
MIX_IDD = 7
152
157
80.0
161
70.0
166
60.0
100 600 1100 1600 2100 2600 3100 3600 4100
LO Frequency (MHz)
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DS110614
RFFC5061/62
Typical Performance Characteristics: RF Mixer 1, RFFC5061 only
VDD=+3V and TA=+27°C unless stated. As measured on RFFC5061 wideband evaluation board.
See application schematic on page 13.
-40 Deg C, +2.7V
Mixer 1 Noise Figure versus Bias Current
Conversion Gain of Mixer 1
-40 Deg C, +3.0V
LO Frequency = 1000MHz, IF Output = 100MHz
IF Output = 100MHz
-40 Deg C, +3.3V
+27 Deg C, +2.7V
+27 Deg C, +3.0V
+27 Deg C, +3.3V
+85 Deg C, +2.7V
+85 Deg C, +3.0V
+85 Deg C, +3.3V
16.0
14.0
12.0
10.0
8.0
0.0
-1.0
-2.0
-3.0
-4.0
-5.0
-6.0
-7.0
-40 Deg C, +2.7V
-40 Deg C, +3.0V
-40 Deg C, +3.3V
+27 Deg C, +2.7V
+27 Deg C, +3.0V
+27 Deg C, +3.3V
+85 Deg C, +2.7V
+85 Deg C, +3.0V
+85 Deg C, +3.3V
6.0
4.0
-8.0
-9.0
-10.0
2.0
0.0
1
2
3
4
5
6
7
7
7
400
600
800 1000 1200 1400 1600 1800 2000
RF Input Frequency (MHz)
Mixer Bias Current Setting (MIX1_IDD)
Mixer 1 Input IP3 versus Bias Current
Mixer 1 Noise Figure versus Frequency
IF Output = 100MHz
LO Frequency = 1000MHz, IF Output = 100MHz
16.0
14.0
12.0
10.0
8.0
30.0
25.0
20.0
15.0
10.0
5.0
-40 Deg C, +2.7V
-40 Deg C, +3.0V
-40 Deg C, +3.3V
+27 Deg C, +2.7V
+27 Deg C, +3.0V
+27 Deg C, +3.3V
+85 Deg C, +2.7V
+85 Deg C, +3.0V
+85 Deg C, +3.3V
MIX_IDD = 1
MIX_IDD = 2
MIX_IDD = 3
MIX_IDD = 4
MIX_IDD = 5
MIX_IDD = 6
MIX_IDD = 7
6.0
4.0
2.0
0.0
0.0
500
750
1000
1250
1500
1750
2000
1
2
3
4
5
6
LO Frequency (MHz)
Mixer Bias Current Setting (MIX1_IDD)
Mixer 1 Linearity Performance
Mixer 1 Input Power for 1dB Compression
LO Frequency = 1000MHz, IF Output = 100MHz
MIX_IDD = 5, +3.0V, IF Output = 100MHz
30.0
25.0
20.0
15.0
10.0
5.0
30.0
14.0
12.0
10.0
8.0
25.0
20.0
15.0
10.0
5.0
-40 Deg C, +2.7V
-40 Deg C, +3.0V
-40 Deg C, +3.3V
+27 Deg C, +2.7V
+27 Deg C, +3.0V
+27 Deg C, +3.3V
+85 Deg C, +2.7V
+85 Deg C, +3.0V
+85 Deg C, +3.3V
6.0
4.0
2.0
Input IP3
Pin 1dB
0.0
0.0
0.0
-2.0
500
750
1000
1250
1500
1750
2000
2250
1
2
3
4
5
6
RF Input Frequency (MHz)
Mixer Bias Current Setting (MIX1_IDD)
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RFFC5061/62
Typical Performance Characteristics: RF Mixer 2, RFFC5061 and RFFC5062
VDD=+3V and TA=+27°C unless stated. As measured on RFFC5061/5062 wideband evaluation board.
See application schematic on page 13.
-40 Deg C, +2.7V
Mixer 2 Noise Figure versus Bias Current
Conversion Gain of Mixer 2
-40 Deg C, +3.0V
LO Frequency = 1000MHz, IF Output = 100MHz
IF Output = 100MHz
-40 Deg C, +3.3V
+27 Deg C, +2.7V
+27 Deg C, +3.0V
+27 Deg C, +3.3V
+85 Deg C, +2.7V
+85 Deg C, +3.0V
+85 Deg C, +3.3V
16.0
14.0
12.0
10.0
8.0
0.0
-1.0
-2.0
-3.0
-4.0
-5.0
-6.0
-7.0
-40 Deg C, +2.7V
-40 Deg C, +3.0V
-40 Deg C, +3.3V
+27 Deg C, +2.7V
+27 Deg C, +3.0V
+27 Deg C, +3.3V
+85 Deg C, +2.7V
+85 Deg C, +3.0V
+85 Deg C, +3.3V
6.0
4.0
-8.0
-9.0
-10.0
2.0
0.0
1
2
3
4
5
6
7
7
7
400
600
800
1000 1200 1400 1600 1800 2000
Mixer Bias Current Setting (MIX2_IDD)
RF Input Frequency (MHz)
Mixer 2 Input IP3 versus Bias Current
Mixer 2 Noise Figure versus Frequency
IF Output = 100MHz
LO Frequency = 1000MHz, IF Output = 100MHz
16.0
14.0
12.0
10.0
8.0
30.0
25.0
20.0
15.0
10.0
5.0
-40 Deg C, +2.7V
-40 Deg C, +3.0V
-40 Deg C, +3.3V
+27 Deg C, +2.7V
+27 Deg C, +3.0V
+27 Deg C, +3.3V
+85 Deg C, +2.7V
+85 Deg C, +3.0V
+85 Deg C, +3.3V
MIX_IDD = 1
MIX_IDD = 2
MIX_IDD = 3
MIX_IDD = 4
MIX_IDD = 5
MIX_IDD = 6
MIX_IDD = 7
6.0
4.0
2.0
0.0
0.0
500
750
1000
1250
1500
1750
2000
1
2
3
4
5
6
LO Frequency (MHz)
Mixer Bias Current Setting (MIX2_IDD)
Mixer 2 Input Power for 1dB Compression
LO Frequency = 1000MHz, IF Output = 100MHz
Mixer 2 Linearity Performance
MIX_IDD = 5, +3.0V, IF Output = 100MHz
14.0
12.0
10.0
8.0
30.0
30.0
25.0
20.0
15.0
10.0
5.0
25.0
20.0
15.0
10.0
5.0
-40 Deg C, +2.7V
-40 Deg C, +3.0V
-40 Deg C, +3.3V
+27 Deg C, +2.7V
+27 Deg C, +3.0V
+27 Deg C, +3.3V
+85 Deg C, +2.7V
+85 Deg C, +3.0V
+85 Deg C, +3.3V
6.0
4.0
2.0
Input IP3
Pin 1dB
0.0
-2.0
0.0
500
0.0
1
2
3
4
5
6
750
1000 1250 1500 1750 2000 2250
Mixer Bias Current Setting (MIX2_IDD)
RF Input Frequency (MHz)
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DS110614
RFFC5061/62
Typical Performance Characteristics: RF Mixers, RFFC5061 and RFFC5062
VDD=+3V and TA=+27°C unless stated. As measured on RFFC5061/5062 wideband evaluation board.
See application schematic on page 13. Note: Mixer 1 plots only apply to RFFC5061.
LO & RF Leakage at Mixer 1 Output
RF Input Power 0dBm, MIX1_IDD = 4
LO & RF Leakage at Mixer 2 Output
RF Input Power 0dBm, MIX2_IDD = 4
0.0
-10.0
-20.0
-30.0
-40.0
-50.0
-60.0
0.0
-10.0
-20.0
-30.0
-40.0
-50.0
-60.0
IF Output at 100MHz
LO Leakage (High Side)
RF Leakage
IF Output at 100MHz
LO Leakage (High Side)
RF Leakage
400.0
600.0
800.0
1000.0
1200.0
1400.0
1600.0
400.0
600.0
800.0
1000.0
1200.0
1400.0
1600.0
RF Input Frequency (MHz)
RF Input Frequency (MHz)
Typical LO Leakage at Mixer Output
+3.0V Supply Voltage
Mixer to Mixer Isolation in Full Duplex Mode
LO = RF input + 100MHz
0.0
-10.0
-20.0
-30.0
-40.0
-50.0
-60.0
-70.0
100.0
90.0
80.0
70.0
60.0
50.0
40.0
Path 1, -40 Deg C
Path 1, +27 Deg C
Path 1, +85 Deg C
Path 2, -40 Deg C
Path 2, +27 Deg C
Path 2, +85 Deg C
MIX_IDD = 4
200 400 600 800 1000 1200 1400 1600 1800 2000
0
500
1000
1500
2000
2500
LO Frequency (MHz)
RF Input Frequency (MHz)
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RFFC5061/62
Typical Performance Characteristics: RF Mixers at 3.7GHz
VDD=+3V and TA=+27°C unless stated. As measured on 3.7GHz narrowband evaluation board, down conversion.
See application schematic on page 14
Mixer 1 Input IP3 versus Bias Current
Conversion Gain of Mixer 1
Down Conversion with IF Output = 200MHz
-40 Deg C, +2.7V
-40 Deg C, +3.0V
-40 Deg C, +3.3V
+27 Deg C, +2.7V
+27 Deg C, +3.0V
+27 Deg C, +3.3V
+85 Deg C, +2.7V
+85 Deg C, +3.0V
+85 Deg C, +3.3V
RF Frequency = 4000MHz, IF Output = 200MHz
30.0
25.0
20.0
15.0
10.0
5.0
0.0
-1.0
-2.0
-3.0
-4.0
-5.0
-6.0
-7.0
-40 Deg C, +2.7V
-40 Deg C, +3.0V
-40 Deg C, +3.3V
+27 Deg C, +2.7V
+27 Deg C, +3.0V
+27 Deg C, +3.3V
+85 Deg C, +2.7V
+85 Deg C, +3.0V
+85 Deg C, +3.3V
-8.0
-9.0
-10.0
0.0
1
2
3
4
5
6
7
3400 3500 3600 3700 3800 3900 4000 4100 4200
RF Input Frequency (MHz)
Mixer Bias Current Setting (MIX1_IDD)
TypicalLO Leakage at Mixer 1 Output
+3.0V Supply Voltage
Mixer1 Noise Figure versus Frequency
IF Output = 200MHz
0.0
-10.0
-20.0
-30.0
-40.0
-50.0
-60.0
18.0
-40 Deg C
+27 Deg C
+85 Deg C
16.0
14.0
12.0
10.0
8.0
MIX_IDD = 1
MIX_IDD = 2
MIX_IDD = 3
MIX_IDD = 4
MIX_IDD = 5
MIX_IDD = 6
MIX_IDD = 7
6.0
4.0
2.0
0.0
3200
3400
3600
3800
4000
4200
4400
3400 3500 3600 3700 3800 3900 4000 4100 4200
RF Input Frequency (MHz)
LO Frequency (MHz)
Mixer 1 Linearity Performance
MIX_IDD = 5, +3.0V, IF Output = 200MHz
LO & RF Leakage at Mixer 1 Output
RF Input Power -10dBm, MIX1_IDD = 4
30.0
30.0
25.0
20.0
15.0
10.0
5.0
-10.0
-20.0
-30.0
-40.0
-50.0
-60.0
-70.0
-80.0
25.0
20.0
15.0
10.0
5.0
IF Outputat 200MHz
LO Leakage(Low Side)
RF Leakage
InputIP3
Pin 1dB
0.0
0.0
3400 3500 3600 3700 3800 3900 4000 4100 4200
RF Input Frequency (MHz)
3400 3500 3600 3700 3800 3900 4000 4100 4200
RF Input Frequency (MHz)
7628 Thorndike Road, Greensboro, NC 27409-9421 · For sales or technical
support, contact RFMD at (+1) 336-678-5570 or sales-support@rfmd.com.
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RFFC5061/62
Typical Performance Characteristics: RF Mixers at 3.7GHz
VDD=+3V and TA=+27°C unless stated. As measured on 3.7GHz narrowband evaluation board, up conversion.
See application schematic on page 14
Resonant match on mixer output, shunt inductor L1 is 2.7nH unless stated.
Conversion Gain of Mixer 2
Up Conversion with IF Input = 500MHz
Mixer 2 Input IP3 versus Bias Current
IF Input = 500MHz, RF output = 3900MHz
0.0
25.0
-40 Deg C, +2.7V
-40 Deg C, +3.0V
-40 Deg C, +3.3V
+27 Deg C, +2.7V
+27 Deg C, +3.0V
+27 Deg C, +3.3V
+85 Deg C, +2.7V
+85 Deg C, +3.0V
+85 Deg C, +3.3V
-1.0
-2.0
-3.0
-4.0
-5.0
-6.0
-7.0
20.0
15.0
10.0
5.0
-40 Deg C, +2.7V
-40 Deg C, +3.0V
-40 Deg C, +3.3V
+27 Deg C, +2.7V
+27 Deg C, +3.0V
+27 Deg C, +3.3V
+85 Deg C, +2.7V
+85 Deg C, +3.0V
+85 Deg C, +3.3V
-8.0
-9.0
-10.0
0.0
3400
3600
3800
4000
4200
1
2
3
4
5
6
7
RF Output Frequency (MHz)
Mixer Bias Current Setting (MIX2_IDD)
Conversion Gain of Mixer 2 versus Shunt Inductor
Mixer2 Noise Figure versus Frequency
Up Conversion with IF Input = 500MHz
Up Conversion with IF Input = 500MHz
20.0
18.0
16.0
14.0
12.0
10.0
8.0
0.0
-5.0
-10.0
MIX_IDD = 1
MIX_IDD = 2
MIX_IDD = 3
MIX_IDD = 4
MIX_IDD = 5
MIX_IDD = 6
MIX_IDD = 7
-15.0
6.0
3.3nH
2.7nH
2.2nH
4.0
-20.0
2.0
0.0
-25.0
3400
3600
3800
4000
4200
2500 2750 3000 3250 3500 3750 4000 4250 4500 4750
RF Output Frequency (MHz)
RF Output Frequency (MHz)
IF and LO Leakage at Mixer 2 Output
RF Input Power - 10dBm, MIX_IDD = 4
Mixer2 Noise Figure versus Bias Current
IF Input = 500MHz, RF Output = 3900MHz
20.0
18.0
16.0
14.0
12.0
10.0
8.0
-10.0
-20.0
-30.0
-40.0
-50.0
-60.0
-70.0
-80.0
-40 Deg C, +2.7V
-40 Deg C, +3.0V
-40 Deg C, +3.3V
+27 Deg C, +2.7V
+27 Deg C, +3.0V
+27 Deg C, +3.3V
+85 Deg C, +2.7V
+85 Deg C, +3.0V
+85 Deg C, +3.3V
RF Output
LO Leakage(Low Side)
IF Leakageat 500MHz
6.0
4.0
2.0
0.0
1
2
3
4
5
6
7
2800 3000 3200 3400 3600 3800 4000 4200 4400 4600
RF Output Frequency (MHz)
Mixer Bias Current Setting (MIX2_IDD)
7628 Thorndike Road, Greensboro, NC 27409-9421 · For sales or technical
support, contact RFMD at (+1) 336-678-5570 or sales-support@rfmd.com.
DS110614
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RFFC5061/62
Package Drawing
QFN, 32-pin, 5mmx5mm
7628 Thorndike Road, Greensboro, NC 27409-9421 · For sales or technical
support, contact RFMD at (+1) 336-678-5570 or sales-support@rfmd.com.
24 of 25
DS110614
RFFC5061/62
Ordering Information
RFFC5061
Part Number
RFFC5061SB
RFFC5061SQ
RFFC5061SR
RFFC5061TR7
RFFC5061TR13
DKFC5061
Description
32-pin QFN
Devices/Container
5-piece sample bag
25-piece sample bag
100-piece reel
750-piece reel
2500-piece reel
1 box
32-pin QFN
32-pin QFN
32-pin QFN
32-pin QFN
Complete Design Kit
RFFC5062
Part Number
RFFC5062SB
RFFC5062SQ
RFFC5062SR
RFFC5062TR7
RFFC5062TR13
DKFC5062
Description
32-pin QFN
Devices/Container
5-piece sample bag
25-piece sample bag
100-piece reel
32-pin QFN
32-pin QFN
32-pin QFN
32-pin QFN
750-piece reel
2500-piece reel
1 box
Complete Design Kit
7628 Thorndike Road, Greensboro, NC 27409-9421 · For sales or technical
support, contact RFMD at (+1) 336-678-5570 or sales-support@rfmd.com.
DS110614
25 of 25
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