RX6000 [RFM]

916.50 MHz Hybrid Receiver; 916.50兆赫混合接收机


型号：	RX6000
厂家：	RF MONOLITHICS, INC
描述：	916.50 MHz Hybrid Receiver 916.50兆赫混合接收机电信集成电路接收机
文件：	总10页 (文件大小：72K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

RX6000

•

Designed for Short-Range Wireless Control and Data Communications

Supports RF Data Transmission Rates Up to 115.2 kbps

3 V, Low Current Operation plus Sleep Mode

916.50 MHz

Hybrid

Stable, Easy to Use, Low External Parts Count

Complies with Directive 2002/95/EC (RoHS)

Receiver

The RX6000 hybrid receiver is ideal for short-range wireless control and data applications where robust op-

eration, small size, low power consumption and low cost are required. The RX6000 employs RFM’s amplifier-

sequenced hybrid (ASH) architecture to achieve this unique blend of characteristics. All critical RF functions

are contained in the hybrid, simplifying and speeding design-in. The RX6000 is sensitive and stable. A wide

dynamic range log detector, in combination with digital AGC and a compound data slicer, provide robust per-

formance in the presence of on-channel interference or noise. Two stages of SAW filtering provide excellent

receiver out- of-band rejection. The RX6000 generates virtually no RF emissions, facilitating compliance with

FCC 15.249 and similar regulations.

Rating

Power Supply and All Input/Output Pins

Non-Operating Case Temperature

Value

-0.3 to +4.0

-50 to +100

260

Units

°C

SM-20H Case

Soldering Temperature (10 seconds / 5 cycles max.)

°C

Electrical Characteristics

Characteristic

Operating Frequency

Sym

Notes

Minimum

Typical

Maximum

Units

916.30

916.70

MHz

Modulation Types

OOK & ASK

Data Rate

115.2

kbps

Receiver Performance, High Sensitivity Mode

Sensitivity, 2.4 kbps, 10-3 BER, AM Test Method

Sensitivity, 2.4 kbps, 10-3 BER, Pulse Test Method

-106

-100

3.0

dBm

Current, 2.4 kbps (R = 330 K)

Sensitivity, 19.2 kbps, 10-3 BER, AM Test Method

Sensitivity, 19.2 kbps, 10-3 BER, Pulse Test Method

-101

-95

dBm

Current, 19.2 kbps (R = 330 K)

3.1

Sensitivity, 115.2 kbps, 10-3 BER, AM Test Method

Sensitivity, 115.2 kbps, 10-3 BER, Pulse Test Method

Current, 115.2 kbps

-97

dBm

-91

3.8

Receiver Performance, Low Current Mode

Sensitivity, 2.4 kbps, 10-3 BER, AM Test Method

Sensitivity, 2.4 kbps, 10-3 BER, Pulse Test Method

-104

-98

dBm

Current, 2.4 kbps (R = 1100 K)

1.8

RF Monolithics, Inc.

RFM Europe

Phone: (972) 233-2903

Phone: 44 1963 251383

Fax: (972) 387-8148

Fax: 44 1963 251510

E-mail: info@rfm.com

http://www.rfm.com

RX6000-062905

Page 1 of 10

Electrical Characteristics (typical values given for 3.0 Vdc power supply, 25 °C)

Characteristic

Sym

Notes

Minimum

Typical

Maximum

Units

Receiver Out-of-Band Rejection, ±5% fo

Receiver Ultimate Rejection

Sleep Mode Current

100

0.7

±5%

ULT

µA

Power Supply Voltage Range

Power Supply Voltage Ripple

Ambient Operating Temperature

2.2

-40

3.7

Vdc

P-P

°C

Notes:

-3

1. Typical sensitivity data is based on a 10 bit error rate (BER), using DC-balanced data. There are two test methods commonly used to measure

OOK/ASK receiver sensitivity, the “100% AM” test method and the “Pulse” test method. Sensitivity data is given for both test methods. See Ap-

pendix 3.8 in the ASH Transceiver Designer’s Guide for the details of each test method, and for sensitivity curves for a 2.2 to 3.7 V supply voltage

range at five operating temperatures. The application/test circuit and component values are shown on the next page and in the Designer’s Guide.

2. At low data rates it is possible to adjust the ASH pulse generator to trade-off some receiver sensitivity for lower operating current. Sensitivity

data and receiver current are given at 2.4 kbps for both high sensitivity operation (R = 330 K) and low current operation (R = 1100 K).

3. Data is given with the ASH radio matched to a 50 ohm load. Matching component values are given on the next page.

4. See Table 1 on Page 8 for additional information on ASH radio event timing.

SM-20H Package Drawing

ASH Transceiver Pin Out

GND1

RFIO

VCC1

AGCCAP

PKDET

19 GND3

18 CNTRL0

17 CNTRL1

16 VCC2

BBOUT

CMPIN

15 PWIDTH

14 PRATE

13 THLD1

12 THLD2

Inches

Nom

RXDATA

TXMOD

LPFADJ

Dimension

Min

Nom

Max

Min

Max

9.881

6.731

1.778

1.651

0.381

0.889

3.175

1.397

10.033

6.858

1.930

1.778

0.508

1.016

3.302

1.524

10.135

6.985

2.032

1.905

0.635

1.143

3.429

1.651

.389

.265

.070

.065

.015

.035

.125

.055

.395

.270

.076

.070

.020

.040

.130

.060

.400

.275

.080

.075

.025

.045

.135

.065

10 11

GND2

RREF

RF Monolithics, Inc.

RFM Europe

Phone: (972) 233-2903

Phone: 44 1963 251383

Fax: (972) 387-8148

Fax: 44 1963 251510

E-mail: info@rfm.com

http://www.rfm.com

RX6000-062905

Page 2 of 10

ASH Receiver Application Circuit

OOK Configuration

ASH Receiver Application Circuit

ASK Configuration

+ 3

VDC

+ 3

VDC

C_DCB

R _TH1

R/S

R _PW

R _PR

R _PW

R _PR

R/S

R _TH2

GND

CNT

GND

CNT

VCC

THLD

CNT

RL1

VCC

THLD

CNT

RL1

THLD

L_AT

RL0

WIDTH RATE

RL0

WIDTH RATE

RFIO

RREF

RFIO

RREF

R _REF

TOP VIEW

L_ESD

GND1

GND2

L_ESD

GND1

GND2

VCC

DET

OUT

CMP

DATA

LPF

ADJ

VCC

AGC

CAP

DET

OUT

CMP

DATA

LPF

ADJ

R _LPF

R _BBO

C_RFB1

C_BBO

+ 3

C_RFB1

+ 3

C_BBO

VDC

C_AGCC_PKD

C_LPF

Data Output

Receiver Set-Up, 3.0 Vdc, -40 to +85 °C

Item

Symbol

OOK

2.4

OOK

ASK

Units

Notes

Nominal NRZ Data Rate

19.2

115.2

kbps

µs

µF

see page 1& 2

single bit

NOM

Minimum Signal Pulse

Maximum Signal Pulse

AGCCAP Capacitor

PKDET Capacitor

BBOUT Capacitor

BBOUT Resistor

416.67

52.08

8.68

34.72

2200

0.001

0.0027

MIN

MAX

AGC

1666.68

208.32

4 bits of same value

±10% ceramic

±5%

PKD

BBO

0.1

0.015

LPFAUX Capacitor

LPFADJ Resistor

0.0047

300

100

µF

±5%

LPF

REF

100

±5%

RREF Resistor

100

±1%

THLD2 Resistor

±1%, for 6 dB below peak

±1%, typical values

±5%

TH2

TH1

THLD1 Resistor

330

PRATE Resistor

330

160

PWIDTH Resistor

DC Bypass Capacitor

RF Bypass Capacitor 1

Antenna Tuning Inductor

Shunt Tuning/ESD Inductor

270 to GND

4.7

1000 to Vcc

±5%

4.7

µF

tantalum

DCB

±5% NPO

RFB1

50 ohm antenna

100

ESD

CAUTION: Electrostatic Device. Observe precautions when handling.

RF Monolithics, Inc.

RFM Europe

Phone: (972) 233-2903

Phone: 44 1963 251383

Fax: (972) 387-8148

Fax: 44 1963 251510

E-mail: info@rfm.com

http://www.rfm.com

RX6000-062905

Page 3 of 10

An incoming RF signal is first filtered by a narrow-band SAW filter, and is

then applied to RFA1. The pulse generator turns RFA1 ON for 0.5 µs. The

amplified signal from RFA1 emerges from the SAW delay line at the input

to RFA2. RFA1 is now switched OFF and RFA2 is switched ON for 0.55 µs,

amplifying the RF signal further. The ON time for RFA2 is usually set at 1.1

times the ON time for RFA1, as the filtering effect of the SAW delay line

stretches the signal pulse from RFA1 somewhat. As shown in the timing di-

agram, RFA1 and RFA2 are never on at the same time, assuring excellent

receiver stability. Note that the narrow-band SAW filter eliminates sampling

sideband responses outside of the receiver passband, and the SAW filter

and delay line act together to provide very high receiver ultimate rejection.

ASH Receiver Theory of Operation

Introduction

RFM’s RX6000 series amplifier-sequenced hybrid (ASH) receivers are

specifically designed for short-range wireless control and data communica-

tion applications. The receivers provide robust operation, very small size,

low power consumption and low implementation cost. All critical RF func-

tions are contained in the hybrid, simplifying and speeding design-in. The

ASH receiver can be readily configured to support a wide range of data

rates and protocol requirements. The receiver features virtually no RF

emissions, making it easy to certify to short-range (unlicensed) radio regu-

lations.

Amplifier-sequenced receiver operation has several interesting character-

istics that can be exploited in system design. The RF amplifiers in an am-

plifier-sequenced receiver can be turned on and off almost instantly,

allowing for very quick power-down (sleep) and wake-up times. Also, both

RF amplifiers can be off between ON sequences to trade-off receiver noise

figure for lower average current consumption. The effect on noise figure

can be modeled as if RFA1 is on continuously, with an attenuator placed in

Amplifier-Sequenced Receiver Operation

The ASH receiver’s unique feature set is made possible by its system ar-

chitecture. The heart of the receiver is the amplifier- sequenced receiver

section, which provides more than 100 dB of stable RF and detector gain

without any special shielding or decoupling provisions. Stability is achieved

by distributing the total RF gain over time. This is in contrast to a superhet-

erodyne receiver, which achieves stability by distributing total RF gain over

multiple frequencies.

front of it with a loss equivalent to 10*log (RFA1 duty factor), where the

duty factor is the average amount of time RFA1 is ON (up to 50%). Since

an amplifier-sequenced receiver is inherently a sampling receiver, the

overall cycle time between the start of one RFA1 ON sequence and the

start of the next RFA1 ON sequence should be set to sample the narrowest

RF data pulse at least 10 times. Otherwise, significant edge jitter will be

added to the detected data pulse.

Figure 1 shows the basic block diagram and timing cycle for an amplifier-

sequenced receiver. Note that the bias to RF amplifiers RFA1 and RFA2

are independently controlled by a pulse generator, and that the two ampli-

fiers are coupled by a surface acoustic wave (SAW) delay line, which has

a typical delay of 0.5 µs.

ASH Receiver Block Diagram & Timing Cycle

Antenna

Detector &

Low-Pass

Filter

SAW

Delay Line

Data

Out

SAW Filter

RFA1

RFA2

Pulse

Generator

RF Input

RF Data Pulse

t_PW1

t_PRI

t_PRC

RFA1 Out

Delay Line

Out

t_PW2

Figure 1

RF Monolithics, Inc.

RFM Europe

Phone: (972) 233-2903

Phone: 44 1963 251383

Fax: (972) 387-8148

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RX6000-062905

Page 4 of 10

RX6000 Series ASH Receiver Block Diagram

CN TRL1

CN TRL0

VCC1: Pin 2

VCC2: Pin 16

GND1: Pin 1

GND2: Pin 10

GND3: Pin 19

Power

Down

Control

Bias Control

NC:

Pin 8

RREF: Pin 11

CMPIN: Pin 6

Antenna

Log

BBOUT

RFIO

DS2

Ref

SAW

CR Filter

SAW

Delay Line

Low-Pass

Filter

Peak

Detector

RFA1

RFA2

Detector

C _BBO

ESD

dB Below

Peak Thld

LPFADJ

PKDET

Choke

C _PKD

AND

RXDATA

R _LPF

AGC Set

AGC

DS1

Gain Select

Ref

Thld

AGC Reset

Pulse Generator

& RF Amp Bias

AGC

Control

Threshold

Control

AGCCAP

PRATE 14

R _PR

15 PWIDTH

R _PW

THLD1

THLD2

C _AGC

R _TH1

R _TH2

R _REF

Figure 2

RX6000 Series ASH Receiver Block Diagram

The detector output drives a gyrator filter. The filter provides a three-pole,

0.05 degree equiripple low-pass response with excellent group delay flat-

ness and minimal pulse ringing. The 3 dB bandwidth of the filter can be set

from 4.5 kHz to 1.8 MHz with an external resistor.

Figure 2 is the general block diagram of the RX6000 series ASH receiver.

Please refer to Figure 2 for the following discussions.

Antenna Port

The filter is followed by a base-band amplifier which boosts the detected

signal to the BBOUT pin. When the receiver RF amplifiers are operating at

a 50%-50% duty cycle, the BBOUT signal changes about 10 mV/dB, with

a peak-to-peak signal level of up to 685 mV. For lower duty cycles, the mV/

dB slope and peak-to-peak signal level are proportionately less. The de-

tected signal is riding on a 1.1 Vdc level that varies somewhat with supply

voltage, temperature, etc. BBOUT is coupled to the CMPIN pin or to an ex-

ternal data recovery process (DSP, etc.) by a series capacitor. The correct

value of the series capacitor depends on data rate, data run length, and

other factors as discussed in the ASH Transceiver Designer’s Guide.

The only external RF components needed for the receiver are the antenna

and its matching components. Antennas presenting an impedance in the

range of 35 to 72 ohms resistive can be satisfactorily matched to the RFIO

pin with a series matching coil and a shunt matching/ESD protection coil.

Other antenna impedances can be matched using two or three compo-

nents. For some impedances, two inductors and a capacitor will be re-

quired. A DC path from RFIO to ground is required for ESD protection.

Receiver Chain

The output of the SAW filter drives amplifier RFA1. This amplifier includes

provisions for detecting the onset of saturation (AGC Set), and for switching

between 35 dB of gain and 5 dB of gain (Gain Select). AGC Set is an input

to the AGC Control function, and Gain Select is the AGC Control function

output. ON/OFF control to RFA1 (and RFA2) is generated by the Pulse

Generator & RF Amp Bias function. The output of RFA1 drives the SAW

delay line, which has a nominal delay of 0.5 µs.

When an external data recovery process is used with AGC, BBOUT must

be coupled to the external data recovery process and CMPIN by separate

series coupling capacitors. The AGC reset function is driven by the signal

applied to CMPIN.

When the receiver is placed in the power-down (sleep) mode, the output

impedance of BBOUT becomes very high. This feature helps preserve the

charge on the coupling capacitor to minimize data slicer stabilization time

when the receiver switches out of the sleep mode.

The second amplifier, RFA2, provides 51 dB of gain below saturation. The

output of RFA2 drives a full-wave detector with 19 dB of threshold gain. The

onset of saturation in each section of RFA2 is detected and summed to pro-

vide a logarithmic response. This is added to the output of the full-wave de-

tector to produce an overall detector response that is square law for low

signal levels, and transitions into a log response for high signal levels. This

combination provides excellent threshold sensitivity and more than 70 dB

of detector dynamic range. In combination with the 30 dB of AGC range in

RFA1, more than 100 dB of receiver dynamic range is achieved.

Data Slicers

The CMPIN pin drives two data slicers, which convert the analog signal

from BBOUT back into a digital stream. The best data slicer choice de-

pends on the system operating parameters. Data slicer DS1 is a capacitive-

ly-coupled comparator with provisions for an adjustable threshold. DS1

provides the best performance at low signal-to-noise conditions. The

RF Monolithics, Inc.

RFM Europe

Phone: (972) 233-2903

Phone: 44 1963 251383

Fax: (972) 387-8148

Fax: 44 1963 251510

E-mail: info@rfm.com

http://www.rfm.com

RX6000-062905

Page 5 of 10

threshold, or squelch, offsets the comparator’s slicing level from 0 to 90

mV, and is set with a resistor between the RREF and THLD1 pins. This

threshold allows a trade- off between receiver sensitivity and output noise

density in the no-signal condition. For best sensitivity, the threshold is set

to 0. In this case, noise is output continuously when no signal is present.

This, in turn, requires the circuit being driven by the RXDATA pin to be able

to process noise (and signals) continuously.

In the low data rate mode, the interval between the falling edge of one

RFA1 ON pulse to the rising edge of the next RFA1 ON pulse t is set by

a resistor between the PRATE pin and ground. The interval can be adjust-

ed between 0.1 and 5 µs. In the high data rate mode (selected at the

PWIDTH pin) the receiver RF amplifiers operate at a nominal 50%-50%

PRI

duty cycle. In this case, the start-to-start period t

for ON pulses to RFA1

PRC

are controlled by the PRATE resistor over a range of 0.1 to 1.1 µs.

This can be a problem if RXDATA is driving a circuit that must “sleep” when

data is not present to conserve power, or when it its necessary to minimize

false interrupts to a multitasking processor. In this case, noise can be

greatly reduced by increasing the threshold level, but at the expense of

sensitivity. The best 3 dB bandwidth for the low-pass filter is also affected

by the threshold level setting of DS1. The bandwidth must be increased as

the threshold is increased to minimize data pulse-width variations with sig-

nal amplitude.

In the low data rate mode, the PWIDTH pin sets the width of the ON pulse

to RFA1 with a resistor to ground (the ON pulse width t

to RFA2

PW1

PW2

is set at 1.1 times the pulse width to RFA1 in the low data rate mode). The

ON pulse width t can be adjusted between 0.55 and 1 µs. However,

PW1

when the PWIDTH pin is connected to Vcc through a 1 M resistor, the RF

amplifiers operate at a nominal 50%-50% duty cycle, facilitating high data

rate operation. In this case, the RF amplifiers are controlled by the PRATE

resistor as described above.

Data slicer DS2 can overcome this compromise once the signal level is

high enough to enable its operation. DS2 is a “dB-below- peak” slicer. The

peak detector charges rapidly to the peak value of each data pulse, and de-

cays slowly in between data pulses (1:1000 ratio). The slicer trip point can

be set from 0 to 120 mV below this peak value with a resistor between

RREF and THLD2. A threshold of 60 mV is the most common setting,

which equates to “6 dB below peak” when RFA1 and RFA2 are running a

50%-50% duty cycle. Slicing at the “6 dB-below-peak” point reduces the

signal amplitude to data pulse-width variation, allowing a lower 3 dB filter

bandwidth to be used for improved sensitivity.

Both receiver RF amplifiers are turned off by the Power Down Control Sig-

nal, which is invoked in the sleep mode.

Receiver Mode Control

The receiver operating modes – receive and power-down (sleep), are con-

trolled by the Bias Control function, and are selected with the CNTRL1 and

CNTRL0 control pins. Setting CNTRL1 and CNTRL0 both high place the

unit in the receive mode. Setting CNTRL1 and CNTRL0 both low place the

unit in the power-down (sleep) mode. CNTRL1 and CNTRL0 are CMOS

compatible inputs. These inputs must be held at a logic level; they cannot

be left unconnected.

DS2 is best for ASK modulation where the transmitted waveform has been

shaped to minimize signal bandwidth. However, DS2 is subject to being

temporarily “blinded” by strong noise pulses, which can cause burst data

errors. Note that DS1 is active when DS2 is used, as RXDATA is the logical

AND of the DS1 and DS2 outputs. DS2 can be disabled by leaving THLD2

disconnected. A non-zero DS1 threshold is required for proper AGC oper-

ation.

Receiver Event Timing

Receiver event timing is summarized in Table 1. Please refer to this table

for the following discussions.

Turn-On Timing

The maximum time t required for the receive function to become opera-

tional at turn on is influenced by two factors. All receiver circuitry will be op-

erational 5 ms after the supply voltage reaches 2.2 Vdc. The BBOUT-

CMPIN coupling-capacitor is then DC stabilized in 3 time constants

AGC Control

The output of the Peak Detector also provides an AGC Reset signal to the

AGC Control function through the AGC comparator. The purpose of the

AGC function is to extend the dynamic range of the receiver, so that the re-

ceiver can operate close to its transmitter when running ASK and/or high

data rate modulation. The onset of saturation in the output stage of RFA1

is detected and generates the AGC Set signal to the AGC Control function.

The AGC Control function then selects the 5 dB gain mode for RFA1. The

AGC Comparator will send a reset signal when the Peak Detector output

(multiplied by 0.8) falls below the threshold voltage for DS1.

(3*t

). The total turn-on time to stable receiver operation for a 10 ms

BBC

power supply rise time is:

= 15 ms + 3*t

BBC

Sleep and Wake-Up Timing

The maximum transition time from the receive mode to the power-down

(sleep) mode t is 10 µs after CNTRL1 and CNTRL0 are both low (1 µs

fall time).

A capacitor at the AGCCAP pin avoids AGC “chattering” during the time it

takes for the signal to propagate through the low-pass filter and charge the

peak detector. The AGC capacitor also allows the hold-in time to be set

longer than the peak detector decay time to avoid AGC chattering during

runs of “0” bits in the received data stream. Note that AGC operation re-

quires the peak detector to be functioning, even if DS2 is not being used.

AGC operation can be defeated by connecting the AGCCAP pin to Vcc.

The AGC can be latched on once engaged by connecting a 150 kilohm re-

sistor between the AGCCAP pin and ground in lieu of a capacitor.

The maximum transition time t from the sleep mode to the receive mode

is 3*t

, where t

is the BBOUT-CMPIN coupling-capacitor time con-

BBC

stant. When the operating temperature is limited to 60 oC, the time required

to switch from sleep to receive is dramatically less for short sleep times, as

less charge leaks away from the BBOUT- CMPIN coupling capacitor.

AGC Timing

The maximum AGC engage time t

is 5 µs after the reception of a -30

AGC

dBm RF signal with a 1 µs envelope rise time.

Receiver Pulse Generator and RF Amplifier Bias

The minimum AGC hold-in time is set by the value of the capacitor at the

AGCCAP pin. The hold-in time t

= C

/19.1, where t is in µs and

AGH

The receiver amplifier-sequence operation is controlled by the Pulse Gen-

erator & RF Amplifier Bias module, which in turn is controlled by the

PRATE and PWIDTH input pins, and the Power Down (sleep) Control Sig-

nal from the Bias Control function.

AGH

AGC

is in pF.

AGC

RF Monolithics, Inc.

RFM Europe

Phone: (972) 233-2903

Phone: 44 1963 251383

Fax: (972) 387-8148

Fax: 44 1963 251510

E-mail: info@rfm.com

http://www.rfm.com

RX6000-062905

Page 6 of 10

Peak Detector Timing

In the low data rate mode, the PWIDTH pin sets the width of the ON pulse

to the first RF amplifier t with a resistor R to ground (the ON pulse

PW1

The Peak Detector attack time constant is set by the value of the capacitor

at the PKDET pin. The attack time t

width to the second RF amplifier t

is set at 1.1 times the pulse width to

PW2

= C

/4167, where

PKA

PKD

the first RF amplifier in the low data rate mode). The ON pulse width t

PW1

is in µs and C

is in pF. The Peak Detector decay time

PKA

PKD

can be adjusted between 0.55 and 1 µs with a resistor value in the range

constant t

= 1000*t

PKA

PKD

of 200 K to 390 K. The value of R

is given by:

Pulse Generator Timing

In the low data rate mode, the interval t

ON pulse to the first RF amplifier and the rising edge of the next ON pulse

to the first RF amplifier is set by a resistor R between the PRATE pin and

ground. The interval can be adjusted between 0.1 and 5 µs with a resistor

in the range of 51 K to 2000 K. The value of the R is given by:

= 404* t

- 18.6, where t

is in µs and R

is in kilohms

PW1

between the falling edge of an

PRI

However, when the PWIDTH pin is connected to Vcc through a 1 M resis-

tor, the RF amplifiers operate at a nominal 50%-50% duty cycle, facilitating

high data rate operation. In this case, the RF amplifiers are controlled by

the PRATE resistor as described above.

LPF Group Delay

= 404* t

+ 10.5, where t

is in µs, and R is in kilohms

PRI PR

PRI

The low-pass filter group delay is a function of the filter 3 dB bandwidth,

In the high data rate mode (selected at the PWIDTH pin) the receiver RF

amplifiers operate at a nominal 50%-50% duty cycle. In this case, the peri-

which is set by a resistor R

to ground at the LPFADJ pin. The minimum

LPF

3 dB bandwidth f

hms.

= 1445/R , where f

is in kHz, and R

is in kilo-

LPF

od t

from the start of an ON pulse to the first RF amplifier to the start of

PRC

the next ON pulse to the first RF amplifier is controlled by the PRATE re-

sistor over a range of 0.1 to 1.1 µs using a resistor of 11 K to 220 K. In this

The maximum group delay t

= 1750/f

= 1.21*R , where t

is in

FGD

LPF

case R is given by:

µs, f

in kHz, and R

in kilohms.

LPF

= 198* t

- 8.51, where t

is in µs and R is in kilohms

PRC PR

PRC

Receiver Event Timing, 3.0 Vdc, -40 to +85 °C

Event

Symbol

Time

+ 15 ms

BBC

Min/Max

Test Conditions

10 ms supply voltage rise time

1 µs CNTRL0/CNTROL 1 rise times

Notes

Turn On to Receive

3*t

max

time until receiver operational

Sleep to RX

3*t

max

min

BBC

RX to Sleep

10 µs

5 µs

1 µs CNTRL0/CNTROL 1 fall times time until receiver is in power-down mode

1 µs rise time, -30 dBm signal RFA1 switches from 35 to 5 dB gain

AGC Engage

AGC

AGH

AGE Hold-In

/19.1

CAGC in pF, t

in µs

user selected; longer than t

user selected

AGC

AGH

PKD

PKDET Attack Time Constant

PKDET Decay Time Constant

PRATE Interval

/4167

min

in pF, t

PKD

PKA

PKD

PKA

1000*t

min

and t in µs

PKA

slaved to attack time

user selected mode

user selected

PKA

PKD

0.1 to 5 µs

range

max

min

low data rate mode

high data rate mode

PRI

PW1

PW2

PWIDTH RFA1

0.55 to 1 µs

PWIDTH RFA2

1.1*t

PW1

PRATE Cycle

0.1 to 1.1 µs

PRC

PWIDTH High (RFA1 & RFA2)

LPF Group Delay

0.05 to 0.55 µs

PWH

1750/f

in µs, f

in kHz

LPF

FGD

LPF

FGD

LPF 3 dB Bandwidth

BBOUT-CMPIN Time Constant

1445/R

in kHz, R in kilohms

LPF

user selected

LPF

0.064*C

min

in µs, C in pF

BBO

user selected

BBC

BBO

BBC

Table 1

RF Monolithics, Inc.

RFM Europe

Phone: (972) 233-2903

Phone: 44 1963 251383

Fax: (972) 387-8148

Fax: 44 1963 251510

E-mail: info@rfm.com

http://www.rfm.com

RX6000-062905

Page 7 of 10

Pin Descriptions

Name

Description

GND1

VCC1

GND1 is the RF ground pin. GND2 and GND3 should be connected to GND1 by short, low-inductance traces.

VCC1 is the positive supply voltage pin for the receiver base-band circuitry. VCC1 must be bypassed by an RF capacitor,

which may be shared with VCC2. See the description of VCC2 (Pin 16) for additional information.

This pin controls the AGC reset operation. A capacitor between this pin and ground sets the minimum time the AGC will

hold-in once it is engaged. The hold-in time is set to avoid AGC chattering. For a given hold-in time t

, the capacitor

AGH

value C

is:

AGC

= 19.1* t

, where t

is in µs and C

is in pF

AGC

AGH

A ±10% ceramic capacitor should be used at this pin. The value of C

given above provides a hold-in time between t

AGH

AGC

and 2.65* t

, depending on operating voltage, temperature, etc. The hold-in time is chosen to allow the AGC to ride

AGH

through the longest run of zero bits that can occur in a received data stream. The AGC hold-in time can be greater than the

peak detector decay time, as discussed below. However, the AGC hold-in time should not be set too long, or the receiver

will be slow in returning to full sensitivity once the AGC is engaged by noise or interference. The use of AGC is optional

when using OOK modulation with data pulses of at least 30 µs. AGC operation can be defeated by connecting this pin to

Vcc. Active or latched AGC operation is required for ASK modulation and/or for data pulses of less than 30 µs. The AGC

can be latched on once engaged by connecting a 150 K resistor between this pin and ground, instead of a capacitor. AGC

operation depends on a functioning peak detector, as discussed below. The AGC capacitor is discharged in the receiver

power-down (sleep) mode.

AGCCAP

This pin controls the peak detector operation. A capacitor between this pin and ground sets the peak detector attack and

decay times, which have a fixed 1:1000 ratio. For most applications, these time constants should be coordinated with the

base-band time constant. For a given base-band capacitor C

, the capacitor value C

is:

BBO

PKD

= 0.33* C

, where C

and C

are in pF

PKD

BBO

A ±10% ceramic capacitor should be used at this pin. This time constant will vary between t

and 1.5* t

with varia-

PKA

PKDET

tions in supply voltage, temperature, etc. The capacitor is driven from a 200 ohm “attack” source, and decays through a

200 K load. The peak detector is used to drive the “dB-below-peak” data slicer and the AGC release function. The AGC

hold-in time can be extended beyond the peak detector decay time with the AGC capacitor, as discussed above. Where

low data rates and OOK modulation are used, the “dB-below-peak” data slicer and the AGC are optional. In this case, the

PKDET pin and the THLD2 pin can be left unconnected, and the AGC pin can be connected to Vcc to reduce the number

of external components needed. The peak detector capacitor is discharged in the receiver power-down (sleep) mode.

BBOUT is the receiver base-band output pin. This pin drives the CMPIN pin through a coupling capacitor C

for internal

BBO

data slicer operation. The time constant t

for this connection is:

BBC

= 0.064*C

, where t

is in µs and C

is in pF

BBO

BBC

BBO

BBC

A ±10% ceramic capacitor should be used between BBOUT and CMPIN. The time constant can vary between t

and

BBC

1.8*t

with variations in supply voltage, temperature, etc. The optimum time constant in a given circumstance will

BBC

depend on the data rate, data run length, and other factors as discussed in the ASH Transceiver Designer’s Guide. A com-

mon criteria is to set the time constant for no more than a 20% voltage droop during SP . For this case:

MAX

= 70*SP

, where SP

is the maximum signal pulse width in µs and C

is in pF

BBO

MAX

BBOUT

The output from this pin can also be used to drive an external data recovery process (DSP, etc.). The nominal output

impedance of this pin is 1 K. When the receiver RF amplifiers are operating at a 50%-50% duty cycle, the BBOUT signal

changes about 10 mV/dB, with a peak-to-peak signal level of up to 685 mV. For lower duty cycles, the mV/dB slope and

peak-to-peak signal level are proportionately less. The signal at BBOUT is riding on a 1.1 Vdc value that varies somewhat

with supply voltage and temperature, so it should be coupled through a capacitor to an external load. A load impedance of

50 K to 500 K in parallel with no more than 10 pF is recommended. When an external data recovery process is used with

AGC, BBOUT must be coupled to the external data recovery process and CMPIN by separate series coupling capacitors.

The AGC reset function is driven by the signal applied to CMPIN. When the receiver is in power-down (sleep) mode, the

output impedance of this pin becomes very high, preserving the charge on the coupling capacitor.

This pin is the input to the internal data slicers. It is driven from BBOUT through a coupling capacitor. The input impedance

of this pin is 70 K to 100 K.

CMPIN

RXDATA is the receiver data output pin. This pin will drive a 10 pF, 500 K parallel load. The peak current available from

this pin increases with the receiver low-pass filter cutoff frequency. In the power-down (sleep) mode, this pin becomes high

impedance. If required, a 1000 K pull-up or pull-down resistor can be used to establish a definite logic state when this pin

is high impedance. If a pull-up resistor is used, the positive supply end should be connected to a voltage no greater than

Vcc + 200 mV.

RXDATA

This pin may be left unconnected or may be grounded.

RF Monolithics, Inc.

RFM Europe

Phone: (972) 233-2903

Phone: 44 1963 251383

Fax: (972) 387-8148

Fax: 44 1963 251510

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RX6000-062905

Page 8 of 10

Name

Description

This pin is the receiver low-pass filter bandwidth adjust. The filter bandwidth is set by a resistor R

ground. The resistor value can range from 330 K to 820 ohms, providing a filter 3 dB bandwidth f

MHz. The resistor value is determined by:

between this pin and

from 4.5 kHz to 1.8

LPF

= 1445/ f , where R

is in kilohms, and f

is in kHz

LPF

LPFADJ

LPF

A ±5% resistor should be used to set the filter bandwidth. This will provide a 3 dB filter bandwidth between f

and 1.3*

LPF

with variations in supply voltage, temperature, etc. The filter provides a three-pole, 0.05 degree equiripple phase

LPF

response. The peak drive current available from RXDATA increases in proportion to the filter bandwidth setting.

GND2

RREF

GND2 is an IC ground pin. It should be connected to GND1 by a short, low inductance trace.

RREF is the external reference resistor pin. A 100 K reference resistor is connected between this pin and ground. A ±1%

resistor tolerance is recommended. It is important to keep the total capacitance between ground, Vcc and this node to less

than 5 pF to maintain current source stability. If THLD1 and/or THDL2 are connected to RREF through resistor values less

that 1.5 K, their node capacitance must be added to the RREF node capacitance and the total should not exceed 5 pF.

THLD2 is the “dB-below-peak” data slicer (DS2) threshold adjust pin. The threshold is set by a 0 to 200 K resistor R

TH2

between this pin and RREF. Increasing the value of the resistor decreases the threshold below the peak detector value

(increases difference) from 0 to 120 mV. For most applications, this threshold should be set at 6 dB below peak, or 60 mV

for a 50%-50% RF amplifier duty cycle. The value of the THLD2 resistor is given by:

THLD2

= 1.67*V, where R

is in kilohms and the threshold V is in mV

TH2

A ±1% resistor tolerance is recommended for the THLD2 resistor. Leaving the THLD2 pin open disables the dB-below-

peak data slicer operation.

The THLD1 pin sets the threshold for the standard data slicer (DS1) through a resistor R

to RREF. The threshold is

TH1

increased by increasing the resistor value. Connecting this pin directly to RREF provides zero threshold. The value of the

resistor depends on whether THLD2 is used. For the case that THLD2 is not used, the acceptable range for the resistor is

0 to 100 K, providing a THLD1 range of 0 to 90 mV. The resistor value is given by:

= 1.11*V, where R

is in kilohms and the threshold V is in mV

TH1

THLD1

For the case that THLD2 is used, the acceptable range for the THLD1 resistor is 0 to 200 K, again providing a THLD1

range of 0 to 90 mV. The resistor value is given by:

= 2.22*V, where R

is in kilohms and the threshold V is in mV

TH1

A ±1% resistor tolerance is recommended for the THLD1 resistor. Note that a non-zero DS1 threshold is required for

proper AGC operation.

The interval between the falling edge of an ON pulse to the first RF amplifier and the rising edge of the next ON pulse to

the first RF amplifier t

is set by a resistor R between this pin and ground. The interval t

can be adjusted between

PRI

0.1 and 5 µs with a resistor in the range of 51 K to 2000 K. The value of R is given by:

= 404* t

+ 10.5, where t

is in µs, and R is in kilohms

PRI PR

PRI

A ±5% resistor value is recommended. When the PWIDTH pin is connected to Vcc through a 1 M resistor, the RF amplifi-

ers operate at a nominal 50%-50% duty cycle, facilitating high data rate operation. In this case, the period t from start-

PRC

PRATE

to-start of ON pulses to the first RF amplifier is controlled by the PRATE resistor over a range of 0.1 to 1.1 µs using a resis-

tor of 11 K to 220 K. In this case the value of R is given by:

= 198* t

- 8.51, where t

is in µs and R is in kilohms

PRC PR

PRC

A ±5% resistor value should also be used in this case. Please refer to the ASH Transceiver Designer’s Guide for additional

amplifier duty cycle information. It is important to keep the total capacitance between ground, Vcc and this pin to less than

5 pF to maintain stability.

The PWIDTH pin sets the width of the ON pulse to the first RF amplifier t

with a resistor R

to ground (the ON pulse

PW1

width to the second RF amplifier t

is set at 1.1 times the pulse width to the first RF amplifier). The ON pulse width t

PW1

PW2

can be adjusted between 0.55 and 1 µs with a resistor value in the range of 200 K to 390 K. The value of R

is given by:

= 404* t

- 18.6, where t

is in µs and R

is in kilohms

PW1

PWIDTH

A ±5% resistor value is recommended. When this pin is connected to Vcc through a 1 M resistor, the RF amplifiers operate

at a nominal 50%-50% duty cycle, facilitating high data rate operation. In this case, the RF amplifier ON times are con-

trolled by the PRATE resistor as described above. It is important to keep the total capacitance between ground, Vcc and

this node to less than 5 pF to maintain stability. When using the high data rate operation with the sleep mode, connect the

1 M resistor between this pin and CNTRL1 (Pin 17), so this pin is low in the sleep mode.

VCC2 is the positive supply voltage pin for the receiver RF section. This pin must be bypassed with an RF capacitor, which

may be shared with VCC1. VCC2 must also be bypassed with a 1 to 10 µF tantalum or electrolytic capacitor.

VCC2

RF Monolithics, Inc.

RFM Europe

Phone: (972) 233-2903

Phone: 44 1963 251383

Fax: (972) 387-8148

Fax: 44 1963 251510

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http://www.rfm.com

RX6000-062905

Page 9 of 10

Name

Description

CNTRL1 and CNTRL0 select the receiver modes. CNTRL1 and CNTRL0 both high place the unit in the receive mode.

CNTRL1 and CNTRL0 both low place the unit in the power-down (sleep) mode. CNTRL1 is a high-impedance input

(CMOS compatible). An input voltage of 0 to 300 mV is interpreted as a logic low. An input voltage of Vcc - 300 mV or

greater is interpreted as a logic high. An input voltage greater than Vcc + 200 mV should not be applied to this pin. A logic

high requires a maximum source current of 40 µA. Sleep mode requires a maximum sink current of 1 µA. This pin must be

held at a logic level; it cannot be left unconnected.

CNTRL1

CNTRL0 is used with CNTRL1 to control the receiver modes. CNTRL0 is a high-impedance input (CMOS compatible). An

input voltage of 0 to 300 mV is interpreted as a logic low. An input voltage of Vcc - 300 mV or greater is interpreted as a

logic high. An input voltage greater than Vcc + 200 mV should not be applied to this pin. A logic high requires a maximum

source current of 40 µA. Sleep mode requires a maximum sink current of 1 µA. This pin must be held at a logic level; it can-

not be left unconnected.

CNTRL0

GND3

RFIO

GND3 is an IC ground pin. It should be connected to GND1 by a short, low inductance trace.

RFIO is the receiver RF input pin. This pin is connected directly to the SAW filter transducer. Antennas presenting an

impedance in the range of 35 to 72 ohms resistive can be satisfactorily matched to this pin with a series matching coil and

a shunt matching/ESD protection coil. Other antenna impedances can be matched using two or three components. For

some impedances, two inductors and a capacitor will be required. A DC path from RFIO to ground is required for ESD pro-

tection.

.435

.370

.345

.305

.265

.225

.185

.145

.105

.09

.065

0.000

Dimensions in inches.

SM-20H PCB Pad Layout

Note: Specifications subject to change without notice.

RF Monolithics, Inc.

RFM Europe

Phone: (972) 233-2903

Phone: 44 1963 251383

Fax: (972) 387-8148

Fax: 44 1963 251510

E-mail: info@rfm.com

http://www.rfm.com

RX6000-062905

Page 10 of 10

RX6000 [RFM]

相关型号：

RX6000-XXX

RX6001

RX6004

RX610

RX621

RX62G

RX62N

RX62N_12

RX62T

RX6501

RX7000

RX703000