LVMDM-35J [RHOMBUS-IND]
LVMDM Series LVC Low Voltage Logic Buffered 5-Tap Delay SMD Modules; LVMDM LVC系列低电压逻辑缓冲5 - tap延迟SMD模块
| 型号： | LVMDM-35J |
| 厂家： | 
Rhombus Industries Inc. |
| 描述： | LVMDM Series LVC Low Voltage Logic Buffered 5-Tap Delay SMD Modules |
| 文件： | 总1页 (文件大小：36K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Inputs accept voltages up to 5.5 V
LVMDM Series LVC Low Voltage Logic
Buffered 5-Tap Delay SMD Modules
74LVC type input can bedriven from either 3.3V or 5V
devices. This allows delay module to serve as a
translator in a mixed 3.3V / 5V system environment.
Electrical Specifications at 25OC
Low Profile 8-Pin Package
LVC 5 Tap
Tap 1
Tap 2
( ns )
Tap 3
( ns )
Tap 4
( ns )
Tap 5
( ns )
Tap-to-Tap
(ns)
Two Surface Mount Versions
( ns )
SMD P/N
Low Voltage CMOS 74LVC
Logic Buffered
LVMDM-7G
LVMDM-9G
LVMDM-11G
LVMDM-13G
LVMDM-15G
LVMDM-20G
LVMDM-25G
LVMDM-30G
LVMDM-35G
LVMDM-40G
LVMDM-45G
LVMDM-50G
LVMDM-60G
LVMDM-75G
LVMDM-80G
3.0 ± 1.0
3.0 ± 1.0
3.0 ± 1.0
3.0 ± 1.0
3.0 ± 1.0
4.0 ± 1.0
5.0 ± 1.0
6.0 ± 1.0
7.0 ± 1.0
8.0 ± 1.0
9.0 ± 1.0
10.0 ± 1.5
12.0 ± 1.5
15.0 ± 2.0
16.0 ± 2.0
4.0 ± 1.0
4.5 ± 1.0
5.0 ± 1.0
5.5 ± 1.0
6.0 ± 1.0
8.0 ± 1.2
10.0 ± 1.5
12.0 ± 1.5
14.0 ± 1.5
16.0 ± 1.5
18.0 ± 1.5
20.0 ± 2.0
24.0 ± 2.0
5.0 ± 1.0
6.0 ± 1.0
7.0 ± 1.0
8.0 ± 1.0
9.0 ± 1.0
12.0 ± 1.5
15.0 ± 1.5
18.0 ± 1.5
21.0 ± 2.0
24.0 ± 2.0
27.0 ± 2.0
30.0 ± 2.0
36.0 ± 2.0
6.0 ± 1.0
7.5 ± 1.0
7 ± 1.0
9 ± 1.0
1.0 ± 0.4
1.5 ± 0.5
2.0 ± 0.6
2.5 ± 0.8
3.0 ± 1.0
4.0 ± 1.0
5.0 ± 1.5
6.0 ± 1.5
7.0 ± 1.8
8.0 ± 2.0
9.0 ± 2.0
10 ± 2.0
12 ± 2.0
15 ± 2.5
16 ± 2.5
20 ± 3.0
5 Equal Delay Taps
Operating Temp. -40OC to +85OC
9.0 ± 1.0
11 ± 1.5
13 ± 1.5
15 ± 1.5
20 ± 2.0
25 ± 2.0
30 ± 2.0
35 ± 2.0
40 ± 2.0
45 ± 2.25
50 ± 2.5
60 ± 3.0
75 ± 3.75
80 ± 4.0
100 ± 5.0
10.5 ± 1.0
12.0 ± 1.5
16.0 ± 1.5
20.0 ± 2.0
24.0 ± 2.0
28.0 ± 2.0
32.0 ± 2.0
36.0 ± 2.0
40.0 ± 2.0
48.0 ± 2.4
LVMDM 8-Pin Schematic
Vcc
Tap1 Tap3 Tap5
8
7
6
5
30.0 ± 2.0 45.0 ± 2.25 60.0 ± 3.0
32.0 ± 2.0
40.0 ± 2.0
48.0 ± 2.4
60.0 ± 3.0
64.0 ± 3.2
80.0 ± 2.0
1
2
3
4
LVMDM-100G 20.0 ± 2.0
GND
IN
Tap2 Tap4
** These part numbers do not have 5 equal taps. Tap-to-Tap Delays reference Tap 1.
TEST CONDITIONS -- Low Voltage CMOS, LVC
Dimensions in Inches (mm)
VCC Supply Voltage................................................ 3.30VDC
Input Pulse Voltage ................................................... 2.70V
Input Pulse Rise Time ....................................... 3.0 ns max.
Input Pulse Width / Period ........................... 1000 / 2000 ns
1. Measurements made at 25OC
.285
.505
(12.83)
MAX.
(7.24)
MAX.
.020
(0.51)
TYP.
.250
DIP
DIP
(6.35)
MAX.
2. Delay Times measured at 1.50V level of leading edge.
3. Rise Times measured from 0.75V to 2.40V.
4. 50pf probe and fixture load on output under test.
.010
(0.25)
TYP.
.120
(3.05)
MIN.
.300
(7.62)
OPERATING SPECIFICATIONS
.365
.020 .050
.100
(9.27)
MAX.
(0.51)
TYP.
(2.54)
(1.27)
Supply Voltage, VCC .......................................... 3.3 ± 0.3 VDC
Supply Current, ICC ........................... 10 mA typ., 30 mA max.
Supply Current, ICCL : VIN = GND ......................... 22 mA max.
Supply Current, ICCH : VIN = VCC ............................. 10 µA max.
Input Voltage, VI ..................................... 0 V min., 5.5 V max.
Logic “1” Input, VIH .................................................. 2.0 V min.
Logic “0” Input, VIL ................................................. 0.8 V max.
Logic “1” Out, VOH: VCC = 3V & IOH = -24 mA ............ 2.0 V min.
Logic “0” Out, VOL: VCC = 3V & IOL = 24 mA ......... 0.55 V max.
Input Capacitance, CI ............................................. 5 pF, typ.
Input Pulse Width, PWI .............................. 40% of Delay min.
Operating Temperature Range ......................... -40O to +85OC
Storage Temperature Range ........................ -65O to +150OC
TYP. TYP.
.285
(7.24)
MAX.
.505
(12.83)
MAX.
.250
(6.35)
MAX.
G-SMD
G-SMD
.008 R
(0.20)
.010
(0.25)
TYP.
.030
(0.76)
TYP.
.015
(0.38)
TYP.
.020 .050
.100
(2.54)
TYP.
.430 (10.92)
.400 (10.16)
(0.51)
(1.27)
TYP. TYP.
.285
(7.24)
MAX.
.505
(12.83)
MAX.
P/ N De sc rip tion
LVMDM - XXX X
LVC Buffered 5 Tap Delay
Molded Package Series:
.265
(6.73)
MAX.
J-SMD
J-SMD
8-pin DIP: LVMDM
Total Delay in nanoseconds (ns)
.285 (7.24)
.260 (6.60)
.020 R
(0.51)
.030
(0.76)
TYP.
Lead Style: Blank = Thru-hole
G = “Gull Wing” SMD
J = “J” Bend SMD
.020 .050
.100
(2.54)
TYP.
.330 (8.38)
MAX.
(0.51)
TYP.
(1.27)
TYP.
Examples: LVMDM-25G = 25ns (5ns per tap) 74LVC, 8-Pin G-SMD
LVMDM-100 = 100ns (20ns per tap) 74LVC, 8-Pin DIP
www.rhombus-ind.com
sales@rhombus-ind.com
18
TEL: (714) 898-0960
FAX: (714) 896-0971
LVMDM 2001-01
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