C3225X5R0J476M [RICHTEK]
2A, 18V, 800kHz Synchronous Step-Down Converter; 2A ， 18V ， 800kHz的同步降压型转换器
| 型号： | C3225X5R0J476M |
| 厂家： | 
RICHTEK TECHNOLOGY CORPORATION |
| 描述： | 2A, 18V, 800kHz Synchronous Step-Down Converter |
| 文件： | 总15页 (文件大小：277K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
®
RT7247C
2A, 18V, 800kHz Synchronous Step-Down Converter
General Description
Features
z
1.5% High Accuracy Reference Voltage
The RT7247C is a high efficiency, monolithic synchronous
step-down DC/DC converter that can deliver up to 2A
output current from a 4.5V to 18V input supply. The
RT7247C's current mode architecture and external
compensation allow the transient response to be
optimized over a wide input range and loads. Cycle-by-
cycle current limit provides protection against shorted
outputs, and soft-start eliminates input current surge during
start-up. The RT7247C also provides under voltage
protection and thermal shutdown protection. The low
current (<3μA) shutdown mode provides output
disconnection, enabling easy power management in
battery-powered systems. The RT7247C is available in
an SOP-8 (Exposed Pad) package.
z 4.5V to 18V Input Voltage Range
z 2A Output Current
z Integrated N-MOSFET Switches
z Current Mode Control
z Fixed Frequency Operation : 800kHz
z Output Adjustable from 0.8V to 12V
z Stable with Low ESR Ceramic Output Capacitors
z Up to 95% Efficiency
z Programmable Soft-Start
z Cycle-by-Cycle Over Current Limit
z Input Under Voltage Lockout
z Output Under Voltage Protection
z Thermal Shutdown Protection
z RoHS Compliant and Halogen Free
Marking Information
Applications
RT7247CHGSP : Product Number
z Wireless AP/Router
RT7247CH
GSPYMDNN
YMDNN : Date Code
z Set-Top-Box
z Industrial and Commercial Low Power Systems
z LCDMonitors and TVs
z Green Electronics/Appliances
z Point of Load Regulation of High-PerformanceDSPs
Simplified Application Circuit
BOOT
RT7247C
VIN
V
IN
C
BOOT
C
IN
L
SW
V
OUT
Chip Enable
R1
R2
EN
SS
C
OUT
FB
C
SS
C
C
R
C
GND
COMP
C
P
Copyright 2012 Richtek Technology Corporation. All rights reserved.
©
is a registered trademark of Richtek Technology Corporation.
DS7247C-02 September 2012
www.richtek.com
1
®
RT7247C
Ordering Information
RT7247C
Pin Configurations
(TOP VIEW)
Package Type
SP : SOP-8 (Exposed Pad-Option 2)
8
7
6
5
BOOT
VIN
SS
2
3
4
EN
GND
Lead Plating System
G : Green (Halogen Free and Pb Free)
SW
COMP
FB
9
GND
H : UVP Hiccup
SOP-8 (Exposed Pad)
Note :
Richtek products are :
` RoHS compliant and compatible with the current require-
ments of IPC/JEDEC J-STD-020.
` Suitable for use in SnPb or Pb-free soldering processes.
Functional Pin Description
Pin No.
Pin Name
Pin Function
Bootstrap for High Side Gate Driver. Connect a 0.1μF or greater ceramic
capacitor from BOOT to SW pins.
1
BOOT
Power Input. The Input Voltage range is from 4.5V to 18V. Must bypass with a
suitable large ceramic capacitor.
2
3
VIN
SW
Switch Node. Connect this pin to an external L-C filter.
4,
Ground. The exposed pad must be soldered to a large PCB and connected to
GND for maximum power dissipation.
GND
9 (Exposed Pad)
Feedback Input. It is used to regulate the output of the converter to a set value
via an external resistive voltage divider.
5
6
7
8
FB
Compensation Node. COMP is used to compensate the regulation control
loop. Connect a series RC network from COMP to GND. In some cases, an
additional capacitor from COMP to GND is required.
COMP
EN
Enable Input. A logic high enables the converter; a logic low forces the IC into
shutdown mode reducing the supply current to less than 3μA.
Soft-Start Control Input. SS controls the soft-start period. Connect a capacitor
from SS to GND to set the soft-start period. A 0.1μF capacitor sets the
soft-start period to 13.5ms.
SS
Copyright 2012 Richtek Technology Corporation. All rights reserved.
©
is a registered trademark of Richtek Technology Corporation.
DS7247C-02 September 2012
www.richtek.com
2
®
RT7247C
Function Block Diagram
VIN
Internal
Regulator
Oscillator
Current Sense
Amplifier
Slope Comp
Shutdown
Comparator
V
V
CC
A
+
V
A
Foldback
R
SENSE
-
Control
1.2V
+
-
0.4V
+
BOOT
SW
Lockout
Comparator
-
S
Q
Q
150mΩ
130mΩ
UV
5kΩ
Comparator
-
EN
+
R
-
+
1.8V
Current
GND
Comparator
V
CC
6µA
0.8V
+
+
-
EA
SS
FB
COMP
Operation
Foldback Control
Internal Regulator
Dynamically adjust the internal clock. It provides a slower
frequency as a lower FB voltage.
Provide internal power for logic control and switch gate
drivers.
UV Comparator
Shutdown Comparator
As FB voltage is lower than the UV voltage, it will activate
a UV protect scheme.
Activate internal regulator once EN input level is higher
than the target level. Force IC to enter shutdown mode
when the EN input level is lower than 0.4V.
Error Amplifier
The output voltage COMP of the error amplifier is adjusted
by comparing FB signal with the internal reference voltage
and SS signal.
Lockout Comparator
Activate the current comparator, release lock-out logic,
and enable the switches as EN input level is higher than
lockout threshold voltage. Otherwise, the switches still
lock out.
Current Sense Amplifier
RSENSE detects the peak current of the high side switch.
This signal is amplified by the current sense amplifier and
added with a slope compensation signal. Then, It controls
the switches by comparing this signal with the COMP
voltage.
Oscillator
The oscillator provides internal clock and controls the
converter's switching frequency.
Copyright 2012 Richtek Technology Corporation. All rights reserved.
©
is a registered trademark of Richtek Technology Corporation.
DS7247C-02 September 2012
www.richtek.com
3
RT7247C
Absolute Maximum Ratings (Note 1)
z Supply Input Voltage, VIN ----------------------------------------------------------------------------------------- −0.3V to 20V
z Switch Voltage, SW ------------------------------------------------------------------------------------------------ −0.3V to (VIN + 0.3V)
z VBOOT − VSW ---------------------------------------------------------------------------------------------------------- −0.3V to 6V
z Other Pins Voltage ------------------------------------------------------------------------------------------------- −0.3V to 20V
z Power Dissipation, PD @ TA = 25°C
SOP-8 (Exposed Pad) --------------------------------------------------------------------------------------------- 1.333W
z Package Thermal Resistance (Note 2)
SOP-8 (Exposed Pad), θJA ---------------------------------------------------------------------------------------- 75°C/W
SOP-8 (Exposed Pad), θJC --------------------------------------------------------------------------------------- 15°C/W
z Lead Temperature (Soldering, 10 sec.)------------------------------------------------------------------------- 260°C
z Junction Temperature ----------------------------------------------------------------------------------------------- 150°C
z Storage Temperature Range -------------------------------------------------------------------------------------- −65°C to 150°C
z ESD Susceptibility (Note 3)
HBM (Human Body Model)---------------------------------------------------------------------------------------- 2kV
Recommended Operating Conditions (Note 4)
z Supply Input Voltage, VIN ----------------------------------------------------------------------------------------- 4.5V to 18V
z Junction Temperature Range-------------------------------------------------------------------------------------- −40°C to 125°C
z Ambient Temperature Range-------------------------------------------------------------------------------------- −40°C to 85°C
Electrical Characteristics
(VIN = 12V, TA = 25°C, unless otherwise specified)
Parameter
Shutdown Supply Current
Supply Current
Symbol
Test Conditions
Min
--
Typ
0.5
0.8
0.8
Max
3
Unit
μA
mA
V
VEN = 0V
VEN = 3V, VFB = 0.9V
--
1.2
Reference Voltage
VREF
GEA
4.5V ≤ VIN ≤ 18V
0.788
0.812
Error Amplifier
ΔIC = ±10μA
--
--
--
940
150
130
--
--
--
μA/V
mΩ
Transconductance
High Side Switch
On-Resistance
Low Side Switch
On-Resistance
High Side Switch Leakage
Current
RDS(ON)1
RDS(ON)2
mΩ
VEN = 0V, VSW = 0V
--
--
--
--
--
0
10
--
μA
A
Upper Switch Current Limit
Min. Duty Cycle, VBOOT − VSW = 4.8V
5.1
3.7
800
270
COMP to Current Sense
Transconductance
GCS
--
A/V
kHz
kHz
Oscillation Frequency
fOSC1
fOSC2
--
Short Circuit Oscillation
Frequency
VFB = 0V
--
Maximum Duty Cycle
Minimum On-Time
DMAX
tON
VFB = 0.7V
--
--
84
--
--
%
100
ns
Copyright 2012 Richtek Technology Corporation. All rights reserved.
©
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
4
DS7247C-02 September 2012
RT7247C
Parameter
Logic-High VIH
Logic-Low VIL
Symbol
Test Conditions
Min
2
Typ
--
Max
18
Unit
EN Input Threshold
Voltage
V
--
--
0.4
Input Under Voltage Lockout
Threshold
Input Under Voltage Lockout
Hysteresis
VUVLO
VIN Rising
3.8
--
4.2
4.5
--
V
ΔVUVLO
320
mV
Soft-Start Current
Soft-Start Period
Thermal Shutdown
ISS
tSS
TSD
VSS = 0V
--
--
--
6
--
--
--
μA
ms
°C
CSS = 0.1μF
13.5
150
Note 1. Stresses beyond those listed “Absolute Maximum Ratings” may cause permanent damage to the device. These are
stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in
the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions may
affect device reliability.
Note 2. θJA is measured at TA = 25°C on a high effective thermal conductivity four-layer test board per JEDEC 51-7. θJC is
measured at the exposed pad of the package.
Note 3. Devices are ESD sensitive. Handling precaution is recommended.
Note 4. The device is not guaranteed to function outside its operating conditions.
Copyright 2012 Richtek Technology Corporation. All rights reserved.
©
is a registered trademark of Richtek Technology Corporation.
DS7247C-02 September 2012
www.richtek.com
5
RT7247C
Typical Application Circuit
1
3
V
2
IN
VIN
BOOT
RT7247C
4.5V to 18V
C
C
BOOT
0.1µF
IN
L
10µF x 2
6.8µH
V
3.3V
OUT
SW
Chip Enable
R1
7
8
EN
SS
75k
C
OUT
22µF x 2
5
6
FB
C
C
C
0.1µF
R
C
SS
R2
3.3nF
17k
24k
4, 9 (Exposed Pad)
COMP
GND
C
P
Open
Table 1. Suggested Components Selection
VOUT (V) R1 (kΩ) R2 (kΩ) RC (kΩ) CC (nF)
L (μH)
15
COUT (μF)
8
27
62
3
11.8
24
40
25
17
13
7
3.3
3.3
3.3
3.3
3.3
3.3
3.3
22 x 2
22 x 2
22 x 2
22 x 2
22 x 2
22 x 2
22 x 2
5
10
3.3
2.5
1.5
1.2
1
75
6.8
4.7
3.6
2
25.5
10.5
12
12
12
24
6
3
12
5
2
Copyright 2012 Richtek Technology Corporation. All rights reserved.
©
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
6
DS7247C-02 September 2012
RT7247C
Typical Operating Characteristics
Output Voltage vs. Input Voltage
Efficiency vs. Output Current
3.34
3.33
3.32
3.31
3.30
3.29
3.28
3.27
3.26
100
90
VIN = 4.5V
VIN = 12V
VIN = 17V
80
70
60
50
40
30
20
10
0
VOUT = 3.3V
1.5 2
VIN = 4.5V to 17V
4
6
8
10
12
14
16
18
0
0.5
1
Input Voltage (V)
Output Current (A)
Output Voltage vs. Temperature
Output Voltage vs. Output Current
3.40
3.38
3.36
3.34
3.32
3.30
3.28
3.26
3.24
3.22
3.20
3.34
3.33
3.32
3.31
3.30
3.29
3.28
3.27
3.26
VIN = 12V
VIN = 17V
VIN = 12V, VOUT = 3.3V
VOUT = 3.3V
1.75 2
-50
-25
0
25
50
75
100
125
0
0.25 0.5 0.75
1
1.25 1.5
Temperature (°C)
Output Current (A)
Switching Frequency vs. Input Voltage
Switching Frequency vs. Temperature
820
810
800
790
780
770
760
750
740
800
790
780
770
760
750
740
730
720
VIN = 17V
VIN = 12V
VIN = 4.5V
VIN = 4.5V to 17V, VOUT = 3.3V, IOUT = 0A
VOUT = 3.3V, IOUT = 0A
4
6
8
10
12
14
16
18
-50
-25
0
25
50
75
100
125
Input Voltage (V)
Temperature (°C)
Copyright 2012 Richtek Technology Corporation. All rights reserved.
©
is a registered trademark of Richtek Technology Corporation.
DS7247C-02 September 2012
www.richtek.com
7
RT7247C
Output Current Limit vs. Temperature
UVLO Threshold vs. Temperature
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
4.4
4.3
4.2
4.1
4.0
3.9
3.8
3.7
3.6
3.5
3.4
Rising
Falling
VIN = 12V, VOUT = 3.3V
50 75 100 125
-50
-25
0
25
-50
-25
0
25
50
75
100
125
Temperature (°C)
Temperature (°C)
Load Transient Response
Load Transient Response
VOUT
(200mV/Div)
VOUT
(200mV/Div)
IOUT
(1A/Div)
IOUT
(1A/Div)
VIN = 12V, VOUT = 3.3V, IOUT = 1A to 2A
VIN = 12V, VOUT = 3.3V, IOUT = 0A to 2A
Time (100μs/Div)
Time (100μs/Div)
Output Ripple Voltage
Output Ripple Voltage
VOUT
(5mV/Div)
VOUT
(5mV/Div)
VSW
(10V/Div)
VSW
(10V/Div)
IL
IL
(1A/Div)
(1A/Div)
VIN = 12V, VOUT = 3.3V, IOUT = 1A
Time (500ns/Div)
VIN = 12V, VOUT = 3.3V, IOUT = 2A
Time (500ns/Div)
Copyright 2012 Richtek Technology Corporation. All rights reserved.
©
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
8
DS7247C-02 September 2012
RT7247C
Power On from VIN
Power Off from VIN
VIN
(5V/Div)
VIN
(5V/Div)
VOUT
(2V/Div)
VOUT
(2V/Div)
IOUT
(2A/Div)
IOUT
(2A/Div)
VIN = 12V, VOUT = 3.3V, IOUT = 2A
Time (10ms/Div)
VIN = 12V, VOUT = 3.3V, IOUT = 2A
Time (25ms/Div)
Power On from EN
Power Off from EN
VEN
(5V/Div)
VEN
(5V/Div)
VOUT
(2V/Div)
VOUT
(2V/Div)
IOUT
(2A/Div)
IOUT
(2A/Div)
VIN = 12V, VOUT = 3.3V, IOUT = 2A
Time (10ms/Div)
VIN = 12V, VOUT = 3.3V, IOUT = 2A
Time (10ms/Div)
Copyright 2012 Richtek Technology Corporation. All rights reserved.
©
is a registered trademark of Richtek Technology Corporation.
DS7247C-02 September 2012
www.richtek.com
9
RT7247C
Application Information
Output Voltage Setting
Soft-Start
The resistive divider allows the FB pin to sense the output
voltage as shown in Figure 1.
The RT7247C provides soft-start function. The soft-start
function is used to prevent large inrush current while
converter is being powered-up. The soft-start timing can
be programmed by the external capacitor between SS and
GND. An internal current source ISS (6μA) charges an
external capacitor to build a soft-start ramp voltage. The
VFB voltage will track the internal ramp voltage during soft-
start interval. The typical soft-start time is calculated as
V
OUT
R1
FB
RT7247C
GND
R2
follows :
0.8×C
SS , if CSS capacitor
Figure 1. Output Voltage Setting
Soft-Start time tSS
=
ISS
0.8×0.1μ
The output voltage is set by an external resistive voltage
divider according to the following equation :
is 0.1μF, then soft-start time =
≒ 13.5ms
6μ
R1
R2
⎛
⎝
⎞
⎟
⎠
Chip Enable Operation
VOUT = VREF 1+
⎜
The EN pin is the chip enable input. Pulling the EN pin
low (<0.4V) will shut down the device. During shutdown
mode, the RT7247C quiescent current drops to lower than
3μA. Driving the EN pin high (>2V, <18V) will turn on the
device again. For external timing control, the EN pin can
also be externally pulled high by adding a REN resistor
and CEN capacitor from the VIN pin (see Figure 3).
Where VREF is the reference voltage (0.8V typ.).
External Bootstrap Diode
Connect a 0.1μF low ESR ceramic capacitor between the
BOOT pin and SW pin. This capacitor provides the gate
driver voltage for the high side MOSFET.
It is recommended to add an external bootstrap diode
between an external 5V and BOOT pin for efficiency
improvement when input voltage is lower than 5.5V or duty
ratio is higher than 65% .The bootstrap diode can be a
low cost one such as IN4148 or BAT54. The external 5V
can be a 5V fixed input from system or a 5V output of the
RT7247C. Note that the external boot voltage must be
lower than 5.5V
EN
R
EN
V
IN
EN
RT7247C
C
EN
GND
Figure 3. Enable Timing Control
An external MOSFET can be added to implement digital
control on the EN pin when no system voltage above 2V
is available, as shown in Figure 4. In this case, a 100kΩ
pull-up resistor, REN, is connected between VIN and the
EN pin. MOSFET Q1 will be under logic control to pull
down the EN pin.
5V
BOOT
0.1µF
RT7247C
SW
R
EN
100k
V
EN
RT7247C
GND
IN
Q1
EN
Figure 2. External Bootstrap Diode
Figure 4. Digital Enable Control Circuit
Copyright 2012 Richtek Technology Corporation. All rights reserved.
©
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
10
DS7247C-02 September 2012
RT7247C
Under Voltage Protection
Hiccup Mode
Having a lower ripple current reduces not only the ESR
losses in the output capacitors but also the output voltage
ripple. High frequency with small ripple current can achieve
the highest efficiency operation. However, it requires a
large inductor to achieve this goal.
For the RT7247C, it provides Hiccup Mode Under Voltage
Protection (UVP). When the VFB voltage drops below 0.4V,
the UVP function will be triggered to shut down switching
operation. If the UVP condition remains for a period, the
RT7247C will retry automatically. When the UVP condition
is removed, the converter will resume operation. The UVP
is disabled during soft-start period.
For the ripple current selection, the value of ΔIL= 0.24(IMAX
)
will be a reasonable starting point. The largest ripple
current occurs at the highest VIN. To guarantee that the
ripple current stays below the specified maximum, the
inductor value should be chosen according to the following
equation :
Hiccup Mode
⎡
⎤ ⎡
⎤
V
f × ΔI
V
OUT
V
IN(MAX)
OUT
L =
× 1−
⎢
⎥ ⎢
⎥
L(MAX)
⎣
⎦ ⎣
⎦
The inductor's current rating (caused a 40°C temperature
rising from 25°C ambient) should be greater than the
maximum load current and its saturation current should
be greater than the short circuit peak current limit. Please
see Table 2 for the inductor selection reference.
VOUT
(2V/Div)
ILX
(2A/Div)
Table 2. Suggested Inductors for Typical
Application Circuit
IOUT = Short
Time (50ms/Div)
Component
Supplier
TDK
Dimensions
(mm)
Series
VLF10045
SLF12565
10 x 9.7 x 4.5
Figure 5. Hiccup Mode Under Voltage Protection
TDK
12.5 x 12.5 x 6.5
TAIYO
YUDEN
NR8040
8 x 8 x 4
Over Temperature Protection
The RT7247C features an Over Temperature Protection
(OTP) circuitry to prevent from overheating due to
excessive power dissipation. The OTP will shut down
switching operation when junction temperature exceeds
150°C. Once the junction temperature cools down by
approximately 20°C, the converter will resume operation.
To maintain continuous operation, the maximum junction
temperature should be lower than 125°C.
CIN and COUT Selection
The input capacitance, CIN, is needed to filter the
trapezoidal current at the source of the high side MOSFET.
To prevent large ripple current, a low ESR input capacitor
sized for the maximum RMS current should be used. The
approximate RMS current is given :
V
V
V
IN
V
OUT
OUT
I
= I
−1
RMS
OUT(MAX)
Inductor Selection
IN
This formula has a maximum at VIN = 2VOUT, where
IRMS = IOUT/2. This simple worst case condition is
commonly used for design because even significant
deviations do not offer much relief. Choose a capacitor
rated at a higher temperature than required. Several
capacitors may also be paralleled to meet size or height
requirements in the design. For the input capacitor, two
10μF low ESR ceramic capacitors are suggested. For the
The inductor value and operating frequency determine the
ripple current according to a specific input and output
voltage. The ripple current ΔIL increases with higher VIN
and decreases with higher inductance.
V
VOUT
⎡
OUT ⎤ ⎡
× 1−
⎥ ⎢
⎤
ΔIL =
⎢
⎣
⎥
⎦
f ×L
V
IN
⎦ ⎣
Copyright 2012 Richtek Technology Corporation. All rights reserved.
©
is a registered trademark of Richtek Technology Corporation.
DS7247C-02 September 2012
www.richtek.com
11
RT7247C
suggested capacitor, please refer to Table 3 for more
details. The selection of COUT is determined by the
required ESR to minimize voltage ripple. Moreover, the
amount of bulk capacitance is also a key for COUT selection
to ensure that the control loop is stable. Loop stability
can be checked by viewing the load transient response
as described in a later section.
θJA is 75°C/W on the standard JEDEC 51-7 four-layers
thermal test board. The maximum power dissipation at
TA = 25°C can be calculated by following formula :
PD(MAX) = (125°C − 25°C) / (75°C/W) = 1.333W
(min.copper area PCB layout)
PD(MAX) = (125°C − 25°C) / (49°C/W) = 2.04W
(70mm2copper area PCB layout)
The output ripple, ΔVOUT, is determined by :
The thermal resistance θJA of SOP-8 (Exposed Pad) is
determined by the package architecture design and the
PCB layout design. However, the package architecture
design had been designed. If possible, it's useful to increase
thermal performance by the PCB layout copper design.
The thermal resistance θJA can be decreased by adding
copper area under the exposed pad of SOP-8 (Exposed
Pad) package.
1
⎡
⎤
ΔV
≤ ΔI ESR +
OUT
L
⎢
⎣
⎥
⎦
8fC
OUT
The output ripple will be the highest at the maximum input
voltage since ΔIL increases with input voltage. Multiple
capacitors placed in parallel may be needed to meet the
ESR and RMS current handling requirement. Higher values,
lower cost ceramic capacitors are now becoming available
in smaller case sizes. Their high ripple current, high voltage
rating and low ESR make them ideal for switching regulator
applications. However, care must be taken when these
capacitors are used at input and output. When a ceramic
capacitor is used at the input and the power is supplied
by a wall adapter through long wires, a load step at the
output can induce ringing at the input, VIN. At best, this
ringing can couple to the output and be mistaken as loop
instability. At worst, a sudden inrush of current through
the long wires can potentially cause a voltage spike at
VIN large enough to damage the part.
As shown in Figure 6, the amount of copper area to which
the SOP-8 (Exposed Pad) is mounted affects thermal
performance. When mounted to the standard
SOP-8 (Exposed Pad) pad (Figure 6.a), θJA is 75°C/W.
Adding copper area of pad under the SOP-8 (Exposed
Pad) (Figure 6.b) reduces the θJA to 64°C/W. Even further,
increasing the copper area of pad to 70mm2 (Figure 6.e)
reduces the θJA to 49°C/W.
The maximum power dissipation depends on the operating
ambient temperature for fixed TJ(MAX) and thermal
resistance, θJA. The derating curve in Figure 7 of derating
curves allows the designer to see the effect of rising
ambient temperature on the maximum power dissipation
Thermal Considerations
For continuous operation, do not exceed the maximum
operation junction temperature 125°C. The maximum
power dissipation depends on the thermal resistance of
IC package, PCB layout, the rate of surroundings airflow
and temperature difference between junction to ambient.
The maximum power dissipation can be calculated by
following formula :
allowed.
2.2
Four-Layer PCB
2.0
1.8
Copper Area
1.6
2
70mm
50mm
1.4
2
2
1.2
1.0
0.8
0.6
0.4
0.2
0.0
30mm
10mm
PD(MAX) = (TJ(MAX) − TA ) / θJA
2
Min.Layout
Where TJ(MAX) is the maximum operation junction
temperature , TA is the ambient temperature and the θJA is
the junction to ambient thermal resistance.
For recommended operating condition specifications, the
maximum junction temperature is 125°C. The junction to
ambient thermal resistance θJA is layout dependent. For
SOP-8 (Exposed Pad) package, the thermal resistance
0
25
50
75
100
125
Ambient Temperature (°C)
Figure 7. Derating Curve of Maximum PowerDissipation
Copyright 2012 Richtek Technology Corporation. All rights reserved.
©
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
12
DS7247C-02 September 2012
RT7247C
Layout Consideration
Follow the PCB layout guidelines for optimal performance
of the RT7247C.
` Keep the traces of the main current paths as short and
wide as possible.
(a) Copper Area = (2.3 x 2.3) mm2, θJA = 75°C/W
` Put the input capacitor as close as possible to the device
pins (VINandGND).
` SW node is with high frequency voltage swing and
should be kept at small area. Keep analog components
away from the SW node to prevent stray capacitive noise
pick-up.
` Connect feedback network behind the output capacitors.
Keep the loop area small. Place the feedback
components near the RT7247C.
(b) Copper Area = 10mm2,θJA = 64°C/W
` An example of PCB layout guide is shown in Figure 8
for reference.
(c) Copper Area = 30mm2 ,θJA = 54°C/W
(d) Copper Area = 50mm2 ,θJA = 51°C/W
(e) Copper Area = 70mm2 ,θJA = 49°C/W
Figure 6. Thermal Resistance vs. CopperArea Layout
Design
Copyright 2012 Richtek Technology Corporation. All rights reserved.
©
is a registered trademark of Richtek Technology Corporation.
DS7247C-02 September 2012
www.richtek.com
13
RT7247C
SW
C
V
V
GND
GND
IN
IN
The feedback components
must be connected as close
to the device as possible.
R
BOOT
EN
C
SS
Input capacitor must
be placed as close
to the IC as possible.
C
IN
C
C
8
7
6
5
BOOT
VIN
SS
2
3
4
R
C
EN
C
P
L
GND
V
OUT
SW
COMP
FB
9
R1
GND
R2
V
OUT
C
OUT
GND
SW node is with high frequency voltage swing and should
be kept at small area. Keep analog components away from
the SW node to prevent stray capacitive noise pick-up
Figure 8. PCB Layout Guide
Table 3. Suggested Capacitors for CIN and COUT
Location
CIN
Component Supplier
MURATA
TDK
Part No.
Capacitance (μF)
Case Size
1206
GRM31CR61E106K
C3225X5R1E106K
TMK316BJ106ML
GRM31CR60J476M
C3225X5R0J476M
GRM32ER71C226M
C3225X5R1C22M
10
10
10
47
47
22
22
CIN
1206
CIN
TAIYO YUDEN
MURATA
TDK
1206
COUT
COUT
COUT
COUT
1206
1210
MURATA
TDK
1210
1210
Copyright 2012 Richtek Technology Corporation. All rights reserved.
©
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
14
DS7247C-02 September 2012
RT7247C
Outline Dimension
H
A
Y
M
EXPOSED THERMAL PAD
(Bottom of Package)
J
B
X
F
C
I
D
Dimensions In Millimeters Dimensions In Inches
Symbol
Min
Max
Min
Max
A
B
C
D
F
H
I
4.801
3.810
1.346
0.330
1.194
0.170
0.000
5.791
0.406
2.000
2.000
2.100
3.000
5.004
4.000
1.753
0.510
1.346
0.254
0.152
6.200
1.270
2.300
2.300
2.500
3.500
0.189
0.150
0.053
0.013
0.047
0.007
0.000
0.228
0.016
0.079
0.079
0.083
0.118
0.197
0.157
0.069
0.020
0.053
0.010
0.006
0.244
0.050
0.091
0.091
0.098
0.138
J
M
X
Y
X
Y
Option 1
Option 2
8-Lead SOP (Exposed Pad) Plastic Package
Richtek Technology Corporation
5F, No. 20, Taiyuen Street, Chupei City
Hsinchu, Taiwan, R.O.C.
Tel: (8863)5526789
Richtek products are sold by description only. Richtek reserves the right to change the circuitry and/or specifications without notice at any time. Customers should
obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. Richtek cannot
assume responsibility for use of any circuitry other than circuitry entirely embodied in a Richtek product. Information furnished by Richtek is believed to be
accurate and reliable. However, no responsibility is assumed by Richtek or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Richtek or its subsidiaries.
DS7247C-02 September 2012
www.richtek.com
15
相关型号：
C3225X5R0J476M250AA
Ceramic Capacitor, Multilayer, Ceramic, 6.3V, 20% +Tol, 20% -Tol, X5R, 15% TC, 47uF, Surface Mount, 1210, CHIP, ROHS COMPLIANT
TDK
©2020 ICPDF网 联系我们和版权申明