首页 |元器件品牌

RT5800 [RICHTEK]

暂无描述;
RT5800
型号： RT5800
厂家： RICHTEK TECHNOLOGY CORPORATION    RICHTEK TECHNOLOGY CORPORATION
描述：

暂无描述
文件： 总47页 (文件大小：2664K)
中文：  中文翻译
下载：  下载PDF数据表文档文件
 查看货源
RT5800  
2.1MHz, 3 CHs, Step-Down Converter with I2C Interface  
Features  
FMEA Compliant PinOut  
General Description  
The RT5800 is a multi-phase, programmable power  
management IC, integrated with four high efficient,  
synchronous step-down converter cores. The RT5800  
can be 2 + 2 and 2 + 1 + 1 output by OTP. It also  
features wide output voltage range and the capability to  
configure the corresponding power stages, which make  
the device optimized to meet power management  
requirements for low-power processors, such as core  
power for CPUs and GPUs. The RT5800 supports  
many programmable functions including voltage level,  
slew rate of voltage change, and slew rate of soft-start  
via an I2C interface capable of operating up to 3.4MHz.  
The RT5800 also supports remote-sense function to  
get accurate output voltage at large loading. Moreover,  
the device has interrupt and fault-detection function to  
report error status. The RT5800 is available in a  
WQFN-30L 4.5x5 (FC) package.  
2 + 2 / 2 + 1 + 1 Phase Output  
Input Supply Voltage Range : 3V to 6V  
I2C Programmable Output Voltage : 0.3V to 1.85V  
Maximum Output Current : 5.5A per Phase  
Output Remote Sense for High Accuracy  
Fast Transient Response  
Selectable Automatic Phase Shielding and  
Power Saving Mode Enables Higher Light Load  
Efficiency  
Dynamic  
Voltage  
Scaling  
(DVS)  
with  
Programmable Slew Rate for Each Output  
Programmable Soft-Start Function  
Interrupt Function and Fault Detection  
Watchdog Function  
Input Under-Voltage Lockout (UVLO)  
Cycle-by-Cycle Current Limit  
Output Under-Voltage Protection  
Over-Temperature Protection  
WQFN-30L 4.5x5 (FC)  
Applications  
Automotive Systems  
Simplified Application Circuit  
AVIN  
VOUT1  
L1  
L4  
PVIN1  
PVIN2  
PVIN3  
PVIN4  
V
IN  
LX1  
C
IN  
LX4  
V
OUT1  
OUT1  
OUT2  
OUT3  
C
C
C
RTN1  
VOUT2  
LX2  
EN  
L2  
L3  
V
OUT2  
SCL  
RT5800  
2
I C Signal  
SDA  
VSELA  
RTN2  
Signal Input  
VOUT3  
LX3  
WDOG_RST  
INT  
V
OUT3  
Signal Output  
RTN3  
VIO  
PGND  
AGND  
AVIN_FILT  
Copyright © 2019 Richtek Technology Corporation. All rights reserved.  
is a registered trademark of Richtek Technology Corporation.  
DS5800-00 November 2019  
www.richtek.com  
1
RT5800  
Ordering Information  
Pin Configuration  
(TOP VIEW)  
-
-
RT5800  
Code Version  
Operation Phase  
21 : program to 2 + 1 + 1 phase operation  
22 : program to 2 + 2 phase operation  
30 29 28 27 26 25 24 23  
Package Type  
QWF : WQFN-30L 4.5x5 (FC)  
1
2
3
22  
21  
20  
PVIN4  
NC  
PVIN2  
NC  
Lead Plating System  
G : Green (Halogen Free and Pb Free)  
LX4  
LX2  
Note :  
Richtek products are :  
PGND  
PGND  
PGND  
4
19  
31  
5
6
7
18  
17  
16  
LX1  
NC  
LX3  
NC  
RoHS compliant and compatible with the current  
PVIN1  
PVIN3  
requirements of IPC/JEDEC J-STD-020.  
8
9
10 11 12 13 14 15  
Suitable for use in SnPb or Pb-free soldering  
processes.  
Marking Information  
RT5800GQWTF-21-01  
0W= : Product Code  
WQFN-30L 4.5x5 (FC)  
YMDNN : Date Code  
0W=YM  
DNN  
RT5800GQWF-22-01  
0E= : Product Code  
YMDNN : Date Code  
0E=YM  
DNN  
Copyright © 2019 Richtek Technology Corporation. All rights reserved.  
is a registered trademark of Richtek Technology Corporation.  
www.richtek.com  
2
DS5800-00 November 2019  
RT5800  
Functional Pin Description  
Pin No.  
Pin Name  
Pin Function  
Power input for power stage 4. It is recommended to use a 10F, X7R  
capacitor.  
1
PVIN4  
2, 6, 17, 21  
NC  
No internal connection.  
3
4, 19  
5
LX4  
Switching node for power stage 4.  
Power ground for power stage.  
Switching node for power stage 1.  
PGND  
LX1  
Power input for power stage 1. It is recommended to use a 10F, X7R  
capacitor.  
7
8
9
PVIN1  
VSEL input pin for all channels. Using corresponding register to define  
action. "Do Not" leave this pin floating.  
VSELA  
Filtered analog supply voltage. It is recommended to use a 1F, X7R  
capacitor.  
AVIN_FILT  
10  
11  
12  
13  
14  
RTN1  
Remote ground sense for Buck1.  
Output voltage sense for Buck1.  
Remote ground sense for Buck3.  
Output voltage sense for Buck3.  
Analog GND.  
VOUT1  
RTN3  
VOUT3  
AGND  
Digital input. Reset all Bucks to default output voltage and some relative  
registers to default settings when this pin is pulled low. Connect this pin to  
VIO pin if this pin is not used. "Do Not" leave this pin floating.  
15  
WDOG_RST  
Power input for power stage 3. It is recommended to use a 10F, X7R  
capacitor.  
16  
PVIN3  
18  
20  
LX3  
LX2  
Switching node for power stage 3.  
Switching node for power stage 2.  
Power input for power stage 2. It is recommended to use a 10F, X7R  
capacitor.  
22  
PVIN2  
23  
24  
SCL  
SDA  
I2C clock. "Do Not" leave this pin floating.  
I2C data. "Do Not" leave this pin floating.  
Interrupt indicator. When INT function is used, set 0x33[6] = 1, 0x34[6] = 1  
and 0x35[6] = 1.  
25  
26  
27  
INT  
VIO  
EN  
I/O supply voltage for digital communications. Connect this pin to 1.8V. "Do  
Not" leave this pin floating.  
Master chip enable. A logic-high enables the converter; a logic-low forces  
the device into shutdown mode. "Do Not" leave this pin floating.  
28  
29  
30  
VOUT2  
RTN2  
AVIN  
Output voltage sense for Buck2.  
Remote ground sense for Buck2.  
Analog input voltage.  
Exposed pad. The exposed pad is connected to PGND and must be  
soldered to a large PCB copper area for maximum power dissipation.  
31(Exposed PAD) PGND  
Copyright © 2019 Richtek Technology Corporation. All rights reserved.  
is a registered trademark of Richtek Technology Corporation.  
DS5800-00 November 2019  
www.richtek.com  
3
RT5800  
Functional Block Diagram  
VIO  
AVIN_FILT  
AVIN  
RTNx  
VOUTx  
PVINx  
Buck 1  
LX1  
LX2  
LX3  
LX4  
Voltage/Current  
Protection  
UVLO Protection  
Regulators  
Current Sensing  
EN  
Enable & VSELA  
Logic  
Buck 2  
VSELA  
Voltage/Current  
Protection  
Watchdog  
Logic  
Voltage/Current  
Reference  
WDOG_RST  
INT  
Current Sensing  
Oscillator  
Core  
Control  
Buck 3  
Voltage/Current  
Protection  
Interrupts  
Interface  
Digital Logic  
I2C Buffer  
DAC  
Current Sensing  
SDA  
SCL  
Buck 4  
Voltage/Current  
Protection  
Thermal Protection  
Current Sensing  
PGND  
AGND  
Copyright © 2019 Richtek Technology Corporation. All rights reserved.  
is a registered trademark of Richtek Technology Corporation.  
www.richtek.com  
4
DS5800-00 November 2019  
RT5800  
Operation  
let DVS0 be used and pull VSELA low to let DVS1 be  
used. Conversely, when setting 0x52[2]=1, pull VSELA  
high to let DVS1 be used and pull VSELA low to let  
DVS0 be used.  
The RT5800 is a power management IC that integrates  
four high efficiency Buck converters, and is factory  
configured as a 2/1/1 phase converter. Each of the four  
converters provides up to 5A output current over an  
input supply voltage range of 3.3V to 6V.  
The RT5800 also supports DVS speed configuration,  
whether the slew rate of voltage changing in the same  
DVSx or between DVS0 and DVS1. Take Buck1 as  
two-phase configuration for an example, when output  
voltage is set from low to high or high to low, register  
0x54[6:4] defines slew rate of DVS up while 0x54[2:0]  
is used to define slew rate of DVS down. In order to  
have better performance during voltage changing  
operation, the master/slave enters PWM operation and  
keeps 200s after the voltage achieves target even  
when IC is set to Auto mode. Figure 1 and Figure 2  
show the DVS up and down operation.  
The RT5800 utilizes the proprietary Advanced Constant  
On-Time (ACOTTM) control architecture. The ultrafast  
ACOTTM control enables the use of small ceramic  
capacitors (MLCC) to save the PCB size.  
During normal operation, the internal high-side power  
switch (HSFET) is turned on for a fixed interval  
determined by a one-shot timer at the beginning of each  
clock cycle. When the HSFET is turned off, the internal  
low-side power switch (LSFET) is turned on. The output  
voltage is sensed remotely at VOUTx and RTNx for high  
accuracy and is compared to an internal reference  
voltage. Hence, the error signal is obtained and  
internally compensated. The compensated error signal  
is then compared to an internal ramp signal. When the  
minimum off-time one-shot (100ns, max.) has timed out  
and the inductor current is below the current limit  
threshold, the one-shot is triggered again if the internal  
ramp signal falls below the compensated error signal.  
The ACOTTM control architecture features ultrafast  
transient response. When a load is suddenly increased,  
the output voltage drops quickly. and triggers a new  
on-time to rise inductor current again.  
95%  
Target Voltage  
VOUT  
Intial Voltage  
5%  
Master  
Switch  
Slave  
Switch  
DVS Up Slew Rate  
Register Setting  
Command  
200μs  
Figure 1. DVS Up Operation  
95%  
Intial Voltage  
Dynamic Voltage Scaling (DVS)  
VOUT  
Target Voltage  
5%  
The RT5800 provides wide output voltage range with  
8-bits resolution and each Buck converter has two  
independently programmable voltage setting. They are  
called DVS0 and DVS1. Take Buck1 as two-phase  
configuration for an example, register 0x48[8:0] can set  
voltage of DVS0 while 0x4A[8:0] is used to set voltage  
of DVS1. There are two methods to select the DVS. For  
the first method, it can be changed by software from  
register 0x52[1:0]. Control DVS0 by setting  
0x52[1:0]=00 and DVS1 by setting 0x52[1:0]=01. For  
the second method, selecting the DVS can be from  
external hardware pin when setting 0x52[1:0]=10.  
VSELA pin can be this role and its polarity is defined by  
0x52[2]. When setting 0x52[2]=0, pull VSELA high to  
Master  
Switch  
Slave  
Switch  
DVS Down Slew Rate  
Register Setting  
Command  
200μs  
Figure 2. DVS Down Operation  
Copyright © 2019 Richtek Technology Corporation. All rights reserved.  
is a registered trademark of Richtek Technology Corporation.  
DS5800-00 November 2019  
www.richtek.com  
5
 
 
RT5800  
enable control, to enable or disable the device. If VEN is  
held below a logic-low threshold voltage (VENL) of the  
enable input (EN), the converter will enter into  
shutdown mode and reset all digital function (I2C), that  
is, the converter is disabled even if the VIN voltage is  
above VIN under-voltage lockout threshold (VUVLO).  
During shutdown mode, the supply current can be  
reduced to ISHDN (20A or below). If the EN voltage  
rises above the logic-high threshold voltage (VENH), the  
device starts switching. When appropriate voltages are  
present on the VIN, AVIN, VIO and EN pins, the  
RT5800 will begin digital function, switching and initiate  
a soft-start ramp of the output voltage. After the device  
is turned on and VIO is ready, all digital functions  
including I2C communication start to work in a boot  
time with 230s (typ.). The voltage of VIO can be used  
to supply power to digital function and it is recommend  
that enable the device after VIO voltage is ready. The  
RT5800 supports enable delay time setting (factory  
setting) and soft-start slew rate setting for each Buck.  
The soft-start function is used to prevent large inrush  
current while the converter is powered up. Register  
0x55[5:4], 0x6F[5:4] and 0x89[5:4] let soft-start time of  
each be programmable. The start-up sequence is  
shown in Figure 3. IC also implements enable control  
by software, it can be set in the registers: 0x49[0],  
0x4B[0], 0x63[0], 0x65[0], 0x7D[0] and 0x7F[0]. If the  
output voltage of Buck is default disable which is only  
set by factory, the output voltage starts to ramp up by  
software and the Figure 4 shows the start-up sequence.  
For disable function, the device supports disable delay  
time setting (factory setting) by external EN pin and the  
output voltage ramps down with default discharge  
resistor. The discharge resistor can be controlled to on  
or off by register 0x42[0], 0x5F[0] and 0x79[0] when the  
converter is disabled by software. The power-off  
sequence is shown in Figure 5 and Figure 6.  
MODE Selection  
Whether it is DVS0 or DVS1, there are two modes of  
operation: forced continuous conduction mode (FCCM)  
and automatic power saving mode (Auto mode). It is  
set in the following registers: 0x49[5], 0x4B[5], 0x63[5],  
0x65[5], 0x7D[5] and 0x7F[5]. For example, to set  
DVS0 of Buck1 to FCCM, just write "1" at 0x49[5].  
Auto Mode with Automatically Phase Adding/Shedding  
Auto mode enables high efficiency at light load. At low  
load current, the inductor current can drop to zero and  
become negative. This is detected by internal zero  
current-detect circuitry which utilizing the LSFET  
RDS(ON) to sense the inductor current. The LSFET is  
turned off when the inductor current drops to zero,  
resulting in discontinuous operation (DCM). Both  
HSFET and LSFET remain off with the output capacitor  
supplying the load current until the feedback voltage  
falls below the feedback reference voltage. DCM  
operation maintains high efficiency at light load, while  
setting MODE to Forced PWM (FCCM) operation helps  
meet tight voltage regulation accuracy requirements.  
For multiphase outputs, the RT5800 automatically  
increases the number of operating phases as the load  
continues to increase above 3A (typ). The two phases  
are interleaved with 180 degrees apart. Interleaving  
reduces ripple current at the input and output.  
Therefore, the input and output capacitors are also  
reduced. Conversely, when the load current per phase  
drops below 2.6A (typ), the RT5800 automatically  
sheds the number of phases.  
FCCM Mode  
Setting MODE to Forced PWM (FCCM) operation helps  
meet  
stringent  
voltage  
regulation  
accuracy  
requirements. Users must enable all the set outputs  
before setting into the FCCM.  
UVLO, Enable Control and Soft-Start  
The RT5800 implements under-voltage lockout  
protection (UVLO) to prevent operation without fully  
turn on the internal HSFET and LSFET. The UVLO  
monitors the voltage of AVIN. When the AVIN voltage  
is lower than UVLO threshold, IC stops switching and  
resets all digital functions.  
The RT5800 provides an EN pin, as an external chip  
Copyright © 2019 Richtek Technology Corporation. All rights reserved.  
is a registered trademark of Richtek Technology Corporation.  
www.richtek.com  
6
DS5800-00 November 2019  
RT5800  
V
= 5V  
IN  
V
IN  
= 5V  
VUVLO  
VIN  
VIN  
V
= 1.8V  
IO  
V
IO  
= 1.8V  
VIO  
EN  
VIO  
EN  
SW EN  
Discharge  
resistor off  
VOUT of  
Buckx  
T
SS  
VOUT of  
Buckx  
EN Delay Time  
(Factory Setting)  
Register  
Setting  
70μs  
Discharge  
resistor on  
230μs  
Boot  
Time  
2
Digital/I C work  
Figure 3. Start-up Sequence  
Figure 6. Power-off Sequence by Software  
V
V
= 5V  
IN  
VUVLO  
VIN  
Power Good Indication  
= 1.8V  
The RT5800 provides a power good indication and this  
function shows the status of output voltage. When  
output voltage is between 110% and 90% of setting  
voltage for each Buck, the PG indication bit goes high.  
The relative registers are 0x14[7], 0x15[7] and 0x16[7].  
IO  
VIO  
EN  
VOUT of  
Buckx  
Fault Detection and Interrupt Pin  
SW EN  
The RT5800 alerts the host when a warning, like Boot  
and Hot Die, or fault events, like over-voltage,  
under-voltage and over-temperature conditions have  
occurred. Registers 0x13, 0x14, 0x15 and 0x16 can  
help host to know if the fault or waning event happens.  
These bits relative to events can be read and cleared.  
Moreover, the RT5800 provides an interrupt pin with  
the push-pull output capability and this pin shows these  
events by using active low. When INT function is used,  
set 0x33[6] = 1, 0x34[6] = 1 and 0x35[6] = 1. The pull  
high output voltage of INT pin will be VIO voltage.  
Register 0x32, 0x33, 0x34 and 0x35 can also set the  
mask function to mask or pass the event flag output to  
external interrupt pin. The overall detection function is  
shown in Figure 7.  
EN Delay Time  
(Factory Setting)  
T
SS  
Register  
Setting  
230μs  
Boot  
Time  
70μs  
Figure 4. Start-up Sequence by Software  
V
= 5V  
IN  
VIN  
VIO  
V
= 1.8V  
IO  
EN  
VOUT of  
Buck  
Disable Delay Time  
(Factory Setting)  
Figure 5. Power-off Sequence  
.
Copyright © 2019 Richtek Technology Corporation. All rights reserved.  
is a registered trademark of Richtek Technology Corporation.  
DS5800-00 November 2019  
www.richtek.com  
7
RT5800  
Rising  
Falling  
BOOT  
Event Flag  
BOOT  
HOT Die  
OT  
BOOT  
Mask  
Rising  
Falling  
HOT Die  
Event Flag  
HOT Die  
Mask  
Rising  
Falling  
OT  
Event Flag  
OT  
Mask  
To INT  
Rising  
Falling  
OV  
Event Flag  
OV  
OV  
Mask  
Rising  
Falling  
UV  
Event Flag  
UV  
UV  
Mask  
Rising  
Falling  
PG  
Event Flag  
PG  
PG  
Mask  
Figure 7. Overall Detection Function  
Table 1. Watchdog Reset Register  
Watchdog Function  
BUCK1_WDT  
BUCK2_WDT  
0x62  
BUCK3_WDT  
The RT5800 implements a watchdog function which  
resets some relative registers, like the output voltage,  
to default settings. Register 0x25 can enable or disable  
watchdog function of each Buck and provide the  
debounce time for selection. The operation of  
watchdog reset is shown in Figure 8. Table 1 shows the  
registers will be reset when WDOG_RST pin is pulled  
low. The I2C command needs to be after the  
WDOG_RST pull high.  
0x48  
0x49[0]  
0x4A  
0x7C  
0x7D[0]  
0x7E  
0x63[0]  
0x64  
0x4B[0]  
0x52  
0x65[0]  
0x6C  
0x7F[0]  
0x86  
The Over-Current Protection  
The RT5800 features cycle-by-cycle current-limit  
protection on both HSFET and LSFET to prevent the  
device from the catastrophic damage in output  
short-circuit, over-current or inductor saturation  
conditions.  
WDOG_RST  
Higher  
V
SET  
Default  
Voltage  
The HSFET over-current protection is achieved by an  
internal current comparator that monitors the current in  
the HSFET during each on-time. The switch current is  
VOUT of  
BUCKx  
Reset Related  
Register  
Lower  
V
SET  
DEBOUNCE Time  
Register Setting  
DVS  
Slew Rate  
compared with the HSFET peak-current limit (ILIM_H  
)
after a certain amount of delay when the HSFET is  
turned on each cycle. If an over-current condition  
occurs, the converter will immediately turn off the  
HSFET and turn on the LSFET to prevent the inductor  
current from exceeding the HSFET current limit.  
Figure 8. Watchdog Reset Operation  
The LSFET over-current protection is achieved by  
measuring the inductor current through the LSFET  
Copyright © 2019 Richtek Technology Corporation. All rights reserved.  
is a registered trademark of Richtek Technology Corporation.  
www.richtek.com  
8
DS5800-00 November 2019  
 
RT5800  
during the LSFET on-time. Once the current rises  
above the LSFET valley current limit (ILIM_L), the  
on-time one-shot will be inhibited until the inductor  
current ramps down to the current limit level (ILIM_L),  
that is, another on-time can only be triggered when the  
inductor current goes below the LSFET current limit. If  
the output load current exceeds the available inductor  
current (clamped by the LSFET current limit), the  
output capacitor needs to supply the extra current so  
that the output voltage will begin to drop. If it drops  
below the output under-voltage protection trip threshold,  
the IC will stop switching to avoid excessive heat.  
state again for next cycle. When each Buck is set to  
latch mode, UVP will let converter enter shutdown  
mode unless resetting IC by external EN pin or falling  
to UVLO low threshold.  
Over-Temperature Protection  
The RT5800 includes an over-temperature protection  
(OTP) circuitry to prevent overheating due to excessive  
power dissipation. The OTP shuts down switching  
operation when junction temperature exceeds a  
thermal shutdown threshold TSD. Once the junction  
temperature cools down by a thermal shutdown  
hysteresis (TSD), the IC resumes normal operation  
with a complete soft-start. It can select not to shut down  
IC when OTP happens by using register 0x30[3].  
Output Under-Voltage Protection  
The RT5800 includes output under-voltage protection  
(UVP) against over-load or short-circuited condition by  
constantly monitoring the output voltage VOUT. If VOUT  
drops below the under-voltage protection trip threshold  
(typically 50% of the internal reference voltage), both  
HSFET and LSFET will stop switching. Register  
0x37[3], 0x38[3] and 0x39[3] can select hiccup or latch  
protection behavior of each Buck converter when  
converter is in UV condition. For hiccup behavior, both  
HSFET and LSFET keep low state in a 1ms and then  
IC starts to switch. If the output voltage is not greater  
than UV threshold after internal soft-start end signal is  
triggered, both HSFET and LSFET will still keep low  
Note that the over temperature protection is intended to  
protect the device during momentary overload  
conditions. The protection is activated outside of the  
absolute maximum range of operation as a secondary  
fail-safe and therefore should not be relied upon  
operationally. Continuous operation above the  
specified absolute maximum operating junction  
temperature may impair device reliability or  
permanently damage the device.  
Copyright © 2019 Richtek Technology Corporation. All rights reserved.  
is a registered trademark of Richtek Technology Corporation.  
DS5800-00 November 2019  
www.richtek.com  
9
RT5800  
Absolute Maximum Ratings (Note 1)  
Supply Input Voltage ------------------------------------------------------------------------------------------------ 0.3V to 6.5V  
LX Pin Switch Voltage----------------------------------------------------------------------------------------------- 0.3V to 7.3V  
< 100ns ----------------------------------------------------------------------------------------------------------------- 5V to 9V  
Other I/O Pin Voltages ---------------------------------------------------------------------------------------------- 0.3V to 7.3V  
Power Dissipation, PD @ TA = 25C  
WQFN-30L 4.5x5 (FC)---------------------------------------------------------------------------------------------- 2.87W  
Package Thermal Resistance  
(Note 2)  
WQFN-30L 4.5x5 (FC), JA----------------------------------------------------------------------------------------- 34.8C/W  
WQFN-30L 4.5x5 (FC), JC(Top) ---------------------------------------------------------------------------------- 18.2C/W  
WQFN-30L 4.5x5 (FC), JB---------------------------------------------------------------------------------------- 13.2C/W  
Lead Temperature (Soldering, 10 sec.)------------------------------------------------------------------------- 260C  
Junction Temperature----------------------------------------------------------------------------------------------- 150C  
Storage Temperature Range-------------------------------------------------------------------------------------- 65C to 150C  
ESD Susceptibility  
(Note 3)  
HBM (Human Body Model) ---------------------------------------------------------------------------------------- 2kV  
Recommended Operating Conditions (Note 4)  
Supply Input Voltage (for 2 + 2 application)-------------------------------------------------------------------- 3.3V to6V  
Supply Input Voltage (for 2 + 1 + 1 application)--------------------------------------------------------------- 3V to6V  
Junction Temperature Range ------------------------------------------------------------------------------------- 40C to 125C  
Electrical Characteristics  
(VIN = 3.7V, TJ = 25C, unless otherwise specified)  
Parameter  
Analog Input Voltage  
Power Input Voltage  
Shutdown Current  
Symbol  
VAVIN  
VPVIN  
ISHDN  
Test Conditions  
For 2 + 2 application  
Min  
3.3  
3.3  
--  
Typ Max Unit  
--  
--  
1
6
6
V
V
For 2 + 2 application  
EN = 0V, Digital circuit doesn't work  
20  
A  
EN = VIO = 1.8V, disable all Buck by  
software  
Buck Off Current  
ISDBO  
ISLP  
VUVLO  
VUVLO  
RDS(ON)_H VIN = 5V  
RDS(ON)_L VIN = 5V  
--  
--  
20  
70  
80  
A  
A  
V
1Phase no Switching  
Current  
VOUT = 1.2 x VOUT_SETTING  
VIN rising  
120  
Under-Voltage Lockout  
Threshold  
2.1  
--  
2.32 2.45  
Under-Voltage Lockout  
Hysteresis  
300  
25  
--  
mV  
m  
m  
High-Side Switch-On  
Resistance  
18  
8
45  
25  
Low-Side Switch-On  
Resistance  
15  
Copyright © 2019 Richtek Technology Corporation. All rights reserved.  
is a registered trademark of Richtek Technology Corporation.  
www.richtek.com  
10  
DS5800-00 November 2019  
RT5800  
Parameter  
Symbol  
Test Conditions  
3V VIN 6V  
Min  
Typ Max Unit  
0.7 x  
VIO  
Logic-High VIH  
--  
--  
--  
SDA, SCL,  
VSELA,  
V
0.3 x  
VIO  
WDOG_RST  
Logic-Low VIL  
3V VIN 6V  
--  
Logic-High VENH  
Logic-Low VENL  
1.2  
--  
--  
--  
--  
EN Threshold  
V
V
0.4  
External Supply Voltage for  
I/O Pin  
VIN_I/O  
1.7  
1.8  
2.45  
Auto PFM/PWM, VOUT = 1V (Note 5)  
Forced PWM, 0.6V VOUT 1.85V  
IOUT(DC) = 1 to 5A (Note 5)  
2.5  
1.5  
--  
--  
--  
2.5  
1.5  
--  
%
%
VOUT DC Accuracy  
Load Regulation  
Line Regulation  
VLOAD  
VLINE  
0.08  
0.2  
%/A  
%/V  
3V VIN 6V, IOUT(DC) = 1.5A (Note 5)  
--  
--  
2phase operation, 0.1 to 4A, tR = tF = 1s,  
L = 0.33H, COUT = 44F/phase  
(Note 5)  
--  
--  
40  
40  
--  
--  
mV  
mV  
Load Transient Response  
1phase operation, 0.1 to 2A, tR = tF = 1s,  
L= 0.33H, COUT = 44F/phase (Note 5)  
Line Transient Response  
Current Balance  
4V to 5V, tR = tF = 10s (Note 5)  
--  
--  
40  
--  
--  
0.5  
--  
mV  
A
Load = 10A, |IAvg ILX_1 or 4  
|
Phase Adding Level  
Phase Shedding Level  
Soft-Start Time  
From 1phase to 2phase (Note 5)  
From 2phase to 1phase (Note 5)  
Slew Rate = 10mV/s  
--  
3
A
--  
2.6  
--  
A
Tstart  
ILIM_H  
20  
20  
%
High-Side Switch Current  
Limit per Channel  
5.8  
8
11  
A
Low-Side Switch Current  
Limit per Channel  
ILIM_L  
TSD  
5.1  
--  
7
9
--  
--  
A
Thermal Shutdown  
160  
30  
C  
C  
Thermal Shutdown  
Hysteresis  
TSD  
--  
HOT Die Warning  
HOT Die Hysteresis  
Discharge Resistor  
0xAA = 0x02 (Note 5)  
(Note 5)  
--  
--  
109  
15  
--  
--  
C  
C  
THYSHD  
70  
40  
--  
115  
50  
180  
60  
--  
VUVP_T  
VUVP_R  
VOVP_T  
VOVP_R  
fSW  
Trigger Level  
Recovery Level  
Trigger Level  
Recovery Level  
VOUT = 1V  
%
%
%
%
Output UVP Flag  
57  
123  
--  
133  
125  
143  
--  
Output OVP Flag  
Switching Frequency  
1850 2100 2500 kHz  
Copyright © 2019 Richtek Technology Corporation. All rights reserved.  
is a registered trademark of Richtek Technology Corporation.  
DS5800-00 November 2019  
www.richtek.com  
11  
RT5800  
Parameter  
Symbol  
Test Conditions  
Min  
Typ Max Unit  
Error Rate of DVS Slew  
Rate  
VIN = 3.7V, VOUT = 0.6V to 1.2V  
20  
--  
20  
%
Output low level, ISOURCE = 2mA  
Push-pull, ISINK = 2mA  
--  
1.6  
--  
--  
--  
--  
--  
0.4  
VIO  
40  
V
V
Digital Output Pin : INT  
Digital Output Pin : SDA  
I2C Speed  
Output low level Resistor  
--  
3.4 MHz  
Hold Time (Repeated) Start  
Condition. After this Period,  
the First Clock Pulse is  
Generated  
tHD;STA  
Fast mode (Note5)  
0.6  
--  
--  
s  
Low Period of the SCL  
Clock  
tLOW  
Fast mode (Note5)  
Fast mode (Note5)  
1.3  
0.6  
--  
--  
--  
--  
s  
s  
High Period of the SCL  
Clock  
tHIGH  
Set-Up Time for a Repeated  
START Condition  
tSU;STA  
Fast mode (Note5)  
0.6  
--  
--  
s  
Data Hold Time  
tHD;DAT  
tSU;DAT  
Fast mode (Note5)  
Fast mode (Note5)  
0
--  
--  
0.9  
--  
s  
Data Set-Up Time  
100  
ns  
Set-Up Time for STOP  
Condition  
tSU;STO  
Fast mode (Note5)  
Fast mode (Note5)  
0.6  
1.3  
--  
--  
--  
--  
s  
s  
Bus Free Time between a  
STOP and START  
Condition  
tBUF  
Rising Time of both SDA  
and SCL Signals  
tR  
tF  
Fast mode (Note5)  
Fast mode (Note5)  
20  
20  
--  
--  
300  
300  
ns  
ns  
Falling Time of both SDA  
and SCL Signals  
SDA Output Low Sink  
Current  
IOL  
SDA Voltage = 0.4V (Note5)  
Fast/High speed mode (Note5)  
2
--  
--  
--  
mA  
ms  
Detect SDA Low Timeout  
tTIMEOUT  
--  
30  
Note 1. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These  
are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in  
the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions may affect  
device reliability.  
Note 2. θJA is measured in the natural convection at TA = 25°C on a Four-layer Richtek Evaluation Board. θJC is measured at  
the top of the package.  
Note 3. Devices are ESD sensitive. Handling precaution is recommended.  
Note 4. The device is not guaranteed to function outside its operating conditions.  
Note 5. Guaranteed by design.  
Copyright © 2019 Richtek Technology Corporation. All rights reserved.  
is a registered trademark of Richtek Technology Corporation.  
www.richtek.com  
12  
DS5800-00 November 2019  
RT5800  
Typical Application Circuit  
2 + 1 + 1 Phase  
30  
AVIN  
V
7
11  
IN  
PVIN1  
VOUT1  
LX1  
3V to 5.5V  
C1  
10μF  
L1  
5
0.33uH  
L4  
22  
PVIN2  
PVIN3  
PVIN4  
3
V
OUT1  
C2  
10μF  
LX4  
0.33uH  
(10A)  
C7  
10  
16  
1
22μF x 4  
RTN1  
C3  
10μF  
28  
20  
29  
VOUT2  
LX2  
L2  
V
OUT2  
C4  
10μF  
0.33uH  
(5A)  
C8  
RT5800  
22μF x 2  
RTN2  
27  
23  
24  
8
1.5V to 5.5V  
EN  
13  
18  
12  
SCL  
VOUT3  
LX3  
2
I C Signal  
SDA  
VSELA  
L3  
V
OUT3  
0.33uH  
(5A)  
C9  
Signal Input  
22μF x 2  
RTN3  
15  
25  
WDOG_RST  
INT  
Signal Output  
4, 19, 31  
14  
PGND  
AGND  
26  
9
1.8V  
VIO  
C5  
AVIN_FILT  
1μF  
C6  
1μF  
2 + 2 Phase  
30  
7
AVIN  
V
11  
5
IN  
PVIN1  
VOUT1  
LX1  
3.3V to 5.5V  
C1  
10μF  
L1  
0.33uH  
L4  
0.33uH  
22  
16  
1
PVIN2  
PVIN3  
PVIN4  
3
V
OUT1  
(11A)  
C2  
10μF  
LX4  
C7  
22μF x 4  
10  
RTN1  
C3  
10μF  
28  
20  
VOUT2  
LX2  
L2  
0.33uH  
L3  
0.33uH  
C4  
10μF  
RT5800  
18  
29  
V
OUT2  
(9A)  
27  
23  
24  
8
LX3  
1.5V to 5.5V  
EN  
C8  
22μF x 4  
SCL  
RTN2  
2
I C Signal  
SDA  
13  
12  
VOUT3  
RTN3  
VSELA  
WDOG_RST  
INT  
Signal Input  
15  
25  
Signal Output  
4, 19, 31  
14  
PGND  
AGND  
26  
9
1.8V  
VIO  
C5  
AVIN_FILT  
1μF  
C6  
1μF  
Copyright © 2019 Richtek Technology Corporation. All rights reserved.  
is a registered trademark of Richtek Technology Corporation.  
DS5800-00 November 2019  
www.richtek.com  
13  
RT5800  
Table 2. Recommended BOM  
Reference  
Qty  
Part number  
Description  
Package  
Manufacture  
DC-DC  
Converter  
WQFN-30L  
4.5x5 (FC)  
U1  
1
RT5800  
RICHTEK  
C1, C2, C3, C4  
C5, C6  
4
2
8
4
GRT188C81A106ME  
GRT188C8YA105KE  
GRT31CR70J226KE  
VCTA25201B-R33MS6  
10F  
1F  
C-0603  
C-0603  
C-1206  
2520  
Murata  
Murata  
Murata  
Cyntec  
C7, C8, C9  
L1, L2, L3, L4  
22F  
0.33H  
Note :  
(1) COUT = 44F per-phase is min. value for the RT5800.  
(2) All the input and output capacitors are the suggested values, referring to the effective capacitances, subject to  
any de-rating effect, like a DC bias.  
Copyright © 2019 Richtek Technology Corporation. All rights reserved.  
is a registered trademark of Richtek Technology Corporation.  
www.richtek.com  
14  
DS5800-00 November 2019  
RT5800  
Typical Operating Characteristics  
Efficiency vs. Output Current  
Efficiency vs. Output Current  
100  
90  
80  
70  
60  
50  
40  
30  
20  
10  
0
100  
90  
80  
V
V
= 3.3V  
= 5V  
IN  
IN  
V
V
= 3.3V  
= 5V  
IN  
IN  
70  
60  
50  
40  
30  
20  
10  
0
Single Phase, V  
= 1V  
5
Two Phase, V  
= 1V  
OUT  
OUT  
9
0
0.5  
1
1.5  
2
2.5  
3
3.5  
4
4.5  
5.5  
0
1
2
3
4
5
6
7
8
10 11  
Output Current (A)  
Output Current (A)  
Output Voltage vs. Output Current  
Output Voltage vs. Output Current  
1.025  
1.020  
1.015  
1.010  
1.005  
1.000  
0.995  
0.990  
0.985  
0.980  
0.975  
1.025  
1.020  
1.015  
1.010  
1.005  
1.000  
0.995  
0.990  
0.985  
0.980  
0.975  
V
V
= 5V  
V
V
= 5V  
IN  
IN  
IN  
IN  
= 3.3V  
= 3.3V  
Two Phase, V  
= 1V, FCCM  
Single Phase, V  
= 1V, FCCM  
OUT  
8
OUT  
0
0.5  
1
1.5  
2
2.5  
3
3.5  
4
4.5  
5
5.5  
0
1
2
3
4
5
6
7
9
10 11  
Output Current (A)  
Output Current (A)  
Output Voltage vs. Input Voltage  
Output Voltage vs. Input Voltage  
1.025  
1.020  
1.015  
1.010  
1.005  
1.000  
0.995  
0.990  
0.985  
0.980  
0.975  
1.025  
1.020  
1.015  
1.010  
1.005  
1.000  
0.995  
0.990  
0.985  
0.980  
0.975  
I
= 0A  
OUT  
I
= 0A  
OUT  
I
= 5.5A  
OUT  
I
= 11A  
OUT  
Two Phase, V  
= 1V, FCCM  
Single Phase, V  
=1V, FCCM  
OUT  
OUT  
3.3 3.5 3.7 3.9 4.1 4.3 4.5 4.7 4.9 5.1 5.3 5.5  
Input Voltage (V)  
3.3 3.5 3.7 3.9 4.1 4.3 4.5 4.7 4.9 5.1 5.3 5.5  
Input Voltage (V)  
Copyright © 2019 Richtek Technology Corporation. All rights reserved.  
is a registered trademark of Richtek Technology Corporation.  
DS5800-00 November 2019  
www.richtek.com  
15  
RT5800  
Load Transient Response-Two Phase  
Load Transient Response-Two Phase  
V
= 3.8V, V  
= 1V, I  
= 0.1A to 4A  
OUT  
IN  
OUT  
T
= T = 1s, FCCM, L = 0.33H  
F
R
C
= 22F/1206/6.3V x 4  
OUT  
V
V
OUT  
(20mV/Div)  
OUT  
(20mV/Div)  
V
= 3.8V, V  
= 1V, I  
= 4A to 0.1A  
OUT  
IN  
OUT  
T
= T = 1s, FCCM, L = 0.33H  
F
R
C
= 22F/1206/6.3V x 4  
OUT  
I
OUT  
(2A/Div)  
I
OUT  
(2A/Div)  
Time (4s/Div)  
Time (4s/Div)  
Load Transient Response-Single Phase  
Load Transient Response-Single Phase  
V
= 3.8V, V  
= 1V, I  
= 0.1A to 2A  
OUT  
IN  
OUT  
T
= T = 1s, FCCM, L = 0.33H  
F
R
C
= 22F/1206/6.3V x 2  
V
OUT  
OUT  
V
OUT  
(20mV/Div)  
(20mV/Div)  
V
= 3.8V, V  
= 1V, I  
= 2A to 0.1A  
OUT  
IN  
OUT  
T
= T = 1s, FCCM, L = 0.33H  
F
R
C
= 22F/1206/6.3V x 2  
I
OUT  
OUT  
(1A/Div)  
I
OUT  
(1A/Div)  
Time (4s/Div)  
Time (4s/Div)  
OCP Hiccup - Two Phase  
OCP Hiccup - Single Phase  
V
= 3.8V, V  
= 1.1V  
OUT  
V
= 3.8V, V  
= 0.8V  
OUT  
V
V
IN  
IN  
OUT  
OUT  
(500mV/Div)  
(400mV/Div)  
V
LX1  
(10V/Div)  
V
LX2  
(10V/Div)  
I
LX1  
(5A/Div)  
I
I
LX4  
LX2  
(5A/Div)  
(5A/Div)  
Time (1ms/Div)  
Time (1ms/Div)  
Copyright © 2019 Richtek Technology Corporation. All rights reserved.  
is a registered trademark of Richtek Technology Corporation.  
www.richtek.com  
16  
DS5800-00 November 2019  
RT5800  
Output Ripple - Two Phase  
Output Ripple - Single Phase  
V
OUT  
V
(10mV/Div)  
OUT  
(10mV/Div)  
V
LX1  
(5V/Div)  
V
LX4  
V
LX2  
(5V/Div)  
(3V/Div)  
I
OUT  
(5A/Div)  
I
OUT  
(5A/Div)  
V
= 3.8V, V  
= 1V, I  
= 11A  
V
= 3.8V, V  
= 1V, I  
= 5.5A  
OUT  
IN  
OUT  
OUT  
IN  
OUT  
Time (500ns/Div)  
Time (500ns/Div)  
EN Threshold Voltage vs. Temperature  
EN Pin Current vs. Temperature  
1.00  
0.95  
0.90  
0.85  
0.80  
0.75  
0.70  
0.8  
0.7  
0.6  
0.5  
0.4  
0.3  
0.2  
0.1  
0
Rising  
Falling  
V
= 3.3V  
V
= 3.6V  
EN  
IN  
-50  
-25  
0
25  
50  
75  
100  
125  
-50  
-25  
0
25  
50  
75  
100  
125  
Temperature (°C)  
Temperature (°C)  
Current Limit vs. Temperature  
MOSFET RDS(ON) vs. Temperature  
8.5  
8.0  
7.5  
7.0  
6.5  
6.0  
5.5  
5.0  
4.5  
4.0  
35  
30  
25  
20  
15  
10  
5
HSFET  
R
DS(ON)_H  
V
V
= 5.5V_Peak  
= 4V_Peak  
IN  
IN  
R
DS(ON)_L  
V
= 5V  
IN  
0
-50  
-25  
0
25  
50  
75  
100  
125  
-50  
-25  
0
25  
50  
75  
100  
125  
Temperature (°C)  
Temperature (°C)  
Copyright © 2019 Richtek Technology Corporation. All rights reserved.  
is a registered trademark of Richtek Technology Corporation.  
DS5800-00 November 2019  
www.richtek.com  
17  
RT5800  
Application Information  
The RT5800 is a power management IC that integrates  
four high efficiency Buck converters, and is factory  
configured as a 2/1/1 phase converter.  
Input Capacitor Selection  
Input capacitance, CIN, is needed to filter the pulsating  
current at the drain of the HSFET. The CIN should be  
sized to do this without causing a large variation in  
input voltage. Several capacitors may also be  
paralleled to meet size, height and thermal  
requirements in the design. For low input voltage  
applications, sufficient bulk input capacitance is  
needed to minimize transient effects during output load  
changes.  
Inductor Selection  
The inductor selection trade-offs among size, cost,  
efficiency, and transient response requirements.  
Generally, three key inductor parameters are specified  
for operation with the device: inductance value (L),  
inductor saturation current (ISAT), and DC resistance  
(DCR).  
The input capacitor should be placed as close as  
possible to each VIN pin with a low inductance  
connection to the PGND of the IC. It is recommended  
to connect capacitors between the VIN pin and the  
PGND pin for 2.1MHz switching frequency as shown in  
the typical application circuit. The larger input  
capacitance is required when a lower switching  
frequency is used. The X7R capacitors are  
A good compromise between size and loss is a 30%  
peak-to-peak ripple current to the IC rated current, but  
it still depends on size consideration. The inductor used  
in the typical application circuit of datasheet is  
recommended. The switching frequency, input voltage,  
output voltage, and selected inductor ripple current  
determines the inductor value as follows :  
V
(V V  
)
OUT  
IN  
OUT  
recommended  
for  
best  
performance  
across  
L =  
V f  
I  
L
IN SW  
temperature and input voltage variations.  
To enhance the efficiency, choose a low-loss inductor  
having the lowest possible DC resistance that fits in the  
allotted dimensions. The selected inductor should have  
a saturation current rating greater than the peak current  
limit of the device. The core must be large enough not  
to saturate at the peak inductor current (IL_PEAK) :  
Output Capacitor Selection  
The selection of COUT is determined by considering to  
satisfy the voltage ripple and the transient loads. The  
peak-to-peak output ripple, VOUT, is determined by :  
1
V  
= I ESR +  
OUT  
L
8C  
F  
OUT  
SW   
V
(V V  
OUT  
)
OUT  
IN  
where the IL is the peak-to-peak inductor ripple  
current. The highest output ripple is at maximum input  
voltage since IL increases with input voltage. Multiple  
capacitors placed in parallel may be needed to meet  
the ESR and RMS current handling requirements.  
I =  
L
V f  
L  
IN SW  
1
2
I
= I  
+
I  
L_PEAK  
OUT_MAX  
L
The current flowing through the inductor is the inductor  
ripple current plus the output current. During power up,  
faults, or transient load conditions, the inductor current  
can increase above the calculated peak inductor  
current level calculated above. In transient conditions,  
the inductor current can increase up to the switch  
current limit of the device. For this reason, the most  
conservative approach is to specify an inductor with a  
saturation current rating equal to or greater than the  
switch current limit rather than the peak inductor  
current.  
Ceramic capacitors have very low equivalent series  
resistance (ESR) and provide the best ripple  
performance. The X7R dielectric capacitor is  
recommended for the best performance across  
temperature and input voltage variations. The variation  
of the capacitance value with temperature, DC bias  
voltage and switching frequency needs to be taken into  
consideration. For example, the capacitance value of a  
capacitor decreases as the DC bias across the  
capacitor increases. Be careful to consider the voltage  
Copyright © 2019 Richtek Technology Corporation. All rights reserved.  
is a registered trademark of Richtek Technology Corporation.  
www.richtek.com  
18  
DS5800-00 November 2019  
RT5800  
coefficient of ceramic capacitors when choosing the  
value and case size. Most ceramic capacitors lose 50%  
or more of their rated values when used near their  
rated voltage.  
simply set JA(EFFECTIVE) as 110% to 120% of the JA  
is reasonable to obtain the allowed PD(MAX)  
.
From the efficiency measurement to find the power loss  
of system and below formula can be used to determine  
the power loss of IC by removing the loss of inductor  
including DC loss and AC loss.  
Transient performance can be improved with a higher  
value output capacitor. Increasing the output  
capacitance will also decrease the output voltage  
ripple.  
Two phase converter power loss :  
I
2
OUT  
P
= (V I V  
I  
)((  
) DCR)2  
The recommended output capacitors are shown in  
typical application circuit.  
loss  
IN IN  
OUT OUT  
2
2
V
ACR  
V
OUT  
2
OUT  
P  
2(  
(1  
) )2  
core_loss  
2
2
SW  
V
12L f  
IN  
Thermal Considerations  
In many applications, the RT5800 does not generate  
much heat due to its high efficiency and low thermal  
resistance of its WQFN- 30L 4.5x5 package. However,  
in applications which the RT5800 runs at a high  
ambient temperature and high input voltage or high  
switching frequency, the generated heat may exceed  
the maximum junction temperature of the part.  
Single phase converter power loss :  
2
OUT  
P
= (V I V  
I  
)I  
DCRP  
core_loss  
loss  
IN IN  
OUT OUT  
2
V
ACR  
V
2
OUT  
OUT  
(1  
)
2
2
SW  
V
12L f  
IN  
Where  
The junction temperature should never exceed the  
absolute maximum junction temperature TJ(MAX), listed  
under Absolute Maximum Ratings, to avoid permanent  
damage to the device. If the junction temperature  
reaches approximately 150°C, the RT5800 stops  
switching the power MOSFETs until the temperature  
cools down by 25°C.  
Pcore_loss and ACR need to be from inductor supplier  
Total loss of IC can’t be larger than maximum power  
loss. If the application requires a higher ambient  
temperature and/or higher switching frequency, care  
should be taken to reduce the temperature rise of the  
part by using a heat sink or air flow. Note that the  
over-temperature protection is intended to protect the  
device during momentary overload conditions. The  
protection is activated outside of the absolute  
maximum range of operation as a secondary fail-safe  
and therefore should not be relied upon operationally.  
Continuous operation above the specified absolute  
maximum operating junction temperature may impair  
device reliability or permanently damage the device.  
The maximum power dissipation can be calculated by  
the following formula :  
PD(MAX) = (TJ(MAX) TA) /JA(EFFECTIVE)  
where  
TJ(MAX) is the maximum allowed junction temperature  
of the die. For recommended operating condition  
specifications, the maximum junction temperature is  
125°C. TA is the ambient operating temperature,  
JA(EFFECTIVE) is the system-level junction to ambient  
thermal resistance. It can be estimated from thermal  
modeling or measurements in the system.  
Layout Guidelines  
When laying out the printed circuit board, the following  
checklist should be used to ensure proper operation of  
the RT5800 :  
The thermal resistance of the device strongly depends  
on the surrounding PCB layout and can be improved by  
providing a heat sink of surrounding copper ground.  
The addition of backside copper with thermal vias,  
stiffeners, and other enhancements can also help  
reduce thermal resistance.  
Four-layer or six-layer PCB with maximum ground  
plane is strongly recommended for good thermal  
performance.  
Keep the traces of the main current paths wide and  
short.  
Experiments in the Richtek thermal lab show that  
Copyright © 2019 Richtek Technology Corporation. All rights reserved.  
is a registered trademark of Richtek Technology Corporation.  
DS5800-00 November 2019  
www.richtek.com  
19  
RT5800  
Place high frequency decoupling capacitor as close  
as possible to the IC to reduce the loop impedance  
and minimize switch node ringing.  
as small as possible. Keep analog components  
away from the LX node.  
Reduce the area size of the LX exposed copper to  
reduce the electrically coupling from this voltage.  
Connect the feedback sense network behind via of  
output capacitor.  
Place multiple vias under the device near PVIN and  
PGND and close to input capacitors to reduce  
parasitic inductance  
and improve thermal  
performance. To keep thermal resistance low,  
extend the ground plane as much as possible, and  
add twenty thermal vias under and near the RT5800  
to additional ground planes within the circuit board  
and on the bottom side.  
Connect all analog grounds to common node and  
then connect the common node to the power ground  
with a single point.  
Figure 9 and Figure 10 shows the layout example  
which includes one two phase converter for Core and  
one single phase converter for Memory application.  
The high frequency switching nodes, LX, should be  
Add vias on exposed pad  
for thermal dissipation and  
Input capacitors must be  
placed as close to IC  
VIN-GND as possible  
Connect to PGND in  
second layer with  
single node.  
current carrying capacity  
CVIO  
I2C  
VOUT2  
30  
29  
28  
27  
26  
25  
24  
23  
L4  
L2  
COUT4_0 COUT4_1  
COUT2_0 COUT2_1  
PVIN4  
PVIN2  
1
2
3
22  
21  
CIN4  
CIN2  
20 LX2  
LX4  
PGND  
LX1  
4
19 PGND  
VOUT1  
PAD  
31  
5
6
7
18  
LX3  
CIN1  
C
IN3  
17  
16  
PVIN1  
PVIN3  
8
9
10  
11  
12  
13  
14  
15  
COUT1_0 COUT1_1  
L1  
L3  
COUT3_0 COUT3_1  
VOUT3  
CAVIN  
AVIN_FILT capacitor  
must be placed as close  
to IC as possible  
Connect to PGND in  
second layer with  
single node.  
Keep feedback sense  
trace away from noise  
trace to reduce coupling.  
Figure 9. Layout Guideline for 2 + 1 + 1 Application  
Copyright © 2019 Richtek Technology Corporation. All rights reserved.  
is a registered trademark of Richtek Technology Corporation.  
www.richtek.com  
20  
DS5800-00 November 2019  
RT5800  
Add vias on exposed pad  
for thermal dissipation and  
Input capacitors must be  
placed as close to IC  
VIN-GND as possible  
Connect to PGND in  
second layer with  
single node.  
current carrying capacity  
CVIO  
I2C  
30  
29  
28  
27  
26  
25  
24  
23  
L4  
L2  
COUT4_0 COUT4_1  
COUT2_0 COUT2_1  
PVIN4  
PVIN2  
1
2
3
22  
21  
CIN4  
CIN2  
20 LX2  
LX4  
PGND  
LX1  
4
19 PGND  
VOUT1  
VOUT2  
PAD  
31  
5
6
7
18  
LX3  
CIN1  
C
IN3  
17  
16  
PVIN1  
PVIN3  
8
9
10  
11  
12  
13  
14  
15  
COUT1_0 COUT1_1  
L1  
L3  
COUT3_0 COUT3_1  
CAVIN  
AVIN_FILT capacitor  
must be placed as close  
to IC as possible  
Connect to PGND in  
second layer with  
single node.  
Keep feedback sense  
trace away from noise  
trace to reduce coupling.  
Figure 10. Layout Guideline for 2 + 2 Application  
Copyright © 2019 Richtek Technology Corporation. All rights reserved.  
is a registered trademark of Richtek Technology Corporation.  
DS5800-00 November 2019  
www.richtek.com  
21  
RT5800  
I2C Interface  
The RT5800 I2C slave address = 7’b0011000 (Changed by Factory Setting). The RT5800 supports fast mode (bit  
rate up to 400kb/s). The write or read bit stream (N ≥ 1) is shown as Figure 11.  
Read N bytes from RT5800  
Slave Address  
Register Address  
Slave Address  
MSB  
MSB  
Data 1  
LSB  
S
0
A
A
Sr  
1
A
A
Assume Address = m  
Data for Address = m  
LSB  
R/W  
MSB  
Data 2  
LSB  
Data N  
A
A
P
Data for Address = m + N - 1  
Data for Address = m + 1  
Register Address  
Write N bytes to RT5800  
Slave Address  
MSB  
Data 1  
LSB MSB  
A
Data 2  
LSB  
S
0
A
A
A
Assume Address = m  
Data for Address = m  
MSB  
Data for Address = m + 1  
LSB  
R/W  
Data N  
A
P
Data for Address = m + N - 1  
P Stop, S Start, Sr Repeat Start  
Driven by Master,  
Driven by Slave (RT5800),  
SDA  
t
LOW  
t
t
t
F
t
SP  
SU,DAT  
t
HD,STA  
t
F
R
t
R
t
BUF  
SCL  
t
t
t
SU,STO  
HD,STA  
SU,STA  
t
t
HIGH  
HD,DAT  
S
P
S
S
r
Figure 11. I2C Read and Write Stream and Timing Diagram  
START condition (S)  
8-bit master code (00001xxx)  
not-acknowledge bit ( )  
The RT5800 also supports High-speed mode (bit rate  
up to 3.4Mb/s) with access code 08H. Figure 12 and  
Figure 13 show detail transfer format. Hs-mode can  
only commence after the following conditions (all of  
which are in F/S-mode) :  
A
F/S-Mode  
Hs-Mode (current-source for SCLH enabled  
A/A  
F/S-Mode  
A
Sr Slave ADD.  
A
Data  
P
S
Master Code  
N bytes + ack.  
Hs-Mode  
Continues  
R/W  
Slave ADD.  
Sr  
Figure 12. Data Transfer Format in Hs-mode  
Copyright © 2019 Richtek Technology Corporation. All rights reserved.  
is a registered trademark of Richtek Technology Corporation.  
www.richtek.com  
22  
DS5800-00 November 2019  
 
RT5800  
8-bit Master code 00001xxx  
t1  
A
t
H
S
SDAH  
SCLH  
1
2 to 5  
6
7
8
9
F/S-Mode  
A
N x (8-bit data + A/A  
7-bit SLA  
R/W  
Sr  
P
Sr  
SDAH  
SCLH  
1
2 to 5  
6
7
8
9
1
2 to 5  
6
7
8
9
If P then F/S mode  
Hs-Mode  
If Sr (dotted lines) then Hs-mode  
t
H
t
FS  
Figure 13. A Complete Hs-mode Transfer  
Copyright © 2019 Richtek Technology Corporation. All rights reserved.  
is a registered trademark of Richtek Technology Corporation.  
DS5800-00 November 2019  
www.richtek.com  
23  
RT5800  
Table 3. I2C Register Summary  
Register  
Address  
Register  
Name  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
Default  
0x01  
IO_CHIPNA  
ME  
0x01  
0x02  
IO_CHIPNAME  
IO_CHIPVE  
RSION  
IO_CHIPVERSION  
0x01  
0x0A  
0x0B  
0x0C  
0x0D  
IO_DIEID3  
IO_DIEID2  
IO_DIEID1  
IO_DIEID0  
IO_DIEID3  
IO_DIEID2  
IO_DIEID1  
IO_DIEID0  
0xFE  
0xDC  
0xBA  
0x98  
IO_SO  
FTRES  
ET  
IO_SOFTR  
ESET  
0x0F  
Reserved  
0x00  
FLT_RECO FLT_BO  
RDTEMP OT  
FLT_RECO BUCK1_  
FLT_HO FLT_TE  
0x13  
0x14  
0x15  
Reserved  
Reserved  
0x00  
0x00  
0x00  
TDIE  
MPSDR  
FLT_BU FLT_BU  
CK1_OV CK1_UV  
Reserved  
Reserved  
Reserved  
Reserved  
RDBUCK1  
FLT_RECO BUCK2_  
RDBUCK2 PG  
FLT_RECO BUCK3_  
RDBUCK3 PG  
PG  
FLT_BU FLT_BU  
CK2_OV CK2_UV  
Reserved  
Reserved  
FLT_BU FLT_BU  
CK3_OV CK3_UV  
0x16  
0x22  
0x25  
0x00  
0x18  
0x00  
IO_I2CCFG Reserved  
IO_I2CADDR  
Reserve  
IO_RSTDV  
Reserved  
S
IO_RSTDVS_CTRL  
Reserved  
IO_DBNTIME  
FLT_OT_  
CTRL  
FLT_CT  
RLOT1  
0x30  
0x32  
Reserved  
0x00  
0x00  
FLT_MASK FLT_MA  
FLT_MA FLT_MA  
Reserved  
Reserved  
TEMP  
SKBOOT  
SKHD  
SKTSDR  
FLT_BU  
CK1MAS  
KPG  
FLT_BU FLT_BU  
CK1MAS CK1MAS  
FLT_MASK  
BUCK1  
BUCK1  
INTACT  
0x33  
0x34  
0x35  
0x37  
Reserved  
0x00  
0x00  
0x00  
0x0C  
KOV  
KUV  
FLT_BU  
CK2MAS  
KPG  
FLT_BU FLT_BU  
CK2MAS CK2MAS  
FLT_MASK  
BUCK2  
BUCK2  
INTACT  
Reserved  
Reserved  
KOV  
KUV  
FLT_BU  
CK3MAS  
KPG  
FLT_BU FLT_BU  
CK3MAS CK3MAS  
FLT_MASK  
BUCK3  
BUCK3  
INTACT  
KOV  
KUV  
FLT_BU  
CK1_CT  
RLUV  
FLT_BUCK  
1_CTRL  
Reserved  
Reserved  
Copyright © 2019 Richtek Technology Corporation. All rights reserved.  
is a registered trademark of Richtek Technology Corporation.  
www.richtek.com  
24  
DS5800-00 November 2019  
RT5800  
Register  
Address  
Register  
Name  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
Default  
FLT_BU  
CK2_CT  
RLUV  
FLT_BUCK  
2_CTRL  
0x38  
0x39  
0x3E  
Reserved  
Reserved  
0x0C  
FLT_BU  
CK3_CT  
RLUV  
FLT_BUCK  
3_CTRL  
Reserved  
Reserved  
0x0C  
0x44  
BUCK1_  
DVS_DO  
WN  
BUCK1_  
RAMP  
BUCK1_  
DVS_UP  
Reserved  
Reserved  
Reserved  
Reserved  
BUCK1_  
CFG0  
BUCK1_  
DIS  
0x42  
0x48  
0x01  
0x8C  
BUCK1_  
DVS0CFG1  
BUCK1_DVS0  
BUCK1_  
DVS0M  
ODE  
BUCK1_  
DVS0CFG0  
BUCK1_  
ENDVS0  
0x49  
0x4A  
0x4B  
Reserved  
Reserved  
0x00  
0x8C  
0x00  
BUCK1_  
DVS1CFG1  
BUCK1_DVS1  
BUCK1_  
DVS1M  
ODE  
BUCK1_  
DVS1CFG0  
BUCK1_  
ENDVS1  
Reserved  
Reserved  
BUCK1_  
DVSPIN  
_POL  
BUCK1_  
DVSCFG  
BUCK1_DVS_  
CTRL  
0x52  
Reserved  
0x00  
BUCK1_  
RSPCFG  
0x54  
0x55  
Reserved  
Reserved  
BUCK1_RSPUP  
Reserved  
BUCK1_RSPDN  
Reserved  
0x14  
0x00  
BUCK1_  
SLEWCTRL  
BUCK1_SS_  
SLEW  
BUCK2_  
DVS_DO  
WN  
BUCK2_  
RAMP  
BUCK2_  
DVS_UP  
0x5B  
Reserved  
Reserved  
Reserved  
BUCK2_  
0x44  
BUCK2_  
CFG0  
0x5F  
0x62  
Reserved  
BUCK2_DVS0  
0x01  
0x8C  
DIS  
BUCK2_  
DVS0CFG1  
BUCK2_  
DVS0M  
ODE  
BUCK2_  
DVS0CFG0  
BUCK2_  
ENDVS0  
0x63  
0x64  
0x65  
Reserved  
Reserved  
0x00  
0x8C  
0x00  
BUCK2_  
DVS1CFG1  
BUCK2_DVS1  
BUCK2_  
DVS1M  
ODE  
BUCK2_  
DVS1CFG0  
BUCK2_  
ENDVS1  
Reserved  
Reserved  
BUCK2_  
DVSPIN  
_POL  
BUCK2_  
DVSCFG  
BUCK2_DVS_  
CTRL  
0x6C  
0x6E  
Reserved  
0x00  
0x14  
BUCK2_  
RSPCFG  
Reserved  
BUCK2_RSPUP  
Reserved  
BUCK2_RSPDN  
Copyright © 2019 Richtek Technology Corporation. All rights reserved.  
is a registered trademark of Richtek Technology Corporation.  
DS5800-00 November 2019  
www.richtek.com  
25  
RT5800  
Register  
Address  
Register  
Name  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
Default  
BUCK2_  
SLEWCTRL  
BUCK2_SS_  
SLEW  
0x6F  
0x75  
Reserved  
Reserved  
0x00  
BUCK3_  
DVS_DO  
WN  
BUCK3_  
RAMP  
BUCK3_  
DVS_UP  
Reserved  
Reserved  
Reserved  
0x44  
BUCK3_  
CFG0  
BUCK3_  
DIS  
0x79  
0x7C  
Reserved  
BUCK3_DVS0  
0x01  
0x8C  
BUCK3_  
DVS0CFG1  
BUCK3_  
DVS0M  
ODE  
BUCK3_  
DVS0CFG0  
BUCK3_  
ENDVS0  
0x7D  
0x7E  
0x7F  
Reserved  
Reserved  
0x00  
0x8C  
0x00  
BUCK3_  
DVS1CFG1  
BUCK3_DVS1  
BUCK3_  
DVS1M  
ODE  
BUCK3_  
DVS1CFG0  
BUCK3_  
ENDVS1  
Reserved  
Reserved  
BUCK3_  
DVSPIN  
_POL  
BUCK3_  
DVSCFG  
BUCK3_DVS_  
CTRL  
0x86  
Reserved  
0x00  
BUCK3_  
RSPCFG  
0x88  
0x89  
Reserved  
Reserved  
BUCK3_RSPUP  
Reserved  
BUCK3_RSPDN  
Reserved  
0x14  
0x00  
BUCK3_  
SLEWCTR  
BUCK3_SS_  
SLEW  
Copyright © 2019 Richtek Technology Corporation. All rights reserved.  
is a registered trademark of Richtek Technology Corporation.  
www.richtek.com  
26  
DS5800-00 November 2019  
RT5800  
Table 4. I2C Register Map  
Register  
Address  
Register  
Name  
0x01  
IO_CHIPNAME  
Bits  
Default  
Bit 7  
0
Bit 6  
0
Bit 5  
0
Bit 4  
0
Bit 3  
0
Bit 2  
0
Bit 1  
0
Bit 0  
1
Read/Write  
Bits  
R
R
R
R
R
R
R
R
Name  
Description  
IO_CHIPNAME  
Bit 7 to Bit 0  
IO_CHIPNAME  
Register  
Address  
Register  
Name  
0x02  
IO_CHIPVERSION  
Bit 2  
Bits  
Default  
Bit 7  
0
Bit 6  
0
Bit 5  
0
Bit 4  
0
Bit 3  
0
Bit 1  
0
Bit 0  
1
0
Read/Write  
Bits  
R
R
R
R
R
R
R
R
Name  
Description  
Bit 7 to Bit 0  
IO_CHIPVERSION  
IO_CHIPVERSION  
Register  
Address  
Register  
Name  
0x0A  
IO_DIEID3  
Bits  
Default  
Bit 7  
1
Bit 6  
1
Bit 5  
1
Bit 4  
1
Bit 3  
1
Bit 2  
1
Bit 1  
1
Bit 0  
0
Read/Write  
Bits  
R
R
R
R
R
R
R
R
Name  
Description  
IO_DIEID3  
Bit 7 to Bit 0  
IO_DIEID3  
Register  
Address  
Register  
Name  
0x0B  
IO_DIEID2  
Bits  
Default  
Bit 7  
Bit 6  
1
Bit 5  
0
Bit 4  
1
Bit 3  
1
Bit 2  
1
Bit 1  
0
Bit 0  
0
1
Read/Write  
Bits  
R
R
R
R
R
R
R
R
Name  
IO_DIEID2  
Description  
IO_DIEID2  
Bit 7 to Bit 0  
Copyright © 2019 Richtek Technology Corporation. All rights reserved.  
is a registered trademark of Richtek Technology Corporation.  
DS5800-00 November 2019  
www.richtek.com  
27  
RT5800  
Register  
Address  
Register  
Name  
0x0C  
IO_DIEID1  
Bits  
Default  
Bit 7  
1
Bit 6  
0
Bit 5  
1
Bit 4  
1
Bit 3  
1
Bit 2  
0
Bit 1  
1
Bit 0  
0
Read/Write  
Bits  
R
R
R
R
R
R
R
R
Name  
Description  
IO_DIEID1  
Bit 7 to Bit 0  
IO_DIEID1  
Register  
Address  
Register  
Name  
0x0D  
IO_DIEID0  
Bits  
Default  
Bit 7  
Bit 6  
0
Bit 5  
0
Bit 4  
1
Bit 3  
1
Bit 2  
0
Bit 1  
0
Bit 0  
0
1
Read/Write  
Bits  
R
R
R
R
R
R
R
R
Name  
Description  
IO_DIEID0  
Bit 7 to Bit 0  
IO_DIEID0  
Register  
Address  
Register  
Name  
0x0F  
IO_SOFTRESET  
Bits  
Default  
Bit 7  
Bit 6  
0
Bit 5  
0
Bit 4  
0
Bit 3  
0
Bit 2  
0
Bit 1  
0
Bit 0  
0
0
Read/Write  
Bits  
R
R
R
R
R
R
R
RW  
Name  
Reserved  
Description  
Bit 7 to Bit 1  
Reserved bits  
Reset all digital function to default setting.  
0 : Not changed  
Bit 0  
IO_SOFTRESET  
1 : Reset and bit cleared  
Copyright © 2019 Richtek Technology Corporation. All rights reserved.  
is a registered trademark of Richtek Technology Corporation.  
www.richtek.com  
28  
DS5800-00 November 2019  
RT5800  
Register  
Address  
Register  
Name  
0x13  
FLT_RECORDTEMP  
Bits  
Default  
Read/Write  
Bits  
Bit 7  
0
Bit 6  
0
Bit 5  
0
Bit 4  
0
Bit 3  
Bit 2  
0
Bit 1  
Bit 0  
0
0
0
RC  
R
R
R
R
RC  
RC  
R
Name  
Description  
Boot interrupt indicator. Read only and cleared.  
0 : Boot process doesn't occur. AVIN is less than UVLO rising threshold.  
1 : Boot process has occurred. AVIN is greater than UVLO rising  
threshold or less than UVLO falling threshold.  
Bit 7  
FLT_BOOT  
Bit 6 to Bit 3  
Bit 0  
Reserved  
Reserved bits  
Hot die interrupt indicator. Read only and cleared.  
0 : Temp of die is lower than threshold.  
1 : Die hot. Greater than threshold.  
Bit 2  
FLT_HOTDIE  
OT interrupt indicator. Read only and cleared.  
0 : No Fault. Less than threshold.  
1 : Fault. Greater than threshold or recovery after greater than  
threshold.  
Bit 1  
FLT_TEMPSDR  
Register  
Address  
Register  
0x14  
FLT_RECORDBUCK1  
Name  
Bits  
Default  
Read/Write  
Bits  
Bit 7  
0
Bit 6  
0
Bit 5  
0
Bit 4  
0
Bit 3  
0
Bit 2  
0
Bit 1  
0
Bit 0  
0
R
R
RC  
RC  
R
R
R
R
Name  
Description  
Power good status indicator.  
Bit 7  
BUCK1_PG  
Reserved  
0 : VOUT > 110% of setting VOUT or VOUT < 90% of setting VOUT  
1 : 110% of setting VOUT > VOUT > 90% of setting VOUT  
Bit 6  
Bit 3 to Bit 0  
Reserved bits  
OV interrupt indicator. Read only and cleared.  
0 : No Fault. Less than threshold.  
1 : Fault. Greater than threshold.  
Bit 5  
Bit 4  
FLT_BUCK1_OV  
UV interrupt indicator. Read only and cleared.  
0 : No Fault. Greater than threshold.  
FLT_BUCK1_UV  
1 : Fault. Less than threshold or recovery after less than threshold.  
Copyright © 2019 Richtek Technology Corporation. All rights reserved.  
is a registered trademark of Richtek Technology Corporation.  
DS5800-00 November 2019  
www.richtek.com  
29  
RT5800  
Register  
Address  
Register  
Name  
0x15  
FLT_RECORDBUCK2  
Bits  
Default  
Read/Write  
Bits  
Bit 7  
0
Bit 6  
0
Bit 5  
0
Bit 4  
0
Bit 3  
Bit 2  
0
Bit 1  
Bit 0  
0
0
0
R
R
RC  
RC  
R
R
R
R
Name  
Description  
Power good status indicator.  
Bit 7  
BUCK2_PG  
Reserved  
0 : VOUT > 110% of setting VOUT or VOUT < 90% of setting VOUT  
1 : 110% of setting VOUT > VOUT > 90% of setting VOUT  
Bit 6  
Bit 3 to Bit 0  
Reserved bits  
OV interrupt indicator. Read only and cleared.  
0 : No Fault. Less than threshold.  
1 : Fault. Greater than threshold.  
Bit 5  
Bit 4  
FLT_BUCK2_OV  
UV interrupt indicator. Read only and cleared.  
0 : No Fault. Greater than threshold.  
FLT_BUCK2_UV  
1 : Fault. Less than threshold or recovery after less than threshold.  
Register  
Address  
Register  
0x16  
FLT_RECORDBUCK3  
Name  
Bits  
Default  
Read/Write  
Bits  
Bit 7  
0
Bit 6  
0
Bit 5  
0
Bit 4  
0
Bit 3  
0
Bit 2  
0
Bit 1  
0
Bit 0  
0
R
R
RC  
RC  
R
R
R
R
Name  
Description  
Power good status indicator.  
Bit 7  
BUCK3_PG  
Reserved  
0 : VOUT > 110% of setting VOUT or VOUT < 90% of setting VOUT  
1 : 110% of setting VOUT > VOUT > 90% of setting VOUT  
Bit 6  
Bit 3 to Bit 0  
Reserved bits  
OV interrupt indicator. Read only and cleared.  
0 : No Fault. Less than threshold.  
1 : Fault. Greater than threshold.  
Bit 5  
Bit 4  
FLT_BUCK3_OV  
UV interrupt indicator. Read only and cleared.  
0 : No Fault. Greater than threshold.  
FLT_BUCK3_UV  
1 : Fault. Less than threshold or recovery after less than threshold.  
Copyright © 2019 Richtek Technology Corporation. All rights reserved.  
is a registered trademark of Richtek Technology Corporation.  
www.richtek.com  
30  
DS5800-00 November 2019  
RT5800  
Register  
Address  
Register  
Name  
0x22  
IO_I2CCFG  
Bits  
Default  
Read/Write  
Bits  
Bit 7  
0
Bit 6  
0
Bit 5  
0
Bit 4  
1
Bit 3  
1
Bit 2  
0
Bit 1  
0
Bit 0  
0
R
R
R
R
R
R
R
R
Name  
Description  
Bit 7  
Reserved  
Reserved bits  
IO_I2CADDR  
Bit 6 to Bit 0  
IO_I2CADDR  
Register  
Address  
Register  
Name  
0x25  
IO_RSTDVS  
Bits  
Default  
Bit 7  
Bit 6  
Bit 5  
0
Bit 4  
0
Bit 3  
0
Bit 2  
0
Bit 1  
0
Bit 0  
0
0
0
Read/Write  
Bits  
R
RW  
RW  
RW  
R
RW  
RW  
RW  
Name  
Reserved  
Description  
Bit 7 and Bit 3  
Reserved bits  
Enable/disable Buck3 watchdog reset function to default voltage when  
WDOG_RST pin is pulled low.  
1 : Enable  
0 : Disable  
Bit 6  
Bit 5  
Bit 4  
Enable/disable Buck2 watchdog reset function to default voltage when  
WDOG_RST pin is pulled low.  
1 : Enable  
IO_RSTDVS  
0 : Disable  
Enable/disable Buck1 watchdog reset function to default voltage when  
WDOG_RST pin is pulled low.  
1 : Enable  
0 : Disable  
Watchdog Debounce Time  
000 : 0ms (Default)  
001 : 1.56ms  
100 : 12.5ms  
101 : 9ms  
Bit 2 to Bit 0  
IO_DBNTIME  
010 : 3.125ms  
011 : 6.25ms  
110 : 15.25ms  
111 : 14.5ms  
Copyright © 2019 Richtek Technology Corporation. All rights reserved.  
is a registered trademark of Richtek Technology Corporation.  
DS5800-00 November 2019  
www.richtek.com  
31  
RT5800  
Register  
Address  
Register  
Name  
0x30  
FLT_OT_CTRL  
Bits  
Default  
Read/Write  
Bits  
Bit 7  
0
Bit 6  
0
Bit 5  
0
Bit 4  
0
Bit 3  
0
Bit 2  
0
Bit 1  
0
Bit 0  
0
R
R
R
R
RW  
R
R
R
Name  
Description  
Bit 7 to Bit 4  
Bit 2 to Bit 0  
Reserved  
Reserved bits  
When OT is detected, the Buck can be set to shutdown or not shutdown.  
Bit 3  
FLT_CTRLOT1  
0 : Shutdown  
1 : Not Shutdown  
Register  
Address  
Register  
0x32  
FLT_MASKTEMP  
Name  
Bits  
Default  
Read/Write  
Bits  
Bit 7  
0
Bit 6  
0
Bit 5  
0
Bit 4  
0
Bit 3  
0
Bit 2  
0
Bit 1  
0
Bit 0  
0
RW  
R
R
R
R
RW  
RW  
R
Name  
Description  
Masking the BOOT detection signal.  
0 : Pass internal logic output to INT pin.  
1 : Mask internal logic output to INT pin.  
Bit 7  
FLT_MASKBOOT  
Reserved  
Bit 6 to Bit 3  
Bit 0  
Reserved bits  
Masking the Hot die detection signal.  
0 : Pass internal logic output to INT pin.  
1 : Mask internal logic output to INT pin.  
Bit 2  
Bit 1  
FLT_MASKHD  
Masking the Thermal shutdown detection signal.  
0 : Pass internal logic output to INT pin.  
1 : Mask internal logic output to INT pin.  
FLT_MASKTSDR  
Copyright © 2019 Richtek Technology Corporation. All rights reserved.  
is a registered trademark of Richtek Technology Corporation.  
www.richtek.com  
32  
DS5800-00 November 2019  
RT5800  
Register  
Address  
Register  
Name  
0x33  
FLT_MASKBUCK1  
Bits  
Default  
Read/Write  
Bits  
Bit 7  
0
Bit 6  
0
Bit 5  
0
Bit 4  
0
Bit 3  
0
Bit 2  
0
Bit 1  
0
Bit 0  
0
RW  
RW  
RW  
RW  
R
R
R
R
Name  
Description  
Masking Buck1 power good detection signal.  
Bit 7  
Bit 6  
Bit 5  
FLT_BUCK1MASKPG 0 : Pass internal logic output to INT pin.  
1 : Mask internal logic output to INT pin.  
Write this bit to "1" to ensure Buck1 INT function normally. "0" is  
reserved for Richtek internal use only.  
BUCK1INTACT  
Masking Buck1 over voltage detection signal.  
FLT_BUCK1MASKOV 0 : Pass internal logic output to INT pin.  
1 : Mask internal logic output to INT pin.  
Masking Buck1 under voltage detection signal.  
FLT_BUCK1MASKUV 0 : Pass internal logic output to INT pin.  
1 : Mask internal logic output to INT pin.  
Bit 4  
Bit 3 to Bit 0  
Reserved  
Reserved bits  
Register  
Address  
Register  
Name  
0x34  
FLT_MASKBUCK2  
Bits  
Default  
Read/Write  
Bits  
Bit 7  
Bit 6  
0
Bit 5  
0
Bit 4  
0
Bit 3  
0
Bit 2  
0
Bit 1  
0
Bit 0  
0
0
RW  
RW  
RW  
RW  
R
R
R
R
Name  
Description  
Masking Buck2 power good detection signal.  
Bit 7  
Bit 6  
Bit 5  
FLT_BUCK2MASKPG 0 : Pass internal logic output to INT pin.  
1 : Mask internal logic output to INT pin.  
Write this bit to "1" to ensure Buck2 INT function normally. "0" is  
reserved for Richtek internal use only.  
BUCK2INTACT  
Masking Buck2 over voltage detection signal.  
FLT_BUCK2MASKOV 0 : Pass internal logic output to INT pin.  
1 : Mask internal logic output to INT pin.  
Masking Buck2 under voltage detection signal.  
FLT_BUCK2MASKUV 0 : Pass internal logic output to INT pin.  
1 : Mask internal logic output to INT pin.  
Bit 4  
Bit 3 to Bit 0  
Reserved  
Reserved bits  
Copyright © 2019 Richtek Technology Corporation. All rights reserved.  
is a registered trademark of Richtek Technology Corporation.  
DS5800-00 November 2019  
www.richtek.com  
33  
RT5800  
Register  
Address  
Register  
Name  
0x35  
FLT_MASKBUCK3  
Bits  
Default  
Read/Write  
Bits  
Bit 7  
0
Bit 6  
0
Bit 5  
0
Bit 4  
0
Bit 3  
0
Bit 2  
0
Bit 1  
0
Bit 0  
0
RW  
RW  
RW  
RW  
R
R
R
R
Name  
Description  
Masking Buck3 power good detection signal.  
Bit 7  
Bit 6  
Bit 5  
FLT_BUCK3MASKPG 0 : Pass internal logic output to INT pin.  
1 : Mask internal logic output to INT pin.  
Write this bit to "1" to ensure Buck3 INT function normally. "0" is  
reserved for Richtek internal use only.  
BUCK3INTACT  
Masking Buck3 over voltage detection signal.  
FLT_BUCK3MASKOV 0 : Pass internal logic output to INT pin.  
1 : Mask internal logic output to INT pin.  
Masking Buck3 under voltage detection signal.  
FLT_BUCK3MASKUV 0 : Pass internal logic output to INT pin.  
1 : Mask internal logic output to INT pin.  
Bit 4  
Bit 3 to Bit 0  
Reserved  
Reserved bits  
Register  
Address  
Register  
Name  
0x37  
FLT_BUCK1_CTRL  
Bits  
Default  
Read/Write  
Bits  
Bit 7  
Bit 6  
0
Bit 5  
0
Bit 4  
0
Bit 3  
1
Bit 2  
1
Bit 1  
0
Bit 0  
0
0
R
R
R
R
RW  
R
R
R
Name  
Reserved  
Description  
Bit 7 to Bit 4  
Bit 2 to Bit 0  
Reserved bits  
Latch or hiccup protection behavior when Buck1 suffers UV detection.  
0 : UV Shutdown  
1 : UV Hiccup  
FLT_BUCK1_  
CTRLUV  
Bit 3  
Register  
Address  
Register  
0x38  
FLT_BUCK2_CTRL  
Name  
Bits  
Default  
Read/Write  
Bits  
Bit 7  
Bit 6  
Bit 5  
0
Bit 4  
0
Bit 3  
1
Bit 2  
1
Bit 1  
0
Bit 0  
0
0
0
R
R
R
R
RW  
R
R
R
Name  
Description  
Bit 7 to Bit 4  
Bit 2 to Bit 0  
Reserved  
Reserved bits  
Latch or hiccup protection behavior when Buck2 suffers UV detection.  
0 : UV Shutdown  
1 : UV Hiccup  
FLT_BUCK2_  
CTRLUV  
Bit 3  
Copyright © 2019 Richtek Technology Corporation. All rights reserved.  
is a registered trademark of Richtek Technology Corporation.  
www.richtek.com  
34  
DS5800-00 November 2019  
RT5800  
Register  
Address  
Register  
Name  
0x39  
FLT_BUCK3_CTRL  
Bits  
Default  
Read/Write  
Bits  
Bit 7  
0
Bit 6  
0
Bit 5  
0
Bit 4  
0
Bit 3  
1
Bit 2  
1
Bit 1  
0
Bit 0  
0
R
R
R
R
RW  
R
R
R
Name  
Description  
Bit 7 to Bit 4  
Bit 2 to Bit 0  
Reserved  
Reserved bits  
Latch or hiccup protection behavior when Buck3 suffers UV detection.  
0 : UV Shutdown  
1 : UV Hiccup  
FLT_BUCK3_  
CTRLUV  
Bit 3  
Register  
Address  
Register  
0x3E  
BUCK1_RAMP  
Name  
Bits  
Default  
Read/Write  
Bits  
Bit 7  
Bit 6  
Bit 5  
0
Bit 4  
0
Bit 3  
0
Bit 2  
1
Bit 1  
0
Bit 0  
0
0
1
R
RW  
R
R
R
RW  
R
R
Name  
Description  
Bit 7  
Bit 5 to Bit 3  
Bit 1 to Bit 0  
Reserved  
Reserved bits  
The operation mode when Buck1 ramps up.  
Bit 6  
Bit 2  
BUCK1_DVS_UP  
0 : Auto Mode  
1 : FCCM  
The operation mode when Buck1 ramps down.  
BUCK1_DVS_DOWN 0 : Decay Mode  
1 : FCCM  
Register  
Address  
Register  
Name  
0x42  
BUCK1_CFG0  
Bits  
Default  
Bit 7  
0
Bit 6  
0
Bit 5  
0
Bit 4  
0
Bit 3  
0
Bit 2  
0
Bit 1  
0
Bit 0  
1
Read/Write  
Bits  
R
R
R
R
R
R
R
RW  
Name  
Description  
Bit 7 to Bit 1  
Reserved  
Reserved bits  
The output discharge resistor operates when Buck1 is turned off by  
software or external enable pin.  
0 : Disable output discharge resistor.  
Bit 0  
BUCK1_DIS  
1 : Enable output discharge resistor.  
Copyright © 2019 Richtek Technology Corporation. All rights reserved.  
is a registered trademark of Richtek Technology Corporation.  
DS5800-00 November 2019  
www.richtek.com  
35  
RT5800  
Register  
Address  
Register  
Name  
0x48  
BUCK1_DVS0CFG1  
Bits  
Default  
Read/Write  
Bits  
Bit 7  
1
Bit 6  
0
Bit 5  
0
Bit 4  
0
Bit 3  
Bit 2  
1
Bit 1  
Bit 0  
0
1
0
RW  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
Name  
Description  
Buck1 DVS0 output voltage setting  
SEL[7:0] = 11111111 : VOUT = 1.85V  
…
SEL[7:0] = 11001000 : VOUT = 1.3V  
…
Bit 7 to Bit 0  
BUCK1_DVS0  
SEL[7:0] = 0000000 : 0.3V  
For 0.3V to 1.3V, VOUT = 0.3V + SEL[7:0](decimal) x 5mV  
For 1.3V to 1.85V, VOUT = 1.3V + {SEL[7:0](decimal) - 200} x 10mV  
Register  
Address  
Register  
0x49  
BUCK1_DVS0CFG0  
Name  
Bits  
Default  
Read/Write  
Bits  
Bit 7  
0
Bit 6  
0
Bit 5  
0
Bit 4  
0
Bit 3  
0
Bit 2  
0
Bit 1  
0
Bit 0  
0
R
R
RW  
R
R
R
R
RW  
Name  
Description  
Bit 7 to Bit 6  
Bit 4 to Bit 1  
Reserved  
Reserved bits  
Buck1 DVS0 operation mode setting  
0 : Auto Mode  
1 : FCCM  
Bit 5  
Bit 0  
BUCK1_DVS0MODE  
Note : Please enable all the set outputs before setting into the FCCM.  
Enable or disable Buck1 DVS0  
0 : Disable  
BUCK1_ENDVS0  
1 : Enable  
Register  
Address  
Register  
0x4A  
BUCK1_DVS1CFG1  
Name  
Bits  
Default  
Read/Write  
Bits  
Bit 7  
1
Bit 6  
0
Bit 5  
0
Bit 4  
0
Bit 3  
1
Bit 2  
1
Bit 1  
0
Bit 0  
0
RW  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
Name  
Description  
Buck1 DVS1 output voltage setting  
SEL[7:0] = 11111111 : VOUT = 1.85V  
…
SEL[7:0] = 11001000 : VOUT = 1.3V  
…
Bit 7 to Bit 0  
BUCK1_DVS1  
SEL[7:0] = 0000000 : 0.3V  
For 0.3V to 1.3V, VOUT = 0.3V + SEL[7:0](decimal) x 5mV  
For 1.3V to 1.85V, VOUT = 1.3V + {SEL[7:0](decimal) - 200} x 10mV  
Copyright © 2019 Richtek Technology Corporation. All rights reserved.  
is a registered trademark of Richtek Technology Corporation.  
www.richtek.com  
36  
DS5800-00 November 2019  
RT5800  
Register  
Address  
Register  
Name  
0x4B  
BUCK1_DVS1CFG0  
Bits  
Default  
Read/Write  
Bits  
Bit 7  
0
Bit 6  
0
Bit 5  
0
Bit 4  
0
Bit 3  
Bit 2  
0
Bit 1  
Bit 0  
0
0
0
R
R
RW  
R
R
R
R
RW  
Name  
Description  
Bit 7 to Bit 6  
Bit 4 to Bit 1  
Reserved  
Reserved bits  
Buck1 DVS1 operation mode setting  
0 : Auto Mode  
1 : FCCM  
Bit 5  
Bit 0  
BUCK1_DVS1MODE  
Note : Please enable all the set outputs before setting into the FCCM.  
Enable or disable Buck1 DVS1  
0 : Disable  
BUCK1_ENDVS1  
1 : Enable  
Register  
Address  
Register  
0x52  
BUCK1_DVSCFG  
Name  
Bits  
Default  
Bit 7  
0
Bit 6  
0
Bit 5  
0
Bit 4  
0
Bit 3  
0
Bit 2  
0
Bit 1  
0
Bit 0  
0
Read/Write  
Bits  
R
R
R
R
R
RW  
RW  
RW  
Name  
Description  
Bit 7 to Bit 3  
Reserved  
Reserved bits  
When Buck1 DVS up and down operations are controlled by using  
external VSELA pin, this bit can define the polarity for VSELA.  
0 : VSELA = 1 => use DVS0 setting  
BUCK1_DVSPIN_  
POL  
Bit 2  
VSELA = 0 => use DVS1 setting  
1 : VSELA = 1 => use DVS1 setting  
VSELA = 0 => use DVS0 setting  
Buck1 DVS up and down operations are controlled by software or  
external pin.  
Bit 1 to Bit 0  
BUCK1_DVS_CTRL 00 : Use DVS0 setting  
01 : Use DVS1 setting  
10 : Controlled by VSELA pin  
Copyright © 2019 Richtek Technology Corporation. All rights reserved.  
is a registered trademark of Richtek Technology Corporation.  
DS5800-00 November 2019  
www.richtek.com  
37  
RT5800  
Register  
Address  
Register  
Name  
0x54  
BUCK1_RSPCFG  
Bits  
Default  
Read/Write  
Bits  
Bit 7  
0
Bit 6  
0
Bit 5  
0
Bit 4  
1
Bit 3  
0
Bit 2  
1
Bit 1  
0
Bit 0  
0
R
RW  
RW  
RW  
R
RW  
RW  
RW  
Name  
Description  
Bit 7, Bit 3  
Reserved  
Reserved bits  
Buck1 DVS slew rate setting for DVS UP  
001 = 16mV step/s 101 = 2mV step/s  
Bit 6 to Bit 4  
Bit 2 to Bit 0  
BUCK1_RSPUP  
011 = 8mV step/s  
100 = 4mV step/s  
110 = 1mV step/s  
111 = 0.5mV step/s  
Buck1 DVS slew rate setting for DVS Down  
001 = 16mV step/s 101 = 2mV step/s  
BUCK1_RSPDN  
011 = 8mV step/s  
100 = 4mV step/s  
110 = 1mV step/s  
111 = 0.5mV step/s  
Register  
Address  
Register  
Name  
0x55  
BUCK1_SLEWCTRL  
Bits  
Default  
Read/Write  
Bits  
Bit 7  
0
Bit 6  
0
Bit 5  
0
Bit 4  
0
Bit 3  
0
Bit 2  
0
Bit 1  
0
Bit 0  
0
R
R
RW  
RW  
R
R
R
R
Name  
Description  
Bit 7 to Bit 6  
Bit 3 to Bit 0  
Reserved  
Reserved bits  
Set the soft-start slew rate when Buck1 is turned on by software or  
external enable pin.  
Bit 5 to Bit 4  
BUCK1_SS_SLEW  
00 = 10mV/s  
01 = 5mV/s  
10 = 2.5mV/s  
11 = 1.25mV/s  
Register  
Address  
Register  
Name  
0x5B  
BUCK2_RAMP  
Bits  
Default  
Read/Write  
Bits  
Bit 7  
0
Bit 6  
1
Bit 5  
0
Bit 4  
0
Bit 3  
0
Bit 2  
1
Bit 1  
0
Bit 0  
0
R
RW  
R
R
R
RW  
R
R
Name  
Description  
Bit 7  
Bit 5 to Bit 3  
Bit 1 to Bit 0  
Reserved  
Reserved bits  
The operation mode when Buck2 ramps up.  
Bit 6  
Bit 2  
BUCK2_DVS_UP  
0 : Auto Mode  
1 : FCCM  
The operation mode when Buck2 ramps down.  
BUCK2_DVS_DOWN 0 : Decay Mode  
1 : FCCM  
Copyright © 2019 Richtek Technology Corporation. All rights reserved.  
is a registered trademark of Richtek Technology Corporation.  
www.richtek.com  
38  
DS5800-00 November 2019  
RT5800  
Register  
Address  
Register  
Name  
0x5F  
BUCK2_CFG0  
Bits  
Default  
Bit 7  
0
Bit 6  
0
Bit 5  
0
Bit 4  
0
Bit 3  
0
Bit 2  
0
Bit 1  
0
Bit 0  
1
Read/Write  
Bits  
R
R
R
R
R
R
R
RW  
Name  
Description  
Bit 7 to Bit 1  
Reserved  
Reserved bits  
The output discharge resistor operation when Buck2 is turned off by  
software or external enable pin.  
0 : Disable output discharge resistor.  
Bit 0  
BUCK2_DIS  
1 : Enable output discharge resistor.  
Register  
Address  
Register  
0x62  
BUCK2_DVS0CFG1  
Name  
Bits  
Default  
Read/Write  
Bits  
Bit 7  
Bit 6  
0
Bit 5  
0
Bit 4  
0
Bit 3  
1
Bit 2  
1
Bit 1  
0
Bit 0  
0
1
RW  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
Name  
Description  
Buck2 DVS0 output voltage setting  
SEL[7:0] = 11111111 : VOUT = 1.85V  
…
SEL[7:0] = 11001000 : VOUT = 1.3V  
…
Bit 7 to Bit 0  
BUCK2_DVS0  
SEL[7:0] = 0000000 : 0.3V  
For 0.3V to 1.3V, VOUT = 0.3V + SEL[7:0](decimal) x 5mV  
For 1.3V to 1.85V, VOUT = 1.3V + {SEL[7:0](decimal) - 200} x 10mV  
Register  
Address  
Register  
0x63  
BUCK2_DVS0CFG0  
Name  
Bits  
Default  
Read/Write  
Bits  
Bit 7  
0
Bit 6  
0
Bit 5  
0
Bit 4  
0
Bit 3  
0
Bit 2  
0
Bit 1  
0
Bit 0  
0
R
R
RW  
R
R
R
R
RW  
Name  
Description  
Bit 7 to Bit 6  
Bit 4 to Bit 1  
Reserved  
Reserved bits  
Buck2 DVS0 operation mode setting  
0 : Auto Mode  
1 : FCCM  
Bit 5  
Bit 0  
BUCK2_DVS0MODE  
Note : Please enable all the set outputs before setting into the FCCM.  
Enable or disable Buck2 DVS0  
0 : Disable  
BUCK2_ENDVS0  
1 : Enable  
Copyright © 2019 Richtek Technology Corporation. All rights reserved.  
is a registered trademark of Richtek Technology Corporation.  
DS5800-00 November 2019  
www.richtek.com  
39  
RT5800  
Register  
Address  
Register  
Name  
0x64  
BUCK2_DVS1CFG1  
Bits  
Default  
Read/Write  
Bits  
Bit 7  
1
Bit 6  
0
Bit 5  
0
Bit 4  
0
Bit 3  
Bit 2  
1
Bit 1  
Bit 0  
0
1
0
RW  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
Name  
Description  
Buck2 DVS1 output voltage setting  
SEL[7:0] = 11111111 : VOUT = 1.85V  
…
SEL[7:0] = 11001000 : VOUT = 1.3V  
…
Bit 7 to Bit 0  
BUCK2_DVS1  
SEL[7:0] = 0000000 : 0.3V  
For 0.3V to 1.3V, VOUT = 0.3V + SEL[7:0](decimal) x 5mV  
For 1.3V to 1.85V, VOUT = 1.3V + {SEL[7:0](decimal) - 200} x 10mV  
Register  
Address  
Register  
0x65  
BUCK2_DVS1CFG0  
Name  
Bits  
Default  
Read/Write  
Bits  
Bit 7  
0
Bit 6  
0
Bit 5  
0
Bit 4  
0
Bit 3  
0
Bit 2  
0
Bit 1  
0
Bit 0  
0
R
R
RW  
R
R
R
R
RW  
Name  
Description  
Bit 7 to Bit 6  
Bit 4 to Bit 1  
Reserved  
Reserved bits  
Buck2 DVS1 operation mode setting  
0 : Auto Mode  
1 : FCCM  
Bit 5  
Bit 0  
BUCK2_DVS1MODE  
Note : Please enable all the set outputs before setting into the FCCM.  
Enable or disable Buck2 DVS1  
0 : Disable  
BUCK2_ENDVS1  
1 : Enable  
Copyright © 2019 Richtek Technology Corporation. All rights reserved.  
is a registered trademark of Richtek Technology Corporation.  
www.richtek.com  
40  
DS5800-00 November 2019  
RT5800  
Register  
Address  
Register  
Name  
0x6C  
BUCK2_DVSCFG  
Bits  
Default  
Bit 7  
0
Bit 6  
0
Bit 5  
0
Bit 4  
0
Bit 3  
0
Bit 2  
0
Bit 1  
0
Bit 0  
0
Read/Write  
Bits  
R
R
R
R
R
RW  
RW  
RW  
Name  
Description  
Bit 7 to Bit 3  
Reserved  
Reserved bits  
When Buck2 DVS up and down operations are controlled by using  
external VSELA pin, this bit can define the polarity for VSELA.  
0 : VSELA = 1 => use DVS0 setting  
BUCK2_DVSPIN_  
POL  
Bit 2  
VSELA = 0 => use DVS1 setting  
1 : VSELA = 1 => use DVS1 setting  
VSELA = 0 => use DVS0 setting  
Buck2 DVS up and down operations are controlled by software or  
external pin.  
Bit 1 to Bit 0  
BUCK2_DVS_CTRL 00 : Use DVS0 setting  
01 : Use DVS1 setting  
10 : Controlled by VSELA pin  
Register  
Address  
Register  
Name  
0x6E  
BUCK2_RSPCFG  
Bits  
Default  
Read/Write  
Bits  
Bit 7  
0
Bit 6  
0
Bit 5  
0
Bit 4  
1
Bit 3  
0
Bit 2  
1
Bit 1  
0
Bit 0  
0
R
RW  
RW  
RW  
R
RW  
RW  
RW  
Name  
Description  
Bit 7, Bit 3  
Reserved  
Reserved bits  
Buck2 DVS slew rate setting for DVS UP  
001 = 16mV step/s 101 = 2mV step/s  
Bit 6 to Bit 4  
Bit 2 to Bit 0  
BUCK2_RSPUP  
011 = 8mV step/s  
100 = 4mV step/s  
110 = 1mV step/s  
111 = 0.5mV step/s  
Buck2 DVS slew rate setting for DVS Down  
001 = 16mV step/s 101 = 2mV step/s  
BUCK2_RSPDN  
011 = 8mV step/s  
100 = 4mV step/s  
110 = 1mV step/s  
111 = 0.5mV step/s  
Copyright © 2019 Richtek Technology Corporation. All rights reserved.  
is a registered trademark of Richtek Technology Corporation.  
DS5800-00 November 2019  
www.richtek.com  
41  
RT5800  
Register  
Address  
Register  
Name  
0x6F  
BUCK2_SLEWCTRL  
Bits  
Default  
Read/Write  
Bits  
Bit 7  
0
Bit 6  
0
Bit 5  
0
Bit 4  
0
Bit 3  
Bit 2  
0
Bit 1  
Bit 0  
0
0
0
R
R
RW  
RW  
R
R
R
R
Name  
Description  
Bit 7 to Bit 6  
Bit 3 to Bit 0  
Reserved  
Reserved bits  
Set the soft-start slew rate when Buck2 is turned on by software or  
external enable pin.  
Bit 5 to Bit 4  
BUCK2_SS_SLEW  
00 = 10mV/s  
01 = 5mV/s  
10 = 2.5mV/s  
11 = 1.25mV/s  
Register  
Address  
Register  
Name  
0x75  
BUCK3_RAMP  
Bits  
Default  
Read/Write  
Bits  
Bit 7  
0
Bit 6  
1
Bit 5  
0
Bit 4  
0
Bit 3  
0
Bit 2  
1
Bit 1  
0
Bit 0  
0
R
RW  
R
R
R
RW  
R
R
Name  
Description  
Bit 7  
Bit 5 to Bit 3  
Bit 1 to Bit 0  
Reserved  
Reserved bits  
The operation mode when Buck3 ramps up.  
Bit 6  
Bit 2  
BUCK3_DVS_UP  
0 : Auto Mode  
1 : FCCM  
The operation mode when Buck3 ramps down.  
BUCK3_DVS_DOWN 0 : Decay Mode  
1 : FCCM  
Register  
Address  
Register  
Name  
0x79  
BUCK3_CFG0  
Bits  
Default  
Bit 7  
0
Bit 6  
0
Bit 5  
0
Bit 4  
0
Bit 3  
0
Bit 2  
0
Bit 1  
0
Bit 0  
1
Read/Write  
Bits  
R
R
R
R
R
R
R
RW  
Name  
Description  
Bit 7 to Bit 1  
Reserved  
Reserved bits  
The output discharge resistor operation when Buck3 is turned off by  
software or external enable pin.  
0 : Disable output discharge resistor.  
Bit 0  
BUCK3_DIS  
1 : Enable output discharge resistor.  
Copyright © 2019 Richtek Technology Corporation. All rights reserved.  
is a registered trademark of Richtek Technology Corporation.  
www.richtek.com  
42  
DS5800-00 November 2019  
RT5800  
Register  
Address  
Register  
Name  
0x7C  
BUCK3_DVS0CFG1  
Bits  
Default  
Read/Write  
Bits  
Bit 7  
1
Bit 6  
0
Bit 5  
0
Bit 4  
0
Bit 3  
Bit 2  
1
Bit 1  
Bit 0  
0
1
0
RW  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
Name  
Description  
Buck3 DVS0 output voltage setting  
SEL[7:0] = 11111111 : VOUT = 1.85V  
…
SEL[7:0] = 11001000 : VOUT = 1.3V  
…
Bit 7 to Bit 0  
BUCK3_DVS0  
SEL[7:0] = 0000000 : 0.3V  
For 0.3V to 1.3V, VOUT = 0.3V + SEL[7:0](decimal) x 5mV  
For 1.3V to 1.85V, VOUT = 1.3V + {SEL[7:0](decimal) - 200} x 10mV  
Register  
Address  
Register  
0x7D  
BUCK3_DVS0CFG0  
Name  
Bits  
Default  
Read/Write  
Bits  
Bit 7  
0
Bit 6  
0
Bit 5  
0
Bit 4  
0
Bit 3  
0
Bit 2  
0
Bit 1  
0
Bit 0  
0
R
R
RW  
R
R
R
R
RW  
Name  
Description  
Bit 7 to Bit 6  
Bit 4 to Bit 1  
Reserved  
Reserved bits  
Buck3 DVS0 operation mode setting  
0 : Auto Mode  
1 : FCCM  
Bit 5  
Bit 0  
BUCK3_DVS0MODE  
Note : Please enable all the set outputs before setting into the FCCM.  
Enable or disable Buck3 DVS0  
0 : Disable  
BUCK3_ENDVS0  
1 : Enable  
Register  
Address  
Register  
0x7E  
BUCK3_DVS1CFG1  
Name  
Bits  
Default  
Read/Write  
Bits  
Bit 7  
1
Bit 6  
0
Bit 5  
0
Bit 4  
0
Bit 3  
1
Bit 2  
1
Bit 1  
0
Bit 0  
0
RW  
RW  
RW  
RW  
RW  
RW  
RW  
RW  
Name  
Description  
Buck3 DVS1 output voltage setting  
SEL[7:0] = 11111111 : VOUT = 1.85V  
…
SEL[7:0] = 11001000 : VOUT = 1.3V  
…
Bit 7 to Bit 0  
BUCK3_DVS1  
SEL[7:0] = 0000000 : 0.3V  
For 0.3V to 1.3V, VOUT = 0.3V + SEL[7:0](decimal) x 5mV  
For 1.3V to 1.85V, VOUT = 1.3V + {SEL[7:0](decimal) - 200} x 10mV  
Copyright © 2019 Richtek Technology Corporation. All rights reserved.  
is a registered trademark of Richtek Technology Corporation.  
DS5800-00 November 2019  
www.richtek.com  
43  
RT5800  
Register  
Address  
Register  
Name  
0x7F  
BUCK3_DVS1CFG0  
Bits  
Default  
Read/Write  
Bits  
Bit 7  
0
Bit 6  
0
Bit 5  
0
Bit 4  
0
Bit 3  
Bit 2  
0
Bit 1  
Bit 0  
0
0
0
R
R
RW  
R
R
R
R
RW  
Name  
Description  
Bit 7 to Bit 6  
Bit 4 to Bit 1  
Reserved  
Reserved bits  
Buck3 DVS1 operation mode setting  
0 : Auto Mode  
1 : FCCM  
Bit 5  
Bit 0  
BUCK3_DVS1MODE  
Note : Please enable all the set outputs before setting into the FCCM.  
Enable or disable Buck3 DVS1  
0 : Disable  
BUCK3_ENDVS1  
1 : Enable  
Register  
Address  
Register  
0x86  
BUCK3_DVSCFG  
Name  
Bits  
Default  
Bit 7  
0
Bit 6  
0
Bit 5  
0
Bit 4  
0
Bit 3  
0
Bit 2  
0
Bit 1  
0
Bit 0  
0
Read/Write  
Bits  
R
R
R
R
R
RW  
RW  
RW  
Name  
Description  
Bit 7 to Bit 3  
Reserved  
Reserved bits  
When Buck3 DVS up and down operations are controlled by using  
external VSELA pin, this bit can define the polarity for VSELA.  
0 : VSELA = 1 => use DVS0 setting  
BUCK3_DVSPIN_  
POL  
Bit 2  
VSELA = 0 => use DVS1 setting  
1 : VSELA = 1 => use DVS1 setting  
VSELA = 0 => use DVS0 setting  
Buck3 DVS up and down operations are controlled by software or  
external pin.  
Bit 1 to Bit 0  
BUCK3_DVS_CTRL 00 : Use DVS0 setting  
01 : Use DVS1 setting  
10 : Controlled by VSELA pin  
Copyright © 2019 Richtek Technology Corporation. All rights reserved.  
is a registered trademark of Richtek Technology Corporation.  
www.richtek.com  
44  
DS5800-00 November 2019  
RT5800  
Register  
Address  
Register  
Name  
0x88  
BUCK3_RSPCFG  
Bits  
Default  
Read/Write  
Bits  
Bit 7  
0
Bit 6  
0
Bit 5  
0
Bit 4  
1
Bit 3  
0
Bit 2  
1
Bit 1  
0
Bit 0  
0
R
RW  
RW  
RW  
R
RW  
RW  
RW  
Name  
Description  
Bit 7, Bit 3  
Reserved  
Reserved bits  
Buck3 DVS slew rate setting for DVS UP  
001 = 16mV step/s 101 = 2mV step/s  
Bit 6 to Bit 4  
Bit 2 to Bit 0  
BUCK3_RSPUP  
011 = 8mV step/s  
100 = 4mV step/s  
110 = 1mV step/s  
111 = 0.5mV step/s  
Buck3 DVS slew rate setting for DVS Down  
001 = 16mV step/s 101 = 2mV step/s  
BUCK3_RSPDN  
011 = 8mV step/s  
100 = 4mV step/s  
110 = 1mV step/s  
111 = 0.5mV step/s  
Register  
Address  
Register  
Name  
0x89  
BUCK3_SLEWCTRL  
Bits  
Default  
Read/Write  
Bits  
Bit 7  
0
Bit 6  
0
Bit 5  
0
Bit 4  
0
Bit 3  
0
Bit 2  
0
Bit 1  
0
Bit 0  
0
R
R
RW  
RW  
R
R
R
R
Name  
Description  
Bit 7 to Bit 6  
Bit 3 to Bit 0  
Reserved  
Reserved bits  
Set the soft-start slew rate when Buck3 is turned on by software or  
external enable pin.  
Bit 5 to Bit 4  
BUCK3_SS_SLEW  
00 = 10mV/s  
01 = 5mV/s  
10 = 2.5mV/s  
11 = 1.25mV/s  
Copyright © 2019 Richtek Technology Corporation. All rights reserved.  
is a registered trademark of Richtek Technology Corporation.  
DS5800-00 November 2019  
www.richtek.com  
45  
RT5800  
Outline Dimension  
Dimensions In Millimeters  
Dimensions In Inches  
Symbol  
Min  
Max  
0.800  
0.050  
0.250  
Min  
Max  
0.031  
0.002  
0.010  
A
0.700  
0.000  
0.175  
0.028  
0.000  
0.007  
A1  
A3  
Tolerance  
±0.050  
W-Type 30L QFN 4.5x5 (FC) Package  
Copyright © 2019 Richtek Technology Corporation. All rights reserved.  
is a registered trademark of Richtek Technology Corporation.  
www.richtek.com  
46  
DS5800-00 November 2019  
RT5800  
Footprint Information  
Package  
V/W/U/XQFN4.5x5-30(FC)  
Number of Pin  
30  
Tolerance  
±0.05  
Richtek Technology Corporation  
14F, No. 8, Tai Yuen 1st Street, Chupei City  
Hsinchu, Taiwan, R.O.C.  
Tel: (8863)5526789  
Richtek products are sold by description only. Customers should obtain the latest relevant information and data sheets before placing orders and should verify that  
such information is current and complete. Richtek cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Richtek product.  
Information furnished by Richtek is believed to be accurate and reliable. However, no responsibility is assumed by Richtek or its subsidiaries for its use; nor for any  
infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights  
of Richtek or its subsidiaries.  
Copyright © 2019 Richtek Technology Corporation. All rights reserved.  
is a registered trademark of Richtek Technology Corporation.  
DS5800-00 November 2019  
www.richtek.com  
47  

相关型号：

RT5C348B

 4-WIRE SERIAL INTERFACE
RICOH

RT5C475A

 PC Card Support
ETC

RT5N141C

 Transistor With Resistor
ISAHAYA

RT5N431C

 Transistor With Resistor
ISAHAYA

RT5P141C

 Transistor With Resistor
ISAHAYA

RT5P14BC

 Transistor With Resistor
ISAHAYA

RT5P230C

 Transistor With Resistor
ISAHAYA

RT5P231C

 Transistor
ISAHAYA

RT5P430C

 Transistor With Resistor
ISAHAYA

RT6010

 Dual Channel High Efficiency and High Accuracy Average Current Control LED Backlight Buck Controller
RICHTEK

RT6030

 4-CH LED Current Source Controller
RICHTEK

RT610

 Adatto alla lettura di codici e al rilevamento di tacche
ETC
©2020 ICPDF网 联系我们和版权申明