RT6203F [RICHTEK]
暂无描述;
| 型号： | RT6203F |
| 厂家： | 
RICHTEK TECHNOLOGY CORPORATION |
| 描述： | 暂无描述 |
| 文件： | 总21页 (文件大小：434K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
®
RT6203F
6A, 18V, 700kHz ACOTTM Synchronous Step-Down Converter
with VID Control
General Description
Features
VID Control Range Via I2C Compatible Interface :
The RT6203F is an adaptive on-time mode synchronous
Buck converter. The main control loop of the RT6203F
uses an adaptive on-time mode control which provides a
very fast transient response with no external components.
The RT6203F operates from 4.5V to 18V VINinput. After
the initial power-up, the output voltage can be changed by
codes sent into the IC via an I2C compatible VID control
bus. There are special codes which can be used to program
current limit level and thermal shutdown level. Shutdown
and startup can be also programmed by special codes.
The device also features an internal soft-start time. Output
voltage is adjustable by VID code setting. VOUT range is
between 0.6V to 1.62V
0.6V to 0.7V in 20mV Steps
0.7V to 1.2V in 10mV Steps
1.2V to 1.62V in 20mV Steps
Adjustable Current Limit
Adjustable Thermal Shutdown
Fast Transient Response
Steady 700kHz Switching Frequency
Optimized for All Ceramic Capacitors
Internal Soft-Start
Input Under-Voltage Lockout
Thermal Shutdown
RoHS Compliant and Halogen Free
Applications
Pin Configuration
Industrial and Commercial Low Power Systems
(TOP VIEW)
Computer Peripherals
8
EN
VOUT
PVCC
SDA
VIN
LCDMonitors and TVs
2
3
4
7
6
5
BOOT
SW
GND
Green Electronics/Appliances
Point of Load Regulation for High-Performance DSPs,
FPGAs, and ASICs
9
SCL
SOP-8 (Exposed Pad)
Simplified Application Circuit
RT6203F
L1
V
IN
VIN
EN
V
SW
OUT
C1
C3
C2
BOOT
VOUT
Enable
SCL
SDA
2
PVCC
I C Control
C4
GND
Copyright 2018 Richtek Technology Corporation. All rights reserved.
©
is a registered trademark of Richtek Technology Corporation.
DS6203F-00 December 2018
www.richtek.com
1
RT6203F
Ordering Information
RT6203F
Marking Information
RT6203FNGSP : Product Number
RT6203FN
GSPYMDNN
YMDNN : Date Code
Package Type
SP : SOP-8 (Exposed Pad-Option 2)
Lead Plating System
G : Green (Halogen Free and Pb Free)
UVP Trim Operation
N : Non-UVP
PWM/PSM Mode
F : PSM mode
Note :
Richtek products are :
RoHS compliant and compatible with the current require-
ments of IPC/JEDEC J-STD-020.
Suitable for use in SnPb or Pb-free soldering processes.
Functional Pin Description
Pin No.
Pin Name
Pin Function
Enable control input. Connect this pin to logic high can enable the device and
connect this pin to GND can disable the device.
1
EN
2
3
4
5
6
VOUT
PVCC
SDA
SCL
Output voltage controlled by VID.
5V power supply output. A capacitor (typical 1F) should be connected to GND.
Data I/O pin.
Clock I/O pin.
Switch output.
SW
Bootstrap. This capacitor is needed to drive the power switch's gate above the
supply voltage. It is connected between SW and BOOT pins to form a floating
supply across the power switch driver. A 0.1F capacitor is recommended for
use.
7
8
BOOT
VIN
Power input and connected to high-side MOSFET drain.
GND. The exposed pad must be soldered to a large PCB and connected to
GND for maximum thermal dissipation.
9 (Exposed Pad) GND
Copyright 2018 Richtek Technology Corporation. All rights reserved.
©
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
2
DS6203F-00 December 2018
RT6203F
Functional Block Diagram
PVCC
BOOT
V
IN
PVCC
Reg
PVCC
VIBIAS
PVCC
VIN
UGATE
LGATE
Min. Off
Control
Driver
SW
Current
Limit
GND
DAC OUT
SW
ZC
+
+
-
Comparator
V
EN
EN
IN
On-Time
VOUT
Serial
Interface
SDA
SCL
DAC
7bits
DAC OUT
Chip
Address
01101000
V
= 0.6V to
OUT
1.62V
Copyright 2018 Richtek Technology Corporation. All rights reserved.
©
is a registered trademark of Richtek Technology Corporation.
DS6203F-00 December 2018
www.richtek.com
3
RT6203F
Operation
The RT6203F is a high-efficiency, synchronous step-down
DC-DC converter that can deliver up to 6Aoutput current
from a 4.5V to 18V input supply.
Enable Control
The RT6203F provides an EN pin, as an external chip
enable control, to enable or disable the device. If VEN is
held below a logic-low threshold voltage (VIL) of the enable
input (EN), the converter will disable output voltage, that
is, the converter is disabled and switching is inhibited
even if the VIN voltage is above VIN under-voltage lockout
threshold (VUVLO). During shutdown mode, the supply
current can be reduced to ISHDN (10μAor below). If the EN
voltage rises above the logic-high threshold voltage (VIH)
while the VIN voltage is higher than UVLO threshold, the
device will be turned on, that is, switching being enabled
and soft-start sequence being initiated. This EN pin is a
high voltage pin and has an internal pull-high current to
implement automatic start-up.
Advanced Constant On-Time Control and PWM
Operation
The RT6203F adopts ACOTTM control for its ultrafast
transient response, low external component counts and
stable with low ESR MLCC output capacitors. When the
feedback voltage falls below the feedback reference
voltage, the minimum off-time one-shot (230ns, typ.) has
timed out and the inductor current is below the current
limit threshold, then the internal on-time one-shot circuitry
is triggered and the high-side switch is turn-on. Since the
minimum off-time is short, the device exhibits ultrafast
transient response and enables the use of smaller output
capacitance.
Soft-Start (SS)
The RT6203F provides an internal soft-start feature for
inrush control. At power up, the internal capacitor is
charged by an internal current source to generate a soft-
start ramp voltage as a reference voltage to the PWM
comparator. The device will initiate switching and the
output voltage will smoothly ramp up to its targeted
regulation voltage only after this ramp voltage is greater
than the target voltage to ensure the converters have a
smooth start-up from pre-biased output. The output voltage
starts to rise in 0.6ms from EN rising, and the soft-start
ramp-up time (VOUT from 0V to 0.95V) is 0.95ms.
The on-time is inversely proportional to input voltage and
directly proportional to output voltage to achieve pseudo-
fixed frequency over the input voltage range.After the on-
time one-shot timer expired, the high-side switch is turn-
off and the low-side switch is turn-on until the on-time
one-shot is triggered again. To achieve stable operation
with low-ESR ceramic output capacitors, an internal ramp
signal is added to the feedback reference voltage to
simulate the output voltage ripple.
Power Saving Mode
The RT6203F automatically enters power saving mode
(PSM) at light load to maintain high efficiency. As the
load current decreases and eventually the inductor current
ripple valley touches the zero current, which is the
boundary between continuous conduction and
discontinuous conduction modes. The low-side switch is
turned off when the zero inductor current is detected. As
the load current is further decreased, it takes longer time
to discharge the output capacitor to the level that requires
the next on-time. The switching frequency decreases and
is proportional to the load current to maintain high
efficiency at light load.
VIN = 12V
VIN
VCC = 5V
VCC
EN
0.6ms
0.95ms
VOUT
Copyright 2018 Richtek Technology Corporation. All rights reserved.
©
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
4
DS6203F-00 December 2018
RT6203F
Input Under-Voltage Lockout
The protection is activated outside of the absolute
maximum range of operation as a secondary fail-safe and
therefore should not be relied upon operationally.
Continuous operation above the specified absolute
maximum operating junction temperature may impair
device reliability or permanently damage the device.
In addition to the EN pin, the RT6203F also provides enable
control through the VIN pin. It features an under-voltage
lockout (UVLO) function that monitors the internal linear
regulator. If VEN rises above VIH first, switching will still be
inhibited until the VIN voltage rises above VUVLO. It is to
ensure that the internal regulator is ready so that operation
with not-fully-enhanced internal MOSFET switches can
be prevented. After the device is powered up, if the input
voltage VIN goes below the UVLO falling threshold voltage
(VUVLO − ΔVUVLO), this switching will be inhibited; if VIN
rises above the UVLO rising threshold (VUVLO), the device
will resume normal operation with a complete soft-start.
The Over-Current Protection
The RT6203F features cycle-by-cycle current-limit
protection on low-side MOSFETs and prevents the device
from the catastrophic damage in output short circuit and
over current.
The low-side MOSFET over-current protection is achieved
by measuring the inductor current through the
synchronous rectifier (low-side switch) during the low-side
on-time. Once the current rises above the low-side switch
valley current limit (ILIM_L), the on-time one-shot will be
inhibited until the inductor current ramps down to the
current limit level (ILIM_L), that is, another on-time can only
be triggered when the inductor current goes below the
low-side current limit. If the output load current exceeds
the available inductor current (clamped by the low-side
current limit), the output capacitor needs to supply the
extra current such that the output voltage will begin to
drop.
Thermal Shutdown
The RT6203F includes an over-temperature protection
(OTP) circuitry to prevent overheating due to excessive
power dissipation. The OTP will shut down switching
operation when junction temperature exceeds a thermal
shutdown threshold (TSD). Once the junction temperature
cools down by a thermal shutdown hysteresis (20°C,
typically), the IC will resume normal operation with a
complete soft-start.
Note that the over temperature protection is intended to
protect the device during momentary overload conditions.
Copyright 2018 Richtek Technology Corporation. All rights reserved.
©
is a registered trademark of Richtek Technology Corporation.
DS6203F-00 December 2018
www.richtek.com
5
RT6203F
Absolute Maximum Ratings (Note 1)
Supply Voltage, VIN------------------------------------------------------------------------------------------------------- −0.3V to 20V
Switch Voltage, SW------------------------------------------------------------------------------------------------------- −0.3V to 20.3V
<50ns ------------------------------------------------------------------------------------------------------------------------ −5V to 25V
BOOT Voltage -------------------------------------------------------------------------------------------------------------- −0.3V to 26.3V
Enable Voltage, EN ------------------------------------------------------------------------------------------------------- −0.3V to 20V
BOOT to Switch Voltage, BOOT − SW ------------------------------------------------------------------------------ −0.3V to 6V
Other Pins ------------------------------------------------------------------------------------------------------------------- −0.3V to 6V
Power Dissipation, PD @ TA = 25°C
SOP-8 (Exposed Pad) --------------------------------------------------------------------------------------------------- 3.44W
Package Thermal Resistance (Note 2)
SOP-8 (Exposed Pad), θJA ---------------------------------------------------------------------------------------------- 29°C/W
SOP-8 (Exposed Pad), θJC --------------------------------------------------------------------------------------------- 2°C/W
Junction Temperature ----------------------------------------------------------------------------------------------------- 150°C
Lead Temperature (Soldering, 10 sec.) ------------------------------------------------------------------------------- 260°C
Storage Temperature Range--------------------------------------------------------------------------------------------- −65°C to 150°C
ESD Susceptibility (Note 3)
HBM (Human Body Model) --------------------------------------------------------------------------------------------- 2kV
Recommended Operating Conditions (Note 4)
Supply Voltage, VIN ------------------------------------------------------------------------------------------------------ 4.5V to 18V
Junction Temperature Range-------------------------------------------------------------------------------------------- −40°C to 125°C
Ambient Temperature Range-------------------------------------------------------------------------------------------- −40°C to 85°C
Electrical Characteristics
(VIN = 12V, TA = 25°C, unless otherwise specified)
Parameter
Supply Current
Symbol
Test Conditions
Min
Typ
Max
Unit
Shutdown Current
Shutdown Current by VID
Quiescent Current
Logic Threshold
ISHDN
VEN = 0V
--
--
--
1.5
75
10
105
1.2
A
A
ISHDN_VID Special code = 1110110
IQ
VEN = 2V, VFB = 1V
0.55
mA
Logic-Low VIL
Logic-High VIH
--
1.6
--
--
--
1
0.4
--
EN Input Voltage
V
EN Pull-High Current
Output Voltage
Output Voltage
--
A
VOUT
VOUT
RT6203F
I2C mode
0.94
0.95
0.96
V
V
Ideal
VOUT
1.5%
Ideal
VOUT
+1.5%
Ideal
VOUT
Output Voltage
Special code = 1100001
(default) VOUT range between
0.7 to 1.2V
Minimum Output Voltage
Rising Time per 10mV
VOUT
--
1
--
s
Copyright 2018 Richtek Technology Corporation. All rights reserved.
©
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
6
DS6203F-00 December 2018
RT6203F
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
Maximum Output Voltage
Rising Time per 10mV
Special code = 1101000
VOUT
--
8
--
s
VOUT range between 0.7 to 1.2V
VPVCC Output
6V = VIN = 18V,
0 < IPVCC < 5mA
VPVCC Output Voltage
VPVCC
4.8
5
5.2
V
Line Regulation
Load Regulation
Output Current
RDS(ON)
VLINE
6V = VIN = 18V, IPVCC = 5mA
0 < IPVCC < 5mA
--
--
--
--
20
30
--
mV
mV
mA
VLOAD
IPVCC
VIN = 6V, VPVCC = 4V
100
210
RDS(ON)_H VBOOT – VSW = 5V
RDS(ON)_L
--
--
48
25
100
50
Switch-On Resistance
m
Current Limit
Special code = 1110000 (default)
Special code = 1110001
8.5
10
7.15
4.3
11.5
8.6
Low-Side Switch Current
Limit
ILIM_L
5.72
3.44
A
Special code = 1110010
5.16
On-Time Timer Control
Switching Frequency
Minimum On-Time
Minimum Off-Time
Soft-Start
fSW
--
--
--
700
60
--
--
--
kHz
ns
tON_MIN
tOFF_MIN
230
ns
Soft-Start Time
UVLO
tSS
--
950
--
s
VUVLO
Wake up VPVCC
Hysteresis
3.55
--
3.85
0.4
4.15
--
UVLO Threshold
V
VUVLO
Thermal Shutdown
Special code = 1110011 (default)
Special code = 1110100
--
--
--
150
130
170
--
--
--
Thermal Shutdown
Threshold
TSD
°C
Special code = 1110101
Note 1. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
These are stress ratings only, and functional operation of the device at these or any other conditions beyond those
indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating
conditions may affect device reliability.
Note 2. θJA is measured under natural convection (still air) at TA = 25°C with the component mounted on a high effective-
thermal-conductivity four-layer test board on a JEDEC 51-7 thermal measurement standard. θJC is measured at the
exposed pad of the package.
Note 3. Devices are ESD sensitive. Handling precaution is recommended.
Note 4. The device is not guaranteed to function outside its operating conditions.
Copyright 2018 Richtek Technology Corporation. All rights reserved.
©
is a registered trademark of Richtek Technology Corporation.
DS6203F-00 December 2018
www.richtek.com
7
RT6203F
Typical Application Circuit
L1
1.5µH
RT6203F
8
6
V
IN
V
OUT
VIN
EN
SW
C2
C3
100nF
C1
C5
22µF x 5
C4
10µF
10µF
100nF
7
2
3
BOOT
VOUT
PVCC
1
Enable
5
4
SCL
SDA
2
I C Control
C6
1µF
GND
9 (Exposed Pad)
C1/C2 = GRM21BR61E106
L1 = WE744770015
C5 = GRM188R60J226
Copyright 2018 Richtek Technology Corporation. All rights reserved.
©
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
8
DS6203F-00 December 2018
RT6203F
Typical Operating Characteristics
Efficiency vs. Output Current
Output Voltage vs. Output Current
100
0.970
0.965
0.960
0.955
0.950
0.945
0.940
0.935
0.930
90
80
VIN = 4.5V
70
VIN = 12V
VIN = 18V
60
50
40
30
20
10
0
VIN = 4.5V
VIN = 12V
VIN = 18V
VOUT = 0.95V
5 6
0
1
2
3
4
0
1
2
3
4
5
6
Output Current (A)
Output Current (A)
Output Voltage vs. Input Voltage
Choke Valley Current Limit vs. Input Voltage
12
0.970
11
0.965
0.960
0.955
0.950
0.945
0.940
0.935
0.930
ILIM = 10A
IOUT = 6A
IOUT = 3A
10
9
IOUT = 1A
IOUT = 100mA
ILIM = 7.15A
8
7
6
ILIM = 4.3A
5
4
VIN = 12V, VOUT = 1.1V
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18
4
6
8
10
12
14
16
18
Input Voltage (V)
Input Voltage (V)
I2C Shutdown Current vs. Input Voltage
UVLO Voltage vs. Temperature
4.40
4.20
4.00
3.80
3.60
3.40
3.20
150
140
130
120
110
100
90
Rising
Falling
80
70
60
VOUT = 1.2V, IOUT = 0A
50
-50
-25
0
25
50
75
100
125
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18
Temperature (°C)
Input Voltage (V)
Copyright 2018 Richtek Technology Corporation. All rights reserved.
©
is a registered trademark of Richtek Technology Corporation.
DS6203F-00 December 2018
www.richtek.com
9
RT6203F
EN Pin Threshold vs. Temperature
Output Ripple
1.60
1.55
1.50
1.45
1.40
1.35
1.30
1.25
1.20
1.15
1.10
1.05
1.00
VIN = 12V, VOUT = 0.95V, IOUT = 10mA
VOUT
Rising
Falling
(30mV/Div)
VSW
(5V/Div)
VIN = 12V, VOUT = 1.1V, IOUT = 0A
Time (100μs/Div)
-50
-25
0
25
50
75
100
125
Temperature (°C)
Load Transient
Output Ripple
VIN = 12V, VOUT = 0.95V, IOUT = 6A
VIN = 12V, VOUT = 0.95V
IOUT = 10mA to 3A, TR = TF = 1μs
VOUT
(30mV/Div)
VOUT
(50mV/Div)
VSW
(5V/Div)
IOUT
(3A/Div)
Time (50μs/Div)
Time (1μs/Div)
Load Transient
Power On from EN
VIN = 12V, VOUT = 0.95V
IOUT = 3A to 6A, TR = TF = 1μs
VIN = 12V, VOUT = 0.95V
OUT = 0A
VOUT
(50mV/Div)
VOUT
(400mV/Div)
I
VSW
(5V/Div)
VEN
(3V/Div)
IOUT
(1A/Div)
IOUT
(3A/Div)
Time (50μs/Div)
Time (500μs/Div)
Copyright 2018 Richtek Technology Corporation. All rights reserved.
©
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
10
DS6203F-00 December 2018
RT6203F
Power Off from EN
Power On from VIN
VOUT
(400mV/Div)
VIN = 12V, VOUT = 0.95V
IOUT = 0A
VOUT
(400mV/Div)
VIN = 12V, VOUT = 0.95V
OUT = 10mA
I
VSW
(5V/Div)
VSW
(5V/Div)
VEN
(3V/Div)
VIN
(10V/Div)
IOUT
(1A/Div)
IOUT
(1A/Div)
Time (5ms/Div)
Time (2ms/Div)
Power On than Short
Power Off from VIN
VOUT
(400mV/Div)
VOUT
(500mV/Div)
VIN = 12V, VOUT = 0.95V
OUT = 0A
I
VSW
(5V/Div)
VIN
(10V/Div)
IOUT
(2A/Div)
IOUT
(1A/Div)
VIN = 12V, VOUT = 0.95V, ILIM = 4.3A
Time (20μs/Div)
Time (50ms/Div)
VID Rising
VID Falling
VIN = 12V, IOUT = 6A
VID 0.6V to VID 1.62V
OUT slew rate =
1Code/1μs,
VIN = 12V, IOUT = 6A
VID 1.62V to VID 0.6V
V
VOUT slew rate = 1Code/1μs,
VOUT
(300mV/Div)
VOUT
(300mV/Div)
VSW
(5V/Div)
VSW
(5V/Div)
Time (50μs/Div)
Time (20μs/Div)
Copyright 2018 Richtek Technology Corporation. All rights reserved.
©
is a registered trademark of Richtek Technology Corporation.
DS6203F-00 December 2018
www.richtek.com
11
RT6203F
Application Information
I2C Interface Function
The RT6203F implements a subset of the I2C standard and provides a complete transaction command with a address
byte followed by a single 8-bit data byte. Becasue there is no register address, the read function and multi-byte data
transfer are not supported in this subset function. If the RT6203F fails to acknowledge for address byte or data byte, the
master should issue a STOP command of ERROR and try again.
The 7-bit address of the RT6203F with a WRITE operation bit can become an 8 bits I2C address byte. (Address =
0b01101000). Table 1 is the structure of the RT6203F Data Byte. Bit0 to Bit6 are the 7-bit code for one of 77 output
voltage and special function. After the soft-start time, Master can sent 8 bits data to control the VOUT of the RT6203F.
The voltages can be selected from Table 2 and Table 3 shows how to use special function. The bit7 is check-sum bit and
Master should set this bit to be the Exclusive-OR of [Bit6:Bit0]. In other words, the sum is even. If not, the RT6203F will
not send an ACK bit.
Table 1. Structure of the RT6203F Data Byte
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
ChkSum
D6
D5
D4
D3
D2
D1
D0
Table 2. VID Function
Code
VOUT
0.6
Code
VOUT
0.75
0.76
0.77
0.78
0.79
0.8
Code
20
VOUT
Code
VOUT
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
0.85
0.86
0.87
0.88
0.89
0.9
30
31
32
33
34
35
36
37
38
39
0.95
0.96
0.97
0.98
0.99
1
0.62
0.64
0.66
0.68
0.7
21
22
23
24
25
0.71
0.72
0.73
0.74
0.81
0.82
0.83
0.84
26
0.91
0.92
0.93
0.94
1.01
1.02
1.03
1.04
27
28
29
Code
40
VOUT
1.05
1.06
1.07
1.08
1.09
1.1
Code
50
VOUT
1.15
1.16
1.17
1.18
1.19
1.2
Code
60
VOUT
1.3
Code
70
VOUT
1.5
41
51
61
1.32
1.34
1.36
1.38
1.4
71
1.52
1.54
1.56
1.58
1.6
42
52
62
72
43
53
63
73
44
54
64
74
45
55
65
75
46
1.11
1.12
1.13
1.14
56
1.22
1.24
1.26
1.28
66
1.42
1.44
1.46
1.48
76
1.62
47
57
67
48
58
68
49
59
69
Copyright 2018 Richtek Technology Corporation. All rights reserved.
©
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
12
DS6203F-00 December 2018
RT6203F
Table 3 shows special codes and relative function. Special codes are valid during the soft-start time.
1110000 to 1110010 : To change the over current limit level.
1110011 to 1110101 : To change the over-temperature protection level.
1110110 to 1110111 : To shut down and start up IC.
1100001 to 1101000 : To change the VOUT slew rate.
Table 3. Special Function
Special Codes
1110000
1110001
1110010
1110011
1110100
1110101
1110110
1110111
1100001
1100010
1100011
1100100
1100101
1100110
1100111
1101000
Function
ILIM = 10A (default)
ILIM = 7.15A
ILIM = 4.3A
OT = 150°C (default)
OT = 130°C
OT = 170°C
Shutdown code
Start-up code
VOUT slew rate = Code /1s (default)
VOUT slew rate = Code /2s
VOUT slew rate = Code /3s
VOUT slew rate = Code /4s
VOUT slew rate = Code /5s
VOUT slew rate = Code /6s
VOUT slew rate = Code /7s
VOUT slew rate = Code /8s
Copyright 2018 Richtek Technology Corporation. All rights reserved.
©
is a registered trademark of Richtek Technology Corporation.
DS6203F-00 December 2018
www.richtek.com
13
RT6203F
The output stage of a synchronous buck converter is
composed of an inductor and capacitor, which stores and
delivers energy to the load, and forms a second-order low-
pass filter to smooth out the switch node voltage to
maintain a regulated output voltage.
in input voltage. The waveform of CIN ripple voltage and
ripple current are shown in Figure 1. The peak-to-peak
voltage ripple on input capacitor can be estimated as
equation below :
1D
IN SW
V
= DI
+ I
ESR
CIN
OUT
OUT
C
f
where
D =
Inductor Selection
V
OUT
The inductor selection trade-offs among size, cost,
efficiency, and transient response requirements.Generally,
three key inductor parameters are specified for operation
with the device: inductance value (L), inductor saturation
current (ISAT), andDC resistance (DCR).
V
IN
For ceramic capacitors, the equivalent series resistance
(ESR) is very low, the ripple which is caused by ESR can
be ignored, and the minimum input capacitance can be
estimated as equation below :
A good compromise between size and loss is to choose
the peak-to-peak ripple current equals to 10% to 50% of
the IC rated current. The switching frequency, input
voltage, output voltage, and selected inductor ripple current
determines the inductor value as follows :
D 1D
C
IN_MIN
= I
OUT_MAX
V
f
CIN_MAX SW
Where VCIN_MAX 200mV
V
(V V
)
OUT
IN
OUT
L =
V
CIN
V f
I
IN SW
L
C
Ripple Voltage
IN
Once an inductor value is chosen, the ripple current (ΔIL)
is calculated to determine the required peak inductor
current.
V
= I
x ESR
OUT
ESR
(1-D) x I
OUT
V
(V V
)
I
OUT
IN
OUT
L
C
IN
Ripple Current
I =
L
and I
= I
+
L(PEAK)
OUT_MAX
V f
IN SW
L
2
D x I
OUT
IL(PEAK) should not exceed the minimum value of IC's upper
current limit level. Besides, the current flowing through
the inductor is the inductor ripple current plus the output
current. During power up, faults or transient load
conditions, the inductor current can increase above the
calculated peak inductor current level calculated above.
In transient conditions, the inductor current can increase
up to the switch current limit of the device. For this reason,
the most conservative approach is to specify an inductor
with a saturation current rating equal to or greater than
the switch current limit rather than the peak inductor
current.
D x t
SW (1-D) x tSW
Figure 1. CIN Ripple Voltage and Ripple Current
In addition, the input capacitor needs to have a very low
ESR and must be rated to handle the worst-case RMS
input current of :
V
V
V
IN
V
OUT
OUT
I
I
1
RMS
OUT_MAX
IN
It is commonly to use the worse IRMS ≅ IOUT/2 at VIN
=
2VOUT for design. Note that ripple current ratings from
capacitor manufacturers are often based on only 2000
hours of life which makes it advisable to further de-rate
the capacitor, or choose a capacitor rated at a higher
temperature than required.
For more conservative, the rating for inductor saturation
current must be equal to or greater than switch current
limit of the device rather than the inductor peak current.
Several capacitors may also be paralleled to meet size,
height and thermal requirements in the design. For low
input voltage applications, sufficient bulk input capacitance
is needed to minimize transient effects during output load
changes.
Input Capacitor Selection
Input capacitance, CIN, is needed to filter the pulsating
current at the drain of the high-side power MOSFET. CIN
should be sized to do this without causing a large variation
Copyright 2018 Richtek Technology Corporation. All rights reserved.
©
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
14
DS6203F-00 December 2018
RT6203F
Ceramic capacitors are ideal for switching regulator
applications due to its small, robust and very low ESR.
However, care must be taken when these capacitors are
used at the input. A ceramic input capacitor combined
with trace or cable inductance forms a high quality (under
damped) tank circuit. If the RT6203F circuit is plugged
into a live supply, the input voltage can ring to twice its
nominal value, possibly exceeding the device's rating. This
situation is easily avoided by placing the low ESR ceramic
input capacitor in parallel with a bulk capacitor with higher
ESR to damp the voltage ringing.
If ceramic capacitors are used as the output capacitors,
both the components need to be considered due to the
extremely low ESR and relatively small capacitance.
Output Transient Undershoot and Overshoot
In addition to voltage ripple at the switching frequency,
the output capacitor and its ESR also affect the voltage
sag (undershoot) and soar (overshoot) when the load steps
up and down abruptly. TheACOTTM transient response is
very quick and output transients are usually small. The
following section shows how to calculate the worst-case
voltage swings in response to very fast load steps.
The input capacitor should be placed as close as possible
to the VIN pins, with a low inductance connection to the
GND of the IC. In addition to a larger bulk capacitor, a
small ceramic capacitors of 0.1μF should be placed close
to the VINandGNDpin. This capacitor should be 0402 or
0603 in size.
The output voltage transient undershoot and overshoot each
have two components : the voltage steps caused by the
output capacitor's ESR, and the voltage sag and soar due
to the finite output capacitance and the inductor current
slew rate. Use the following formulas to check if the ESR
is low enough (typically not a problem with ceramic
capacitors) and the output capacitance is large enough to
prevent excessive sag and soar on very fast load step
edges, with the chosen inductor value.
Output Capacitor Selection
The RT6203F are optimized for ceramic output capacitors
and best performance will be obtained using them. The
total output capacitance value is usually determined by
the desired output voltage ripple level and transient response
requirements for sag (undershoot on load apply) and soar
(overshoot on load release).
The amplitude of the ESR step up or down is a function of
the load step and the ESR of the output capacitor :
VESR _STEP = ΔIOUT x RESR
The amplitude of the capacitive sag is a function of the
load step, the output capacitor value, the inductor value,
the input-to-output voltage differential, and the maximum
duty cycle. The maximum duty cycle during a fast transient
is a function of the on-time and the minimum off-time since
the ACOTTM control scheme will ramp the current using
on-times spaced apart with minimum off-times, which is
as fast as allowed. Calculate the approximate on-time
(neglecting parasites) and maximum duty cycle for a given
input and output voltage as :
Output Ripple
The output voltage ripple at the switching frequency is a
function of the inductor current ripple going through the
output capacitor's impedance. To derive the output voltage
ripple, the output capacitor with capacitance, COUT, and
its equivalent series resistance, RESR, must be taken into
consideration. The output peak-to-peak ripple voltage
VRIPPLE, caused by the inductor current ripple ΔIL, is
characterized by two components, which are ESR ripple
VRIPPLE(ESR) and capacitive ripple VRIPPLE(C), can be
expressed as below :
VOUT
IN fSW
tON
tON
=
and DMAX =
V
tON tOFF_MIN
The actual on-time will be slightly longer as the IC
compensates for voltage drops in the circuit, but we can
neglect both of these since the on-time increase
compensates for the voltage losses. Calculate the output
VRIPPLE = VRIPPLE(ESR) VRIPPLE(C)
VRIPPLE(ESR) = IL RESR
IL
VRIPPLE(C)
=
8COUT fSW
voltage sag as :
2
L(I
)
OUT
V
SAG
=
2C
V
D
V
MAX OUT
OUT
IN(MIN)
Copyright 2018 Richtek Technology Corporation. All rights reserved.
©
is a registered trademark of Richtek Technology Corporation.
DS6203F-00 December 2018
www.richtek.com
15
RT6203F
The amplitude of the capacitive soar is a function of the
load step, the output capacitor value, the inductor value
R
EN1
V
IN
EN
R
EN2
RT6203F
GND
and the output voltage :
2
L(I
)
OUT
V
SOAR
=
2C
V
OUT
OUT
Figure 4. ResistorDivider for Lockout Threshold Setting
Due to some modern digital loads can exhibit nearly
instantaneous load changes, the amplitude of the ESR
step up or down should be taken into consideration.
External Bootstrap Diode
Connect a 0.1μF low ESR ceramic capacitor between the
BOOT and SW pins. This capacitor provides the gate driver
voltage for the high-side MOSFET. It is recommended to
add an external bootstrap diode between an external 5V
and BOOT pin for efficiency improvement when input
voltage is lower than 5.5V. The bootstrap diode can be a
low cost one such as IN4148 or BAT54. The external 5V
can be a 5V fixed input from system or a 5V output of the
RT6203FNote that the external boot voltage must be lower
than 5.5V.
Enable Operation (EN)
EN is a high voltage input pin. For automatic start-up, the
EN pin can be connected to VIN directly. The inherent
hysteresis makes EN useful as a simple timing delay. To
add an additional time delay, the ENpin can be connected
to GND through a capacitor CEN, as shown in Figure 2.
The additional time delay for switching operation to start
can be calculated with the EN's internal logic threshold.
(typically 2V).
An external MOSFET can be added to implement an logic-
controlled EN pin, as shown in Figure 3. The MOSFET
Q1 can provide the logic control on the EN pin, pulling it
down. To prevent enabling circuit when VIN is smaller than
the VOUT target value or some other desired voltage level,
a resistive divider can be placed to control the ENvoltage
as the additional input under voltage lockout function, as
shown in Figure 4.
External BOOT Capacitor Series Resistor
The internal power MOSFET gate driver is not only
optimized to turn the switch on fast enough to minimize
switching loss, but also slow enough to reduce EMI. Since
the switch rapidly turn-on will induce high di/dt noise which
let EMI issue much worse. During switch turn-off, SW is
discharged relatively slowly by the inductor current during
the dead time between high-side and low-side switch on-
times. In some cases it is desirable to reduce EMI further,
at the expense of some additional power dissipation. The
switch turn-on can be slowed by placing a small (<47Ω)
resistance between BOOT and the external bootstrap
capacitor. This will slow the high-side switch turn-on speed
and VSW's rise. The recommended external diode
connection is shown in Figure 5, using external diode to
charge the BOOT capacitor, and place a resistor between
BOOT and the capacitor/diode connection to reduce turn-
on speed for any EMI issue consideration.
R
EN
V
EN
RT6203F
IN
C
EN
GND
Figure 2. Enable Timing Control
R
EN
V
EN
RT6203F
IN
Q1
Enable
GND
Figure 3. Logic Control for the EN Pin
Copyright 2018 Richtek Technology Corporation. All rights reserved.
©
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
16
DS6203F-00 December 2018
RT6203F
5V
surrounding PCB layout and can be improved by providing
a heat sink of surrounding copper ground. The addition of
backside copper with thermal vias, stiffeners, and other
enhancements can also help reduce thermal resistance.
BOOT
R
As an example, consider the case when the RT6203F is
RT6203F
SW
0.1µF
used in applications where VIN = 12V, IOUT = 6A, fSW
=
700kHz, VOUT = 0.95V. The efficiency at 0.95V, 6A is
73.1% by using WE -744770015 (1.5μH, 5mΩ DCR) as
the inductor and measured at room temperature. The core
loss can be obtained from its website of 35.1mW in this
case. In this case, the power dissipation of the RT6203F
Figure 5. External BootstrapDiode and BOOT Capacitor
Series Resistor
Thermal Considerations
In many applications, the RT6203F does not generate
much heat due to its high efficiency and low thermal
resistance of its SOP-8 package. However, in applications
in which the RT6203F is running at a high ambient
temperature and high input voltage, the generated heat
may exceed the maximum junction temperature of the
part.
is
1 η
η
PD, RT
=
POUT I2 DCR + PCORE = 1.88W
O
Considering the system-level θJA(EFFECTIVE) is 34.8°C/W
(other heat sources are also considered), the junction
temperature of the regulator operating in a 25°C ambient
temperature is approximately :
The RT6203F includes a programmable over-temperature
protection (OTP) circuitry to prevent overheating due to
excessive power dissipation. If the junction temperature
reaches approximately 150°C(default), the RT6203F stop
switching the power MOSFETs until the temperature drops
about 20°C cooler.
TJ = 1.88W 34.8C/W + 25C = 90.5C
Figure 6 shows the RT6203F RDS(ON) versus different
junction temperature. If the application calls for a higher
ambient temperature, we might recalculate the device
power dissipation and the junction temperature based on
a higher RDS(ON) since it increases with temperature.
Note that the over temperature protection is intended to
protect the device during momentary overload conditions.
The protection is activated outside of the absolute
maximum range of operation as a secondary fail-safe and
therefore should not be relied upon operationally.
Continuous operation above the specified absolute
maximum operating junction temperature may impair
device reliability or permanently damage the device.
Using 50°C ambient temperature as an example. Due to
the variation of junction temperature is dominated by the
ambient temperature, the TJ' at 50°C ambient temperature
can be pre-estimated as
T ' = 90.5C + 50C 25C = 115.5C
J
According to Figure 6, the increasing RDS(ON) can be found
as
RDS ON _H = 61.8m (at 115.5C) 56.7m 90.5C = 5.1m
The maximum power dissipation can be calculated by
the following formula :
RDS ON _L = 28.1m (at 115.5C) 25.7m 90.5C = 2.4m
The external power dissipation caused by the increasing
RDS(ON) at higher temperature can be calculated as
P
= T
T / θ
A
D MAX
J MAX
JA EFFECTIVE
where TJ(MAX) is the maximum allowed junction temperature
of the die. For recommended operating condition
specifications, the maximum junction temperature is
125°C. TA is the ambient operating temperature,
θJA(EFFECTIVE) is the system-level junction to ambient
thermal resistance. It can be estimated from thermal
modeling or measurements in the system.
0.95
12
0.95
12
PD,RDS ON = 6A 2
5.1m + 6A 2 1
2.4m = 0.094W
As a result, the new power dissipation due to the variation
of RDS(ON) is 1.976W. Therefore, the estimated new
junction temperature is
TJ' = 1.976W 34.8C/W + 50C = 118.8C
The device thermal resistance depends strongly on the
Copyright 2018 Richtek Technology Corporation. All rights reserved.
©
is a registered trademark of Richtek Technology Corporation.
DS6203F-00 December 2018
www.richtek.com
17
RT6203F
If the application calls for a higher ambient temperature
and may exceed the recommended maximum junction
temperature of 125°C, care should be taken to reduce the
temperature rise of the part by using a heat sink or air
flow.
Layout Considerations
Follow the PCB layout guidelines for optimal performance
of the device.
Keep the high-current paths short, especially at the
ground terminals. This practice is essential for stable,
jitter-free operation. The high current path comprising
of input capacitor, high-side FET, inductor, and the output
capacitor should be as short as possible. This practice
is essential for high efficiency.
Resistance vs. Temperature
70
60
RDS(ON)_H
50
Place the input MLCC capacitors as close to the VIN
andGNDpins as possible. The major MLCC capacitors
should be placed on the same layer as the RT6203F.
40
30
RDS(ON)_L
20
10
0
SW node is with high frequency voltage swing and
should be kept at small area. Keep analog components
away from the SW node to prevent stray capacitive noise
pickup.
-50
-25
0
25
50
75
100
125
Connect feedback network behind the output capacitors.
Temperature (°C)
Figure 6. RT6203F RDS(ON) vs. Temperature
Place the feedback components next to the FB pin.
For better thermal performance, to design a wide and
thick plane for GND pin or to add a lot of vias to GND
plane.
An example of PCB layout guide is shown from Figure 7.
Copyright 2018 Richtek Technology Corporation. All rights reserved.
©
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
18
DS6203F-00 December 2018
RT6203F
Four-layer or six-layer PCB with maximum ground plane
is strongly recommended for good thermal performance.
The feedback trace is on bottom layer and
shielded by GND plane of inner layer.
COUT5
COUT4
COUT3
COUT2
Input capacitors must be placed as
close to IC VIN-GND as possible
C
OUT1
C
IN3
C
IN2
Keep analog components away from the BOOT
nodes.
C
IN1
EN
L
8
7
6
5
2
3
4
C
VCC
GND
C
BOOT
9
Add 12 thermal vias with 0.25mm diameter on
exposed pad for thermal dissipation and current
carrying capacity. Suggest inner layers are GND
plane.
SW should be connected to inductor by wide and short trace.
Keep sensitive components away from this trace .
SDA
SCL
Keep digital signal away from the noise traces and shielded by GND
plane.
Extend the GND plane for better thermal
dissipation.
Figure 7. PCB Layout Guide
Copyright 2018 Richtek Technology Corporation. All rights reserved.
is a registered trademark of Richtek Technology Corporation.
©
DS6203F-00 December 2018
www.richtek.com
19
RT6203F
Outline Dimension
H
A
Y
M
EXPOSED THERMAL PAD
(Bottom of Package)
J
B
X
F
C
I
D
Dimensions In Millimeters Dimensions In Inches
Symbol
Min
Max
Min
Max
A
B
C
D
F
H
I
4.801
3.810
1.346
0.330
1.194
0.170
0.000
5.791
0.406
2.000
2.000
2.100
3.000
5.004
4.000
1.753
0.510
1.346
0.254
0.152
6.200
1.270
2.300
2.300
2.500
3.500
0.189
0.150
0.053
0.013
0.047
0.007
0.000
0.228
0.016
0.079
0.079
0.083
0.118
0.197
0.157
0.069
0.020
0.053
0.010
0.006
0.244
0.050
0.091
0.091
0.098
0.138
J
M
X
Y
X
Y
Option 1
Option 2
8-Lead SOP (Exposed Pad) Plastic Package
Copyright 2018 Richtek Technology Corporation. All rights reserved.
©
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
20
DS6203F-00 December 2018
RT6203F
Footprint Information
Footprint Dimension (mm)
Package
Number of Pin
Tolerance
M
P
A
B
C
D
Sx
2.30
3.40
Sy
2.30
2.40
Option1
Option2
PSOP-8
8
1.27
6.80
4.20
1.30
0.70
4.51
±0.10
Richtek Technology Corporation
14F, No. 8, Tai Yuen 1st Street, Chupei City
Hsinchu, Taiwan, R.O.C.
Tel: (8863)5526789
Richtek products are sold by description only. Customers should obtain the latest relevant information and data sheets before placing orders and should verify
that such information is current and complete. Richtek cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Richtek
product. Information furnished by Richtek is believed to be accurate and reliable. However, no responsibility is assumed by Richtek or its subsidiaries for its use;
nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent
or patent rights of Richtek or its subsidiaries.
DS6203F-00 December 2018
www.richtek.com
21
相关型号：
©2020 ICPDF网 联系我们和版权申明