RT6575B [RICHTEK]

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RT6575B
型号: RT6575B
厂家: RICHTEK TECHNOLOGY CORPORATION    RICHTEK TECHNOLOGY CORPORATION
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®
RT6575A/B  
Dual-Channel Synchronous DC/DC Step-Down Controller  
with 5V/3.3V LDOs  
General Description  
Features  
Support Connected Standby Mode for Ultrabook  
CCRCOT Control with 100ns Load Step Response  
PWM Maximum Duty Ratio > 98%  
5V to 25V Input Voltage Range  
Dual Adjustable Output :  
The RT6575A/B is a dual-channel step-down controller  
generating supply voltages for battery-powered systems.  
It includes two Pulse-Width Modulation (PWM) controllers  
adjustable from 2V to 5.5V, and two fixed 5V/3.3V linear  
regulators. Each linear regulator provides up to 100mA  
output current and 3.3V linear regulator provides 1%  
accuracy under 35mA. The RT6575A/B has an oscillator  
output to drive the external charge pump application. Other  
features include on-board power-up sequencing, a power-  
good output, internal soft-start, and soft-discharge output  
that prevents negative voltage during shutdown.  
CH1 : 2V to 5.5V  
CH2 : 2V to 4V  
5V/3.3V LDOs with 100mA Output Current  
1% Accuracy on 3.3V LDO Output  
Oscillator Driving Output for Charge Pump  
Application  
Internal Frequency Setting  
A constant current ripple PWM control scheme operates  
without sense resistors and provides 100ns response to  
load transient. For maximizing power efficiency, the  
RT6575A/B automatically switches to the diode-emulation  
mode in light load applications. The RT6575A/B is available  
in the WQFN-20L 3x3 package.  
300kHz/355kHz (CH1/CH2)  
Internal Soft-Start and Soft-Discharge  
4700ppm/°C RDS(ON) Current Sensing  
Independent Switcher Enable Control  
Built-in OVP/UVP/OCP/OTP  
Non-Latch UVLO  
Power Good Indicator  
RoHS Compliant and Halogen Free  
Simplified Application Circuit  
V
IN  
UGATE2  
VIN  
RT6575A/B  
BOOT2  
UGATE1  
BOOT1  
PHASE2  
LGATE2  
V
OUT2  
V
OUT1  
PHASE1  
LGATE1  
FB2  
CS1  
CS2  
BYP1  
FB1  
LDO5  
5V  
Channel 1 Enable  
Channel 2 Enable  
EN1  
PGOOD  
LDO3  
ator  
PGOOD Indic  
EN2  
3.3V  
VCLK  
GND  
Copyright 2016 Richtek Technology Corporation. All rights reserved.  
©
is a registered trademark of Richtek Technology Corporation.  
DS6575A/B-03 February 2016  
www.richtek.com  
1
RT6575A/B  
Applications  
Notebook and Sub-Notebook Computers  
Marking Information  
RT6575AGQW  
3G= : Product Code  
System Power Supplies  
YMDNN : Date Code  
3G=YM  
2-Cell to 4-Cell Li+ Battery-PoweredDevices  
DNN  
Ordering Information  
RT6575A/B  
RT6575BGQW  
3F= : Product Code  
Pin 1 Orientation***  
YMDNN : Date Code  
3F=YM  
DNN  
(2) : Quadrant 2, Follow EIA-481-D  
Package Type  
QW : WQFN-20L 3x3 (W-Type)  
Lead Plating System  
G : Green (Halogen Free and Pb Free)  
Pin Configurations  
Pin Function With  
A : LDO3 Always On  
B : LDO3/LDO5 Always On  
(TOP VIEW)  
Note :  
***Empty means Pin1 orientation is Quadrant 1  
Richtek products are :  
20 19 18 17 16  
1
2
3
4
5
15  
14  
13  
12  
11  
CS1  
FB1  
LDO3  
FB2  
LGATE1  
BYP1  
LDO5  
VIN  
LGATE2  
RoHS compliant and compatible with the current require-  
ments of IPC/JEDEC J-STD-020.  
GND  
21  
CS2  
Suitable for use in SnPb or Pb-free soldering processes.  
6
7
8
9 10  
WQFN-20L 3x3  
Copyright 2016 Richtek Technology Corporation. All rights reserved.  
©
is a registered trademark of Richtek Technology Corporation.  
www.richtek.com  
2
DS6575A/B-03 February 2016  
RT6575A/B  
Functional Pin Description  
Pin No.  
Pin Name  
Pin Function  
Current Limit Setting. Connect a resistor to GND to set the threshold for Channel 1  
synchronous RDS(ON) sense. The GND PHASE1 current limit threshold is 1/8th  
the voltage seen at CS1 over a 0.2V to 2V range. There is an internal 10A  
current source from LDO5 to CS1.  
1
CS1  
Feedback Voltage Input for Channel 1. Connect FB1 to a resistive voltage divider  
from VOUT1 to GND to adjust output from 2V to 5.5V.  
2
3
4
FB1  
3.3V Linear Regulator Output. It is always on when VIN is higher than VINPOR  
threshold.  
LDO3  
FB2  
Feedback Voltage Input for Channel 2. Connect FB2 to a resistive voltage divider  
from VOUT2 to GND to adjust output from 2V to 4V.  
Current Limit Setting. Connect a resistor to GND to set the threshold for Channel 2  
synchronous RDS(ON) sense. The GND PHASE2 current limit threshold is 1/8th  
the voltage seen at CS2 over a 0.2V to 2V range. There is an internal 10A  
current source from LDO5 to CS2.  
5
CS2  
6
7
EN2  
Enable Control Input for Channel 2.  
PGOOD  
Power Good Indicator Output for Channel 1 and Channel 2. (Logical AND)  
Switch Node of Channel 2 MOSFETs. PHASE2 is the internal lower supply rail for  
the UGATE2 high-side gate driver. PHASE2 is also the current-sense input for the  
Channel 2.  
8
PHASE2  
Bootstrap Supply for Channel 2 High-Side Gate Driver. Connect to an external  
capacitor according to the typical application circuits.  
9
BOOT2  
High-Side Gate Driver Output for Channel 2. UGATE2 swings between PHASE2  
and BOOT2.  
10  
UGATE2  
Low-Side Gate Driver Output for Channel 2. LGATE2 swings between GND and  
LDO5.  
11  
12  
13  
14  
15  
LGATE2  
VIN  
Power Input for 5V and 3.3V LDO Regulators and Buck Controllers.  
5V Linear Regulator Output. LDO5 is also the supply voltage for the low-side  
MOSFET and analog supply voltage for the device.  
LDO5  
BYP1  
Switch-over Source Voltage Input for LDO5.  
Low-Side Gate Driver Output for Channel 1. LGATE1 swings between GND and  
LDO5.  
LGATE1  
High-Side Gate Driver Output for Channel 1. UGATE1 swings between PHASE1  
and BOOT1.  
16  
17  
UGATE1  
BOOT1  
Bootstrap Supply for Channel 1 High-Side Gate Driver. Connect to an external  
capacitor according to the typical application circuits.  
Switch Node of Channel 1 MOSFETs. PHASE1 is the internal lower supply rail for  
the UGATE1 high-side gate driver. PHASE1 is also the current sense input for the  
Channel 1.  
18  
PHASE1  
19  
20  
VCLK  
EN1  
Oscillator Output for Charge Pump.  
Enable Control Input for Channel 1.  
21  
Ground. The exposed pad must be soldered to a large PCB and connected to  
GND for maximum power dissipation.  
GND  
(Exposed Pad)  
Copyright 2016 Richtek Technology Corporation. All rights reserved.  
©
is a registered trademark of Richtek Technology Corporation.  
DS6575A/B-03 February 2016  
www.richtek.com  
3
RT6575A/B  
Functional Block Diagram  
BOOT1  
BOOT2  
UGATE1  
UGATE2  
PHASE2  
PHASE1  
LDO5  
LDO5  
Channel 1  
Buck  
Channel 2  
Buck  
Controller  
Controller  
LGATE1  
LGATE2  
FB1  
FB2  
CS2  
CS1  
BYP1  
PGOOD  
VCLK  
OSC  
GND  
SW5 Threshold  
BYP1  
Power-On  
Sequence  
Clear Fault Latch  
EN1  
EN2  
REF  
LDO3  
BYP1  
LDO3  
LDO5  
VIN  
LDO5  
Operation  
PGOOD  
The RT6575A/B includes two constant on-time  
synchronous step-down controllers and two linear  
regulators.  
The power good output is an open-drain architecture. When  
the two channels soft-start are both finished, the PGOOD  
open-drain output will be high impedance.  
Buck Controller  
Current Limit  
In normal operation, the high-side N-MOSFET is turned  
on when the output is lower than VREF, and is turned off  
after the internal one-shot timer expires. While the high-  
sideN-MOSFET is turned off, the low-sideN-MOSFET is  
turned on to conduct the inductor current until next cycle  
begins.  
The current limit circuit employs a unique valleycurrent  
sensing algorithm. If the magnitude of the current sense  
signal at PHASE is above the current limit threshold, the  
PWM is not allowed to initiate a new cycle. Thus, the  
current to the load exceeds the average output inductor  
current, the output voltage falls and eventually crosses  
the under-voltage protection threshold, inducing IC  
shutdown.  
Soft-Start  
For internal soft-start function, an internal current source  
charges an internal capacitor to build the soft-start ramp  
voltage. The output voltage will track the internal ramp  
voltage during soft-start interval.  
Copyright 2016 Richtek Technology Corporation. All rights reserved.  
©
is a registered trademark of Richtek Technology Corporation.  
www.richtek.com  
4
DS6575A/B-03 February 2016  
RT6575A/B  
Over-Voltage Protection (OVP) & Under-Voltage  
Protection (UVP)  
The two channel output voltages are continuously  
monitored for over-voltage and under-voltage conditions.  
When the output voltage exceeds over-voltage threshold  
(113% of VOUT), UGATE goes low and LGATE is forced  
high. When it is less than 52% of reference voltage, under-  
voltage protection is triggered and then both UGATE and  
LGATE gate drivers are forced low. The controller is latched  
until ENx is reset or LDO5 is re-supplied.  
LDO5 and LDO3  
When the VIN voltage exceeds the POR rising threshold,  
LDO3 will default turn-on. The LDO5 can be power on by  
ENx. The linear regulator LDO5 and LDO3 provide 5V and  
3.3V regulated output.  
Switching Over  
The BYP1 is connected to the Channel 1 output. After the  
Channel 1 output voltage exceeds the set threshold  
(4.66V), the output will be bypassed to the LDO5 output  
to maximize the efficiency.  
Copyright 2016 Richtek Technology Corporation. All rights reserved.  
©
is a registered trademark of Richtek Technology Corporation.  
DS6575A/B-03 February 2016  
www.richtek.com  
5
RT6575A/B  
Absolute Maximum Ratings (Note 1)  
VINtoGND----------------------------------------------------------------------------------------------------------------- 0.3V to 30V  
BOOTx toGND  
DC---------------------------------------------------------------------------------------------------------------------------- 0.3V to 36V  
<100ns ---------------------------------------------------------------------------------------------------------------------- 5V to 42V  
BOOTx to PHASEx  
DC---------------------------------------------------------------------------------------------------------------------------- 0.3V to 6V  
<100ns ---------------------------------------------------------------------------------------------------------------------- 5V to 7.5V  
PHASEx to GND  
DC---------------------------------------------------------------------------------------------------------------------------- 5V to 30V  
<100ns ---------------------------------------------------------------------------------------------------------------------- 10V to 42V  
UGATEx toGND  
DC---------------------------------------------------------------------------------------------------------------------------- 5V to 36V  
<100ns ---------------------------------------------------------------------------------------------------------------------- 10V to 42V  
UGATEx to PHASEx  
DC---------------------------------------------------------------------------------------------------------------------------- 0.3V to 6V  
<100ns ---------------------------------------------------------------------------------------------------------------------- 5V to 7.5V  
LGATEx toGND  
DC---------------------------------------------------------------------------------------------------------------------------- 0.3V to 6V  
<100ns ---------------------------------------------------------------------------------------------------------------------- 5V to 7.5V  
Other Pins------------------------------------------------------------------------------------------------------------------ 0.3V to 6.5V  
Power Dissipation, PD @ TA = 25°C  
WQFN-20L 3x3 ----------------------------------------------------------------------------------------------------------- 3.33W  
Package Thermal Resistance (Note 2)  
WQFN-20L 3x3, θJA ------------------------------------------------------------------------------------------------------ 30°C/W  
WQFN-20L 3x3, θJC ----------------------------------------------------------------------------------------------------- 7.5°C/W  
Junction Temperature ---------------------------------------------------------------------------------------------------- 150°C  
Lead Temperature (Soldering, 10 sec.)------------------------------------------------------------------------------ 260°C  
Storage Temperature Range ------------------------------------------------------------------------------------------- 65°C to 150°C  
ESD Susceptibility (Note 3)  
HBM (Human Body Model)--------------------------------------------------------------------------------------------- 2kV  
Recommended Operating Conditions (Note 4)  
Supply Voltage, VIN ----------------------------------------------------------------------------------------------------- 5V to 25V  
Junction Temperature Range------------------------------------------------------------------------------------------- 40°C to 125°C  
Ambient Temperature Range------------------------------------------------------------------------------------------- 40°C to 85°C  
Copyright 2016 Richtek Technology Corporation. All rights reserved.  
©
is a registered trademark of Richtek Technology Corporation.  
www.richtek.com  
6
DS6575A/B-03 February 2016  
RT6575A/B  
Electrical Characteristics  
(VIN = 12V, VEN1 = VEN2 = 3.3V, VCS1 = VCS2 = 2V, No Load, TA = 25°C, unless otherwise specified)  
Parameter  
Input Supply  
Symbol  
Test Conditions  
Min  
Typ  
Max  
Unit  
Rising Threshold  
--  
4.6  
3.7  
4.9  
--  
VIN Power-On Reset  
VINPOR  
V
Falling Threshold  
3.2  
RT6575A Both Buck Controllers  
Off, VEN1 = VEN2 = GND  
--  
--  
--  
--  
60  
80  
80  
100  
25  
VIN Standby Supply Current IVIN_SBY  
A  
RT6575B Both Buck Controllers  
Off, VEN1 = VEN2 = GND  
Both Buck Controllers On,  
VIN Quiescent Current  
BYP1 Supply Current  
IVIN_nosw  
15  
A  
A  
V
FBx = 2.05V, VBYP1 = 5.05V  
Both Buck Controllers On,  
FBx = 2.05V, VBYP1 = 5.05V  
IBYP1_nosw  
420  
500  
V
Buck Controllers Output and FB Voltage  
FBx Valley Trip Voltage  
VFBx  
CCM Operation  
BYP1 = 0.5V  
1.98  
10  
2
2.02  
--  
V
IDCHG_BYP  
1
BYP1 Discharge Current  
V
45  
mA  
PHASEx Discharge Current  
IDCHG_LX  
VPHASEx = 0.5V  
5
8
--  
mA  
Switching Frequency  
V
IN = 20V, VOUT1 = 5V  
240  
280  
--  
300  
355  
200  
360  
430  
275  
Switching Frequency  
fSWx  
kHz  
ns  
VIN = 20V, VOUT2 = 3.33V  
VFBx = 1.9V  
Minimum Off-Time  
tOFF(MIN)  
Soft-Start  
Soft-Start Time  
tSSx  
VOUT Ramp-up Time  
--  
0.9  
--  
ms  
Current Sense  
CSx Source Current  
ICSx  
VCSx = 1V, VFBx = 1.9V  
9
--  
--  
10  
4700  
1
11  
--  
A  
ppm/C  
mV  
CSx Current Temperature  
Coefficient  
TCICSx  
VZC  
In Comparison with 25°C  
VFBx = 2.05V, GND PHASEx  
Zero-Current Threshold  
--  
Internal Regulator  
VIN = 12V, No Load  
4.9  
4.8  
5
5
5.1  
5.1  
VIN > 7V, ILDO5 < 100mA  
VIN > 5.5V, ILDO5 < 35mA  
VIN > 5V, ILDO5 < 20mA  
VIN = 12V, No Load  
LDO5 Output Voltage  
LDO3 Output Voltage  
VLDO5  
V
V
4.8  
5
5.1  
4.5  
4.75  
3.3  
3.3  
3.3  
3.3  
5.1  
3.267  
3.217  
3.267  
3.217  
3.333  
3.383  
3.333  
3.383  
VIN > 7V, ILDO3 < 100mA  
VIN > 5.5V, ILDO3 < 35mA  
VIN > 5V, ILDO3 < 20mA  
VLDO3  
Copyright 2016 Richtek Technology Corporation. All rights reserved.  
©
is a registered trademark of Richtek Technology Corporation.  
DS6575A/B-03 February 2016  
www.richtek.com  
7
RT6575A/B  
Parameter  
Symbol  
ILDO5  
Test Conditions  
Min  
100  
100  
--  
Typ  
175  
175  
4.66  
Max  
--  
Unit  
mA  
mA  
V
VLDO5 = 4.5V, VBYP1 = GND,  
VIN = 7.4V  
LDO5 Output Current  
LDO3 Output Current  
ILDO3  
VLDO3 = 3V, VIN = 7.4V  
--  
LDO5 Switch-over  
Threshold to BYP1  
VSWTH  
Rising Edge at BYP1 Regulation Point  
--  
LDO5 Switch-over  
Equivalent Resistance  
RSW  
LDO5 to BYP1, 10mA  
--  
1.5  
3
VCLK Output  
VCLK On-Resistance  
RVCLK  
fVCLK  
Pull-up and Pull-down Resistance  
--  
--  
10  
--  
--  
VCLK Switching  
Frequency  
260  
kHz  
UVLO  
Rising Edge  
Falling Edge  
Channel x Off  
--  
3.7  
--  
4.3  
3.9  
2.5  
4.6  
4.1  
--  
LDO5 UVLO Threshold  
VUVLO5  
VUVLO3  
V
V
LDO3 UVLO Threshold  
Power Good Indicator  
PGOOD Detect, VFBx Rising Edge  
Hysteresis  
84  
--  
88  
8
92  
--  
PGOOD Threshold  
VPGxTH  
%
PGOOD Leakage  
Current  
High state, VPGOOD = 5.5V  
ISINK = 4mA  
--  
--  
--  
--  
1
A  
PGOOD Output Low  
Voltage  
0.3  
V
Fault Detection  
FBx with Respect to Internal  
Reference  
OVP Trip Threshold  
VOVP  
109  
113  
117  
%
OVP Propagation Delay  
UVP Trip Threshold  
--  
1
--  
s  
VUVP  
UVP Detect, FBx Falling Edge  
47  
52  
57  
%
UVP Shutdown Blanking  
Time  
tSHDN_UVP From ENx Enable  
--  
1.3  
--  
ms  
Thermal Shutdown  
Thermal Shutdown  
TSD  
--  
--  
150  
10  
--  
--  
°C  
°C  
Thermal Shutdown  
Hysteresis  
TSD  
Logic Inputs  
ENx  
Threshold  
Voltage  
Logic-High VENx_H  
Logic-Low VENx_L  
SMPS On  
SMPS Off  
1.6  
--  
--  
--  
--  
V
0.4  
Internal Boost Switch  
Internal Boost Switch  
On-Resistance  
RBST  
LDO5 to BOOTx  
--  
80  
--  
Copyright 2016 Richtek Technology Corporation. All rights reserved.  
©
is a registered trademark of Richtek Technology Corporation.  
www.richtek.com  
8
DS6575A/B-03 February 2016  
RT6575A/B  
Parameter  
Symbol  
Test Conditions  
Min  
Typ  
Max Unit  
Power MOSFET Drivers  
High State, VBOOTx VUGATEx = 0.25V,  
VBOOTx VPHASEx = 5V  
--  
--  
--  
3
2
3
--  
--  
UGATEx On-Resistance  
RUGATEx  
Low State, VUGATEx VPAHSEx  
0.25V, VBOOTx VPHASEx = 5V  
=
High State, VLDO5 VLGATEx = 0.25V,  
VLDO5 = 5V  
--  
LGATEx On-Resistance  
Dead-Time  
RLGATEx  
Low State, VLGATEx GND = 0.25V  
LGATEx Rising  
--  
--  
--  
1
--  
20  
30  
--  
tD  
ns  
--  
UGATEx Rising  
Note 1. Stresses beyond those listed Absolute Maximum Ratingsmay cause permanent damage to the device. These are  
stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in  
the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions may  
affect device reliability.  
Note 2. θJA is measured at TA = 25°C on a high effective thermal conductivity four-layer test board per JEDEC 51-7. θJC is  
measured at the exposed pad of the package.  
Note 3. Devices are ESD sensitive. Handling precaution is recommended.  
Note 4. The device is not guaranteed to function outside its operating conditions.  
Copyright 2016 Richtek Technology Corporation. All rights reserved.  
©
is a registered trademark of Richtek Technology Corporation.  
DS6575A/B-03 February 2016  
www.richtek.com  
9
RT6575A/B  
Typical Application Circuit  
V
IN  
5V to 25V  
R8  
0
C1  
10µF  
RT6575A  
UGATE2  
C13  
C12  
R10 0  
R9 0  
Q2  
BSC0909  
NS  
10µF  
10µF  
10  
9
12  
VIN  
C10  
0.1µF  
BOOT2  
Q1  
BSC0909  
NS  
R4 0  
16  
17  
C11  
0.1µF  
L2  
2.2µH  
UGATE1  
BOOT1  
8
V
OUT2  
R3 0  
PHASE2  
LGATE2  
3.3V  
C17  
220µF  
Q4  
BSC0909  
NS  
11  
L1  
3.3µH  
C2  
0.1µF  
R11*  
C14*  
18  
15  
V
OUT1  
5V  
PHASE1  
LGATE1  
Q3  
BSC0909  
NS  
C3  
220µF  
R5*  
C4*  
R14  
13k  
C21*  
4
FB2  
14  
2
R15  
20k  
BYP1  
FB1  
C22  
R12  
15k  
13  
0.1µF  
C18*  
LDO5  
5V  
C9  
1µF  
D1  
C5  
0.1µF  
R13  
10k  
7
3
PGOOD  
LDO3  
C6  
PGOOD Indicator  
3.3V Always On  
19  
VCLK  
0.1µF  
D2  
D3  
C16  
1µF  
C7  
0.1µF  
R1  
C8  
0.1µF  
82.5k  
D4  
1
5
CS1  
CS2  
R2  
82.5k  
BAT254  
CPO  
20  
6
Channel 1 Enable  
Channel 2 Enable  
EN1  
EN2  
21 (Exposed Pad)  
GND  
On  
Off  
* : Optional  
V
IN  
5V to 25V  
R8  
0
C1  
10µF  
RT6575B  
C13  
10µF  
C12  
10µF  
R10 0  
10  
Q2  
BSC0909  
NS  
12  
UGATE2  
VIN  
C10  
0.1µF  
R9 0  
9
BOOT2  
Q1  
BSC0909  
NS  
R4 0  
16  
17  
C11  
0.1µF  
L2  
2.2µH  
UGATE1  
BOOT1  
8
V
3.3V  
R3 0  
OUT2  
PHASE2  
LGATE2  
C17  
220µF  
Q4  
BSC0909  
NS  
11  
L1  
C2  
0.1µF  
R11*  
C14*  
3.3µH  
18  
15  
V
OUT1  
5V  
PHASE1  
LGATE1  
Q3  
BSC0909  
NS  
C3  
220µF  
R5*  
C4*  
R14  
13k  
C21*  
4
FB2  
14  
2
R15  
20k  
BYP1  
FB1  
C22  
R12  
15k  
13  
0.1µF  
C18*  
LDO5  
5V Always On  
C9  
1µF  
D1  
C5  
0.1µF  
R13  
10k  
7
3
PGOOD  
LDO3  
C6  
PGOOD Indicator  
3.3V Always On  
19  
VCLK  
0.1µF  
D2  
D3  
C16  
1µF  
C7  
0.1µF  
R1  
C8  
0.1µF  
82.5k  
D4  
1
5
CS1  
CS2  
R2  
82.5k  
BAT254  
CPO  
20  
6
Channel 1 Enable  
Channel 2 Enable  
EN1  
EN2  
21 (Exposed Pad)  
GND  
On  
Off  
* : Optional  
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10  
DS6575A/B-03 February 2016  
RT6575A/B  
Typical Operating Characteristics  
Efficiency vs. Load Current  
Efficiency vs. Load Current  
100  
90  
80  
70  
60  
50  
40  
100  
VOUT1  
VOUT2  
90  
VIN = 7.4V  
VIN = 11.1V  
VIN = 14.8V  
VIN = 20V  
VIN = 7.4V  
VIN = 11.1V  
VIN = 14.8V  
80  
VIN = 20V  
70  
60  
EN1 = LDO3, EN2 = 0V, VCLK On  
50  
EN1 = EN2 = LDO3, VCLK On  
0.001  
0.01  
0.1  
1
10  
0.001  
0.01  
0.1  
1
10  
Load Current (A)  
Load Current (A)  
Switching Frequency vs. Load Current  
Switching Frequency vs. Load Current  
400  
350  
300  
250  
200  
150  
100  
50  
350  
300  
250  
200  
150  
100  
50  
VOUT1  
VOUT2  
EN1 = LDO3, EN2 = 0V  
EN1 = 0V, EN2 = LDO3  
VIN = 20V  
VIN = 12V  
VIN = 7.4V  
VIN = 20V  
VIN = 12V  
VIN = 7.4V  
0
0
0.001  
0.01  
0.1  
1
10  
0.001  
0.01  
0.1  
1
10  
Load Current (A)  
Load Current (A)  
Switching Frequency vs. Input Voltage  
Switching Frequency vs. Input Voltage  
400  
350  
300  
250  
200  
150  
100  
50  
350  
300  
250  
200  
150  
100  
50  
VOUT2  
VOUT1  
EN1 = 0V, EN2 = LDO3, ILOAD = 6A  
EN1 = LDO3, EN2 = 0V, ILOAD = 6A  
0
0
5
7
9
11 13 15 17 19 21 23 25  
Input Voltage (V)  
5
7
9
11 13 15 17 19 21 23 25  
Input Voltage (V)  
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11  
RT6575A/B  
Output Voltage vs. Load Current  
Output Voltage vs. Load Current  
4.98  
4.97  
4.96  
4.95  
4.94  
4.93  
4.92  
3.335  
3.330  
3.325  
3.320  
3.315  
3.310  
3.305  
3.300  
3.295  
VIN = 20V  
VIN = 14.8V  
VIN = 11.1V  
VIN = 7.4V  
VIN = 20V  
VIN = 14.8V  
VIN = 11.1V  
VIN = 7.4V  
EN1 = LDO3, EN2 = 0V  
0.0001 0.001 0.01  
EN1 = 0V, EN2 = LDO3  
0.1  
1
10  
0.0001  
0.001  
0.01  
0.1  
1
10  
Load Current (A)  
Load Current (A)  
LDO5 vs. Load Current  
LDO3 vs. Load Current  
3.312  
3.311  
3.310  
3.309  
3.308  
3.307  
3.306  
3.305  
3.304  
3.303  
3.302  
5.011  
5.010  
5.009  
5.008  
5.007  
5.006  
5.005  
5.004  
VIN = 12V, EN1 = 0V, EN2 = LDO3  
VIN = 12V, EN1 = LDO3, EN2 = 0V, BYP1 Off  
0
10 20 30 40 50 60 70 80 90 100  
Load Current (mA)  
0
10 20 30 40 50 60 70 80 90 100  
Load Current (mA)  
Quiescent Current vs. Input Voltage  
BYP1 Supply Current vs. Input Voltage  
30  
25  
20  
15  
10  
5
500  
490  
480  
470  
460  
450  
440  
430  
420  
410  
400  
EN1 = EN2 = LDO3, VCLK On, BYP On  
EN1 = EN2 = LDO3, VCLK On, BYP On  
0
5
7
9
11 13 15 17 19 21 23 25  
Input Voltage (V)  
5
7
9
11 13 15 17 19 21 23 25  
Input Voltage (V)  
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12  
DS6575A/B-03 February 2016  
RT6575A/B  
Power Off from EN  
Power On from EN  
EN  
(5V/Div)  
EN  
(5V/Div)  
VOUT2  
(3V/Div)  
VOUT2  
(3V/Div)  
VOUT1  
(4V/Div)  
VOUT1  
(4V/Div)  
LDO5  
(5V/Div)  
LDO5  
(5V/Div)  
VIN = 12V, EN1 = EN2 = LDO3, No Load  
VIN = 12V, EN1 = EN2 = LDO3, No Load  
Time (20ms/Div)  
Time (500μs/Div)  
VOUT2 Load Transient Response  
VOUT1 Load Transient Response  
VOUT2  
(100mV/Div)  
VOUT1  
(100mV/Div)  
UGATE2  
(50V/Div)  
UGATE1  
(50V/Div)  
LGATE2  
(6V/Div)  
LGATE1  
(6V/Div)  
IOUT2  
(4A/Div)  
IOUT1  
(4A/Div)  
VIN = 12V, EN1 = 0V,  
VIN = 12V, EN1 = LDO3,  
EN2 = LDO3, IOUT2 = 0A to 6A  
EN2 = 0V, IOUT1 = 0A to 6A  
Time (50μs/Div)  
Time (50μs/Div)  
OVP  
UVP  
VOUT1  
(5V/Div)  
VOUT1  
(2V/Div)  
UGATE1  
(20V/Div)  
IL1  
(4A/Div)  
UGATE1  
IL1  
PGOOD  
(4V/Div)  
LGATE1  
(5V/Div)  
LGATE1  
(10V/Div)  
VIN = 12V, EN1 = EN2 = LDO3, No Load  
VIN = 12V, EN1 = EN2 = LDO3  
Time (100μs/Div)  
Time (200μs/Div)  
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13  
RT6575A/B  
Application Information  
on-time is inversely proportional to the input voltage as  
measured by VIN and proportional to the output voltage.  
The inductor ripple current operating point remains  
relatively constant, resulting in easy design methodology  
and predictable output voltage ripple. The frequency of 3V  
output controller is set higher than the frequency of 5V  
output controller. This is done to prevent audio frequency  
beatingbetween the two sides, which switch  
asynchronously for each side.  
The RT6575A/B is a dual-channel, low quiescent, Mach  
ResponseTM DRVTM mode synchronous Buck controller  
targeted for Ultrabook system power supply solutions.  
Richtek's Mach ResponseTM technology provides fast  
response to load steps. The topology solves the poor load  
transient response timing problems of fixed frequency  
current mode PWMs, and avoids the problems caused  
by widely varying switching frequencies in CCR (constant  
current ripple) constant on-time and constant off-time  
PWM schemes. Aspecial adaptive on-time control trades  
off the performance and efficiency over wide input voltage  
range. The RT6575A/B includes 5V (LDO5) and 3.3V  
(LDO3) linear regulators. The LDO5 linear regulator steps  
down the battery voltage to supply both internal circuitry  
and gate drivers. The synchronous switch gate drivers are  
directly powered by LDO5. When VOUT1 rises above 4.66V,  
an automatic circuit disconnects the linear regulator and  
allows the device to be powered by VOUT1 via the BYP1  
pin.  
The RT6575A/B adaptively changes the operation  
frequency according to the input voltage. Higher input  
voltage usually comes from an external adapter, so the  
RT6575A/B operates with higher frequency to have better  
performance. Lower input voltage usually comes from a  
battery, so the RT6575A/B operates with lower switching  
frequency for lower switching losses. For a specific input  
voltage range, the switching cycle period is given by :  
For 5V VOUT,  
V
IN 2.710-6  
IN 3.79  
Period (sec.) =  
V
PWM Operation  
For 3.3V VOUT,  
Period (sec.) =  
The Mach ResponseTM DRVTM mode controller relies on  
the output filter capacitor's Effective Series Resistance  
(ESR) to act as a current sense resistor, so that the output  
ripple voltage provides the PWM ramp signal. Referring to  
the RT6575A/B's Function Block Diagram, the  
synchronous high-side MOSFET is turned on at the  
beginning of each cycle. After the internal one-shot timer  
expires, the MOSFET will be turned off. The pulse width  
of this one-shot is determined by the converter's input  
output voltages to keep the frequency fairly constant over  
the entire input voltage range. Another one-shot sets a  
minimum off-time (200ns typ.). The on-time one-shot will  
be triggered if the error comparator is high, the low-side  
switch current is below the current limit threshold, and  
the minimum off-time one-shot has timed out.  
V
IN 2.4510-6  
IN 2.59  
V
where the VIN is in volt.  
The on-time guaranteed in the Electrical Characteristics  
table is influenced by switching delays in the external  
high-side power MOSFET.  
Diode Emulation Mode  
In diode emulation mode, the RT6575A/B automatically  
reduces switching frequency at light load conditions to  
maintain high efficiency. This reduction of frequency is  
achieved smoothly. As the output current decreases from  
heavy load condition, the inductor current is also reduced,  
and eventually comes to the point that its current valley  
touches zero, which is the boundary between continuous  
conduction and discontinuous conduction modes. To  
emulate the behavior of diodes, the low-side MOSFET  
allows only partial negative current to flow when the  
inductor free wheeling current becomes negative. As the  
load current is further decreased, it takes longer and longer  
PWM Frequency and On-time Control  
For each specific input voltage range, the Mach  
ResponseTM control architecture runs with pseudo constant  
frequency by feed forwarding the input and output voltage  
into the on-time one-shot timer. The high-side switch  
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14  
DS6575A/B-03 February 2016  
RT6575A/B  
time to discharge the output capacitor to the level that  
requires the next ONcycle. The on-time is kept the  
same as that in the heavy load condition. In reverse, when  
the output current increases from light load to heavy load,  
the switching frequency increases to the preset value as  
the inductor current reaches the continuous conduction.  
The transition load point to the light load operation is shown  
in Figure 1. and can be calculated as follows :  
Current Limit Setting  
The RT6575A/B has cycle-by-cycle current limit control.  
The current limit circuit employs a unique valleycurrent  
sensing algorithm. If the magnitude of the current sense  
signal at PHASEx is above the current limit threshold,  
the PWM is not allowed to initiate a new cycle (Figure 2).  
The actual peak current is greater than the current limit  
threshold by an amount equal to the inductor ripple current.  
Therefore, the exact current limit characteristic and  
maximum load capability are a function of the sense  
resistance, inductor value, battery and output voltage.  
I
L
Slope = (V - V  
) / L  
IN  
OUT  
I
I
t
PEAK  
I
L
I
/ 2  
LOAD = PEAK  
I
I
PEAK  
LOAD  
0
t
ON  
I
t
LIMIT  
Figure 1. Boundary Condition of CCM/DEM  
(VIN VOUT  
)
Figure 2. ValleyCurrent Limit  
ILOAD(SKIP)  
tON  
2L  
The RT6575A/B uses the on resistance of the synchronous  
rectifier as the current sense element and supports  
temperature compensated MOSFET RDS(ON) sensing. The  
RILIM resistor between the CSx pin andGNDsets the current  
limit threshold. The resistor RILIM is connected to a current  
source from CSxwhich is 10μA (typ.) at room temperature.  
The current source has a 4700ppm/°C temperature slope  
to compensate the temperature dependency of the  
RDS(ON). When the voltage drop across the sense resistor  
or low-side MOSFET equals 1/8 the voltage across the  
RILIM resistor, positive current limit will be activated. The  
high-side MOSFET will not be turned on until the voltage  
drop across the MOSFET falls below 1/8 the voltage across  
the RILIM resistor.  
where tON is the on-time.  
The switching waveforms may appear noisy and  
asynchronous when light load causes diode emulation  
operation. This is normal and results in high efficiency.  
Trade offs in PFM noise vs. light load efficiency is made  
by varying the inductor value.Generally, low inductor values  
produce a broader efficiency vs. load curve, while higher  
values result in higher full load efficiency (assuming that  
the coil resistance remains fixed) and less output voltage  
ripple. Penalties for using higher inductor values include  
larger physical size and degraded load transient response  
(especially at low input voltage levels).  
Linear Regulators (LDOx)  
The RT6575A/B includes 5V (LDO5) and 3.3V (LDO3)  
linear regulators. The regulators can supply up to 100mA  
for external loads. Bypass LDOx with a 1μF to 4.7μF, and  
recommended value is 1μF ceramic capacitor. When VOUT1  
is higher than the switch over threshold (4.66V), an internal  
1.5Ω P-MOSFET switch connects BYP1 to the LDO5  
pin while simultaneously disconnects the internal linear  
regulator.  
Choose a current limit resistor according to the following  
equation :  
VLIMIT = (RLIMIT x 10μA) / 8 = ILIMIT x RDS(ON)  
RLIMIT = (ILIMIT x RDS(ON)) x 8 / 10μA  
Carefully observe the PC board layout guidelines to ensure  
that noise andDC errors do not corrupt the current sense  
signal at PHASEx and GND. Mount or place the IC close  
to the low-side MOSFET.  
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15  
RT6575A/B  
VCLK for Charge Pump  
supply. The instantaneous drive current is supplied by an  
input capacitor connected between LDO5 andGND.  
A260kHz VCLK signal can be used for the external charge  
pump circuit. The VCLK signal becomes available when  
EN1 enters ON state. VCLK driver circuit is driven by BYP1  
voltage.  
For high current applications, some combinations of high  
and low-side MOSFETs may cause excessive gate drain  
coupling, which leads to efficiency killing, EMI producing,  
and shoot through currents. This is often remedied by  
adding a resistor in series with BOOTx, which increases  
the turn-on time of the high-side MOSFET without  
degrading the turn-off time. See Figure 4.  
The external 14V charge pump is driven by VCLK. As  
shown in Figure 3, when VCLK is low, C1 will be charged  
by VOUT1 through D1. C1 voltage is equal to VOUT1 minus  
the diode drop. When VCLK becomes high, C1 transfers  
the charge to C2 through D2 and charges C2 voltage to  
VVCLK plus C1 voltage. As VCLK transitions low on the  
next cycle, C3 is charged to C2 voltage minus a diode  
drop throughD3. Finally, C3 charges C4 throughD4 when  
VCLK switches high. Thus, the total charge pump voltage,  
VCP, is :  
V
IN  
UGATEx  
BOOTx  
R
BOOT  
PHASEx  
Figure 4. Increasing the UGATEx Rise Time  
Soft-Start  
VCP = VOUT1 + 2 x VVCLK 4 x VD  
where VVCLK is the peak voltage of the VCLK driver which  
is equal to LDO5 and VD is the forward voltage dropped  
across the Schottky diode.  
The RT6575A/B provides an internal soft-start function to  
prevent large inrush current and output voltage overshoot  
when the converter starts up. The soft-start (SS)  
automatically begins once the chip is enabled.During soft-  
start, it clamps the ramping of internal reference voltage  
which is compared with FBx signal. The typical soft-start  
duration is 0.9ms. A unique PWM duty limit control that  
prevents output over-voltage during soft-start period is  
designed specifically for FBx floating.  
VCLK  
C1  
C3  
VOUT1  
Charge Pump  
D1  
D2  
D3  
C2  
D4  
C4  
Figure 3. Charge Pump Circuit Connected to VCLK  
MOSFET Gate Driver (UGATEx, LGATEx)  
UVLO Protection  
The high-side driver is designed to drive high current, low  
RDS(ON) N-MOSFET(s). When configured as a floating driver,  
5V bias voltage is delivered from the LDO5 supply. The  
average drive current is also calculated by the gate charge  
at VGS = 5V times switching frequency. The instantaneous  
drive current is supplied by the flying capacitor between  
the BOOTx and PHASEx pins. A dead-time to prevent  
shoot through is internally generated from high-side  
MOSFET off to low-side MOSFET on and low-side  
MOSFET off to high-side MOSFET on.  
The RT6575A/B has LDO5 under-voltage lock out  
protection (UVLO). When the LDO5 voltage is lower than  
3.9V (typ.) and the LDO3 voltage is lower than 2.5V (typ.),  
both switch power supplies are shut off. This is a non-  
latch protection.  
Power Good Output (PGOOD)  
PGOOD is an open-drain output and requires a pull-up  
resistor. PGOODis actively held low in soft-start, standby,  
and shutdown. For RT6575A/B, PGOODis released when  
both output voltages are above 88% of nominal regulation  
point. The PGOOD signal goes low if either output turns  
off or is 20% below or 13% over its nominal regulation  
point.  
The low-side driver is designed to drive high current low  
RDS(ON) N-MOSFET(s). The internal pull down transistor  
that drives LGATEx low is robust, with a 1Ω typical on-  
resistance. A 5V bias voltage is delivered from the LDO5  
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16  
DS6575A/B-03 February 2016  
RT6575A/B  
Output Over-Voltage Protection (OVP)  
Thermal Protection  
The output voltage can be continuously monitored for over-  
voltage condition. If the output voltage exceeds 13% of  
its set voltage threshold, the over-voltage protection is  
triggered and the LGATEx low-side gate drivers are forced  
high. This activates the low-side MOSFET switch, which  
rapidly discharges the output capacitor and pulls the output  
voltage downward.  
The RT6575A/B features thermal shutdown to prevent  
damage from excessive heat dissipation. Thermal  
shutdown occurs when the die temperature exceeds  
150°C.All internal circuitries are turned off during thermal  
shutdown. The RT6575A/B triggers thermal shutdown if  
LDO5 is not supplied from VOUT1, while input voltage on  
VIN and drawing current from LDO5 are too high.  
Nevertheless, even if LDO5 is supplied from VOUT1  
,
The RT6575A/B is latched once OVP is triggered and can  
only be released by either toggling ENx or cycling VIN.  
There is a 1μs delay built into the over-voltage protection  
circuit to prevent false transition.  
overloading LDO5 can cause large power dissipation on  
automatic switches, which may still result in thermal  
shutdown.  
Note that latching LGATEx high will cause the output  
voltage to dip slightly negative due to previously stored  
energy in the LC tank circuit. For loads that cannot tolerate  
a negative voltage, place a power Schottky diode across  
the output to act as a reverse polarity clamp.  
Discharge Mode (Soft Discharge)  
When ENx is low the output under-voltage fault latch is  
set, the output discharge mode will be triggered. During  
discharge mode, an internal switch creates a path for  
discharging the output capacitors' residual charge toGND.  
If the over-voltage condition is caused by a shorted in  
high-side switch, turning the low-side MOSFET on 100%  
will create an electrical shorted circuit between the battery  
and GND to blow the fuse and disconnecting the battery  
from the output.  
Standby Mode  
When VIN exceeds POR threshold and ENx < 0.4V, the  
RT6575A/B operate in standby mode, and CH1 and CH2  
are OFF state. For the RT6575A, LDO5 is OFF and LDO3  
is ON state and approximately consumes 15μA of input  
current. For the RT6575B, LDO5 and LDO3 are ONstate  
and approximately consumes 25μAwhile in standby mode.  
Output Under-Voltage Protection (UVP)  
The output voltage can be continuously monitored for under-  
voltage condition. If the output is less than 52% (typ.) of  
its set voltage threshold, the under-voltage protection will  
be triggered and then both UGATEx and LGATEx gate  
drivers will be forced low. The UVP is ignored for at least  
1.3ms (typ.) after a start-up or a rising edge on ENx. Toggle  
ENx or cycle VIN to reset the UVP fault latch and restart  
the controller.  
Power-Up Sequencing and On/Off Controls (ENx)  
EN1 and EN2 control the power-up sequencing of the two  
channels of the Buck converter. The 0.4V falling edge  
threshold on ENx can be used to detect a specific analog  
voltage level and to shutdown the device. Once in  
shutdown, the 1.6V rising edge threshold activates,  
providing sufficient hysteresis for most applications.  
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17  
RT6575A/B  
Table 1. Operation Mode Truth Table  
Condition  
Mode  
Comment  
LDO Over  
Current Limit  
Transitions to discharge mode after VIN POR. LDO5  
and LDO3 remain active.  
LDOx < UVLO threshold  
Run  
ENx = high, VOUT1 or VOUT2 are enabled Normal Operation.  
LGATEx is forced high. LDO3 and LDO5 are active.  
Exit by VIN POR or by toggling ENx.  
Over-Voltage  
Protection  
Either output >113% of the nominal level.  
Either output < 52% of the nominal level Both UGATEx and LGATEx are forced low and enter  
after 1.3ms time-out expires and output is discharge mode. LDO3 and LDO5 are active. Exit by  
Under-Voltage  
Protection  
enabled  
VIN POR or by toggling ENx.  
During discharge mode, there is one path to  
Discharge  
Standby  
Either output is still high in standby mode discharge the output capacitors’ residual charge to  
GND via an internal switch.  
VIN > POR  
ENx < 0.4V  
For RT6575A : LDO3 is active  
For RT6575B : LDO3, LDO5 are active  
Thermal  
Shutdown  
TJ > 150°C  
All circuitries are off. Exit by VIN POR.  
Table 2. Enabling/PGOOD State (RT6575A)  
EN1  
OFF  
ON  
EN2  
LDO5  
OFF  
ON  
LDO3  
ON  
CH1 (5VOUT)  
CH2 (3.3VOUT)  
VCLK  
OFF  
ON  
PGOOD  
Low  
OFF  
OFF  
ON  
OFF  
ON  
OFF  
OFF  
ON  
ON  
Low  
OFF  
ON  
ON  
ON  
OFF  
ON  
OFF  
ON  
Low  
ON  
ON  
ON  
ON  
High  
Table 3. Enabling/PGOOD State (RT6575B)  
EN1  
OFF  
ON  
EN2  
OFF  
OFF  
ON  
LDO5  
ON  
LDO3  
ON  
CH1 (5VOUT)  
CH2 (3.3VOUT)  
VCLK  
OFF  
ON  
PGOOD  
Low  
OFF  
ON  
OFF  
OFF  
ON  
ON  
ON  
Low  
OFF  
ON  
ON  
ON  
OFF  
ON  
OFF  
ON  
Low  
ON  
ON  
ON  
ON  
High  
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18  
DS6575A/B-03 February 2016  
RT6575A/B  
VIN POR threshold  
VIN  
LDO3  
EN threshold  
EN1  
VREG5 UVLO threshold  
Start-Up Time  
LDO5  
Soft-Start Time  
5V VOUT  
EN2  
EN threshold  
Start-Up Time  
3.3V VOUT  
PGOOD  
PGOOD  
Soft-Start Time  
Delay  
Figure 5. RT6575A Timing  
VIN POR threshold  
VIN  
LDO3  
2.5V  
LDO5  
EN threshold  
Start-Up Time  
EN1  
Soft-Start Time  
5V VOUT  
EN2  
EN threshold  
Start-Up Time  
3.3V VOUT  
PGOOD  
PGOOD  
Soft-Start Time  
Delay  
Figure 6. RT6575B Timing  
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19  
RT6575A/B  
Output Voltage Setting (FBx)  
Output Capacitor Selection  
Connect a resistive voltage divider at the FBx pin between  
VOUTx and GND to adjust the output voltage from 2V to  
5.5V for CH1 and 2V to 4V for CH2, as shown in Figure 7.  
The recommended R2 value is between 10kΩ to 20kΩ,  
and solve for R1 using the equation below :  
The capacitor value and ESR determine the amount of  
output voltage ripple and load transient response. Thus,  
the capacitor value must be greater than the largest value  
calculated from the equations below :  
(ILOAD)2 L(tON + tOFF(MIN)  
)
VSAG  
R1   
V
V  
1 +  
)
2COUT V tON VOUTx(tON + tOFF(MIN)  
OUT(Valley)  
FBx  
  
IN  
R2  
where VFBx is 2V (typ.).  
(ILOAD)2 L  
2COUT VOUTx  
VSOAR  
V
IN  
1
UGATEx  
VPP LIRILOAD(MAX) ESR +  
8COUT f  
VOUTx  
PHASEx  
LGATEx  
where VSAG and VSOAR are the allowable amount of  
undershoot and overshoot voltage during load transient,  
Vp-p is the output ripple voltage, and tOFF(MIN) is the  
minimum off-time.  
R1  
R2  
FBx  
GND  
Thermal Considerations  
Figure 7. Setting VOUTx with a resistive voltage divider  
For continuous operation, do not exceed absolute  
maximum junction temperature. The maximum power  
dissipation depends on the thermal resistance of the IC  
package, PCB layout, rate of surrounding airflow, and  
difference between junction and ambient temperature. The  
maximum power dissipation can be calculated by the  
following formula :  
Output Inductor Selection  
The switching frequency (on-time) and operating point  
(% ripple or LIR) determine the inductor value as shown  
below :  
t
(V V  
)
ON  
IN  
OUTx  
L   
LIRI  
LOAD(MAX)  
PD(MAX) = (TJ(MAX) TA) / θJA  
where LIR is the ratio of the peak-to-peak ripple current to  
the average inductor current.  
where TJ(MAX) is the maximum junction temperature, TA is  
the ambient temperature, and θJA is the junction to ambient  
thermal resistance.  
Find a low-loss inductor having the lowest possible DC  
resistance that fits in the allotted dimensions. Ferrite cores  
are often the best choice, although powdered iron is  
inexpensive and can work well at 200kHz. The core must  
be large enough not to saturate at the peak inductor  
For recommended operating condition specifications, the  
maximum junction temperature is 125°C. The junction to  
ambient thermal resistance, θJA, is layout dependent. For  
WQFN-20L 3x3 package, the thermal resistance, θJA, is  
30°C/W on a standard JEDEC 51-7 four-layer thermal test  
board. The maximum power dissipation at TA = 25°C can  
be calculated by the following formula :  
current, IPEAK  
:
IPEAK = ILOAD(MAX) + [ (LIR / 2) x ILOAD(MAX)  
]
The calculation above shall serve as a general reference.  
To further improve transient response, the output  
inductance can be further reduced. Of course, besides  
the inductor, the output capacitor should also be  
considered when improving transient response.  
PD(MAX) = (125°C 25°C) / (30°C/W) = 3.33W for  
WQFN-20L 3x3 package  
Copyright 2016 Richtek Technology Corporation. All rights reserved.  
©
is a registered trademark of Richtek Technology Corporation.  
www.richtek.com  
20  
DS6575A/B-03 February 2016  
RT6575A/B  
The maximum power dissipation depends on the operating  
ambient temperature for fixed TJ(MAX) and thermal  
resistance, θJA. The derating curve in Figure 8 allows the  
designer to see the effect of rising ambient temperature  
on the maximum power dissipation.  
Layout Considerations  
Layout is very important in high frequency switching  
converter design. Improper PCB layout can radiate  
excessive noise and contribute to the converter’s  
instability. Certain points must be considered before  
starting a layout with the RT6575A/B.  
4.0  
Four-Layer PCB  
3.5  
Place the filter capacitor close to the IC, within 12mm  
(0.5 inch) if possible.  
3.0  
2.5  
2.0  
1.5  
1.0  
0.5  
0.0  
Keep current limit setting network as close as possible  
to the IC. Routing of the network should avoid coupling  
to high-voltage switching node.  
Connections from the drivers to the respective gate of  
the high-side or the low-side MOSFET should be as  
short as possible to reduce stray inductance. Use  
0.65mm (25 mils) or wider trace.  
0
25  
50  
75  
100  
125  
All sensitive analog traces and components such as  
FBx, PGOOD, and should be placed away from high  
voltage switching nodes such as PHASEx, LGATEx,  
UGATEx, or BOOTx nodes to avoid coupling. Use  
internal layer(s) as ground plane(s) and shield the  
feedback trace from power traces and components.  
Ambient Temperature (°C)  
Figure 8. Derating Curve of Maximum PowerDissipation  
Place ground terminal of VIN capacitor(s), VOUTx  
capacitor(s), and Source of low-side MOSFETs as close  
to each other as possible. The PCB trace of PHASEx  
node, which connects to Source of high-side MOSFET,  
Drain of low-side MOSFET and high voltage side of the  
inductor, should be as short and wide as possible.  
Copyright 2016 Richtek Technology Corporation. All rights reserved.  
©
is a registered trademark of Richtek Technology Corporation.  
DS6575A/B-03 February 2016  
www.richtek.com  
21  
RT6575A/B  
Outline Dimension  
1
2
1
2
DETAILA  
Pin #1 ID and Tie Bar Mark Options  
Note : The configuration of the Pin #1 identifier is optional,  
but must be located within the zone indicated.  
Dimensions In Millimeters  
Dimensions In Inches  
Symbol  
Min  
Max  
Min  
Max  
A
A1  
A3  
b
0.700  
0.000  
0.175  
0.150  
2.900  
1.650  
2.900  
1.650  
0.800  
0.050  
0.250  
0.250  
3.100  
1.750  
3.100  
1.750  
0.028  
0.000  
0.007  
0.006  
0.114  
0.065  
0.114  
0.065  
0.031  
0.002  
0.010  
0.010  
0.122  
0.069  
0.122  
0.069  
D
D2  
E
E2  
e
0.400  
0.016  
L
0.350  
0.450  
0.014  
0.018  
W-Type 20L QFN 3x3 Package  
Richtek Technology Corporation  
14F, No. 8, Tai Yuen 1st Street, Chupei City  
Hsinchu, Taiwan, R.O.C.  
Tel: (8863)5526789  
Richtek products are sold by description only. Richtek reserves the right to change the circuitry and/or specifications without notice at any time. Customers should  
obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. Richtek cannot  
assume responsibility for use of any circuitry other than circuitry entirely embodied in a Richtek product. Information furnished by Richtek is believed to be  
accurate and reliable. However, no responsibility is assumed by Richtek or its subsidiaries for its use; nor for any infringements of patents or other rights of third  
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Richtek or its subsidiaries.  
www.richtek.com  
22  
DS6575A/B-03 February 2016  

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