RT8010A-25PQW中文资料_数据手册_规格书

RT8010/A

1.5MHz, 1A, High Efficiency PWM Step-Down DC/DC Converter

General Description

Features

ꢀ +2.5V to +5.5V Input Range

The RT8010/A is a high-efficiency Pulse-Width-Modulated

(PWM) step-downDC-DC converter. Capable of delivering

1A output current over a wide input voltage range from

2.5V to 5.5V, the RT8010/A is ideally suited for portable

electronic devices that are powered from 1-cell Li-ion

battery or from other power sources such as cellular

phones, PDAs and hand-held devices.

ꢀ Output Voltage (Adjustable Output From 0.6V to V_IN)

`RT8010 : 1.0V, 1.2V, 1.5V, 1.6V, 1.8V, 2.5V and 3.3V

Fixed/Adjustable Output Voltage

`RT8010A Adjustable Output Voltage Only

ꢀ 1A Output Current

ꢀ 95% Efficiency

ꢀ No Schottky Diode Required

Two operating modes are available including : PWM/Low-

Dropout autoswitch and shut-down modes. The Internal

synchronous rectifier with low R_DS(ON)dramatically reduces

conduction loss at PWM mode. No external Schottky

diode is required in practical application.

ꢀ 1.5MHz Fixed-Frequency PWM Operation

ꢀ Small 6-Lead WDFN and 16-Lead WQFN Package

ꢀ RoHS Compliant and 100% Lead (Pb)-Free

Applications

The RT8010/A enters Low-Dropout mode when normal

PWM cannot provide regulated output voltage by

continuously turning on the upper PMOS. RT8010/A enter

shut-down mode and consumes less than 0.1μA when

EN pin is pulled low.

ꢀ Mobile Phones

ꢀ Personal InformationAppliances

ꢀ Wireless and DSL Modems

ꢀ MP3 Players

ꢀ Portable Instruments

The switching ripple is easily smoothed-out by small

package filtering elements due to a fixed operating

frequency of 1.5MHz. This along with small WDFN-6L2x2

and WQFN-16L 3x3 package provides small PCB area

application. Other features include soft start, lower internal

reference voltage with 2% accuracy, over temperature

protection, and over current protection.

Ordering Information

RT8010/A(-

)

Package Type

QW : WDFN/WQFN (W-Type)

Operating Temperature Range

P : Pb Free with Commercial Standard

G : Green (Halogen Free with Commer-

cial Standard)

Output Voltage

Default : Adjustable (RT8010/A)

Fixed (RT8010)

10 : 1.0V

Pin Configurations

(TOP VIEW)

12 : 1.2V

16 15 14 13

15 : 1.5V

16 : 1.6V

18 : 1.8V

25 : 2.5V

VIN

12

11

GND

1

2

3

4

10 VIN

VIN

GND

9

FB/VOUT

1

2

3

6

5

4

NC

EN

FB/VOUT

GND

33 : 3.3V

5

6

7

8

VIN

LX

WQFN-16L 3x3

WDFN-6L 2x2

WDFN-6L 2x2 (RT8010)

WQFN-16L 3x3 (RT8010A)

Note :

RichTek Pb-free and Green products are :

`RoHS compliant and compatible with the current require-

ments of IPC/JEDEC J-STD-020.

Marking Information

For marking information, contact our sales representative

directly or through a RichTek distributor located in your

area, otherwise visit our website for detail.

`Suitable for use in SnPb or Pb-free soldering processes.

`100% matte tin (Sn) plating.

DS8010/A-02 March 2007

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1

RT8010/A

Typical Application Circuit

L

2.2uH

3

4

V

OUT

IN

VIN

LX

2.5V to 5.5V

C

IN

RT8010/A

4.7uF

2

1

6

5

EN

VOUT

C

OUT

10uF

NC

GND

Figure 1. Fixed Voltage Regulator

L

2.2uH

3

V

4

IN

V

VIN

OUT

LX

2.5V to 5.5V

C

IN

C1

RT8010/A

4.7uF

R1

R2

C

OUT

2

1

6

EN

NC

FB

10uF

5

GND

I

R2

R1

R2 ⎠

⎛

⎞

V_OUT= V_REFx 1+

⎜

⎟

⎝

with R2 = 300kΩ to 60kΩ so the I_R2= 2μA to 10μA,

and (R1 x C1) should be in the range between 3x10^-6and 6x10^-6for component selection.

Figure 2. Adjustable Voltage Regulator

Layout Guide

RT8010/A_ADJ

RT8010/A_FIX

Output

NC

FB

6

1

2

3

1

2

3

6

5

4

VOUT

GND

LX

NC

Output capacitor

must be near

RT8010

capacitor

must be near

RT8010/A

EN

GND

LX

5

4

EN

L1

VIN

R1

C

OUT

C

OUT

LX should be

connected to

C

IN

R2

C

IN

Inductor by wide

and short trace,

keep sensitive

compontents away

from this trace

LX should be connected

to Inductor by wide and

short trace, keep

sensitive compontents

away from this trace

C

must be placed

IN

C

must be placed

IN

between V and

DD

GND as closer as

possible

between V and

DD

GND as closer as

possible

Figure 3

Layout note:

1. The distance that C_INconnects to V_INis as close as possible (Under 2mm).

2. C_OUTshould be placed near RT8010/A.

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DS8010/A-02 March 2007

RT8010/A

Functional Pin Description

Pin Number

Pin Name

Pin Function

RT8010

RT8010A

1,

6, 8, 16,

NC

No Internal Connect (Floating or Connecting to GND).

Exposed Pad Exposed Pad

2

3

4

5

6

7

EN

Chip Enable (Active High).

9, 10, 11, 12 VIN

Power Input. (Pin 9 and Pin 10 must be connected with Pin 11)

Pin for Switching. (Pin 13 must be connected with Pin 14)

Ground.

13, 14, 15

1, 2, 3, 5

4

LX

GND

FB/VOUT

Feedback/Output Voltage Pin.

Function Block Diagram

EN

VIN

RS1

OSC &

Shutdown

Control

Current

Limit

Detector

Slope

Compensation

Current

Sense

Control

Logic

Driver

LX

PWM

Comparator

FB/VOUT

Error

Amplifier

RC

UVLO &

Power Good

Detector

RS2

COMP

V

REF

GND

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RT8010/A

Absolute Maximum Ratings (Note 1)

ꢀ Supply Input Voltage------------------------------------------------------------------------------------------------------ 6.5V

ꢀ EN, FB Pin Voltage ------------------------------------------------------------------------------------------------------- −0.3V to V_IN

ꢀ Power Dissipation, P_D@ T_A= 25°C

WDFN-6L 2x2 -------------------------------------------------------------------------------------------------------------- 0.606W

WQFN-16L 3x3 ------------------------------------------------------------------------------------------------------------ 1.47W

ꢀ Package Thermal Resistance (Note 4)

WDFN-6L 2x2, θ_JA--------------------------------------------------------------------------------------------------------- 165°C/W

WDFN-6L 2x2, θ_JC-------------------------------------------------------------------------------------------------------- 20°C/W

WQFN-16L 3x3, θ_JA------------------------------------------------------------------------------------------------------- 68°C/W

WQFN-16L 3x3, θ_JC------------------------------------------------------------------------------------------------------ 7.5°C/W

ꢀ Lead Temperature (Soldering, 10 sec.)------------------------------------------------------------------------------- 260°C

ꢀ Storage Temperature Range -------------------------------------------------------------------------------------------- −65°C to 150°C

ꢀ Junction Temperature ----------------------------------------------------------------------------------------------------- 150°C

ꢀ ESD Susceptibility (Note 2)

HBM (Human Body Mode) ---------------------------------------------------------------------------------------------- 2kV

MM (Machine Mode) ------------------------------------------------------------------------------------------------------ 200V

Recommended Operating Conditions (Note 3)

ꢀ Supply Input Voltage------------------------------------------------------------------------------------------------------ 2.5V to 5.5V

ꢀ Junction Temperature Range-------------------------------------------------------------------------------------------- −40°C to 125°C

ꢀ Ambient Temperature Range-------------------------------------------------------------------------------------------- −40°C to 85°C

Electrical Characteristics

(V_IN= 3.6V, V_OUT= 2.5V, V_REF= 0.6V, L = 2.2μH, C_IN= 4.7μF, C_OUT= 10μF, T_A= 25°C, I_MAX= 1A unless otherwise specified)

Parameter

Input Voltage Range

Symbol

Test Conditions

Min

2.5

--

Typ

--

Max

5.5

Units

V

I

IN

Quiescent Current

Shutdown Current

50

0.1

0.6

--

70

I

= 0mA, V = V + 5%

REF

μA

V

Q

OUT

FB

EN = GND

--

1

I

SHDN

Reference Voltage

Adjustable Output Range

For Adjustable Output Voltage

(Note 6)

0.588

0.612

V

REF

OUT

V

REF

V

− 0.2V

IN

V

= 2.5V to 5.5V, V

= 1.0V

= 1.2V

= 1.5V

= 1.6V

= 1.8V

IN

OUT

--

+3

%

ΔV

−3

OUT

0A < I

< 1A

OUT

V

IN

= 2.5V to 5.5V, V

0A < I

< 1A

OUT

Output Voltage

Fix

V

IN

= 2.5V to 5.5V, V

Accuracy

0A < I

< 1A

OUT

V

IN

= 2.5V to 5.5V, V

0A < I

< 1A

OUT

V

IN

= 2.5V to 5.5V, V

0A < I

< 1A

OUT

To be continued

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DS8010/A-02 March 2007

RT8010/A

Parameter

Symbol

Test Conditions

Min

−3

Typ

--

Max Units

V

= V

+ ΔV to 5.5V

(Note 5)

+3

%

ΔV

IN

OUT

Output Voltage

Accuracy

Fix

+ ΔV to 5.5V

--

ΔV

OUT

−3

Output Voltage

Accuracy

Adjustable

--

+3

%

ΔV

−3

OUT

0A < I

< 1A

OUT

FB Input Current

--

0.28

0.38

0.25

0.35

1.5

--

50

--

nA

I

V

= V

−50

--

FB

IN

V

= 3.6V

IN

PMOSFET R

R

I

= 200mA

Ω

ON

DS(ON)_P OUT

--

= 2.5V

= 3.6V

= 2.5V

--

NMOSFET R

R

I

= 200mA

Ω

A

V

ON

DS(ON)_N OUT

--

P-Channel Current Limit

1.4

--

I

V

IN

V

IN

V

IN

= 2.5V to 5.5 V

= 2.5V to 5.5V

LIM_P

EN High-Level Input Voltage

EN Low-Level Input Voltage

1.5

--

V

EN_H

--

0.4

--

EN_L

Under Voltage Lock Out threshold UVLO

Hysteresis

--

1.8

0.1

1.5

160

--

V

--

Oscillator Frequency

Thermal Shutdown Temperature

Max. Duty Cycle

1.2

--

1.8

--

MHz

°C

%

f

V

= 3.6V, I

= 100mA

OSC

IN

OUT

T

SD

100

−1

--

LX Leakage Current

--

1

= 3.6V, V = 0V or V = 3.6V

μA

IN

LX

Note 1. Stresses listed as the above “Absolute Maximum Ratings” may cause permanent damage to the device. These are for

stress ratings. Functional operation of the device at these or any other conditions beyond those indicated in the

operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended

periods may remain possibility to affect device reliability.

Note 2. Devices are ESD sensitive. Handling precaution recommended.

Note 3. The device is not guaranteed to function outside its operating conditions.

Note 4. θ_JAis measured in the natural convection at T_A= 25°C on a high effective four layers thermal conductivity test board of

JEDEC 51-7 thermal measurement standard. The case point of θ_JCis on the expose pad for the QFN package.

Note 5. ΔV = I_OUTx P_RDS(ON)

Note 6. Guarantee by design.

DS8010/A-02 March 2007

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RT8010/A

Typical Operating Characteristics

Efficiency vs. Output Current

100

90

80

70

60

50

40

30

20

10

0

100

90

V_IN= 3.6V

V_IN= 4.2V

V_IN= 5.0V

70

80

V_IN= 5.0V

V_IN= 3.3V

V_IN= 2.5V

60

50

40

30

20

10

V_OUT= 1.2V, C_OUT= 4.7μF, L = 4.7μH

V_OUT= 3.3V, C_OUT= 4.7μF, L = 4.7μH

0

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

Output Current (A)

1

0

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

Output Current (A)

1

Efficiency vs. Output Current

UVLO Voltage vs.Temperature

100

90

80

70

60

50

40

30

20

10

0

2.0

1.9

1.8

1.7

1.6

1.5

1.4

1.3

1.2

Rising

V_IN= 5.0V

V_IN= 3.3V

V_IN= 2.5V

Falling

V_OUT= 1.2V, I_OUT= 0A

V_OUT= 1.2V, C_OUT= 10μF, L = 2.2μH

0

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

Output Current (A)

1

-40 -25 -10

5

20 35 50 65 80 95 110 125

(°C)

Temperature

EN Pin Threshold vs. Input Voltage

EN Pin Threshold vs. Temperature

1.20

1.15

1.10

1.05

1.00

0.95

0.90

0.85

0.80

0.75

0.70

0.65

0.60

1.6

1.5

1.4

1.3

1.2

1.1

1.0

0.9

0.8

0.7

0.6

0.5

0.4

Rising

Falling

Rising

Falling

V_OUT= 1.2V, I_OUT= 0A

V_IN= 3.6V, V_OUT= 1.2V, I_OUT= 0A

2.5 2.8 3.1 3.4 3.7

4

4.3 4.6 4.9 5.2 5.5

-40 -25 -10

5

20 35 50 65 80 95 110 125

(°C)

Temperature

Input Voltage (V)

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RT8010/A

Output Voltage vs. Temperature

Output Voltage vs. Load Current

1.230

1.225

1.220

1.215

1.210

1.205

1.200

1.195

1.190

1.185

1.180

1.25

1.24

1.23

1.22

1.21

1.20

1.19

1.18

1.17

1.16

1.15

V_IN= 5.0V

V_IN= 3.6V

V_IN= 3.6V, I_OUT= 0A

0

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

Load Current (A)

1

-40 -25 -10

5

20 35 50 65 80 95 110 125

Temperature

(°C)

Frequency vs. Input Voltage

Frequency vs. Temperature

1.60

1.55

1.50

1.45

1.40

1.35

1.30

1.25

1.20

1.60

1.55

1.50

1.45

1.40

1.35

1.30

1.25

1.20

V_IN= 3.6V, V_OUT= 1.2V, I_OUT= 300mA

-40 -25 -10

5

20 35 50 65 80 95 110 125

2.5 2.8 3.1 3.4 3.7

4

4.3 4.6 4.9 5.2 5.5

Temperature

(°C)

Input Voltage (V)

Output Current Limit vs. Input Voltage

Output Current Limit vs. Temperature

2.6

2.5

2.4

2.3

2.2

2.1

2.0

1.9

1.8

1.7

1.6

1.5

2.6

2.5

2.4

2.3

2.2

2.1

2.0

1.9

1.8

1.7

1.6

1.5

V_IN= 5.0V

V_IN= 3.6V

V_IN= 3.3V

V_OUT= 1.2V @ T_A= 20°C

V_OUT= 1.2V

2.5 2.8 3.1 3.4 3.7

4

4.3 4.6 4.9 5.2 5.5

-40 -25 -10

5

20 35 50 65 80 95 110 125

(°C)

Temperature

Input Voltage (V)

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7

RT8010/A

Power On from EN

V_IN= 3.6V, V_OUT= 1.2V, I_OUT= 10mA

V_IN= 3.6V, V_OUT= 1.2V, I_OUT= 1A

V_EN

(2V/Div)

V_EN

(2V/Div)

V_OUT

(1V/Div)

V_OUT

(1V/Div)

I_IN

(500mA/Div)

Time (100μs/Div)

Power Off from EN

Power On from VIN

V_IN= 3.6V, V_OUT= 1.2V, I_LX= 1A

V_EN= 3V, V_OUT= 1.2V, I_LX= 1A

V_EN

(2V/Div)

V_IN

(2V/Div)

V_OUT

(1V/Div)

V_OUT

(1V/Div)

I_LX

(1A/Div)

I_LX

(1A/Div)

Time (100μs/Div)

Time (250μs/Div)

Load Transient Response

V_IN= 3.6V, V_OUT= 1.2V

I_OUT= 50mA to 0.5A

I_OUT= 50mA to 1A

V_OUTac

(50mV/Div)

V_OUTac

(50mV/Div)

I_OUT

(500mA/Div)

I_OUT

(500mA/Div)

Time (50μs/Div)

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RT8010/A

Load Transient Response

V_IN= 5V, V_OUT= 1.2V

I_OUT= 50mA to 0.5A

V_IN= 5V, V_OUT= 1.2V

I_OUT= 50mA to 1A

V_OUTac

(50mV/Div)

V_OUTac

(50mV/Div)

I_OUT

(500mA/Div)

I_OUT

(500mA/Div)

Time (50μs/Div)

Output Ripple Voltage

V_IN= 3.6V, V_OUT= 1.2V

_OUT= 1A

V_IN= 5V, V_OUT= 1.2V

I_OUT= 1A

I

V_OUT

(10mV/Div)

V_OUT

(10mV/Div)

V_LX

(2V/Div)

V_LX

(2V/Div)

Time (500ns/Div)

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9

RT8010/A

Applications Information

current is exceeded. This results in an abrupt increase in

inductor ripple current and consequent output voltage ripple.

Do not allow the core to saturate!

The basic RT8010/Aapplication circuit is shown in Typical

Application Circuit. External component selection is

determined by the maximum load current and begins with

the selection of the inductor value and operating frequency

Different core materials and shapes will change the size/

current and price/current relationship of an inductor.

followed by C_INand C_OUT

.

Toroid or shielded pot cores in ferrite or permalloy materials

are small and don't radiate energy but generally cost more

than powdered iron core inductors with similar

characteristics. The choice of which style inductor to use

mainly depends on the price vs size requirements and

any radiated field/EMI requirements.

Inductor Selection

For a given input and output voltage, the inductor value

and operating frequency determine the ripple current. The

ripple current ΔI_Lincreases with higher V_INand decreases

with higher inductance.

V

f ×L

V

OUT

V

IN

⎡

⎤

⎡

⎤

OUT

ΔI =

L

× 1−

⎢

⎣

⎥

⎦

⎢

⎣

⎥

⎦

C_INand C_OUTSelection

The input capacitance, C_IN, is needed to filter the

trapezoidal current at the source of the top MOSFET. To

prevent large ripple voltage, a low ESR input capacitor

sized for the maximum RMS current should be used. RMS

current is given by :

Having a lower ripple current reduces the ESR losses in

the output capacitors and the output voltage ripple. Highest

efficiency operation is achieved at low frequency with small

ripple current. This, however, requires a large inductor.

Areasonable starting point for selecting the ripple current

is ΔI_L= 0.4(I_MAX). The largest ripple current occurs at the

highest V_IN. To guarantee that the ripple current stays

below a specified maximum, the inductor value should be

chosen according to the following equation :

V_OUT

V

IN

I_RMS= I_OUT(MAX)

−1

V

V_OUT

IN

This formula has a maximum at V_IN= 2V_OUT, where

I_RMS= I_OUT/2. This simple worst-case condition is

commonly used for design because even significant

deviations do not offer much relief.Note that ripple current

ratings from capacitor manufacturers are often based on

only 2000 hours of life which makes it advisable to further

derate the capacitor, or choose a capacitor rated at a higher

temperature than required. Several capacitors may also

be paralleled to meet size or height requirements in the

design.

⎡

⎤

V

OUT

⎡

⎤

OUT

f × ΔIL(MAX)

L =

× 1−

⎢

⎥

⎦

⎢

⎣

⎥

⎦

V

IN(MAX)

⎣

Inductor Core Selection

Once the value for L is known, the type of inductor must

be selected. High efficiency converters generally cannot

afford the core loss found in low cost powdered iron cores,

forcing the use of more expensive ferrite or mollypermalloy

cores. Actual core loss is independent of core size for a

fixed inductor value but it is very dependent on the

inductance selected. As the inductance increases, core

losses decrease. Unfortunately, increased inductance

requires more turns of wire and therefore copper losses

will increase.

The selection of C_OUTis determined by the effective series

resistance (ESR) that is required to minimize voltage ripple

and load step transients, as well as the amount of bulk

capacitance that is necessary to ensure that the control

loop is stable. Loop stability can be checked by viewing

the load transient response as described in a later section.

The output ripple, ΔV_OUT, is determined by :

Ferrite designs have very low core losses and are preferred

at high switching frequencies, so design goals can

concentrate on copper loss and preventing saturation.

Ferrite core material saturates “hard”, which means that

inductance collapses abruptly when the peak design

⎡

⎣

⎤

1

ΔV

≤ ΔI ESR +

OUT

L

⎢

⎥

⎦

8fC

OUT

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DS8010/A-02 March 2007

RT8010/A

The output ripple is highest at maximum input voltage

since ΔI_Lincreases with input voltage. Multiple capacitors

placed in parallel may be needed to meet the ESR and

RMS current handling requirements.Dry tantalum, special

polymer, aluminum electrolytic and ceramic capacitors are

all available in surface mount packages. Special polymer

capacitors offer very low ESR but have lower capacitance

density than other types. Tantalum capacitors have the

highest capacitance density but it is important to only

use types that have been surge tested for use in switching

power supplies. Aluminum electrolytic capacitors have

significantly higher ESR but can be used in cost-sensitive

applications provided that consideration is given to ripple

current ratings and long term reliability. Ceramic capacitors

have excellent low ESR characteristics but can have a

high voltage coefficient and audible piezoelectric effects.

The high Q of ceramic capacitors with trace inductance

can also lead to significant ringing.

For adjustable voltage mode, the output voltage is set by

an external resistive divider according to the following

equation :

R1

V

= V

(1+

)

OUT

REF

R2

where V_REFis the internal reference voltage (0.6V typ.)

Efficiency Considerations

The efficiency of a switching regulator is equal to the output

power divided by the input power times 100%. It is often

useful to analyze individual losses to determine what is

limiting the efficiency and which change would produce

the most improvement. Efficiency can be expressed as :

Efficiency = 100% − (L1+ L2+ L3+ ...)

where L1, L2, etc. are the individual losses as a percentage

of input power. Although all dissipative elements in the

circuit produce losses, two main sources usually account

for most of the losses : VIN quiescent current and I²R

losses.

Using Ceramic Input and Output Capacitors

The VIN quiescent current loss dominates the efficiency

loss at very low load currents whereas the I²R loss

dominates the efficiency loss at medium to high load

currents. In a typical efficiency plot, the efficiency curve

at very low load currents can be misleading since the

actual power lost is of no consequence.

Higher values, lower cost ceramic capacitors are now

becoming available in smaller case sizes. Their high ripple

current, high voltage rating and low ESR make them ideal

for switching regulator applications. However, care must

be taken when these capacitors are used at the input and

output. When a ceramic capacitor is used at the input

and the power is supplied by a wall adapter through long

wires, a load step at the output can induce ringing at the

input, V_IN. At best, this ringing can couple to the output

and be mistaken as loop instability. At worst, a sudden

inrush of current through the long wires can potentially

cause a voltage spike at V_INlarge enough to damage the

part.

1. The VIN quiescent current appears due to two factors

including : the DC bias current as given in the electrical

characteristics and the internal main switch and

synchronous switch gate charge currents. The gate charge

current results from switching the gate capacitance of the

internal power MOSFET switches. Each time the gate is

switched from high to low to high again, a packet of charge

ΔQ moves from V_INto ground.

Output Voltage Programming

The resulting ΔQ/Δt is the current out of V_INthat is typically

larger than the DC bias current. In continuous mode,

The resistive divider allows the FB pin to sense a fraction

of the output voltage as shown in Figure 4.

I_GATECHG= f(Q_T+Q_B)

V

OUT

where Q_Tand Q_Bare the gate charges of the internal top

and bottom switches. Both the DC bias and gate charge

losses are proportional to V_INand thus their effects will

be more pronounced at higher supply voltages.

R1

FB

RT8010/A

GND

R2

Figure 4. Setting the Output Voltage

DS8010/A-02 March 2007

www.richtek.com

11

RT8010/A

2. I²R losses are calculated from the resistances of the

internal switches, R_SWand external inductor R_L. In

continuous mode, the average output current flowing

through inductor L is “chopped” between the main switch

and the synchronous switch. Thus, the series resistance

looking into the LX pin is a function of both top and bottom

MOSFET R_DS(ON)and the duty cycle (DC) as follows :

For RT8010/A packages, the Figure 5 of derating curves

allows the designer to see the effect of rising ambient

temperature on the maximum power allowed.

1.6

Four Layers PCB

1.4

1.2

WQFN-16L 3x3

1.0

R_SW= R_DS(ON)TOPx DC + R_DS(ON)BOTx (1−DC)

0.8

The R_DS(ON)for both the top and bottom MOSFETs can be

obtained from the Typical Performance Characteristics

curves. Thus, to obtain I²R losses, simply add R_SWto R_L

and multiply the result by the square of the average output

current.

WDFN-6L 2x2

0.6

0.4

0.2

0.0

Other losses including C_INand C_OUTESR dissipative

losses and inductor core losses generally account for less

than 2% of the total loss.

0

25

50

75

100

125

(°C)

Ambient Temperature

Figure 5. Derating Curves for RT8010/APackage

Thermal Considerations

Checking Transient Response

The maximum power dissipation depends on the thermal

resistance of IC package, PCB layout, the rate of

surroundings airflow and temperature difference between

junction to ambient. The maximum power dissipation can

be calculated by following formula :

The regulator loop response can be checked by looking

at the load transient response. Switching regulators take

several cycles to respond to a step in load current. When

a load step occurs, V_OUTimmediately shifts by an amount

equal to ΔI_LOAD(ESR), where ESR is the effective series

resistance of C_OUT. ΔI_LOADalso begins to charge or

discharge C_OUTgenerating a feedback error signal used

by the regulator to return V_OUTto its steady-state value.

During this recovery time, V_OUTcan be monitored for

overshoot or ringing that would indicate a stability problem.

P_D(MAX)= ( T_J(MAX)- T_A) / θ_JA

Where T_J(MAX)is the maximum operation junction

temperature, T_Ais the ambient temperature and the θ_JAis

the junction to ambient thermal resistance.

For recommended operating conditions specification of

RT8010/ADC/DC converter, where T_J(MAX)is the maximum

junction temperature of the die and T_Ais the maximum

ambient temperature. The junction to ambient thermal

resistance θ_JAis layout dependent. For WDFN-6L 2x2

packages, the thermal resistance θ_JAis 165°C/W on the

standard JEDEC 51-7 four layers thermal test board.

Layout Considerations

Follow the PCB layout guidelines for optimal performance

of RT8010/A.

` For the main current paths as indicated in bold lines in

Figure 6, keep their traces short and wide.

The maximum power dissipation at T_A= 25°C can be

` Put the input capacitor as close as possible to the device

calculated by following formula :

pins (VINandGND).

P_D(MAX)= (125°C − 25°C) / 165°C/W = 0.606W for

WDFN-6L 2x2 packages

`LX node is with high frequency voltage swing and should

be kept small area. Keep analog components away from

LX node to prevent stray capacitive noise pick-up.

The maximum power dissipation depends on operating

ambient temperature for fixed T_J(MAX)and thermal

resistance θ_JA.

` Connect feedback network behind the output capacitors.

Keep the loop area small. Place the feedback

components near the RT8010/A.

www.richtek.com

12

DS8010/A-02 March 2007

RT8010/A

` Connect all analog grounds to a command node and

then connect the command node to the power ground

behind the output capacitors.

` An example of 2-layer PCB layout is shown in Figure 7

to Figure 8 for reference.

V

IN

OUT

L1

RT8010/A

VIN

3

4

Figure 7. Top Layer

LX

C2

1

R1

NC

EN

6

5

FB/VOUT

GND

C3

2

C1

R2

V

IN

R3

Figure 6. EVB Schematic

Figure 8. Bottom Layer

Table 1. Recommended Inductors

Inductance

DCR

(mΩ)

Dimensions

(mm)

Supplier

(uH)

Current Rating (mA)

Series

TAIYO YUDEN

GOTREND

Sumida

2.2

4.7

1480

1500

1000

1020

1100

60

58

3.00 x 3.00 x 1.50

3.85 x 3.85 x 1.80

NR 3015

GTSD32

75

4.50 x 3.20 x 1.55

3.00 x 3.00 x 1.50

3.85 x 3.85 x 1.80

CDRH2D14

NR 3015

Sumida

135

120

146

TAIYO YUDEN

GOTREND

GTSD32

Table 2. Recommended Capacitors for C_INand C_OUT

Capacitance

Supplier

Package

Part Number

(uF)

TDK

4.7

603

805

C1608JB0J475M

MURATA

4.7

10

GRM188R60J475KE19

JMK107BJ475RA

TAIYO YUDEN

TDK

JMK107BJ106MA

C2012JB0J106M

MURATA

GRM219R60J106ME19

GRM219R60J106KE19

JMK212BJ106RD

MURATA

TAIYO YUDEN

DS8010/A-02 March 2007

www.richtek.com

13

RT8010/A

Outline Dimension

D

D2

L

E

E2

SEE DETAIL A

1

b

e

2

1

2

1

A

A3

A1

DETAILA

Pin #1 ID and Tie Bar Mark Options

Note : The configuration of the Pin #1 identifier is optional,

but must be located within the zone indicated.

Dimensions In Millimeters

Dimensions In Inches

Symbol

Min

Max

Min

Max

A

A1

A3

b

0.700

0.000

0.175

0.200

1.950

1.000

1.950

0.500

0.800

0.050

0.250

0.350

2.050

1.450

2.050

0.850

0.028

0.000

0.007

0.008

0.077

0.039

0.077

0.020

0.031

0.002

0.010

0.014

0.081

0.057

0.081

0.033

D

D2

E

E2

e

0.650

0.026

L

0.300

0.400

0.012

0.016

W-Type 6L DFN 2x2 Package

www.richtek.com

14

DS8010/A-02 March 2007

RT8010/A

SEE DETAIL A

D

D2

L

1

E

E2

1

2

1

2

e

b

DETAILA

A

A3

Pin #1 ID and Tie Bar Mark Options

A1

Note : The configuration of the Pin #1 identifier is optional,

but must be located within the zone indicated.

Dimensions In Millimeters

Dimensions In Inches

Symbol

Min

Max

Min

Max

A

A1

A3

b

0.700

0.000

0.175

0.180

2.950

1.300

2.950

1.300

0.800

0.050

0.250

0.300

3.050

1.750

3.050

1.750

0.028

0.000

0.007

0.116

0.051

0.116

0.051

0.031

0.002

0.010

0.012

0.120

0.069

0.120

0.069

D

D2

E

E2

e

0.500

0.020

L

0.350

0.450

0.014

0.018

W-Type 16L QFN 3x3 Package

Richtek Technology Corporation

Headquarter

Richtek Technology Corporation

Taipei Office (Marketing)

5F, No. 20, Taiyuen Street, Chupei City

Hsinchu, Taiwan, R.O.C.

8F, No. 137, Lane 235, Paochiao Road, Hsintien City

Taipei County, Taiwan, R.O.C.

Tel: (8863)5526789 Fax: (8863)5526611

Tel: (8862)89191466 Fax: (8862)89191465

Email: marketing@richtek.com

DS8010/A-02 March 2007

www.richtek.com

15

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