RT8120A_技术文档

®

RT8120

Single-Phase Synchronous Buck PWM Controller

General Description

Features

^zWide Input Voltage Range : 3V to 13.2V

^zEmbedded Switching Boot Diode

^z0.8V 1%, 0.6V 1.5% Internal Reference

^zShoot-Through Protection and Short Pulse Free

Technology for Gate Drivers

The RT8120 is a single-phase synchronous buck PWM

DC/DC controller designed to drive two N-MOSFET. It

provides a highly accurate, programmable output voltage

precisely regulated to low voltage requirements with an

internal 0.8V 1% ( option for 0.6V 1.5%) reference. The

RT8120 uses a single feedback loop voltage mode PWM

control for fast transient response.An oscillator with fixed

frequency 300kHz reduces the external inductor and

capacitor component size for saving PCB board area. The

RT8120 provides fast transient response to satisfy high

current output applications while minimizing external

components. It is suitable for high performance graphic

processors,DDR and VTTpower. The RT8120 incorporates

an externally compensated error amplifier and an internal

soft-start and output enable. The RT8120 comes in

SOP-8 and SOP-8 (Exposed Pad) packages.

^zFixed Frequency 300kHz

^zInternal Soft-Start

^zOver Current Protection by Sensing MOSFET R_DS(ON)

^zEnable/Shutdown Control

^zDrives Two N-MOSFETs

^zFull Duty Cycle : 0% to 85%

^zFast Transient Response

z Voltage Mode PWM Control with External

Feedback Loop Compensation

z Pinless LGATE Over Current Setting (LGOCS)

z Under Voltage Protection

z SOP-8 and SOP-8 (Exposed Pad) Packages

z RoHS Compliant and Halogen Free

Ordering Information

RT8120

Applications

Package Type

S : SOP-8

SP : SOP-8 (Exposed-Pad-Option 1)

z System (Graphic, MB) with 5V or 12V Power

z Graphic Cards (AGP 8X, 4X, PCI Express*16)

z 3.3V to 12V Input DC/DC Regulators

Lead Plating System

z Low VoltageDistributed Power Supplies

G : Green (Halogen Free and Pb Free)

Z : ECO (Ecological Element with

Halogen Free and Pb free)

Pin Configurations

Reference Voltage

A/C : 0.6V

(TOP VIEW)

B/D : 0.8V

8

BOOT

UGATE

PHASE

COMP/EN

FB

2

3

4

7

6

5

Note :

GND

Richtek products are :

LGATE/OCSET

VCC

` RoHS compliant and compatible with the current require-

ments of IPC/JEDEC J-STD-020.

` Suitable for use in SnPb or Pb-free soldering processes.

SOP-8

8

7

6

5

BOOT

UGATE

PHASE

COMP/EN

FB

2

3

4

GND

9

LGATE/OCSET

VCC

SOP-8 (Exposed Pad)

©

is a registered trademark of Richtek Technology Corporation.

DS8120-08 September 2013

www.richtek.com

1

RT8120

Marking Information

RT8120xGS

RT8120xZS

RT8120xZS : Product Number

YMDNN : Date Code

RT8120xGS : Product Number

RT8120x

GSYMDNN

RT8120x

ZSYMDNN

YMDNN : Date Code

RT8120xGSP

RT8120xZSP

RT8120xGSP : Product Number

YMDNN : Date Code

RT8120xZSP : Product Number

YMDNN : Date Code

RT8120x

GSPYMDNN

RT8120x

ZSPYMDNN

Typical Application Circuit

V

IN

RT8120

C1

R1

R2

R3

5

1

V

CC

C

VCC

BOOT

IN

C

Bypass

2

8

Q1

UGATE

PHASE

7

6

COMP/EN

FB

L

OUT

V

OUT

R

C

OUT

4

3

R5

C3

C

P

LGATE/

OCSET

GND

R4

EN

Q2

1

R

C

FB1

C

C2

3.3nF

R

OCSET

R

FB2

©

is a registered trademark of Richtek Technology Corporation.

www.richtek.com

2

DS8120-08 September 2013

RT8120

Function Block Diagram

VCC

Internal

Regulator

BOOT

POR

UGATE

PHASE

Error

Amp

V

REF

PWM

+

-

+

Gate

Control

FB

-

VCC

COMP/EN

LGATE/

OCSET

ramp

SS

Soft-Start/

Fault Logic

fault

GND

+

-

Oscillator

Sample

/Hold

I

OCSET

Figuer 1. RT8120A/B Function Block Diagram

VCC

Internal

Regulator

BOOT

POR

UGATE

PHASE

Error

Amp

V

REF

PWM

+

Gate

Control

FB

COMP/EN

-

VCC

LGATE/

OCSET

ramp

SS

Soft-Start/

Fault Logic

fault

GND

+

-

PHASE

V

IN

Detection

Oscillator

Sample

/Hold

I

OCSET

Figuer 2. RT8120C/DFunction BlockDiagram

©

is a registered trademark of Richtek Technology Corporation.

DS8120-08 September 2013

www.richtek.com

3

RT8120

Functional Pin Description

Pin No.

SOP-8

(Exposed Pad)

Pin Name

Pin Function

SOP-8

Bootstrap Power Pin. This pin powers the upper gate driver.

Connect a bootstrap capacitor between the BOOT pin and

PHASE pin on the upper MOSFET.

1

2

BOOT

Upper-Gate Driver Output. Connect to gate of the high side

power N-MOSFET. This pin is monitored by the adaptive

shoot-through protection circuitry to determine when the upper

MOSFET has turned off.

2

3

UGATE

Ground for the IC. All voltage levels are measured with respect to

this pin. Connect this pin directly to the low side MOSFET source

and ground plane with the lowest impedance. The exposed pad

must be soldered to a large PCB and connected to GND for

maximum power dissipation.

3,

GND

9 (Exposed Pad)

Lower-Gate Driver Output. Connect to the gate of the low side

power N-MOSFET. It provides the PWM-controlled gate drive

(from VCC). This pin is also monitored by the adaptive

shoot-through protection circuitry to determine when the lower

4

LGATE/OCSET MOSFET has turned off. During a short period of time following

Power-On Reset (POR) or shutdown release, this pin is also used

to determine the over-current threshold of the converter

(LGOCS). Connect a resistor (R_OCSET) from this pin to GND. See

the over current protection section for equations.

Supply Input Pin. Connect this pin to a well-decoupled 5V or 12V

5

6

5

6

VCC

FB

bias supply. It is also the positive supply for the lower gate driver,

LGATE.

Feedback Input Pin. This pin is the inverting input of the error

amplifier. FB senses the switch output through an external

resistor divider network.

Feedback Compensation. And could be used as EN pin, when

COMP < 0.4V, to disable entire chip.

7

8

7

8

COMP/EN

PHASE

Switch Node. Connect this pin to the source of the upper

MOSFET and the drain of the lower MOSFET.

©

is a registered trademark of Richtek Technology Corporation.

www.richtek.com

4

DS8120-08 September 2013

RT8120

Absolute Maximum Ratings (Note 1)

z VCC to GND, VCC --------------------------------------------------------------------------------------- 15V

z BOOT to PHASE, V_BOOT−PHASE----------------------------------------------------------------------- 15V

z PHASE to GND

DC------------------------------------------------------------------------------------------------------------ −0.5V to 15V

< 20ns ------------------------------------------------------------------------------------------------------ −8V to 25V

z UGATE to PHASE

DC------------------------------------------------------------------------------------------------------------ −0.3V to (V_BOOT−PHASE+ 0.3V)

< 20ns ------------------------------------------------------------------------------------------------------ −5V to (V_BOOT−PHASE+ 5V)

z LGATE toGND

DC------------------------------------------------------------------------------------------------------------ −0.3V to (V_CC+ 0.3V)

< 20ns ------------------------------------------------------------------------------------------------------ −5V to (V_CC+ 5V)

z Other Pins-------------------------------------------------------------------------------------------------- −0.3V to 7V

z Power Dissipation, P_D@ T_A= 25°C

SOP-8------------------------------------------------------------------------------------------------------- 0.53W

SOP-8 (Exposed Pad) ---------------------------------------------------------------------------------- 3.26W

z Package Thermal Resistance (Note 2)

SOP-8, θ_JA------------------------------------------------------------------------------------------------ 188°C/W

SOP-8 (Exposed Pad), θ_JA---------------------------------------------------------------------------- 30.6°C/W

SOP-8 (Exposed Pad), θ_JC---------------------------------------------------------------------------- 3.4°C/W

z Lead Temperature (Soldering, 10 sec.)-------------------------------------------------------------- 260°C

z Junction Temperature ------------------------------------------------------------------------------------ 150°C

z Storage Temperature Range --------------------------------------------------------------------------- −65°C to 150°C

z ESD Susceptibility (Note 3)

HBM (Human Body Model)----------------------------------------------------------------------------- 2kV

Recommended Operating Conditions (Note 4)

z Supply Input Voltage, VIN ------------------------------------------------------------------------------ 3V to 13.2V

z Control Input Voltage, VCC ---------------------------------------------------------------------------- 4.5V to 13.2V

z Junction Temperature Range--------------------------------------------------------------------------- −40°C to 125°C

z Ambient Temperature Range--------------------------------------------------------------------------- −40°C to 85°C

©

is a registered trademark of Richtek Technology Corporation.

DS8120-08 September 2013

www.richtek.com

5

RT8120

Electrical Characteristics

( T_A= 25°C, unless otherwise specified)

Parameter

Supply Current

Shutdown Current

Symbol

Test Conditions

UGATE, LGATE Open, V = 12V

Min

--

Typ Max Unit

I

1.5

0.7

4.1

--

mA

V

CC

UGATE, LGATE Open, V = 12V

--

SHDN

CC

Power On Reset Threshold V

V

Rising

CC

3.9

4.3

CCR_TH

Power On Reset

V

0.26 0.45 0.64

V

CC_Hys

OSC

Hysteresis

Switching Frequency

Ramp Amplitude

f

270

--

300

1.3

--

330

--

kHz

ΔV

V

OSC

P-P

Minimum Duty Cycle

Maximum Duty Cycle

0

--

%

D

--

85

--

MAX

RT8120A/C

0.591 0.6 0.609

0.792 0.8 0.808

Reference Voltage

V

REF

RT8120B/D

Open Loop DC Gain

Gain Bandwidth

Guaranteed by Design

--

70

10

6

--

dB

MHz

V/μs

μA/V

μA

A

DC

GBW

SR

Slew Rate

--

Guaranteed by Design, C = 10pF

L

Transconductance

Output Source Current

Output Sink Current

gm

500

700

80

--

120

1.5

2

--

I

V

< V

COMPSK

FB

REF

μA

I

COMPSC

SS

REF

RT8120A/C

RT8120B/D

Soft-Start Time

ms

t

--

Upper Gate Sourcing

Ability

--

1.2

3

--

A

Ω

I

V

− V

PHASE

= 12V, max source current

= 0.1V

UG_SRC

BOOT

Upper Gate R

Sinking

DS(ON)

R

− V

PHASE

UG_SNK

UGATE

Lower Gate Sourcing

Ability

1.2

1.8

30

A

I

= 12V, max source current

= 0.1V

LG_SRC

CC

Lower Gate R

Sinking

DS(ON)

R

Ω

LG_INK

LGATE

Deadtime between UGATE

Off to LGATE On

ns

− V

= 1.2V to V

=1.2V

UGATE

PHASE

LGATE

Deadtime Between LGATE

Off to UGATE On

= 1.2V

Protection

Under Voltage Protection

65

75

80

%

V

UVP_FB

D_UVP

Under Voltage Delay

LGATE OC Setting Current

Over Current Threshold

Enable Threshold

--

9

6

--

11

μs

V

I

10

μA

mV

V

OCSET

--

375

0.4

--

V

R

= Open

OCSET

PHASE

EN

0.3

0.55

V

©

is a registered trademark of Richtek Technology Corporation.

www.richtek.com

6

DS8120-08 September 2013

RT8120

Note 1. Stresses beyond those listed “Absolute Maximum Ratings” may cause permanent damage to the device. These are

stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in

the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions may

affect device reliability.

Note 2. θ_JAis measured at T_A= 25°C on a high effective thermal conductivity four-layer test board per JEDEC 51-7. θ_JCis

measured at the exposed pad of the package.

Note 3. Devices are ESD sensitive. Handling precaution is recommended.

Note 4. The device is not guaranteed to function outside its operating conditions.

©

is a registered trademark of Richtek Technology Corporation.

DS8120-08 September 2013

www.richtek.com

7

RT8120

Typical Operating Characteristics

Efficiency vs. Output Current

Output Voltage vs. Output Current

100

1.500

1.495

1.490

1.485

1.480

1.475

1.470

95

90

85

80

75

70

65

60

55

V_IN= V_CC= 12V, V_OUT= 1.5V

50

0

5

10

15

20

25

30

0

2

4

6

8

10 12 14 16 18 20

Output Current (A)

Reference Voltage vs. Temperature

Frequency vs. Temperature

300

290

280

270

260

250

0.820

0.815

0.810

0.805

0.800

0.795

0.790

0.785

0.780

V_IN= V_CC= 12V

75 100 125

V_IN= V_CC= 12V

-50

-25

0

25

50

-50

-25

0

25

50

75

100

125

Temperature ( C)

°

Temperature ( C)

°

Power On

Power Off

V_UGATE

(20V/Div)

V_UGATE

(20V/Div)

V_LGATE

(10V/Div)

V_LGATE

(10V/Div)

V_CC

(10V/Div)

V_CC

(10V/Div)

V_OUT

(1V/Div)

V_OUT

(1V/Div)

V_IN= V_CC= 12V, V_OUT= 1.05V, I_LOAD= 10A

Time (2.5ms/Div)

V_IN= V_CC= 12V, V_OUT= 1.05V, I_LOAD= 10A

Time (2.5ms/Div)

©

is a registered trademark of Richtek Technology Corporation.

www.richtek.com

8

DS8120-08 September 2013

RT8120

COMP/EN Power On

COMP/EN Power Off

V_UGATE

(20V/Div)

V_UGATE

(20V/Div)

V_LGATE

(10V/Div)

V_LGATE

(10V/Div)

V_COMP/EN

(2V/Div)

V_COMP/EN

(1V/Div)

V_OUT

(1V/Div)

V_OUT

(2V/Div)

V_IN= V_CC= 12V, V_OUT= 1.05V, I_LOAD= 10A

Time (500μs/Div)

Time (250μs/Div)

Load Transient Response

V_UGATE

(20V/Div)

V_UGATE

(20V/Div)

I_LOAD

(10A/Div)

I_LOAD

(10A/Div)

V_OUT

(50mV/Div)

V_OUT

(50mV/Div)

V_IN= V_CC= 12V, V_OUT= 1.05V,

I_LOAD= 0A to15A

V_IN= V_CC= 12V, V_OUT= 1.05V,

I_LOAD= 15A to 0A

Time (10μs/Div)

Over Current Protection

Under Voltage Protection

V_IN= V_CC= 12V, V_OUT= 1.05V

V_UGATE

(20V/Div)

V_UGATE

(10V/Div)

V_LGATE

(20V/Div)

V_LGATE

(10V/Div)

Inductor

Current

(20A/Div)

V_OUT

(1V/Div)

V_FB

(500mV/Div)

R_OCSET= 6.2kΩ

Low side MOSFET = IPD06N03 x 2

V_IN= V_CC= 12V, V_OUT= 1.05V, No Load

Time (2.5ms/Div)

Time (25μs/Div)

©

is a registered trademark of Richtek Technology Corporation.

DS8120-08 September 2013

www.richtek.com

9

RT8120

Application Information

initialization and soft-start cycle. This allows flexible power

sequence control for specified application. In practical

applications, connect a small-signal MOSFET to the

COMP/EN pin to implement the enable/disable function.

Function Description

The RT8120 is a single-phase synchronous buck PWM

controller with integrated N-MOSFET gate drivers. The

RT8120 can be used in a broad variety of applications,

with its wide input voltage range from 3V or 13.2V. It

provides single feedback loop, voltage mode control with

fast transient response. An internal 0.8V (option for 0.6V)

reference allows the output voltage to be precisely

regulated for low output voltage applications. A fixed

frequency (300kHz) oscillator is integrated to minimize

external components. Protection features include

programmable over current protection and Under Voltage

Lockout (UVLO).

VIN Detection (RT8120C/D Only)

Once VCC exceeds its power on reset (POR) rising

threshold voltage, UGATE will output continuous pulses

(~60kHz, 200ns), and LGATE will be forced low for

converter input voltage V_INdetection. If the voltage pulses

at the PHASE pin exceed 1V when UGATE is turned on,

V_INis recognized as ready. Then, the controller will initiate

soft-start operation.

Internal Soft-Start

Supply Voltage and Power On Reset (POR)

The RT8120 provides an internal soft-start function. The

soft-start function is used to prevent large inrush current

and output voltage overshoot while the converter is being

powered-up. The soft-start function automatically begins

once the chip is enabled. An internal current source

charges the internal soft-start capacitor such that the

internal soft-start voltage ramps up uniformly. The FB

voltage will track the internal soft-start voltage during the

soft-start interval. Therefore, the PWM pulse width

increases gradually to limit the input current. After the

internal soft-start voltage exceeds the reference voltage,

the FB voltage no longer tracks the soft-start voltage but

rather follows the reference voltage. Therefore, the duty

cycle of the UGATE signal as well as the input current at

power up are limited.

The input voltage range for VCC is from 4.5 V to 13.2 V

with respect toGND.An internal linear regulator regulates

the supply voltage for internal control logic circuit. A

minimum 0.1μF ceramic capacitor is recommended to

bypass the supply voltage. Place the bypassing capacitor

physically near the IC. VCC also supplies the integrated

MOSFET drivers. A bootstrap diode is embedded to

facilitate PCB design and reduce the total BOM cost. No

external Schottky diode is required in real applications.

The Power-On Reset (POR) circuit monitors the supply

voltage at the VCC pin. If VCC exceeds the POR rising

threshold voltage (typ. 4V), the controller resets and

prepares the PWM for operation. If VCC falls below the

POR falling threshold during normal operation, all

MOSFETs stop switching. The POR rising and falling

threshold has a hysteresis (typ.0.45V) to prevent

unintentional noise based reset.

Over Current Protection (OCP)

The RT8120 provides lossless over current protection by

detecting the voltage drop across the low side MOSFET

when it is turned on. The over current trip threshold is set

by an external resistor, R_OCSET, at LGATE.During the initial

stage when LGATE is turned on, the RT8120 samples

and holds the phase voltage. The sample-and-hold voltage

represents the valley inductor current and is compared to

the OCP threshold. If the sensed phase voltage is lower

than the OCP threshold, OCP will be triggered. Both

UGATE and LGATE will go low, and the controller will enter

the hiccup mode until the OCP condition is released.

Chip Enable and Disable

The COMP/EN pin of the RT8120 is a multiplexed pin.

During soft-start and normal converter operation, this pin

represents the output of the error amplifier. When COMP/

EN pin voltage falls or is pulled externally below the enable

level V_EN, the chip shuts down. When the controller shuts

down, UGATE and LGATE signals will go low. When the

pull-down device is released and the COMP/ENpin rises

above the V_ENtrip point, the RT8120 will begin a new

©

is a registered trademark of Richtek Technology Corporation.

www.richtek.com

10

DS8120-08 September 2013

RT8120

LGATE Over Current Setting (LGOCS)

MOSFET Drivers

Over current threshold is externally programmed by adding

a resistor (R_OCSET) between LGATE andGND. Once VCC

exceeds the POR threshold, an internal current source

I_OCSETflows through R_OCSET. The voltage across R_OCSETis

The RT8120 integrates high current gate drivers for the

twoN-MOSFETs to obtain high efficiency power conversion

in synchronous buck topology. A dead time is used to

prevent crossover conduction for the high side and low

side MOSFETs. Because both gate signals are off during

dead time, the inductor current freewheels through the

body diode of the low side MOSFET. The freewheeling

current and the forward voltage of the body diode contribute

to power loss. The RT8120 employs constant dead time

control scheme to ensure safe operation without

sacrificing efficiency. Furthermore, elaborate logic circuit

is implemented to prevent cross conduction.

stored as the over current protection threshold V_OCSET

.

After that, the current source is switched off. R_OCSETcan

be determined using the following equation :

I

x R

LGDS(ON)

VALLEY

R

=

OCSET

I

OCSET

where I_VALLEYrepresents the desired inductor OCP trip

current (valley inductor current).

If R_OCSETis not present, there is no current path for I_OCSET

to build the OCP threshold. In this situation, the OCP

threshold is internally preset to 375mV (typical).

For high output current applications, two or more power

MOSFETs are usually paralleled to reduce R_DS(ON). The

gate driver needs to provide more current to switch on/off

these paralleled MOSFETs.Gate driver with lower source/

sink current capability result in longer rising/ falling time

in gate signals, and therefore higher switching loss.

Under Voltage Protection (UVP)

The voltage on the FB pin is monitored for under voltage

protection. If the FB voltage is lower than the UVP threshold

(typically 75% x V_REF) during normal operation, UVP will

be triggered. When the UVP is triggered, both UGATE

and LGATE go low. The controller enters hiccup mode

until the UVP condition is removed.

The RT8120 embeds high current gate drivers to obtain

high efficiency power conversion. The embedded drivers

contribute to the majority of the power dissipation of the

controller. Therefore, SOP package is chosen for its power

dissipation rating. If no gate resistor is used, the power

dissipation of the controller can be approximately

calculated using the following equation :

Output Voltage Setting

The RT8120 allows the output voltage of the DC/DC

converter to be adjusted from 0.8V (option for 0.6V) to

85% of V_INvia an external resistor divider. It will try to

maintain the feedback pin at internal reference voltage

(0.8V, with option for 0.6V).

P_DRIVER= f_SWx (Q_Gx V_BOOT

+

Q_{G_LOW SIDE}x V_{DRIVER_LOW SIDE}

)

where V_BOOTrepresents the voltage across the bootstrap

capacitor and f_SWis the switching frequency.

V

OUT

It is important to ensure the package can dissipate the

switching loss and have enough room for safe operation.

R

FB1

FB2

FB

Inductor Selection

R

The inductor plays an importance role in step-down

converters because it stores the energy from the input

power rail and then releases the energy to the load. From

the viewpoint of efficiency, the dc resistance (DCR) of the

inductor should be as small as possible to minimize the

conduction loss. In addition, the inductor covers a

significant proportion of the board space, so its size is

also important. Low profile inductors can save board space

Figure 3. Output Voltage Setting

According to the resistor divider network above, the output

voltage is set as :

⎛

⎞

⎟

R_FB1

V_OUT= V_REFx 1 +

⎜

R_{FB2 ⎠}

⎝

©

is a registered trademark of Richtek Technology Corporation.

DS8120-08 September 2013

www.richtek.com

11

RT8120

especially when the height has a limitation. However, low

DCR and low profile inductors are usually cost ineffective.

ΔV_{OUT_ESR}= ΔI_Lx ESR

ΔV_{OUT_C}= ΔI_Lx

1

8 x C_OUTx f_SW

Additionally, larger inductance results in lower ripple

current, which translates into the lower power loss.

However, the inductor current rising time increases with

inductance value. This means the transient response will

be slower. Therefore, the inductor design is a trade-off

between performance, size and cost.

When load transient occurs, the output capacitor supplies

the load current before controller can respond. Therefore,

the ESR will dominate the output voltage sag during load

transient. The output voltage sag can be calculated using

the following equation :

V_{OUT_SAG}= ESR x ΔI_OUT

In general, inductance is chosen such that the ripple

current ranges between 20% to 40% of the full load current.

The inductance can be calculated using the following

equation :

For a given output voltage sag specification, the ESR value

can be determined.

Another parameter that has influence on the output voltage

sag is the equivalent series inductance (ESL). The rapid

change in load current results in di/dt during transient.

Therefore ESL contributes to part of the voltage sag. Using

a capacitor with low ESL will obtain better transient

performance. Generally, using several capacitors

connected in parallel will also have better transient

performance than just one single capacitor with the same

total ESR.

V

− V

V

IN

OUT

L

=

x

(MIN)

f

x k x I

V

IN

SW

OUT_RATED

where k is the ratio between inductor ripple current and

rated output current.

Input Capacitor Selection

Voltage rating and current rating are the key parameters

when selecting an input capacitor. Conservatively speaking,

an input capacitor should have a voltage rating 1.5 times

greater than the maximum input voltage to be considered

a safe design.

Unlike electrolytic capacitors, the ceramic capacitor has

relatively low ESR and can reduce the voltage deviation

during load transient. However, the ceramic capacitor can

only provide low capacitance value. Therefore, it is

suggested to use a mixed combination of electrolytic

capacitor and ceramic capacitor for achieving better

transient performance.

The input capacitor is used to supply the input RMS

current, which can be approximately calculated using the

following equation :

⎛

⎞

⎟

V_OUT

V

I_RMS= I_OUT

x

x 1 −

⎜

V

IN

⎝

^IN⎠

MOSFET Selection

The next step is to select a proper capacitor for the RMS

current rating. Using more than one capacitor with low

Equivalent Series Resistance (ESR) in parallel to form a

capacitor bank is a good design. Placing the ceramic

capacitor close to the drain of the high side MOSFET can

also be helpful in reducing the input voltage ripple at

heavy load.

The majority of power loss in the step-down power

conversion is due to the loss in the power MOSFETs. For

low voltage high current applications, the duty cycle of

the high side MOSFET is small. Therefore, the switching

loss of the high side MOSFET is of concern. Power

MOSFETs with lower total gate charge are preferred in

such kind of application. However, the small duty cycle

means the low side MOSFET is on for most of the switching

cycle. Therefore, the conduction loss tends to dominate

the total power loss of the converter. To improve the overall

efficiency, MOSFETs with low R_DS(ON)are preferred in the

circuit design. In some cases, more than one MOSFET

are connected in parallel to further decrease the on-state

Output Capacitor Selection

The output capacitor and the inductor form a low-pass filter

in the buck topology. In steady state condition, the ripple

current flowing into/out of the capacitor results in voltage

ripple. The output voltage ripples contains two

components, ΔV_{OUT_ESR}and ΔV_{OUT_C.}

©

is a registered trademark of Richtek Technology Corporation.

www.richtek.com

12

DS8120-08 September 2013

RT8120

resistance. However, this depends on the low side

MOSFET driver capability and the budget.

Figure 5 shows a typical buck control loop using a Type II

compensator. The control loop consists of the power stage,

PWM comparator and a compensator. The PWM

comparator compares V_COMPwith the oscillator (OSC)

sawtooth wave to provide a Pulse-Width Modulated (PWM)

with an amplitude of V_INat the PHASE node. The PWM

wave is smoothed by the output filter L_OUTand C_OUT. The

output voltage (V_OUT) is sensed and fed to the inverting

input of the error amplifier.

It is recommended to bypass low side MOSFET with a

snubber circuit (R = 1Ω, C = 3.3nF).

Compensation Network Design

The RT8120 is a voltage mode controller and requires

external compensation to have an accurate output voltage

regulation with fast transient response. The RT8120 uses

a high gain operational transconductance amplifier (EOTA)

as the error amplifier.As Figure 4 shows, the EOTAworks

as the voltage controlled current source. The calculation

The modulator transfer function is the small-signal transfer

function of V_OUT/V_COMP(output voltage over the error

amplifier output). This transfer function is dominated by a

DC gain, a double pole, and an ESR zero as shown in

Figure 6.

of the transconductance is shown below :

ΔI

ΔV_M

GM = ^OUT, where ΔV = V

−

V

IN−

(

)

(

)

M

IN+

and ΔV_COMP= ΔI_OUTx Z_OUT

V

+

-

I

IN+

OUT

GM

V

COMP

Z

OUT

V

IN-

Figure 4. Operational TransconductanceAmplifier, EOTA

V

IN

PWM

Comparator

UGATE

Q1

+

-

L

OUT

PAHSE

LGATE

Driver

Logic

V

OUT

C

OUT

ΔV_OSC

Q2

V

REF

+

R

FB1

GM

FB

-

R

FB2

COMP

V

COMP

C

P

C

R

C

Figure 5. Typical Voltage Mode Buck Converter Control Loop

©

is a registered trademark of Richtek Technology Corporation.

DS8120-08 September 2013

www.richtek.com

13

RT8120

80⁸⁰

To determine the 0dB crossing frequency (f_C, control loop

bandwidth) is the first step of compensator design. Usually,

the f_Cis set to 0.1 to 0.3 times the switching frequency.

The second step is to calculate the open loop modulator

gain and find out the gain loss at f_C. The third step is to

design a compensator gain that can compensate the

modulator gain loss at f_C. The final step is to design f_Z1

and f_P2to allow the loop sufficient phase margin. f_Z1is

designed to cancel one of the double poles of modulator.

Usually, place f_Z1before f_LC. f_P2is usually placed below

the switching frequency (typically, 0.5 to 1 times the

switching frequency) to cancel high frequency noise.

Loop Gain

60

f_P1

f_LC

f_Z1

40⁴⁰

Compensation

Gain

20

f_P2

0

Modulator

Gain

-20

f_ESR

-40

-60

10Hz

10

100Hz

1.0KHz

1k

10KHz

100KHz

100k

1.0MHz

1M

100

10k

vdb(vo) vdb(comp2) vdb(lo)

Frequency

Frequency (Hz)

Figure 6. Typical Bode Plot of a Voltage Mode Buck

Converter

Thermal Considerations

The DC gain of the modulator is the input voltage (V_IN)

For continuous operation, do not exceed absolute

maximum junction temperature. The maximum power

dissipation depends on the thermal resistance of the IC

package, PCB layout, rate of surrounding airflow, and

difference between junction and ambient temperature. The

maximum power dissipation can be calculated by the

following formula :

divided by the peak-to-peak oscillator voltage V_OSC

.

V

IN

Gain_MODULATOR

=

ΔV_OSC

The output LC filter introduces a double pole, 40dB/decade

gain slope above its corner resonant frequency, and a total

phase lag of 180 degrees. The resonant frequency of the

LC filter is expressed as :

1

P_D(MAX)= (T_J(MAX)− T_A) / θ_JA

f

=

LC

2π

L

x C

OUT OUT

Where T_J(MAX)is the maximum junction temperature, T_A

is the ambient temperature, and θ_JAis the junction to

ambient thermal resistance.

The ESR zero is contributed by the ESR associated with

the output capacitance. Note that this requires that the

output capacitor should have enough ESR to satisfy

stability requirements. The ESR zero of the output

capacitor is expressed as follows :

For recommended operating condition specifications, the

maximum junction temperature is 125°C. The junction to

ambient thermal resistance, θ_JA, is layout dependent. For

SOP-8 package, the thermal resistance, θ_JA, is 188°C/W

on a standard JEDEC 51-7 four-layer thermal test board.

For SOP-8 (Exposed Pad) package, the thermal

resistance, θ_JA, is 30.6°C/W on a standard JEDEC 51-7

four-layer thermal test board. The maximum power

dissipation at T_A= 25°C can be calculated by the following

formulas :

1

f_ESR

=

2π x C_OUTx ESR

The goal of the compensation network is to provide

adequate phase margin (usually greater than 45 degrees)

and the highest bandwidth (0dB crossing frequency). It is

also recommended to manipulate loop frequency response

that its gain crosses over 0dB at a slope of −20dB/dec.

According to Figure 6, the compensation network

frequency is as below :

P_D(MAX)= (125°C − 25°C ) / (188°C/W) = 0.53W for

SOP-8 package

f

= 0

P1

P_D(MAX)= (125°C − 25°C ) / (30.6°C/W) = 3.26W for

SOP-8 (Exposed Pad) package

1

f

=

P2

C

x C

p

⎛

⎜

⎝

⎞

⎟

⎠

C

2π x R

x

C

+ C

P

C

1

f

=

Z1

2π x R x C

C

©

is a registered trademark of Richtek Technology Corporation.

www.richtek.com

14

DS8120-08 September 2013

RT8120

The maximum power dissipation depends on operating

ambient temperature for fixed T_J(MAX)and thermal

resistance, θ_JA. The derating curves in Figure 7 allow the

designer to see the effect of rising ambient temperature

on the maximum power dissipation.

` Minimize the trace length between the power MOSFETs

and its drivers.

Since the drivers use short, high current pulses to drive

the power MOSFETs, the driving traces should be as

short and wide as possible to reduce the trace

inductance. This is especially true for the low side

MOSFET, since this can reduce the possibility of the

shoot through.

3.6

Four-Layer PCB

3.2

SOP-8 (Exposed Pad)

2.8

2.4

2.0

1.6

1.2

` Provide enough copper area around the power MOSFETs

and the inductors to aid in heat sinking. Using thick

copper PCB can also reduce the resistance and

inductance to improve efficiency.

0.8

` The bank of the output capacitor should be placed

physically close to the load. This can minimize the

impedance seen by the load and then improve the

transient response.

SOP-8

0.4

0.0

0

25

50

75

100

125

Ambient Temperature (°C)

` Placing all the high frequency decoupling ceramic

Figure 7. Derating Curve of Maximum PowerDissipation

capacitors close to their decoupling targets.

` Small-signal components should be located as close

as possible to the IC. The small signal components

include the feedback components, current sensing

components, compensation components, function

setting components and any bypass capacitors.

Layout Considerations

Layout planning plays a critical role in modern high-

frequency switching converter design. Circuit boards with

good layout can help the IC function properly and achieve

low losses, low switching noise, and stable operation with

improved performance. Without a good layout, the PCB

could radiate excessive noise, causing noise-induced IC

problems and converter instability. The following guidelines

is suggested have better IC performance.

These components belong to the high impedance circuit

loop and are inherently sensitive to noise pick-up.

Therefore, they must be located close to their respective

controller pins and away from the noisy switching nodes.

` A multi-layer PCB design is recommended. Make use

of one single layer as the power ground and have a

separate control signal ground as the reference of all

signals.

` The power components should be placed first. Keep the

connection between power components as short as

possible.

` Input bulk capacitors should be placed close to the drain

of the high side MOSFET and the source of the low

side MOSFET.

` Place the VCC bypass capacitor as close as possible to

the RT8120.

©

is a registered trademark of Richtek Technology Corporation.

DS8120-08 September 2013

www.richtek.com

15

RT8120

Outline Dimension

H

A

M

J

B

F

C

I

D

Dimensions In Millimeters

Dimensions In Inches

Symbol

Min

Max

Min

Max

A

B

C

D

F

H

I

4.801

3.810

1.346

0.330

1.194

0.170

0.050

5.791

0.400

5.004

3.988

1.753

0.508

1.346

0.254

6.200

1.270

0.189

0.150

0.053

0.013

0.047

0.007

0.002

0.228

0.016

0.197

0.157

0.069

0.020

0.053

0.010

0.244

0.050

J

M

8-Lead SOP Plastic Package

©

is a registered trademark of Richtek Technology Corporation.

www.richtek.com

16

DS8120-08 September 2013

RT8120

H

A

Y

M

EXPOSED THERMAL PAD

(Bottom of Package)

J

B

X

F

C

I

D

Dimensions In Millimeters Dimensions In Inches

Symbol

Min

Max

5.004

4.000

1.753

0.510

1.346

0.254

0.152

6.200

1.270

2.300

2.500

3.500

Min

Max

A

B

C

D

F

H

I

4.801

3.810

1.346

0.330

1.194

0.170

0.000

5.791

0.406

2.000

2.100

3.000

0.189

0.150

0.053

0.013

0.047

0.007

0.000

0.228

0.016

0.079

0.083

0.118

0.197

0.157

0.069

0.020

0.053

0.010

0.006

0.244

0.050

0.091

0.098

0.138

J

M

X

Y

X

Y

Option 1

Option 2

8-Lead SOP (Exposed Pad) Plastic Package

Richtek Technology Corporation

14F, No. 8, Tai Yuen 1^stStreet, Chupei City

Hsinchu, Taiwan, R.O.C.

Tel: (8863)5526789

Richtek products are sold by description only. Richtek reserves the right to change the circuitry and/or specifications without notice at any time. Customers should

obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. Richtek cannot

assume responsibility for use of any circuitry other than circuitry entirely embodied in a Richtek product. Information furnished by Richtek is believed to be

accurate and reliable. However, no responsibility is assumed by Richtek or its subsidiaries for its use; nor for any infringements of patents or other rights of third

parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Richtek or its subsidiaries.

DS8120-08 September 2013

www.richtek.com

17


型号：	RT8120A
厂家：	RICHTEK TECHNOLOGY CORPORATION
描述：	Single-Phase Synchronous Buck PWM Controller
文件：	总17页 (文件大小：223K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

RT8120A [RICHTEK]

相关型号：

RT8120B

RT8120D

RT8120E

RT8120F

RT8120G

RT8120H

RT8120J

RT8120K

RT8120_V01

RT8121

RT8122-10-6M0

RT8122-12-5M0