RT8127_技术文档

®

RT8127

High Efficiency Dual-Channel Output Synchronous Buck PWM

Controller with Phase Interleaving and Two LDO Regulators

General Description

Features

z Green Voltage Mode (GVM^TM) Control

The RT8127 is a high efficiency Dual-Channel output

synchronous Buck PWM controller with integrated

MOSFET drivers and two LDOs. This part featuresGreen

Voltage Mode (GVM^TM) control, which is specifically

designed to improve efficiency at light load condition. At

light load condition, the RT8127 is pin configurable to

automatically operate in diode emulation mode with

constant on-time PFM to reduce switching frequency so

as to improve conversion efficiency. As the load current

increases, the RT8127 leaves the diode emulation mode

and operates in Continuous Conduction Mode (CCM) with

fixed-frequency, 180° out of phase interleaved PWM to

reduce input capacitance. The RT8127 supports 4.5V to

26V input voltage range and has integrated 5V LDO which

supplies the internal gate drivers as well as the controller.

When channel 1 Buck regulator output voltage is higher

than 5V, the supply voltage will be automatically switched

to the Buck regulator output from the integrated 5V LDO.

The RT8127 supports enable/disable function for each

channel and also features external soft-start, adjustable

switching frequency and power good indication. This device

utilizes lossless inductor DCR current sensing for over

current protection. Other protections include over voltage,

under voltage, thermal shutdown and under voltage

lockout.

z High Light Load Efficiency

z Audio-Skip Mode (ASM) at Light Load

z Pin Configurable CCM/DEM Operation

z 180° Interleaving PWM in CCM Operation

z Support 4.5V to 26V Input Voltage Range

z Integrated 5V MOSFET Driver and Bootstrap Circuit

z Integrated 5V and 12V LDO

z Enable Control for Each Channel

z External/Internal Soft-Start

z Programmable LGATE PWM Frequency Setting

(LGFS)

z Automatic Switchable 5V Regulator

z Power Good Indication

z VIN Feed-Forward in Control Loop

z Lossless DCR Current Sensing

z OVP, UVP, OCP, Thermal Shutdown and UVLO

z Small 28-Lead WQFN Package

z RoHS Compliant and Halogen Free

Applications

z Motherboard, Server,Graphic Card

z System Power Supplies

z Power Module

Marking Information

The RT8127 is available in a WQFN-28L4x4 small footprint

package.

0H= : Product Code

YMDNN : Date Code

0H=YM

DNN

Simplified Application Circuit

V

IN

RT8127

V

IN

VIN

UGATE2

PHASE2

LGATE2

UGATE1

PHASE1

LGATE1

1.4µH

V

OUT2

V

OUT1

942µF

CSP2

CSN2

CSP1

CSN1

EN1/SS1

EN2/SS2

12VLDO

12V/3.3V

GND

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RT8127

Ordering Information

RT8127

Pin Configurations

(TOP VIEW)

Package Type

QW : WQFN-28L 4x4 (W-Type)

Lead Plating System

G : Green (Halogen Free and Pb Free)

28 27 26 25 24 23 22

Note :

1

2

3

4

5

6

7

21

20

19

18

17

16

15

UGATE2

BOOT2

PHASE2

LGATE2

PGND2

CSP2

UGATE1

BOOT1

PHASE1

LGATE1/RT

PGND1

CSP1

Richtek products are :

GND

` RoHS compliant and compatible with the current require-

ments of IPC/JEDEC J-STD-020.

29

CSN2

CSN1

` Suitable for use in SnPb or Pb-free soldering processes.

8

9 10 11 12 13 14

WQFN-28L 4x4

Functional Pin Description

Pin No.

Pin Name

Pin Function

Channel 2 High Side MOSFET Floating Gate Driver Output. Connect this pin to the

channel 2 high side MOSFET gate.

1

UGATE2

Channel 2 Bootstrap Flying Capacitor Connection Pin. This pin powers channel 2

high side MOSFET driver. Connect this pin to PHASE2 with a ceramic capacitor.

Channel 2 Switching Node Connection Pin. Connect this pin to the joint of high side

MOSFET source and low side MOSFET drain, and the inductor of channel 2.

2

3

4

BOOT2

PHASE2

LGATE2

Channel 2 Low Side MOSFET Gate Driver Output. Connect this pin to the gate of

channel 2 low side MOSFET.

Power Ground of Channel 2. This pin is the return ground of channel 2 low side

MOSFET gate driver. Connect this pin to the PCB ground plane layer with vias.

5

PGND2

6

7

CSP2

CSN2

Positive Current Sense Input for Channel 2.

Negative Current Sense Input for Channel 2.

Channel 2 Regulator Output Voltage Feedback Pin. This pin is the inverting input

node of the error amplifier.

8

9

FB2

COMP2

Channel 2 Regulator Compensation Pin. This pin is the output of the error amplifier.

Channel 2 Enable Pin. Pull this pin to ground to disable channel 2. This pin is

internally pulled high. Leave this pin unconnected to enable channel 2 with default

soft-start time. This pin can also be used for external soft-start interval setting.

Connect a ceramic capacitor to this pin to extend soft-start time.

The input voltage at EN2/SS2 pin must be higher than 2.97V to make sure soft-start

can be finished and PGOOD assertion.

10

11

12

EN2/SS2

PGOOD

EN1/SS1

Power Good Indicator Output. This pin has an open drain structure. Pull this pin high

to a voltage source with a resistor.

Channel 1 Enable Pin. Pull this pin to ground to disable channel 1. This pin is

internally pulled high. Leave this pin unconnected to enable channel 1 with default

soft-start time. This pin can also be used for external soft-start interval setting.

Connect a ceramic capacitor to this pin to extend soft-start time.

The input voltage at EN1/SS1 pin must be higher than 2.97V to make sure soft-start

can be finished and PGOOD assertion.

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DS8127-05 June 2014

RT8127

Pin No.

Pin Name

Pin Function

Channel 1 Regulator Compensation Pin. This pin is the output of the error

amplifier.

13

COMP1

Channel 1 Regulator Output Voltage Feedback Pin. This pin is the inverting

input node of the error amplifier.

14

FB1

15

16

CSN1

CSP1

Negative Current Sense Input for Channel 1.

Positive Current Sense Input for Channel 1.

Power Ground of Channel 1. This pin is the return ground of channel 1 low

side MOSFET gate driver. Connect this pin to the PCB ground plane layer

with vias.

17

18

19

PGND1

Channel 1 Low Side MOSFET Gate Driver Output. Connect this pin to the

gate of channel 1 low side MOSFET. This pin is also used to set the PWM

switching frequency in CCM. Connect a resistor from this pin to GND to set

the PWM switching frequency.

LGATE1/RT

PHASE1

Channel 1 Switching Node Connection Pin. Connect this pin to the joint of

high side MOSFET source and low side MOSFET drain, and the inductor of

channel 1.

Channel 1 Bootstrap Flying Capacitor Connection Pin. This pin powers

channel 1 high side MOSFET driver. Connect this pin to PHASE1 with a

ceramic capacitor.

20

21

22

BOOT1

UGATE1

VIN

Channel 1 High Side MOSFET Floating Gate Driver Output. Connect this pin

to the gate of channel 1 high side MOSFET.

IC Power Supply Input. Connect this pin to a voltage source with a bypass

ceramic capacitor connected to GND for noise decoupling. This pin is the

power source of the two integrated LDOs.

12V LDO Output. It is recommended to connect a minimum 1μF ceramic

capacitor from this pin to GND.

23

24

12VLDO

12VLDOEN

12V LDO Enable Pin. Logic-high at this pin enables the integrated 12V LDO.

CCM/DEM Programming Pin. Voltage at this pin determines the operation

mode in each channel.

Connect this pin to GND : both of the channels are set to automatic CCM/DEM

transition operation with audio-skip operation in DEM.

Connect this pin to VCC : both of the channels are set to CCM operation.

Leave this pin floating : channel 1 is set to automatic CCM/DEM transition

operation with audio-skip operation in DEM and channel 2 is set to CCM

operation.

25

SKIP

26

27

LDOEN

VCC

5V LDO Enable Pin. Logic-high at this pin enables the integrated 5V LDO.

Integrated 5V LDO Output. It is recommended to connect a minimum 4.7μF

ceramic capacitor between this pin and ground. VCC is the power supply for

the control circuit and MOSFET drivers.

5V LDO Bypass Input. Connect this pin to channel 1 regulator output (usually

5V). The LDOBYP pin voltage, V_LDOBYP, is monitored for controller supply

power swap. When V_LDOBYPis higher than the threshold, the controller will

automatically switch the chip power supply from 5V LDO to channel 1 output

and disable the 5V LDO for power saving.

28

LDOBYP

Return Ground of Controller. The exposed pad must be soldered to a large

PCB and connected to ground plane for maximum power dissipation.

29 (Exposed Pad) GND

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RT8127

Function Block Diagram

BOOT2

UGATE2

PHASE2

BOOT1

UGATE1

PHASE1

PWM

Controller

PWM

Controller

LGATE1/RT

PGND1

LGATE2

0 °

180 °

PGND2

12VLDO

12VLDOEN

OSC

GND

12VLDO

5VLDO

VIN

GVM CTL

V

TH_LDOBYP

Operation

The RT8127 is a dual output voltage mode synchronous

Buck controller with integrated MOSFET drivers and two

LDOs. The 12VLDO output also can be stepped down to

3.3V by the controlling of 12VLDOEN pin.

Over Current Protection (OCP)

The over current protection is triggered if the voltage

difference between CSPx and CSNx over 40mV for 16

switching cycles. Both UGATEx and LGATEx will go low

until VCC is resupplied and exceeds the POR rising

threshold voltage.

The controller has a fixed frequency control with 180° phase

shift in CCM. The fixed frequency can be adjusted from

typical 300kHz to 600kHz.

Over Voltage Protection (OVP)

The controller supports dynamic mode transition function

with three operating states : forced CCM,Diode Emulation

Mode (DEM) and audio skipping modes at light load.

If the FBx voltage is higher than the OVP threshold

(typically 120% x V_REF) during normal operation, OVP

will be triggered. When OVP is triggered, UGATEx goes

low and LGATEx is forced to high.

Enable

The recommended ON / OFF control can tie the ENx to

GND with a switch.

Under Voltage Protection (UVP)

If the FBx voltage is lower than the UVP threshold

(typically 50% x V_REF) during normal operation, UVP will

be triggered. When UVP is triggered, both UGATEx and

LGATEx go low until VCC is resupplied and exceeds the

POR rising threshold voltage.

Under Voltage Lockout (UVLO)

During normal operation, if the voltage at the VCC pin

drops below UVLO falling edge threshold. The VCC UVLO

circuitry inhibits switching by keeping UGATEx and

LGATEx low.

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DS8127-05 June 2014

RT8127

PGOOD

PGOOD is actively held low in soft-start, standby, and

shutdown conditions. It is released when both output

voltages of VFB1 and VFB2 are within 20% of the nominal

regulation point.

LDOBYP

When V_LDOBYPis higher than the threshold, the controller

will automatically switch the chip power supply from 5V

LDO to channel 1 output and disable the 5V LDO for power

saving.

Soft-Start

An internal current source charges the internal soft-start

capacitor such that the internal soft-start voltage ramps

up uniformly. The FB voltage will track the internal soft-

start voltage during the soft-start interval.

The RT8127 also provides an external soft-start function.

An additional capacitor connected at SSx pin will be

charged by a 10μA current source and determines the

soft-start time.

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RT8127

Absolute Maximum Ratings (Note 1)

z Supply Voltage, VIN --------------------------------------------------------------------------------- −0.3V to 30V

z VCC, PVCC, LDOBYP------------------------------------------------------------------------------ −0.3V to 6V

z PGOOD ------------------------------------------------------------------------------------------------- −0.3V to 6V

z LDOEN -------------------------------------------------------------------------------------------------- −0.3V to 30V

z BOOT to PHASE ------------------------------------------------------------------------------------- −0.3V to 6V

z PHASE to GND

DC-------------------------------------------------------------------------------------------------------- −0.7V to (V_IN+ 0.3V)

<20ns --------------------------------------------------------------------------------------------------- −5V to 30V

<10ns --------------------------------------------------------------------------------------------------- −10V to 30V

<5ns ----------------------------------------------------------------------------------------------------- −15V to 30V

z UGATE toGND

DC-------------------------------------------------------------------------------------------------------- (V_PHASE− 0.3V) to (V_BOOT+ 0.3V)

<20ns --------------------------------------------------------------------------------------------------- (V_PHASE− 5V) to (V_BOOT+ 5V)

z LGATE toGND

DC-------------------------------------------------------------------------------------------------------- (GND − 0.3V) to (VCC + 0.3V)

<20ns --------------------------------------------------------------------------------------------------- (GND − 5V) to (VCC + 5V)

z Other Pins---------------------------------------------------------------------------------------------- (GND − 0.3V) to 6V

z Power Dissipation, P_D@ T_A= 25°C

WQFN-28L 4x4 --------------------------------------------------------------------------------------- 1.923W

z Package Thermal Resistance (Note 2)

WQFN-28L 4x4, θ_JA---------------------------------------------------------------------------------- 52°C/W

WQFN-28L 4x4, θ_JC^{---------------------------------------------------------------------------------------------------------------------}7°C/W

z Junction Temperature -------------------------------------------------------------------------------- 150°C

z Lead Temperature (Soldering, 10 sec.)---------------------------------------------------------- 260°C

z Storage Temperature Range ----------------------------------------------------------------------- −65°C to 150°C

z ESD Susceptibility (Note 3)

HBM (Human Body Model)------------------------------------------------------------------------- 2kV

Recommended Operating Conditions (Note 4)

z Supply Voltage, VIN --------------------------------------------------------------------------------- 4.5V to 26V

z Junction Temperature Range----------------------------------------------------------------------- −40°C to 125°C

z Ambient Temperature Range----------------------------------------------------------------------- −40°C to 85°C

Electrical Characteristics

(V_IN= 12V, V_CC= 5V, T_A= 25°C, unless otherwise specified)

Parameter

General

Symbol

Test Conditions

Min

Typ Max Unit

VIN Supply Voltage

VIN Supply Current

VCC Power On Reset

VCC POR Hysteresis

V_IN

4.5

--

12

2

26

--

V

mA

V

I_VIN

V_POR

ΔV_POR

--

4.2

0.3

--

V

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DS8127-05 June 2014

RT8127

Parameter

Symbol

Test Conditions

Min Typ Max Unit

EN1, EN2, LDOEN, 12VLDOEN = 0V

--

5

Shutdown Current

I

μA

VIN_SHDN

EN1, EN2, LDOEN = 0V,

12VLDOEN = 5V / 2.5V

--

100

150

EN1, EN2 = 0V, LDOEN = 5V,

12VLDOEN = 5V / 2.5V

EN1, EN2 = 0V, LDOEN = 5V,

12VLDOEN = 0V

--

350

300

400

350

Standby Current

VIN_SBY

5V LDO

Output Voltage

Regulation

V

= 12V, Load Current = 100mA

4.9

60

5

5.15

--

V

CC

IN

Current Capability

LDOBYP

I

--

mA

VCC_SRC

LDOBYP Threshold

LDOBYP Hysteresis

V

4.8

--

4.9

0.1

5

V

TH_LDOBYP

ΔV

0.25

TH_LDOBYP

LDOBYP Internal Switch

On-Resistance

R

--

1

Ω

LDOBYP

12V LDO

Source Current Capability I

10

--

mA

V

12VLDO

Voltage Regulation for

12V Output

V

= 15V, Load Current = 10mA

11.4

12

12.6

12VLDO

3.3VLDO

IN

Voltage Regulation for

3.3V Output

V

3.1

3.3

3.5

V

Enable Control

EN1/EN2 Threshold

EN1/EN2 Hysteresis

LDOEN Threshold

LDOEN Hysteresis

V

0.58 0.68 0.78

V

mV

V

EN

ΔV

--

1.4

--

78

1.6

0.2

--

1.8

--

EN

V

TH_LDOEN

ΔV

V

TH_LDOEN

12VLDOEN Input for 3.3V

Output

V

12VLDO Output = 3.3V

12VLDO Output = 12V

2

2.5

3

V

TH_12VLDOEN_3.3V

12VLDOEN Input for 12V

Output

V

4.5

--

5

5.5

0.4

V

TH_12VLDOEN_12V

TH_12VLDOEN

12VLDOEN Disable

PGOOD

--

PGOOD Threshold

Error Amplifier

Open Loop Gain

Gain Bandwidth

Slew Rate

V

With Respect to V

80

--

120

%

PGOOD

OL

REF

A

(Note 5)

--

80

15

2

--

dB

GBW

SR

MHz

V/μs

COMP Pin to GND with 10pF

Reference Voltage

V

792

800

808

mV

REF

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RT8127

Parameter

Symbol

Test Conditions

Min

Typ Max Unit

PWM Controller

R

= 1.8k

255

297

340

510

80

300

350

400

600

--

345

402

460

690

--

LGFS

= 4.7k

= 9.1k

= 16k

Switching Frequency

f

kHz

SW

Maximum Duty Cycle

Ramp Amplitude

D

%

V

MAX

ΔV

V

= 12V

IN

--

2.4

0.8

180

--

OSC

Ramp Valley

V

--

V

RAMPOFS

PWM Clock Interleaving

MOSFET Driver

CCM Operation

(Note 5)

--

Deg

UGATE Driver Source

UGATE Driver Sink

LGATE Driver Source

LGATE Driver Sink

R

V

− V = 5V

PHASE

--

2.5

1.5

2

--

Ω

UGATEsr

UGATEsk

LGATEsr

LGATEsk

BOOT

1

Deadtime between UGATE Off

and LGATE On

Deadtime between LGATE Off

and UGATE On

CCM Operation

Current = 10mA

--

40

20

--

ns

V

Embedded Bootstrap Diode

Voltage Drop

V

0.8

DROP

Soft-Start

Internal Soft-Start Time

t

6

9

--

ms

SS

Enabled when EN = L, measure

CSN1/CSN2 resistance

Soft-Stop Resistance

R

--

80

Ω

PL

SKIP Pin

Logic-High

SKIP Input

V

CH1 and CH2 : CCM

3.6

--

IH

IL

V

Threshold Voltage

Logic-Low

CH1 and CH2 : Automatic CCM/DEM

1.4

Audio Skip Mode PWM

Frequency

f

--

30

--

kHz

SW_ASM

Protection

Over Voltage Protection

Under Voltage Protection

UVP Delay

V

After VCC POR, with Respect to V

110

--

120

50

2

130

--

%

OVP

UVP

REF

After Soft-Start, with Respect to V

REF

t

1.4

35

--

ms

mV

D_UVP

OCP Threshold Voltage

V

Measure V

− V

40

45

OCP

SCP

ISP

ISN

Short Circuit OCP Threshold

Voltage

V

--

60

--

mV

Thermal Shutdown Temperature T

--

150

40

--

°C

SD

Thermal Shutdown Hysteresis

ΔT

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RT8127

Note 1. Stresses beyond those listed “Absolute Maximum Ratings” may cause permanent damage to the device. These are

stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in

the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions may

affect device reliability.

Note 2. θ_JAis measured at T_A= 25°C on a high effective thermal conductivity four-layer test board per JEDEC 51-7. θ_JCis

measured at the exposed pad of the package.

Note 3. Devices are ESD sensitive. Handling precaution is recommended.

Note 4. The device is not guaranteed to function outside its operating conditions.

Note 5. Guaranteed by design.

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RT8127

Typical Application Circuit

V

IN

C1

270µF

C2

0.1µF

R29

10

RT8127

BOOT1

R1

0.5

20

21

C5

22

VIN

0.1µF

C14

1µF

R2

0.5

R15

10k

NTMFS4

921NT1G

R17

30k

V

UGATE1

OUT1

5V

26

L1

1.4µH

Q1

Q2

LDOEN

19

18

PHASE1

24

C4

C3

12VLDOEN

LGATE1/RT

NTMFS4

936NT1G

optional

R

NTC1

R3

2.2

10k

R16

6.8k 11k

R18

22µF

940µF

NC

R5

C7

2.2nF

R

1.8k

LGFS

R19

R6 10k

0.1µF

0

2

1

BOOT2

C16

C6

C17

R4 68k

16

15

C15

0.1µF

CSP1

CSN1

10µF

270µF

Q3

V

OUT2

3.3V

UGATE2

R7

C8

0.1µF

NTMFS4

921NT1G

C11

820

R20

C9 120pF

6.8nF

L2

0

1.4µH

3

4

13

14

COMP1

FB1

PHASE2

LGATE2

R9

C10

6.2k

R8 27k

1nF

optional

R

NTC2

10k

R21

2.2

Q4

C21

22µF

R14

1.2k

NC

NTMFS4

936NT1G

C18

2.2nF

R13

10

R22 R23

10k

28

27

C20

LDOBYP

VCC

0.8k

R24

C12

0.1µF

6

7

C19 0.1µF

940µF

CSP2

CSN2

C13

4.7µF

R10

30k

C25

6.8nF

C23

120pF

11

25

R25 820

C24

C22

0.1µF

PGOOD

R28

27k

R26

9

8

R11

COMP2

FB2

0

6.2k

1nF

SKIP

R27

1.96k

R12

NC

5

PGND2

PGND1

12

10

EN1/SS1

EN2/SS2

17

Q5

Q6

C26

NC

CH1 Enable

CH2 Enable

23

12VLDO

GND

12V/3.3V

29 (Exposed Pad)

C27

NC

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RT8127

Typical Operating Characteristics

Efficiency vs. Load Current

100

90

80

70

60

50

40

30

20

10

0

100

V_IN= 12V, V_CC= 5V, V_OUT= 5V,

EN1 = EN2 = 12VLDOEN

= LDOEN = ON

80

V_IN= 19V, V_CC= 5V, V_OUT= 5V,

EN1 = EN2 = 12VLDOEN

= LDOEN = ON

90

70

60

AUTO SKIP

FCCM

50

40

30

20

10

0

0.001

0.01

0.1

1

10

100

0.001

0.01

0.1

1

10

100

Load Current (A)

Efficiency vs. Load Current

100

90

80

70

60

50

40

30

20

10

0

100

90

80

70

60

50

40

30

20

10

0

V_IN= 24V, V_CC= 5V, V_OUT= 5V,

EN1 = EN2 = 12VLDOEN

= LDOEN = ON

V_IN= 12V, V_CC= 5V, V_OUT= 3.3V,

EN1 = EN2 = 12VLDOEN

= LDOEN = ON

AUTO SKIP

FCCM

0.001

0.01

0.1

1

10

0.001

0.01

0.1

1

10

100

Load Current (A)

Efficiency vs. Load Current

100

90

80

70

60

50

40

30

20

10

0

100

90

80

70

60

50

40

30

20

10

0

V_IN= 19V, V_CC= 5V, V_OUT= 3.3V,

EN1 = EN2 = 12VLDOEN

= LDOEN = ON

V_IN= 24V, V_CC= 5V, V_OUT= 3.3V,

EN1 = EN2 = 12VLDOEN

= LDOEN = ON

AUTO SKIP

FCCM

0.001

0.01

0.1

1

10

0.001

0.01

0.1

1

10

100

Load Current (A)

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RT8127

Shutdown Response

Power Up

V_OUT1

(5V/Div)

PGOOD

(5V/Div)

PGOOD

(5V/Div)

EN1

(5V/Div)

UGATE1

(10V/Div)

UGATE1

(10V/Div)

V_IN= 12V, V_CC= 5V

Time (10ms/Div)

Time (1ms/Div)

VOUT1 Load Transient Response

VOUT2 Load Transient Response

V_OUT2

V_OUT1

(50mV/Div)

Inductor

Current

(10A/Div)

Inductor

Current

(10A/Div)

LGATE2

(10V/Div)

LGATE1

(10V/Div)

UGATE2

(20V/Div)

UGATE1

(20V/Div)

V_IN= 12V, V_CC= 5V, V_OUT= 3.3V, Load = 0 to 5A

V_IN= 12V, V_CC= 5V, V_OUT= 5V, Load = 0 to 5A

Time (100μs/Div)

OCP

Shorted Start Up

V_OUT2

(1V/Div)

V_OUT1

(5V/Div)

Inductor

Current

(20A/Div)

Inductor

Current

(20A/Div)

LGATE2

(5V/Div)

LGATE1

(5V/Div)

UGATE1

(20V/Div)

UGATE2

(10V/Div)

V_IN= 12V, V_CC= 5V

Time (10μs/Div)

Time (200μs/Div)

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DS8127-05 June 2014

RT8127

OVP

UVP

V_OUT1

(2V/Div)

FB2

(500mV/Div)

PGOOD

Inductor

Current

(5A/Div)

(5V/Div)

LGATE1

(5V/Div)

LGATE2

(5V/Div)

UGATE1

(10V/Div)

UGATE2

(10V/Div)

V_IN= 12V, V_CC= 5V

Time (50μs/Div)

Time (10μs/Div)

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RT8127

Application Information

The RT8127 is a dual output voltage mode synchronous

Buck controller with integrated MOSFET drivers and two

LDOs. It is suited to 5V/3.3V low voltage power supplies

with demanding high efficiency and fast transient response,

such as graphic card and motherboard. The internal linear

regulators named 5VLDO and 12VLDO respectively

provides 5V and 12V outputs. The internal circuitry and

gate drivers can be supplied by the 5VLDO or the output

of 5V channel. When the output voltage of 5V channel is

above 4.85V, the 5VLDO will be turned off and the device

is supplied by the output of 5V channel.

inductor free wheeling current becomes negative. As the

load current is further decreased, it takes longer and longer

time to discharge the output capacitor to the level that

requires the next “ON” cycle. In reverse, when the output

current increases from light load to heavy load, the

switching frequency increases to the preset value as the

inductor current reaches the continuous conduction.

The transition load point to the light load operation is shown

in Figure 1 and can be calculated as follows :

I

L

Slope = (V - V

) / L

IN

OUT

I

L, peak

The RT8127 supports dynamic mode transition function

with three operating states: forced CCM,Diode Emulation

Mode (DEM) and audio skipping modes at light load. These

different operating states improve the system efficiency

as high as possible. The RT8127 has a fixed frequency

control with 180°phase shift in CCM. The fixed frequency

can be adjusted from typical 300kHz to 600kHz by the

I

= I

/ 2

Load

L, peak

0

t

ON

external resistor R_LGFS

.

Figure 1. Boundary of Inductor current betweenDEM

and CCM

Operation Mode Selection

V

− V

OUT

2L

(

)

× t

IN

The SKIP pin is used to select the operation mode. When

the SKIP pin is tied to VCC, both of the channels operate

in forced-CCM mode. When the SKIP pin is connected to

GND, both of the channels operate in automatic CCM/

DEM and transition operation with audio-skip mode inDEM.

When the SKIP pin is floating, channel 1 operates in

automatic CCM/DEM and transition operation with audio-

skip mode inDEM, and channel 2 operates in forced-CCM

mode.

I

≈

Load (SKIP)

ON

where t_ONis the on-time.

Audio Skip Mode

The RT8127 activates a unique type of Diode Emulation

Mode with a minimum switching frequency of 30kHz,

called Audio Skip Mode. This mode eliminates audio-

frequency modulation that would otherwise be present

when a lightly loaded controller automatically skips

pulses. In Audio Skip Mode, the low side switch gate

driver signal is “OR”ed with an internal oscillator

(>30kHz). Once the internal oscillator is triggered, the

ultrasonic controller pulls LGATEx high and turns on the

low side MOSFET to induce a negative inductor current.

After the output voltage falls below the reference voltage,

the controller turns off the low side MOSFET (LGATEx

pulled low) and triggers a constant on-time (UGATEx driven

high). When the on-time has expired, the controller re-

enables the low side MOSFET until the controller detects

that the inductor current dropped below the zero crossing

threshold.

Diode-Emulation Mode

In Diode Emulation Mode, the RT8127 automatically

reduces switching frequency at light load conditions to

maintain high efficiency. This reduction of frequency is

achieved smoothly. As the output current decreases from

heavy-load condition, the inductor current is also reduced,

and eventually comes to the point that its current valley

touches zero, which is the boundary between continuous

conduction and discontinuous conduction modes. By

emulating the behavior of diodes, the low side MOSFET

allows only partial negative current to flow when the

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DS8127-05 June 2014

RT8127

Forced-CCM Mode

start function will be chosen. The external soft-start

sequence is shown in Figure 2. During soft-start period,

the FB voltage will track the reference voltage V_REFwhich

slew rate is according to the slew rate of the ENx pin

voltage.During shut down period, the FB voltage also tracks

reference voltage which slew rate is according to the ENx

pin voltage.

The low noise, forced-CCM mode (SKIP = VCC) disables

the zero-crossing comparator, which controls the low side

switch on-time. This causes the low side gate-driver

waveform to become the complement of the high side

gate-driver waveform. This in turn causes the inductor

current to reverse at light loads as the PWM loop strives

to maintain a duty ratio of VOUT/VIN. The benefit of forced-

CCM mode is to keep the switching frequency fairly

constant, but it comes at a cost : The no-load current will

slightly increase, depending on the external MOSFET(s),

reference and linear regulators.

In order to prevent LGATEx turn on for a long time to induce

violent inductor current in shutdown interval, the falling

slew rate of the ENx pin voltage should not slower than

1V/μs and the recommended inductor should be higher

than 1μH.

The recommended ON / OFF control is to connect the

ENx to GND with a MOSFET. If the external source is

directly connected to the ENx pin to control ON / OFF,

the external source must be higher than 2.97V to make

sure soft-start can be finished and PGOOD assertion.

MOSFET Gate Driver

The high side driver is designed to drive high current, low

R_DS(on) N-MOSFET(s). When configured as a floating

driver, 5V bias voltage is delivered from 5VLDO supply.

The average drive current is also calculated by the gate

charge at V_GS= 5V times switching frequency. The

instantaneous drive current is supplied by the flying

capacitor between BOOTx and PHASEx pins.Adead time

to prevent shoot through is internally generated between

high side MOSFET off to low side MOSFET on, and low

side MOSFET off to high side MOSFET on. The low side

driver is designed to drive high current low R_DS(on)

N-MOSFET(s). The internal pull-down transistor that drives

LGATEx low is robust, with a 0.6Ω typical on resistance.

A 5V bias voltage is delivered from 5VLDO supply. For

high current applications, some combinations of high and

low side MOSFET(s) may cause excessive gate-drain

coupling, which can lead to efficiency-killing and EMI

producing shoot-through currents. This is often remedied

by adding a resistor in series with BOOTx, which increases

the turn-on time of the high side MOSFET without degrading

the turn-off time.

When LDOEN is Low, both VOUT1 and VOUT2 will shut

down even though EN1 or EN2 are ON state. When LDOEN

is ON state, VOUT1 and VOUT2 are controlled

independently by EN1 and EN2. The 12VLDO stays alive

only consider if 12VLDOEN is ON state.

2.97

1.6

0.8

EN shutdown

threshold

ENx

0

0.8

V

Slew rate is controlled

by ENx pin voltage

REF

V

REF

0

SSOK

PGOOD

UGATEx

LGATEx

FCCM

Enable

UGATEx

LGATEx

DEM

with

ASM

The RT8127 provides external soft-start function and

enables control through the ENx pin.

Soft-Start

Ultrasonic Mode

(Load Current Dependent)

The internal soft-start function or external soft-start function

will be chosen according to the slew rate of the ENx pin

voltage. If the slew rate of ENx pin voltage is slower than

the slew rate of internal soft-start ramp, the external soft-

Figure 2. External Soft-Start Sequence

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15

RT8127

Table1. Enable Logic States

12VLDOEN

5VLDOEN

EN1

EN2

12VLDO 5VLDO

VOUT1

OFF

ON

VOUT2

OFF

ON

L

X(don’t care)

OFF

ON

H

X(don’t care)

ON

L/H

H

L

H

L

OFF/ON

ON

H

ON

OFF

ON

H

ON

Soft-Start

Supply Voltage and Power On Reset (POR)

The RT8127 provides an internal soft-start function. The

soft-start function is used to prevent large inrush current

and output voltage overshoot while the converter is being

powered up. The soft-start function automatically begins

once the chip is enabled. An internal current source

charges the internal soft-start capacitor such that the

internal soft-start voltage ramps up uniformly. The FB

voltage will track the internal soft-start voltage during the

soft-start interval. The PWM pulse width increases

gradually to limit the input current. After the internal soft-

start voltage exceeds the reference voltage, the FB voltage

no longer tracks the soft-start voltage but rather follows

the reference voltage. Therefore, the duty cycle of the

UGATE signal as well as the input current at power up are

limited.

VCC is the power supply for the control circuit and

MOSFET driver. An internal linear regulator regulates the

supply voltage for internal control logic circuit. Aminimum

0.1μF ceramic capacitor is recommended to bypass the

supply voltage. Place the bypassing capacitor physically

near the IC. VCC also supplies the integrated MOSFET

drivers. A bootstrap diode is embedded to facilitate PCB

design and reduce the total BOM cost. No external

Schottky diode is required in real applications. The Power

On Reset (POR) circuit monitors the supply voltage at

the VCC pin. If VCC exceeds the POR rising threshold

voltage (typ. 4.2V), the controller resets and prepares the

PWM for operation. If VCC falls below the POR falling

threshold during normal operation, all MOSFET(s) stop

switching. The POR rising and falling threshold has a

hysteresis (typ. 0.3V) to prevent unintentional noise based

reset.

The RT8127 also provides a proximate external soft-start

function shown in Figure 3. An additional capacitor

connected from ENx/SSx pin to the GND will be charged

by a 10μA current source and determines the soft-start

time.

Low Dropout Regulators (LDOx)

The RT8127 includes 5V and 12V low dropout regulators.

The 5V regulator can supply up to 60mAfor external loads.

Bypass LDOx with a minimum 1μF ceramic capacitor.

When the output voltage of 5V channel is higher than the

switch over threshold (4.85V), an internal 1Ω P-MOSFET

switch connects LDOBYP to the 5VLDO pin while

simultaneously disconnects the internal linear regulator.

ΔV

ENx

VOUTx

Soft-Start time

The 12VLDO output can be stepped down to 3.3V by

connecting 12VLDOEN pin to 2V to 3V.

Figure 3. External Soft-Start

The soft-start time can be calculated as :

C×ΔV

I

SS

(

)

Under Voltage Lockout (UVLO)

t

=

SS

During normal operation, if the voltage at the VCC pin

drops below UVLO falling edge threshold.

Where, I_SS= 10μA, ΔV = 1V, and C is the external capacitor

placed from ENx/SSx to GND. The recommend C is

0.15μF to 0.2μF.

The VCC Under Voltage Lockout (UVLO) circuitry inhibits

switching by keeping UGATEx and LGATEx low.

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DS8127-05 June 2014

RT8127

Power Good Output (PGOOD)

delay and latched. Also to prevent false triggering, the

SCP threshold is designed to be 1.5 times of OCP

threshold.

PGOOD is an open-drain output and requires a pull up

resistor. PGOODis actively held low in soft-start, standby,

and shutdown. It is released when both output voltages

are within 20% of the nominal regulation point for RT8127.

The over current threshold of inductor peak current (I_{LPK_OC}

)

and load current (I_{LOAD_OC}) can be calculated by the

following equations :

The PGOOD delay time is from FB exceeding 80% of

VREF to PGOOD rising high, the delay time is around 3

times the soft-start time t_SS.

V_{X_OC}

DCR

R_X+R_Y

I_{LPK_OC}

=

×

R_Y

Where V_{X_OC}= 40mV

V − V

× V

OUT

Current Sensing

(

−

LPK_OC

)

IN

OUT

I

= I

LOAD_OC

2×L × V ×f

X

IN SW

The CSPx and CSNx denote the positive and negative

input of the current sense amplifier. Users can either use

a current sense resistor or the inductor'sDCR for current

sensing. Using inductor's DCR allows higher efficiency

as shown in Figure 4.

Over Voltage Protection (OVP)

The voltage on the FBx pin is monitored for over voltage

protection. If the FBx voltage is higher than the OVP

threshold (typically 120% x V_REF) during normal operation,

OVP will be triggered. When OVP is triggered, UGATEx

goes low and LGATEx is forced high. The controller is

latched until VCC is resupplied and exceeds the POR

rising threshold voltage.

V

IN

V

OUT

Lx DCR

PHASEx

I

L

R

X

R

C

Y

X

CSPx

CSNx

+ V -

X

Under Voltage Protection (UVP)

The voltage on the FBx pin is also monitored for under

voltage protection. If the FBx voltage is lower than the

UVP threshold (typically 50% x V_REF) during normal

operation, UVP will be triggered. When UVP is triggered,

both UGATEx and LGATEx go low until VCC is resupplied

and exceeds the POR rising threshold voltage.

Figure 4. Lossless Inductor Sensing

The sensing voltage V_Xcan be set as :

R

Y

V

=

×I ×DCR

L

X

R +R

X

Y

Then the value of R_X, R_Yand C_Xcan be calculated as :

L_X

DCR

= R // R_Y×C

(

)

X

Output Voltage Setting

Over Current Protection

The RT8127 allows the output voltage of the DC/DC

converter to be adjusted from 0.8V to 80% of VIN via an

external resistor divider as shown in Figure 5. It will try to

maintain the feedback pin at internal reference voltage.

The Over Current Protection (OCP) of RT8127 is detected

from the inductor current sensing for good accuracy.

Therefore, the controller can be less noise sensitive. The

over current protection is triggered if the voltage difference

between CSPx and CSNx exceeds 40mV for continuous

16 switching cycles. Once the OCP is triggered, both of

the UGATE and LGATE will go low until VCC is resupplied

and exceeds the POR rising threshold voltage.

V

OUT

R

FB1

FB2

FB

R

Except the OCP function described above, the controller

provides Short Circuit Protection (SCP) function. Since

short circuit may cause catastrophic damage over a very

short period, the SCP should be triggered with a very short

Figure 5. Output Voltage Setting

The output voltage can be set according to :

R_FB1

R_FB2

⎛

⎝

⎞

⎟

⎠

V_OUT= V_REF× 1 +

⎜

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RT8127

Output Inductor Selection

For a given output voltage sag specification, the ESR value

can be determined.Another parameter that has influence

on the output voltage sag is the equivalent series

inductance (ESL). The rapid change in load current results

in di/dt during transient. Therefore ESL contributes to part

of the voltage sag. Using a capacitor with low ESL will

obtain better transient performance. Generally, using

several capacitors connected in parallel will also have better

transient performance than just one single capacitor with

the same total ESR. Unlike electrolytic capacitors, the

ceramic capacitor has relatively low ESR and can reduce

the voltage deviation during load transient. However, the

ceramic capacitor can only provide low capacitance value.

Therefore, it is suggested to use a mixed combination of

electrolytic capacitor and ceramic capacitor for achieving

better transient performance.

Inductor plays an important role in the Buck converter

because the energy from the input power rail is stored in

it and then released to the load. From the viewpoint of

efficiency, the DC Resistance (DCR) of inductor should

be as small as possible because inductor carries current

all the time. Using inductor that has lowerDCR can obtain

higher efficiency. In addition, because inductor takes most

of the board space, its size is also important. Low profile

inductors can save board space especially when the height

has limitation. Additionally, larger inductance results in

lower ripple current, and therefore the lower power loss.

However, the inductor current rising time increases with

inductance value. This means the inductor will have a

longer charging time before its current reaches the required

output current. Since the response time is increased, the

transient response performance will be decreased.

Therefore, the inductor design is a trade-off between

performance, size and cost. In general, inductance is

designed such that the ripple current ranges between 20%

to 30% of full load current. The inductance can be

calculated by using the following equation :

MOSFET Selection

The majority of power loss in the step-down power

conversion is due to the loss in the power MOSFET(s).

For low voltage high current applications, the duty cycle

of the high side MOSFET is small. Therefore, the switching

loss of the high side MOSFET is of concern. Power

MOSFET(s) with lower total gate charge are preferred in

such kind of application. However, the small duty cycle

means the low side MOSFET is on for most of the switching

cycle. Therefore, the conduction loss tends to dominate

the total power loss of the converter. To improve the overall

efficiency, MOSFET(s) with low R_DS(ON)are preferred in

the circuit design. In some cases, more than one MOSFET

are connected in parallel to further decrease the on-state

resistance. However, this depends on the low side

MOSFET driver capability and the budget.

V

_IN− V_OUT

V_OUT

V

IN

L_(MIN)

=

×

F_SW×k×I_{OUT_FullLoad}

where k is 0.2 to 0.3.

Output Capacitor Selection

The output capacitor and the inductor form a low-pass filter

in the Buck topology. In steady state condition, the ripple

current flowing into/out of the capacitor results in voltage

ripple. The output voltage ripples contains two parts,

ΔV_{OUT_ESR}and ΔV_{OUT_C}

.

ΔV_{OUT_ESR}= ΔI_L×ESR

1

Compensation Network Design

ΔV_{OUT_C}= ΔI_L×

8×C_OUT×f_SW

The RT8127 is a voltage mode synchronous Buck

controller. To compensate a typical voltage mode Buck

converter, there are two ordinary compensation schemes,

well known as type-II compensator and type-III

compensator. The choice of using type-II or type-III

compensator will be up to platform designers, and the

main concern will be the position of the capacitor ESR

zero and mid-frequency to high frequency gain boost.

Typically, the ESR zero of output capacitor will tend to

When load transient occurs, the output capacitor supplies

the load current before controller can respond. Therefore,

the ESR will dominate the output voltage sag during load

transient. The output voltage sag can be calculated by

using the following equation :

V_{OUT_SAG}= ESR x ΔI_OUT

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RT8127

stabilize the effect of output LC double poles, hence the

position of the output capacitor ESR zero in frequency

domain may influence the design of voltage loop

compensation. If f_Z(ESR)is <1/2f_C, where f_Cdenotes 0dB

crossing frequency, type-II compensation will be sufficient

for voltage stability. If f_Z(ESR)is > 1/2f_C(or higher gain and

phase margin is required at mid frequency to high

frequency), then type-III compensation may be a better

solution for voltage loop compensation.

the frequencies of poles and zero are :

1

f

Z1

=

2π ×R2×C1

f

P1

= 0

1

f

P2

=

C1×C2

C1 + C2

2π ×R2×

Determining the 0dB crossing frequency (f_C, control loop

bandwidth) is the first step of compensator design. Usually,

the f_Cis set to 0.1 to 0.3 times of the switching frequency.

The second step is to calculate the open loop modulator

gain and find out the gain loss at f_C. The third step is to

design a compensator gain that can compensate the

modulator gain loss at f_C. The final step is to design f_Z1

and f_P2to allow the loop sufficient phase margin. f_Z1is

designed to cancel one of the double-pole of modulator.

Usually, place f_Z1before f_P(LC). f_P2is usually placed below

the switching frequency (typically, 0.5 to 1 times of the

switching frequency) to cancel high frequency noise.

The frequency of the double-pole is determined as follows.

1

f

=

P(LC)

2π L

×C

OUT

The frequency of the ESR zero is determined as follows.

1

f

=

Z(ESR)

2π ×C

×ESR

OUT

A typical type-II compensation network is shown in Figure

6.

C2

C1

R2

A typical type-III compensation contains two zeros and

two poles, where the extra one zero and one pole compared

with type-II compensation are added for stabilizing the

system when ESR zero is relatively far from LC double-

pole in frequency domain. Figure 8 and Figure 9 show the

R1

-

EA

+

V

REF

-

typical circuit and bode plot of the type-III compensation.

Figure 6. Type-II CompensationNetwork

C2

C3

C1

R3

R1

R2

After determining the phase margin at crossover

frequency, the position of zero and pole produced by type-

II compensation network, F_Z1and F_P2, can then be

determined. The bode plot of type-II compensation is

shown in Figure 7.

-

EA

+

V

REF

-

Figure 8. Type-III CompensationNetwork

F

P1

F

P1

F

P2

Z1

Frequency (Hz)

Figure 7. Bode Plot of the Type-II Compensation

F

Z1

F

Z2

F

P2

F

P3

Frequency (Hz)

Figure 9. Bode Plot of the Type-III Compensation

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RT8127

A well-designed compensator regulates the output voltage

according to the reference voltage V_REFwith fast transient

response and good stability. In order to achieve fast

transient response and accurate output regulation, an

adequate compensator design is necessary. The goal of

the compensation network is to provide adequate phase

margin (usually greater than 45°) and the highest bandwidth

(0dB crossing frequency, f_C) possible. It is also

recommended to manipulate the loop frequency response

such that its gain crosses 0dB with a slope of −20dB/

dec. According to Figure 9, the frequencies of poles and

zeros are :

For recommended operating condition specifications, the

maximum junction temperature is 125°C. The junction to

ambient thermal resistance, θ_JA, is layout dependent. For

WQFN-28L 4x4 package, the thermal resistance, θ_JA, is

52°C/W on a standard JEDEC 51-7 four-layer thermal test

board. The maximum power dissipation at T_A= 25°C can

be calculated by the following formula :

P_D(MAX)= (125°C − 25°C) / (52°C/W) = 1.923W for

WQFN-28L 4x4 package

The maximum power dissipation depends on the operating

ambient temperature for fixed T_J(MAX)and thermal

resistance, θ_JA. The derating curve in Figure 10 allows

the designer to see the effect of rising ambient temperature

on the maximum power dissipation.

1

f

=

Z1

Z2

2π ×R2×C1

1

f

2π × R1 + R3 ×C3

(

)

2.00

Four-Layer PCB

f_P1= 0

1

1.60

1.20

0.80

0.40

0.00

f_P2

f_P3

=

2π ×R3×C3

1

C1×C2

2π ×R2×

C1 + C2

Generally, f_Z1and f_Z2are designed to cancel the double-

pole of the modulator. Usually, place f_Z1at a fraction of

f_P(LC), and place f_Z2at f_P(LC). f_P2is usually placed at f_Z(ESR)

to cancel the ESR zero, and f_P3is placed below the

switching frequency to cancel high frequency noise.

0

25

50

75

100

125

Ambient Temperature (°C)

Thermal Considerations

Figure 10.Derating Curve of Maximum Power

Dissipation

For continuous operation, do not exceed absolute

maximum junction temperature. The maximum power

dissipation depends on the thermal resistance of the IC

package, PCB layout, rate of surrounding airflow, and

difference between junction and ambient temperature. The

maximum power dissipation can be calculated by the

following formula :

P_D(MAX)= (T_J(MAX)− T_A) / θ_JA

where T_J(MAX)is the maximum junction temperature, T_Ais

the ambient temperature, and θ_JAis the junction to ambient

thermal resistance.

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DS8127-05 June 2014

RT8127

Layout Consideration

Layout planning plays a critical role in modern high

frequency switching converter design. Circuit boards with

good layout can help the IC functions properly and achieve

low losses, low switching noise, and stable operation with

good performance. For the best performance of the

RT8127, the following PCB Layout guidelines must be

strictly followed.

` Place the filter capacitor close to the device pin, within

12mm (0.5 inch) if possible.

` Place the frequency setting resistor close to the IC

frequency setting pin.

` Place feedback and compensation circuits as close to

the device pin as possible.

` Keep current limit setting network as close as possible

to the IC. Routing of the network should avoid coupling

to high voltage switching node.

` Connections from the drivers to the respective gate of

the high side or the low side MOSFET should be as

short as possible to reduce stray inductance. Use

0.65mm (25 mils) or wider trace.

` All sensitive analog traces and components such as

VOUTx, FBx,GND, PGOODand VCC should be placed

away from high voltage switching nodes such as

PHASEx, LGATEx, UGATEx, or BOOTx nodes to avoid

coupling. Use internal layer(s) as ground plane(s) and

shield the feedback trace from power traces and

components.

` Gather ground terminal of VIN capacitor(s), VOUTx

capacitor(s), and source of low side MOSFETs as close

as possible. PCB trace defined as PHASEx node, which

connects to source of high side MOSFET, drain of low

side MOSFET and high voltage side of the inductor,

should be as short and wide as possible.

` Keep Channel 1 and Channel 2 network isolated to avoid

mutually noise coupling.

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21

RT8127

Outline Dimension

D

D2

SEE DETAIL A

L

1

E

E2

1

2

1

2

DETAILA

e

b

Pin #1 ID and Tie Bar Mark Options

A

A3

Note : The configuration of the Pin #1 identifier is optional,

but must be located within the zone indicated.

A1

Dimensions In Millimeters

Dimensions In Inches

Symbol

Min

Max

Min

Max

A

A1

A3

b

0.700

0.000

0.175

0.150

3.900

2.350

3.900

2.350

0.800

0.050

0.250

4.100

2.450

4.100

2.450

0.028

0.000

0.007

0.006

0.154

0.093

0.154

0.093

0.031

0.002

0.010

0.161

0.096

0.161

0.096

D

D2

E

E2

e

0.400

0.016

L

0.350

0.450

0.014

0.018

W-Type 28L QFN 4x4 Package

Richtek Technology Corporation

14F, No. 8, Tai Yuen 1^stStreet, Chupei City

Hsinchu, Taiwan, R.O.C.

Tel: (8863)5526789

Richtek products are sold by description only. Richtek reserves the right to change the circuitry and/or specifications without notice at any time. Customers should

obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. Richtek cannot

assume responsibility for use of any circuitry other than circuitry entirely embodied in a Richtek product. Information furnished by Richtek is believed to be

accurate and reliable. However, no responsibility is assumed by Richtek or its subsidiaries for its use; nor for any infringements of patents or other rights of third

parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Richtek or its subsidiaries.

www.richtek.com

22

DS8127-05 June 2014


型号：	RT8127
厂家：	RICHTEK TECHNOLOGY CORPORATION
描述：	暂无描述
文件：	总22页 (文件大小：372K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

RT8127 [RICHTEK]

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