RT8167A_技术文档

®

RT8167A

Dual Single-Phase PWM Controller for CPU Core/GFX

Power Supply

General Description

Features

^zG-NAVP^TM(GreenNativeActive Voltage Positioning)

The RT8167A is a dual single-phase synchronous Buck

PWM controller with integrated gate drivers, compliant

with Intel VR12/IMVP7 specification. A serial VID (SVID)

interface is built-in in the RT8167A to communicate with

Intel VR12/IMVP7 compliant CPU. The integrated

differential remote output voltage sensing function and

built-in high accuracyDAC achieve accurate output voltage

regulation.

Topology

^zDual Output Controller with Two Built-in Gate

Drivers

^zSerial VID Interface

^z0.5% DAC Accuracy

^zDifferential Remote Output Voltage Sensing

^zBuilt-in ADC for Platform Programming

^zDiode Emulation Mode (DEM) at Light Load

Condition

The RT8167A supports VR12/ IMVP7 compatible power

management states and VID on-the-fly function. The

RT8167A operates in two power management states

including DEM in PS2 and Forced-CCM in PS1/PS0.

Richtek's proprietaryG-NAVP^TM(GreenNativeAVP) makes

AVP (Active Voltage Positioning) design easier and more

robust. By utilizing theG-NAVP^TMtopology,DEM and CCM

efficiency can be improved.

^zDroop Enable/Disable

z Fast Transient Response

z VR12/IMVP7 Compatible Power Management

States

z VR Ready Indicator

z Thermal Throttling Indicator

z Current Monitor Output

The RT8167A integrates high accuracy ADC for platform

setting functions, such as no-load offset or over current

level. Individual VR ready output signals are provided for

both CORE VR andGFX VR. The IC also features complete

fault protection functions, including over voltage, under

voltage, negative voltage, over current and under voltage

lockout. The RT8167A is available in a WQFN-48L 6x6

small foot print package.

z Switching Frequency up to 1MHz per Phase

z Protection : OVP, UVP, NVP, OCP, UVLO

z Small 48-Lead WQFN Package

z RoHS Compliant and Halogen Free

Applications

z VR12 / IMVP7 Intel CPU Core Supply

z AVP Step-down Converter

z Notebook/ Netbook/ Desktop Computer CPU Core

Supply

Marking Information

RT8167AGQW : Product Number

RT8167A

GQW

Ordering Information

RT8167A

YMDNN : Date Code

YMDNN

Package Type

QW : WQFN-48L 6x6 (W-Type)

Lead Plating System

G : Green (Halogen Free and Pb Free)

Note :

Richtek products are :

` RoHS compliant and compatible with the current

requirements of IPC/JEDEC J-STD-020.

` Suitable for use in SnPb or Pb-free soldering processes.

©

is a registered trademark of Richtek Technology Corporation.

DS8167A-00 January 2012

www.richtek.com

1

®

RT8167A

Pin Configurations

(TOP VIEW)

48 47 46 45 44 43 42 41 40 39 38 37

1

2

36

35

34

33

32

31

30

29

28

27

26

25

ISEN1P

ISEN1N

COMP

FB

RGND

IMON

IMONFB

DRPEN

OFS

OFSA

GFXPS2

VCC

ISENAP

ISENAN

COMPA

FBA

RGNDA

IMONA

IMONFBA

VCLK

VDIO

ALERT

DRPENA

VRA_READY

3

4

5

6

GND

7

8

9

49

10

11

12

13 14 15 16 17 18 19 20 21 22 23 24

WQFN-48L 6x6

Functional Pin Description

Pin No.

Pin Name

Pin Function

1

2

3

4

ISEN1P

Positive Current Sense Input of CORE VR

Negative Current Sense Input of CORE VR

ISEN1N

COMP

FB

CORE VR Compensation. This pin is the output node of the error amplifier.

CORE VR Feedback. This is the negative input node of the error amplifier.

Return Ground for CORE VR. This pin is the negative input for differential remote

voltage sensing.

5

RGND

Current Monitor Output of CORE VR. The output voltage V_IMONof this pin is

proportional to the output current. For digital output current reporting, detailed

V_IMONis generated by built-in ADC.

6

IMON

This pin is used to externally set the current monitor output gain of CORE VR.

Connect this pin with one resistor R_IMONFBto CORE VCC_SENSE while IMON pin

is connected to ground with another resistor, R_IMON. The current monitor output

gain can be set by the ratio of these two resistors.

7

IMONFB

Droop Enable Mode Setting of CORE VR. An internal 80μA current source is

connected to the DRPEN pin and flows out of this pin for 10μs. Connect this pin to

V_CCto enable droop function. Connect this pin to GND to disable droop function.

8

9

DRPEN

OFS

Output Voltage No-Load Offset Setting of CORE VR. Connect to a resistive voltage

divider from V_CCto GND to set the pin voltage V_OFSfor offset setting. Connect this

pin to GND for no offset setting.

Output Voltage No-Load Offset Setting of GFX VR. Connect to a resistive voltage

divider from V_CCto GND to set the pin voltage V_OFSAfor offset setting. Connect this

pin to GND for no offset setting.

10

OFSA

©

is a registered trademark of Richtek Technology Corporation.

DS8167A-00 January 2012

www.richtek.com

2

®

RT8167A

Pin No.

Pin Name

Pin Function

Forced DEM Enable Setting of GFX VR. Connect to V_CCfor forced-DEM setting

and connect to GND for following SVID power state command.

11

GFXPS2

5V Power Supply Input of Controller. Bypass this pin to GND with a 1μF or greater

12

13

VCC

ceramic capacitor.

Initial Startup Voltage V_{INI_GFX}Setting of GFX VR. Connect to a resistive voltage

divider from V_CCto GND to set the pin voltage V_SETINIAfor GFX VR initial startup

voltage V_{INI_GFX}setting. Connect this pin to GND for 0V V_{INI_GFX}setting.

SETINIA

Initial Startup Voltage V_{INI_CORE}Setting of CORE VR. Connect to a resistive

voltage divider from V_CCto GND to set the pin voltage V_SETINIfor CORE VR initial

startup voltage V_{INI_CORE}setting. Connect this pin to GND for 0V V_{INI_CORE}setting.

14

SETINI

Maximum Temperature Setting of CORE VR. Connect to a resistive voltage divider

from V_CCto GND to set the pin voltage V_TMPMAXfor TMPMAX setting.

15

16

TMPMAX

ICCMAX

Maximum Current Setting of CORE VR. Connect to a resistive voltage divider from

V_CCto GND to set the pin voltage V_ICCMAXfor ICCMAX setting.

Maximum Current Setting of GFX VR. Connect to a resistive voltage divider from

17

18

ICCMAXA

TSEN

V_CCto GND to set the pin voltage V_ICCMAXAfor ICCMAXA setting.

Thermal Monitor Sense Pin of CORE VR.

Over Current Protection Setting of CORE VR. Connect to a resistive voltage divider

from V_CCto GND to set the pin voltage V_OCSETfrom 0 to 3.3V for CORE VR over

current protection threshold.

19

20

21

OCSET

TSENA

OCSETA

Thermal Monitor Sense Pin of GFX VR.

Over Current Protection Setting of GFX VR. Connect to a resistive voltage divider

from V_CCto GND to adjust the pin voltage V_OCSETAfrom 0 to 3.3V for GFX VR over

current protection threshold.

22

23

IBIAS

Internal bias current setting. Connect a 53.6kΩ resistor from IBIAS pin to GND.

Thermal Monitor Output (Active Low). Connect a pull high resistor from VRHOT pin

to 1.05V.

VRHOT

Voltage Ready Indicator of CORE VR. Connect a pull high resistor from

VR_READY pin to 1.05V.

24

25

VR_READY

Voltage Ready Indicator GFX VR. Connect a pull high resistor from VRA_READY

pin to 1.05V.

VRA_READY

Droop Enable Mode Setting of GFX VR. An internal 80μA current source is

connected to DRPENA pin and flows out of this pin for 10μs. Connect this pin to

V_CCto enable droop function. Connect this pin to GND to disable droop function.

26

DRPENA

27

28

SVID Alert Pin (Active Low). Connect a 75Ω resistor from ALERT pin to 1.05V.

ALERT

VDIO

Controller and CPU Data Transmission Interface. Connecting a 64.9Ω resistor

between VDIO pin to 1.05V.

Synchronous Clock from the CPU. Connect a 64.9Ω resistor from VCLK pin to

1.05V.

29

30

VCLK

This pin is used to externally set the current monitor output gain of GFX VR.

Connect this pin with one resistor R_IMONFBAto GFX VCC_SENSE while IMON pin

is connected to ground with another resistor R_IMONA. The current monitor output

gain can be set by the ratio of these two resistors.

IMONFBA

Current Monitor Output of GFX VR. The output voltage VIMONA of this pin is

proportional to the output current. For digital output current reporting, detailed

VIMONA is generated by built-in ADC.

31

IMONA

©

is a registered trademark of Richtek Technology Corporation.

DS8167A-00 January 2012

www.richtek.com

3

RT8167A

Pin No.

Pin Name

RGNDA

Pin Function

Return Ground for GFX VR. This pin is the negative input for differential

remote voltage sensing.

32

33

34

35

36

37

38

FBA

GFX VR Feedback. This is the negative input node of the error amplifier.

GFX VR Compensation. This pin is the output node of the error amplifier.

Negative Current Sense Input of GFX VR.

COMPA

ISENAN

ISENAP

TONSETA

EN

Positive Current Sense Input of GFX VR.

On-Time Setting of GFX VR. Connect this pin to VIN with one resistor.

Chip Enable (Active High).

Bootstrap Flying Capacitor Connection for GFX VR. This pin powers the high

side MOSFET drivers. Connect this pin to PHASEA with an external ceramic

capacitor.

39

40

41

BOOTA

High Side MOSFET Floating Gate Driver Output for GFX VR. Connect this

pin to the gate of high side MOSFET.

UGATEA

PHASEA

Switching Node Connection for GFX VR. PHASEA is also the zero cross

detect input for GFX VR. Connect this pin to the high side MOSFET sources

together with the low side MOSFET drains and the inductor.

Synchronous-Rectifier Gate Driver Output of GFX VR. Connect this pin to the

gate of low side MOSFET.

5V Power Supply of Driver. Bypass this pin to GND with a 1μF or greater

ceramic capacitor.

Synchronous-Rectifier Gate Driver Output of CORE VR. Connect this pin to

the gate of low side MOSFET.

42

43

44

LGATEA

PVCC

LGATE

Switching Node Connection for CORE VR. PHASE is the internal lower

supply rail for the UGATE. PHASE is also the zero cross detect input for

CORE VR. Connect this pin to the high side MOSFET sources together with

the low side MOSFET drains and the inductor.

45

46

PHASE

UGATE

High Side MOSFET Floating Gate Driver Output for CORE VR. Connect this

pin to the gate of high side MOSFET.

Bootstrap Flying Capacitor Connection for CORE VR. This pin powers the

high side MOSFET drivers. Connect this pin to PHASE with an external

ceramic capacitor.

47

48

BOOT

TONSET

On-Time Setting of CORE VR. Connect this pin to VIN with one resistor.

Ground. The exposed pad must be soldered to a large PCB and connected to

GND for maximum power dissipation.

49 (Exposed pad) GND

©

is a registered trademark of Richtek Technology Corporation.

www.richtek.com

4

DS8167A-00 January 2012

RT8167A

Typical Application Circuit

R2

130k

R3

5.1

RT8167A

TONSET

V

CC

48

V

IN

R1

2.2

5V to 25V

12

C2

VCC

5V

0.1µF

C1

1µF

R4

0

47

46

BOOT

Q1

Q2

C4

V

CCP

UG

ATE

10µF

V

CORE

L1

1µH

R5

0

C3

R6

R7 R8 R9 R10 R11

75

0.1µF

130 130 150 10k 10k

Optional

45

PHASE

DCR 7.6m

R12

C6

330µF

/9m

C26

330µF

/9m

44

43

0

29

28

27

25

24

23

LGATE

PVCC

R13

C7

VCLK

VDIO

ALERT

VRA_READY

VCLK

VDIO

5V

C8

R

NTC1

ALERT

VRA_READY

1µF

4.7k

R14 3.9k

1

2

VR_READ

Y

ISEN1P

ISEN1N

VRHOT

R16

2.4k

C5

0.068µF

Optional

C25

VCC

R15

4.7k

C9

R17 R18 R19 R20 R21 R22

10k 10k 27k 8.7k 10k 10k

Optional

R23

10k

R24

26

8

21

19

13

14

0

7

4

DRPENA

DRPEN

OCSETA

OCSET

SETINIA

SETINI

DRPENA

DRPEN

OCSETA

OCSET

IMONFB

FB

C10

Optional

C12

Optional

C11

SETINIA

SETINI

CORE VCC_ SENSE

3

COMP

RGND

V

CORE

R27

100

R26

10k

R25

71k

5

6

CORE VSS_SENSE

R28 R29 R30 R31 R32 R33

NC NC 10k 10k NC NC

IM

ON

IMON

R34

100

C13

0.1µF

R35

620k

VCC

R36

39k

TONSETA

R43

R44

V

37

IN

5V to 25

R37 R38 R39 R40 R41 R42

51k 150k 100k NC NC NC

C14

15

16

17

10

9

0.1µF

TMPMAX

ICCMAX

ICCMAXA

OFSA

TMPMAX

ICCMAX

ICCMAXA

OFSA

OFS

GFXPS2

R45

0

39

40

BOTTA

Q3

C16

10µF

UGATEA

V

GFX

L2

2µH

R46

0

OFS

GFXPS2

C15

0.1µF

11

Optional

41

42

PHASEA

LGATEA

DCR 14.6m

Q4

R53

0

C27

330µF

/15m

C19

330µF

/15m

R54

C17

R47 R48 R49 R50 R51 R52

33k 5.1k 1.6k

0

10k

R

NTCA

1k

R55

36

35

11k

ISENAP

ISENAN

R57

1.2k

VCC

C18

0.1µF

R

NTC

TA

R

10k

ß = 3380

R59

12k

NTC

R56

1k

T1

R58

12k

10k

ß = 3380

C20

Optional

R72

750

R60

10k

R61

R71

750

0

20

18

22

30

33

IMONFBA

FBA

TSENA

TSEN

IBIAS

C21

Optional

C22

C23

SENSE

GFX VCC_

R62

1k

R64

R63

1k

34

53.6k

COMPA

V

GFX

R65

42k

R67

100

R66

10k

32

31

RGNDA

IMONA

GFX VSS_S

ENSE

38

EN

IMONA

R68

100

GND

C24

0.1µF 180k

R69

49 (Exposed P

ad)

R70

1.8M

Figure 1. Dual Output Application Circuit

©

is a registered trademark of Richtek Technology Corporation.

DS8167A-00 January 2012

www.richtek.com

5

RT8167A

TONSET

VCC

R1

2.2

R2

130k

R3

5.1

12

48

VCC

V

5V

IN

C1

1µF

5V to 25

C2

0.1µF

R4 0

R5 0

47

46

BOOT

Q1

V

CCP

C4

UGATE

10µF

R6

R7

R8

R9

R10

75

L1

C3

V

CORE

1µH

0.1µF

130 130 150 10k

Optional

45

PHASE

29

28

27

VCLK

VDIO

ALERT

VR_READY

VRHOT

m

DCR 7.6

VCLK

VDIO

ALERT

Q2

5V

R11 0

44

43

R12

C7

C26

C6

330µF

/9m

LGATE

PVCC

330µF

/9m

R

NTC1

4.7k

24

23

C8

1µF

VR_READY

VRHOT

R13 3.9k

1

2

ISEN1P

ISEN1N

Optional

C25

R15

2.4k

VCC

C5

0.068µF

R16 R17 R18

10k 8.7k 10k

R14

4.7k

C9

8

19

14

Optional

DRPEN

OCSET

DRPEN

OCSET

SETINI

R19

10k

R20

0

SETINI

7

4

IMONFB

FB

C10

Optional

R27 R28 R29

Optional

NC

10k NC

NSE

CORE VCC_SE

C11

C12

3

COMP

V

CORE

R21

71k

R22

10k

3

R2

5

6

100

SE

CORE VSS_SEN

RGND

IMON

VCC

R26

100k

IMON

R30 R31 R32

51k 150k NC

R24

620k

C13

0.1µF

R25

39k

15

16

TMPMAX

ICCMAX

OFS

TMPMAX

ICCMAX

37

39

9

TONSETA

BOOTA

GND

OFS

Floating

40

41

UGATEA

PHASEA

Floating

R33 R34 R35

33k 5.1k

0

42

25

LGATEA

Floating

GND

VRA_READY

OFSA

10

17

11

21

GND

VCC

GND

VCC

GND

ICCMAXA

GFXPS2

OCSETA

NTC

10k

ß = 3380

R36

12k

T1

26

36

30

33

34

18

22

DRPENA

ISENAP

IMONFBA

TSEN

IBIAS

VCC

Floating

R39

750

FBA

Floating

GND

COMPA

IMONA

ISENAN

R37

1k

R38

53.6k

31

35

VCC

20

32

13

TSENA

RGNDA

SETINIA

VCC

GND

38

EN

GND

49 (Exposed Pad)

Figure 2. Single Output Application Circuit

©

is a registered trademark of Richtek Technology Corporation.

www.richtek.com

6

DS8167A-00 January 2012

RT8167A

Function Block Diagram

UVLO

CORE VR

GFX VR

MUX

ADC

Current Monitor

SVID XCVR

Control & Protection Logic

GFXPS2

GND

GFX VR

VID/OFS control

GFX VR

Slew Rate control

DAC

RGNDA

OFSA

VREFA

GFX 0LL EN

OFS Control

Droop Enabler

DRPENA

ERROR

AMP

GM

Slew Rate Control

+

-

+

-

Offset

Cancellation

FBA

GFX VR CCRCOT

PWM Generator

VREFA

+

-

TONSETA

BOOTA

COMPA

PWM CMP

GFX 0LL VCS

/5

GFX 0LL EN

ISENAP

ISENAN

+

X4.8

GFX VR OCP

10

UGATEA

PHASEA

-

Current

GFX VR

Protection Signal

Sense AMP

Driver logic

control

OCSETA

PVCC

GFX VR

OV/UV/NV

LGATEA

GFX VR

Operation Mode

CORE VR

VID/OFS Control

CORE VR

Slew Rate control

RGND

OFS

DAC

CORE 0LL EN

VREF

Droop Enabler

DRPEN

ERROR

AMP

OFS Control

GM

Slew Rate Control

+

Offset

Cancellation

-

FB

CORE VR

CCRCOT

PWM Generator

-

+

-

VREF

TONSET

COMP

PWM CMP

/5

CORE 0LL VCS

CORE 0LL EN

BOOT

ISEN1P

ISEN1N

CORE VR

OCP

+

UGATE

PHASE

X4.8

10

-

Current

CORE VR

Protection Signal

Sense AMP

Driver logic

control

PVDD

OCSET

CORE VR

OV/UV/NV

LGATE

CORE VR

Operation Mode

IBIAS

2.14V

©

is a registered trademark of Richtek Technology Corporation.

DS8167A-00 January 2012

www.richtek.com

7

RT8167A

Table 1. IMVP7/VR12 Compliant VID Table

VID7

0

VID6

0

VID5

0

1

VID4

0

1

0

VID3

0

1

0

1

0

VID2

0

1

0

1

0

1

0

1

0

VID1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

VID0

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

H1

0

1

2

H0

0

VDAC Voltage

0.000

0.250

0.255

0.260

0.265

0.270

0.275

0.280

0.285

0.290

0.295

0.300

0.305

0.310

0.315

0.320

0.325

0.330

0.335

0.340

0.345

0.350

0.355

0.360

0.365

0.370

0.375

0.380

0.385

0.390

0.395

0.400

0.405

0.410

0.415

1

2

3

4

5

6

7

8

9

A

B

C

D

E

F

0

1

2

3

4

5

6

7

8

9

A

B

C

D

E

F

0

1

2

©

is a registered trademark of Richtek Technology Corporation.

www.richtek.com

8

DS8167A-00 January 2012

RT8167A

VID7

0

VID6

0

1

VID5

1

0

VID4

0

1

0

VID3

0

1

0

1

0

VID2

0

1

0

1

0

1

0

1

0

1

VID1

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

VID0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

H1

2

3

4

H0

3

DAC Voltage

0.420

0.425

0.430

0.435

0.440

0.445

0.450

0.455

0.460

0.465

0.470

0.475

0.480

0.485

0.490

0.495

0.500

0.505

0.510

0.515

0.520

0.525

0.530

0.535

0.540

0.545

0.550

0.555

0.560

0.565

0.570

0.575

0.580

0.585

0.590

4

5

6

7

8

9

A

B

C

D

E

F

0

1

2

3

4

5

6

7

8

9

A

B

C

D

E

F

0

1

2

3

4

5

©

is a registered trademark of Richtek Technology Corporation.

DS8167A-00 January 2012

www.richtek.com

9

RT8167A

VID7

0

VID6

1

VID5

0

1

VID4

0

1

0

VID3

0

1

0

1

0

1

VID2

1

0

1

0

1

0

1

0

1

0

VID1

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

VID0

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

H1

4

5

6

H0

6

DAC Voltage

0.595

0.600

0.605

0.610

0.615

0.620

0.625

0.630

0.635

0.640

0.645

0.650

0.655

0.660

0.665

0.670

0.675

0.680

0.685

0.690

0.695

0.700

0.705

0.710

0.715

0.720

0.725

0.730

0.735

0.740

0.745

0.750

0.755

0.760

0.765

0.770

7

8

9

A

B

C

D

E

F

0

1

2

3

4

5

6

7

8

9

A

B

C

D

E

F

0

1

2

3

4

5

6

7

8

9

©

is a registered trademark of Richtek Technology Corporation.

www.richtek.com

10

DS8167A-00 January 2012

RT8167A

VID7

0

1

VID6

1

0

VID5

1

0

VID4

0

1

0

VID3

1

0

1

0

1

VID2

0

1

0

1

0

1

0

1

0

1

VID1

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

VID0

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

H1

6

7

8

H0

A

B

C

D

E

F

0

DAC Voltage

0.775

0.780

0.785

0.790

0.795

0.800

0.805

0.810

0.815

0.820

0.825

0.830

0.835

0.840

0.845

0.850

0.855

0.860

0.865

0.870

0.875

0.880

0.885

0.890

0.895

0.900

0.905

0.910

0.915

0.920

0.925

0.930

0.935

0.940

0.945

0.950

1

2

3

4

5

6

7

8

9

A

B

C

D

E

F

0

1

2

3

4

5

6

7

8

9

A

B

C

D

©

is a registered trademark of Richtek Technology Corporation.

DS8167A-00 January 2012

www.richtek.com

11

RT8167A

VID7

1

VID6

0

VID5

0

1

VID4

0

1

0

1

VID3

1

0

1

0

1

0

VID2

1

0

1

0

1

0

1

0

1

0

VID1

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

VID0

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

H1

8

H0

E

F

0

DAC Voltage

0.955

0.960

0.965

0.970

0.975

0.980

0.985

0.990

0.995

1.000

1.005

1.010

1.015

1.020

1.025

1.030

1.035

1.040

1.045

1.050

1.055

1.060

1.065

1.070

1.075

1.080

1.085

1.090

1.095

1.100

1.105

1.110

1.115

1.120

1.125

1.130

8

9

1

9

2

9

3

9

4

9

5

9

6

9

7

9

8

9

A

B

C

D

E

F

0

9

A

B

1

2

3

4

5

6

7

8

9

A

B

C

D

E

F

0

1

©

is a registered trademark of Richtek Technology Corporation.

www.richtek.com

12

DS8167A-00 January 2012

RT8167A

VID7

1

VID6

0

1

VID5

1

0

VID4

1

0

1

VID3

0

1

0

1

0

VID2

0

1

0

1

0

1

0

1

0

1

VID1

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

VID0

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

H1

B

C

D

H0

2

DAC Voltage

1.135

1.140

1.145

1.150

1.155

1.160

1.165

1.170

1.175

1.180

1.185

1.190

1.195

1.200

1.205

1.210

1.215

1.220

1.225

1.230

1.235

1.240

1.245

1.250

1.255

1.260

1.265

1.270

1.275

1.280

1.285

1.290

1.295

1.300

1.305

1.310

3

4

5

6

7

8

9

A

B

C

D

E

F

0

1

2

3

4

5

6

7

8

9

A

B

C

D

E

F

0

1

2

3

4

5

©

is a registered trademark of Richtek Technology Corporation.

DS8167A-00 January 2012

www.richtek.com

13

RT8167A

VID7

1

VID6

1

VID5

0

1

VID4

1

0

1

VID3

0

1

0

1

0

1

VID2

1

0

1

0

1

0

1

0

1

0

VID1

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

VID0

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

H1

D

E

F

H0

6

DAC Voltage

1.315

1.320

1.325

1.330

1.335

1.340

1.345

1.350

1.355

1.360

1.365

1.370

1.375

1.380

1.385

1.390

1.395

1.400

1.405

1.410

1.415

1.420

1.425

1.430

1.435

1.440

1.445

1.450

1.455

1.460

1.465

1.470

1.475

1.480

1.485

7

8

9

A

B

C

D

E

F

0

1

2

3

4

5

6

7

8

9

A

B

C

D

E

F

0

F

1

F

2

F

3

F

4

F

5

F

6

F

7

F

8

©

is a registered trademark of Richtek Technology Corporation.

www.richtek.com

14

DS8167A-00 January 2012

RT8167A

VID7

VID6

VID5

VID4

VID3

VID2

VID1

VID0

H1

F

H0

9

DAC Voltage

1.490

1

0

1

0

1

0

1

0

1

0

1

0

1

F

A

1.495

F

B

1.500

F

C

D

E

1.505

F

1.510

F

1.515

F

1.520

©

is a registered trademark of Richtek Technology Corporation.

DS8167A-00 January 2012

www.richtek.com

15

RT8167A

Absolute Maximum Ratings (Note 1)

z VCC toGND ----------------------------------------------------------------------------------------------- −0.3V to 6.5V

z PVCC toGND --------------------------------------------------------------------------------------------- −0.3V to 6.5V

z RGNDx toGND ------------------------------------------------------------------------------------------- −0.3V to 0.3V

z TONSETx toGND ---------------------------------------------------------------------------------------- −0.3V to 28V

z Others ------------------------------------------------------------------------------------------------------- −0.3V to (VCC + 0.3V)

z BOOTx to PHASEx -------------------------------------------------------------------------------------- −0.3V to 6.5V

z PHASEx to GND

DC------------------------------------------------------------------------------------------------------------ −0.3V to 28V

<20ns ------------------------------------------------------------------------------------------------------- −8V to 32V

z UGATEx to PHASEx

DC------------------------------------------------------------------------------------------------------------ −0.3V to (BOOTx − PHASEx)

<20ns ------------------------------------------------------------------------------------------------------- −5V to 7.5V

z LGATEx toGND

DC------------------------------------------------------------------------------------------------------------ −0.3V to (PVCC − 0.3V)

<20ns ------------------------------------------------------------------------------------------------------- −2.5V to 7.5V

z Power Dissipation, P_D@ T_A= 25°C

WQFN−48L 6x6 ------------------------------------------------------------------------------------------- 2.857W

z Package Thermal Resistance (Note 2)

WQFN−48L 6x6, θ_JA------------------------------------------------------------------------------------- 35°C/W

WQFN−48L 6x6, θ_JC------------------------------------------------------------------------------------- 6°C/W

z Junction Temperature ------------------------------------------------------------------------------------ 150°C

z Lead Temperature (Soldering, 10 sec.)-------------------------------------------------------------- 260°C

z Storage Temperature Range --------------------------------------------------------------------------- −65°C to 150°C

z ESD Susceptibility (Note 3)

HBM (Human Body Mode) ----------------------------------------------------------------------------- 2kV

MM (Machine Mode) ------------------------------------------------------------------------------------- 200V

Recommended Operating Conditions (Note 4)

z Supply Voltage of Controller, V_CC-------------------------------------------------------------------- 4.5V to 5.5V

z Supply Voltage of Gate Driver, V_PVCC---------------------------------------------------------------- 4.5V to 5.5V

z Battery Input Voltage, V_IN------------------------------------------------------------------------------ 5V to 25V

z Junction Temperature Range--------------------------------------------------------------------------- −40°C to 125°C

z Ambient Temperature Range--------------------------------------------------------------------------- −40°C to 85°C

Electrical Characteristics

(V_CC= 5V, T_A= 25°C, unless otherwise specified)

Parameter

Supply Input

Symbol

Test Conditions

Min

Typ Max Unit

V

/V

V

= 1.05V, Not Switching

4.5

5

5.5

25

V

CC PVCC

EN

Input Voltage Range

V

IN

Battery Input Voltage

--

Supply Current

I

+ I

V

EN

= 1.05V, Not Switching

--

12

20

--

mA

VCC

PVCC

(V + PVCC)

CC

Supply Current

(TONSETx)

I

V

FB

=1V, V = 12V, R = 100kΩ

TON

110

μA

TONSETx

IN

©

is a registered trademark of Richtek Technology Corporation.

www.richtek.com

16

DS8167A-00 January 2012

RT8167A

Parameter

Symbol

Test Conditions

Min

Typ

Max

Unit

Shutdown Current

I

VCC_SHDN

V

= 0V

--

5

μA

EN

(PVCC + V

)

+ I

CC

PVCC_SHDN

Shutdown Current

(TONSETx)

I

--

5

μA

TONSETx_SHDN

TON Setting

TONSETx Voltage

On-Time

V

I

= 80μA, V

= 1V

0.95

315

1.075

350

1.2

0V

ns

TONSETx

RTON

FBx

t

I

= 80μA, V

385

ON

RTON

TONSETx Input Current

Range

I

V

= 1.1V

25

--

280

--

μA

RTON

FBx

Minimum Off-Time

T

I

350

ns

OFF_MIN

Droop Enable / Disable

DRPENx Internal

Current Source

EN goes high within 10μs

--

4.5

--

80

--

2

μA

DRPENx

Detect V

within 10μs

Detect V

, EN goes high

DRPENx

Droop Enable Threshold V

DRPENx

V

Droop Disable

V

, EN goes high

DRPENx

--

Threshold

within 10μs

GFX VR Forced DEM

GFXPS2x Enable

Threshold

GFXPS2x Disable

Threshold

V

4.3

--

V

GFXPS

V

0.7

References and System Output Voltage

VID

OFS

Setting = 1.000V~1.520V

SVID

−0.5

−5

0

0.5

5

%VID

mV

Setting = 0V

SVID

VID

OFS

Setting = 0.800V~1.000V

SVID

Setting = 0V

SVID

DAC Accuracy

(PS0/PS1)

VID

OFS

Setting = 0.500V~0.800V

SVID

V

−8

8

FBx

Setting = 0V

SVID

VID

OFS

Setting = 0.250V~0.500V

SVID

−8

8

Setting = 0V

SVID

VID

OFS

Setting = 1.100V

SVID

−10

10

Setting =−0.640V~0.635V

SVID

V

= 0V, V

= 0V

INI_GFX

0

0.3125 0.5125

INI_CORE

= 0.9V, V

= 0.9V 0.7375 0.9375 1.1375

INI_GFX

SETINIx Voltage

V

SETINIx

= 1V, V

= 1V

1.3625 1.5625 1.7625

INI_GFX

= 1.1V, V

= 1.1V 2.6125

--

72

56

40

24

8

5

Offset = 100mV

Offset = 50mV

68

52

36

20

0

--

60

44

28

12

--

External OFSx Voltage

Offset = −50mV

Offset = −100mV

No Offset Voltage

%V

OFSx

CC

Impedance of OFSx Pin R

1

--

MΩ

OFSx

©

is a registered trademark of Richtek Technology Corporation.

DS8167A-00 January 2012

www.richtek.com

17

RT8167A

Parameter

Symbol

Test Conditions

= 53.6kΩ

IBIAS

Min

Typ

Max

Unit

IBIAS Pin Voltage

V

R

2.09 2.14 2.19

2.5 3.125 3.75

V

IBIAS

SetVID Slow

SetVID Fast

Dynamic VID Slew Rate SR

mV/μs

DVID

10

12.5

15

Error Amplifier

DC Gain

A

R = 47kΩ (Note5)

70

--

80

10

--

dB

DC

L

Gain-Bandwidth Product GBW

C

= 5pF

(Note5)

MHz

LOAD

= 10pF (Gain = −4, R

LOAD

LOAD_COMP

Slew Rate

SR

V

--

0.5

--

5

--

3.6

--

V/μs

V

COMP

= 47kΩ, V

= 0.5V to 3V)

COMPx

Output Voltage Range

R = 47kΩ

L

COMP

MAX Source/Sink

Current

I

V

= 2V

COMP

250

--

μA

COMP

Impedance of FBx

R

1

--

MΩ

FBx

Current Sense Amplifier

Input Offset Voltage

V

−1

1

--

1

--

mV

MΩ

OFS_CSA

ISENxN

ISENxP

Impedance of Neg. Input R

Impedance of Pos. Input

R

1

Current Sense

Differential Input Range

V

= 1.1V,

FBx

V

−50

--

100

mV

CSDIx

= V

− V

CSDIx

ISENxP ISENxN

Current Sense DC Gain

(Loop)

A

V

= 1.1V, −30mV < V

= 1.1V −30mV < V

< 50mV

--

10

--

1

V/V

%

I

FBx

CSDIx

V

ISEN

Linearity

< 50mV

−1

ISEN_ACC

DAC

ISEN_IN

Digital Current Monitor

Current Monitor Output

Voltage (Droop Enabled)

V

= 1V, V

= 0.9V,

FBx

ISENxN

V

--

1.6

--

V

IMONx_ENLL

= 10k, R

= 160k

RIMONFBx

IMONx

V

R

= V_ISENxP− V

= 100mV

CSDIx

ISENxN

= 10k,

Current Monitor Output

Voltage (Droop Disabled)

V

= 1V, V

IMONx_DISLL

IMON

FBx

RIMONFBx

= 80k

IMONx

IMON Voltage Range

Digital IMON LSB

0

--

12.94

30

3.3

--

V

3.3V / 255 = 12.94mV

--

mV

V

= 388.3mV, DIOUT [7 : 0] = 30

= 776.5mV, DIOUT [7 : 0] = 60

27

57

33 Decimal

63 Decimal

IMONx

60

Digital Code of IMON

C

t

DIMON

V

= 1164.7mV, DIOUT [7 : 0] = 90

87

--

90

93 Decimal

Update Period of Digital

Current Monitor

1600

--

μs

IMON

Gate Driver

V

_BOOTx− V

= 5V

= 0.1V

PHASEx

UGATEx

Upper Driver Source

R

--

1

--

Ω

UGATEx_sr

Upper Driver Sink

Lower Driver Source

Lower Driver Sink

R

V

= 0.1V

UGATEx

--

1

--

Ω

UGATEx_sk

LGATEx_sr

LGATEx_sk

PVCC = 5V, PVCC − V

= 0.1V

LGATEx

V

= 0.1V

0.5

LGATEx

Internal Boot Charging

Switch On-Resistance

R

PVCC to BOOTx

--

30

--

Ω

BOOTx

©

is a registered trademark of Richtek Technology Corporation.

www.richtek.com

18

DS8167A-00 January 2012

RT8167A

Parameter

Symbol

Test Conditions

Min

Typ

Max

Unit

Zero Current Detection

Threshold

V

= GND − V

--

10

--

mV

ZCD_TH

PHASEx

Protection

Under Voltage Lock-out

Threshold

Under Voltage Lock-out

Hysteresis

Over Voltage Protection

Threshold

Under Voltage Protection

Threshold

VCC Falling edge

4.04

--

4.24

100

--

V

UVLO

ΔV

mV

UVLO

Respect to VOUT_MAX

1μs filter time

, with

SVID

V

100

−350

−100

150

200

−250

--

OVP

V

UVP

= V

− V

, 0.8V <

REFx

ISENxN

−300

−50

UVP

NVP

V

REFx

<1.52V, with 3μs filter time

Negative Voltage

Protection Threshold

V

NVP

= V_ISENxN− GND

Current Sense Gain for

Over Current Protection

V

= 2.4V

OCSET

A

--

48

--

V/V

OC

V

− V

= 50mV

ISENxP

ISENxN

Logic Inputs

EN Input

Threshold

Voltage

Logic-High V

With respect to 1V, 70%

With respect to 1V, 30%

0.7

--

V

IH

IL

Logic-Low

V

0.3

Leakage Current of EN

−1

0.65

--

1

--

μA

V

With respect to Intel Spec.

VCLK,VDIO Input

Threshold Voltage

IH

IL

0.45

V

Leakage Current of

VCLK, VDIO

I

−1

--

1

μA

LEAK_IN

ALERT

V

ALERT Low Voltage

VR Ready

ALERT

I

= 4mA

--

0.4

V

ALERT_ SINK

VRx_READY Low Voltage V

I

= 4mA

to V high

VRx_READY

--

0.4

V

VRx_READY VRx_READY_ SINK

VRx_READY Delay

Thermal Throttling

VRHOT Output Voltage

t

V

= V

70

100

160

μs

VRx_READY

ISENxN

BOOT

V

VRHOT

I

= 40mA

--

0.4

--

1

V

VRHOT_SINK

High Impedance Output

ALERT, VRx_READY,

VRHOT

I

−1

μA

LEAK_OUT

Temperature Zone

TSEN Threshold for

Tmp_Zone [7] transition

100°C

97°C

94°C

91°C

88°C

--

1.8725

1.8175

1.7625

1.7075

1.6525

--

V

TSEN Threshold for

Tmp_Zone [6] transition

TSEN Threshold for

Tmp_Zone [5] transition

V

TSENx

TSEN Threshold for

Tmp_Zone [4] transition

TSEN Threshold for

Tmp_Zone [3] transition

©

is a registered trademark of Richtek Technology Corporation.

DS8167A-00 January 2012

www.richtek.com

19

RT8167A

Parameter

Symbol

Test Conditions

Min

Typ

Max

Unit

TSEN Threshold for

Tmp_Zone [2] transition

85°C

82°C

75°C

--

1.5975

--

V

TSEN Threshold for

Tmp_Zone [1] transition

V

--

1.5425

--

V

TSENx

TSEN Threshold for

Tmp_Zone [0] transition

--

1.4875

1600

--

V

Update Period

ADC

t

μs

TSEN

Latency

t

--

400

35

μs

LAT

C

V

= 0.637V

29

32

decimal

ICCMAX1

ICCMAX2

ICCMAX

C

V

= 1.2642V

61

125

5

64

128

8

67

131

11

decimal

ICCMAX

Digital Code of ICCMAX

Digital Code of ICCMAXA

V

= 2.5186V

ICCMAX3

ICCMAXA1

ICCMAXA2

ICCMAXA3

TMPMAX1

TMPMAX2

TMPMAX3

ICCMAX

V

= 0.1666V

= 0.3234V

= 0.637V

ICCMAXA

V

13

29

82

97

122

16

19

ICCMAXA

V

32

35

ICCMAXA

V

= 1.6758V

= 1.9698V

= 2.4598V

85

88

TMPMAX

Digital Code of TMPMAX

V

100

125

103

128

TMPMAX

V

TMPMAX

Note 1. Stresses beyond those listed “Absolute Maximum Ratings” may cause permanent damage to the device. These are

stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in

the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions may

affect device reliability.

Note 2. θ_JAis measured at T_A= 25°C on a high effective thermal conductivity four-layer test board per JEDEC 51-7. θ_JCis

measured at the exposed pad of the package.

Note 3. Devices are ESD sensitive. Handling precaution is recommended.

Note 4. The device is not guaranteed to function outside its operating conditions.

Note 5. Guaranteed by design.

©

is a registered trademark of Richtek Technology Corporation.

www.richtek.com

20

DS8167A-00 January 2012

RT8167A

Typical Operating Characteristics

CORE VR Power Off from EN

CORE VR Power On from EN

V_CORE

(500mV/Div)

V_CORE

(500mV/Div)

EN

(2V/Div)

EN

(2V/Div)

VR_READY

(2V/Div)

VR_READY

(2V/Div)

UGATE

(20V/Div)

UGATE

(20V/Div)

Boot VID = 1V

Time (100μs/Div)

CORE VR OCP

CORE VR OVP and NVP

V_CORE

(1V/Div)

I_LOAD

LGATE

(10A/Div)

(10V/Div)

VR_READY

(1V/Div)

VR_READY

(1V/Div)

UGATE

(20V/Div)

UGATE

(20V/Div)

VID = 1.1V

Time (100μs/Div)

Time (40μs/Div)

CORE VR Dynamic VID Up

CORE VR Dynamic VID Down

V_CORE

(500mV/Div)

VCLK

(2V/Div)

VCLK

(2V/Div)

VDIO

(2V/Div)

VDIO

(2V/Div)

ALERT

(2V/Div)

0.7V to 1.2V, Slew Rate = Slow, I_LOAD= 4A

1.2V to 0.7V, Slew Rate = Slow, I_LOAD= 4A

Time (40μs/Div)

©

is a registered trademark of Richtek Technology Corporation.

DS8167A-00 January 2012

www.richtek.com

21

RT8167A

CORE VR Dynamic VID Down

CORE VR Dynamic VID Up

V_CORE

(500mV/Div)

VCLK

(2V/Div)

VCLK

(2V/Div)

VDIO

(2V/Div)

VDIO

(2V/Div)

ALERT

(2V/Div)

0.7V to 1.2V, Slew Rate = Fast, I_LOAD= 4A

1.2V to 0.7V, Slew Rate = Fast, I_LOAD= 4A

Time (10μs/Div)

CORE VR Load Transient

V_CORE

(20mV/Div)

8

I_LOAD

(A/Div)

1

VID = 1.1V, I_LOAD= 1A to 8A, Slew Time = 150ns

VID = 1.1V, I_LOAD= 8A to 1A, Slew Time = 150ns

Time (100μs/Div)

CORE VR Mode Transition

V_CORE

(20mV/Div)

VCLK

(1V/Div)

VCLK

(1V/Div)

LGATE

(10V/Div)

UGATE

(20V/Div)

VID = 1.1V, PS0 to PS2, I_LOAD= 0.2A

VID = 1.1V, PS2 to PS0, I_LOAD= 0.2A

Time (100μs/Div)

©

is a registered trademark of Richtek Technology Corporation.

www.richtek.com

22

DS8167A-00 January 2012

RT8167A

CORE VR Thermal Monitoring

CORE VR V_REFvs. Temperature

1.10

1.08

1.06

1.04

1.02

1.00

0.98

0.96

0.94

0.92

0.90

1.9

1.7

TSEN

(V/Div)

VRHOT

(500mV/Div)

TSEN Sweep from 1.7V to 1.9V

Time (10ms/Div)

-50

-25

0

25

50

75

100

125

Temperature (°C)

GFX VR Power On from EN

GFX VR Power Off from EN

V_GFX

(500mV/Div)

V_GFX

(500mV/Div)

EN

(2V/Div)

EN

(2V/Div)

VRA_READY

(2V/Div)

VRA_READY

(2V/Div)

UGATEA

(20V/Div)

UGATEA

(20V/Div)

Boot VID = 1V

Time (100μs/Div)

GFX VR OCP

GFX VR OVP and NVP

V_GFX

(1V/Div)

VRA_READY

(1V/Div)

I_LOAD

(5A/Div)

LGATEA

(10V/Div)

VRA_READY

(1V/Div)

UGATEA

(20V/Div)

UGATEA

(20V/Div)

VID = 1.1V

Time (100μs/Div)

Time (40μs/Div)

©

is a registered trademark of Richtek Technology Corporation.

DS8167A-00 January 2012

www.richtek.com

23

RT8167A

GFX VR Dynamic VID

V_GFX

(500mV/Div)

VCLK

(2V/Div)

VCLK

(2V/Div)

VDIO

(2V/Div)

VDIO

(2V/Div)

ALERT

(2V/Div)

0.7V to 1.2V, Slew Rate = Slow, I_LOAD= 1.25A

1.2V to 0.7V, Slew Rate = Slow, I_LOAD= 1.25A

Time (40μs/Div)

GFX VR Dynamic VID

V_GFX

(500mV/Div)

VCLK

(2V/Div)

VCLK

(2V/Div)

VDIO

(2V/Div)

VDIO

(2V/Div)

ALERT

(2V/Div)

0.7V to 1.2V, Slew Rate = Fast, I_LOAD= 1.25A

1.2V to 0.7V, Slew Rate = Fast, I_LOAD= 1.25A

Time (10μs/Div)

GFX VR Load Transient

V_GFX

(20mV/Div)

4

I_LOAD

(A/Div)

1

VID = 1.1V, I_LOAD= 1A to 4A, Slew Time = 150ns

VID = 1.1V, I_LOAD= 4A to 1A, Slew Time = 150ns

Time (100μs/Div)

©

is a registered trademark of Richtek Technology Corporation.

www.richtek.com

24

DS8167A-00 January 2012

RT8167A

GFX VR Mode Transition

V_GFX

(20mV/Div)

VCLK

(1V/Div)

VCLK

(1V/Div)

LGATEA

(10V/Div)

LGATEA

(10V/Div)

UGATEA

(20V/Div)

UGATEA

(20V/Div)

VID = 1.1V, PS0 to PS2, I_LOAD= 0.1A

VID = 1.1V, PS2 to PS0, I_LOAD= 0.1A

Time (100μs/Div)

GFX VR Thermal Monitoring

GFX VR V_REFvs. Temperature

1.10

1.08

1.06

1.04

1.02

1.00

0.98

0.96

0.94

0.92

0.90

1.9

TSENA

(V/Div)

1.7

VRHOT

(500mV/Div)

TSENA Sweep from 1.7V to 1.9V

Time (10ms/Div)

-50

-25

0

25

50

75

100

125

Temperature (°C)

©

is a registered trademark of Richtek Technology Corporation.

DS8167A-00 January 2012

www.richtek.com

25

RT8167A

Application Information

management states and VIDon-the-fly function. The power

management states includeDEM in PS2/PS3 and Forced-

CCM in PS1/PS0. The VID on-the-fly function has three

different slew rates : Fast, Slow andDecay. The RT8167A

integrates a high accuracy ADC for platform setting

functions, such as no-load offset and over current level.

The controller supports both DCR and sense-resistor

current sensing. The RT8167A provides VR ready output

signals of both CORE VR and GFX VR. It also features

complete fault protection functions including over voltage,

under voltage, negative voltage, over current and under

voltage lockout. The RT8167A is available in a WQFN-

48L 6x6 small foot print package.

The RT8167A is a VR12/IMVP7 compliant, dual single-

phase synchronous Buck PWM controller for the CPU

CORE VR and GFX VR. The gate drivers are embedded

to facilitate PCB design and reduce the total BOM cost. A

serial VID (SVID) interface is built-in in the RT8167A to

communicate with Intel VR12/IMVP7 compliant CPU.

The RT8167AadoptsG-NAVP^TM(GreenNativeAVP), which

is Richtek's proprietary topology derived from finite DC

gain compensator, making it an easy setting PWM

controller to meet AVP requirements. The load line can

be easily programmed by setting the DC gain of the error

amplifier. The RT8167Ahas fast transient response due to

theG-NAVP^TMcommanding variable switching frequency.

G-NAVP^TMtopology also represents a high efficiency

system with green power concept. With G-NAVP^TM

topology, the RT8167Abecomes a green power controller

with high efficiency under heavy load, light load, and very

light load conditions. The RT8167A supports mode

transition function between CCM andDEM. These different

operating states allow the overall power system to have

low power loss. By utilizing the G-NAVP^TMtopology, the

operating frequency of RT8167A varies with output voltage,

load and VINto further enhance the efficiency even in CCM.

Design Tool

To help users reduce efforts and errors caused by manual

calculations, a user-friendly design tool is now available

on request. This design tool calculates all necessary

design parameters by entering user's requirements.

Please contact Richtek's representatives for details.

Serial VID (SVID) Interface

SVIDis a three-wire serial synchronous interface defined

by Intel. The three wire bus includes VDIO, VCLK and

ALERT signals. The master (Intel's VR12/IMVP7 CPU)

initiates and terminates SVIDtransactions and drives the

VDIO, VCLK, andALERT during a transaction. The slave

(RT8167A) receives the SVID transactions and acts

accordingly.

The built-in high accuracy DAC converts the SVID code

ranging from 0.25V to 1.52V with 5mV per step. The

differential remote output voltage sense and high accuracy

DAC allow the system to have high output voltage accuracy.

The RT8167A supports VR12/IMVP7 compatible power

©

is a registered trademark of Richtek Technology Corporation.

www.richtek.com

26

DS8167A-00 January 2012

RT8167A

Standard Serial VID Command

Master Payload

Slave Payload

Contents

Code

00h

Commands

Description

Contents

not supported

N/A

Set new target VID code, VR jumps to new VID

target with controlled default “fast” slew rate

12.5mV/μs.

Set new target VID code, VR jumps to new VID

target with controlled default “slow” slew rate

3.125mV/μs.

Set new target VID code, VR jumps to new VID

target, but does not control the slew rate. The

output voltage decays at a rate proportional to

the load current

01h

02h

SetVID_Fast

SetVID_Slow

VID code

N/A

03h

SetVID_Decay

VID code

Byte indicating

power states

04h

05h

06h

SetPS

N/A

Set power state

Pointer of registers

in data table

SetRegADR

SetReg DAT

Set the pointer of the data register

Write the contents to the data register

New data register

content

Specified

Register

Contents

Pointer of registers

in data table

Slave returns the contents of the specified

register as the payload

07h

GetReg

08h

-

not supported

N/A

1Fh

©

is a registered trademark of Richtek Technology Corporation.

DS8167A-00 January 2012

www.richtek.com

27

RT8167A

Data and Configuration Register

Description

Index Register Name

Access

Default

1Eh

00h

01h

02h

05h

Vendor ID

Vendor ID, default 1Eh.

RO, Vendor

Product ID

Product ID.

65h

Product Revision

Protocol ID

Product Revision.

SVID Protocol ID.

01h

Bit mapped register, identifies the SVID VR capabilities

and which of the optional telemetry register are

supported.

06h

VR_Capability

RO, Vendor

81h

10h

11h

Status_1

Status-2

Data register containing the status of VR.

R-M, W-PWM

00h

Data register containing the status of transmission.

Temperature

Zone

Data register showing temperature zone that have been

entered.

12h

15h

R-M, W-PWM

00h

Data register showing direct ADC conversion of averaged

output current.

Output_Current

R-M, W-PWM

00h

1Ch Status_2_lastread The register contains a copy of the status_2.

Data register containing the maximum ICC of platform

21h

22h

24h

ICC_Max

Temp_Max

SR-Fast

supports.

RO, Platform

RO

--

Binary format in Amp, IE 64h = 100A.

Data register containing the temperature max the platform

supports.

Binary format in °C, IE 64h = 100°C

Only for CORE VR

Data register containing the capability of fast slew rate the

platform can sustains. Binary format in mV/μs, IE 0Ah =

10mV/μs.

0Ah

Data register containing the capability of slow slew rate.

Binary format in mV/μs IE 02h = 2.5mV/μs.

The register is programmed by the master and sets the

maximum VID.

25h

30h

SR-Slow

RO

02h

BFh

VOUT_Max

RW, Master

31h

32h

33h

VID Setting

Power State

Offset

Data register containing currently programmed VID.

Register containing the current programmed power state.

Set offset in VID steps.

RW, Master

00h

Bit mapped data register which configures multiple VRs

behavior on the same bus.

34h

35h

Multi VR Config

Pointer

RW, Master

00h

30h

Scratch pad register for temporary storage of the

SetRegADR pointer register.

Notes :

RO = Read Only

RW = Read/Write

R-M = Read by Master

W-PWM = Write by PWM only

Vendor = hard coded by VR vendor

Platform = programmed by platform

Master = programmed by the master

PWM = programmed by the VR control IC

©

is a registered trademark of Richtek Technology Corporation.

www.richtek.com

28

DS8167A-00 January 2012

RT8167A

Power Ready Detection and Power On Reset (POR)

Current

Mirror

During start-up, the RT8167A detects the voltage on the

2.14V

voltage input pins : VCC and EN. When VCC > V_UVLO

,

+

-

the RT8167A will recognize the power state of system to

be ready (POR = high) and wait for enable command at

EN pin. After POR = high and EN > V_ENTH, the RT8167A

will enter start-up sequence for both CORE VR and GFX

VR. If the voltage on any voltage pin drops below POR

threshold (POR = low), the RT8167A will enter power down

sequence and all the functions will be disabled. SVIDwill

be invalid within 300μs after chip becomes enabled. All

the protection latches (OVP, OCP, UVP, OTP) will be

cleared only after POR = low. EN = low will not clear

these latches.

IBIAS

53.6k

Figure 4. IBIAS Setting

ICCMAX, ICCMAXA and TMPMAX

The RT8167Aprovides ICCMAX, ICCMAXAand TMPMAX

pins for platform users to set the maximum level of output

current or VR temperature: ICCMAX for CORE VR

maximum current, ICCMAXA for GFX VR maximum

current, and TMPMAX for CORE VR maximum

temperature.

VCC

EN

+

-

POR

V

UVLO

To set ICCMAX, ICCMAXA and TMPMAX, platform

designers should use resistive voltage dividers on these

three pins. The current of the divider should be several

milli-Amps to avoid noise effect. The three items share

the same algorithms : theADC divides 5V into 255 levels.

Therefore, LSB = 5/255 = 19.6mV, which means 19.6mV

applied to ICCMAX pin equals to 1Asetting. For example,

if a platform designer wants to set TMPMAX to 120°C, the

voltage applied to TMPMAX should be 120 x 19.6mV =

2.352V. The ADC circuit inside these three pins will

decode the voltage applied and store the maximum current/

temperature setting into ICC_MAX and Temp_Max

registers. The ADC monitors and decodes the voltage at

these three pins only after EN = high. If EN = low, the

RT8167Awill not take any action even when the VR output

current or temperature exceeds its maximum setting at

these ADC pins. The maximum level settings at these

ADC pins are different from over current protection or over

temperature protection. That means, these maximum level

setting pins are only for platform users to define their

system operating conditions and these messages will only

be utilized by the CPU.

+

-

Chip EN

ENTH

Figure 3. Power Ready Detection and Power On Reset

(POR)

Precise Reference Current Generation

The RT8167A includes extensive analog circuits inside

the controller. These analog circuits need very precise

reference voltage/current to drive these analog devices.

The RT8167A will auto-generate a 2.14V voltage source

at IBIAS pin, and a 53.6kΩ resistor is required to be

connected between IBIAS and analog ground. Through

this connection, the RT8167A generates a 40μA current

from IBIAS pin to analog ground and this 40μAcurrent will

be mirrored inside the RT8167A for internal use. Other

types of connection or other values of resistance applied

at the IBIAS pin may cause failure of the RT8167A's analog

circuits. Thus a 53.6kΩ resistor is the only recommended

component to be connected to the IBIAS pin. The

resistance accuracy of this resistor is recommended to

be at least 1%.

©

is a registered trademark of Richtek Technology Corporation.

DS8167A-00 January 2012

www.richtek.com

29

RT8167A

V

CC

V_{INI_CORE}and V_{INI_GFX}Setting

The initial start up voltage (V_{INI_CORE}, V_{INI_GFX}) of the

RT8167A can be set by platform users through SETINI

and SETINIApins. Voltage divider circuit is recommended

ICCMAX

A/D

Converter

ICCMAXA

TMPMAX

to be applied to SETINI and SETINIApins. The V_{INI_CORE}

/

V_{INI_GFX}relate to SETINI/SETINIA pin voltage setting as

shown in Figure 6. Recommended voltage setting at SETINI

and SETINIA pins are also shown in Figure 6.

Figure 5. ADC Pins Setting

VCC (5

V)

V_{INI_CORE}

Recommended

V

= 1.1V

INI_CORE

V_{INI_GFX}SETINI/SETINIA Pin Voltage

V

= 1.1V

INI_GFX

5

8

1.1V

1V

x VCC≒3.125V or VCC

1/2 VCC

3

x VCC≒1.875V

V

= 1V

8

INI_CORE

V

INI_GFX

3

16

0.9V

0V

x VCC≒0.9375V

1/4 VCC

1/8 VCC

GND

V

=

0.9V

INI_CORE

1

16

V

= 0.9V

INI_GFX

x VCC≒0.3125V or GND

V

= 0V

INI_CORE

INI_GFX

V

Figure 6. SETINI and SETINIA Pin Voltage Setting

Start Up Sequence

voltage reaches the target voltage, the RT8167Awill send

out VR_READY signal to indicate the power state of the

RT8167A is ready. The VR_READY circuit is an open-

drain structure so a pull-up resistor is recommended for

connecting to a voltage source.

The RT8167A utilizes internal soft-start sequence which

strictly follows Intel VR12/IMVP7 start up sequence

specifications. After POR = high and EN = high, a 300μs

delay is needed for the controller to determine whether all

the power inputs are ready for entering start up sequence.

If pin voltage of SETINI/SETINIA is zero, the output voltage

of CORE/GFX VR is programmed to stay at 0V. If pin

voltage of SETINI/SETINIA is not zero, VR output voltage

will ramp up to initial boot voltage (V_{INI_CORE},V_{INI_GFX}) after

both POR = high and EN = high. After the output voltage

of CORE/GFX VR reaches target initial boot voltage, the

controller will keep the output voltage at the initial boot

voltage and wait for the next SVID commands. After the

RT8167A receives valid VID code (typically SetVID_Slow

command), the output voltage will ramp up/down to the

target voltage with specified slew rate. After the output

Power Down Sequence

Similar to the start up sequence, the RT8167A also utilizes

a soft shutdown mechanism during turn-off. After POR =

low, the internal reference voltage (positive terminal of

compensation EA) starts ramping down with 3.125mV/μs

slew rate, and output voltage will follow the reference

voltage to 0V. After output voltage drops below 0.2V, the

RT8167Ashuts down and all functions are disabled. The

VR_READY will be pulled down immediately after POR =

low.

©

is a registered trademark of Richtek Technology Corporation.

www.richtek.com

30

DS8167A-00 January 2012

RT8167A

VCC

POR

EN

EN Chip

(Internal Signal)

SVID

Valid

xx

XX

Off

300µs

0.2V

Off

V

CORE

CORE VR

Operation Mode

CCM

SVID defined

V

GFX

0.2V

Off

GFX VR

Operation Mode

CCM

SVID defined

100µs

VR_READY

VRA_READY

100µs

Figure 7 (a). Power sequence for RT8167A (V_{INI_CORE}= V_{INI_GFX}= 0V)

VCC

POR

EN

EN Chip

(Internal Signal)

300µs

SVID

xx

Valid

XX

250µs

V

INI_CORE

0.2V

Off

V

CORE

CORE VR

Operation Mode

Off

CCM

SVID defined

100µs

VR_READY

50µs

V

INI_GFX

V

GFX

0.2V

Off

GFX VR

Operation Mode

Off

CCM

SVID defined

CCM

100µs

VRA_READY

Figure 7 (b). Power sequence for RT8167A (V_{INI_CORE}0, V

0V)

≠

INI_GFX

©

is a registered trademark of Richtek Technology Corporation.

DS8167A-00 January 2012

www.richtek.com

31

RT8167A

Disable GFX VR : Before EN = High

Similar to the valley current mode control with finite

compensator gain, the high side MOSFET on-time is

determined by the CCRCOT PWM generator. When load

current increases, V_CSincreases, the steady state COMP

voltage also increases which makes the output voltage

decrease, thus achieving AVP.

GFX VR enable or disable is determined by the internal

circuitry that monitors the ISENAN voltage during start

up. Before EN= high,GFX VR detects whether the voltage

of ISENAN is higher than “VCC − 1V” to disable GFX

VR. The unused driver pins can be connected to GND or

left floating.

Droop Function Enable

GFX VR Forced-DEM Function Enable : After

VRA_Ready = High

The CORE/GFX VR's droop function can be enabled or

disabled withDRPEN/DRPENApin.After EN = high within

10μs, the RT8167Awill source 80μAcurrent fromDRPEN/

DRPENA pin to the external resistor to determine the

voltage level. If the voltage atDRPEN/DRPENApin is lower

than 3.5V, then the VR will operate in droop-disabled mode.

If the voltage is higher than 4V, then the VR will operate in

droop-enabled mode.

The GFX VR's forced-DEM function can be enabled or

disabled with GFXPS2 pin. The RT8167A detects the

voltage ofGFXPS2 for forced-DEM function. If the voltage

atGFXPS2 pin is higher than 4.3V, theGFX VR operates

in forced-DEM. If this voltage is lower than 0.7V, theGFX

VR follows SVID power state command.

Droop Setting (with Temperature Compensation)

Loop Control

It's very easy to achieve the Active Voltage Positioning

(AVP) by properly setting the error amplifier gain due to

the native droop characteristics. The target is to have

Both CORE and GFX VR adopt Richtek's proprietary G-

NAVP^TMtopology. G-NAVP^TMis based on the finite-gain

valley current mode with CCRCOT (Constant Current

Ripple Constant On Time) topology. The output voltage,

V_COREor V_GFX, will decrease with increasing output load

current. The control loop consists of PWM modulator with

power stage, current sense amplifier and error amplifier

as shown in Figure 8.

V_OUT= V_REFx− I_LOADx R_DROOP

(1)

Then solving the switching condition V_COMPx= V_CSxin

Figure 8 yields the desired error amplifier gain as

A ×R

R2

R1

I

SENSE

(2)

A

=

V

R

V

IN

DROOP

where A_Iis the internal current sense amplifier gain and

R_SENSEis the current sense resistance. If no external sense

resistor is present, the DCR of the inductor will act as

R_SENSE. R_DROOPis the resistive slope value of the converter

output and is the desired static output impedance.

V

OUT

/V

High Side

MOSFET

UGATEx

PHASEx

(V

)

CORE GFX

GFX/CORE VR

CCRCOT

PWM Generator

Driver

Logic

Control

L

R

C

LGATEx

Low Side

MOSFET

R

X

C

X

C

CMP

V

OUT

ISENxP

ISENxN

V

CSx

+

Ai

A

> A

V1

V2

-

C

Byp

C2

R2

C1

R1

CORE/GFX VR

COMPx

FBx

V

A

CC_SENSE

V2

V1

-

EA

CORE/GFX VR

RGNDx

+

0

V

SS_SENSE

Load Current

VREFx

Figure 9. ErrorAmplifierGain (A_V) Influence on V_OUT

Accuracy

Figure 8. Simplified Schematic for Droop and Remote

Sense in CCM

©

is a registered trademark of Richtek Technology Corporation.

www.richtek.com

32

DS8167A-00 January 2012

RT8167A

Since the DCR of inductor is temperature dependent, it

affects the output accuracy in high temperature conditions.

Temperature compensation is recommended for the

lossless inductor DCR current sense method. Figure 10

shows a simple but effective way of compensating the

temperature variations of the sense resistor using anNTC

thermistor placed in the feedback path.

R2 = A_{V, 25}x (R1b + R1a // R_{NTC, 25}

)

(7)

whereA_{V, 25°C}is the error amplifier gain at room temperature

obtained from (2). R1b can be obtained by substituting

(7) to (3),

R1b =

R_{SENSE, HOT}

×(R1a //R_{NTC, HOT}) − (R1a//R_{NTC, COLD}

)

R_{SENSE, COLD}

C2

C1

R_{SENSE, HOT}

⎛

⎜

⎝

⎞

⎟

⎠

1−

R_{SENSE, COLD}

(8)

R2

R1a

NTC

R1b

COMPx

V

CC_SENSE

FBx

-

Loop Compensation

EA

RGNDx

V

+

SS_SENSE

Optimized compensation of the CORE VR allows for best

possible load step response of the regulator's output. A

type-I compensator with one pole and one zero is adequate

for a proper compensation. Figure 10 shows the

compensation circuit. It was previously mentioned that to

determine the resistive feedback components of error

amplifier gain, C1 and C2 must be calculated for the

compensation. The target is to achieve constant resistive

output impedance over the widest possible frequency

range.

VREFx

Figure 10. Loop Setting with Temperature Compensation

Usually, R1a is set to equal R_NTC(25°C), while R1b is

selected to linearize theNTC's temperature characteristic.

For a given NTC, the design would be to obtain R1b and

R2 and then C1 and C2. According to (2), to compensate

the temperature variations of the sense resistor, the error

amplifier gain (A_V) should have the same temperature

coefficient with R_SENSE. Hence

The pole frequency of the compensator must be set to

compensate the output capacitor ESR zero :

A

R

SENSE, HOT

V, HOT

(3)

=

A

R

SENSE, COLD

V, COLD

1

(9)

f_P

=

From (2), we can haveAv at any temperature (T) as

R2

2× π× C×R_C

A

=

(4)

where C is the capacitance of the output capacitor and R_C

is the ESR of the output capacitor. C2 can be calculated

as follows :

V, T

R1a / /R

+ R1b

NTC, T

The standard formula for the resistance ofNTC thermistor

as a function of temperature is given by :

C×R

R2

C

(10)

C2 =

⎡

1

298

⎤

β

−

(

) (

)

{

}

⎢

⎣

⎥

⎦

T+273

(5)

R_{NTC, T}= R_{NTC, 25}

e

The zero of compensator has to be placed at half of the

switching frequency to filter the switching-related noise.

where R_{NTC, 25}is the thermistor's nominal resistance at

room temperature, β (beta) is the thermistor's material

constant in Kelvins, and T is the thermistor's actual

temperature in Celsius.

Such that,

1

C1 =

(11)

R1b + R1a // R

× π× f

SW

(

)

NTC, 25°C

TON Setting

TheDCR value at different temperatures can be calculated

using the equation below :

High frequency operation optimizes the application by

trading off efficiency due to higher switching losses with

smaller component size. This may be acceptable in ultra-

portable devices where the load currents are lower and

the controller is powered from a lower voltage supply. Low

frequency operation offers the best overall efficiency at

DCR_T= DCR₂₅x [1+0.00393 x (T-25)]

(6)

where 0.00393 is the temperature coefficient of copper.

For a givenNTC thermistor, solving (4) at room temperature

(25°C) yields

©

is a registered trademark of Richtek Technology Corporation.

DS8167A-00 January 2012

www.richtek.com

33

RT8167A

the expense of component size and board space. Figure

11 shows the on-time setting circuit. Connect a resistor

(R_TONSETx) between V_INand TONSETx to set the on-time

R

R1

C1

TONSETx

VREFx

GFX/CORE

VR CCRCOT

PWM

V

IN

Generator

of UGATEx :

-12

28×10 ×R

TONSETx

(12)

On-Time

t

(V

REFx

< 1.2V) =

ONx

V

IN

− V

REFx

Figure 11. On-Time Setting with RC Filter

where t_ONxis the UGATEx turn on period, VINis the input

voltage of converter, and V_REFxis the internal reference

voltage.

Differential Remote Sense Setting

The CORE/GFX VR includes differential, remote-sense

inputs to eliminate the effects of voltage drops along the

PC board traces, CPU internal power routes and socket

contacts. The CPU contains on-die sense pins CORE/

GFX V_{CC_SENSE}and V_{SS_SENSE}. Connect RGNDx to CORE/

GFX V_{SS_SENSE}. Connect FBx to CORE/GFX V_{CC_SENSE}

with a resistor to build the negative input path of the error

amplifier. The precision voltage reference V_REFxis referred

to RGND for accurate remote sensing.

When V_REFxis larger than 1.2V, the equivalent switching

frequency may be over the maximum design range, making

it unacceptable. Therefore, the VR implements a pseudo-

constant-frequency technology to avoid this disadvantage

of CCRCOT topology. When V_REFxis larger than 1.2V,

the on-time equation will be modified to :

t_ONx(V_REFx≥ 1.2V)

23.33×10^-12×R_TONSETx× V_REFx

(13)

=

V_IN− V_REFx

Current Sense Setting

On-time translates roughly to switching frequencies. The

on-times guaranteed in the Electrical Characteristics are

influenced by switching delays in external high side

MOSFET.Also, the dead-time effect increases the effective

on-time, reducing the switching frequency. It occurs only

in CCM during dynamic output voltage transitions when

the inductor current reverses at light or negative load

currents. With reversed inductor current, PHASEx goes

high earlier than normal, extending the on-time by a period

equal to the high side MOSFET rising dead time.

The current sense topology of the CORE/GFX VR is

continuous inductor current sensing. Therefore, the

controller can be less noise sensitive. Low offset amplifiers

are used for loop control and over current detection. The

internal current sense amplifier gain (A_I) is fixed to be 10.

The ISENxP and ISENxNdenote the positive and negative

input of the current sense amplifier.

Users can either use a current sense resistor or the

inductor'sDCR for current sensing. Using inductor'sDCR

allows higher efficiency as shown in Figure 12. To let

L

DCR

For better efficiency of the given load range, the maximum

(15)

= R × C

X

switching frequency is suggested to be :

1

f_S(MAX)(kHz) =

×

then the transient performance will be optimum. For

example, choose L = 0.36μH with 1mΩ DCR and

C_X= 100nF, to yields for R_X:

t_ON− t_HS−Delay

⎡

⎤

V_REFx(MAX)+I_LOAD(MAX)× R_{ON_LS−FET}+ DCR − R_DROOP

⎣

⎦

⎡ ⎤

+I_LOAD(MAX)× R_{ON_LS−FET}− R_{ON_HS−FET}

V

IN(MAX)

⎣

⎦

0.36μH

1m Ω×10 0nF

R

=

= 3.6kΩ

X

(16)

(14)

where f_S(MAX)is the maximum switching frequency, t_HS-

_Delayis the turn on delay of high side MOSFET, V_REFx(MAX)

is the maximum application DAC voltage of application,

V_IN(MAX)is the maximum application input voltage,

I_LOAD(MAX)is the maximum load of application, R_{ON_LS-FET}

is the low side MOSFET R_DS(ON), R_{ON_HS-FET}is the high

side MOSFET R_DS(ON), DCR_Lis the inductor DCR, and

R_DROOPis the load line setting.

V

OUT

(V

/V

)

CORE GFX

L

DCR

PHASEx

C

X

R

X

ISENxP

ISENxN

+

V

CSx

A

I

-

C

Byp

Figure 12. Lossless Inductor Sensing

©

is a registered trademark of Richtek Technology Corporation.

www.richtek.com

34

DS8167A-00 January 2012

RT8167A

Considering the inductance tolerance, the resistor R_Xhas

to be tuned on board by examining the transient voltage.

If the output voltage transient has an initial dip below the

minimum load line requirement with a slow recovery, R_X

is too small. Vice versa, if the resistance is too large the

output voltage transient will only have a small initial dip

and the recovery will be too fast, causing a ring-back.

After receiving SetPS command, the CORE/GFX VR will

immediately change to the new operation state. When

VR receives SetPS command of PS2 operation mode,

the VR operates as a DEM controller.

If VR receives dynamic VID change command (SetVID),

VR will automatically enter PS0 operation mode. After

output voltage reaches target voltage, VR will stay at PS0

state and ignore former SetPS command. Only by

re-sending SetPS command after SetVID command will

VR be forced into PS2 operation state again.

Using current-sense resistor in series with the inductor

can have better accuracy, but the efficiency is a trade-off.

Considering the equivalent inductance (L_ESL) of the current

sense resistor, a RC filter is recommended. The RC filter

calculation method is similar to the above-mentioned

inductorDCR sensing method.

Thermal Monitoring and Temperature Reporting

CORE/GFX VR provides thermal monitoring function via

sensing TSEN pin voltage. Through the voltage divider

resistors R1, R2, R3 and R_NTC, the voltage of TSEN will

be proportional to VR temperature. When VR temperature

rises, the TSENx voltage also rises. The ADC circuit of

VR monitors the voltage variation at TSENx pin from 1.47V

to 1.89V with 55mV resolution, and this voltage is decoded

into digital format and stored into the Temperature Zone

register.

No-Load Offset

The RT8167Aprovides a no-load offset function which has

four-level offsets of output voltage for the CORE/GFX VR.

The no-load offset function is implemented through the

OFSx pin. Avoltage divider circuit is recommended to be

applied to OFSx pins. The output offset voltage relation to

the OFSx pin voltage setting is shown in Figure 13.

Recommended voltage setting at OFS and OFSA pins

are also shown in Figure 13.

V

CC

VCC (5V)

R

1

R

NTC

Offset

Recommended

Offset Voltag

0.64 VCC

e =100mV

R

2

Voltage OFS/OFSA Pin Voltage

TSENx

100mV 0.8 x VCC≒4V or VCC

R

3

50mV

−50mV

−100mV

0mV

0.56 x VCC≒2.8V

0.4 x VCC≒2V

0.24 x VCC≒1.2V

GND

Offset Voltage

0.48 VCC

= 50mV

Offset Voltage

0.32 VCC

= -50mV

Figure 14. Thermal Monitoring Circuit

Offset Voltage

0.16 VCC

= -100mV

To meet Intel's VR12/IMVP7 specification, platform users

have to set the TSEN voltage to meet the temperature

variation of VR from 75% to 100% VR max temperature.

For example, if the VR max temperature is 100°C, platform

users have to set the TSEN voltage to be 1.4875V when

VR temperature reaches 75°C and 1.8725V when VR

temperature reaches 100°C. Detailed voltage setting

versus temperature variation is shown in Table 2.

Thermometer code is implemented in the Temperature

Zone register.

Offset Voltage = 0

GND

mV

Figure 13. OFS and OFSA Pins Voltage Setting

Operation Mode Transition

The RT8167Asupports operation mode transition function

in CORE/GFX VR for the SetPS command of Intel's VR12/

IMVP7 CPU. The default operation mode of the RT8167A's

CORE/GFX VR is PS0, which is CCM operation. The other

operation mode is PS2 (DEM operation).

©

is a registered trademark of Richtek Technology Corporation.

DS8167A-00 January 2012

www.richtek.com

35

RT8167A

Table 2. Temperature Zone Register

Current Monitoring and Current Reporting

Comparator Trip Points

SVID Temperatures Scaled to maximum =

Thermal 100%

Alert Voltage Represents Assert bit

Minimum Level

The CORE/GFX VR provides current monitoring function

via sensing the voltage difference of IMONFBx pin and

output voltage. Figure 15 shows the current monitoring

setting principle. The equivalent output current will be

sensed from IMONFBx pin and mirrored to IMONx pin.

The resistor connected to IMONx pin determines voltage

gain of the IMON output.

VRHOT

b7

100%

b6

b5

b4

b3

b2

b1

b0

97% 94% 91% 88% 85% 82% 75%

1.745 1.69 1.635 1.58 1.52 1.47

1.855V 1.8V

V

5V

V

Temperature_Zone

Register Content

1111_1111

TSEN Pin Voltage

Current Monitor

VREFx + 2 (V

0LL EN

- V

)

ISENxP

ISENxN

1.855 ≤ V

TSEN

+

-

V

CC_SENSE

R

1.800 ≤ V

1.745 ≤ V

1.690 ≤ V

1.635 ≤ V

1.580 ≤ V

1.525 ≤ V

1.470 ≤ V

V

≤ 1.835

0111_1111

TSEN

≤ 1.780

≤ 1.725

≤ 1.670

≤ 1.615

≤ 1.560

≤ 1.505

0011_1111

I

IMONFB

MIrror

VREFx

IMONFBx

IMONx

0001_1111

0000_1111

V

IMON

0000_0111

C1

R

IMON

0000_0011

0000_0001

0000_0000

< 1.470

TSEN

Figure 15. Current Monitor Setting Principle

The RT8167A supports two temperature reporting,

VRHOT(hardware reporting) and ALERT(software

reporting), to fulfill VR12/IMVP7 specification. VRHOT is

an open-drain structure which sends out active-low VRHOT

signals. When TSEN voltage rises above 1.855V (100%

of VR temperature), the VRHOT signal will be set to low.

When TSEN voltage drops below 1.8V (97% of VR

temperature), the VRHOT signal will be reset to high. When

TSEN voltage rises above 1.8V (97% of VR temperature),

The RT8167A will update the bit1 data from 0 to 1 in the

Status_1 register and assertALERT. When TSENvoltage

drops below 1.745V (94% of VR temperature), VR will

update the bit1 data from 1 to 0 in the Status_1 register

and assertALERT.

The voltage of IMONFBx is different when VR operates in

droop enable mode and droop disable mode :

Droop enable mode : V_IMONFBx= V_REFx

Droop disable mode :

(17)

V_IMONFBx= V_REFx+ 2 (V_ISENxP− V_ISENxN

)

(18)

The current monitor indicator V_IMONequation is shown as:

(I

− V_{CC_SENSE})×R_IMON

R_IMONFB

IMONFBx

(19)

V

IMON

=

where V_IMONFBxis the pin voltage of IMONFBx, V_{CC_SENSE}

is the output voltage of CORE/GFX VR, and R_IMONand

R_IMONFBare the current monitor current setting resistors.

The maximum voltage of current monitoring will be limited

at 3.3V. Platform designers have to design the R_IMONto

meet the maximum voltage of IMON at full load.

The temperature reporting function for theGFX VR can be

disabled by pulling TSENA pin to VCC in case the

temperature reporting function for theGFX VR is not used

or the GFX VR is disabled. When the GFX VR's

temperature reporting function is disabled, the RT8167A

will reject the SVID command of getting the

Temperature_Zone register content of the GFX VR.

However, note that the temperature reporting function for

the CORE VR is always active. CORE VR's temperature

reporting function can not be disabled by pulling TSEN

pin to VCC.

When VR operates in droop enable mode, find R_IMONand

R_IMONFBbased on :

V

R

IMON(MAX)

IMON

=

(20)

R

I

×R

IMONFB

(MAX) DROOP

where V_IMON(MAX)is the maximum voltage at full load,

R_DROOPis the load line setting of VR, and I_MAXis the full

load current of VR.

©

is a registered trademark of Richtek Technology Corporation.

www.richtek.com

36

DS8167A-00 January 2012

RT8167A

When VR operate in droop disable mode, R_IMONand

R_IMONFBcan be obtained according to equation below :

The current limit is triggered when inductor current

exceeds the current limit threshold I_LIMIT, defined by

V_OCSET. The driver will be forced to turn off UGATE until

the over current condition is cleared. If the over current

condition remains valid for 15 PWM cycles, VR will trigger

OCP latch. Latched OCP forces both UGATE and LGATE

to go low. When OCP is triggered in one of VRs, the

other VR will enter into soft shutdown sequence. The OCP

latch mechanism will be masked when VRx_READY =

low, which means that only the current limit will be active

when V_OUTis ramping up to initial voltage (or V_REFx).

V

R

IMON(MAX)

IMON

=

(21)

R

I

×R

× 2

SENSE

IMONFB

(MAX)

where V_IMON(MAX)is the maximum voltage at full load,

R_SENSEis the equivalent resistance of current sense circuit,

and I_MAXis the full load current of VR.

TheADC circuit of the CORE/GFX VR monitors the voltage

variation at the IMONpin from 0V to 3.3V, and this voltage

is decoded into digital format and stored into the

Output_Current register. The ADC divides 3.3V into 255

levels, so LSB = 3.3V/255 = 12.941mV. Platform

designers should design V_IMONxto be 3.3V at ICCMAX.

If inductorDCR is used as the current sense component,

then temperature compensation is recommended for

protection under all conditions. Figure 17 shows a typical

OCP setting with temperature compensation.

For example, when load current = 0.5 x ICCMAX, V_IMON

1.65V and Output_Current register = 7Fh.

=

V

CC

The IMONpin is the output of internal operational amplifier

and sends out IMON signal. When IMON voltage rises

above 3.3V (100% of VR output current), the VR will update

the bit2 data from 0 to 1 in the Status_1 register. The 1 in

bit2 of Status_1 register will be cleared to 0 only after the

master (usually Intel's VR12/IMVP7 CPU) executes

GetReg command to Status_1 register.

R

OC1a

NTC

OC1b

R

OCSETx

R

OC2

Figure 17. OCP Setting with Temperature Compensation

Over Current Protection

Usually, R_OC1ais selected to be equal to the thermistor's

nominal resistance at room temperature. Ideally, V_OCSET

is assumed to have the same temperature coefficient as

R_SENSE(InductorDCR) :

The CORE/GFX VR compares a programmable current

limit set point to the voltage from the current sense amplifier

output for Over Current Protection (OCP). The voltage

applied to OCSETx pin defines the desired peak current

V

R

SENSE, HOT

limit threshold I_LIMIT

:

OCSET, HOT

=

(24)

V

R

SENSE, COLD

OCSET, COLD

V_OCSET= 48 x I_LIMITx R_SENSE

(22)

According to the basic circuit calculation, V_OCSETcan be

obtained at any temperature :

Connect a resistive voltage divider from VCC toGND, with

the joint of the resistive divider connected to OCSET pin

as shown in Figure 16. For a given R_OC2, then

R_OC2

V_{OCSET, T}= V_CC

×

R_OC1a/ /R_{NTC, T}+ R_OC1b+ R_OC2

(25)

Re-write (24) from (25), to get V_OCSETat room temperature

V

⎛

⎞

CC

(23)

R

= R

×

OC2

−1

⎟

OC1

⎜

⎝

V

OCSET

⎠

V

CC

R

//R

+ R

R

SENSE, HOT

R

OC1

OC1a

NTC, COLD

OC1b

OC2

=

OCSETx

R

//R

R

SENSE, COLD

OC1a

NTC, HOT

OC1b

OC2

R

OC2

(26)

V_{OCSET, 25}

V_CC

=

R_OC2

Figure 16. OCP Setting without Temperature

Compensation

×

(27)

R_OC1a/ /R_{NTC, 25}+ R_OC1b+ R_OC2

©

is a registered trademark of Richtek Technology Corporation.

DS8167A-00 January 2012

www.richtek.com

37

RT8167A

Solving (26) and (27) yields R_OC1band R_OC2

Under Voltage Lock Out (UVLO)

R_OC2

=

During normal operation, if the voltage at the VCC pin

drops below UVLO falling edge threshold, both VR will

trigger UVLO. The UVLO protection forces all high side

MOSFETs and low side MOSFETs off to turn off.

α ×R_{EQU, HOT}−R_{EQU, COLD}+ (1− α)×R_{EQU, 25}

V_CC

V_{OCSET, 25}

×(1− α)

(28)

(29)

R_OC1b

=

(α −1)×R2 + α ×R_{EQU, HOT}− R_{EQU, COLD}

(1− α)

Inductor Selection

The switching frequency and ripple current determine the

inductor value as follows :

where

α =

V

_IN− V_OUT

R_{SENSE, HOT}

DCR₂₅×[1+ 0.00393×(T_HOT− 25)]

L_MIN

=

× t_ON

(32)

=

I_Ripple(MAX)

R_{SENSE, COLD}DCR₂₅×[1+ 0.00393×(T_COLD− 25)]

(30)

(31)

where t_ONis the UGATE turn on period.

R_{EQU, T}= R_OC1a// R_{NTC, T}

Higher inductance induces less ripple current and hence

higher efficiency. However, the tradeoff is a slower transient

response of the power stage to load transients. This might

increase the need for more output capacitors, thus driving

up the cost. Find a low-loss inductor having the lowest

possibleDC resistance that fits in the allotted dimensions.

The core must be large enough not to be saturated at the

peak inductor current.

Over Voltage Protection (OVP)

The over voltage protection circuit of CORE/GFX VR

monitors the output voltage via the ISENxN pin. The

supported maximum operating VID of VR (V_(MAX)) is stored

in the V_OUT(MAX)register. Once V_ISENxNexceeds “V_(MAX)

+

200mV”, OVP is triggered and latched. VR will try to turn

on low side MOSFETs and turn off high side MOSFETs to

protect CPU. When OVP is triggered by the one of the

VRs, the other VR will enter soft shutdown sequence. A

10μs delay is used in OVP detection circuit to prevent

false trigger.

Output Capacitor Selection

Output capacitors are used to obtain high bandwidth for

the output voltage beyond the bandwidth of the converter

itself. Usually, the CPU manufacturer recommends a

capacitor configuration. Two different kinds of output

capacitors can be found, bulk capacitors closely located

to the inductors and ceramic output capacitors in close

proximity to the load. Latter ones are for mid-frequency

decoupling with very small ESR and ESL values while the

bulk capacitors have to provide enough stored energy to

overcome the low-frequency bandwidth gap between the

regulator and the CPU.

Negative Voltage Protection (NVP)

During OVP latch state, both CORE/GFX VRs also monitor

ISENxN pin for negative voltage protection. Since the OVP

latch will continuously turn on low side MOSFET of VR,

VR may suffer negative output voltage. Therefore, when

the voltage of ISENxN drops below −0.05V after triggering

OVP, VR will turn off low side MOSFETs while high side

MOSFETs remain off. TheNVP function will be active only

after OVP is triggered.

Layout Considerations

Careful PC board layout is critical to achieving low

switching losses and clean, stable operation. The

switching power stage requires particular attention. If

possible, mount all of the power components on the top

side of the board with their ground terminals flushed

against one another. Follow these guidelines for optimum

PC board layout :

Under Voltage Protection (UVP)

Both CORE/GFX VR implement Under Voltage Protection

(UVP). If ISENxNis less than V_REFxby 300mV + V_OFFSET

,

VR will trigger UVP latch. The UVP latch will turn off both

high side and low side MOSFETs. When UVP is triggered

by one of the VRs, the other VR will enter into soft

shutdown sequence. The UVP mechanism is masked

when VRx_READY = low.

©

is a registered trademark of Richtek Technology Corporation.

www.richtek.com

38

DS8167A-00 January 2012

RT8167A

` Keep the high current paths short, especially at the

ground terminals.

` Keep the power traces and load connections short. This

is essential for high efficiency.

` When trade-offs in trace lengths must be made, it's

preferable to allow the inductor charging path to be made

longer than the discharging path.

` Place the current sense component close to the

controller. ISENxP and ISENxNconnections for current

limit and voltage positioning must be made using Kelvin

sense connections to guarantee the current sense

accuracy. The PCB trace from the sense nodes should

be parallel to the controller.

` Route high-speed switching nodes away from sensitive

analog areas (COMPx, FBx, ISENxP, ISENxN, etc...)

` Special attention should be paid in placing the DCR

current sensing components. TheDCR current sensing

capacitor and resistors must be placed close to the

controller.

` The capacitor connected to the ISEN1N/ISENANfor noise

decoupling is optional and it should also be placed close

to the ISEN1N/ISENAN pin.

` The NTC thermistor should be placed physically close

to the inductor for better DCR thermal compensation.

©

is a registered trademark of Richtek Technology Corporation.

DS8167A-00 January 2012

www.richtek.com

39

RT8167A

Outline Dimension

2

1

2

1

DETAILA

Pin #1 ID and Tie Bar Mark Options

Note : The configuration of the Pin #1 identifier is optional,

but must be located within the zone indicated.

Dimensions In Millimeters

Dimensions In Inches

Symbol

Min

Max

Min

Max

A

A1

A3

b

0.700

0.000

0.175

0.150

5.950

4.250

5.950

4.250

0.800

0.050

0.250

6.050

4.350

6.050

4.350

0.028

0.000

0.007

0.006

0.234

0.167

0.234

0.167

0.031

0.002

0.010

0.238

0.171

0.238

0.171

D

D2

E

E2

e

0.400

0.016

L

0.350

0.450

0.014

0.018

W-Type 48L QFN 6x6 Package

Richtek Technology Corporation

5F, No. 20, Taiyuen Street, Chupei City

Hsinchu, Taiwan, R.O.C.

Tel: (8863)5526789

Richtek products are sold by description only. Richtek reserves the right to change the circuitry and/or specifications without notice at any time. Customers should

obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. Richtek cannot

assume responsibility for use of any circuitry other than circuitry entirely embodied in a Richtek product. Information furnished by Richtek is believed to be

accurate and reliable. However, no responsibility is assumed by Richtek or its subsidiaries for its use; nor for any infringements of patents or other rights of third

parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Richtek or its subsidiaries.

www.richtek.com

40

DS8167A-00 January 2012


型号：	RT8167A
厂家：	RICHTEK TECHNOLOGY CORPORATION
描述：	Dual Single-Phase PWM Controller for CPU Core/GFX Power Supply 双单相PWM控制器，用于CPU核心/ GFX电源电压核心转换控制器
文件：	总40页 (文件大小：659K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

RT8167A [RICHTEK]

相关型号：

RT8167AGQW

RT8167A_14

RT8167B

RT8167BGQW

RT8170A

RT8171B

RT8171C

RT8172A

RT8175A

RT8179B

RT8199B

RT82