RT9026 [RICHTEK]
暂无描述;
| 型号： | RT9026 |
| 厂家： | 
RICHTEK TECHNOLOGY CORPORATION |
| 描述： | 暂无描述 双倍数据速率 |
| 文件： | 总14页 (文件大小：259K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
RT9026
DDR Termination Regulator
General Description
Features
l Support DDRI, DDRII, DDRIII, Low-Power DDRIII and
DDRIV Requirement
RT9026 is a 3A sink/source tracking termination regulator.
It is specifically designed for low-cost and low-external
component count systems. The RT9026 possesses a high
speed operating amplifier that provides fast load transient
response and only requires 20mF of ceramic output
capacitance. The RT9026 supports remote sensing
functions and all features required to power theDDRI/II/III
and low-power DDRIII/DDRIV VTT bus termination
according to the JEDEC specification. In addition, the
RT9026 includes integrated sleep-state controls placing
VTT in High-Z in S3 (suspend to RAM) and soft-off forVTT
and VTTREF in S5 (shutdown). The RT9026 is available
in the thermal efficient package SOP-8 (Exposed Pad),
MSOP-10 (Exposed Pad) and WDFN-10L 3x3.
} Source/Sink 3A for DDRI and DDRII
} Source/Sink 2A for DDRIII
} Source/Sink 1.5A for Low-Power DDRIII
} Source/Sink 1.2A for Low-Power DDRIV
l Input Voltage Range : 3.15V to 5.5V
l VLDOIN Voltage Range : 1.2V to 3.3V
l Requires Only 20mF Ceramic Output Capacitance
l Supports High-Z in S3 and Soft-Off in S5
l IntegratedDivider Tracks 1/2 VDDQSNS for Both VTT
and VTTREF
l Remote Sensing (VTTSNS)
l ±20mV Accuracy for VTT and VTTREF
l 10mA Buffered Reference (Sourcing/Sinking)
(VTTREF)
Applications
l Built-In Soft-Start
l DDRI/II/III and Low-Power DDRIII/DDRIV Memory
l Over Current Protection
Termination
l Thermal Shutdown Protection
l SOP-8 (Exposed Pad), MSOP-10 (Exposed Pad) and
10-Lead WDFN Package
l SSTL-2, SSTL-18
l HSTLTermination
l RoHS Compliant and Halogen Free
Ordering Information
RT9026
Pin Configurations
Package Type
SP : SOP-8 (Exposed Pad-Option 1)
FP : MSOP-10 (Exposed Pad)
QW : WDFN-10L 3x3 (W-Type)
(TOP VIEW)
8
7
6
5
GND
S3
VTT
2
3
4
VLDOIN
VIN
GND
9
Lead Plating System
P : Pb Free
G : Green (Halogen Free and Pb Free)
VTTSNS
VTTREF
VDDQSNS
SOP-8 (Exposed Pad)
Note :
Richtek products are :
VDDQSNS
VLDOIN
VTT
PGND
VTTSNS
10
9
VIN
S5
GND
S3
VTTREF
2
3
4
5
} RoHS compliant and compatible with the current require-
ments of IPC/JEDEC J-STD-020.
} Suitable for use in SnPb or Pb-free soldering processes.
8
GND
7
11
6
MSOP-10 (Exposed Pad)
1
10 VIN
VDDQSNS
VLDOIN
VTT
9
2
3
4
5
S5
GND
11
8
7
GND
S3
PGND
9 VTTREF
VTTSNS
WDFN-10L 3x3
DS9026-07 September 2011
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1
RT9026
Marking Information
RT9026PSP
RT9026PFP
RT9026PSP : Product Code
A0- : Product Code
YMDNN : Date Code
RT9026
PSPYMDNN
YMDNN : Date Code
A0-YM
DNN
RT9026GSP
RT9026GFP
RT9026GSP : Product Code
YMDNN : Date Code
A0= : Product Code
YMDNN : Date Code
RT9026
GSPYMDNN
A0=YM
DNN
RT9026PQW
E6- : Product Code
YMDNN : Date Code
E6-YM
DNN
RT9026GQW
E6= : Product Code
YMDNN : Date Code
E6=YM
DNN
Typical Application Circuit
RT9026
RT9026
3.3V or 5V
7
VLDOIN
10
1
2
VLDOIN
VLDOIN
VDDQSNS
VLDOIN
VTT
VIN
4
VTTREF
VDDQSNS
VTTSNS
VTTREF
0.1µF
C1
C1
C2
5
6
C3
10µF
10µF
1µF
8, 11 (Exposed Pad)
3
8
GND
3
5
VIN
3.3V or 5V
VTT
C4
6
9
VTT
VTT
S3
VTTREF
C4
C2
1µF
VTTREF
VTTSNS
2
10µF x 2
C3
S5
10µF x 2
S3
S5
S3
GND
1, 9 (Exposed Pad)
0.1µF
4
7
PGND
S3
Figure 1. For SOP-8 (Exposed Pad) Package
Figure 2. For MSOP-10 (Exposed Pad) / WDFN-10L 3x3
Package
Functional Pin Description
Pin No.
Pin Name
Pin Function
RT9026 FP
□
RT9026 SP
□
RT9026□QW
Ground. The exposed pad must be soldered to a large PCB and
connected to GND for maximum power dissipation.
1,
8,
GND
9 (Exposed Pad) 11 (Exposed Pad)
Active Low Suspend to RAM Mode Control Pin, VTT is turned
off and left High-Z, VTTREF is active.
2
3
7
5
S3
VTT Voltage Sense Input Pin. Connect to plus terminal of the
output capacitor.
VTTSNS
To be Continued
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DS9026-07 September 2011
RT9026
Pin No.
Pin Name
Pin Function
reference output, equal to
RT9026 FP
RT9026□QW
□
RT9026 SP
□
Buffered output that is
VDDQSNS/2.
a
4
6
VTTREF
5
6
1
VDDQSNS VLDOIN Sense Input Pin.
10
VIN
Analog Input Pin (to control loop).
Power supply of the VTT and VTTREF output stage (to power
MOS).
7
2
VLDOIN
Output voltage for connection to termination resistors, equal to
VDDQSNS/2.
8
--
--
3
4
9
VTT
PGND
S5
Power Ground of the VTT Output.
Active low shutdown control pin, both VTT and VTTREF are
turned off and discharged to ground.
Function Block Diagram
VDDQSNS
VLDOIN
Half DDQ
+
-
+
VTTREF
-
GND
VIN
ENREF
+
+
-
VIN OK
VTT
2.32V/
2.2V
-
ENVTT
ENVTT
S3
S5
5V(10%)
ENREF
PGND
+
-
PGOOD
+
-
-5V(10%)
VTTSNS
Table 1. S3 and S5 Control Table
State
S3
S5
VTT
VREF
1.25V/0.9V/0.75V 1.25V/0.9V/0.75V
Normal
High
High
/0.675V/0.6V
12mV/6mV
(High-Z)
/0.675V/0.6V
1.25V/0.9V/0.75V
/0.675V/0.6V
Standby
Low
High
Shutdown
Shutdown
Low
Low
Low
0V (Discharge)
0V (Discharge)
0V (Discharge)
0V (Discharge)
High
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RT9026
Absolute Maximum Ratings (Note 1)
l Supply Input Voltage, VIN ---------------------------------------------------------------------------------------------- 6V
l Supply Input Voltage, VLDOIN, VDDQSNS ------------------------------------------------------------------------ 3.6V
l Power Dissipation, PD @ TA = 25°C
SOP-8 (Exposed Pad) -------------------------------------------------------------------------------------------------- 1.333W
MSOP-10 (Exposed Pad) ---------------------------------------------------------------------------------------------- 1.163W
WDFN-10L 3x3 ----------------------------------------------------------------------------------------------------------- 1.429W
l Package Thermal Resistance (Note 2)
SOP-8 (Exposed Pad), qJA -------------------------------------------------------------------------------------------- 75°C/W
SOP-8 (Exposed Pad), qJC -------------------------------------------------------------------------------------------- 28°C/W
MSOP-10 (Exposed Pad), qJA ---------------------------------------------------------------------------------------- 86°C/W
MSOP-10 (Exposed Pad), qJC ---------------------------------------------------------------------------------------- 30°C/W
WDFN-10L 3x3, qJA ------------------------------------------------------------------------------------------------------ 70°C/W
WDFN-10L 3x3, qJC ----------------------------------------------------------------------------------------------------- 8.2°C/W
l Lead Temperature (Soldering, 10 sec.)------------------------------------------------------------------------------ 260°C
l JunctionTemperature --------------------------------------------------------------------------------------------------- 150°C
l StorageTemperature Range ------------------------------------------------------------------------------------------- - 65°C to 150°C
l ESD Susceptibility (Note 3)
HBM (Human Body Mode) --------------------------------------------------------------------------------------------- 2kV
MM (Machine Mode) ---------------------------------------------------------------------------------------------------- 200V
Recommended Operating Conditions (Note 4)
l Supply Input Voltage, VIN ---------------------------------------------------------------------------------------------- 3.15V to 5.5V
l Supply Input Voltage, VLDOIN, VDDQSNS ------------------------------------------------------------------------ 1.2V to 3.3V
l Junction Temperature Range ------------------------------------------------------------------------------------------ - 40°C to 125°C
l AmbientTemperature Range ------------------------------------------------------------------------------------------ - 40°C to 85°C
Electrical Characteristics
(VIN = 5V, VLDOIN = VDDQSNS = 2.5V, C1=10mF, C2=1mF, C3=0.1mF, C4=10mFx2, TA = 25°C, S5 function only for RT9026PFP
and RT9026PQW, unless otherwise specified)
Parameter
Symbol
Test Conditions
Min
--
Typ
--
Max Unit
VIN (to control loop) Supply
Current
I
I
I
V
= 5V, No Load, S5 = S3 = 5V
2
300
1
mA
mA
mA
VIN
IN
VIN Standby Current
V
V
= 5V, No Load, S5 = 5V, S3 = 0V
= 5V, No Load, S5 = S3 = 0V
(Only for RT9026PFP and RT9026PQW)
--
--
VINSTB
IN
IN
VIN Shutdown Current
--
--
VINSHDN
VLDOIN (to power MOS)
Supply Current
I
I
V
= 5V, No Load, S5 = S3 = 5V
--
--
2
mA
VLDOIN
IN
VLDOIN Standby Current
V
IN
V
IN
V
IN
= 5V, No Load, S5 = 5V, S3 = 0V
= 5V, No Load, S5 = S3 = 0V
= 5V, S5 = S3 = 5V
--
--
--
--
--
--
--
--
--
10
1
mA
mA
mA
mA
VLDOINSTB
VLDOINSHDN
VDDQSNS
VLDOIN Shutdown Current I
VDDQSNS Input Current
VTTSNS Input Current
I
--
50
1
I
V
= 5V, S5 = S3 = 5V
--
VTTSNS
IN
VDDQSNS = VLDOIN = 2.5V
VDDQSNS = VLDOIN = 1.8V
VDDQSNS = VLDOIN = 1.5V
1.25
0.9
0.75
--
VTT Output Voltage
VTT
V
--
--
To be Continued
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DS9026-07 September 2011
RT9026
Parameter
Symbol
VTT
Test Conditions
VDDQSNS = VLDOIN = 1.35V
VDDQSNS = VLDOIN = 1.2V
Min
--
Typ
0.675
0.6
Max
--
Unit
VTT Output Voltage
V
--
--
VDDQSNS = VLDOIN =
2.5V/1.8V/1.5V/1.35V/1.2V,
- 20
- 40
- 40
- 40
--
--
--
--
20
40
40
40
∣I
∣= 0A
VTT
VDDQSNS = VLDOIN = 1.2V,
∣I ∣= 1.2A
VTTREF, VTT Output
Tolerance
VTT
V
mV
VTTTOL
VDDQSNS = VLDOIN =
2.5V/1.8V/1.5V/1.35V,
∣I
∣= 1.5A
VTT
VDDQSNS = VLDOIN = 2.5V/1.8V,
∣I ∣= 3A
VTT
VTT Source Current Limit
VTT Sink Current Limit
I
VTT = 0V
3
3
4
4
--
--
A
A
VTTOCLsr
I
VTT = VDDQSNS
VTTOCLsk
VDDQSNS = 0V, VTT = 1.25V,
S5 = S3 = 0V
VTT Discharge Current
VTTREF Output Voltage
I
10
--
17
--
--
mA
V
DSCHRG
1.25/0.9/
0.75/
0.675/0.6
æV
ç
ö
÷
ø
VDDQSNS
V
V
=
VTTREF
VTTREF
2
è
VLDOIN = VDDQSNS =
2.5V/1.8V/1.5V/1.35V/1.2V,
VDDQSNS/2, VTTREF
Output Voltage Tolerance
V
- 20
--
20
mV
mA
V
VTTREFTOL
I
< 10mA
VTTREF
VTTREF Source Current Limit I
V
= 0V
20
--
40
--
60
2.7
--
VTTREFOCL
VTTREF
Rising
UVLO Threshold Voltage
V
UVLO
Hysteresis
S5, S3 pin
S5, S3 pin
S5, S3 pin
--
0.2
--
Logic-High
Input Voltage
V
IH
1.6
--
--
V
Logic-Low
V
IL
--
0.4
Logic Input Leakage Current
I
--
--
--
--
1
--
--
mA
°C
°C
ILK
Thermal Shutdown Protection T
160
20
SD
Thermal Shutdown Hysteresis DT
SD
Note 1. Stresses listed as the above “Absolute Maximum Ratings” may cause permanent damage to the device. These are for
stress ratings. Functional operation of the device at these or any other conditions beyond those indicated in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended
periods may remain possibility to affect device reliability.
Note 2. qJA is measured in the natural convection at TA = 25°C on a high effective four-layers thermal conductivity test board of
JEDEC 51-7 thermal measurement standard. The case point of qJC is on the exposed pad for SOP-8 (Exposed Pad)
, MSOP-10 (Exposed Pad) and WDFN-10L 3x3 package.
Note 3. Devices are ESD sensitive. Handling precaution is recommended.
Note 4. The device is not guaranteed to function outside its operating conditions.
DS9026-07 September 2011
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RT9026
Typical Operating Characteristics
VDDQSNS = VLDOIN, C1 = 10μF, C2 = 1μF, C3 = 0.1μF, C4 = 10μF x 2 unless otherwise specified.
1.25VTT Output Voltage vs. Temperature
0.9VTT Output Voltage vs. Temperature
1.30
1.28
1.26
1.24
1.22
1.20
0.95
0.94
0.93
0.92
0.91
0.90
0.89
0.88
0.87
0.86
0.85
VIN = 3.3V
VIN = 5V
VIN = 3.3V
VIN = 5V
VLDOIN = 2.5V
VLDOIN = 1.8V
-50
-25
0
25
50
75
100
125
-50
-25
0
25
50
75
100
125
Temperature (°C)
Temperature (°C)
0.75VTT Output Voltage vs. Temperature
0.675VTT Output Voltage vs. Temperature
0.725
0.715
0.705
0.695
0.685
0.675
0.665
0.655
0.645
0.635
0.625
0.80
0.79
0.78
0.77
0.76
0.75
0.74
0.73
0.72
0.71
0.70
VIN = 3.3V
VIN = 5V
VIN = 3.3V
VIN = 5V
VLDOIN = 1.5V
VLDOIN = 1.35V
-50
-25
0
25
50
75
100
125
-50
-25
0
25
50
75
100
125
Temperature (°C)
Temperature (°C)
0.6VTT Output Voltage vs. Temperature
VIN Supply Current vs. Temperature
0.65
0.64
0.63
0.62
0.61
0.60
0.59
0.58
0.57
0.56
0.55
1000
950
900
850
800
750
700
650
600
VIN = 5V, VLDOIN = 2.5V
VLDOIN = 1.8V
VIN = 3.3V
VIN = 5V
VIN = 5V, VLDOIN = 1.5V
VLDOIN = 1.35V
VLDOIN = 1.2V
VIN = 3.3V, VLDOIN = 2.5V
VLDOIN
= 1.8V
VLDOIN = 1.5V
VLDOIN = 1.35V
VLDOIN = 1.2V
VLDOIN = 1.2V
-50
-25
0
25
50
75
100
125
-50
-25
0
25
50
75
100
125
Temperature (°C)
Temperature (°C)
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DS9026-07 September 2011
RT9026
VIN Standby Current vs. Temperature
1.25VTT @ 3A Transient Response
250
230
210
190
170
150
Source
VIN = 5V, VLDOIN = 2.5V
VIN = 5V, VLDOIN = 2.5V
VLDOIN = 1.8V
VLDOIN = 1.5V
VLDOIN = 1.35V
VLDOIN = 1.2V
VTT
(20mV/Div)
VIN = 3.3V, VLDOIN = 2.5V
VLDOIN = 1.8V
VLDOIN = 1.5V
VLDOIN = 1.35V
VLDOIN = 1.2V
IVTT
(2A/Div)
-50
-25
0
25
50
75
100
125
Time (500μs/Div)
Temperature (°C)
0.9VTT @ 3A Transient Response
0.75VTT @ 2A Transient Response
Source
Source
VIN = 5V, VLDOIN = 1.8V
VIN = 5V, VLDOIN = 1.5V
VTT
(20mV/Div)
VTT
(20mV/Div)
IVTT
IVTT
(2A/Div)
(1A/Div)
Time (500μs/Div)
Time (500μs/Div)
0.675VTT @ 1.5A Transient Response
0.6VTT @ 1.2A Transient Response
Source
Source
VIN = 5V, VLDOIN = 1.35V
VIN = 5V, VLDOIN = 1.2V
VTT
(20mV/Div)
VTT
(20mV/Div)
IVTT
(1A/Div)
IVTT
(1A/Div)
Time (400μs/Div)
Time (400μs/Div)
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RT9026
0.9VTT @ 3A Transient Response
1.25VTT @ 3A Transient Response
Sink
Sink
VIN = 5V, VLDOIN = 1.8V
VIN = 5V, VLDOIN = 2.5V
VTT
(20mV/Div)
VTT
(20mV/Div)
IVTT
(2A/Div)
IVTT
(2A/Div)
Time (500μs/Div)
Time (500μs/Div)
0.75VTT @ 2A Transient Response
0.675VTT @ 1.5A Transient Response
Sink
Sink
VIN = 5V, VLDOIN = 1.5V
VIN = 5V, VLDOIN = 1.35V
VTT
(20mV/Div)
VTT
(20mV/Div)
IVTT
(1A/Div)
IVTT
(1A/Div)
Time (500μs/Div)
Time (400μs/Div)
0.9VTTREF @ 10mA Transient Response
0.6VTTREF @ 1.2A Transient Response
Source
VIN = 5V, VLDOIN = 1.8V
Sink
VIN = 5V, VLDOIN = 1.2V
VTTREF
(10mV/Div)
VTT
(20mV/Div)
IVTT
(1A/Div)
IVTTREF
(10mA/Div)
Time (1ms/Div)
Time (400μs/Div)
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DS9026-07 September 2011
RT9026
0.9VTTREF @ 10mA Transient Response
Start Up
Sink
VIN = 5V, VLDOIN = 1.8V
S3
(5V/Div)
VTTREF
(10mV/Div)
S5
(5V/Div)
VTTREF
(1V/Div)
IVTTREF
(10mA/Div)
VTT
(1V/Div)
S3 = 0V, C3 = 0.1μF, S5 : Low to High
Time (2.5μs/Div)
Time (1ms/Div)
Start Up
Start Up
S3
(5V/Div)
S3
(5V/Div)
S5
(5V/Div)
S5
(5V/Div)
VTTREF
(1V/Div)
VTTREF
(1V/Div)
VTT
(1V/Div)
VTT
(1V/Div)
S3 = 0V, S5 = 5V, S3 : Low to High
S3 = 0V, C3 = 1μF, S5 : Low to High
Time (10μs/Div)
Time (10μs/Div)
Power Off
S3
S3
(5V/Div)
S5
S5
(5V/Div)
VTTREF
VTTREF
(1V/Div)
VTT
VTT
(1V/Div)
S3 = 0V, C3 = 0.1μF, S3 and S5 : High to Low
Time (1ms/Div)
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RT9026
Application Information
For stable operation, the total capacitance of the cerarnic
capcitor at the VTT output terminal must not be larger
than 30μF. The RT9026 is designed specifically to work
with low ESR ceramic output capacitor in space saving
and performance consideration. Larger output capacitance
can reduce the noise and improve load transient response,
stability and PSRR. The output capacitor should be located
near the VTT output terminal pin as close as possible.
RT9026 is a 3Asink/source tracking termination regulator.
It is specifically designed for low-cost and low-external
component count system such as notebook PC
applications. The RT9026 possesses a high speed
operating amplifier that provides fast load transient response
and only requires a 10μF ceramic input capacitor and two
10μF ceramic output capacitor.
VTTREF Regulator
Thermal Considerations
VTTREF is a reference output voltage with source/sink
current capability up to 10mA. To ensure stable operation
0.1μF ceramic capacitor between VTTREF and GND is
recommended.
For continuous operation, do not exceed absolute
maximum operation junction temperature. The maximum
power dissipation depends on the thermal resistance of
IC package, PCB layout, the rate of surroundings airflow
and temperature difference between junction to ambient.
The maximum power dissipation can be calculated by
following formula :
S3, S5 Logic Control
The S3 and S5 terminals should be connected to SLP_S3
and SLP_S5 signals respectively. Both VTTREF and VTT
are turned on at normal state (S3 = High, S5 = High). In
standby state (S3 = Low, S5 = High) VTTREF is kept
alive while VTT is turned off and left high impedance. Both
VTT and VTTREF outputs are turned off and discharged
to ground through internal MOSFETs during shutdown
state (S5 = low).
PD(MAX) = ( TJ(MAX) − TA ) / θJA
Where TJ(MAX) is the maximum operation junction
temperature, TA is the ambient temperature and the θJA is
the junction to ambient thermal resistance.
For recommended operating conditions specification of
the RT9026, the maximum junction temperature is 125°C.
The junction to ambient thermal resistance θJA is layout
dependent. The thermal resistance θJA for WDFN-10L 3x3
is 70°C/W, for SOP-8 (Exposed Pad) is 75°C/W and for
MSOP-10 (Exposed Pad) is 86°C/W on the standard
JEDEC 51-7 four layers thermal test board. The maximum
power dissipation at TA = 25°C can be calculated by
following formula :
Table 2. S3 and S5 Control
STATE
Normal
Standby
S3
H
S5
H
VTTREF
VTT
ON
ON
L
H
ON
OFF(high-Z)
OFF
OFF
Shutdown
L
L
(discharge) (discharge)
PD(MAX) = (125°C − 25°C) / (70°C/W) = 1.429W for
WDFN-10L 3x3 packages
Capacitor Selection
Good bypassing is recommended from VLDOIN to GND
to help improveAC performance. A10μF or greater input
capacitor located as close as possible to the IC is
recommended. The input capacitor must be located at a
distance of less than 0.5 inches from the VLDOIN pin of
the IC.
PD(MAX) = (125°C − 25°C) / (75°C/W) = 1.333W for
SOP-8 (Exposed Pad) packages
PD(MAX) = (125°C − 25°C) / (86°C/W) = 1.163W for
MSOP-10 (Exposed Pad) packages
The maximum power dissipation depends on operating
ambient temperature for fixed TJ(MAX) and thermal
resistance θJA. For RT9026 packages, the Figure 3 of
derating curves allows the designer to see the effect of
rising ambient temperature on the maximum power
allowed.
Adding a ceramic capacitor 1μF close to the VIN pin and
it should be kept away from any parasitic impedance from
the supply power.
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10
DS9026-07 September 2011
RT9026
1.5
1.4
1.3
1.2
1.1
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
Four-Layers PCB
WDFN-10L 3x3
SOP-8 (Exposed Pad)
MSOP-10 (Exposed Pad)
0
25
50
75
100
125
Ambient Temperature (°C)
Figure 3. Derating Curves for the RT9026 Packages
DS9026-07 September 2011
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11
RT9026
Outline Dimension
H
A
Y
M
EXPOSED THERMAL PAD
(Bottom of Package)
J
B
X
F
C
I
D
Dimensions In Millimeters Dimensions In Inches
Symbol
Min
Max
5.004
4.000
1.753
0.510
1.346
0.254
0.152
6.200
1.270
2.300
2.300
2.500
3.500
Min
Max
A
B
C
D
F
H
I
4.801
3.810
1.346
0.330
1.194
0.170
0.000
5.791
0.406
2.000
2.000
2.100
3.000
0.189
0.150
0.053
0.013
0.047
0.007
0.000
0.228
0.016
0.079
0.079
0.083
0.118
0.197
0.157
0.069
0.020
0.053
0.010
0.006
0.244
0.050
0.091
0.091
0.098
0.138
J
M
X
Y
X
Y
Option 1
Option 2
8-Lead SOP (Exposed Pad) Plastic Package
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12
DS9026-07 September 2011
RT9026
D
U
L
EXPOSED THERMAL PAD
(Bottom of Package)
E
V
E1
e
A2
A
A1
b
Dimensions In Millimeters
Dimensions In Inches
Symbol
Min
Max
Min
Max
A
A1
A2
b
0.810
0.000
0.750
0.170
2.900
1.100
0.100
0.950
0.270
3.100
0.032
0.000
0.030
0.007
0.114
0.043
0.004
0.037
0.011
0.122
D
e
0.500
0.020
E
4.800
2.900
0.400
1.300
1.500
5.000
3.100
0.800
1.700
1.900
0.189
0.114
0.016
0.051
0.059
0.197
0.122
0.031
0.067
0.075
E1
L
U
V
10-Lead MSOP (Exposed Pad) Plastic Package
DS9026-07 September 2011
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13
RT9026
D2
D
L
E
E2
SEE DETAIL A
1
2
1
2
1
e
b
A
DETAILA
Pin #1 ID and Tie Bar Mark Options
A3
A1
Note : The configuration of the Pin #1 identifier is optional,
but must be located within the zone indicated.
Dimensions In Millimeters
Dimensions In Inches
Symbol
Min
Max
Min
Max
A
A1
A3
b
0.700
0.000
0.175
0.180
2.950
2.300
2.950
1.500
0.800
0.050
0.250
0.300
3.050
2.650
3.050
1.750
0.028
0.000
0.007
0.007
0.116
0.091
0.116
0.059
0.031
0.002
0.010
0.012
0.120
0.104
0.120
0.069
D
D2
E
E2
e
0.500
0.020
L
0.350
0.450
0.014
0.018
W-Type 10L DFN 3x3 Package
Richtek Technology Corporation
Headquarter
Richtek Technology Corporation
Taipei Office (Marketing)
5F, No. 20, Taiyuen Street, Chupei City
Hsinchu, Taiwan, R.O.C.
5F, No. 95, Minchiuan Road, Hsintien City
Taipei County, Taiwan, R.O.C.
Tel: (8863)5526789 Fax: (8863)5526611
Tel: (8862)86672399 Fax: (8862)86672377
Email: marketing@richtek.com
Information that is provided by Richtek Technology Corporation is believed to be accurate and reliable. Richtek reserves the right to make any change in circuit
design, specification or other related things if necessary without notice at any time. No third party intellectual property infringement of the applications should be
guaranteed by users when integrating Richtek products into any application. No legal responsibility for any said applications is assumed by Richtek.
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14
DS9026-07 September 2011
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